A semiconductor chip according to an embodiment includes a body portion with a front surface and a rear surface, the body portion being oriented in such a way that the rear surface is above the front surface, first and second through electrodes penetrating the body portion with protrusions that protrude above the rear surface of the body portion, a wiring portion formed under the front surface of the body portion, a power pattern formed over the rear surface of the body portion and spaced apart from the protrusions, an interlayer insulating layer filling spaces between the power pattern and the protrusions, and first and second rear connection electrodes formed over the interlayer insulating layer and respectively connected to the first and second through electrodes, wherein the first rear connection electrode is simultaneously connected to the first through electrode and a part of the power pattern that is adjacent to the first through electrode.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 23/50 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements for integrated circuit devices
H01L 23/528 - Layout of the interconnection structure
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
2.
ERROR CORRECTION DECODER, STORAGE DEVICE INCLUDING ERROR CORRECTION DECODER, AND OPERATING METHOD THEREOF
A storage device may include a memory device and a memory controller. The memory device may store data. The memory controller may iterate error correction decoding on data read from the memory device, determine whether to continue iterating based on a result obtained by comparing a first threshold number with a number of Unsatisfied Check Nodes (UCNs) included in a syndrome of first decoded data, which is a result of a first set number of iterations of the error correction decoding on the read data, and determine whether to continue iterating based on a result obtained by comparing a second threshold number with a number of UCNs included in a syndrome of second decoded data, which is a result of a sum of the first set number and a second set number of iterations of the error correction decoding on the read data.
A semiconductor device includes a source structure, an insulating layer disposed within the source structure, the insulating layer including a first edge that extends in a first direction and a second edge that extends in a second direction, the second direction intersecting the first direction, a first contact structure disposed within the insulating layer, the first contact structure having a second width in the second direction and a first width in the first direction, the first width being greater than the second width, and a second contact structure disposed on the insulating layer and connected to the first contact structure, the second contact structure having a fourth width in the second direction and a third width in the first direction, the third width being greater than the fourth width.
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
4.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE
A semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device including a stacked body including conductive patterns and insulating patterns that are alternately stacked, a filling layer configured to pass through the stacked body, a first channel layer configured to pass through the stacked body and coupled to the filling layer, a second channel layer configured to pass through the stacked body and coupled to the filling layer, a first interposed layer configured to pass through the stacked body and disposed between the first channel layer and the filling layer, a second interposed layer configured to pass through the stacked body and disposed between the second channel layer and the filling layer, and a memory layer surrounding the filling layer, the first and second channel layers, and the first and second interposed layers.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
A semiconductor device includes a test control circuit configured to enter a test mode and configured to generate a test word line precharge signal, based on a test mode entry signal, an active pulse, a precharge pulse, a reset signal, and a test code; a mat including a plurality of word line drivers; and a word line control circuit configured to generate a word line driving signal, a plurality of voltage driving signals, and a plurality of voltage discharge signals for controlling operations of the plurality of word line drivers, based on the test word line precharge signal, a mat enable signal, and a plurality of internal addresses. The word line driving signal is a signal that is enabled after a start of an active operation and that is disabled after a set period from timing for a precharge operation.
A memory device may include a plurality of memory blocks and a peripheral circuit configured to check a shift in threshold voltages of target select transistors by simultaneously applying a reference voltage to target select lines that are coupled to the plurality of memory blocks.
A memory device comprising: a memory cell array, and a controller configured to connect, in a first interval equal to or longer than a bit line setup interval, each of first and second bit lines, which are connected to cells respectively having first and second program states, to a node of a first permission voltage, connect, in the first interval, a third bit line, which is connected to a cell having a program prohibition state, to a node of a prohibition voltage, maintain, in a second interval that is equal to or shorter than a program pulse application interval, the respective connections of the first bit line and the third bit line, and disconnect, in the second interval, the second bit line from the node of the first permission voltage to apply the second bit line with a second permission voltage.
Seoul National University R&DB Foundation (Republic of Korea)
Inventor
Kim, Minwook
Kim, Jinsoo
Son, Ikjoon
Lee, Euidong
Abstract
A data storage device comprises a disk array including a plurality of disks; and a redundant array of independent disks (RAID) controller configured to manage the disk array according to a RAID mode, wherein each of the plurality of disks includes: a nonvolatile memory device having a plurality of zones of which supports a sequential write operation; and a random write buffer associated to one of the plurality of zones, the random write buffer having a start address that is indicated by a write pointer, the write pointer indicating a location where a next write operation is to be performed.
In an embodiment of the disclosed technology, parity information for external data inputted to a storage device is generated, and, depending on whether a parity transmission function is activated, or the state of a buffer memory of an external device located outside the storage device, the parity information is stored and managed in the buffer memory of the external device or a nonvolatile memory of the storage device. Thus, it is possible to efficiently manage the parity information and improve performance of ensuring integrity of the external data.
In an embodiment of the disclosed technology, a storage device includes a circuit board, a memory disposed on the circuit board and including a plurality of memory cells configured to store data, and an internal processor coupled to be in communication with the memory and configured to perform an operation on the data stored in the memory upon receipt of a command from an external device, wherein the command is extracted based on an operational intensity of the operation to be performed in response to the command, in a process in which a compiler generates an instruction according to a program executed by an external processor that is disposed outside the memory and separate from the internal processor.
A data input/output device includes a control circuit configured to generate a plurality input control signals in synchronization with a write clock, to perform a domain crossing operation of converting a write clock into a read clock, and to generate a plurality of output control signals based on an output counting signal generated through the domain crossing operation, and a data input/output circuit configured to latch a plurality of pieces of internal data input in parallel in synchronization with the plurality of input control signals, and to serialize the latched plurality pieces of internal data to generate data in synchronization with the plurality of output control signals.
According to the present technology, a memory system includes a plurality of memory devices each including a plurality of memory blocks, and a memory controller configured to receive information for target performance from an outside and a return request of achievement information indicating whether the target performance is achievable and including group information on each size of one or more necessary groups for achieving the target performance, provide the achievement information to the outside in response to the return request, and allocate memory blocks to the necessary groups based on the achievement information.
Provided herein may be a semiconductor memory device. The semiconductor memory device may include first holes arranged in a first direction to be spaced apart from each other by a first distance, a first drain select line coupled to first memory cell strings among first and second memory cell strings separated from each of the first holes, and a second drain select line coupled to the second memory cell strings. Identical data may be stored in the first and second memory cells coupled to a selected word line, among memory cells included in each of the first memory cell strings and memory cells included in each of the second memory cell strings.
Provided is an operation method of a memory controller which includes obtaining first read data from a second external device based on a first read command received from a first external device and performing error correction and decoding on the first read data to determine whether reading is successful or unsuccessful, performing a hard decoding-based read recovery operation and a soft decoding-based read recovery operation when a read failure occurs as a result of the first read operation, determining whether there is a second read command queued when the hard decoding-based read recovery has failed, temporarily stopping the read recovery operation for the first read data when there is the second read command queued and obtaining second read data by reading data from the second external device based on the second read command and performing error correction and decoding on the second read data.
G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
G06F 11/14 - Error detection or correction of the data by redundancy in operation, e.g. by using different operation sequences leading to the same result
G11C 16/08 - Address circuits; Decoders; Word-line control circuits
G11C 16/26 - Sensing or reading circuits; Data output circuits
15.
SEMICONDUCTOR MEMORY DEVICE FOR PERFORMING PROGRAM OPERATION
Provided herein may be a semiconductor memory device. The semiconductor memory device may include a memory cell array including a plurality of memory cells, a plurality of page buffers respectively coupled to the plurality of memory cells through bit lines, and a control logic configured to control a program operation of each of the plurality of page buffers. Each of the plurality of page buffers may include a first latch circuit configured to store first data indicating a main verification result obtained using a main verify voltage, a second latch circuit configured to store second data indicating a first sub-verification result obtained using a first sub-verify voltage lower than the main verify voltage, and a third latch circuit configured to store third data indicating a second sub-verification result obtained using a second sub-verify voltage lower than the first sub-verify voltage.
A memory device may include: a plurality of memory cells; a data manager for receiving data from the plurality of memory cells, and generating sub-data groups having a predetermined size, based on the received data; and a data compressor for detecting first-value bits having a first logic value among the bits in the received data, determining a number of target bits corresponding to each of the sub-data groups among the first-value bits to become 1 or less per sub-data group, and generating a plurality of compressed-data chunks including a logic value of the target bits and position information representing a position of the target bits in the data.
A semiconductor device may include a peripheral circuit portion, a memory cell array disposed over the peripheral circuit portion and including a vertical conductive line, a bonding pad structure between the peripheral circuit portion and the memory cell array, a dielectric pad layer configured to cover the top of the vertical conductive line of the memory cell array, and a higher-level pad that is coupled to the vertical conductive line through the dielectric pad layer.
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
H10B 12/00 - Dynamic random access memory [DRAM] devices
18.
SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
The semiconductor device include a horizontal layer spaced apart from a lower structure to extend along a direction parallel to the lower structure; a first conductive line extending along a direction perpendicular to the lower structure and coupled to one end of the horizontal layer; a data storage element coupled to the other end of the horizontal layer; and a second conductive line extending along a direction across the horizontal layer, wherein the second conductive line comprises: a high work function electrode; and a low work function electrode having a cup shape laterally oriented and disposed adjacent to the first conductive line and having a lower work function than the high work function electrode.
There are provided a semiconductor memory device and a manufacturing method of a semiconductor memory device. The semiconductor memory device includes a gate stack structure, a channel structure passing through the gate stack structure, and a memory layer between the channel structure and the gate stack structure. A channel layer or a channel pattern, which constitutes the channel structure, includes a structure having a corner or includes a filling type structure and a liner type structure.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
20.
MEMORY SYSTEM AND METHOD OF PERFORMING BACKGROUND OPERATION
A memory controller, a memory system and a method of operating a memory controller controlling a memory device are described. The memory controller may include a workload manager in communication with the memory device in which data is written and is read, the workload manager configured to acquire an amount of write data written to the memory device during a preset reference time, calculate a workload parameter indicating a ratio of the amount of write data to a reference write amount, and store the workload parameter for the preset reference time, and a performance manager configured to control, based on the workload parameter, a certain background operation performed by the memory device during a period corresponding to the workload parameter.
Embodiments of the present disclosure relate to a memory controller and operating method thereof. According to embodiments of the present disclosure, the memory controller may generate a fused linked list which includes information of a plurality of write commands received from a host and a plurality of synchronization commands requesting a synchronization operation, and control the synchronization operation for one or more of the plurality of write commands based on the fused linked list.
A memory system having a memory block and a memory controller in communication with the memory block. The memory controller is configured to: read and decode codewords from the memory block, determine a fail bit count (FBC), a strong correct (SC) rate indicating a percentage of failed bits correctable through log likelihood ratios (LLRs), and a number of spare bytes in the codewords decoded from the memory, predict a soft decoding error based on a fixed FBC, a fixed SC rate, and the number of spare bytes, and determine soft errors in the codewords read from the memory block based on the predicted soft decoding error.
A random number generator and method for generating random numbers. The random number generator has a) a noise source configured to generate M noise bits, and b) an entropy enhancement component (EEC) configured to receive an input sequence of the noise bits from the M sources, process the input sequence of the noise bits, and output a random sequence of bits, wherein the random sequence of bits is more random than the input sequence of the noise bits.
G06F 7/58 - Random or pseudo-random number generators
H03K 19/21 - EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
24.
DATA RECOVERY WITH ENHANCED SUPER CHIP-KILL RECOVERY AND METHOD OF OPERATING SUCH MEMORY SYSTEM
A memory system having a memory block and a memory controller in communication with the memory block. The memory controller is configured to: decode codewords in the memory block; determine failed codewords based on one or more parity checks including a chipkill parity; and turbo-decode the failed codewords using at least two decoders in a feedback loop with adders prior to each decoder for scaling soft decode information prior to subsequent decoding of the failed codewords.
A semiconductor device includes a gate structure including a cell region and a contact region, a slit structure configured to extend in a first direction through the gate structure, first channel structures disposed in the cell region of the gate structure, and second channel structures disposed in the cell region of the gate structure and disposed to be more adjacent to the contact region of the gate structure than the first channel structures. In a second direction that intersects the first direction, the first channel structures may be spaced apart from the slit structure by a first distance, and the second channel structures may be spaced apart from the slit structure at a second distance.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 23/528 - Layout of the interconnection structure
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
26.
SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
A semiconductor device may include: a lower structure; a horizontal layer spaced apart from the lower structure and extending along a direction parallel to the lower structure; a vertical conductive line extending along a direction perpendicular to the lower structure and coupled to a first side end of the horizontal layer; a data storage element coupled to a second side end of the horizontal layer; and a horizontal conductive line extending along a direction crossing the horizontal layer and including a sloped side facing the vertical conductive line.
Provided is a method by which a second chip obtains a control code such as firmware in a memory controller having a chiplet-based structure. The memory controller includes a first chip configured to perform a first operation, a plurality of second chips configured to perform a second operation, a plurality of data links configured to connect the first chip and each of the plurality of second chips on a one-to-one basis and used for data transmission between the first chip and each of the plurality of second chips during normal operation after booting, a control link connected to the first chip and all the plurality of second chips and used to transmit a control code for performing the second operation of the plurality of second chips, and a memory connected to the first chip to store the control code of the plurality of second chips.
A memory device includes: a plurality of memory cell strings including a plurality of memory cells connected to a plurality of word lines; a peripheral circuit for performing a read operation that reads data stored selected memory cells connected to a selected word line among the plurality of word lines; and a read operation controller for controlling the peripheral circuit to perform the read operation in a first mode or a second mode, based on a result obtained by performing a disturb sensing operation that identifies a degree to which a threshold voltage of dummy memory cells connected to a dummy word line is changed when the selected word line is included in weak word line information.
An output driver includes a pull-up driving circuit coupled between a supply voltage terminal and an output pad, and configured to perform a pull-up operation on the output pad, a pull-down driving circuit coupled between the output pad and a ground terminal, and configured to perform a pull-down operation on the output pad, and a high voltage protection circuit including a resistor string and a transistor that are coupled in series between the output pad and the ground terminal.
H03K 17/081 - Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
30.
MEMORY SYSTEM WITH MULTIPLE MEMORY RANKS AND METHOD OF OPERATING THE MEMORY SYSTEM WITH MULTIPLE MEMORY RANKS
A memory system includes a plurality of memory ranks, and a memory controller configured to control the plurality of memory ranks. The memory controller performs scheduling such that a request to be processed first is selected based on a counting value obtained by counting requests with the plurality of memory ranks as target memory ranks.
A peripheral component interconnect express (PCIe) device includes a common function performing operations associated with a PCIe interface according to a function type, the common function being programmable to be a function type selected from a plurality function types, an access identification information controller generating first access identification information for allowing an access to the common function, and providing the first access identification information to an assigned system image to which the common function has been assigned, a data packet receiver receiving a data packet including target identification information indicating a target system image from the target system image, and an access allowance determiner determining whether or not to allow the target system image to access the common function based on the first access identification information and the target identification information.
A semiconductor device includes a gate structure including conductive layers and insulating layers that are alternately stacked. The semiconductor device also includes an insulating core located in the gate structure and including a long axis and a short axis. The semiconductor device further includes a first channel pattern and a second channel pattern surrounding the insulating core and located to face each other along the long axis. The semiconductor device additionally includes a barrier pattern surrounding the first channel pattern and the second channel pattern and having different thicknesses along the long axis and the short axis.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/30 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/30 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
33.
ELECTRONIC DEVICE, ELECTRONIC SYSTEM INCLUDING THE SAME AND OPERATING METHOD OF THE ELECTRONIC SYSTEM
Disclosed is an electronic device including a counter suitable for counting a clock signal and generating a count signal corresponding to a count value of the clock signal, a target count generator suitable for generating a target count signal based on the count signal and a second adjusting signal, a comparator suitable for comparing the target count signal with a reference count signal and generating a comparison signal which corresponds to a difference value between the count value corresponding to the target count signal and a count value corresponding to the reference count signal, and a count value adjuster suitable for generating the second adjusting signal corresponding to the difference value, based on the comparison signal.
H04N 25/76 - Addressed sensors, e.g. MOS or CMOS sensors
H03K 5/22 - Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
According to the present technology, a storage device includes a nonvolatile storage area including a plurality of backup memory blocks each including a plurality of memory cells respectively connected to a plurality of word lines, and a controller configured to control the nonvolatile storage area to determine a target memory block in which data is to be stored among the plurality of backup memory blocks, determine a reference word line among the plurality of word lines coupled to the target memory block, and perform a pre-conditioning operation of programming dummy data to memory cells connected to at least one of remaining word lines except for the reference word line among the plurality of word lines coupled to the target memory block.
G11C 14/00 - Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
G06F 3/06 - Digital input from, or digital output to, record carriers
35.
IMAGE SENSOR, RANDOM NUMBER GENERATION SYSTEM USING THE IMAGE SENSOR
A random number generation system for generating random number(s) using an image sensor is disclosed. The image sensor includes a photoelectric conversion element configured to generate charges in response to light, a first tap in which a first charge from among the charges generated by the photoelectric conversion element is accumulated, and a second tap in which a second charge from among the charges generated by the photoelectric conversion element is accumulated.
A data processing system includes a storage medium, and a controller including a data processing block, configured to receive data from a host, transmit the received data to the storage medium, read data from the storage medium in response to a read request from the host, and decode the read data by the data processing block according to multiple decoding modes. The data processing block includes a first decoder and a second decoder, and is configured to manage the first decoder and the second decoder to run the decoding for the read data, and activate a fast decoding having shorter latency than a normal decoding after a fast decoding condition is satisfied.
H03M 13/37 - Decoding methods or techniques, not specific to the particular type of coding provided for in groups
G06F 3/06 - Digital input from, or digital output to, record carriers
G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
A storage device includes a memory controller and a plurality of memory devices. The plurality of memory devices comprise a first memory device coupled to the memory controller and an nth memory device coupled in series to the first memory device, where n is a natural number greater than 1. The memory controller is configured to transmit, to a first memory device, a signal that includes a target ID indicating a selected memory device from among the plurality of memory devices. Each memory device includes a plurality of memory dies, an interface configured to distribute the signal based on the target ID, and a redriver configured to redrive the signal such that the signal is transferred to another memory device.
A semiconductor package including: a base layer; a first chip stack and a second chip stack sequentially stacked over the base layer, each of the first and second chip stacks including a plurality of semiconductor chips which are offset stacked to expose chip pads at one side edge thereof, and the chip pads including stack identification pads for identifying the first chip stack and the second chip stack and chip identification pads for identifying the plurality of semiconductor chips in each of the first and second chip stacks; a first inter-chip wire and a second inter-chip wire connecting power-applied ones of the chip identification pads of the plurality of semiconductor chips of the first and second chip stacks; a first stack wire and second stack wire connecting the chip identification pad of a lowermost semiconductor chip of the first and second chip stacks to the base layer.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
39.
MEMORY CELL AND SEMICONDUCTOR MEMORY DEVICE WITH THE SAME
A semiconductor memory device and method for making the same. The semiconductor device includes a transistor laterally extending in a direction parallel to a substrate and including an active layer over the substrate, the active layer having a first end and a second end; bit line contact nodes formed on an upper surface and a lower surface of the first end of the active layer, respectively; a bit line side-ohmic contact vertically extending and connecting to the first end of the active layer and the bit line contact nodes; a bit line extending in a vertical direction to the substrate and connected to the bit line side-ohmic contact; and a capacitor connected to the second end of the active layer.
H10B 12/00 - Dynamic random access memory [DRAM] devices
G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
40.
MEMORY INCLUDING MEMORY CELLS HAVING DIFFERENT SIZES
A memory may include a first memory block including a plurality of first memory cells; and a second memory block including a plurality of second memory cells each having a larger size than each of the plurality of first memory cells. Normal data may be stored in the first memory block, and critical data requiring reliability may be stored in the second memory block.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
G11C 16/26 - Sensing or reading circuits; Data output circuits
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
41.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE
The present technology relates to a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a stack including a plurality of interlayer insulating layers and a plurality of gate conductive layers alternately stacked, a channel plug formed on a cell region by vertically passing through the stack, a plurality of support structures formed on a contact region by vertically passing through the stack, and a sacrificial layer surrounding a lower end portion sidewall of each of the plurality of support structures.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
Provided herein may be a memory device and a method of operating the same. The memory device may include a memory block including a plurality of memory strings, a peripheral circuit configured to perform an erase operation and a program operation on the memory block, and a control logic configured to control the peripheral circuit to perform the erase operation and the program operation on the memory block, wherein the control logic is configured to control the peripheral circuit to perform an abnormally injected electron removal operation that removes abnormally injected electrons trapped in a charge storage layer of a plurality of memory cells included in the memory block after the erase operation has been completed.
A semiconductor device includes first and second memory devices configured to share a first transmission line from which a write clock is received and a second transmission line from which data is received. The memory devices receive the data through first to eighth internal clocks that are generated by dividing a frequency of the write clock, and selectively align and store at least some of the data that is received in synchronization with the first to eighth internal clocks based on timing at which the data is synchronized with the write clock.
A semiconductor device includes a pull-up source voltage generation circuit configured to drive a pull-up voltage to a normal voltage during a normal period and to drive the pull-source voltage to a test voltage during a test period. The semiconductor device also includes a pull-down source voltage generation circuit configured to drive a pull-down voltage to a ground voltage during the normal period and to drive the pull-down source voltage to a bit line pre-charge voltage during the test period. The semiconductor device further includes an equalization control signal driver configured to receive the pull-up source voltage and the pull-down source voltage to drive an equalization control signal for equalizing voltage levels of an internal bit line pair of a bit line sense amplifier.
G11C 7/12 - Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
A memory device includes a memory block including a plurality of pages; and a control logic configured to control, when a read command for a selected page among the plurality of pages is received, a read operation on the selected page to be performed using a plurality of read voltages, wherein the plurality of read voltages are determined based on a reference value for the selected page and a read count representing a number of times a read operation of reading data stored in the selected page is performed after a program operation of storing data in the selected page.
G11C 16/26 - Sensing or reading circuits; Data output circuits
G11C 7/02 - Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals
G11C 15/04 - Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements
Disclosed is an image sensing device, including: a plurality of pixel arrays, and the pixel arrays include: a first pixel array including a plurality of first unit pixels, and a second pixel array disposed to surround the first pixel array and including a plurality of second unit pixels, and the first unit pixel includes a plurality of photodiodes, and each photodiode of the first unit pixel is connected to a different transfer transistor.
A memory module includes a plurality of first memory chips and a second memory chip. Raw data is stored in the plurality of first memory chips. Parity data generated based on the raw data is stored in the second memory chip. Each of the first memory chips and the second memory chip is configured to exchange data with a controller based on a burst length unit. The second memory chip stores a first parity data generated from the raw data by a first error correction method, and stores a second parity data generated from the raw data and the first parity data by a second error correction method.
Provided herein may be a memory controller and a memory system including the same. The memory controller may include an error correction circuit configured to perform error correction decoding on data that is read by read retry operations, a buffer memory configured to store decoding history information including retry fail voltages used for a failure in the read retry operations and syndrome weights respectively corresponding to the retry fail voltages, and a processor configured to, when a number of times that the read retry operations fail reaches a threshold number of times, determine a voltage corresponding to a minimum syndrome weight determined based on a relationship between changes in the syndrome weights relative to magnitudes of the retry fail voltages, to be an optimally estimated read voltage, and provide data that is read using the optimally estimated read voltage to the error correction circuit.
An image processing device may include: a noise information manager for managing noise information of a target image sensor and a reference image sensor. It may also include a physical intrinsic identification key generator, which generates a physical intrinsic identification key of the target image sensor, based on a difference between noise signals output from pixels of the target image sensor that are adjacent to each other. An intrinsic image generator generates intrinsic image data, which includes the physical intrinsic identification key of the target image sensor.
EWHA UNIVERSITY-INDUSTRY COLLABORATION FOUNDATION (Republic of Korea)
Inventor
Kim, Ji Hoon
Kim, So Hyeon
Abstract
Proposed are an on chip multi-core system and an optimizing method for PR resource selection in which management for allocating a plurality of partial regions (PRs) constituting a reconfigurable resource pool to a corresponding core of multiple cores and management for reconfiguring the inside of each PR can be separately performed, fragmentation can be minimized after the allocation of the PRs, and the reconfiguration time of an accelerator can be shortened. The on chip multi-core system includes a PR map, a core unit, a PR resource management processor, an inter PR routing controller, a bitstream memory, and an intra PR configuration controller.
An image sensing device includes an image sensor suitable for correcting depth information based on a control signal, and for generating image data according to the depth information, and a controller suitable for analyzing an error of the depth information, and for generating the control signal, based on first and second cycle signals provided from the image sensor.
H04N 17/00 - Diagnosis, testing or measuring for television systems or their details
H04N 23/65 - Control of camera operation in relation to power supply
H04N 23/959 - Computational photography systems, e.g. light-field imaging systems for extended depth of field imaging by adjusting depth of field during image capture, e.g. maximising or setting range based on scene characteristics
H04N 25/705 - Pixels for depth measurement, e.g. RGBZ
H04N 25/709 - Circuitry for control of the power supply
H04N 25/76 - Addressed sensors, e.g. MOS or CMOS sensors
A semiconductor device may include a first capacitor and a second capacitor located at a different height from the first capacitor. Each of the first and second capacitors includes a lower electrode, an upper electrode and a dielectric layer between the lower electrode and the upper electrode. A selected one of the lower and upper electrodes includes a first portion having a cylindrical shape including a closed lower surface and an opened upper surface and a second portion vertically extended from the first portion of the selected one. A selected another one of the lower and upper electrodes includes a first portion having a bar shape extended into the first portion of the selected one, a second portion vertically extended from the first portion of the selected another one, and a third portion having a disc shape between the first portion and the second portion in the selected another one.
H01L 27/08 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
53.
SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
There are provided a semiconductor memory device and a manufacturing method thereof. The semiconductor memory device includes: a source layer; a channel structure extending in a first direction from within the source layer; a source-channel contact layer surrounding the channel structure on the source layer; a first select gate layer overlapping with the source-channel contact layer and surrounding the channel structure; a stack including interlayer insulating layers and conductive patterns that are alternately stacked in the first direction and surrounding the channel structure, the stack overlapping with the first select gate layer; and a first insulating pattern that is formed thicker between the first select gate layer and the channel structure than between the stack and the channel structure.
A semiconductor device includes a page buffer array and a continuous read determination circuit configured to determine a continued read request for pages in which encoded data are stored, based on an address and a command that are received from a host. When it is determined that a request that is received from the host is the continued read request, the page buffer array is controlled to sense and store coding data of a page in which the coding data have been stored and to use the sensed coding data in a subsequent read operation.
G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
G11C 16/08 - Address circuits; Decoders; Word-line control circuits
A semiconductor device includes a supporter including a plurality of stairs, a gate structure including gate lines that are stacked on the supporter, wherein the gate lines include pads, and the pads are disposed over the plurality of stairs, first contact plugs that are connected to the pads, and channel structures that extend through the gate structure.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
56.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device may include first conductive lines extending in a first direction; second conductive lines extending in a second direction that intersects the first direction; memory cells disposed between the first conductive lines and the second conductive lines in a third direction perpendicular to each of the first and the second directions, each of the memory cells comprising a variable resistance pattern; first gap-fill patterns disposed between the memory cells and having first thermal conductivity; and second gap-fill patterns disposed on the first gap-fill patterns in the third direction and having second thermal conductivity lower than the first thermal conductivity, wherein an interface between each of the second gap-fill patterns and each a corresponding one of the first gap-fill patterns is disposed between an upper surface and a lower surface of the variable resistance pattern.
H10N 70/00 - Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
A storage device may input a program command requesting to program target data into the memory, input the target data into a memory, and input the program confirmation command into the memory after inputting the program command and the target data into the memory. In this case, the program confirmation command may include information about a cell type of memory cells to be programmed with target data among a plurality of memory cells.
Provided herein is an electronic device and a method of image processing. An electronic device may include an image sensor configured to obtain image data including color pixel values and texture pixel values using color pixels and texture pixels, a resolution converter configured to generate two or more images having different sizes based on the image data, a parameter calculator configured to acquire two or more parametric images, respectively corresponding to the two or more images, using converted color pixel values and converted texture pixel values that are included in each of the two or more images, a parameter synthesizer configured to acquire a synthesized parametric image by synthesizing the two or more parametric images, and an image acquirer configured to acquire an output image based on the synthesized parametric image and the texture pixel values included in the image data.
A semiconductor device includes: a substrate; a bit line positioned over the substrate and extending in a first direction; a first dielectric layer covering the bit line; a first channel layer positioned over the first dielectric layer; at least one word line positioned over the first channel layer and extending in a second direction crossing the first direction; a second dielectric layer at least filling a space between adjacent word lines; a first contact coupled to the bit line by penetrating the second dielectric layer, the first channel layer, and the first dielectric layer; a third dielectric layer positioned over the word line, the second dielectric layer, and the first contact; and a second contact coupled to the first channel layer by penetrating the third dielectric layer and the second dielectric layer.
A semiconductor device according to an embodiment includes a substrate, first and second pillar electrodes extending along a vertical direction substantially perpendicular to a surface of the substrate, and a plurality of memory cells disposed between the first and second pillar electrodes. Each of the plurality of memory cells includes first and second shared device layers that are disposed adjacent to the first and second pillar electrodes, respectively, and extend along the vertical direction, first and second base device layers disposed between the first and second shared device layers, and a control gate electrode disposed on one of the first and second base device layers. Both first and second base device layers are disposed on a plane over the substrate and substantially parallel to the surface of the substrate.
A semiconductor device includes: a substrate; two heating patterns arranged to be spaced apart from each other over the substrate; two metal oxide patterns respectively positioned over the two heating patterns; two second oxide semiconductor patterns comprising source/drain regions and respectively positioned over the two metal oxide patterns; a first oxide semiconductor pattern forming a channel region positioned between the two second oxide semiconductor patterns; a gate electrode positioned over or below the first oxide semiconductor pattern; and a gate dielectric layer interposed between the gate electrode and the first oxide semiconductor pattern, wherein an oxygen density of the two second oxide semiconductor patterns is smaller than an oxygen density of the first oxide semiconductor pattern.
The present technology relates to an electronic device. According to the present technology, a page buffer may include a bit line voltage control circuit, a latch and a reference voltage supply circuit. The bit line voltage control circuit may selectively connect a bit line and a sensing node. The latch may provide a latch signal corresponding to data. The reference voltage supply circuit may include a first PMOS transistor and a first NMOS transistor coupled in series between the sensing node and a ground voltage terminal, and apply a first reference voltage to the sensing node. The first PMOS transistor may be controlled according to the reference voltage control signal. The first NMOS transistor may be controlled by the latch signal.
G11C 7/12 - Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
G11C 7/14 - Dummy cell management; Sense reference voltage generators
There are provided a semiconductor memory device and a manufacturing method of a semiconductor memory device. The semiconductor memory device includes: a plurality of conductive layers stacked to be spaced apart from each other in a first direction; a channel hole extending in the first direction to penetrate the plurality of conductive layers; two or more channel patterns disposed to be spaced apart from each other along a sidewall of the channel hole; and two or more memory patterns disposed to be spaced apart from each other between the sidewall of the channel hole and the two or more channel patterns, respectively.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
64.
SEMICONDUCTOR DEVICE AND TRAINING METHOD OF THE SEMICONDUCTOR DEVICE
A semiconductor device including an input circuit including a buffer configured to buffer an external signal that is received from a pad, a variable delay circuit configured to delay a signal that is output by the buffer in response to a plurality of delay setting signals, and a latch configured to output the output of the variable delay circuit as an internal signal by latching the output in response to a clock signal, and a setting circuit configured to store the plurality of delay setting signals.
An operation method of a memory may include receiving a meta data read command and a first address; reading meta data from memory cells in columns corresponding to the first address and storing the read meta data in a meta data buffer; receiving a normal read command and a second address; reading normal read data from memory cells in columns corresponding to the second address; and outputting the normal read data and a part of the meta data stored in the meta data buffer.
A semiconductor memory device includes: a memory cell region including normal cells and row-hammer cells coupled to each of a plurality of rows, wherein the row-hammer cells of a selected row are suitable for storing first data and second data, the first data representing a number of accesses to the selected row and the second data denoting whether to refresh second adjacent rows of the selected row; and a refresh control circuit suitable for: selecting a sampling address based on the first data read from a row corresponding to an input address when an active command is inputted, determining, in response to a refresh command, whether to refresh first adjacent rows of a target row corresponding to the sampling address, and determining, in response to the refresh command, whether to refresh second adjacent rows of the target row based on the second data read from the target row.
There are provided a memory device and a manufacturing method of the memory device. The memory device includes: a peripheral circuit disposed on a substrate; and a gate stack structure overlapping with the peripheral circuit. The gate stack structure includes a plurality of first cell plugs having substantially a cylindrical structure and a plurality of second cell plugs having substantially a hexagonal prism structure.
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
68.
CONTROL CIRCUIT, MEMORY DEVICE INCLUDING THE SAME, AND METHOD
A control circuit configured to associate a plurality of memory with an error correction scheme. The control circuit including an internal operation circuit configured to generate an internal command based on an access unit of the plurality of memory. The control circuit including a storage circuit configured to store information on the access unit of the plurality of memory.
The present disclosure may provide a semiconductor device having a stable structure and a low manufacturing degree of the difficulty. The device may include conductive layers and insulating layers which are alternately stacked; a plurality of pillars passing through the conductive layers and the insulating layers; and a plurality of deposition inhibiting patterns, each deposition inhibiting pattern being formed along a portion of an interface between a side-wall of each of the pillars and each of the conductive layers and along a portion of an interface between each of the insulating layers and each of the conductive layers.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
70.
SEMICONDUCTOR DEVICE AND OPERATING METHOD OF SEMICONDUCTOR DEVICE
A semiconductor device may include a page buffer comprising first to fifth latches, wherein the first to third latches and the fifth latch are configured to store 4-bit original data, among 5-bit original data, respectively, and the fourth latch is configured to store data identical with the data that has been stored in the second latch and a control circuit configured to determine a program inhibition pattern based on data that have been stored in two of the first to fifth latches and control the page buffer so that data that has been stored in at least one of the first to fifth latches is inverted based on the program inhibition pattern.
A semiconductor device includes: a lower semiconductor structure including one or more first lower test pads, one or more second lower test pads that are alternately arranged with the one or more first lower test pads, and a lower test terminal that is electrically connected to the second lower test pad through a second lower test line; and an upper semiconductor structure positioned over the lower semiconductor structure and including an upper test pad and an upper test terminal that is electrically connected to the upper test pad through an upper test line, wherein, when the lower semiconductor structure and the upper semiconductor structure are aligned, the upper test pad overlaps with and contacts a corresponding first lower test pad among the one or more first lower test pads, and is spaced apart from the second lower test pad that is adjacent to the corresponding first lower test pad.
G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
72.
MEMORY DEVICE PERFORMING PROGRAM OPERATION AND METHOD OF OPERATING THE SAME
The present technology relates to a semiconductor device. According to the present technology, a memory device having a reduced size may include a plurality of memory cells connected to a selected word line, a plurality of page buffers configured to store at least one second logical page data except for first logical page data in a plurality of first program loops performed on the plurality of memory cells, and store the first logical page data after the plurality of first program loops are performed, and a control logic configured to control the plurality of first program loops based on the at least one second logical page data, determine first memory cells programmed to one program state based on the first logical page data, and control a plurality of second program loops performed on second memory cells.
A method of operating a memory device includes performing a first program operation on first memory cells connected to a first channel region among a plurality of channel regions formed by separating one channel hole into the plurality of channel regions, based on a first verify voltage. The method also includes performing a second program operation on second memory cells connected to a second channel region among the plurality of channel regions, based on a second verify voltage. The method further includes determining third memory cells having a threshold voltage lower than a target threshold voltage distribution among the first memory cells while performing the second program operation. The method additionally includes performing a third program operation on the third memory cells.
The present technology relates to an electronic device. According to the present technology, a storage device includes a plurality of nonvolatile memory devices, a buffer memory configured to temporarily store data provided by the memory devices, and a controller including a descriptor queue storing a plurality of descriptors, wherein the controller controls the memory devices to perform a read operation corresponding to a first descriptor among the plurality of descriptors, performs a first status check operation of checking whether read data read through the read operation is stored in the buffer memory, and determines, based on a result of the first status check operation, read data to be output to an external device from among the read data read through the read operation.
An image signal processor and an image signal processing method are disclosed. The image signal processor includes a local white balance gain (LWBG) calculator configured to calculate a first gain representing a ratio between red pixel data and green pixel data and a second gain representing a ratio between blue pixel data and green pixel data, a local white balance gain (LWBG) corrector configured to generate a first correction gain and a second correction gain by filtering each of the first gain and the second gain, and a demosaicing corrector configured to correct each of the red pixel data, the green pixel data, and the blue pixel data using the first correction gain and the second correction gain.
The disclosed technology relates to an electronic device with a memory module. In some implementations, a memory module may include a memory device and a memory controller. The memory device may store data. The memory controller may communicate with an external device through a first interface and the memory device through a second interface, and set a type of the second interface as a parallel interface or a serial interface according to a ratio between a first request and a second request received from the external device.
INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY (Republic of Korea)
Inventor
Shin, Cheol Min
Kang, Hyun Goo
Paik, Ungyu
Song, Taeseup
Jeong, Hojin
Abstract
A slurry composition may include an abrasive, a solvent, and polyol. The abrasive may include any one of metal oxide, metal nitride, metal oxynitride, and a combination thereof. The polyol may have about 0.01 mM to about 500 mM of a concentration. Thus, high polishing selectivities may be provided between a B—Si layer, a TiN layer and a SiN layer by controlling a polishing rate of the TIN layer.
A semiconductor device includes a stack structure, a channel layer passing through the stack structure, a memory layer enclosing the channel layer and including first and second openings which expose the channel layer, a well plate coupled to the channel layer through the first opening, and a source plate coupled to the channel layer through the second opening.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
Korea University Research and Business Foundation (Republic of Korea)
Inventor
Yu, Hyun-Yong
Jung, Seung Geun
Son, Mu Yeong
Abstract
A semiconductor device and a method of manufacturing the same. The semiconductor device has a substrate in which recess regions are formed and semiconductor regions acting as a source region or a drain region is defined between the recess regions; a gate insulating layer disposed on an inner surface of each recess region; a recess gate disposed on the gate insulating layer in each recess region; an insulating capping layer disposed above the recess gate in each recess region; a metallic insertion layer disposed between a side surface of the recess gate and a side surface of the insulating capping layer and facing with a side surface of the source region or the drain region; and an intermediate insulating layer disposed between the metallic insertion layer and the recess gate to electrically insulate the metallic insertion layer from the recess gate.
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/36 - Semiconductor bodies characterised by the concentration or distribution of impurities
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
80.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A semiconductor device includes a stacked body including stacked insulating layers and stacked conductive layers; a cell plug; a connection contact structure; and a source layer coupled to the cell plug. The cell plug includes upper and lower portions, the connection contact structure includes a first connection contact disposed at substantially the same level as the lower portion of the cell plug, and a second connection contact disposed at substantially the same level as the upper portion thereof, a level at which the first and second connection contacts contact each other is substantially the same as a level at which the upper and lower portions of the cell plug contact each other, and a level of an uppermost portion of the second connection contact is higher than a level of a bottom surface of the source layer, and is lower than a level of a top surface thereof.
H10B 43/50 - EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
H01L 23/535 - Arrangements for conducting electric current within the device in operation from one component to another including internal interconnections, e.g. cross-under constructions
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
H10B 41/50 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
A device for implementing a storage architecture includes a front-end chip configured to perform first interfacing with a first device, a plurality of back-end chips configured to perform second interfacing with second devices, and an input/output chip disposed to be separated from the front-end chip and the plurality of back-end chips and configured to perform a communication between the second devices and the plurality of back-end chips.
A method of operating an interface device including a first elastic buffer is provided. The method of operating the interface device includes performing a link equalization operation, checking a transmission mode of the interface device, and determining a transmission parameter of the interface device based on a status of the first elastic buffer or a status of a second elastic buffer included in another interface device communicating with the interface device when the transmission mode is a transmission parameter adjustment mode.
H04L 7/00 - Arrangements for synchronising receiver with transmitter
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
83.
SEMICONDUCTOR MEMORY DEVICE, CONTROLLER, MEMORY SYSTEM AND METHOD OF OPERATING THE SAME
The present technology includes a method of operating a controller that controls a semiconductor memory device including a plurality of memory blocks. The method includes receiving a read request for data included in any one memory block among the plurality of memory blocks from a host, and controlling the semiconductor memory device to read data corresponding to the read request using a read-history table. The read-history table includes read voltages used for a plurality of read pass operations for the any one memory block, respectively.
A memory device performs a coarse-program operation and a fine-program operation. During the coarse-program operation, the memory device selectively precharges a bit line to perform a verification. During the fine-program operation, the memory device precharges all bit lines to perform the verification.
A memory system includes: a memory device including a plurality of memory blocks each including a plurality of pages; and a memory controller configured to allocate, to a meta page among the plurality of pages, a first region including regions configured to store plural pieces of meta data respectively according to types of the plural pieces of meta data, and a second region configured to store additional meta data corresponding to at least one meta data among the plural pieces of meta data is stored, and control the memory device to store the plural pieces of meta data and the additional meta data in the first region and the second region, respectively.
A memory system includes a memory device including a plurality of memory blocks and a memory controller. The memory controller determines, when a read request for data stored in a first memory block among the plurality of memory blocks is received, whether a dummy read operation on the first memory block is to be performed, based on an erase count value of a second memory block which shares a block word line with the first memory block before a read operation on the first memory block is performed.
A memory device includes: a memory cell array including a plurality of memory cells; a peripheral circuit including a plurality of page buffers respectively connected to the plurality of memory cells through a plurality of bit lines and a voltage generating circuit for selectively outputting a program voltage and a verify voltage; and a control circuit configured to control the peripheral circuit to perform a plurality of program loops each including a program voltage apply operation and a verify operation. Each of the plurality of page buffers may include: a first latch for storing a verify result according to the verify operation of an nth program loop among the plurality of program loops; and a second latch for storing a verify result according to the verify operation of an (n−1)th program loop among the plurality of program loops.
A memory controller may allocate, to buffer memory, a write data buffer region and a write cache tag (WCT) buffer region corresponding to a write command from a host. The memory controller may store write data and WCTs for the write data in the write data buffer region and the WCT buffer region, respectively.
A memory device includes: a memory cell array including a cell string including a plurality of memory cells respectively connected between a common source line and a plurality of bit lines; a peripheral circuit for performing an internal operation on the memory cells; and control logic for controlling the peripheral circuit to apply a voltage necessary for the internal operation to word lines connected to the plurality of memory cells. The peripheral circuit includes a pass voltage information generator for generating pass voltage information including a number of clocks input from a time at which a pass voltage is applied to the word lines to a time at which a voltage level of the common source line reaches a predetermined reference level. The control logic includes a pass voltage determiner for determining a pass voltage to be applied to the word lines, based on the pass voltage information.
An image signal processor and an image signal processing method are disclosed. The image signal processor includes a half-edge pattern determination unit configured to determine whether a target kernel including a target pixel corresponds to a half-edge pattern, a half-edge pattern matching unit configured to determine directionality of the target kernel based on a half-edge pattern mask in which a highest weight is assigned to a pixel arranged in one direction from the target pixel when the target kernel corresponds to the half-edge pattern, and a pixel interpolation unit configured to interpolate the target pixel using pixel data of a pixel disposed at a position corresponding to the directionality of the target kernel, wherein the half-edge pattern is a pattern in which a region on one side of the edge crossing the kernel is filled with a texture region and a non-texture region.
A memory system having a memory block and a memory controller in communication with the memory block. The memory controller is configured to: decode codewords from the memory block, identify failed codewords from the decoded codewords, estimate raw bit errors RBERs of the failed codewords, sort failed codewords from a failed sector of the memory block in order from a first set of the failed codewords in the failed sector having a higher probability of being successfully decoded to a second set of the failed codewords in the failed sector having a lower probability of being successfully decoded, and perform a super chip kill SCK operation on one of the failed codewords in the first set to produce a recovered codeword.
A semiconductor device may include a memory cell array including a first memory string that is connected to a first drain selection line and a second memory string that is connected to a second drain selection line, a control circuit configured to generate a first switch control signal and a second switch control signal based on an address signal, a first switch disposed in a direction corresponding to the first drain selection line and configured to connect a global word line with a local word line or disconnect the global word line from the local word line based on the first switch control signal, and a second switch disposed in a direction corresponding to the second drain selection line and configured to connect the global word line with the local word line or disconnect the global word line from the local word line based on the second switch control signal.
A semiconductor device includes a first gate structure including a plurality of first conductive layers and a plurality of first insulating layers that are alternately stacked; an isolation insulating layer located in the first gate structure, the isolation insulating layer including a first line portion extending in a first direction, a plurality of first protrusions protruding from the first line portion towards one side of the first line portion in a second direction, and a plurality of second protrusions protruding from the first line portion towards another side of the first line portion in an opposite direction to the first protrusions, wherein the second direction is orthogonal to the first direction; a plurality of first memory patterns, wherein one of the plurality of first memory patterns surrounds one of the plurality of first protrusions; and a plurality of first passivation patterns, wherein one of the plurality of first passivation patterns is located between the first line portion and one of the plurality of first memory patterns.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
94.
NAND FLASH MEMORY DEVICE WITH ENHANCED DATA RETENTION CHARACTERISTICS AND OPERATING METHOD THEREOF
Seoul National University R&DB Foundation (Republic of Korea)
Inventor
Park, Sung Ho
Abstract
A flash memory device includes a control circuit and a cell array including a first memory string including a plurality of first flash memory cells having control gates connected to a plurality of word lines, respectively, and a first bit line selection switch connecting the plurality of first flash memory cells to a first bit line in response to a voltage of a first drain selection line. The control circuit controls a first operation to program a selected flash memory cell with data so that a threshold voltage of the selected flash memory cell becomes greater than a first target threshold voltage and a second operation to erase the selected flash memory cell so that the threshold voltage becomes equal to or smaller than a target threshold voltage, the first target threshold voltage being greater than the target threshold voltage that is set according to the data.
A semiconductor device includes a stack disposed over a peripheral circuit. The stack includes alternately stacked insulating layers and sacrificial layers. The semiconductor device also includes a first contact structure penetrating through the stack to connect with the peripheral circuit. The first contact structure includes a protruding part extending outward from a sidewall of the first contact structure. The semiconductor device further includes a second contact structure disposed on the first contact structure. The second contact structure is connected to the protruding part of the first contact structure.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
Probe cards that can replace lens units are disclosed. In some implementations, a probe card may include a lens unit through which light irradiated from a light source unit; a jig into which the lens unit is inserted inside, and a holder unit for closely supporting the lens unit.
A memory device includes: a memory block including a plurality of memory cells; a peripheral circuit for performing a program operation on selected memory cells among the plurality of memory cells; and a control logic for controlling the program operation of the peripheral circuit. The control logic controls the peripheral circuit to perform a foggy program operation on first memory cells connected to a first word line among the plurality of memory cells, perform a foggy program operation on second memory cells connected to a second word line adjacent to the first word line among the plurality of memory cells, and perform a fine program operation on the first memory cells, based on a target program state of the second memory cells.
G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
An image signal processor, and a method for processing an image signal, include a directionality strength determiner, a half-directional pattern determiner, and a pixel interpolator. The directionality strength determiner divides a target kernel including a target pixel into a plurality of sub-kernels, and generates gradient sum information by calculating directionality strength of each of the plurality of sub-kernels. The half-directional pattern determiner determines whether a half-directional edge pattern is included in each of the sub-kernels in response to the gradient sum information. The pixel interpolator interpolates the target pixel in response to the edge pattern determined by the half-directional pattern determiner.
H04N 23/81 - Camera processing pipelines; Components thereof for suppressing or minimising disturbance in the image signal generation
H04N 23/83 - Camera processing pipelines; Components thereof for controlling camera response irrespective of the scene brightness, e.g. gamma correction specially adapted for colour signals
99.
SEMICONDUCTOR MEMORY DEVICE PERFORMING PROGRAM OPERATION AND OPERATING METHOD OF THE SEMICONDUCTOR MEMORY DEVICE
A semiconductor memory device includes: a memory cell array including a plurality of memory cells; a peripheral circuit including a plurality of page buffers each performing an auxiliary verify operation and a main verify operation, which are used to program selected memory cells among the plurality of memory cells; and control logic for controlling the auxiliary verify operation and the main verify operation of the peripheral circuit. During the main verify operation, the control logic controls the peripheral circuit to selectively precharge sensing nodes of the plurality page buffers respectively corresponding to the selected memory cells, based on a result of the auxiliary verify operation.
According to one embodiment, a magnetic memory device includes a first ferromagnetic layer, a first nonmagnetic layer provided on the first ferromagnetic layer, a second ferromagnetic layer provided on the first nonmagnetic layer, an oxide layer containing magnesium (Mg), a rare-earth element, and a noble-metal element and provided on the second ferromagnetic layer, and a second nonmagnetic layer provided on the oxide layer.
patents
