A method of forming a mask pattern may include forming a sacrificial mask pattern on a substrate. A plurality of upper mask patterns may be formed on side surfaces of the sacrificial mask pattern. Each of the plurality of upper mask patterns may include a surface enhancement layer and an upper mask layer. The upper mask layer may be formed between the surface enhancement layer and the sacrificial mask pattern. By removing the sacrificial mask pattern, the plurality of upper mask patterns may be exposed.
H01L 21/033 - Fabrication de masques sur des corps semi-conducteurs pour traitement photolithographique ultérieur, non prévue dans le groupe ou comportant des couches inorganiques
H01L 21/3213 - Gravure physique ou chimique des couches, p.ex. pour produire une couche avec une configuration donnée à partir d'une couche étendue déposée au préalable
According to an embodiment of the present disclosure, a semiconductor device includes an even data input circuit configured to store, in an even core cell, data that is input through an even data pad and that has a first pattern in response to an even data input strobe signal in a write operation of a parallel test. The semiconductor device includes an odd data input circuit configured to store, in an odd core cell, data that is input through the even data pad and that has a second pattern in response to an odd data input strobe signal in the write operation of the parallel test.
A semiconductor system including: an operation period adjusting circuit configured to generate operation information for adjusting an operation period, when an input count of an active command during a test mode period is equal to or more than a preset count; and a command generation circuit configured to adjust the input count of the active command applied to a semiconductor device during a preset period, by adjusting the operation period on the basis of the operation information.
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
G11C 29/36 - Dispositifs de génération de données, p.ex. inverseurs de données
4.
SEMICONDUCTOR DEVICES RELATED TO DATA INPUT AND OUTPUT OPERATIONS
A semiconductor device includes a strobing signal generating circuit configured to sequentially generate write input signals, based on a write strobing signal and to sequentially generate write output signals, based on a delayed write strobing signal when a write operation is performed. The semiconductor device incudes an input/output control circuit configured to receive and latch write data input from a data input/output circuit, based on the write input signals, and to store the latched write data in a cell area as write core data, based on the write output signals.
G11C 7/22 - Circuits de synchronisation ou d'horloge pour la lecture-écriture [R-W]; Générateurs ou gestion de signaux de commande pour la lecture-écriture [R-W]
G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p.ex. circuits de commande E/S de données, mémoires tampon de données E/S
G11C 7/20 - Circuits d'initialisation de cellules de mémoire, p.ex. à la mise sous ou hors tension, effacement de mémoire, mémoire d'image latente
5.
SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
A method for fabricating a semiconductor device includes: forming a mold stack layer including a mold layer and a supporter layer over a substrate; forming opening by etching the mold stack layer; selectively forming a supporter reinforcement layer on an exposed surface of the supporter layer which is positioned in the opening; forming a bottom electrode in the opening in which the supporter reinforcement layer is formed; and forming a supporter opening by etching a portion of the supporter layer to form a supporter that supports an outer wall of the bottom electrode.
Provided herein is a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device may include a gate stacked body in which a plurality of interlayer insulating layers and a plurality of conductive patterns are alternately stacked, and a plurality of channel structures disposed to extend in a vertical direction in the gate stacked body disposed in a cell region, wherein the plurality of conductive patterns extend in a horizontal direction in the cell region, and extend in the vertical direction or in a direction between the vertical direction and the horizontal direction in a word line contact region adjacent to the cell region.
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs sous-groupes différents du même groupe principal des groupes , ou dans une seule sous-classe de ,
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
7.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A semiconductor device may include a gate structure, a source structure that is disposed on the gate structure, channel structures that extend into the source structure through the gate structure and include a channel layer and a memory layer surrounding the channel layer, the memory layer including a cut area that exposes the channel layer, and a slit structure that extends into the source structure through the gate structure between the channel structures, an upper surface of the slit structure being disposed at a lower level than the cut area.
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
H10B 41/40 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région de circuit périphérique
H10B 43/40 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région de circuit périphérique
8.
DATA CORRECTING DEVICE AND DATA CORRECTING METHOD THEREOF
Disclosed is a device for correcting an erasure including a defect symbol location generating unit and an erasure decoding unit. The defect symbol location generating unit generates third information on a location of an erasure. The erasure decoding unit performs an erasure correcting operation on a read codeword read from a memory unit based on the third information.
A storage device may include a memory and a controller. The memory may include a plurality of memory units. The controller may transmit a read command for a target memory unit among the plurality of memory units to the memory, read a state value from the memory after transmitting the read command to the memory, and determine that all bits of data stored in the target memory unit are 1 when the state value is a first value, and determine that all bits of the data stored in the target memory unit are 0 when the state value is a second value.
According to an embodiment of the present disclosure, a memory device, a peripheral circuit configured to perform a program operation, including a plurality of program loops, and a control logic configured to, in some of the plurality of loops of the program operation, control the peripheral circuit to apply a program voltage to a selected word line, apply a first pass voltage to adjacent word lines that are adjacent to the selected word line, and then apply a second pass voltage to adjacent word lines at a predetermined time point, wherein the second pass voltage has a different magnitude compared to the first pass voltage, and in the rest of the plurality of loops of the program operation, control the peripheral circuit to apply the second pass voltage to the adjacent word lines at a time point that is different from the predetermined time point from a selected loop.
G11C 16/34 - Détermination de l'état de programmation, p.ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
G11C 16/10 - Circuits de programmation ou d'entrée de données
11.
SEMICONDUCTOR SYSTEM FOR PERFORMING AN ACTIVE OPERATION USING AN ACTIVE PERIOD CONTROL METHOD
A semiconductor system including: an operation period adjusting circuit configured to generate operation information for adjusting an operation period, when an input count of an active command during a test mode period is equal to or more than a preset count; and a command generation circuit configured to adjust the input count of the active command applied to a semiconductor device during a preset period, by adjusting the operation period on the basis of the operation information.
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
G11C 29/36 - Dispositifs de génération de données, p.ex. inverseurs de données
In an embodiment, a semiconductor die includes a substrate, an interlayer insulating layer under a front-side surface the substrate, a horizontal metal interconnection in the interlayer insulating layer, a front-side pad under a lower surface of the interlayer insulating layer, a front-side bump structure under a lower surface of the front-side pad, a through-electrode vertically passing through the substrate, a back-side insulating layer over the back-side surface of the substrate, a first back-side metal plate layer over the back-side insulating layer, a back-side passivation layer over the back-side insulating layer and covering the first back-side metal plate layer, and a back-side bump structure over the through-electrode and the back-side passivation layer.
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes
H01L 23/552 - Protection contre les radiations, p.ex. la lumière
13.
SEMICONDUCTOR DEVICE AND OPERATING METHOD OF SEMICONDUCTOR DEVICE
Disclosed is a semiconductor device including a first cell mat including memory cells connected to a first bit line, a second cell mat including memory cells connected to a second bit line, a sense amplifier configured to amplify a difference in voltages between the first bit line and the second bit line, and a control circuit configured to differently adjust timing at which the first bit line and the second bit line are connected to or disconnected from the sense amplifier.
In a method of manufacturing a semiconductor device, an additional, induced-stress-limiting structure may be provided on a surface, which opposes stress that can be induced in a semiconductor device during its manufacturing processes. Such a stress compensation layer may be formed on a surface to compensate a stress applied to the rest of structure.
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
In an embodiment of the disclosed technology, a host device may control an operation of writing data to a plurality of types of memory cells included in a memory, through booster logic units respectively corresponding to the plurality of types of memory cells, and a timing thereof. It is possible to prevent performance of a device from degrading due to differences in characteristics of operations in which data are written to the plurality of types of memory cells, and improve performance and efficiency of an operation of writing data to a plurality of memory cells.
Embodiments of the present disclosure relate to a storage device based on a daisy chain topology. According to embodiments of the present disclosure, a storage device may include a plurality of memory package chips each including a plurality of memory dies capable of storing data; and a controller communicating with the plurality of memory package chips and connected to the plurality of memory package chips through one or more daisy chain circuits.
G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p.ex. circuits de commande E/S de données, mémoires tampon de données E/S
G11C 8/18 - Circuits de synchronisation ou d'horloge; Génération ou gestion de signaux de commande d'adresse, p.ex. pour des signaux d'échantillonnage d'adresse de ligne [RAS] ou d'échantillonnage d'adresse de colonne [CAS]
Provided herein may be a memory system and a host device. The memory system may include a first memory module communicating with a host through a first interface and a second memory module communicating with the host through a second interface. The second memory module may include a memory device configured to store data and a memory controller configured to update at least one of first metadata related to a space-locality and second metadata related to a time-locality based on a result of comparing the numbers of the pages respectively corresponding to a first trigger address and a second trigger address sequentially input from the host, and to prefetch, to the first memory module, the data determined based on the first metadata and the second metadata. The first and second trigger addresses are addresses corresponding to data for which access to the first memory module is missed.
G06F 12/0862 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p.ex. mémoires cache avec pré-lecture
G06F 12/0804 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p.ex. mémoires cache avec mise à jour de la mémoire principale
G06F 13/42 - Protocole de transfert pour bus, p.ex. liaison; Synchronisation
18.
SEMICONDUCTOR DEVICE AND OPERATING METHOD OF SEMICONDUCTOR DEVICE CAPABLE OF REDUCING DATA ERROR RATE
A semiconductor device may include a control circuit generating a current direction control signal, a row address signal, and a column address signal, a current direction control circuit selectively providing first and second bias voltages to row and column voltage lines, a row decoder selecting at least one of word lines and driving the selected word line to a voltage level of the row voltage line, a column decoder selecting at least one of bit lines and driving the selected bit line to a voltage level of the column voltage line, a memory cell array including a plurality of memory cells at intersecting locations of the word lines and the bit lines, and a data output circuit detecting data stored in selected memory cells after the start of a read operation and detecting and correcting an error of the detected data.
G11C 29/52 - Protection du contenu des mémoires; Détection d'erreurs dans le contenu des mémoires
G11C 7/12 - Circuits de commande de lignes de bits, p.ex. circuits d'attaque, de puissance, de tirage vers le haut, d'abaissement, circuits de précharge, circuits d'égalisation, pour lignes de bits
G11C 7/22 - Circuits de synchronisation ou d'horloge pour la lecture-écriture [R-W]; Générateurs ou gestion de signaux de commande pour la lecture-écriture [R-W]
19.
STORAGE DEVICE INCLUDING STORAGE CONTROLLER PROCESSING COMMAND IN WHICH SEPARATE COMMANDS ARE MERGED AND OPERATING METHOD THEREOF
A storage device includes: a non-volatile memory device; and a storage controller for receiving a first Protocol Information unit (PIU) including a first merge message from an external device, and performing, based on the first PIU, at least one of a sense operation of reading first data stored in a memory block of the non-volatile memory device and a select operation of storing, in the memory block, second data received from the external device. The first PIU includes a basic header segment commonly included in PIUs transmitted/received between the external device and the storage controller, and a first Extra Header Segment (EHS) including the first merge message.
An image sensing device is provided to include first to third light subpixels configured to include first to third photoelectric conversion elements, respectively, each of the first to third photoelectric conversion elements configured to generate photocharges indicative of incident light received by each photoelectric conversion element; a first storage subpixel including a first storage element configured to store overflown photocharges that correspond to an excess of photocharges that are generated to exceed predetermined capacities of the first to third photoelectric conversion elements; and each of first to third path transistors electrically connected between the first storage element and each of the first to third photoelectric conversion elements, respectively, wherein the first to third light subpixels and the first storage subpixel are arranged in a (2×2) matrix to form a first pixel.
H04N 25/771 - Circuits de pixels, p.ex. mémoires, convertisseurs A/N, amplificateurs de pixels, circuits communs ou composants communs comprenant des moyens de stockage autres que la diffusion flottante
Provided herein is a memory device for driving charge pumps respectively included in memory dies. The memory device includes a first memory die including a first charge pump and a first pump control circuit, and a second memory die including a second charge pump coupled to the first charge pump through a pump line and a second pump control circuit coupled to the first pump control circuit through a control line. The first pump control circuit is configured to control the first charge pump to perform a pump operation of generating a pump voltage in response to a command received by the first memory die, and output an operation alarm signal through the control line, and the second pump control circuit is configured to control the second charge pump to perform the pump operation in response to the operation alarm signal.
There are provided a semiconductor memory device and a manufacturing method of the semiconductor memory device. A semiconductor memory device includes a lower stack structure on the substrate and including a plurality of lower layers stacked in a vertical direction, an intermediate stack structure on the lower stack structure and including a plurality of intermediate layers stacked in the vertical direction, a plurality of grooves in the contact region and penetrating the intermediate stack structure, the plurality of grooves exposing the lower stack structure at different depths, and a plurality of steps formed along sidewalls of the grooves.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/528 - Configuration de la structure d'interconnexion
H10B 41/10 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la configuration vue du dessus
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
H10B 41/35 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire avec un transistor de sélection de cellules, p.ex. NON-ET
H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p.ex. NON-ET
23.
MEMORY DEVICE AND MANUFACTURING METHOD OF THE MEMORY DEVICE
A memory device includes: a memory cell array including a plurality of cell plugs; a first slit isolating the memory cell array into a plurality of memory regions, the first slit extending in a first direction; and second slits penetrating the plurality of memory regions, the second slits being arranged to be spaced apart from each other in a second direction intersecting the first direction. Gate lines included in each of the plurality of memory regions may be isolated from each other by the first slit. Each gate line located in the same layer among the gate lines included in each of the plurality of memory regions may extend through a first connection region between the second slits for each corresponding memory region.
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p.ex. FAMOS
G11C 5/06 - Dispositions pour interconnecter électriquement des éléments d'emmagasinage
H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
24.
SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR MEMORY DEVICE
A semiconductor device includes: a substrate extending in a first direction and a second direction intersecting with the first direction; a plurality of input/output pads disposed at one side of the substrate; a first circuit adjacent to the input/output pads in the first direction; a second circuit disposed to be spaced farther apart from the input/output pads in the first direction than the first circuit; a first memory cell array overlapping the first circuit; a second memory cell array overlapping the second circuit; first metal source patterns overlapping the first memory cell array and being spaced apart from each other in the second direction; and a second metal source pattern overlapping the second memory cell array and formed to have a width wider than a width of each of the first metal source patterns in the second direction.
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs sous-groupes différents du même groupe principal des groupes , ou dans une seule sous-classe de ,
G11C 16/08 - Circuits d'adressage; Décodeurs; Circuits de commande de lignes de mots
G11C 16/24 - Circuits de commande de lignes de bits
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H10B 41/10 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la configuration vue du dessus
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
H10B 41/35 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire avec un transistor de sélection de cellules, p.ex. NON-ET
H10B 41/41 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région de circuit périphérique de régions de mémoire comprenant un transistor de sélection de cellules, p.ex. NON-ET
H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p.ex. NON-ET
H10B 43/40 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région de circuit périphérique
25.
MEMORY CONTROLLER, STORAGE DEVICE, AND OPERATING METHOD OF STORAGE DEVICE
A memory controller includes: a host interface configured to receive, from a host, a diagnostic command for requesting performance of a self-test operation; and a processor configured to perform the self-test operation on a memory device, and generate a response corresponding to the diagnostic command, wherein the host interface is configured to transmit, to the host, the response including: a basic header segment commonly included in protocol information units transmitted/received between the memory controller and the host; and an extra header segment including result information indicating a result of the self-test operation.
A semiconductor device includes a plurality of memory cells. Each memory cell includes: a memory layer configured to store data; and a selector layer configured to control an access to the memory layer, wherein the selector layer includes a layer which includes an insulating material and a porous material that are mixed, and a dopant that is present in the layer and breaks a bond between constituent elements of the insulating material.
A semiconductor system including: an operation period adjusting circuit configured to generate operation information for adjusting an operation period, when an input count of an active command during a test mode period is equal to or more than a preset count; and a command generation circuit configured to adjust the input count of the active command applied to a semiconductor device during a preset period, by adjusting the operation period on the basis of the operation information.
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
G11C 29/36 - Dispositifs de génération de données, p.ex. inverseurs de données
28.
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF A SEMICONDUCTOR DEVICE
A semiconductor device may include: a first gate structure including first gate lines, a first step structure including first pads, a first gap-fill insulating layer located between the first gate lines and the first step structure, and first wiring lines connecting the first gate lines and the first pads, respectively; and a second gate structure including second gate lines located on the first gate lines, a second step structure located on the first gap-fill insulating layer and including second pads, a second gap-fill insulating layer located on the first step structure, and second wiring lines connecting the second gate lines and the second pads, respectively.
G11C 5/06 - Dispositions pour interconnecter électriquement des éléments d'emmagasinage
G11C 16/08 - Circuits d'adressage; Décodeurs; Circuits de commande de lignes de mots
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
H10B 41/40 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région de circuit périphérique
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
H10B 43/40 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région de circuit périphérique
A memory may include: a cell array including a plurality of memory cells; a line control circuit configured to apply a read voltage to a selected memory cell among the plurality of memory cells; and a sense amplifier configured to determine data of the selected memory cell, wherein a length of an interval between a time point when the read voltage is applied to the selected memory cell and a time point when the sense amplifier is activated is adjusted according to an elapsed time since a write operation is performed on the selected memory cell.
A page buffer circuit of a memory device includes a sensing circuit configured to sense a voltage level of a sensing node changed according to a state of a bit line during a sensing operation. The page buffer circuit also includes a clamping circuit connected to the sensing node, wherein the claiming circuit is configured to control the voltage level of the sensing node not to drop below a clamping level in a predetermined period of the sensing operation.
Provided herein may be a semiconductor device and a method of manufacturing the same. The semiconductor device may include a gate stacked structure including insulating layers and conductive layers that are alternatingly stacked, a hole extending in a vertical direction into the gate stacked structure, and including a first sidewall and a second sidewall facing each other, a first separation pattern and a second separation pattern that contact a boundary portion between the first sidewall and the second sidewall, the first and second separation patterns facing each other and extending in the vertical direction, a first plug pattern contacting the first sidewall and extending in the vertical direction, and a second plug pattern contacting the second sidewall and extending in the vertical direction.
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
H01L 21/28 - Fabrication des électrodes sur les corps semi-conducteurs par emploi de procédés ou d'appareils non couverts par les groupes
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
32.
VOLTAGE GENERATION CIRCUIT AND SEMICONDUCTOR DEVICE USING THE SAME
A voltage generation circuit includes a global driver, a local driver, and a local voltage converter. The global driver changes the voltage level of a second voltage line based on the voltage levels of a first boundary voltage and a first voltage line and changes the voltage level of a fourth voltage line based on the voltage levels of a second boundary voltage and a third voltage line. The local driver adjusts the voltage levels of the first and third voltage lines based on the voltage levels of the second and fourth voltage lines. The local voltage converter generates an internal voltage having a voltage level between the voltage levels of the first and third voltage lines.
G05F 1/46 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu
G05F 3/16 - Régulation de la tension ou du courant là où la tension ou le courant sont continus utilisant des dispositifs non commandés à caractéristiques non linéaires consistant en des dispositifs à semi-conducteurs
A semiconductor device includes: a substrate including a peripheral region and a core region; a substrate including a peripheral region and a core region; a first conductive pattern disposed over the substrate of the peripheral region; a second conductive pattern disposed over the substrate of the core region; a first spacer structure formed on both sidewalls of the first conductive pattern; and a second spacer structure having a thickness which is smaller than a total thickness of the first spacer structure formed on both sidewalls of the second conductive pattern.
A semiconductor chip includes a detection circuit configured to generate a discharge signal that is enabled when a voltage level of an external voltage is greater than a first set level and configured to generate a voltage control signal that is enabled when an output voltage is generated to have a voltage level of a ground voltage in a test mode, a charge discharge circuit configured to discharge charges of an output node that is included in a driving circuit when the discharge signal is enabled, and the driving circuit configured to generate the output voltage the voltage level of which rises up to a second set level by supplying charges from the external voltage to the output node in response to a driving signal a voltage level of which is decreased during an interval in which the voltage control signal is enabled.
G11C 7/20 - Circuits d'initialisation de cellules de mémoire, p.ex. à la mise sous ou hors tension, effacement de mémoire, mémoire d'image latente
G01R 19/175 - Indications des instants de passage du courant ou de la tension par une valeur déterminée, p.ex. de passage par zéro
G11C 7/22 - Circuits de synchronisation ou d'horloge pour la lecture-écriture [R-W]; Générateurs ou gestion de signaux de commande pour la lecture-écriture [R-W]
G11C 11/4072 - Circuits pour l'initialisation, pour la mise sous ou hors tension, pour l'effacement de la mémoire ou pour le préréglage
35.
MEMORY MODULE, MEMORY SYSTEM INCLUDING MEMORY MODULE, AND METHOD OF OPERATING THE SAME
The present technology relates to an electronic device. According to the present technology, a memory system includes a first memory module communicating with a host through a first interface and a second memory module communicating with the host through a second interface and having a tier lower than that of the first memory module. The first memory module comprises a memory device and a memory controller. The memory device may store cache data. The memory controller may store access pattern information of the host for the memory device, select candidate data to be evicted among the cache data based on the access pattern information of the host and a plurality of algorithms, and evict target data among the candidate data.
G06F 12/0891 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p.ex. mémoires cache utilisant des moyens d’effacement, d’invalidation ou de réinitialisation
G06F 12/126 - Commande de remplacement utilisant des algorithmes de remplacement avec maniement spécial des données, p.ex. priorité des données ou des instructions, erreurs de maniement ou repérage
G06F 13/42 - Protocole de transfert pour bus, p.ex. liaison; Synchronisation
36.
MEMORY MODULE, MEMORY SYSTEM INCLUDING MEMORY MODULE, AND METHOD OF OPERATING THE SAME
The present technology relates to an electronic device. According to the present technology, a memory system includes a host, a first memory module communicating with the host through a first interface and a second memory module communicating with the host through a second interface. The host comprises a prefetch table storage and a map manager. The prefetch table storage may store a prefetch table indicating candidate data to be prefetched to the first memory module among data stored in the second memory module. The map manager may prefetch target data from the second memory module to the first memory module according to whether the target data is included in the candidate data when the target data requested by the host is cache-missed in the first memory module and is cache-hit in the second memory module.
G06F 12/0862 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p.ex. mémoires cache avec pré-lecture
The present technology relates to an electronic device. According to the present technology, a memory module communicating with a host through a compute express link (CXL) interface includes a non-volatile memory device, a volatile memory device and a memory controller. The non-volatile memory device may store data. The memory controller may select candidate data to be prefetched among the data based on access pattern information of the host for the data and a plurality of algorithms, and prefetch target data among the candidate data to the volatile memory device.
G06F 12/0862 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p.ex. mémoires cache avec pré-lecture
A semiconductor device may include: a plurality of word lines; a select line; a channel layer extending into the select line through the word lines; a floating gate surrounding sidewalls of the channel layer between the channel layer and the select line; and a charge trap layer including a first and a second portion, wherein the first portion surrounds the sidewalls of the channel layer between the channel layer and the word lines and the second portion surrounds the floating gate between the channel layer and the select line.
H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p.ex. NON-ET
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
H10B 41/35 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire avec un transistor de sélection de cellules, p.ex. NON-ET
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
39.
SEMICONDUCTOR MODULE FOR PERFORMING ERROR CORRECTION OPERATION
A semiconductor module includes an address control circuit configured to generate an internal address based on an address in a first read operation and a second read operation that are sequentially performed and configured to generate multiple decoding enable signals and an error information enable signal, a memory circuit including multiple mats and configured to output internal data based on the internal address and the multiple decoding enable signals in the first read operation and configured to output internal meta data and second internal parities based on the internal address and the multiple decoding enable signals in the second read operation, and an error information storage circuit configured to output first internal parities based on the internal address and the error information enable signal in the first read operation.
G11C 11/4093 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p.ex. mémoires tampon de données
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
A data storage device may include a memory device divided into a plurality of logical units, and a controller configured to generate a first read command sequence and a second read command sequence for a first logical unit and a second logical unit, respectively, among the plurality of logical units, in response to an external command and configured to continuously output the first and second read command sequences to the memory device.
A memory device includes a control signal generation circuit configured to generate a control signal at a voltage level corresponding to a current temperature in each operation period, among a plurality of operation periods, of a program operation, and a bit line control circuit configured to charge a bit line in response to the control signal.
G11C 16/10 - Circuits de programmation ou d'entrée de données
G11C 7/04 - Dispositions pour écrire une information ou pour lire une information dans une mémoire numérique avec des moyens d'éviter les effets perturbateurs thermiques
G11C 16/24 - Circuits de commande de lignes de bits
G11C 16/26 - Circuits de détection ou de lecture; Circuits de sortie de données
42.
STORAGE DEVICE THAT EXECUTES MIGRATING DATA AND OPERATING METHOD OF THE STORAGE DEVICE
A storage device may execute an operation of migrating valid data stored in one or more source data sections of a plurality of data sections to one or more destination data sections of the plurality of data sections in response to a request from an external device. When the valid data is migrated from the source data sections to the destination data sections, the storage device may execute an operation of writing meta data for the migrated valid data.
Korea Advanced Institute of Science and Technology (République de Corée)
Inventeur(s)
Lee, Changyeop
Ryu, Seung-Tak
Cheon, Junho
Abrégé
A voltage-to-time converter (VTC) circuit includes an input capacitor being charged according to an input voltage during a precharge operation; an output capacitor being charged during the precharge operation; a first transistor configured to discharge the output capacitor according to a voltage charged in the input capacitor during a first operation following the precharge operation; and a second transistor configured to charge the output capacitor according to the voltage charged in the input capacitor during a second operation following the first operation.
A semiconductor device includes: first to fourth word lines alternately arranged with first to third bit lines in a vertical direction; first to sixth memory cells disposed between the first word line and the first bit line, between the first bit line and the second word line, between the second word line and the second bit line, between the second bit line and the third word line, between the third word line and the third bit line, and between the third bit line and the fourth word line, respectively; first and second word line contacts respectively connecting the first and second word lines to the substrate; third and fourth word line contacts respectively connecting the third and fourth word lines to the first and second word lines; and first to third bit line contacts respectively connecting the first to third bit lines to the substrate.
The present technology relates to an electronic device. According to an embodiment of the present disclosure, a memory device may include a plurality of memory cells connected to each word line, a peripheral circuit configured to perform a program operation on memory cells that are connected to a selected word line, and a control logic configured to control the peripheral circuit to perform the program operation on the memory cells that are connected to the selected word line after performing a pre-program operation that increases a threshold voltage of over-erasure cells, among memory cells that are connected to an adjacent word line, having a threshold voltage of an over-erasure state that is lower than a threshold voltage of an erasure state, to the threshold voltage of the erasure state, wherein the adjacent word line is a word line that is next to the selected word line.
G11C 16/34 - Détermination de l'état de programmation, p.ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p.ex. FAMOS
G11C 16/08 - Circuits d'adressage; Décodeurs; Circuits de commande de lignes de mots
G11C 16/10 - Circuits de programmation ou d'entrée de données
46.
MEMORY CONTROLLER, MEMORY SYSTEM, AND OPERATING METHOD THEREOF
A memory controller includes a cache memory, a host control circuit, and a flash translation layer. The host control circuit receives a read command and a logical address from a host, reads out mapping information corresponding to the logical address from a buffer memory device, and caches the mapping information in the cache memory. The flash translation layer reads a physical address corresponding to the logical address from the mapping information cached in the cache memory.
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p.ex. contrôle de parité, exclusion des 9 ou des 11
A memory system may wait to receive one or more read commands from a reference time point, and read data, requested by the one or more read commands, from the memory device in response to a determination that it is possible to simultaneously read data divided and stored, as an M number of data units, in an M number of planes among a plurality of planes in response to the one or more read commands or that a maximum read wait time has elapsed from the reference time point, M being a natural number.
A memory system and method for data reclaim which reads data from a memory using a preset voltage threshold based on a page type being read; records an initial set of program voltages for successful reads of the data from the memory; determines an initial distribution of the initial set of program voltages, over time subsequent sets of the program voltages for successful reads of the data from the memory; determines subsequent distributions of the subsequent sets of the program voltages; and based on program voltage variations of the subsequent distributions from the initial deviation, recycles the data in the memory.
G11C 16/12 - Circuits de commutation de la tension de programmation
G11C 11/56 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments d'emmagasinage comportant plus de deux états stables représentés par des échelons, p.ex. de tension, de courant, de phase, de fréquence
A semiconductor device may include a first semiconductor structure including a gate structure and a stack, the gate structure including channel structures and the stack including a capacitor, and a second semiconductor structure that is bonded to the first semiconductor structure, the second semiconductor structure including a peripheral circuit. The capacitor may include conductive layers and dielectric layers that are alternately stacked along an internal surface of a trench that is formed within the stack.
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/528 - Configuration de la structure d'interconnexion
H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
H10B 43/40 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région de circuit périphérique
H10B 99/00 - Matière non prévue dans les autres groupes de la présente sous-classe
51.
STORAGE DEVICE MIGRATING USER DATA STORED IN MEMORY DIE IN AN UNUSABLE STATE
A storage device may group a plurality of memory dies into M memory die groups, and migrate, when a first memory die in a first memory die group among the M memory die groups is determined to be in an unusable state, user data stored in user data blocks of the first memory die to a first overprovisioning block group. The first overprovisioning block group may include overprovisioning blocks of memory dies other than the first memory die among the memory dies in the first memory die group.
A storage device may execute a read retry operation on a plurality of memory cells when a failure occurs during a read operation on the plurality of memory cells. The storage device may perform the read retry operation based on M history read biases, and determine a first sequence in which the M history read biases are applied when the read retry operation is performed, based on a read retry sequence key.
Proposed is a method of operating a memory controller, the method including receiving a program command from a host, computing the minimum number of dies in which write data is programmable in response to the program command, determining whether or not the write data is programmable in the dies corresponding to the computed minimum number, on the basis of a size of a data stored in a FTL write queue, and determining whether or not dummy data is additionally necessary to the data stored in the FTL write queue, on the basis of a result of the determining of whether or not the write data is programmable.
In an embodiment of the disclosed technology, a semiconductor system may include a substrate; a first memory chip supported by the substrate, wherein the first memory chip includes a first main pad structured to be electrically connected to an interconnection structure disposed outside the first memory chip and a first sub pad electrically connected to the first main pad; and one or more second memory chips supported by the substrate, wherein each of the one or more second memory chips includes a second main pad structured to be electrically connected to an interconnection structure disposed outside the first memory chip and a second sub pad electrically connected to the second main pad, and the second main pad or the second sub pad included in one second memory chip of the one or more second memory chips is electrically connected to the first sub pad by a first internal interconnection structure.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
55.
MEMORY DEVICE AND METHOD OF MANUFACTURING THE MEMORY DEVICE
The present technology includes a memory device and a method of manufacturing the memory device. The memory device includes source contacts passing through a stack structure stacked on a source line, first supports passing through the stack structure between the source contacts, second supports passing through the stack structure between the first supports and the source contacts, and an auxiliary pattern passing through a portion of the stack structure between the first supports. The source contacts, and the first and second supports contact the source line, and the auxiliary pattern is spaced apart from the source line.
H10B 41/35 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire avec un transistor de sélection de cellules, p.ex. NON-ET
In an embodiment of the disclosed technology, a controller of a host device may manage data stored in a storage device, on the basis of a section which corresponds to a super block of the storage device and includes at least two segments. It is possible to provide measures enabling limited overwrite of a full section including a valid segment and allowing allocation and garbage collection to be performed by the unit of segment, thereby efficiently using a storage space while maintaining a log structure file system of the storage device.
A method of operating a memory device includes applying a first erase voltage to a source line in an erase operation of a memory block connected between the source line and bit lines. The method also includes decreasing a voltage of the source line to which the first erase voltage is applied to a second erase voltage and then increasing a voltage of the source line to which the second erase voltage is applied to a third erase voltage. The magnitude of the second erase voltage is between the magnitudes of the first and third erase voltages.
According to an embodiment of the present technology, a storage device includes a non-volatile memory device including a first memory block area and a second memory block area, and a storage controller configured to control the non-volatile memory device, determine a target erase count based on a generated assignment request among a first assignment request and a second assignment request, and assign a target memory block corresponding to the target erase count, as a memory block corresponding to the generated assignment request, to a shared block pool. The first assignment request corresponds to a memory block of a first type in the first memory block area, the second assignment request corresponds to a memory block of a second type in the first memory block area, and the target memory block is included in the first memory block area.
In a method of manufacturing a semiconductor device a substrate having a cell region and a peripheral region is prepared. A first cell-periphery structure including a conductive layer is formed over a surface of the substrate. In the cell region, a cell bit line trench is formed by patterning the first cell-periphery structure. A second cell-periphery structure including a second conductive layer is formed over the surface of the substrate. The second cell-periphery structure forms a cell bit line structure filling the cell bit line trench in the cell region, and is disposed over the first cell-periphery structure in the peripheral region. A periphery gate structure is formed by patterning the first and second cell-periphery structures in the peripheral region.
An image sensing device includes a plurality of unit pixels formed to generate pixel signals corresponding to incident light through photoelectric conversion of the incident light. Each of the unit pixels includes a well tap region configured to apply a bias voltage to a well region of a substrate, a first sub-pixel located at a first side of the well tap region and configured to include a first photoelectric conversion region, a first pixel transistor, a first floating diffusion region, and a first transfer gate, and a second sub-pixel located at a second side of the well tap region that is opposite to the first side of the well tap region and configured to include a second photoelectric conversion region, a second pixel transistor, a second floating diffusion region, and a second transfer gate.
A clock generation circuit includes a reference voltage generator configured to generate a first current having a current value inversely proportional to a reference voltage and a temperature, a bias circuit configured to generate a bias current, a second current having a current value proportional to the temperature, and a third current based on the reference voltage, a voltage generator configured to generate a supply voltage based on the first current, the bias current, and the second current, and an oscillation circuit configured to generate a clock signal having a constant frequency based on the supply voltage and the third current, wherein the supply voltage is generated to have a slope based on a ratio of the first current to the second current.
H03K 3/011 - Modifications du générateur pour compenser les variations de valeurs physiques, p.ex. tension, température
H03K 5/24 - Circuits présentant plusieurs entrées et une sortie pour comparer des impulsions ou des trains d'impulsions entre eux en ce qui concerne certaines caractéristiques du signal d'entrée, p.ex. la pente, l'intégrale la caractéristique étant l'amplitude
H03K 17/687 - Commutation ou ouverture de porte électronique, c. à d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs les dispositifs étant des transistors à effet de champ
A memory may include a data transmission/reception circuit and a memory bank including a plurality of cell arrays. When a metadata mode is activated, data and metadata received through the data transmission/reception circuit may be distributed to and stored in the plurality of cell arrays. When the metadata mode is deactivated, the data received through the data transmission/reception circuit may be distributed to and stored in cell arrays except one or more no-access cell arrays, among the plurality of cell arrays.
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p.ex. contrôle de parité, exclusion des 9 ou des 11
An image sensing device includes a plurality of unit pixels. Each of the plurality of unit pixels includes a photoelectric conversion region formed in a substrate and configured to generate photocharges from incident light, a control region located on one surface of the substrate and configured to correspond to each of the plurality of unit pixels, a detection region configured to capture the photocharges moving by a hole current, an isolation region configured to surround the photoelectric conversion region, and a passivation region disposed on the other surface opposite to the one surface of the substrate, wherein the hole current flows between the control region and the passivation region.
A memory device including a plurality of memory cells, a peripheral circuit configured to perform a read operation of reading data from memory cells connected to a selected word line, and a read operation controller configured to apply a plurality of read voltages to the selected word line, apply a first pass voltage to unselected word lines while first read voltages for determining a program state of memory cells having a threshold voltage higher than a reference voltage among the plurality of read voltages are applied to the selected word line, and apply a second pass voltage higher than the first pass voltage to the unselected word line while second read voltages for determining a program state of memory cells having a threshold voltage lower than the reference voltage among the plurality of read voltages are applied to the selected word line.
G11C 16/10 - Circuits de programmation ou d'entrée de données
G11C 16/08 - Circuits d'adressage; Décodeurs; Circuits de commande de lignes de mots
G11C 16/28 - Circuits de détection ou de lecture; Circuits de sortie de données utilisant des cellules de détection différentielle ou des cellules de référence, p.ex. des cellules factices
G11C 16/34 - Détermination de l'état de programmation, p.ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
65.
SEMICONDUCTOR DEVICE INCLUDING INTERLAYER INSULATION STRUCTURE INCLUDING METAL-ORGANIC FRAMEWORK
A semiconductor device according to an embodiment of the present disclosure includes a substrate, a gate structure disposed over the substrate, a dielectric structure disposed to contact a sidewall surface of the gate structure over the substrate, and a channel layer disposed on a sidewall surface of the dielectric structure over the substrate. The gate structure includes a gate electrode layer and an interlayer insulation structure which are alternately stacked. The interlayer insulation structure includes a metal-organic framework layer.
H10B 51/20 - Dispositifs de RAM ferro-électrique [FeRAM] comprenant des transistors ferro-électriques de mémoire caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
An adder circuit includes a negative number processing circuit configured to receive mantissa data and sign data of a plurality of floating point data and configured to output selected mantissa data, and an adder tree configured to perform an addition operation on the selected mantissa data to generate mantissa addition data. The negative number processing circuit is configured to output mantissa data of floating point data having a positive sign as the selected mantissa data, and to output an inverted mantissa data in which values of mantissa data of the floating point data having a negative sign are inverted as the selected mantissa data. And the adder tree is configured to perform the addition operation on the selected mantissa data with a number of “+1” operations equal to the number of the inverted mantissa data output from the negative number processing circuit.
A semiconductor device may include: first semiconductor structure including a page buffer, a first peripheral circuit, a bit line located on the page buffer, a stack located on the bit line and the stack including a) a step structure, b) a source structure located on the stack, and channel structures extending through the stack; and a second semiconductor structure bonded to the first semiconductor structure and the second semiconductor structure including a) a second peripheral circuit located to face the source structure and b) pass transistors located to face the step structure.
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs sous-groupes différents du même groupe principal des groupes , ou dans une seule sous-classe de ,
68.
SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SYSTEM RELATED TO ROW HAMMER REFRESH
A semiconductor device includes an interval control circuit configured to generate a detection interval signal by detecting that an internal address, which is input right before a pulse of a row hammer command signal is generated, is sampled as a target address, a signal correction circuit configured to generate a correction random signal adjust the internal address so that the internal address is sampled as the target address less than or equal to a preset number of times between consecutive pulses of the row hammer command signal during a designation interval and a detection interval in which the detection interval signal is activated, and a row hammer refresh circuit configured to execute a row hammer refresh based on the target address that is generated in response to the correction random signal.
A semiconductor device may include: a first semiconductor structure including a stack including an inverted step structure, a source structure located below the stack, a bit line located above the stack, and channel structures extending through the stack; a second semiconductor structure bonded to the first semiconductor structure and including pass transistors located to face the inverted step structure and a first peripheral circuit located to face the source structure; and a third semiconductor structure bonded to the first semiconductor structure and including a page buffer located to face the bit line and a second peripheral circuit located to face the inverted step structure.
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs sous-groupes différents du même groupe principal des groupes , ou dans une seule sous-classe de ,
70.
PAGE BUFFER CIRCUIT AND READ OPERATION METHOD OF MEMORY
Disclosed is a read operation method of a memory, and the read operation method may include evaluating a sensing node according to a voltage level of a bit line, sensing a voltage level of the sensing node after a first time elapses from a start of the evaluation, and sensing the voltage level of the sensing node after a second time longer than the first time elapses from the start of the evaluation.
G11C 16/34 - Détermination de l'état de programmation, p.ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p.ex. circuits de commande E/S de données, mémoires tampon de données E/S
G11C 16/08 - Circuits d'adressage; Décodeurs; Circuits de commande de lignes de mots
G11C 16/26 - Circuits de détection ou de lecture; Circuits de sortie de données
71.
SEMICONDUCTOR DEVICE AND OPERATING METHOD OF THE SAME
A semiconductor device may include a memory cell that is connected to a word line and a bit line, a line driving circuit configured to apply to the word line, a program pulse that is enabled to a level of a program voltage and a control circuit configured to control the line driving circuit to: repeatedly apply the program pulse to the word line until a level of a threshold voltage of the memory cell becomes higher than a target level, and adjust, during the repeatedly applying, a level of the program voltage based on a difference between the target level and the level of the threshold voltage.
G11C 16/10 - Circuits de programmation ou d'entrée de données
G11C 16/12 - Circuits de commutation de la tension de programmation
G11C 16/14 - Circuits pour effacer électriquement, p.ex. circuits de commutation de la tension d'effacement
G11C 16/34 - Détermination de l'état de programmation, p.ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
A memory device includes strings and a peripheral circuit. The strings are connected between a bit line and a source line. The peripheral circuit is configured to perform an erase operation on a first string among the strings by applying an erase voltage to at least one of the bit line and the source line and configured to control a second string among the strings to be prohibited from being erased during the erase operation.
G11C 16/16 - Circuits pour effacer électriquement, p.ex. circuits de commutation de la tension d'effacement pour effacer des blocs, p.ex. des réseaux, des mots, des groupes
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p.ex. FAMOS
G11C 16/34 - Détermination de l'état de programmation, p.ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
73.
SEMICONDUCTOR DEVICE AND STACK TYPE SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME
A semiconductor memory device includes a core block including a plurality of unit memory blocks, a peripheral circuit block including a data input/output pad, a through electrode configured to exchange signals with another semiconductor memory device, and a data input/output circuit coupled to the through electrode, the core block, and the peripheral circuit block and configured to share one receiver in order to transmit a signal from the through electrode to the peripheral circuit block and in order to transmit a signal from the through electrode to the core block.
G11C 5/06 - Dispositions pour interconnecter électriquement des éléments d'emmagasinage
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs sous-groupes différents du même groupe principal des groupes , ou dans une seule sous-classe de ,
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
74.
PAGE BUFFER, SEMICONDUCTOR DEVICE INCLUDING PAGE BUFFER, AND OPERATING METHOD OF SEMICONDUCTOR DEVICE
A page buffer may include a bit line connection circuit configured to connect or disconnect a bit line and a first node, a plurality of latch circuits that is connected to the first node in common. The page buffer may further include, and logical operation circuit configured to perform a logical operation by using one or more of a voltage level of the first node and a voltage level of a second node as an input and to set the voltage level of the first node responsive to results of the operational operation.
G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p.ex. circuits de commande E/S de données, mémoires tampon de données E/S
G11C 7/12 - Circuits de commande de lignes de bits, p.ex. circuits d'attaque, de puissance, de tirage vers le haut, d'abaissement, circuits de précharge, circuits d'égalisation, pour lignes de bits
G11C 8/08 - Circuits de commande de lignes de mots, p.ex. circuits d'attaque, de puissance, de tirage vers le haut, d'abaissement, circuits de précharge, pour lignes de mots
H03K 19/20 - Circuits logiques, c. à d. ayant au moins deux entrées agissant sur une sortie; Circuits d'inversion caractérisés par la fonction logique, p.ex. circuits ET, OU, NI, NON
A semiconductor device includes a trench formed in a substrate; a gate dielectric layer suitable for covering a bottom surface and sidewalls of the trench; a first gate electrode suitable for gap-filling a bottom portion of the trench over the gate dielectric layer; a second gate electrode formed over the first gate electrode; and an anti-oxidation layer disposed at an interface between the first gate electrode and the second gate electrode.
A memory system includes a controller configured to transmit a reset write command and reset write data, and transmit a set write command and set write data; and at least one memory device configured to generate seed data by performing a first operation on the reset write data and read data read out from a target memory area in response to the reset write command, generate write data by performing a second operation on the seed data and the set write data in response to the set write command, and write back the write data to the target memory area.
A memory device includes a first outer support structure extending along a first direction. The memory device also includes a first protrusion pattern extending along the first direction, the first protrusion pattern being in contact with an end of the first outer support structure. The memory device further includes a connection support structure spaced apart from the first protrusion pattern along a second direction perpendicular to the first direction. The memory device additionally includes a first oblique support structure connecting the connection support structure and the first outer support structure to each other in an oblique direction to the first and second directions.
A semiconductor package in which an auxiliary conductor is coupled to a trace pattern is presented. The semiconductor package includes a semiconductor die disposed over a package substrate including a trace pattern. The semiconductor package includes a first auxiliary conductor having a first end and a second end coupled to the trace pattern.
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
79.
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor integrated circuit device may include a target fine pattern and an adjacent fine pattern. The target fine pattern may have a first width, a first length and a first height. The first width may be gradually decreased toward a lower region. The first length may be gradually increased toward the lower region. The first height may be greater than the first width and the first length. The adjacent fine pattern may have contact with the target fine pattern along a lengthwise direction. The adjacent fine pattern may have a second width, a second length and the first height. The second width may be gradually decreased toward the lower region. The second length may be gradually decreased toward the lower region.
A memory module may include a management bus and a plurality of memories connected in series and connected to the management bus, each of the plurality of memories including an identification (ID) input terminal and an ID output terminal. Among the plurality of memories, a memory, for which an activation signal is applied to an ID input terminal of the memory, may set an ID for the memory in response to ID setting information transmitted on the management bus.
A semiconductor device may include a gate structure including conductive layers and insulating layers that are alternately stacked and including a stair structure for exposing at least one of the conductive layers, a contact plug that extends through the gate structure and that is electrically connected to a uppermost conductive layer that is exposed by the stair structure, and insulating spacers that are disposed between remaining conductive layers, among the conductive layers, and the contact plug. The insulating layers may each have a first thickness, and the insulating spacers may each have a second thickness smaller than the first thickness.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
82.
SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR MEMORY DEVICE
Provided herein is a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device includes a first gate stacked body including a plurality of interlayer insulating layers and a plurality of conductive patterns that are alternately stacked in a vertical direction, a second gate stacked body including a source select line and an insulating pattern that are sequentially formed on the first gate stacked body, and a channel structure extending into the first gate stacked body and the second gate stacked body in a vertical direction, and including a first end upwardly protruding higher than the second gate stacked body, wherein the source select line includes a plurality of conductive layers that are sequentially stacked.
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
H10B 41/35 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire avec un transistor de sélection de cellules, p.ex. NON-ET
H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p.ex. NON-ET
83.
IMAGE SENSING DEVICE AND METHOD FOR MANUFACTURING THE SAME
Disclosed are image sensing devices. In some implementations, an image sensing device may include a plurality of pixel arrays including first, second, and third pixel arrays, wherein each pixel array comprises a plurality of color filter, and the first pixel array includes a metal grid arranged along an edge of the first pixel array such that the metal grid is disposed between the plurality of color filters in the first pixel array and a plurality of color filters in another pixel array adjacent to the first pixel array, wherein the color filters in the first pixel array are blue color filters.
Sogang University Research and Business Development Foundation (République de Corée)
Inventeur(s)
Lee, Seungjin
Lee, Changgyu
Kim, Youngjae
Park, Inhyuk
Chung, Woo Suk
Abrégé
A key-value (KV) based data storage device includes a first memory, a second memory, a key buffer, and a controller. The first memory stores a first table, the second memory includes a Log-Structured Merge (LSM) tree area storing a plurality of second tables forming an LSM tree structure and a value log area storing a value corresponding to a key, and the key buffer stores one or more prefetched second tables corresponding to a key. The controller is configured to process a range query command by prefetching a second table adjacent to a previously-prefetched second table from the second memory and storing the second table in the key buffer when a number of unqueried keys in the previously-prefetched second table is smaller than a predetermined number. Processing the range query command may also include prefetching values from the value log area into a value buffer.
A semiconductor apparatus includes a Pseudo Random Binary Sequence (PRBS) generation circuit, a first data input and output circuit, and a second data input and output circuit. The PRBS generation circuit generates a PRBS signal and the first and second data input and output circuits receive in common the PRBS signal. The first data input and output circuit scrambles, based on a first scramble code, the PRBS signal to generate a first output data signal and the second data input and output circuit scrambles, based on a second scramble code having different value from the first scramble code, the PRBS signal to generate a second output data signal.
A semiconductor device includes a stacked structure including a first region in which conductive layers and the insulating layers are stacked alternately with each other, and a second region in which sacrificial layers and the insulating layers are stacked alternately with each other, a first slit structure located at a boundary between the first region and the second region and including a first through portion passing through the stacked structure and first protrusions extending from a sidewall of the first through portion, a second slit structure located at the boundary and including a second through portion passing through the stacked structure and second protrusions extending from a sidewall of the second through portion and coupled to the first protrusions, a circuit located under the stacked structure, and a contact plug passing through the second region of the stacked structure and electrically connected to the circuit.
H10B 43/20 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H10B 41/20 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur
H10B 41/40 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région de circuit périphérique
H10B 43/40 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région de circuit périphérique
87.
METHOD OF FORMING SEMICONDUCTOR DEVICE INCLUDING SEMICONDUCTOR LINER
A method for forming a semiconductor device may include forming, on a substrate, a trench which delimits a preliminary active region. A buffer layer may be formed on the preliminary active region using a first heat treatment process that is performed at 520° C. to 580° C. A sacrificial layer may be formed by replacing the buffer layer. An active region may be exposed by removing the sacrificial layer. A semiconductor liner may be formed on the active region.
H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
88.
KEY-VALUE BASED DATA STORAGE DEVICE AND OPERATION METHOD THEREOF
Sogang University Research and Business Development Foundation (République de Corée)
Inventeur(s)
Lee, Seungjin
Lee, Changgyu
Kim, Youngjae
Park, Inhyuk
Chung, Woo Suk
Abrégé
A key-value (KV) based data storage device configured to process one or more range query commands includes a first table, summary data, a Log-Structured merge (LSM) tree area storing a plurality of second tables forming an LSM tree structure, and a value log area storing a value corresponding to a key stored in the LSM tree structure. The summary data includes version data including a global version representing current states of the first table and the plurality of second tables. The KV based storage device adds a copy version of the global version in the version data when initiating processing of a range query command and refers to that copy version while processing that range query command.
A semiconductor device may include: a first gate structure including a plurality of first conductive layers that are alternately stacked with a plurality of first insulating layers; a second gate structure including a plurality of second conductive layers that are alternately stacked with a plurality of second insulating layers; a third gate structure including third conductive layers that are alternately stacked with a plurality of third insulating layers; and a first contact plug extending into the first gate structure through the third gate structure and the second gate structure, the first contact plug connected to a first of the plurality of first conductive layers, and the first contact plug including a first inflection portion located at an interface between the second gate structure and the third gate structure.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
H10B 63/00 - Dispositifs de mémoire par changement de résistance, p.ex. dispositifs RAM résistifs [ReRAM]
90.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device may comprise a plurality of conductive lines and a plurality of contact plugs. The plurality of conductive lines may include a first conductive line a second conductive line. The plurality of contact plugs may include a first contact plug and a second contact plug. The first contact plug may have a first pillar portion and a first protruding portion protruding from a sidewall of the first pillar portion at a first depth, so as to be in alignment and contact with a sidewall of the first conductive line. The second contact plug may have a second pillar portion and a second protruding portion protruding from a sidewall of the second pillar portion at a second depth, so as to be in alignment and contact with a sidewall of the second conductive line.
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
H10B 41/35 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire avec un transistor de sélection de cellules, p.ex. NON-ET
H10B 41/50 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région limite entre la région noyau et la région de circuit périphérique
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p.ex. NON-ET
91.
DATA RECEIVING CIRCUIT FOR CHIPLET BASED STORAGE ARCHITECTURES
A data receiving circuit includes a forwarded fast clock domain configured to output data transmitted from a data transmitting circuit in synchronization with a forwarded fast clock signal, and a local clock domain configured to generate a synchronized fetch enable signal in synchronization with a local fast clock signal and output the data transmitted from the forwarded fast clock domain in synchronization with a local slow clock.
G11C 7/22 - Circuits de synchronisation ou d'horloge pour la lecture-écriture [R-W]; Générateurs ou gestion de signaux de commande pour la lecture-écriture [R-W]
G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p.ex. circuits de commande E/S de données, mémoires tampon de données E/S
92.
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
A semiconductor device includes: a first electrode including a carbon layer; a second electrode; a variable resistance layer interposed between the first electrode and the second electrode; and a barrier layer interposed between the first electrode and the variable resistance layer, the barrier layer including nitrogen and carbon. A concentration of the nitrogen in the barrier layer is equal to or higher than that of the carbon in the barrier layer.
H10N 70/00 - Dispositifs à l’état solide sans barrière de potentiel ni de surface, spécialement adaptés au redressement, à l'amplification, à la production d'oscillations ou à la commutation
H10B 63/00 - Dispositifs de mémoire par changement de résistance, p.ex. dispositifs RAM résistifs [ReRAM]
H10N 70/20 - Dispositifs de commutation multistables, p.ex. memristors
93.
SEMICONDUCTOR MEMORY DEVICE AND A MANUFACTURING METHOD OF THE SEMICONDUCTOR MEMORY DEVICE
A semiconductor memory device, and a manufacturing method of the semiconductor memory device, includes: a bit line overlapping with a peripheral circuit layer; interlayer insulating layers and conductive patterns alternately stacked in a first direction on the bit line; vertical channels connected to the bit line, the vertical channels penetrating the interlayer insulating layers and the conductive patterns, the vertical channels protruding farther in the first direction than the stacked interlayer insulating layers and the conductive patterns; a connection pattern in contact with a portion of each of the vertical channels that protrudes farther in the first direction than the stacked interlayer insulating layers and the conductive patterns, the connection pattern connecting the vertical channels; a source channel in contact with the connection pattern, the source channel extending in the first direction; and a source select line surrounding the source channel.
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
G11C 7/18 - Organisation de lignes de bits; Disposition de lignes de bits
G11C 8/14 - Organisation de lignes de mots; Disposition de lignes de mots
H01L 23/528 - Configuration de la structure d'interconnexion
H10B 41/10 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la configuration vue du dessus
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
H10B 41/40 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région de circuit périphérique
H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
H10B 43/40 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région de circuit périphérique
94.
SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF
A semiconductor memory device includes a memory cell array circuit and a driving force adjustment circuit. The memory cell array circuit includes a plurality of memory cells. The driving force adjustment circuit adjusts driving forces of a plurality of respective verify pass voltages based on whether or not the plurality of memory cells are programmed.
G11C 16/34 - Détermination de l'état de programmation, p.ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p.ex. FAMOS
G11C 16/08 - Circuits d'adressage; Décodeurs; Circuits de commande de lignes de mots
G11C 16/10 - Circuits de programmation ou d'entrée de données
G11C 16/14 - Circuits pour effacer électriquement, p.ex. circuits de commutation de la tension d'effacement
G11C 16/26 - Circuits de détection ou de lecture; Circuits de sortie de données
An electronic device includes a synthetic voltage generation circuit configured to generate a synthetic voltage by synthesizing a supply voltage a voltage level of which is changed in response to a change in a voltage level of a first external voltage and an upper limit reference voltage a voltage level of which is set in response to a first selection signal and a second selection signal that are generated by detecting a process, voltage, and temperature (PVT) variation, and an internal voltage generation circuit configured to, based on the synthetic voltage, generate an internal voltage that is used as a body voltage of a transistor included in an internal circuit.
H02M 1/00 - APPAREILS POUR LA TRANSFORMATION DE COURANT ALTERNATIF EN COURANT ALTERNATIF, DE COURANT ALTERNATIF EN COURANT CONTINU OU VICE VERSA OU DE COURANT CONTINU EN COURANT CONTINU ET EMPLOYÉS AVEC LES RÉSEAUX DE DISTRIBUTION D'ÉNERGIE OU DES SYSTÈMES D'ALI; TRANSFORMATION D'UNE PUISSANCE D'ENTRÉE EN COURANT CONTINU OU COURANT ALTERNATIF EN UNE PUISSANCE DE SORTIE DE CHOC; LEUR COMMANDE OU RÉGULATION - Détails d'appareils pour transformation
H02M 3/156 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs avec commande automatique de la tension ou du courant de sortie, p.ex. régulateurs à commutation
96.
IMAGE SENSOR, IMAGE PROCESSING SYSTEM INCLUDING THE IMAGE SENSOR AND OPERATING METHOD OF THE IMAGE PROCESSING SYSTEM
Disclosed is an image sensor, an image processing system including the image sensor, and an operating method of the image processing system, the image sensor including a first detection circuit configured to detect an eye region of a user from an information image obtained by capturing an image of the user, a first probability map generation circuit configured to generate a first probability map which corresponds to a direction in which the user's eyes gaze, based on the eye region, and a storage circuit configured to store the first probability map.
A memory system includes a plurality of memory devices; and a memory controller configured to perform an initial training operation to set a plurality of time codes corresponding to the plurality of memory devices, respectively, receive a plurality of data signals read from the plurality of memory devices, as internal data signals, according to the plurality of time codes, respectively, and adjust the plurality of time codes based on the internal data signals and error pattern maps generated by collecting error location information for the internal data signals.
G11C 29/52 - Protection du contenu des mémoires; Détection d'erreurs dans le contenu des mémoires
G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p.ex. circuits de commande E/S de données, mémoires tampon de données E/S
G11C 7/20 - Circuits d'initialisation de cellules de mémoire, p.ex. à la mise sous ou hors tension, effacement de mémoire, mémoire d'image latente
G11C 7/22 - Circuits de synchronisation ou d'horloge pour la lecture-écriture [R-W]; Générateurs ou gestion de signaux de commande pour la lecture-écriture [R-W]
A controller of a storage device includes a memory configured to serve as a lookahead cache; a read request storage configured to store therein read requests; and a cache manager configured to perform a bottleneck check operation when a process for a cache hit read request stored in the read request storage is completed, and selectively deactivate the lookahead cache based on a check result in bottleneck check operations.
The present technology provides an external data storage device comprising: a memory module including a plurality of semiconductor chips suitable for storing data received from an external device; a case including a plurality of surfaces surrounding the memory module; and a case stand suitable for supporting the case in an approximately vertical direction on a ground.
A method for manufacturing an electronic device includes forming a first source layer including a trench, forming a first sacrificial layer in the trench, forming a first structure over the first source layer, wherein the first structure includes first material layers and second material layers which are alternately stacked over the each other, forming first openings passing through the first structure and extending to the first sacrificial layer, forming first channel layers in the first openings, forming a slit passing through the first structure and extending to the first sacrificial layer, forming a second opening by removing the first sacrificial layer through the slit, and forming a second source layer in the second opening, wherein the second source layer is coupled to the first channel layers.
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p.ex. NON-ET
