A semiconductor memory device includes a first stack including lower conductive patterns separated from each other and stacked on a substrate to form a lower stepped structure, a support pillar passing through the first stack and including an insulating layer, a second stack including upper conductive patterns separated from each other and stacked on the first stack, the upper conductive patterns including an upper stepped structure that does not overlap with the lower stepped structure and the support pillar, a channel structure passing through the second stack and the first stack, and a memory layer surrounding a sidewall of the channel structure.
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
H01L 23/528 - Configuration de la structure d'interconnexion
G11C 5/02 - Disposition d'éléments d'emmagasinage, p.ex. sous la forme d'une matrice
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
H10B 41/50 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région limite entre la région noyau et la région de circuit périphérique
H10B 43/50 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région limite entre la région noyau et la région de circuit périphérique
2.
SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
A semiconductor device includes: a lateral layer spaced apart from a lower structure and extending in a direction parallel to the lower structure; a vertical conductive line extending in a direction perpendicular to the lower structure and coupled to a first-side end of the lateral layer; a data storage element coupled to a second-side end of the lateral layer; and a lateral conductive line extending in a direction crossing the lateral layer, wherein the lateral conductive line includes: a first work function electrode; a second work function electrode disposed adjacent to the vertical conductive line and having a lower work function than the first work function electrode; and a third work function electrode disposed adjacent to the data storage element and having a lower work function than the first work function electrode.
A memory device, and a method of operating the same, includes a plurality of memory cells coupled to a plurality of word lines, a peripheral circuit configured to perform a program operation of storing data in the plurality of memory cells, a weak word line information storage configured to store information about a weak word line among the plurality of word lines, and a program operation controller configured to control the peripheral circuit such that the program operation is performed in a first program mode or a second program mode depending on a result of determining whether a selected word line corresponding to an address provided from a memory controller is a weak word line by comparing word lines based on the information about the weak word line.
A delay circuit including a first output clock generation circuit and a second output clock generation circuit. The first output clock generation circuit generates a first output clock signal by mixing phases of a first clock signal and a second clock signal based on an (n+1)-th generated delay control signal. The second output clock generation circuit generates a second output clock signal by mixing the phases of the first and second clock signals based on both an n-th generated delay control signal and the (n+1)-th generated delay control signal.
H03L 7/081 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase avec un déphaseur commandé additionnel
H03L 7/085 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence y compris le filtrage ou l'amplification de son signal de sortie
5.
SIGNAL GENERATION CIRCUIT HAVING MINIMUM DELAY, SEMICONDUCTOR APPARATUS USING THE SAME, AND SIGNAL GENERATION METHOD
A signal generation circuit includes a first delay circuit, a second delay circuit, and a duty control circuit. The first delay circuit delays a first input signal to generate a first output signal. The second delay circuit delays a second input signal to generate a second output signal. The duty control circuit compares phases of the first and second output signals and changes the value of the second delay control signal, and then decreases the times, by which the first and second input signals are delayed, by the same value.
H03K 3/017 - Réglage de la largeur ou du rapport durée période des impulsions
H03L 7/081 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase avec un déphaseur commandé additionnel
Provided herein may be a memory device and a method of operating the same. The memory device may include a plurality of memory cells, a peripheral circuit configured to perform a verify operation that identifies threshold voltages of the plurality of memory cells by using a first verify voltage and a second verify voltage, and a program operation controller configured to control the peripheral circuit, after the verify operation is terminated and during a period in which a program voltage is applied to the plurality of memory cells, to apply a first control signal to a page buffer that is coupled to a first memory cell having a threshold voltage that is higher than the first verify voltage and lower than the second verify voltage, and apply a second control signal having a lower level voltage than the first control signal to the page buffer.
G11C 16/34 - Détermination de l'état de programmation, p.ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
G11C 16/24 - Circuits de commande de lignes de bits
G11C 16/10 - Circuits de programmation ou d'entrée de données
A method of manufacturing a semiconductor device is provided. The method may include forming a stack, forming a preliminary stepped structure by patterning the stack, forming a first stepped structure, a second stepped structure, and an opening located between the first stepped structure and the second stepped structure by etching the preliminary stepped structure, forming a passivation layer that fills the opening and covers the first stepped structure, and forming a third stepped structure by etching the second stepped structure using the passivation layer as an etching barrier.
A semiconductor memory device includes a memory cell array including memory cells, a peripheral circuit performing a read/verify operation of selected memory cells, and a control logic circuit controlling the read/verify operation of the peripheral circuit. The control logic circuit controls the peripheral circuit to apply a first voltage to a selected word line connected to the selected memory cells, float unselected word lines adjacent to the selected word line among unselected word lines, apply a first under-drive voltage lower than the first voltage to the selected word line during at least a partial period in which the unselected word lines adjacent to the selected word line are floated, and apply a second voltage higher than the first under-drive voltage and lower than the first voltage to the selected word line.
G11C 16/26 - Circuits de détection ou de lecture; Circuits de sortie de données
G11C 16/34 - Détermination de l'état de programmation, p.ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
G11C 16/08 - Circuits d'adressage; Décodeurs; Circuits de commande de lignes de mots
9.
MEMORY DEVICE AND MANUFACTURING METHOD OF THE MEMORY DEVICE
There are provided a memory device and a manufacturing method of the memory device. The memory device includes: a stack structure including gate lines stacked to be spaced apart from each other; main plugs arranged to be spaced apart from each other; plug isolation patterns isolating the main plugs into first and second sub-plugs; and a select isolation pattern isolating at least one gate line located between the plug isolation patterns adjacent to each other.
H01L 23/528 - Configuration de la structure d'interconnexion
H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
H10B 41/10 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la configuration vue du dessus
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
10.
Semiconductor memory device including write driver with power gating structures and operating method thereof
A semiconductor device includes a first circuit having a first power gating structure, a second circuit, and a third circuit having a second power gating structure that is different from the first power gating structure, and suitable for isolating the second circuit from the first circuit during a particular period.
H03K 17/693 - Dispositifs de commutation comportant plusieurs bornes d'entrée et de sortie, p.ex. multiplexeurs, distributeurs
11.
SEMICONDUCTOR MEMORY DEVICE AND CONTROLLER FOR READING DATA WITH IMPROVED SPEED, AND METHOD OF OPERATING THE SEMICONDUCTOR MEMORY DEVICE AND THE CONTROLLER
A semiconductor memory device includes a memory cell array, a peripheral circuit, and a control logic. The memory cell array includes a plurality of memory cells. The peripheral circuit performs a read operation on selected memory cells, among the plurality of memory cells. The control logic controls the read operation of the peripheral circuit in response to a read command that is received from an external device and determines whether to perform a discharge operation of word lines that are connected to the plurality of memory cells based on a type of the read command.
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
A memory device includes a memory cell array including a plurality of memory cells; a peripheral circuit configured to perform a recovery operation of applying a recovery voltage to the memory cells for increasing a residual polarization of the memory cells and configured to perform a normal operation of applying a driving voltage to the memory cells for reading data from the memory cells or writing data into the memory cells; and a control logic configured to control, when powered up, the peripheral circuit to perform the recovery operation and then perform the normal operation.
A semiconductor wafer includes at least one chip region disposed in a substrate, a first chip guard disposed over the substrate in a chip sealing region positioned outside the at least one chip region, a second chip guard disposed over the substrate in a scribe lane region positioned outside the chip sealing region, and a test circuit pattern disposed in the scribe lane region and including a ground line electrically connected to a ground well in the substrate. The second chip guard includes a ground wiring layer electrically connected to the ground line of the test circuit pattern.
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 21/66 - Test ou mesure durant la fabrication ou le traitement
H01L 23/58 - Dispositions électriques structurelles non prévues ailleurs pour dispositifs semi-conducteurs
An operation method of a memory may include receiving an active command and an active address; determining whether a row corresponding to the active address and a row corresponding to a target row address are able to be substantially simultaneously activated; activating the row corresponding to the active address; and activating the row corresponding to the target row address in response to determining that the row corresponding to the active address and the row corresponding to the target row address are able to be substantially simultaneously activated.
The present technology relates to a resistive memory device and a method of manufacturing the same. The resistive memory device includes a stack structure in which a plurality of interlayer insulating layers and a plurality of conductive layers are alternately stacked, a hole passing through the stack structure in a vertical direction, a gate insulating layer, a channel layer, and a variable resistance layer sequentially formed along a sidewall of the hole, and a high dielectric layer formed between the channel layer and the gate insulating layer, the high dielectric layer being adjacent to the plurality of interlayer insulating layers.
H01L 47/00 - Dispositifs à résistance négative à effet de volume, p.ex. dispositifs à effet Gunn; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives
16.
SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
Provided herein may be a semiconductor memory device and a method of manufacturing the same. The semiconductor memory device may include a gate stack, and a channel structure disposed in the gate stack, wherein the channel structure may include a channel layer including a first portion penetrating the gate stack and a second portion extending from the first portion to protrude higher than the gate stack, a core insulating layer disposed in a central region of the channel structure, and a barrier layer disposed between the channel layer and the core insulating layer.
Provided herein may be a test circuit of an electronic device, the electronic device including the test circuit, and an operating method thereof. The electronic device may include analog circuits, a control circuit configured to connect, to an output terminal, each of a plurality of nodes respectively included in the analog circuits to an output terminal, a control signal generator configured to generate a control signal for controlling the control circuit based on an input signal received from an external device, and a switching circuit disposed on an electrical path for connecting the plurality of nodes and the control circuit to each other and configured to be electrically open during a preset time amount from a time point at which a voltage from an external power source starts to be applied to the control circuit.
H03K 17/687 - Commutation ou ouverture de porte électronique, c. à d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs les dispositifs étant des transistors à effet de champ
A controller controls a semiconductor memory device including a plurality of pages. The controller includes a command generator configured to generate a command for controlling a program operation or a read operation of a semiconductor memory device, and a data recovery manager configured to generate parity data corresponding to a weak page among a plurality of pages included in the semiconductor memory device and recover data programmed to the weak page.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p.ex. contrôle de parité, exclusion des 9 ou des 11
A wafer test system includes a chuck for supporting a wafer including a plurality of dies, a probe head for inputting a test signal for an electrical test to the probe card and receiving an electrical test result corresponding to the test signal, a probe card for inputting test signals to the dies through a plurality of pins and receiving test result, a sensing device mounted on the surface of the probe card, for sensing an active state occurring in the wafer when the electrical test is performed, and a determination unit for receiving the electrical test result and the active state information for the dies and determining whether each of the dies has failed using the result of the electrical test on the wafer and active state information.
A memory controller includes a test controller, a test information storage, and a machine learning processor. The test controller performs a test on a memory device using a target pattern selected from among a plurality of test patterns in each of a plurality of test modes in which voltage and time conditions of test signals are set differently. The test information storage stores test result information including values associated with fail bits of the memory device measured in the test. The machine learning processor detects a defect acceleration mode in which a defect of the memory device is accelerated, among the plurality of test modes, in the test performed using the target pattern on the basis of the test result information.
The present technology relates to an electronic device. According to the present technology, a memory controller may include a latency monitor and an operation controller. The latency monitor may count an over-latency count value representing a number of over-latencies exceeding a reference value among latencies for requests from a host during each of a plurality of periods, calculate gaps which are difference values between the over-latency count values of the plurality of periods, and generate latency information including the over-latency count values and the gaps. The operation controller may determine, based on the latency info oration, whether each gap between at least two target periods among the plurality of periods exceeds a threshold value, and delay a response to the requests according to a determination result.
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
22.
DATA PROCESSING SYSTEM, OPERATING METHOD OF THE DATA PROCESSING SYSTEM, AND COMPUTING SYSTEM USING THE DATA PROCESSING SYSTEM AND OPERATING METHOD OF THE DATA PROCESSING SYSTEM
A data processing system may include a processing memory including a plurality of sub-arrays, and a controller that controls the processing memory, detects a valid component from a first operand received from an exterior and having a digital level, applies a voltage corresponding to the valid component having a digital level to a row line of at least one sub-array, and stores a second operand received from an exterior in the at least one sub-array.
A semiconductor system according to an embodiment of the present disclosure includes a controller configured to output a command address, a first chip selection signal, and a second chip selection signal, and a semiconductor device, including a first rank and a second rank, configured to receive the command address, the first chip selection signal, and the second chip selection signal and configured to calibrate each termination resistance value based on the command address, the first chip selection signal, and the second chip selection signal. The first rank calibrates the termination resistance value of the first rank to a target resistance value based on the command address and the first chip selection signal when a write operation on the first rank is performed, and the first rank calibrates the termination resistance value of the first rank to a dynamic resistance value based on the second chip selection signal when a write operation on the second rank is performed.
G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p.ex. circuits de commande E/S de données, mémoires tampon de données E/S
G11C 7/22 - Circuits de synchronisation ou d'horloge pour la lecture-écriture [R-W]; Générateurs ou gestion de signaux de commande pour la lecture-écriture [R-W]
24.
SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
A method for fabricating a semiconductor device includes: forming a sacrificial pad including a plurality of line portions and a plurality of auxiliary lines over a lower structure; forming an etch target layer over the sacrificial pad; forming a plurality of openings by etching the etch-target layer and stopping the etching at the sacrificial pad; forming a pillar filling the openings; forming an isolation trench by etching the etch-target layer and stopping the etching at the sacrificial pad; and forming a pad-type recess by removing the sacrificial pad through the isolation trench.
The present disclosure relates to an electronic circuit. A circuit board according to the present disclosure includes a first conductor layer including a first pad for transmitting and receiving a first signal to and from an external device, a plurality of second conductor layers stacked on the first conductor layer, and a third conductor layer stacked on the plurality of second conductor layers for transmitting and receiving a second signal to and from the external device, wherein at least one target conductor layer among the plurality of second conductor layers has a mesh structure and is electrically grounded, and remaining second conductor layers except for the at least one target conductor layer include respective voids and are electrically opened.
A memory system may include a memory device including a plurality of memory blocks each including a plurality of pages and a memory controller. The memory controller may be configured to determine a plurality of super memory blocks each including two or more of the plurality of memory blocks, calculate valid page counts of each of the plurality of super memory blocks, and determine a victim block for garbage collection based on a minimum value among the valid page counts of the plurality of super memory blocks and average value of the valid page counts of the plurality of super memory blocks. Furthermore, a dispersion of valid page counts of memory block groups within the super memory blocks may be used to determine the victim block.
A semiconductor device includes an alignment data generation circuit aligning first and second latch data generated from a first group of input data in synchronization with a first internal strobe signal, outputting the aligned first and second latch data as first alignment data, aligning a first and second latch data generated from a second group of the input data in synchronization with a second internal strobe signal, and outputting the aligned first and second latch data as second alignment data. The semiconductor device includes a write data generation circuit generating first and second write data from the first and second alignment data in synchronization with a latch clock after the start of a first operation mode and generating the first and second write data from the first alignment data in synchronization with the latch clock after the start of a second operation mode.
A controller may include i) a storage memory configured to store N-bit read data and N reliability data units, ii) a decoder configured to execute a decoding operation for the read data based on the reliability data units, and iii) a processing circuit configured to determine a value of reliability data unit corresponding to I-th bit of read data based on an I-th bit of first read data, an I-th bit of second read data and a difference between first syndrome weight and second syndrome weight.
H03M 13/15 - Codes cycliques, c. à d. décalages cycliques de mots de code produisant d'autres mots de code, p.ex. codes définis par un générateur polynomial, codes de Bose-Chaudhuri-Hocquenghen [BCH]
H03M 13/11 - Détection d'erreurs ou correction d'erreurs transmises par redondance dans la représentation des données, c.à d. mots de code contenant plus de chiffres que les mots source utilisant un codage par blocs, c.à d. un nombre prédéterminé de bits de contrôle ajouté à un nombre prédéterminé de bits d'information utilisant plusieurs bits de parité
29.
APPARATUS FOR EVICTING COLD DATA FROM VOLATILE MEMORY DEVICE
A memory system may include: a non-volatile memory device, a volatile memory device suitable for defining, as cold data, data stored in a word line, on which a refresh operation is performed a number of times greater than a reference number among a plurality of word lines coupled to a volatile memory cell array, and evicting the cold data, and a controller suitable for controlling operations of the volatile memory device and the non-volatile memory device, and storing the evicted cold data into the non-volatile memory device.
Provided herein may be a storage device, an electronic device including the storage device, and an operating method thereof. The storage device may include a memory controller, the memory controller including a plurality of functions configured to be identified as a plurality of storage devices logically separated from each other by an external host, a resource manager configured to store characteristic values and resource values respectively corresponding to the plurality of functions, and a command processor configured to, when commands respectively corresponding to the plurality of functions are received from the external host, preferentially process a command corresponding to a first function having lowest resource value, among the plurality of functions, based on the resource values, and update a resource value of the first function by accumulating an characteristic value of the first function in the resource value of the first function.
A memory system comprising: a memory device configured to store, in a non-volatile storage area included therein, a list of a plurality of performance classes and a table of performance information representing a group of performance parameter values for each of the plurality of performance classes, and a controller configured to provide the list to an external device according to a first request received from the external device, select one of the plurality of performance classes within the table according to a second request received from the external device, and control an operation of the memory device at an operation speed and in an operation method according to the performance parameter values corresponding to the selected performance class.
A controller controls an operation of a semiconductor memory device based on a request received from a host. The controller includes a host interface, a first function block, a second function block, and an internal command cache. The host interface generates a first internal command in response to the request. The first function block generates a second internal command in response to the first internal command. The second function block operates in response to the second internal command. The internet command cache caches at least one internal command corresponding to a reference internal command.
G06F 12/0802 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p.ex. mémoires cache
33.
MEMORY DEVICE AND OPERATING METHOD OF THE MEMORY DEVICE
A memory device, and a method of operating the memory device, includes a memory block including strings formed between bit lines and a source line and includes a peripheral circuit configured to perform a read operation of a selected memory cell included in a selected string among the strings. The peripheral circuit includes page buffers configured to increase a voltage of channels of the strings by applying a first precharge voltage to the bit lines in a set-up phase of the read operation, apply a second precharge voltage lower than the first precharge voltage to the bit lines in a read phase of the read operation, and discharge the bit lines in a discharge phase of the read operation.
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
G11C 11/4074 - Circuits d'alimentation ou de génération de tension, p.ex. générateurs de tension de polarisation, générateurs de tension de substrat, alimentation de secours, circuits de commande d'alimentation
G11C 11/4094 - Circuits de commande ou de gestion de lignes de bits
G11C 11/4093 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p.ex. mémoires tampon de données
A storage device includes: a memory device including a plurality of memory dies; a calibration controller for performing a calibration operation of measuring first to third calibration values with respect to a data strobe signal at first to third temperatures of the storage device, respectively; a calibration register for generating an equation between a temperature and a calibration value based on the first to third calibration values and the first to third temperatures, and storing a calibration table based on the equation; and a memory interface for communicating with the memory device, based on the calibration table.
A semiconductor memory device includes: a first stack structure and a second stack structure on a semiconductor substrate; a first vertical structure having a side all in contact with the first stack structure, the first vertical structure including a first memory layer and a first channel pattern; a second vertical structure having a sidewall in contact with the second stack structure, the second vertical structure including a second memory layer and a second channel pattern; a first bit line contact structure on the first vertical structure; and a first bit line overlapping with the first bit line contact structure. Each of the first stack structure and the second stack structure includes conductive layers stacked on the semiconductor substrate to be spaced apart from each other. The first bit line contact structure has a shape which is widened toward the first bit line.
The present disclosure relates to a memory device and a manufacturing method of the memory device. The memory device according to an embodiment includes a stacked structure including gate lines separated from and stacked on top of each other, a main plug formed in a vertical direction to the stacked structure, a plug separation pattern separating the main plug into first and second sub-plugs, a gap formed in the plug separation pattern; and a separation layer surrounding the gap.
A method of forming patterns includes: forming a hard mask layer on a target layer, coating a cleavage relief layer on the hard mask layer to fill cleavages generated in the hard mask layer, forming photoresist patterns on the cleavage relief layer, removing portions of the cleavage relief layer and portions of the hard mask layer using the photoresist patterns as a first etch mask to form hard mask patterns, removing portions of the target layer using the hard mask patterns as a second etch mask to form target layer patterns, and removing the hard mask patterns. The hard mask layer includes an amorphous carbon layer (ACL), and the cleavage relief layer includes a spin-on carbon (SOC) layer.
H01L 21/033 - Fabrication de masques sur des corps semi-conducteurs pour traitement photolithographique ultérieur, non prévue dans le groupe ou comportant des couches inorganiques
H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
H01L 21/3213 - Gravure physique ou chimique des couches, p.ex. pour produire une couche avec une configuration donnée à partir d'une couche étendue déposée au préalable
A semiconductor memory device includes a stack structure and a slit structure. The stack structure includes insulation layers and conductive layers alternately stacked with the insulation layers. The slit structure is configured to divide the stack structure into memory blocks. A part of the slit structure configured to define one memory block has a dashed shape including a slit region and a bridge region.
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
G11C 16/08 - Circuits d'adressage; Décodeurs; Circuits de commande de lignes de mots
H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p.ex. NON-ET
39.
STORAGE SYSTEM INCLUDING A DECOUPLING DEVICE HAVING A PLURALITY OF UNIT CAPACITORS
Provided is a storage system including a decoupling device having a plurality of unit capacitors. The storage system includes a storage device, a control device, and a decoupling device disposed on a circuit substrate. The storage device is configured to receive and store data from the control device. The control device is configured to generate an inner voltage. The decoupling device is connected to the control device and decouples the inner voltage. The decoupling device includes a plurality of unit capacitors constituting a plurality of decoupling capacitors. Each of the unit capacitors includes a plurality of capacitor elements, a first terminal, and a second terminal. Some of the unit capacitors are selectively connected with each other to constitute the decoupling capacitors having various capacitances.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
G11C 5/04 - Supports pour éléments d'emmagasinage; Montage ou fixation d'éléments d'emmagasinage sur de tels supports
G11C 5/06 - Dispositions pour interconnecter électriquement des éléments d'emmagasinage
G11C 11/4074 - Circuits d'alimentation ou de génération de tension, p.ex. générateurs de tension de polarisation, générateurs de tension de substrat, alimentation de secours, circuits de commande d'alimentation
40.
SEMICONDUCTOR CHIP INCLUDING THROUGH ELECTRODE, AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME
A semiconductor chip includes a body part having a front surface and a rear surface, a plurality of through electrodes penetrating the body part and arranged in a first direction in an array region, a plurality of front surface connection electrodes respectively coupled to the through electrodes over the front surface of the body part, and a plurality of rear surface connection electrodes respectively coupled to the through electrodes over the rear surface of the body part. The array region includes a central region and edge regions positioned on both sides of the central region in the first direction. A center of the front surface connection electrode and a center of the rear surface connection electrode that are positioned in each of the edge regions are positioned at a distance farther from the central region than a center of the corresponding through electrode.
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
41.
POWER SUPPLY APPARATUS AND METHOD AND STORAGE SYSTEM INCLUDING THE SAME
A power supply apparatus may include a power management circuits, a switch circuit and a power controller. The power controller configured to sequentially drive the power management circuits in accordance with a drive sequence, and control the switch circuit to apply, to the output terminals, the output voltage of a normally operated power management circuit as the driven power management circuit among the power management circuits.
G06F 1/3206 - Surveillance d’événements, de dispositifs ou de paramètres initiant un changement de mode d’alimentation
G06F 1/3234 - Gestion de l’alimentation, c. à d. passage en mode d’économie d’énergie amorcé par événements Économie d’énergie caractérisée par l'action entreprise
42.
PERIPHERAL COMPONENT INTERCONNECT EXPRESS INTERFACE DEVICE AND SYSTEM INCLUDING THE SAME
Provided herein is a PCIe interface device. The PCIe interface device may include a NOP DLLP generator configured to generate a No Operation (NOP) data link layer packet (DLLP) including event information representing an event in response to the occurrence of the event and a transmitter configured to transmit the NOP DLLP to an external device through a link including a plurality of lanes.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p.ex. contrôle de parité, exclusion des 9 ou des 11
G06F 11/07 - Réaction à l'apparition d'un défaut, p.ex. tolérance de certains défauts
G06F 9/448 - Paradigmes d’exécution, p.ex. implémentation de paradigmes de programmation
The present disclosure provides a chip including an even area including an even through via through which an even address is received and an even redundancy through via through which an even redundancy address is received, and an odd area including an odd through via through which an odd address is received and an odd redundancy through via through which an odd redundancy address is received. In the present disclosure, the even area may include an even address selection circuit configured to, based on a chip information signal, generate a selection even address and a selection even redundancy address from the even address, the even redundancy address, the odd address, and the odd redundancy address, and an even internal address generation circuit configured to, based on an even repair signal, generate an internal even address from the selection even address and the selection even redundancy address.
A data processing system includes a controller configured to receive a first encoded data item and a write request from a host, the first encoded data item being encoded based on a hamming code. The controller is further configured to store the first encoded data item in a write buffer, decode the first encoded data item stored in the write buffer based on the hamming code to detect and correct a first error in the first encoded data item to obtain a first error-corrected data item, encode the first error-corrected data item based on an error correction code to generate a second encoded data item, and transmit the second encoded data item to program the second encoded data item in a non-volatile memory device.
A memory system is provided to include a first virtual function controller in communication with a first virtual machine of a host and configured to receive, from the first virtual machine, a command for accessing a namespace and provide, to the first virtual machine, a response to the command; a second virtual function controller in communication with a second virtual machine of the host and configured to be coupled to the namespace and receive the command from the first virtual function controller based on status information of the first virtual function controller and the second virtual function controller; a buffer memory configured to provide an area for data corresponding to the command; and a memory controller configured to access the namespace based on the command and provide the buffer memory with the data.
G06F 9/455 - Dispositions pour exécuter des programmes spécifiques Émulation; Interprétation; Simulation de logiciel, p.ex. virtualisation ou émulation des moteurs d’exécution d’applications ou de systèmes d’exploitation
A synchronization circuit for an interconnection protocol, a controller and a storage device are provided. The synchronization circuit includes a first synchronization circuit module and a second synchronization circuit module. The first synchronization circuit module converts first control information of a first clock domain output by a data link layer receiver of the first device into second control information of a second clock domain, and outputs the second control information of the second clock domain. The second synchronization circuit module is coupled to the first synchronization circuit module, and converts the second control information of the second clock domain output by the first synchronization circuit module into third control information of a third clock domain to be output to a data link layer transmitter of the first device. Any two among the first, second and third clock domains are asynchronous.
G11C 7/22 - Circuits de synchronisation ou d'horloge pour la lecture-écriture [R-W]; Générateurs ou gestion de signaux de commande pour la lecture-écriture [R-W]
G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p.ex. circuits de commande E/S de données, mémoires tampon de données E/S
47.
APPARATUS AND METHOD FOR RECOVERING DATA IN A MEMORY SYSTEM
A memory system includes a memory device and a controller. The memory device includes a plurality of memory blocks for storing or outputting plural data entries and a first parity entry associated with the plural data entries. The controller a second parity entry based on a part of the plural data entries, an updated data entry which renews the part of the plural data entries, and the first parity entry, in response to an update event regarding the part of the plural data entries, allocate, for storing the second parity entry, a first memory block having least program-erase cycles among the plurality of memory blocks, allocate, for storing the updated data entry, a second memory block storing the first parity entry, and control the memory device to program the updated data entry and the second parity entry in the first memory block and the second memory block.
A semiconductor device includes a memory circuit including first and second banks and configured to count the numbers of inputs of first and second active signals for executing active operations on the first and second banks to generate a counting signal and to generate first and second hammering detection signals when the numbers of inputs of the first and second active signals are equal to or greater than a set number, and an active control circuit configured to store an active address as a target address when at least one of the first and second hammering detection signals is enabled, and to execute addition and subtraction operations on the target address to output a result of the addition and subtraction operations as an internal address for at least one of the first and second banks for executing a smart refresh operation, based on the counting signal in a refresh operation.
The present disclosure relates to a semiconductor memory device including a semiconductor substrate including a memory cell region and contact regions, a first stacked structure on the semiconductor substrate, a second stacked structure disposed between the semiconductor substrate and the first stacked structure, a plurality of cell plugs extending in a vertical direction crossing a top surface of the semiconductor substrate and arranged between the first stacked structure and the second stacked structure in the memory cell region, and a plurality of supports extending in the vertical direction and arranged on the first stacked structure in the contact region, wherein the second stacked structure is arranged in a different level from the plurality of supports.
H01L 27/1157 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par la région noyau de mémoire avec transistors de sélection de cellules, p.ex. NON-ET
H01L 27/11582 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par des agencements tridimensionnels, p.ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. canaux en forme de U
H01L 27/11573 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par la région de circuit périphérique
A semiconductor memory device includes a stacked structure including insulating layers and conductive layers that are alternately disposed in a vertical direction, a first structure including a channel layer that passes through the stacked structure and a memory pattern between the channel layer and the stacked structure, and a second structure including an insulating pattern that is formed along a sidewall of the stacked structure and a gate pattern that is formed on a sidewall of the insulating pattern.
H01L 27/11582 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par des agencements tridimensionnels, p.ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. canaux en forme de U
51.
CONTROLLER FOR CONTROLLING ONE-TIME PROGRAMMABLE MEMORY, SYSTEM, AND OPERATION METHOD THEREOF
A controller includes an e-fuse memory including a plurality of e-fuse memory cells and a control device. Such a control device may group the plurality of e-fuse memory cells into a plurality of e-fuse segments each having a given size, and set a plurality of e-fuse flags. Each of the plurality of e-fuse flags indicates whether data is programmed in a respective one of the plurality of e-fuse segment.
A memory system, a memory controller, and an operating method of the memory system are provided. The memory system may include a memory device including a first type memory block and a second type memory block and a memory controller configured to determine, when receiving a command to set a read boost mode for the target logical address, whether the data corresponding to the target logical address can be copied from the first type memory block to the second type memory block, and copy the data corresponding to the target logical address from the first type memory block to the second type memory block.
Daegu Gyeongbuk Institute of Science and Technology (République de Corée)
Inventeur(s)
Kim, Yeseong
Park, Jongho
Kwon, Hyukjun
Kim, Seowoo
Ha, Minho
Lim, Eui Cheol
Abrégé
A device for partitioning an input neural network includes an interposing circuit configured to determine a partitioning position to at which the input neural network is to be partitioned, to interpose a partitioning layer in the input neural network at the partitioning position; and to output and entire neural network that is obtained by interposing the partitioning layer in the input neural network, a training circuit configured to train the entire neural network; and a partitioning circuit configured to divide the entire neural network into a plurality of neural network partitions by partition the partitioning layer. The input neural network includes a plurality of layers.
A power supply apparatus may include a charging circuit configured to receive an external voltage and to generate a charging voltage by charging and discharging energy by switching according to a level of the charging voltage; an auxiliary power circuit configured to store an electric charge using the charging voltage; and a health monitoring circuit configured to determine a charging health state of the auxiliary power circuit by counting a number of switchings of the charging circuit during an interval in which the charging voltage rises to a first level from a second level, the determined charging health state being based on the number of switchings.
A system includes a first device including a first transmitter and a first receiver, and a second device including a second transmitter and a second receiver and configured to communicate with the first device. The two devices perform a first equalization operation by performing a first phase in which the first receiver performs a signal tuning operation on the second transmitter, a second phase in which the second receiver performs a signal tuning operation on the first transmitter, and one or more other phases. The first, second, and other phases may constitute all the phases of the first equalization operation, and some of the other phases may precede the first and second phases. In response to detection of an error after the first equalization operation, the two devices may perform a second equalization operation by performing the first phase, the second phase, or both, but not performing the other phases.
Provided herein may be a storage device and a printed circuit board for a solid state drive. The storage device may include a substrate including a conductive via, a plurality of memory devices mounted on a top surface of the substrate, a memory controller mounted on the top surface and electrically connected to the conductive via, and a port formed on a bottom surface of the substrate and electrically connected to the conductive via and a host device.
H05K 1/11 - Eléments imprimés pour réaliser des connexions électriques avec ou entre des circuits imprimés
H05K 1/18 - Circuits imprimés associés structurellement à des composants électriques non imprimés
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs sous-groupes différents du même groupe principal des groupes , ou dans une seule sous-classe de ,
57.
DEBUG DEVICE, DEBUG SYSTEM, AND DEBUG METHOD FOR TESTING STORAGE DEVICE
Provided herein may be a debug device, a debug system, and a debug method. The debug device may include a communicator coupled to a debug interface of a storage device, an interrupt signal generator configured to, when a request to measure an operation time for an instruction is received, output an interrupt signal for controlling an interrupt operation to be performed by the storage device, through the communicator, a tick count detector configured to acquire first tick counts corresponding to a start time point and an end time point of the interrupt operation and acquire second tick counts corresponding to a start time point and an end time point of the instruction, through the communicator, and a calibrator configured to determine the operation time using the first tick counts and the second tick counts.
A data storage device in accordance with an embodiment may include a controller configured to output a read control signal including an option number related to a read condition, and a memory device including a read condition table storage circuit, wherein the read condition table storage circuit is configured to store the read condition for the option number, and wherein the memory device is configured to perform a read operation under a read condition corresponding to the option number in response to the read control signal.
A semiconductor device includes: a semiconductor substrate; a plurality of bit line structures spaced apart from each other over the semiconductor substrate and each including a stacked structure of a bit line and a bit line hard mask; a contact pad positioned over the semiconductor substrate between the neighboring bit line structures; a contact structure including a stacked structure of a first contact formed over the contact pad and a second contact having a greater line width than the first contact; a first spacer structure interposed between the first contact and each of the bit line structures; and a second spacer structure interposed between the second contact and each of the bit line structures and having a smaller dielectric constant than the first spacer structure.
A stacked integrated circuit includes a first chip including a first through via set and a second through via set that are disposed to be symmetrical to each other in relation to a first rotating axis and including a first input and output (IO) circuit and a second IO circuit that are disposed to be asymmetrical to each other in relation to the first rotating axis and a second chip including a third through via set and a fourth through via set that are disposed to be symmetrical to each other in relation to a second rotating axis and including a third IO circuit and a fourth IO circuit that are disposed to be asymmetrical to each other in relation to the second rotating axis, the second chip being rotated around the second rotating axis and stacked on the first chip.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
61.
SEMICONDUCTOR SYSTEM FOR PERFORMING ROW HAMMERING TRACKING OPERATION
A semiconductor system includes a controller configured to generate a command and an address for performing a row hammering tracking operation and performing a precharge operation on a bank on which a tracking write operation of the row hammering tracking operation has been completed and a semiconductor device including the bank and a row hammering storage circuit, the semiconductor device configured to count an active number of the bank that is stored in the row hammering storage circuit by performing a tracking read operation of the row hammering tracking operation based on the command and the address, then store, in the row hammering circuit, the active number of the bank that is counted by performing the tracking write operation of the row hammering tracking operation, and perform the precharge operation on the bank based on the command.
There are provided a semiconductor memory device and a manufacturing method of a semiconductor memory device. The semiconductor memory device may include a stack structure including a plurality of conductive layers, a hole formed in the stack structure, a memory layer allowing a first part and a second part of the hole to be spaced apart from each other in the hole, and a first channel layer disposed in the first part of the hole and a second channel layer disposed in the second part of the hole.
H01L 27/11582 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par des agencements tridimensionnels, p.ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. canaux en forme de U
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p.ex. FAMOS
H01L 27/11519 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec grilles flottantes caractérisées par la configuration vue du dessus
H01L 27/11556 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec grilles flottantes caractérisées par des agencements tridimensionnels, p.ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
H01L 27/11565 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par la configuration vue du dessus
H01L 23/528 - Configuration de la structure d'interconnexion
A stacked integrated circuit includes a first chip including a first area and a second area that are disposed to be substantially symmetrical to each other in relation to a first rotating axis. The first area includes a first through via set and a first front pad set that are connected by using a first connection method. The second area includes a second through via set and a second front pad set that are connected by using a second connection method. The first through via set and the second through via set are disposed to be substantially symmetrical to each other in relation to the first rotating axis. The first front pad set and the second front pad set are disposed to be substantially symmetrical to each other in relation to the first rotating axis.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
G11C 5/06 - Dispositions pour interconnecter électriquement des éléments d'emmagasinage
A semiconductor memory device includes a first channel structure which is adjacent to an insulating structure and penetrates a plurality of conductive layers, a second channel structure which is spaced apart from the insulating structure and penetrates the plurality of conductive layers, a first impurity region included in an end portion of the first channel structure, and a second impurity region included in an end portion of the second channel structure. A doping concentration of an impurity in the first impurity region is different from a doping concentration of an impurity in the second impurity region.
A memory device includes a first wafer including a first memory block and a second memory block; and a second wafer arranged in a vertical direction with respect to the first wafer, including a third memory block with a stack number of word lines and a number of strings, each respectively larger than a stack number of word lines and a number of strings of the first memory block and each respectively larger than a stack number of word lines and a number of strings of the second memory block, and sharing, by the third memory block, a plurality of word line drivers with the first memory block and the second memory block.
A memory system and an operating method thereof perform word line verification by deactivating each of a plurality of word lines at the same time as initiating a bit line equalization, determine a fail bit count for each word line according to a number of bit flips that occurred during the word line verification, and determine a degraded word line on the basis of the fail bit counts of the plurality of word lines.
An semiconductor device may include a first conductive line; a second conductive line disposed to be spaced apart from the first conductive line; a variable resistance layer disposed between the first conductive line and the second conductive line; and an electrode layer which is disposed at least one of a first location between the first conductive lines and the variable resistance layer, or a second location between the variable resistance layer and the second conductive lines and includes a thickness dependent metal-insulator transition (TDMIT) material that exhibits an electrical resistance depending on a thickness of the TDMIT material.
H10N 70/00 - Dispositifs à l’état solide sans barrière de potentiel ni de surface, spécialement adaptés au redressement, à l'amplification, à la production d'oscillations ou à la commutation
H10B 63/00 - Dispositifs de mémoire par changement de résistance, p.ex. dispositifs RAM résistifs [ReRAM]
68.
SEMICONDUCTOR DEVICE AND FABRICATION METHOD OF THE SAME
A semiconductor device includes: a bit line structure formed over a substrate; a storage node contact plug spaced apart from the bit line structure; and a nitride spacer positioned between the bit line structure and the storage node contact plug, wherein the nitride spacer has a higher silicon content in a portion adjacent to the storage node contact plug than in a portion adjacent to the bit line structure.
An image sensing device and a method for forming the same are disclosed. The image sensing device includes a first substrate, first photoelectric conversion elements formed in the first substrate and configured to generate photocharges in response to a reception of light, a second substrate formed over the first substrate, and second photoelectric conversion elements formed in the second substrate and configured to generate photocharges in response to a reception of light, the second photoelectric conversion elements contacting corresponding the first photoelectric conversion elements, respectively.
A semiconductor device includes a first gate structure including a first pad staircase structure and a first sidewall connected to the first pad staircase structure. The semiconductor device also includes a dummy stack including a dummy staircase structure and a first dummy sidewall connected to the dummy staircase structure, the first dummy sidewall including at least one first protrusion. The semiconductor device further includes a first insulating structure located between the first gate structure and the dummy stack.
H01L 27/24 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des composants à l'état solide pour le redressement, l'amplification ou la commutation, sans barrière de potentiel ni barrière de surface
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 45/00 - Dispositifs à l'état solide spécialement adaptés pour le redressement, l'amplification, la production d'oscillations ou la commutation, sans barrière de potentiel ni barrière de surface, p.ex. triodes diélectriques; Dispositifs à effet Ovshinsky; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives
71.
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SEMICONDUCTOR DEVICE
Disclosed is a semiconductor device including a gate structure located on a source structure, and including conductive layers and insulating layers that are alternately stacked on each other, a contact plug passing through the gate structure, and electrically connected to the source structure, a stressor surrounding sidewalls of the contact plug, and a seed layer surrounding the stressor.
H01L 27/11578 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par des agencements tridimensionnels, p.ex. avec des cellules à des niveaux différents de hauteur
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 27/11551 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec grilles flottantes caractérisées par des agencements tridimensionnels, p.ex. avec des cellules à des niveaux différents de hauteur
72.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A method of manufacturing a semiconductor device includes forming a test circuit in a cross area of a scribe lane area disposed between chip areas of a substrate. The method also includes forming a first dummy structure on the test circuit, forming a test pad in a line area of the scribe lane area of the substrate, and cutting the substrate along the scribe lane area.
H01L 21/66 - Test ou mesure durant la fabrication ou le traitement
H01L 27/11519 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec grilles flottantes caractérisées par la configuration vue du dessus
H01L 27/11556 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec grilles flottantes caractérisées par des agencements tridimensionnels, p.ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
H01L 27/11582 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par des agencements tridimensionnels, p.ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. canaux en forme de U
H01L 27/11565 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par la configuration vue du dessus
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
73.
SEMICONDUCTOR APPARATUS PERFORMING A PLURALITY OF CLOCK SIGNALING OPERATIONS AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME
A semiconductor apparatus includes a clock distribution network, a data output circuit, and a data input circuit. The clock distribution network receives a system clock signal and drives the system clock signal to a CMOS level and a CML level to signal in different manners. The data output circuit outputs data based on the clock signal driven to the CMOS level. The data input circuit receives data based on the clock signal driven to the CML level.
H03K 19/0185 - Dispositions pour le couplage; Dispositions pour l'interface utilisant uniquement des transistors à effet de champ
H03K 17/687 - Commutation ou ouverture de porte électronique, c. à d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs les dispositifs étant des transistors à effet de champ
A system and associated method for a storage device. In the system and method, a sort command from a host is received. In response to having received the sort command, the storage device is configured for sorting by allocating at least one storage location to store data to be sorted based at least on a) an amount of the data to be sorted and b) an available storage space in a memory of the storage device. In the system and method, an upgradable sorting algorithm is utilized to generate sorted data subsets, and the sorted serialized data subsets are stored based on the at least one storage location indicating where the data to be sorted is to be stored. Page identifiers (IDs) of the sorted data subsets are provided to the host.
A semiconductor device includes a gate structure including conductive layers and insulating layers, which are alternately stacked, channel structures penetrating the gate structure, and contact plugs disposed under the gate structure and connected to the channel structures, respectively. The semiconductor device also includes a bit line connected to the channel structures through the contact plugs, a peripheral circuit disposed under the bit line, and a discharge interconnection that connects the bit line and the peripheral circuit.
H01L 23/60 - Protection contre les charges ou les décharges électrostatiques, p.ex. écrans Faraday
H01L 27/11556 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec grilles flottantes caractérisées par des agencements tridimensionnels, p.ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
H01L 27/11526 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec grilles flottantes caractérisées par la région de circuit périphérique
H01L 27/11582 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par des agencements tridimensionnels, p.ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. canaux en forme de U
H01L 27/11573 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par la région de circuit périphérique
76.
METHOD OF MANUFACTURING A SEMICONDUCTOR CHIP INCLUDING A STRESS CONCENTRATION PORTION
A method of manufacturing a semiconductor chip includes forming a first stack by alternately stacking first material layers and second material layers over a semiconductor substrate, forming a first trench penetrating the first stack, and forming a first stress concentration portion by forming a second stack over the first stack.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
77.
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME
A semiconductor apparatus includes a data input and output (input/output) circuit configured to operate by receiving a first voltage, a core circuit configured operate by receiving a second voltage, and a control circuit configured to output a power control signal for activating the data input/output circuit when the first voltage is higher than a first set voltage and the second voltage is higher a second set voltage.
A memory includes a first check matrix calculation circuit configured to generate a first parity based on a group indicator portion of a check matrix and write data; a memory core including cell regions configured to store therein the write data and the first parity, neighboring ones of the cell regions sharing one or more sub-word line drivers; a first syndrome calculation circuit configured to generate a first syndrome based on the first parity read from the memory core and a first result of calculating the group indicator portion and data read from the memory core; and a failure determination circuit configured to detect, for each row of the memory core, a defective one of the sub-word line drivers based on the first syndrome.
A memory device includes a plurality of memories, a plurality of access units and a controller configured to control data from an access unit according to an operation cycle of another access unit whose form factor is different from that of the access unit.
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p.ex. contrôle de parité, exclusion des 9 ou des 11
A memory device includes a plurality of memories, a plurality of access units and a controller configured to control data from an access unit according to an operation cycle of another access unit whose form factor is different from that of the access unit.
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p.ex. contrôle de parité, exclusion des 9 ou des 11
81.
UFS DEVICE FOR TRANSMITTING STATUS INFORMATION THROUGH AFC FRAME AND OPERATING METHOD THEREOF
Embodiments of the present disclosure relate to an UFS device and an operating method thereof. According to the embodiments of the present disclosure, the UFS device may collect status information of the UFS device, create an Acknowledgement and Flow Control (AFC) frame including the collected status information, and transmit the AFC frame to a host performing communication with the UFS device.
A memory system includes a non-volatile memory device and a performance manager. The performance manager activates a plurality of sub-controllers according to a setting of a host device, allocates memory regions respectively to the plurality of sub-controllers, the memory regions being included in the non-volatile memory device, and determines, according to maximum performance values and a size ratio of the memory regions, credit sets to be allocated respectively to the plurality of sub-controllers.
Interface devices and systems that include interface devices are disclosed. In some implementations, a device includes a transceiver configured to transmit and receive data, a lane margining controller in communication with the transceiver and configured to control the transceiver to transmit, through a margin command, to an external device, a request for requesting a state of an elastic buffer of the external device, and control the transceiver to receive the state of the elastic buffer of from the external device, and a port setting controller adjust a clock frequency range of a spread spectrum clocking scheme based on the state of the elastic buffer.
H04L 7/00 - Dispositions pour synchroniser le récepteur avec l'émetteur
H04L 7/033 - Commande de vitesse ou de phase au moyen des signaux de code reçus, les signaux ne contenant aucune information de synchronisation particulière en utilisant les transitions du signal reçu pour commander la phase de moyens générateurs du signal de synchronisation, p.ex. en utilisant une boucle verrouillée en phase
84.
NONVOLATILE MEMORY DEVICE AND OPERATION METHOD THEREOF
Korea Advanced Institute of Science and Technology (République de Corée)
Inventeur(s)
Lee, Jung Woo
Choi, Yang Kyu
Yu, Ji Man
Abrégé
A nonvolatile memory device and an operating method thereof are disclosed. An operating method of a nonvolatile memory device may comprise providing the nonvolatile memory device including a memory transistor, the memory transistor including a source, a drain, a channel disposed between the source and the drain, and a first insulating layer, a charge storage layer, a second insulating layer, and a gate which are sequentially disposed on the channel, and curing the memory transistor by removing charges or traps existing at least at an interface between the channel and the first insulating layer by generating a gate induced drain leakage (GIDL) current on the drain side of the memory transistor and using Joule heating caused by the GIDL current.
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p.ex. FAMOS
G11C 16/14 - Circuits pour effacer électriquement, p.ex. circuits de commutation de la tension d'effacement
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
G11C 16/34 - Détermination de l'état de programmation, p.ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
G11C 16/10 - Circuits de programmation ou d'entrée de données
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
Techniques for obtaining a device core dump in a multiprocessor device may include detecting an occurrence of an error in a processor of a multiprocessor device, and trigger an inter-processor interrupt from the processor in which the error occurred to each of the other processors of the multiprocessor device to halt operation of the multiprocessor device. Processor core dumps corresponding to the processors can then be stored in a memory subsystem. A determination can be made that a data ready indication for each of the processors has been set to indicate that the corresponding processor core dump has been stored in the memory subsystem. The processor core dumps can then be copied from the memory subsystem to a non-volatile memory to generate a device core dump in the non-volatile memory.
A three-dimensional memory device is proposed. The three-dimensional memory device comprises a plurality of memory cell strings each memory cell string comprising a plurality of memory cells, a plurality of word lines each one associated with respective memory cells of the plurality of memory cell strings arranged at a same vertical distance from the substrate, and a control circuit. The control circuit is configured to apply a sequence of incremental step programming pulses to a selected memory cell and perform program verify after applying a first programming pulse. The control circuit is further configured to determine an updated first programming pulse based on a second programming pulse indicating that the selected memory cell has been programmed and perform the program verify operations starting from the updated first programming pulse for each subsequently-selected memory cell.
G11C 16/34 - Détermination de l'état de programmation, p.ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p.ex. FAMOS
G11C 16/10 - Circuits de programmation ou d'entrée de données
87.
PERIPHERAL COMPONENT INTERCONNECT EXPRESS DEVICE AND OPERATING METHOD THEREOF
A Peripheral Component Interconnect express (PCIe) device includes a Direct Memory Access (DMA) device including a plurality of functions; and a PCIe interface device for performing communication between a host and the DMA device. The PCIe interface device includes a reset operation controller for, when a plurality of reset signals are received from the host, grouping operations, which are the same as one another among reset operations respectively corresponding to the plurality of reset signals, determining a processing order of the reset operations, and performing the reset operations according to the processing order.
G06F 13/28 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant le transfert par rafale, p.ex. acces direct à la mémoire, vol de cycle
G06F 13/42 - Protocole de transfert pour bus, p.ex. liaison; Synchronisation
88.
SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR MEMORY DEVICE
Provided herein may be a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device may include a sub-block insulating layer interposed between a first select gate structure and a second select gate structure, a plurality of conductive patterns stacked over first and second select gate structures to be spaced apart from each other, and a channel structure penetrating one of the first and second select gate structures and the plurality of conductive patterns, the channel structure including an inflection point located at a level between the sub-block insulating layer and the plurality of conductive patterns.
H01L 27/11582 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par des agencements tridimensionnels, p.ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. canaux en forme de U
H01L 27/11565 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par la configuration vue du dessus
89.
IMAGE PROCESSING SYSTEM AND IMAGE PROCESSING METHOD
An image processing device comprises a data group generator, a gradient value manager, and a cost volume manager. The data group generator is configured to receive pixel values of an image that include phase and brightness information, and determine data groups indicating disparity of the image based on target pixel values, where the data groups correspond to a range that is determined according to the phase information. The gradient value manager is configured to determine gradient values of a region corresponding to the target pixel values and determine gradient information. The gradient information is determined by applying threshold values to the gradient values, where the threshold values are determined according to the target pixel values. The cost volume manager is configured to determine a cost volume by weighted summing the data groups based on the gradient information.
A memory device includes: a memory cell array including a first memory cell group including memory cells located within a first physical distance from a reference node and a second memory cell group including memory cells located beyond the first physical distance from the reference node; a peripheral circuit configured to perform a program operation of applying program voltages increasing gradually to memory cells included in the memory cell array through word lines; and control logic configured to determine a time at which a first program permission voltage is applied to the first memory cell group and determine a magnitude of the first program permission voltage on the basis of a magnitude of the program voltages in response to a gradual increase in the program voltages, the control logic is further configured to control the peripheral circuit to apply the first program permission voltage to the first memory cell group through bit lines.
A memory system may include a nonvolatile memory device comprising a first area and a second area having a higher data I/O operation speed than the first area, and a controller suitable for performing a first read operation on hot data having a hot property, among data stored in the first area. The controller may control the nonvolatile memory device to copy the hot data into the second area during the first read operation, and access the hot data copied in the second area, when a second read operation on the hot data is requested after the first read operation.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p.ex. contrôle de parité, exclusion des 9 ou des 11
The present technology includes a storage device including a memory device including a first storage region and a second storage region and a memory controller configured to, in response to a write request in the first storage region from an external host, acquire data stored the first region based on a fail prediction information provided from the memory device and to perform a write operation corresponding to the write request, wherein the first storage region and the second storage region are allocated according to logical addresses of data to be stored in by requests of the external host.
G06F 12/0806 - Systèmes de mémoire cache multi-utilisateurs, multiprocesseurs ou multitraitement
G06F 12/0891 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p.ex. mémoires cache utilisant des moyens d’effacement, d’invalidation ou de réinitialisation
G06F 11/00 - Détection d'erreurs; Correction d'erreurs; Contrôle de fonctionnement
93.
HIGH VOLTAGE SWITCH CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME
A high voltage switch circuit and a semiconductor memory device having the same are provided. The high voltage switch circuit includes a switching circuit for outputting a high voltage by transmitting one of a plurality of pump voltages to an output node; and a discharge circuit connected between the output node and a terminal of an internal power voltage, the discharge circuit discharging the high voltage to a level of the internal power voltage. The discharge circuit includes a triple well transistor.
A semiconductor apparatus includes an internal clock generating circuit, a stop controlling circuit, and a data clock generating circuit. The internal clock generating circuit generates, based on a reference clock signal, a plurality of internal clock signals. The stop controlling circuit generates a stop signal and a clock level signal based on the reference clock signal and the plurality of internal clock signals. The data clock generating circuit generates a data clock signal and a complementary data clock signal based on the plurality of internal clock signals, the stop signal, and the clock level signal.
H03K 5/135 - Dispositions ayant une sortie unique et transformant les signaux d'entrée en impulsions délivrées à des intervalles de temps désirés par l'utilisation de signaux de référence de temps, p.ex. des signaux d'horloge
H03L 7/08 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase
G06F 1/08 - Générateurs d'horloge ayant une fréquence de base modifiable ou programmable
95.
MEMORY CONTROLLER AND METHOD OF OPERATING THE SAME
Provided herein may be a memory controller and a method of operating the same. The method of operating a memory controller may include determining whether a reset request received from a host is valid, based on boot workload information related to a plurality of boot stages of the host, and performing a reset operation on a memory device depending on whether the reset request is valid.
A method for manufacturing a three-dimensional memory device includes forming a lower multi-layered stack by alternately stacking a plurality of first dielectric layers and a plurality of first sacrificial layers on a substrate; forming an etch stop layer on the lower multi-layered stack; forming an upper multi-layered stack by alternately stacking a plurality of second dielectric layers and a plurality of second sacrificial layers on the etch stop layer; forming a vertical trench by etching the upper multi-layered stack using the etch stop layer as an etch end target; removing the etch stop layer under the vertical trench; and forming a first stairway-shaped trench in the lower multi-layered stack under the vertical trench, and forming a second stairway-shaped trench in the upper multi-layered stack.
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 27/11582 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par des agencements tridimensionnels, p.ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. canaux en forme de U
H01L 23/535 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions internes, p.ex. structures d'interconnexions enterrées
97.
MEMORY CONTROLLER AND MEMORY SYSTEM INCLUDING THE SAME
The present technology relates to an electronic device. According to the present technology, a memory controller may include an attribute determiner configured to determine an attribute of each of a plurality of pages included in a first external device to indicate one of a hot page and a cold page, based on an access interval which is an interval from a time at which data is stored in each of the pages to a time at which access to the data is requested, a page analyzer configured to determine a ratio of hot pages having a hot page attribute to the plurality of pages, and a memory allocator configured to control one of the first external device and the second external device to store therein externally provided data based on the ratio of hot pages.
The present disclosure relates to a semiconductor memory device including a second lower insulating layer, a dummy stack on the second lower insulating layer, a source structure arranged at a same height as the second lower insulating layer, a cell stack on the source structure, a plurality of contact plugs passing through the dummy stack, and a dummy contact passing through a portion of the dummy stack and arranged between the contact plugs.
H01L 23/535 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions internes, p.ex. structures d'interconnexions enterrées
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 27/11582 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par des agencements tridimensionnels, p.ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. canaux en forme de U
H01L 27/11573 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par la région de circuit périphérique
99.
SEMICONDUCTOR MEMORY DEVICE AND METHODS OF MANUFACTURING AND OPERATING THE SAME
A semiconductor memory device and methods of manufacturing and operating the same are set forth. The semiconductor memory device includes a stack structure including a plurality of interlayer insulating layers and a plurality of gate electrodes, which may be alternately stacked on a substrate, and a plurality of channel structures penetrating the stack structure in a vertical direction. Each of the plurality of channel structures includes a channel layer, a tunnel insulating layer, an emission preventing layer, and a charge storage layer, each of which vertically extends toward the substrate.
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p.ex. FAMOS
G11C 16/10 - Circuits de programmation ou d'entrée de données
G11C 13/00 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage non couverts par les groupes , ou
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
H10B 63/00 - Dispositifs de mémoire par changement de résistance, p.ex. dispositifs RAM résistifs [ReRAM]
H10N 70/20 - Dispositifs de commutation multistables, p.ex. memristors
100.
SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
There are provided a semiconductor memory device and a manufacturing method thereof. The semiconductor memory device includes: a source layer; a channel structure extending in a first direction from within the source layer; a source-channel contact layer surrounding the channel structure on the source layer; a first select gate layer overlapping with the source-channel contact layer and surrounding the channel structure; a stack including interlayer insulating layers and conductive patterns that are alternately stacked in the first direction and surrounding the channel structure, the stack overlapping with the first select gate layer; and a first insulating pattern that is formed thicker between the first select gate layer and the channel structure than between the stack and the channel structure.
G11C 11/413 - Circuits auxiliaires, p.ex. pour l'adressage, le décodage, la commande, l'écriture, la lecture, la synchronisation ou la réduction de la consommation
