SK Hynix Inc.

Republic of Korea

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        Patent 12,577
        Trademark 44
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        United States 12,471
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        Canada 11
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[Owner] SK Hynix Inc. 10,168
Hynix Semiconductor Inc. 2,176
SK hynix memory solutions inc. 163
Siliconfile Technologies Inc. 92
BOE-Hydis Technology Co., Ltd. 22
Date
New (last 4 weeks) 169
2024 June (MTD) 59
2024 May 167
2024 April 60
2024 March 71
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IPC Class
G06F 3/06 - Digital input from, or digital output to, record carriers 1,370
G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers 999
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS 944
G11C 7/00 - Arrangements for writing information into, or reading information out from, a digital store 746
G11C 16/10 - Programming or data input circuits 645
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NICE Class
09 - Scientific and electric apparatus and instruments 38
35 - Advertising and business services 3
42 - Scientific, technological and industrial services, research and design 2
40 - Treatment of materials; recycling, air and water treatment, 1
Status
Pending 1,471
Registered / In Force 11,150
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1.

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE INCLUDING SPLIT SELECTION LINES AND METHOD OF MANUFACTURING THE SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

      
Application Number 18356951
Status Pending
Filing Date 2023-07-21
First Publication Date 2024-06-13
Owner SK hynix Inc. (Republic of Korea)
Inventor Pak, Jin Su

Abstract

A semiconductor integrated circuit device includes a stack structure, a split structure, a plurality of channel structures and at least one boundary channel structure. The stack structure includes a plurality of insulation layers and a plurality of conductive layers alternately stacked in a first direction. The split structure is configured to split at least one selected conductive layer among the conductive layers from the insulation layers adjacent to the selected conductive layer. The channel structures are spaced apart from the split structure. The channel structures are arranged in the stack structure. The boundary channel structure is partially overlapped with the split structure. The boundary channel structure is arranged in the stack structure.

IPC Classes  ?

  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
  • G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
  • H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout

2.

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

      
Application Number 18193643
Status Pending
Filing Date 2023-03-31
First Publication Date 2024-06-13
Owner SK hynix Inc. (Republic of Korea)
Inventor Kim, Seung Hwan

Abstract

A semiconductor device includes a lower structure; a plurality of horizontal conductive layers that are oriented horizontally in a direction parallel to a surface of the lower structure; a vertical conductive line commonly coupled to first-side ends of the horizontal conductive layers and extending in a direction perpendicular to the surface of the lower structure; and a plurality of reservoir capacitors respectively coupled to second-side ends of the horizontal conductive layers and vertically stacked over the lower structure.

IPC Classes  ?

  • H10B 12/00 - Dynamic random access memory [DRAM] devices

3.

CLOCK DISTRIBUTION NETWORK, AND SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SYSTEM INCLUDING THE CLOCK DISTRIBUTION NETWORK

      
Application Number 18320701
Status Pending
Filing Date 2023-05-19
First Publication Date 2024-06-13
Owner SK hynix Inc. (Republic of Korea)
Inventor Kang, Ji Hyo

Abstract

A clock distribution network includes a global clock generation circuit and a data clock generation circuit. The global clock generation circuit generates a first group of division clock signals by dividing a system clock signal, and generates a second group of division clock signals by dividing the first group of division clock signals. The data clock generation circuit generates a first group of data clock signals based on the system clock signal and at least some of the first group of division clock signals, and generates a second group of data clock signals based on at least some of the first group of data clock signals and at least some of the second group of division clock signals.

IPC Classes  ?

  • G06F 1/10 - Distribution of clock signals
  • G06F 1/08 - Clock generators with changeable or programmable clock frequency
  • G06F 1/12 - Synchronisation of different clock signals

4.

CONTROLLER, STORAGE DEVICE AND METHOD FOR OPERATION TO BALANCE MEMORY DEGRADATION

      
Application Number 18447204
Status Pending
Filing Date 2023-08-09
First Publication Date 2024-06-13
Owner SK hynix Inc. (Republic of Korea)
Inventor Lee, Sung Min

Abstract

In order to reduce the degradation deviation of each area of a volatile memory storing data related to the non-volatile memory included in a storage device, an area storing the corresponding data may be changed and set according to the type of data stored in the volatile memory at a preset time.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

5.

MULTI-LEVEL DATA STORAGE DEVICE AND OPERATION METHOD THEREOF

      
Application Number 18453967
Status Pending
Filing Date 2023-08-22
First Publication Date 2024-06-13
Owner
  • SK hynix Inc. (Republic of Korea)
  • Korea Advanced Institute of Science and Technology (Republic of Korea)
Inventor
  • Koo, Kyoungho
  • Won, Youjip

Abstract

A multi-level data storage device includes a first storage device; a second storage device located at a lower level than the first storage device; an input/output (I/O) control circuit configured to control a first write operation for the first storage device and a second write operation for the second storage device; and an imbalance control circuit configured to calculate an imbalance index corresponding to a write set that is generated when a sum of a number of first write operations and a number of the second write operations becomes a predetermined number, and configured to control the I/O control circuit to control imbalance of write operations performed in the multi-level data storage device by controlling the first write operation or the second write operation based on the imbalance index.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

6.

DEVICE FOR DISTANCE MEASUREMENT

      
Application Number 18337338
Status Pending
Filing Date 2023-06-19
First Publication Date 2024-06-13
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Lee, Sun Young
  • Song, Jeong Eun

Abstract

An image sensor includes at least two pixels and a control circuit. The control circuit is configured to provide a first modulation voltage and a second modulation voltage having a phase difference of 180 degrees from each other to each of the at least two pixels in a first mode. The control circuit is also configured to provide the first modulation voltage to a first pixel among the at least two pixels and provide the second modulation voltage to a second pixel among the at least two pixels in a second mode.

IPC Classes  ?

  • G01S 7/481 - Constructional features, e.g. arrangements of optical elements
  • G01S 17/08 - Systems determining position data of a target for measuring distance only

7.

SUBSTRATE INCLUDING A REFERENCE VOLTAGE LAYER HAVING AN IMPEDANCE CALIBRATOR

      
Application Number 18306874
Status Pending
Filing Date 2023-04-25
First Publication Date 2024-06-13
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Lee, Jae Hoon
  • Kim, Jong Wook
  • Eom, Ju Il

Abstract

A substrate in accordance with an embodiment of the disclosure includes a signal transmission layer including a signal transmission pad and a signal transmission interconnection; a first dielectric layer stacked on the signal transmission layer; and a first reference voltage layer stacked on the first dielectric layer. The first reference voltage layer includes a first space hole and an impedance calibrator. The impedance calibrator includes an impedance calibration part disposed in the first space hole; and a first bridge connecting a first portion of the impedance calibration part to a first portion of the first reference voltage layer.

IPC Classes  ?

  • H05K 1/02 - Printed circuits - Details
  • H05K 1/09 - Use of materials for the metallic pattern
  • H05K 1/11 - Printed elements for providing electric connections to or between printed circuits

8.

STORAGE DEVICE AND OPERATING METHOD THEREOF

      
Application Number 18325109
Status Pending
Filing Date 2023-05-30
First Publication Date 2024-06-13
Owner SK hynix Inc. (Republic of Korea)
Inventor Cho, Sung Yeob

Abstract

A storage device is provided which is capable of preventing characteristic degradation of the storage device at low temperature and reducing a failure. The storage device includes a memory device; a leakage current information storage for storing information associated with a leakage current generated based on a temperaturerange of the memory device; and a current controller for controlling the current internally consumed, based on the information associated with the leakage current, when a current temperature of the memory device is equal to or lower than a first temperature.

IPC Classes  ?

  • G11C 11/4078 - Safety or protection circuits, e.g. for preventing inadvertent or unauthorised reading or writing; Status cells; Test cells
  • G01R 31/52 - Testing for short-circuits, leakage current or ground faults
  • G11C 7/04 - Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects

9.

STORAGE DEVICE DETERMINING QUICKLY WHETHER ERROR CORRECTION DECODING HAS FAILED AND METHOD OF OPERATING THE STORAGE DEVICE

      
Application Number 18309806
Status Pending
Filing Date 2023-04-30
First Publication Date 2024-06-13
Owner SK hynix Inc. (Republic of Korea)
Inventor Gim, Yeong Dong

Abstract

A storage device may execute first error correction decoding on a plurality of memory cells when a read operation on the plurality of memory cells fails, and determine, when the first error correction decoding fails, whether to execute second error correction decoding on the plurality of memory cells based on at least one of a value of an early termination flag and whether an early termination condition is satisfied.

IPC Classes  ?

  • G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens

10.

MEMORY CORE AND SEMICONDUCTOR APPARATUS WITH TRANSPOSED MATRIX CALCULATION FUNCTION INCLUDING THE SAME

      
Application Number 18325836
Status Pending
Filing Date 2023-05-30
First Publication Date 2024-06-13
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Hong, Gi Moon
  • Kwon, Dae Han

Abstract

A memory core includes a first signal line; a second signal line; a first transistor coupled between the second signal line and a data storage element; a second transistor coupled between the first signal line and the data storage element; and a switching circuit configured to, in response to a mode selection signal, switch an operation of the memory core between a first mode and a second mode, the first mode controlling the first transistor according to a level of the first signal line and turning off the second transistor and a second mode controlling the second transistor according to a level of the second signal line and turning off the first transistor.

IPC Classes  ?

  • G06F 7/78 - Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data for changing the order of data flow, e.g. matrix transposition or LIFO buffers; Overflow or underflow handling therefor
  • G11C 11/408 - Address circuits
  • G11C 11/4091 - Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
  • G11C 11/4096 - Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches

11.

READ ERROR INJECTION

      
Application Number 18065564
Status Pending
Filing Date 2022-12-13
First Publication Date 2024-06-13
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Zeleniak, Dmitri
  • Chertkov, Pavel
  • Abramov, Valery
  • Peniaz, Sergei
  • Musin, Sergei

Abstract

Techniques for injecting memory read errors may include obtaining an error injection profile from a test library. A defense level in the defense hierarchy can be selected for execution according to the probabilities in the error injection profile. One or more errors can be injected into read operations of the storage device according to the defense-level read retry vector of the selected defense level, and a defense algorithm of the selected defense level is executed to recover read data of the read operations.

IPC Classes  ?

  • G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
  • G06F 11/27 - Built-in tests
  • G06F 11/30 - Monitoring

12.

SEMICONDUCTOR DEVICE INCLUDING INTERNAL TRANSMISSION PATH AND STACKED SEMICONDUCTOR DEVICE USING THE SAME

      
Application Number 18587961
Status Pending
Filing Date 2024-02-27
First Publication Date 2024-06-13
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Lee, Jinhyung
  • Park, Myeong Jae
  • Oh, Su Hyun
  • Lee, Chang Kwon

Abstract

A semiconductor device comprising: a first or a second path configured to transmit a first signal which swings between a ground level and a first level, a third path configured to transmit a second signal which swings between the ground level and a second level lower than the first level, a transmitter configured to output received the first signal through the first or second path as the second signal to the third path, and initialize in response to an enable signal, and a receiver configured to output received the second signal through the third path as the first signal through the first or second path, determine level of the second signal through a reference level that is regulated according to a fed-back level of an output terminal thereof, and initialize in response to the enable signal.

IPC Classes  ?

  • G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
  • G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring

13.

MEMORY DEVICE

      
Application Number 18338088
Status Pending
Filing Date 2023-06-20
First Publication Date 2024-06-13
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Yim, Da Mi
  • Lee, Ki Hong
  • Noh, Yoo Hyun

Abstract

A memory device includes a word line including a cell array region and a connection region extending in a first direction from the cell array region; a first select line and a second select line, spaced apart from each other in a second direction intersecting the first direction on the cell array region, the first select line and the second select line, extending onto the connection region of the word line; and an isolation pattern disposed between the first select line and the second select line. The isolation pattern includes a first sub-isolation pattern extending in the first direction and a second sub-isolation pattern extending in the second direction from the first sub-isolation pattern. The second select line is bent to surround an outside corner defined at an intersection point of the first sub-isolation pattern and the second sub-isolation pattern of the isolation pattern.

IPC Classes  ?

  • H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

14.

MEMORY DEVICE AND OPERATING METHOD THEREOF

      
Application Number 18333366
Status Pending
Filing Date 2023-06-12
First Publication Date 2024-06-13
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Kim, Jong Woo
  • Shin, Young Cheol

Abstract

A memory device includes a memory cell array including a plurality of pages; a peripheral circuit for performing a program operation; and a control logic for controlling the peripheral circuit to, when a program command for a first page among the plurality of pages and a plurality of page data are received, program a second page based on one page data among the plurality of page data, and program the first page based on other page data, according to a stage of the program operation.

IPC Classes  ?

  • G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
  • G06F 3/06 - Digital input from, or digital output to, record carriers
  • G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
  • G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • G11C 16/10 - Programming or data input circuits
  • G11C 16/26 - Sensing or reading circuits; Data output circuits

15.

SEMICONDUCTOR MEMORY DEVICE

      
Application Number 18331821
Status Pending
Filing Date 2023-06-08
First Publication Date 2024-06-13
Owner SK hynix Inc. (Republic of Korea)
Inventor Choi, Eun Seok

Abstract

A semiconductor memory device includes a source bonding structure including a first source layer and a second source layer bonded to each other, a first memory cell array structure connected to the first source layer of the source bonding structure, and a second memory cell array structure connected to the second source layer of the source bonding structure. The source bonding structure includes at least one of a semiconductor bonding area and a metal bonding area.

IPC Classes  ?

  • G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 23/528 - Layout of the interconnection structure
  • H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
  • H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
  • H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region

16.

SYSTEM AND METHOD FOR LSM COMPACTION

      
Application Number 18079355
Status Pending
Filing Date 2022-12-12
First Publication Date 2024-06-13
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Kim, Jongryool
  • Lim, Hyung Jin
  • Li, Shiju
  • Tang, Kevin

Abstract

In a compaction scheme for a log structured merge (LSM) tree, a storage device is configured to: receive a first user data piece from a host; generate a first meta data piece for a highest level of the LSM tree, corresponding to the first user data piece; when the highest level exceeds a set storage limit, trigger a compaction process on the first and second meta data pieces to generate compacted meta data pieces excluding overlapping meta data elements of the second meta data pieces overlapped with the first meta data piece. Through a garbage collection, victim user data elements corresponding to the overlapping meta data elements are deleted.

IPC Classes  ?

  • G06F 16/242 - Query formulation
  • G06F 16/21 - Design, administration or maintenance of databases
  • G06F 16/22 - Indexing; Data structures therefor; Storage structures
  • G06F 16/25 - Integrating or interfacing systems involving database management systems

17.

STORAGE DEVICE MANAGING MAP INFORMATION AND METHOD OF OPERATING THE STORAGE DEVICE

      
Application Number 18314683
Status Pending
Filing Date 2023-05-09
First Publication Date 2024-06-13
Owner SK hynix Inc. (Republic of Korea)
Inventor Park, Sung Jin

Abstract

A storage device receives a write request including first data and a first logical address corresponding to the first data, stores the first data in a first memory block among a plurality of memory blocks, determines a second memory block among the plurality of memory blocks to which the first data stored in the first memory block is to be migrated, and stores first map information including the physical address of the second memory block and the first logical address.

IPC Classes  ?

18.

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR MEMORY DEVICE

      
Application Number 18337307
Status Pending
Filing Date 2023-06-19
First Publication Date 2024-06-13
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Park, Mi Seong
  • Park, In Su
  • Jang, Jung Shik
  • Jeon, Seok Min
  • Choi, Won Geun
  • Choi, Jung Dal

Abstract

The present disclosure includes a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device includes a stack including a plurality of conductive layers stacked to be spaced apart in a first direction, an opening in the stack extending in the first direction and having an elliptical shape in a plan view, and a first channel pattern and a second channel pattern spaced apart from each other in a second direction toward which a major axis of the elliptical shape faces in the opening, the first channel pattern and the second channel pattern extending in the first direction. Each of the first channel pattern and the second channel pattern includes a central portion overlapping with the major axis of the elliptical shape and bent portions extending away from the central portion.

IPC Classes  ?

  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
  • H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout

19.

IMAGE PROCESSING SYSTEM AND IMAGE PROCESSING METHOD

      
Application Number 18334818
Status Pending
Filing Date 2023-06-14
First Publication Date 2024-06-13
Owner SK hynix Inc. (Republic of Korea)
Inventor Ahn, Sang Woo

Abstract

An image processing system includes an image sensor including a pixel array including first pixels corresponding to a first phase difference degree and second pixels corresponding to a second phase difference degree. The image processing system also includes an image set manager for generating a first image set corresponding to a first resolution, based on pixel values of the first pixels, and generating a second image set corresponding to a second resolution, based on pixel values of the second pixels. The image processing system further includes and an image synthesizer for generating first depth information, based on the first image set, generating second depth information, based on the second image set, and generating a synthetic image of the first image set and the second image set, based on the first depth information and the second depth information.

IPC Classes  ?

  • G06T 7/571 - Depth or shape recovery from multiple images from focus
  • G06T 7/593 - Depth or shape recovery from multiple images from stereo images
  • H04N 13/218 - Image signal generators using stereoscopic image cameras using a single 2D image sensor using spatial multiplexing
  • H04N 13/271 - Image signal generators wherein the generated image signals comprise depth maps or disparity maps
  • H04N 23/80 - Camera processing pipelines; Components thereof
  • H04N 25/702 - SSIS architectures characterised by non-identical, non-equidistant or non-planar pixel layout

20.

MEMORY DEVICE RELATED TO PERFORMING A PROGRAM OPERATION ON MEMORY CELLS

      
Application Number 18583632
Status Pending
Filing Date 2024-02-21
First Publication Date 2024-06-13
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Choi, Hyeok Jun
  • Park, Hee Sik
  • Jeong, Seung Geun

Abstract

Provided herein is a memory device for performing a program operation on memory cells. The memory device include a plurality of memory cells configured to store data, a voltage generator configured to apply program voltages to a word line coupled to the plurality of memory cells during a program operation in which the plurality of memory cells are programmed to a plurality of program states, a cell speed determiner configured to determine a program speed of the plurality of memory cells depending on a number of pulses for the program voltages applied to the word line while the program operation is being performed, and a program manager configured to change a condition for remaining program operations depending on the program speed determined by the cell speed determiner.

IPC Classes  ?

  • G11C 16/10 - Programming or data input circuits
  • G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • G11C 16/08 - Address circuits; Decoders; Word-line control circuits
  • G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention

21.

DATA STORAGE DEVICE, MEMORY CONTROLLER AND METHOD OF OPERATING THE SAME

      
Application Number 18329423
Status Pending
Filing Date 2023-06-05
First Publication Date 2024-06-13
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Ji, Seung Hun
  • Song, Min O
  • Lee, Jae Il

Abstract

A data storage device includes a storage and a memory controller. The storage is configured to store data. The memory controller generates meta-data including a mapping relationship between a logical address used in an external device and a physical address used in the storage. The memory controller generates a normal meta-slice having a first size including the meta-data in a first operation mode. The memory controller stores a meta-page including the normal meta-slice in the storage. The memory controller generates a modified meta-slice having a second size as a part of the normal meta-slice in the second operation mode. The memory controller stores a meta-page including the modified meta-slice and context data corresponding to size information of the modified meta-slice in the storage. The memory controller restores the meta-data based on the context data in a power-on mode.

IPC Classes  ?

  • G06F 11/14 - Error detection or correction of the data by redundancy in operation, e.g. by using different operation sequences leading to the same result
  • G06F 12/02 - Addressing or allocation; Relocation

22.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

      
Application Number 18319260
Status Pending
Filing Date 2023-05-17
First Publication Date 2024-06-13
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Kim, Chul Young
  • Baek, Ji Yeon
  • Yun, Kyung Sung
  • Lee, Kyung Jin
  • Jung, Sul Gi

Abstract

A semiconductor device includes: a first gate structure including a cell region and a contact region; a channel structure located in the cell region of the first gate structure; and a supporter located in the contact region of the first gate structure.

IPC Classes  ?

  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
  • H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout

23.

MEMORY APPARATUS AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME

      
Application Number 18583294
Status Pending
Filing Date 2024-02-21
First Publication Date 2024-06-13
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Choi, Heeeun
  • Jeong, Yeong Han

Abstract

A memory apparatus includes an address decoding circuit configured to output a test redundancy address based on an address that is transmitted from a memory controller; and a redundancy address check circuit configured to determine whether the test redundancy address is replacing a failed address, in order to perform an ECC test operation by using the test redundancy address.

IPC Classes  ?

  • G11C 29/42 - Response verification devices using error correcting codes [ECC] or parity check
  • G11C 29/00 - Checking stores for correct operation; Testing stores during standby or offline operation
  • G11C 29/18 - Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
  • G11C 29/36 - Data generation devices, e.g. data inverters

24.

IMAGE SENSING DEVICE AND METHOD FOR MANUFACTURING THE SAME

      
Application Number 18365065
Status Pending
Filing Date 2023-08-03
First Publication Date 2024-06-13
Owner SK hynix Inc. (Republic of Korea)
Inventor Kim, Won Jin

Abstract

A method for manufacturing an image sensing device includes forming a grid structure over a semiconductor substrate to provide spaces for disposing color filters, forming first color filters, second color filters, third color filters in some of the spaces defined by the grid structure, the first color filters, the second color filters, and the third color filters configured to transmit light corresponding to a first color, a second color, and a third color, respectively, forming an overcoating layer to cover the first to third color filters, the overcoating layer filling remaining spaces of the spaces defined by the grid structure, the remaining spaces free of the first to third color filters, and forming microlenses over the overcoating layer.

IPC Classes  ?

25.

MEMORY DEVICE INCLUDING MEMORY PACKAGE AND MEMORY SYSTEM INCLUDING THE MEMORY DEVICE

      
Application Number 18328781
Status Pending
Filing Date 2023-06-05
First Publication Date 2024-06-13
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Kang, Sung Geun
  • Shim, In Bo
  • Jin, Su Il
  • Choi, Eun Kyu

Abstract

A memory system includes a memory device and a memory controller for providing data to the memory device based on a clock signal. The memory device includes a first memory group; a second memory group; an internal clock generator for generating a first internal clock signal and a second internal clock signal, which respectively correspond to a first period and a second period of the clock signal; and a data distributor for providing the data respectively to the first memory group and the second memory group, based on the first internal clock signal and the second internal clock signal.

IPC Classes  ?

  • G11C 7/22 - Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
  • G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers

26.

STORAGE SYSTEM AND METHOD FOR REDUCING OVERHEAD OF SNAPSHOT

      
Application Number 18078574
Status Pending
Filing Date 2022-12-09
First Publication Date 2024-06-13
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Kim, Jongryool
  • Lim, Hyung Jin
  • Lo, Timothy
  • Lee, Jaewoong

Abstract

Embodiments of the present invention provide an architecture of a large-scale storage system supporting snapshot. The system includes a storage; and a storage system coupled to the server through a network. The storage system includes: at least one storage device coupled to the server through the network; and a computing component coupled between the storage device and the network and configured to: generate snapshot data based on data for backup, which is stored in the storage device; compact the snapshot data; and transfer, to the storage, the compacted snapshot data through a storage client interface for the storage.

IPC Classes  ?

  • G06F 16/11 - File system administration, e.g. details of archiving or snapshots

27.

APPARATUS FOR MEASURING WAFER BONDING STRENGTH AND METHOD OF OPERATING THE APPARATUS AND METHOD OF MEASURING WAFER BONDING STRENGTH

      
Application Number 18475204
Status Pending
Filing Date 2023-09-27
First Publication Date 2024-06-13
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Park, Jung Hwan
  • Lee, Ji Hye

Abstract

An apparatus for measuring wafer bonding strength may include a wafer fixer and measuring unit. The wafer fixer may be configured to fix bonded wafers. The measuring unit may be configured to measure bonding strength of the bonded wafers. The measuring unit may include a blade, a driver and a sensor. The blade may apply a force to an interface between the bonded wafers to separate the bonded wafers from each other. The driver may provide the blade with a driving force. The sensor may measure the force applied to the blade.

IPC Classes  ?

  • G01N 3/16 - Investigating strength properties of solid materials by application of mechanical stress by applying steady tensile or compressive forces applied through gearing
  • G01N 3/04 - Chucks

28.

SEMICONDUCTOR DEVICE AND OPERATING METHOD OF SEMICONDUCTOR DEVICE

      
Application Number 18296373
Status Pending
Filing Date 2023-04-06
First Publication Date 2024-06-06
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Han, Chang Hyun
  • Sung, Moon Soo

Abstract

A semiconductor device may include: a cell array including memory cells connected to local word lines; pass transistors that connect global word lines and the local word lines in response to a block selection signal; an operation voltage supplying circuit that applies a read voltage or a pass voltage to the global word lines; and a well bias supplying circuit that, during a read operation, applies a well bias having a negative level to a well region of the pass transistor connected to a selected local word line, in a discharge period in which an unselected local word line is discharged.

IPC Classes  ?

  • G11C 16/08 - Address circuits; Decoders; Word-line control circuits
  • G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • G11C 16/14 - Circuits for erasing electrically, e.g. erase voltage switching circuits
  • G11C 16/26 - Sensing or reading circuits; Data output circuits

29.

MASTER DEVICE IDENTIFYING ADDRESS OF SLAVE DEVICE, ELECTRONIC DEVICE INCLUDING THE SAME, AND OPERATING METHOD OF ELECTRONIC DEVICE

      
Application Number 18299006
Status Pending
Filing Date 2023-04-11
First Publication Date 2024-06-06
Owner SK hynix Inc. (Republic of Korea)
Inventor Shin, Woong Sik

Abstract

A master device identifying the address of the slave device may, when identifying a slave device selected from a candidate group including a plurality of slave devices performing the same operation but having different addresses, store an address list including an address of each of a plurality of slave devices included in the candidate group, may transmit an address signal corresponding to each of the addresses included in the address list to a serial bus, and may identify the address of the slave device based on a level of an identification signal corresponding to the address signal.

IPC Classes  ?

  • G06F 13/362 - Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
  • G06F 13/42 - Bus transfer protocol, e.g. handshake; Synchronisation

30.

SEMICONDUCTOR SYSTEM

      
Application Number 18301441
Status Pending
Filing Date 2023-04-17
First Publication Date 2024-06-06
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Kwak, Kang Sub
  • Yoon, Sang Sic

Abstract

A semiconductor device includes a driving signal generation circuit configured to generate a pull-up driving signal that is enabled when a data clock input control signal is input during a normal operation, configured to generate a pull-down driving signal that is enabled when any one of a write signal and a read signal is input, and configured to generate the pull-down driving signal that is enabled after a set interval when a synchronization signal is input, and a sync enable signal generation circuit configured to generate a sync enable signal for receiving a data clock from a time at which the pull-up driving signal is enabled to a time at which the pull-down driving signal is enabled.

IPC Classes  ?

  • G11C 7/22 - Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
  • G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers

31.

MEMORY DEVICE AND STORAGE DEVICE INCLUDING THE SAME

      
Application Number 18301992
Status Pending
Filing Date 2023-04-18
First Publication Date 2024-06-06
Owner SK hynix Inc. (Republic of Korea)
Inventor You, Byoung Sung

Abstract

A memory device may include a plurality of subcores and a main core configured to control a subcore of the plurality of subcores to perform a preprocessing task of a memory operation in response to a preprocessing command.

IPC Classes  ?

  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline, look ahead
  • G06F 9/48 - Program initiating; Program switching, e.g. by interrupt
  • G06F 9/52 - Program synchronisation; Mutual exclusion, e.g. by means of semaphores

32.

CLOCK DISTRIBUTION NETWORK, SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME, AND CLOCK DISTRIBUTION METHOD THEREOF

      
Application Number 18314656
Status Pending
Filing Date 2023-05-09
First Publication Date 2024-06-06
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Kang, Ji Hyo
  • Kim, Kyung Hoon

Abstract

A clock distribution network includes a global clock tree and a local clock tree. When the clock distribution network is activated, the local clock tree is first activated, and the voltage levels of first and second output clock signals are set as a common mode voltage level. When the global clock tree is activated, the global clock tree generates first and second global clock signals from first and second input clock signals. The local clock tree generates the first and second output clock signals from the first and second global clock signals.

IPC Classes  ?

  • G06F 1/10 - Distribution of clock signals
  • G06F 1/08 - Clock generators with changeable or programmable clock frequency
  • H03K 19/0185 - Coupling arrangements; Interface arrangements using field-effect transistors only

33.

MEMORY DEVICE AND METHOD OF OPERATING THE SAME

      
Application Number 18320200
Status Pending
Filing Date 2023-05-19
First Publication Date 2024-06-06
Owner SK hynix Inc. (Republic of Korea)
Inventor Joo, Byoung In

Abstract

Provided herein is a memory device and a method of operating the same. The memory device includes memory cells coupled between a word line and bit lines, a main processor configured to control program-related voltages that are applied to the word line and the bit lines, a page buffer configured to store data sensed based on threshold voltages of the memory cells, a sensing circuit configured to perform a pass/fail check operation of comparing a sensing current corresponding to the sensed data with a reference current, and a sub-processor configured to control the page buffer and the sensing circuit to perform the pass/fail check operation in parallel with control of the program-related voltages while the main processor controls the program-related voltages.

IPC Classes  ?

  • G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
  • G11C 16/12 - Programming voltage switching circuits
  • G11C 16/24 - Bit-line control circuits

34.

MEMORY DEVICE AND METHOD OF OPERATING THE MEMORY DEVICE

      
Application Number 18321617
Status Pending
Filing Date 2023-05-22
First Publication Date 2024-06-06
Owner SK hynix Inc. (Republic of Korea)
Inventor Choi, Young Hwan

Abstract

An embodiment relates to a memory device and a method of operating the memory device. The memory device includes a memory block including a plurality of pages respectively corresponding to a plurality of word lines, peripheral circuits configured to apply operation voltages to the plurality of word lines and sequentially discharge or simultaneously discharge the plurality of word lines during a program operation, and control logic configured to control the peripheral circuits to sequentially discharge or simultaneously discharge the plurality of word lines based on whether a selected page among the plurality of pages is included in a weak page group during the program operation.

IPC Classes  ?

  • G11C 16/08 - Address circuits; Decoders; Word-line control circuits
  • G11C 16/10 - Programming or data input circuits
  • G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention

35.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SEMICONDUCTOR DEVICE

      
Application Number 18323999
Status Pending
Filing Date 2023-05-25
First Publication Date 2024-06-06
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Jang, Jung Shik
  • Park, In Su
  • Choi, Won Geun
  • Choi, Jung Dal
  • Kwak, Rho Gyu
  • Choi, Seok Min

Abstract

A semiconductor device including: a gate structure including stacked gate lines; an insulating core located in the gate structure and including a first long axis and a first short axis; a memory layer surrounding the insulating core; first channel pattern and a second channel pattern located facing each other along the first long axis, wherein the first channel pattern and the second channel pattern are located between the insulating core and the memory layer; and a capping layer located between the first channel pattern and the second channel pattern.

IPC Classes  ?

  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • H01L 23/528 - Layout of the interconnection structure
  • H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
  • H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 41/30 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
  • H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
  • H10B 43/30 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region

36.

MEMORY DEVICE PERFORMING READ OPERATION AND METHOD OF OPERATING THE SAME

      
Application Number 18325730
Status Pending
Filing Date 2023-05-30
First Publication Date 2024-06-06
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Sohn, Hyeok Chan
  • Shin, Beom Ju
  • Kim, Byung Ryul
  • Jo, Kang Wook

Abstract

The present technology relates to an electronic device. A memory device according to the present technology may include a first plane, a second plane, a data input/output circuit, and an encoder. The data input/output circuit may output data read from the first and second planes. The encoder may compress second data read from the second plane while first data read from the first plane is being output. The data input/output circuit may output the compressed second data after outputting the first data.

IPC Classes  ?

  • G11C 16/26 - Sensing or reading circuits; Data output circuits
  • G11C 16/12 - Programming voltage switching circuits

37.

STORAGE DEVICE AND OPERATING METHOD OF THE SAME

      
Application Number 18327892
Status Pending
Filing Date 2023-06-02
First Publication Date 2024-06-06
Owner SK hynix Inc. (Republic of Korea)
Inventor Um, Gi Pyo

Abstract

A storage device includes a nonvolatile memory for storing data; a volatile memory including a plurality of banks; a plurality of detection engines, each detection engine acquiring a detection value representing validity of data stored in a corresponding bank among the plurality of banks; and a nonvolatile memory controller for determining, when a write request for requesting a write operation of storing data stored in a selected bank among the plurality of banks into the nonvolatile memory and a first detection value of the selected bank are received, whether the write operation is to be performed, based on the first detection value and a second detection value acquired by a detection engine corresponding to the selected bank after the write request is received.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers
  • G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens

38.

IMAGE PROCESSING SYSTEM AND IMAGE PROCESSING METHOD

      
Application Number 18330290
Status Pending
Filing Date 2023-06-06
First Publication Date 2024-06-06
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Kim, Min Gi
  • Shin, Hyun Gu

Abstract

An image processing device that reduces grid pattern noise in a captured image and which improves captured image quality may include an image input circuit configured to receive pixel values from an image sensor, a kernel manager configured to generate kernels corresponding to a grid pattern determined based on an N×N array pattern of a color filter array included in the image sensor, a preprocessor configured to perform a blur operation based on the pixel values and the kernels and to amplify pattern pixel values corresponding to the grid pattern, among the pixel values, and a grid pattern detector configured to change pixel values irrelevant to the grid pattern, among the pixel values, to a preset value based on the kernels and to generate a grid image including only the grid pattern.

IPC Classes  ?

  • G06T 5/00 - Image enhancement or restoration
  • G06T 5/20 - Image enhancement or restoration by the use of local operators
  • G06V 10/56 - Extraction of image or video features relating to colour

39.

MEMORY DEVICE PERFORMING PROGRAM OPERATION AND METHOD OF OPERATING THE SAME

      
Application Number 18331689
Status Pending
Filing Date 2023-06-08
First Publication Date 2024-06-06
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Shin, Hyun Seob
  • Kwak, Dong Hun

Abstract

A semiconductor memory device includes a memory block, a peripheral circuit, and a control logic. The memory block includes memory cells. The peripheral circuit performs a program operation including program loops on selected memory cells. The control logic controls the peripheral circuit to apply a program inhibit voltage to bit lines connected to memory cells of a first group of target states, apply the program inhibit voltage to bit lines connected to memory cells on which programming is determined to be completed in a previous program loop, among memory cells of a second group of target states, and apply a program allowable voltage to bit lines connected to memory cells on which programming is determined to not be completed in the previous program loop, among the memory cells of the second group of target states. The first and second groups are determined by a number of current program loops.

IPC Classes  ?

  • G11C 16/10 - Programming or data input circuits
  • G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
  • G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention

40.

IMAGE PROCESSING DEVICE AND FACE DETECTION METHOD

      
Application Number 18332579
Status Pending
Filing Date 2023-06-09
First Publication Date 2024-06-06
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Han, Ji Hee
  • Kim, Jong Heon
  • Kim, Hun
  • Im, Jae Hyun
  • Cho, Ju Hyun

Abstract

An image processing device is provided, which has an improved face detection method. The image processing device may include a background manager, which determines a foreground region having a target object and a background region which excludes the target object based on image data that includes pixel values of pixels included in the image and depth map data that includes disparity values of the image pixels. A target object manager determines a reference position of the target object by counting foreground pixels included in the foreground region in a preset direction at a plurality of positions, and detecting the target object corresponding to a preset shape within a region of interest that is set based on the reference position.

IPC Classes  ?

  • G06V 40/16 - Human faces, e.g. facial parts, sketches or expressions
  • G06T 5/00 - Image enhancement or restoration
  • G06T 7/11 - Region-based segmentation
  • G06T 7/136 - Segmentation; Edge detection involving thresholding
  • G06T 7/194 - Segmentation; Edge detection involving foreground-background segmentation
  • G06T 7/50 - Depth or shape recovery
  • G06T 7/70 - Determining position or orientation of objects or cameras
  • G06V 10/25 - Determination of region of interest [ROI] or a volume of interest [VOI]

41.

MEMORY SYSTEM WITH SECURED PERFORMANCE AND RELIABILITY, MEMORY CONTROLLER AND METHOD OF OPERATING THE SAME

      
Application Number 18344893
Status Pending
Filing Date 2023-06-30
First Publication Date 2024-06-06
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Kim, Kwang Su
  • Park, Youn Won

Abstract

A memory system may include a storage device and a memory controller. The storage device may include a plurality of memory blocks. Each of the memory blocks may include a plurality of pages. The memory controller may perform a maintenance management operation including predetermined numbers of sub-operations performed for a first period in each first cycle on the storage device, wherein the memory controller is configured to increase a reservation number of the sub-operations when a first type command requested from an external device is processed at a time of triggering the sub-operations, and determine a trigger interval of the sub-operations based on the reservation number.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

42.

SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF

      
Application Number 18435272
Status Pending
Filing Date 2024-02-07
First Publication Date 2024-06-06
Owner SK hynix Inc. (Republic of Korea)
Inventor Lee, Dong Hwan

Abstract

There are provided a semiconductor memory device and a manufacturing method thereof. The semiconductor memory device includes: a gate stack structure including interlayer insulating layers and conductive patterns, which are alternately stacked in a vertical direction on a substrate; a plurality of channel structures penetrating the gate stack structure, each of the plurality of channel structures with one end portion protruding past a boundary of the gate stack structure; and a source layer formed on the gate stack structure. The protruding end portion of each of the plurality of channel structures extends into the source layer. The protruding end portion of each of the plurality of channel structures has a flat section.

IPC Classes  ?

  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
  • H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

43.

SEMICONDUCTOR DEVICE AND METHOD FOR PERFORMING CRACK DETECTION OPERATION

      
Application Number 18113964
Status Pending
Filing Date 2023-02-24
First Publication Date 2024-06-06
Owner SK hynix Inc. (Republic of Korea)
Inventor Kim, Hyun Seung

Abstract

A semiconductor device includes a first crack detection circuit configured to receive a first external detection signal and output the first external detection signal as a first internal detection signal through a first metal line or configured to receive the first internal detection signal through the first metal line and output the first internal detection signal as the first external detection signal, and a second crack detection circuit configured to receive the first internal detection signal and output the first internal detection signal as a second internal detection signal through a second metal line or configured to receive the second internal detection signal through the second metal line and output the second internal detection signal as the first internal detection signal.

IPC Classes  ?

  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer

44.

SEMICONDUCTOR DEVICE CAPABLE OF CHECKING DETERIORATION OF SELECT TRANSISTOR AND OPERATING METHOD THEREOF

      
Application Number 18299714
Status Pending
Filing Date 2023-04-13
First Publication Date 2024-06-06
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Choi, Hyung Jin
  • Yang, In Gon
  • Yoo, Young Seung

Abstract

A semiconductor device may include a memory cell array including a memory block including a plurality of memory strings connected between a plurality of bit lines and a common source line, a control circuit that generates a page buffer control signal, a voltage control signal, and a drive address signal, a page buffer group including a plurality of page buffers and configured to form each of the plurality of bit lines to a preset voltage level, and generate a threshold voltage variation result on the basis of a change in the voltage level of each of the plurality of bit lines, a voltage generation circuit that generates a threshold verification voltage and a pass voltage, and a line drive circuit that drives a plurality of select lines to a level of the threshold verification voltage, and drives a plurality of word lines to a level of the pass voltage, during the threshold voltage variation verification.

IPC Classes  ?

  • G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • G11C 16/10 - Programming or data input circuits
  • G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention

45.

METHOD AND DEVICE FOR APPLYING A BOKEH EFFECT TO IMAGE

      
Application Number 18301084
Status Pending
Filing Date 2023-04-14
First Publication Date 2024-06-06
Owner SK hynix Inc. (Republic of Korea)
Inventor Adachi, Yuuki

Abstract

An image processor determines a shape of a kernel applied to an image based on at least one of distance information or color information. The image processor generates a bokeh image in which at least a partial area of the image is blurred using the kernel.

IPC Classes  ?

  • G06T 5/00 - Image enhancement or restoration
  • G06T 5/20 - Image enhancement or restoration by the use of local operators
  • G06T 7/194 - Segmentation; Edge detection involving foreground-background segmentation
  • G06T 7/50 - Depth or shape recovery
  • G06T 7/90 - Determination of colour characteristics
  • G06V 40/16 - Human faces, e.g. facial parts, sketches or expressions

46.

STORAGE DEVICE DETERMINING MEMORY AREA TO WHICH DATA IS WRITTEN USING WRITE THROUGHPUT AND METHOD OF OPERATION

      
Application Number 18306163
Status Pending
Filing Date 2023-04-24
First Publication Date 2024-06-06
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Jung, Hoe Seung
  • Kim, Do Hyung
  • Lee, Joo Young
  • Hong, Sung Kwan

Abstract

A storage device may determine write throughput based on a plurality of write commands received from the outside of the storage device, and write target data write-requested from the outside to a first memory area including one or more of a plurality of first type memory blocks or a second memory area including one or more of a second type memory blocks according to whether the write throughput is greater than or equal to a threshold throughput. The first type memory blocks may operate at a higher speed than the second type memory blocks.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

47.

MEMORY SYSTEM WITH IMPROVED MAP TABLE UPDATE EFFICIENCY, MEMORY CONTROLLER THEREFOR, AND OPERATING METHOD THEREOF

      
Application Number 18308683
Status Pending
Filing Date 2023-04-28
First Publication Date 2024-06-06
Owner SK hynix Inc. (Republic of Korea)
Inventor Jang, Eun Soo

Abstract

A memory system may include a storage device, an external interface circuit configured to receive a write logical address associated with a write command and a storage location for mapping information and store the write logical address in the storage location; and a processor configured to determine the storage location at which the write logical address is to be stored within a map table and control the storage device to program write data associated with the write command, the map table storing map data between external logical addresses and physical addresses of the storage device.

IPC Classes  ?

  • G06F 12/1009 - Address translation using page tables, e.g. page table structures

48.

INTERNAL REFERENCE VOLTAGE GENERATION DEVICE

      
Application Number 18316972
Status Pending
Filing Date 2023-05-12
First Publication Date 2024-06-06
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Hong, Jae Hyeong
  • Lee, Jung Yeop
  • Koo, Bon Kwang
  • Kim, Heon Ki
  • Nam, Young Seok
  • Park, Young Jo
  • Ahn, Keun Seon
  • An, Soon Sung
  • Ok, Sung Hwa
  • Lee, Se Min
  • Lee, Seung Yeop
  • Jang, Nam Hea
  • Jang, Jun Seo
  • Joo, Ji Eun

Abstract

An internal reference voltage generation device may include a cell array including a plurality of cells which provide reference voltages of different levels. Each of the plurality of cells may include one of a plurality of divider resistors included in a resistor string; a transmission gate configured to output a voltage of a divider node which is connected to the one divider resistor, in response to a select signal; and a unit decoder configured to provide the select signal to the transmission gate.

IPC Classes  ?

  • G05F 1/56 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices

49.

STORAGE DEVICE AND THROTTLING OPERATION METHOD THEREOF

      
Application Number 18325130
Status Pending
Filing Date 2023-05-30
First Publication Date 2024-06-06
Owner SK hynix Inc. (Republic of Korea)
Inventor Jang, In Jong

Abstract

The present disclosure relates to an operation method of a storage device, which is for overcoming the instability of the storage device caused by throttling cancellation. An operation method of a memory controller may include: acquiring a temperature of a memory; determining, on the basis of the temperature of the memory, to start a throttling operation that reduces performance of the memory; determining whether the throttling operation is cancelled; and recovering the throttling operation, which alleviates instability of the memory caused by the throttling cancellation.

IPC Classes  ?

  • G06F 11/30 - Monitoring
  • G06F 11/07 - Responding to the occurrence of a fault, e.g. fault tolerance
  • G06F 11/14 - Error detection or correction of the data by redundancy in operation, e.g. by using different operation sequences leading to the same result

50.

MEMORY DEVICE PERFORMING ERASE OPERATION AND METHOD OF OPERATING THE SAME

      
Application Number 18325808
Status Pending
Filing Date 2023-05-30
First Publication Date 2024-06-06
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Mun, Yeong Jo
  • Kwak, Dong Hun

Abstract

A memory device, and a method of operating the memory device, includes a memory block, a peripheral circuit, an erase controller, and a parameter setter. The memory device includes a plurality of sub blocks. The peripheral circuit performs an erase operation on a target sub block among the plurality of sub blocks. The erase controller controls the peripheral circuit to perform the erase operation based on a default parameter or an optimal parameter according to a group to which the target sub block belongs among first, second, and third groups. The parameter setter sets the optimal parameter based on a result of the erase operation when the target sub block is included in the first group or the third group.

IPC Classes  ?

  • G11C 16/16 - Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
  • G11C 16/28 - Sensing or reading circuits; Data output circuits using differential sensing or reference cells, e.g. dummy cells
  • G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention

51.

MEMORY DEVICE PERFORMING SENSING OPERATION AND METHOD OF OPERATING THE SAME

      
Application Number 18325999
Status Pending
Filing Date 2023-05-31
First Publication Date 2024-06-06
Owner SK hynix Inc. (Republic of Korea)
Inventor Park, Se Chun

Abstract

The present technology relates to an electronic device. According to the present technology, a memory device may include a plurality of memory cells, a defect detector, and a test controller. The defect detector may generate defect information indicating a defect state in which a value of a cell current measured in a sensing operation on selected memory cells among the plurality of memory cells is less than a threshold value. The test controller may count fail bits from a result of a test operation performed on the selected memory cells using a test reference current in response to the defect information, and set a bit line voltage to be used in the sensing operation based on a comparison result between a number of fail bits detected in the test operation and a reference number.

IPC Classes  ?

  • G11C 29/12 - Built-in arrangements for testing, e.g. built-in self testing [BIST]

52.

METHOD OF OPERATING A CONTROLLER AND A MEMORY DEVICE RELATED TO RECOVERING DATA

      
Application Number 18327759
Status Pending
Filing Date 2023-06-01
First Publication Date 2024-06-06
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Park, Tae Hun
  • Kwak, Dong Hun
  • Shin, Hyun Seob

Abstract

A method of operating a controller includes transmitting a program command to a memory device, receiving a message indicating that a program operation corresponding to the program command is failed from the memory device, and transmitting an erase command for performing an erase operation on a page corresponding to the program command to the memory device in response to the message.

IPC Classes  ?

  • G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
  • G11C 16/14 - Circuits for erasing electrically, e.g. erase voltage switching circuits
  • G11C 16/26 - Sensing or reading circuits; Data output circuits
  • G11C 29/52 - Protection of memory contents; Detection of errors in memory contents

53.

STORAGE DEVICE FOR SETTING OPERATION PARAMETERS FOR RANDOM ACCESS MEMORY UPON POWER-ON AND OPERATION

      
Application Number 18335137
Status Pending
Filing Date 2023-06-15
First Publication Date 2024-06-06
Owner SK hynix Inc. (Republic of Korea)
Inventor Lee, Sung Min

Abstract

A storage device may execute, upon power-on, a training operation on a pattern data chunk a number of times, and update one or more operation parameters of the random access memory when the number of maximum error bits generated during the training operation is equal to or greater than a set threshold number of bits.

IPC Classes  ?

  • G06F 11/07 - Responding to the occurrence of a fault, e.g. fault tolerance

54.

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

      
Application Number 18340035
Status Pending
Filing Date 2023-06-23
First Publication Date 2024-06-06
Owner SK hynix Inc. (Republic of Korea)
Inventor Kim, Song

Abstract

A semiconductor device includes a lower structure; a vertical conductive line extending in a first direction which is perpendicular to a surface of the lower structure; a reservoir capacitor disposed over the lower structure to be spaced apart from the vertical conductive line; a bridge horizontal layer disposed between the vertical conductive line and the reservoir capacitor and extending horizontally in a second direction which is parallel to the surface of the lower structure; and a pair of horizontal layers extending in a third direction intersecting the bridge horizontal layer with the bridge horizontal layer interposed therebetween.

IPC Classes  ?

  • H10B 12/00 - Dynamic random access memory [DRAM] devices
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched

55.

SEMICONDUCTOR DIE STACK STRUCTURE

      
Application Number 18346674
Status Pending
Filing Date 2023-07-03
First Publication Date 2024-06-06
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Kim, Sung Kyu
  • Kim, Jong Yeon
  • Na, Song
  • Lim, Sang Hyuk
  • Kwon, Jong Oh
  • Park, Jin Woo

Abstract

A semiconductor die stack structure includes a base die, a plurality of semiconductor die stack units, and bumps. Each of the plurality of semiconductor die stack units includes a lower semiconductor die and an upper semiconductor die. Each of the lower semiconductor die and the upper semiconductor die includes a body and a front-side pad structure. The front-side pad structure includes a front-side pad seed layer and a front-side pad pattern. The front-side pad pattern includes a first front-side pad portion, a second front-side pad portion, and a third front-side pad portion. The first front-side pad portion and the second front-side pad portion forms a staircase. The first front-side pad portion and the third front-side pad form a reverse staircase. The first front-side pad portion, the second front-side pad portion, and the third front-side pad include a same metal.

IPC Classes  ?

  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 23/373 - Cooling facilitated by selection of materials for the device
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body

56.

IMAGE SENSING DEVICE

      
Application Number 18355238
Status Pending
Filing Date 2023-07-19
First Publication Date 2024-06-06
Owner SK hynix Inc. (Republic of Korea)
Inventor Cho, Sung Wook

Abstract

An image sensing device includes a pixel region provided in a first portion of a semiconductor substrate such that photoelectric conversion elements for converting incident light into an electrical signal are disposed in the first portion of the semiconductor substrate, a dummy region located outside the pixel region to surround the pixel region and provided in a second portion of the semiconductor substrate without including a photoelectric conversion element, first microlenses disposed over the first portion of the semiconductor substrate and in the pixel region, the first microlenses configured to converge the incident light onto corresponding photoelectric conversion elements, second microlenses disposed over the second portion of the semiconductor substrate and in the dummy region, the second microlenses isolated from the first microlenses, and at least one alignment pattern disposed in the second portion of semiconductor substrate so as to be aligned with the second microlenses.

IPC Classes  ?

57.

IMAGE SENSING DEVICE AND METHOD FOR MANUFACTURING THE SAME

      
Application Number 18365423
Status Pending
Filing Date 2023-08-04
First Publication Date 2024-06-06
Owner SK hynix Inc. (Republic of Korea)
Inventor Kim, Won Jin

Abstract

An image sensing device includes a plurality of first color filters configured to transmit light corresponding to a first color, a plurality of second color filters configured to transmit light corresponding to a second color, a plurality of third color filters configured to transmit light corresponding to a third color, a plurality of fourth color filters configured to transmit light corresponding to a fourth color, and a grid structure disposed between the first to fourth color filters and structured to block light from one color filter to another color filter. Some color filters from among the first to fourth color filters are formed to have a lower height than the grid structure, and the remaining color filters are formed to have a higher height than the grid structure.

IPC Classes  ?

58.

METHOD FOR FABRICATING THE SEMICONDUCTOR MEMORY DEVICE

      
Application Number 18438894
Status Pending
Filing Date 2024-02-12
First Publication Date 2024-06-06
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Lee, Yu Jeong
  • Yun, Dae Hwan
  • Choi, Gil Bok

Abstract

A method for fabricating a semiconductor memory device may include the steps of: forming a stacked body on a source layer by alternately stacking a plurality of interlayer dielectric layers and a plurality of gate sacrificial layers; forming a plurality of channel holes through the stacked body, the channel holes each having a lower end extended into the source layer; forming a channel layer along the surfaces of the channel holes, the channel layer including a first region formed in the stacked body and a second region formed in the source layer; and forming a channel passivation layer in the first region to scale down the thickness of the channel layer of the first region.

IPC Classes  ?

  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
  • H01L 29/04 - Semiconductor bodies characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
  • H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form

59.

SEMICONDUCTOR DEVICE INCLUDING TRANSISTOR INCLUDING HORIZONTAL GATE STRUCTURE AND VERTICAL CHANNEL LAYER AND METHOD FOR FABRICATING THE SAME

      
Application Number 18443297
Status Pending
Filing Date 2024-02-16
First Publication Date 2024-06-06
Owner SK hynix Inc. (Republic of Korea)
Inventor Yoon, Young Gwang

Abstract

A semiconductor device includes: a first stacked structure including a first lower dielectric layer, a first horizontal gate structure, and a first upper dielectric layer stacked vertically; a second stacked structure including a second lower dielectric layer, a second horizontal gate structure, and a second upper dielectric layer stacked vertically, and having a first side facing a first side of the first stacked structure; a first channel layer formed on the first side of the first stacked structure; a second channel layer formed on the first side of the second stacked structure; a lower electrode layer commonly coupled to lower ends of the first and second channel layers between the first and second stacked structures; a first upper electrode layer coupled to an upper end of the first channel layer; and a second upper electrode layer coupled to an upper end of the second channel layer.

IPC Classes  ?

  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 29/66 - Types of semiconductor device

60.

METHOD OF PREDICTING AN OPTIMAL PROCESS CONDITION MODEL TO IMPROVE A YIELD OF A SEMICONDUCTOR FABRICATION PROCESS AND METHOD OF CONTROLLING A SEMICONDUCTOR FABRICATION PROCESS BASED ON AN OPTIMAL PROCESS CONDITION MODEL

      
Application Number 18295252
Status Pending
Filing Date 2023-04-03
First Publication Date 2024-05-30
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Han, Jin Hee
  • Ma, Seong Min
  • Lee, Deuk Nyeon
  • Lee, Chang Hwan

Abstract

In a method of predicting an optimal process condition model for a semiconductor fabrication process, process parameter information of a unit process in the semiconductor fabrication process may be collected. First characteristics information of objects to be processed before the unit process and second characteristic information of processed objects after the unit process may be extracted. Process global uniformity (PGU) may be calculated using the first characteristic information and the second characteristic information. A data set of the unit process may be created using the process parameter information and the PGU. A virtual process environment function of the unit process may be created using the data set. The optimal process condition model of the unit process may be created using the virtual process environment function.

IPC Classes  ?

  • G05B 19/418 - Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control (DNC), flexible manufacturing systems (FMS), integrated manufacturing systems (IMS), computer integrated manufacturing (CIM)

61.

STORAGE DEVICE CONTROLLING TARGET OPERATION BASED ON COLLECTED PERFORMANCE INFORMATION AND OPERATING METHOD THEREOF

      
Application Number 18297551
Status Pending
Filing Date 2023-04-07
First Publication Date 2024-05-30
Owner SK hynix Inc. (Republic of Korea)
Inventor Kim, Jin Woo

Abstract

A storage device may store performance information of the storage device in a target memory area including one or more of a plurality of memory blocks on determination that a set target condition is satisfied. And the storage device may control a target operation based on the stored performance information.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

62.

SEMICONDUCTOR DEVICE INCLUDING BONDING PAD

      
Application Number 18307816
Status Pending
Filing Date 2023-04-27
First Publication Date 2024-05-30
Owner SK hynix Inc. (Republic of Korea)
Inventor Lee, Byung Ho

Abstract

A semiconductor device includes: a lower semiconductor structure including a plurality of first lower electrode bonding pads, a plurality of second lower electrode bonding pads, and a lower connection pattern connecting the plurality of first lower electrode bonding pads to each other while being connected to a first voltage; and an upper semiconductor structure disposed over the lower semiconductor structure and including a plurality of first upper electrode bonding pads, a plurality of second upper electrode bonding pads, and an upper connection pattern connecting the plurality of second upper electrode bonding pads to each other while being connected to a second voltage different from the first voltage, wherein the plurality of first lower electrode bonding pads are bonded to the plurality of first upper electrode bonding pads, respectively, and the plurality of second lower electrode bonding pads are bonded to the plurality of second upper electrode bonding pads, respectively.

IPC Classes  ?

  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices

63.

STORAGE DEVICE FOR REDUCING DELAY OF PARITY OPERATION, CONTROLLER AND METHOD FOR OPERATING CONTROLLER

      
Application Number 18309796
Status Pending
Filing Date 2023-04-29
First Publication Date 2024-05-30
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Choi, Hyo Jin
  • Lee, Kwan Su

Abstract

A first processor manages state information of a buffer area of a buffer memory used as a parity area in a parity operation mode and outputs a control signal according to the state information, and a second processor which performs a parity operation using the buffer area performs the parity operation according to the control signal of the first processor.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

64.

SEMICONDUCTOR DEVICE FOR PROGRAMMING OR ERASING SELECT TRANSISTORS AND METHOD OF OPERATING THE SAME

      
Application Number 18310290
Status Pending
Filing Date 2023-05-01
First Publication Date 2024-05-30
Owner SK hynix Inc. (Republic of Korea)
Inventor Choi, Hyung Jin

Abstract

In a semiconductor memory device, a program voltage is applied to select lines, which are coupled to corresponding select transistors included in a plurality of string groups. A verify operation on the select transistors is then performed, which simultaneously checks the operation of first select transistors included in a first string group and second select transistors included in a second string group.

IPC Classes  ?

  • G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
  • G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • G11C 16/16 - Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups

65.

SEMICONDUCTOR DEVICE PERFORMING PROGRAM OPERATION AND OPERATING METHOD THEREOF

      
Application Number 18310760
Status Pending
Filing Date 2023-05-02
First Publication Date 2024-05-30
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Choi, Hyung Jin
  • Park, Se Chun

Abstract

A method of operating a semiconductor device includes: starting a program operation on selected memory cells among a plurality of memory cells in response to a program command; suspending the program operation in response to a program suspend command; and performing a pre-verify operation by using a modified verify voltage in response to a program resume command.

IPC Classes  ?

  • G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
  • G11C 16/08 - Address circuits; Decoders; Word-line control circuits
  • G11C 16/10 - Programming or data input circuits

66.

MEMORY DEVICE INCLUDING ERROR CORRECTION DEVICE

      
Application Number 18314147
Status Pending
Filing Date 2023-05-09
First Publication Date 2024-05-30
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Jeong, Jin Ho
  • Kim, Dae Suk
  • Yoon, Sang Woo
  • Rim, A Ram
  • Jang, Mun Seon

Abstract

A memory device includes a memory cell area including a plurality of cell blocks divided into a plurality of normal cell blocks, at least one ECC cell block, and at least one redundancy cell block, the plurality of cell blocks being configured to output data and error correction codes; an error correction circuit configured to generate error-corrected data by correcting errors in the data using the error correction codes; a first switch group configured to output the error-corrected data while performing, according to first repair control information, a shifting operation on the error-corrected data; and a second switch group configured to transfer the data from the memory cell area to the error correction circuit while performing, according to second repair control information, a zero-padding operation on the data output from one of the cell blocks.

IPC Classes  ?

  • G11C 29/52 - Protection of memory contents; Detection of errors in memory contents
  • G11C 29/00 - Checking stores for correct operation; Testing stores during standby or offline operation
  • G11C 29/44 - Indication or identification of errors, e.g. for repair

67.

IMAGE PROCESSING DEVICE AND IMAGE PROCESSING METHOD

      
Application Number 18316121
Status Pending
Filing Date 2023-05-11
First Publication Date 2024-05-30
Owner SK hynix Inc. (Republic of Korea)
Inventor Choi, Jun Hyeok

Abstract

An image processing device may include: a target pixel set determiner for determining a target pixel set, among a plurality of Phase Detection Auto Focus (PDAF) pixel sets, based on average values and variance values of pixel values output from a plurality of pixels corresponding to a kernel set based on each of the plurality of PDAF pixel sets, wherein the average values and the variance values respectively correspond to colors of color filters included in the plurality of pixels; and a pixel value corrector for converting pixel values of the target pixel set into first pixel values corresponding to a predetermined color and correcting the first pixel values to second pixel values corresponding to an arrangement pattern of the plurality of pixels based on pixel values of a plurality of adjacent pixels adjacent to the target pixel set.

IPC Classes  ?

  • H04N 1/60 - Colour correction or control
  • G06V 10/56 - Extraction of image or video features relating to colour
  • G06V 10/75 - Image or video pattern matching; Proximity measures in feature spaces using context analysis; Selection of dictionaries
  • H04N 25/11 - Arrangement of colour filter arrays [CFA]; Filter mosaics

68.

MEMORY DEVICE PERFORMING READ OPERATION AND METHOD OF OPERATING THE SAME

      
Application Number 18318546
Status Pending
Filing Date 2023-05-16
First Publication Date 2024-05-30
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Jung, Jae Yeop
  • Kwak, Dong Hun

Abstract

A memory device includes a memory cell array comprising a plurality of regions. Each region is a segment or portion of a page. Each region is connected to dummy word lines and word lines. A voltage generator provides a read voltage for reading a memory cell connected to a selected word line, and provides a pass voltage for turning on a dummy memory cell included in a region corresponding to the selected region. A read operation controller controls the voltage generator to apply the pass voltage to the dummy word lines and apply the read voltage to the selected word line.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

69.

MEMORY DEVICE AND METHOD OF OPERATING THE SAME

      
Application Number 18318725
Status Pending
Filing Date 2023-05-17
First Publication Date 2024-05-30
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Jeong, Chan Hui
  • Kwak, Dong Hun
  • Park, Se Chun

Abstract

The present technology relates to an electronic device. According to the present technology, a memory device may include a plurality of memory cells, a peripheral circuit, and a control logic. The peripheral circuit may perform a fail bit detection operation on memory cells selected from among the plurality of memory cells. The control logic may control the peripheral circuit to set target parameters related to a main operation based on a comparison result between a fail bit detection time measured in the fail bit detection operation and a reference time, and perform the main operation on the selected memory cells based on the target parameters.

IPC Classes  ?

  • G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
  • G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • G11C 16/10 - Programming or data input circuits
  • G11C 16/14 - Circuits for erasing electrically, e.g. erase voltage switching circuits
  • G11C 16/32 - Timing circuits

70.

AUTOMOTIVE SYSTEM, METHOD OF OPERATING THE SAME, AND MEMORY DEVICE FOR THE SAME

      
Application Number 18320053
Status Pending
Filing Date 2023-05-18
First Publication Date 2024-05-30
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Kim, Tae Ha
  • Kim, Jung Ae

Abstract

An automotive system includes a memory device and a controller. The memory device is installed in an automobile. The controller controls the memory device and an electronic device in the automobile. The controller controls the memory device to process a background operation during a time limit when a background operation trigger event may be detected.

IPC Classes  ?

  • G06F 9/54 - Interprogram communication
  • G06F 1/3296 - Power saving characterised by the action undertaken by lowering the supply or operating voltage

71.

SEMICONDUCTOR DEVICE AND METHOD OF TESTING THE SEMICONDUCTOR DEVICE

      
Application Number 18320088
Status Pending
Filing Date 2023-05-18
First Publication Date 2024-05-30
Owner SK hynix Inc. (Republic of Korea)
Inventor Lee, Jun Hyuk

Abstract

Provided herein is a semiconductor device and a method of testing the semiconductor device. The method of operating a semiconductor device includes initializing a latch included in a page buffer, applying a read pass voltage to a plurality of word lines, allowing at least one of the plurality of word lines to float, and performing a sensing operation on the page buffer.

IPC Classes  ?

  • G11C 29/44 - Indication or identification of errors, e.g. for repair
  • G11C 29/12 - Built-in arrangements for testing, e.g. built-in self testing [BIST]
  • G11C 29/18 - Address generation devices; Devices for accessing memories, e.g. details of addressing circuits

72.

STORAGE DEVICE AND OPERATING METHOD THEREOF

      
Application Number 18323507
Status Pending
Filing Date 2023-05-25
First Publication Date 2024-05-30
Owner SK hynix Inc. (Republic of Korea)
Inventor Lee, Seok Min

Abstract

A storage device includes: an embedding vector manager for determining an estimated access frequency of each of a plurality of embedding vectors, based on a learning data set, and dividing the plurality of embedding vectors into a plurality of embedding vector groups, based on an order of the estimated access frequencies; and a plurality of memory cell arrays for each storing embedding vectors included in any one embedding vector group among the plurality of embedding vector groups.

IPC Classes  ?

  • G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
  • G11C 7/16 - Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters

73.

INTERWORKING METHOD EXTERNAL DEVICE AND STORAGE DEVICE

      
Application Number 18328780
Status Pending
Filing Date 2023-06-05
First Publication Date 2024-05-30
Owner SK hynix Inc. (Republic of Korea)
Inventor Jang, In Jong

Abstract

The present disclosure relates to a memory controller which supports an interworking method for a test between an external device and a storage device, and a host. The memory controller proposed in the present disclosure may include a first interface configured to communicate with an external device, a second interface configured to communicate with a memory, a command queue configured to store commands received from the external device and a processor configured to perform a control operation according to a command stored in the command queue, and suspend the performance of the control operation according to the command for a waiting time corresponding to a value of a mutex counter for the command, when a mutex flag for the command is activated.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

74.

MEMORY CONTROLLER, STORAGE DEVICE INCLUDING THE MEMORY CONTROLLER, AND METHOD OF OPERATING THE MEMORY CONTROLLER AND THE STORAGE DEVICE

      
Application Number 18404695
Status Pending
Filing Date 2024-01-04
First Publication Date 2024-05-30
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Kim, Do Hun
  • Lee, Kwang Sun
  • Jeong, Gi Jo

Abstract

The present technology relates to an electronic device. According to the present technology, a storage device having an improved operation speed may include a nonvolatile memory device, a main memory configured to temporarily store data related to controlling the nonvolatile memory device, and a memory controller configured to control the nonvolatile memory device and the main memory under control of an external host. The main memory may aggregate and process a number of write transactions having continuous addresses, among write transactions received from the memory controller, equal to a burst length unit of the main memory.

IPC Classes  ?

  • G06F 12/0802 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
  • G06F 3/06 - Digital input from, or digital output to, record carriers
  • G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens

75.

THREE-DIMENSIONAL SEMICONDUCTOR DEVICE HAVING A SUPPORT PATTERN IN CONTACT WITH A SIDE SURFACE OF A CONTACT PLUG

      
Application Number 18432491
Status Pending
Filing Date 2024-02-05
First Publication Date 2024-05-30
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Lee, Go Hyun
  • Kim, Jae Taek
  • Jung, Hye Yeong

Abstract

The semiconductor device includes a substrate having a cell area and a via area; a transistor and a logic interconnection disposed over the substrate; a lower insulating layer covering the transistor and the logic interconnection; a lower conductive layer on the lower insulating layer in the cell area; a support pattern disposed on the lower insulating layer in the via area; a lower via plug having a side surface in contact with the support pattern and a bottom surface in contact with the logic interconnection; a word line stack disposed on the lower conductive layer in the cell area; an dielectric layer stack disposed on the support pattern in the via area; a vertical channel pillar penetrating the word line stack to be connected to the lower conductive layer; and an upper via plug penetrating the dielectric layer stack to be vertically aligned with the lower via plug.

IPC Classes  ?

  • H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 23/535 - Arrangements for conducting electric current within the device in operation from one component to another including internal interconnections, e.g. cross-under constructions
  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

76.

FUSE LATCH OF SEMICONDUCTOR DEVICE FOR LATCHING DATA OF A REPAIR FUSE CELL

      
Application Number 18432663
Status Pending
Filing Date 2024-02-05
First Publication Date 2024-05-30
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Seo, Jae Hwan
  • Jung, Chul Moon

Abstract

A fuse latch of a semiconductor device including PMOS transistors and NMOS transistors includes a data transmission circuit configured to transmit data to a first node and a second node in response to a first control signal, a latch circuit configured to latch the data received from the data transmission circuit through the first node and the second node, and a data output circuit configured to output the data latched by the latch circuit in response to a second control signal. NMOS transistors contained in the data transmission circuit, the latch circuit, and the data output circuit may be formed in first, fourth, and fifth active regions, PMOS transistors are formed in second and third active regions, and the first to fifth active regions are sequentially arranged in a first direction.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

77.

METHOD FOR FABRICATING EUV MASK AND PHOTOMASK USING THE EUV MASK

      
Application Number 18432842
Status Pending
Filing Date 2024-02-05
First Publication Date 2024-05-30
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Park, Suk Won
  • Park, Chan Ha
  • Lee, Sang Ho
  • Lim, Chang Moon
  • Jee, Tae Kwon

Abstract

An Extreme UltraViolet (EUV) mask includes: a reflective layer over a substrate; a capping layer including a porous hydrogen trapping layer over the reflective layer; and an absorption layer over the capping layer.

IPC Classes  ?

78.

MEMORY SYSTEM AND OPERATING METHOD OF THE MEMORY SYSTEM

      
Application Number 18436025
Status Pending
Filing Date 2024-02-08
First Publication Date 2024-05-30
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Park, Chang Kyun
  • Koh, Young Sik
  • Park, Seung Jin
  • Lee, Dong Hyun

Abstract

A memory system includes a memory device including an interface circuit and a semiconductor memory, and a controller to generate a command for controlling the memory device. The interface circuit receives the command from the controller; determines whether the command is for the semiconductor memory or the interface circuit; and when it is determined that the command is for the interface circuit, performs a blocking operation to block transfer of the command between the interface circuit and the semiconductor memory and performs an internal operation of the interface circuit. The internal operation includes a signal controlling operation, a training operation, a read operation, an on-die termination operation, a ZQ calibration operation, or a driving force control operation.

IPC Classes  ?

  • G11C 8/18 - Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
  • G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
  • G11C 7/22 - Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
  • G11C 11/4076 - Timing circuits
  • G11C 16/32 - Timing circuits

79.

STORAGE DEVICE FOR EXECUTING BACKGROUND OPERATION BASED ON POWER STATE AND OPERATING METHOD THEREOF

      
Application Number 18172477
Status Pending
Filing Date 2023-02-22
First Publication Date 2024-05-30
Owner SK hynix Inc. (Republic of Korea)
Inventor Jang, In Jong

Abstract

A storage device may enter a plurality of intermediate power states sequentially while entering from a first power state to a second power state. The storage device may check background flag information while entering each of the plurality of intermediate power states, and execute a target background operation, executable in a first intermediate power state, based on the background flag information.

IPC Classes  ?

  • G06F 1/3225 - Monitoring of peripheral devices of memory devices
  • G06F 1/3296 - Power saving characterised by the action undertaken by lowering the supply or operating voltage

80.

TEST CIRCUIT OF SEMICONDUCTOR APPARATUS AND TEST SYSTEM INCLUDING THE SAME

      
Application Number 18174658
Status Pending
Filing Date 2023-02-27
First Publication Date 2024-05-30
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Jung, Jong Seok
  • Kwon, Chan Keun
  • Kim, Jong Seok
  • Lee, Young Kwan

Abstract

A test circuit of a semiconductor apparatus includes a first resistor, a second resistor and a feed-back loop circuit. The first resistor is coupled between a pad and a test element. The second resistor is coupled to the first resistor in a parallel manner. The feed-back loop circuit is configured to feed a result back to the second resistor, the result being one of comparing a first voltage and a second voltage with each other, the first voltage and the second voltage being applied respectively to the first resistor and the second resistor.

IPC Classes  ?

  • H01L 21/66 - Testing or measuring during manufacture or treatment

81.

STORAGE DEVICE FOR LOADING MAP SEGMENT AND SENDING MAP SEGMENT TO EXTERNAL DEVICE, AND OPERATING METHOD THEREOF

      
Application Number 18184241
Status Pending
Filing Date 2023-03-15
First Publication Date 2024-05-30
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Jung, Hoe Seung
  • Kim, Do Hyung
  • Kim, Chi Heon
  • Lee, Joo Young

Abstract

A storage device may load, between a first time point at which information on candidate memory regions among a plurality of memory regions is started to be sent to an external device and a second time point at which a command requesting a map segment for a target memory region among the plurality of memory regions is received from the external device, all or a part of map segments corresponding to the candidate memory regions into a buffer.

IPC Classes  ?

82.

APPARATUS AND METHOD FOR PROGRAMMING AND VERIFYING DATA IN A NONVOLATILE MEMORY DEVICE

      
Application Number 18295726
Status Pending
Filing Date 2023-04-04
First Publication Date 2024-05-30
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Choi, Hyung Jin
  • Ko, Gwi Han

Abstract

A memory device comprising: a memory cell array comprising multiple memory cells, and a controller configured to repeatedly perform a program loop comprising a voltage application interval and a verification interval until a program operation for cells that have been connected to a word line that have been selected as a program target reach a threshold voltage level and configured to adjust an increase in a level of a program voltage that is applied to the selected word line in the voltage application interval of a second program loop following a first program loop, based on a result of a comparison between a threshold voltage level of each of cells that have been selected as a verification target, among the cells that have been connected to the selected word line, and a pre-target level in the verification interval of the first program loop, among the program loops that are repeated.

IPC Classes  ?

  • G11C 16/10 - Programming or data input circuits
  • G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention

83.

CHALCOGENIDE MATERIAL AND SEMICONDUCTOR DEVICE INCLUDING THE SAME

      
Application Number 18299608
Status Pending
Filing Date 2023-04-12
First Publication Date 2024-05-30
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Jung, Gwang Sun
  • Ahn, Jun Ku
  • Cho, Sung Lae
  • Hwang, Uk

Abstract

Disclosed is a chalcogenide material including germanium (Ge), selenium (Se), arsenic (As), silicon (Si) and indium (In). In the chalcogenide material, a content of selenium (Se) is 49 at % to 56 at %, a content of indium (In) is 1.1 at % or less, and a sum of contents of germanium (Ge) and silicon (Si) is 18 at % to 21 at %.

IPC Classes  ?

  • H10B 63/00 - Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
  • C04B 35/547 - Shaped ceramic products characterised by their composition; Ceramic compositions; Processing powders of inorganic compounds preparatory to the manufacturing of ceramic products based on non-oxides based on sulfides or selenides
  • H10B 63/10 - Phase change RAM [PCRAM, PRAM] devices

84.

MEMORY DEVICE AND METHOD OF OPERATING THE MEMORY DEVICE

      
Application Number 18302728
Status Pending
Filing Date 2023-04-18
First Publication Date 2024-05-30
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Shin, Jae Hyeon
  • Son, Chang Han
  • Yang, In Gon
  • Hwang, Sung Hyun

Abstract

The present technology relates to an electronic device. A memory device including a plurality of memory cells connected to a plurality of word lines arranged between a plurality of source select lines and a plurality of drain select lines, a peripheral circuit configured to perform a program operation of programming data in selected memory cells among the plurality of memory cells, and a program operation controller configured to control the peripheral circuit to apply a voltage, for turning on or off source select transistors connected to the plurality of source select lines, to the plurality of source select lines, while applying a pass voltage to the plurality of word lines after applying a program voltage to selected word lines connected to the selected memory cells.

IPC Classes  ?

  • G11C 16/10 - Programming or data input circuits
  • G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • G11C 16/08 - Address circuits; Decoders; Word-line control circuits
  • G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention

85.

SEMICONDUCTOR DEVICE AND METHOD OF OPERATING THE SAME CAPABLE OF PREVENTING MALFUNCTION DURING READ OPERATION

      
Application Number 18304238
Status Pending
Filing Date 2023-04-20
First Publication Date 2024-05-30
Owner SK hynix Inc. (Republic of Korea)
Inventor Cho, Byung Goo

Abstract

A semiconductor device includes a chip selection signal receiver configured to receive, from an external memory controller, a chip selection signal activating to a state in which communication is possible with the external memory controller. The semiconductor device also includes a data signal receiver configured to receive a command and an address from the external memory controller. The semiconductor device further includes an operation controller configured to perform an internal operation according to the command and the address received through the data signal receiver while the chip selection signal is input. The semiconductor device additionally includes an internal signal generator configured to output an inactivated internal chip selection signal blocking transferal of the chip selection signal to the operation controller when a command other than a command requesting an output of data is received while the internal operation is performed.

IPC Classes  ?

  • G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers

86.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

      
Application Number 18307620
Status Pending
Filing Date 2023-04-26
First Publication Date 2024-05-30
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Shin, Wan Sup
  • Kang, Yoon Ho
  • Kim, Ji Seong

Abstract

A semiconductor device includes a gate structure including insulating layers and conductive layers that are alternately stacked, a channel layer located in the gate structure, a silicide layer located in the channel layer, and a memory layer surrounding the channel layer. At least one of the channel layer, the silicide layer, and the memory layer includes a halogen element.

IPC Classes  ?

  • H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/8234 - MIS technology
  • H01L 29/49 - Metal-insulator semiconductor electrodes
  • H01L 29/68 - Types of semiconductor device controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched

87.

MEMORY DEVICE FOR PERFORMING PROGRAM OPERATION ACCORDING TO INCREMENTAL STEP PULSE PROGRAMMING METHOD, STORAGE DEVICE INCLUDING THE SAME, AND OPERATING METHOD OF THE MEMORY DEVICE

      
Application Number 18312459
Status Pending
Filing Date 2023-05-04
First Publication Date 2024-05-30
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Choi, Hyung Jin
  • Ko, Gwi Han
  • Jeong, Chan Hui
  • Park, Se Chun

Abstract

A memory device includes: a plurality of memory cells; a peripheral circuit configured to perform a plurality of program loops each including a program voltage apply operation of applying a program voltage to selected memory cells, and a verify operation of verifying a program state of the selected memory cells; and a control logic configured to control the peripheral circuit to apply program voltages increasing in a step-wise manner by a first step voltage in program loops in a first state, and increasing by a second step voltage that is lower than the first step voltage in program loops in a second state that occur after the program loops in the first state. The first state and the second state of the program loops are determined based on when a verify operation on a program state having a highest threshold voltage is performed.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

88.

SEMICONDUCTOR DEVICE INCLUDING RESISTANCE CHANGE LAYER WITH METAL-ORGANIC FRAMEWORK

      
Application Number 18315381
Status Pending
Filing Date 2023-05-10
First Publication Date 2024-05-30
Owner SK hynix Inc. (Republic of Korea)
Inventor Koo, Won Tae

Abstract

A semiconductor device includes a first electrode and a second electrode that are spaced apart from each other, and a resistance change layer disposed between the first and second electrodes and including a metal-organic framework having cavities. The resistance change layer includes channels disposed in the cavities, receiving metal ions provided from one electrode of the first and second electrodes.

IPC Classes  ?

  • H10K 10/50 - Bistable switching devices
  • G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
  • H10B 63/00 - Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
  • H10K 10/82 - Electrodes

89.

MEMORY DEVICE AND METHOD OF OPERATING THE SAME

      
Application Number 18317362
Status Pending
Filing Date 2023-05-15
First Publication Date 2024-05-30
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Shin, Hyun Seob
  • Kwak, Dong Hun

Abstract

The present technology relates to an electronic device. According to the present technology, a memory device may include a plurality of memory cells, a read and write circuit, and a program controller. The plurality of memory cells may be connected to a plurality of channels passing through a plurality of word lines. The program controller may control the read and write circuit to perform a sensing operation on first memory cells and second memory cells among the plurality of memory cells during differently set sensing time periods. The first memory cells may be connected to first channels adjacent to a plurality of slits, among a plurality of channels separated by the plurality of slits. The second memory cells may be connected to second channels farther from the plurality of slits than the first channels.

IPC Classes  ?

  • G11C 16/10 - Programming or data input circuits
  • G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • G11C 16/24 - Bit-line control circuits

90.

MEMORY DEVICE AND METHOD OF OPERATING THE SAME

      
Application Number 18319240
Status Pending
Filing Date 2023-05-17
First Publication Date 2024-05-30
Owner SK hynix Inc. (Republic of Korea)
Inventor Lee, Hee Youl

Abstract

A memory device, and a method of operating the same, includes checking a first elapsed time between an end time of a program operation performed on a first page and a selection time when a second page is selected after the end time, comparing the first elapsed time with a reference time interval, and performing a dummy program operation on the second page when the first elapsed time is equal to or longer than the reference time interval.

IPC Classes  ?

  • G11C 11/4096 - Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
  • G11C 11/4076 - Timing circuits
  • G11C 11/4099 - Dummy cell treatment; Reference voltage generators

91.

MEMORY DEVICE, OPERATING METHOD THEREOF, AND VERIFICATION RESULT GENERATOR

      
Application Number 18319292
Status Pending
Filing Date 2023-05-17
First Publication Date 2024-05-30
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Choi, Hyung Jin
  • Park, Chan Sik

Abstract

A memory device includes: a memory cell array including a plurality of memory cells; a peripheral circuit including a plurality of page buffers respectively connected to the plurality of memory cells; a sensing circuit connected to the plurality of page buffers respectively, the sensing circuit: performing a sensing operation on the page buffers in units of a plurality of chunks, each chunk including two or more page buffers, among the plurality of page buffers, and outputting a sensing result of each of the plurality of chunks; a verification result output circuit for outputting a final verification result of a target program state, among a plurality of program states to which the memory cells are to be programmed, based on the sensing results of the plurality of chunks; and a control logic for controlling the sensing circuit and the peripheral circuit, based on the final verification result.

IPC Classes  ?

  • G11C 16/26 - Sensing or reading circuits; Data output circuits
  • G11C 16/24 - Bit-line control circuits

92.

PAGE BUFFER, MEMORY DEVICE INCLUDING PAGE BUFFER AND MEMORY SYSTEM INCLUDING MEMORY DEVICE

      
Application Number 18321576
Status Pending
Filing Date 2023-05-22
First Publication Date 2024-05-30
Owner SK hynix Inc. (Republic of Korea)
Inventor Park, Kang Woo

Abstract

A memory device including a page buffer is part of a memory system. The memory device includes first memory cells, each configured to be programmed to have a threshold voltage corresponding to any one of a plurality of program states. The memory device also includes data latches configured to respectively store a plurality of pieces of first logical page data to be stored in the first memory cells. The memory device further includes a pre-sensing latch configured to store data sensed through a pre-verify operation. The pre-sensing latch stores second logical page data to be stored in second memory cells when a main verify operation for a threshold program state, among the plurality of program states, has passed.

IPC Classes  ?

  • G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
  • G11C 16/10 - Programming or data input circuits
  • G11C 16/26 - Sensing or reading circuits; Data output circuits

93.

MEMORY DEVICE AND OPERATING METHOD FOR CONTROLLING DATA OUTPUT TIME

      
Application Number 18325788
Status Pending
Filing Date 2023-05-30
First Publication Date 2024-05-30
Owner SK hynix Inc. (Republic of Korea)
Inventor Kwak, Dong Hun

Abstract

According to the present disclosure, a memory device includes a memory cell, a delay information storage configured to store delay information associated with a time at which data stored in the memory cell is output, and an operation controller configured to output the data to an external device after delaying a time corresponding to the delay information from a time of discharging a voltage provided to the memory cell.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

94.

MEMORY DEVICE AND OPERATING METHOD OF THE MEMORY DEVICE

      
Application Number 18326781
Status Pending
Filing Date 2023-05-31
First Publication Date 2024-05-30
Owner SK hynix Inc. (Republic of Korea)
Inventor Lee, Hee Youl

Abstract

There are provided a memory device and an operating method of the memory device. The memory device includes: a plurality of pages each comprising a plurality of memory cells; a peripheral circuit for, in a read operation of a selected page among the pages, applying a read voltage to a selected word line connected to the selected page, sequentially applying sub-pass voltages and target pass voltages higher than the sub-pass voltages to adjacent word lines adjacent to the selected word line, and applying the target pass voltages to the other unselected word lines; and a control circuit for controlling the peripheral circuit. Before the read voltage is applied to the selected word line, the control circuit controls the peripheral circuit to apply the sub-pass voltages to the adjacent word lines, and apply the target pass voltages to the other unselected word lines.

IPC Classes  ?

  • G11C 16/26 - Sensing or reading circuits; Data output circuits
  • G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • G11C 16/08 - Address circuits; Decoders; Word-line control circuits
  • G11C 16/24 - Bit-line control circuits

95.

VOLTAGE REGULATOR

      
Application Number 18334983
Status Pending
Filing Date 2023-06-14
First Publication Date 2024-05-30
Owner SK hynix Inc. (Republic of Korea)
Inventor Lee, Jung Han

Abstract

A voltage regulator includes a voltage generator configured to receive a reference voltage and a feedback voltage and configured to generate an output voltage corresponding to the feedback voltage, a voltage divider configured to divide the output voltage to generate the feedback voltage, and a controller configured to control a voltage division value of the voltage divider in response to a program enable signal and a charge-pump enable signal during an activation period of an enable signal.

IPC Classes  ?

  • G05F 1/46 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc
  • G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit

96.

IMAGE SENSING DEVICE WHICH OUTPUTS PLURAL CLOCK SIGNALS THROUGH RESPECTIVE PLURAL OUTPUT TERMINALS

      
Application Number 18432083
Status Pending
Filing Date 2024-02-05
First Publication Date 2024-05-30
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Song, Jeong Eun
  • Shin, Min Seok
  • Park, Yu Jin
  • Seo, Sung Uk
  • Lee, Sun Young

Abstract

Disclosed is an image sensing device including a first clock distributor suitable for receiving a first input clock signal through a first input terminal, and outputting a plurality of first output clock signals through a plurality of first output terminals, and a first conductive line coupled in common to the plurality of first output terminals.

IPC Classes  ?

  • H04N 25/71 - Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
  • H04N 25/677 - Noise processing, e.g. detecting, correcting, reducing or removing noise applied to fixed-pattern noise, e.g. non-uniformity of response for non-uniformity detection or correction for reducing the column or line fixed pattern noise

97.

SEMICONDUCTOR DEVICE INCLUDING RESISTOR ELEMENT

      
Application Number 18432788
Status Pending
Filing Date 2024-02-05
First Publication Date 2024-05-30
Owner SK hynix Inc. (Republic of Korea)
Inventor Yoon, Chan Ho

Abstract

A semiconductor device includes a first pad defined on one surface of a first chip; a second pad defined on one surface of a second chip which is stacked on the first chip, and bonded to the first pad; a first resistor element defined in the first chip, and coupled to the first pad; and a second resistor element defined in the second chip, and coupled to the second pad.

IPC Classes  ?

  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,

98.

MEMORY DEVICE FOR IMPROVING EFFICIENCY OF COMMAND INPUT OPERATION

      
Application Number 18295852
Status Pending
Filing Date 2023-04-05
First Publication Date 2024-05-23
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Sohn, Hyeok Chan
  • Kim, Byung Ryul
  • Park, Yong Soon
  • Jo, Kang Wook

Abstract

A memory device comprises a command decoding unit configured to generate a command by decoding an input signal applied to a first pad, wherein whether the command decoding unit is to be disabled is selected based on whether an operating state signal is activated, an operating state control unit configured to activate or deactivate the operating state signal in response to a set signal applied to the first pad, and an internal operation execution unit configured to perform a set internal operation in response to the command.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

99.

APPARATUS AND METHOD FOR PROGRAMMING AND VERIFYING DATA IN NON-VOLATILE MEMORY DEVICE

      
Application Number 18295855
Status Pending
Filing Date 2023-04-05
First Publication Date 2024-05-23
Owner SK hynix Inc. (Republic of Korea)
Inventor Choi, Hyung Jin

Abstract

A memory device comprises: a memory cell array including multiple cells have program states divided on a basis of N threshold voltage levels, and a controller configured to: divide, into N groups corresponding to the N threshold voltage levels, cells selected as a verification target, and perform, if a selected group of the N groups corresponds to remaining threshold voltage levels except a highest threshold voltage level among the N threshold voltage levels, a pass masking operation of determining the selected group to have a program pass state when a number of cells checked to have a program fail state in the selected group is less than a reference number in a verification interval included in a program operation, wherein the controller is configured not to perform, if the selected group corresponds to the highest threshold voltage level, the pass masking operation on the selected group in the verification interval.

IPC Classes  ?

  • G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
  • G11C 16/10 - Programming or data input circuits
  • G11C 29/52 - Protection of memory contents; Detection of errors in memory contents

100.

IMAGE PROCESSING DEVICE AND IMAGE PROCESSING METHOD

      
Application Number 18298242
Status Pending
Filing Date 2023-04-10
First Publication Date 2024-05-23
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Choi, Jun Hyeok
  • Lee, Dae Hyun

Abstract

An image processing device includes a memory for storing reference color ratios and crosstalk values of each of light source images acquired by sensing light sources having different wavelengths. The image processing device also includes a processor for receiving an image including a plurality of regions each including outer pixel values and inner pixel values of the same color, and correcting the outer pixel values or the inner pixel values by using difference values between the respective reference color ratios and a color ratio of the image as weights of the crosstalk values.

IPC Classes  ?

  • H04N 23/81 - Camera processing pipelines; Components thereof for suppressing or minimising disturbance in the image signal generation
  • H04N 23/84 - Camera processing pipelines; Components thereof for processing colour signals
  • H04N 25/10 - Circuitry of solid-state image sensors [SSIS]; Control thereof for transforming different wavelengths into image signals
  • H04N 25/62 - Detection or reduction of noise due to excess charges produced by the exposure, e.g. smear, blooming, ghost image, crosstalk or leakage between pixels
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