A memory system and a method of operating the memory system are provided. The memory system includes a plurality of semiconductor memory devices each of which includes a plurality of memory blocks. The memory system also includes a controller configured to control the plurality of semiconductor memory devices to perform a program operation, a read operation, and an operation of removing a hole in a space region on a target memory block of the plurality of memory blocks. The controller controls the plurality of semiconductor memory devices to perform the operation of removing the hole in the space region on the target memory block when an erase count of the target memory block of the plurality of memory blocks is greater than a set value.
Provided herein may be a memory controller and a method of operating the same. The memory controller may include a plurality of control cores configured to control a plurality of memory devices, respectively, a host core configured to allocate write requests received from a host to each of the plurality of control cores based on predefined criteria, and a shared memory configured to be accessed by the host core and the plurality of control cores, wherein, in response to occurrence of a sudden power-off, the host core is further configured to store, in the shared memory, dump information including information about logical addresses corresponding to the write requests, and wherein a first control core is further configured to store, in a memory device controlled by the first control core, the dump information of a second control core associated with the first control core.
An input/output circuit including: a pull-up driving circuit including at least one internal node coupled to a pad, the pull-up driving circuit configured to pull up a voltage of the pad to a Tx power supply voltage; and a pull-down driving circuit configured to pull down the voltage of the pad to a ground voltage. The pull-up driving circuit is configured to set a voltage level of the at least one internal node to a voltage level of a power supply voltage on the basis of a fixed voltage, when a voltage difference between the Tx power supply voltage and the voltage of the pad is greater than the voltage level of the power supply voltage.
An auxiliary power circuit may measure a first time during which the voltage level of a capacitor falls from a first level to a second level by a leakage current of the capacitor, may charge the capacitor to a third level, may measure a second time during which the voltage level of the capacitor falls from the third level to a fourth level by the leakage current of the capacitor and a discharge current of a current source, may calculate a capacitance of the capacitor based on the first level, the second level, the first time, the third level, the fourth level, the second time and the discharge current of the current source, and may determine the state of the capacitor based on the calculated capacitance of the capacitor.
A memory device includes a substrate, an active layer that is spaced apart from the substrate and laterally oriented, a word line that is laterally oriented in parallel to the active layer along one side of the active layer, an active body that is vertically oriented by penetrating through the active layer, a bit line that is vertically oriented by penetrating through the active layer to be spaced apart from one side of the active body, and a capacitor that is vertically oriented by penetrating through the active layer to be spaced apart from another side of the active body.
Provided herein may be a memory device and a method of operating the same. The memory device may include a memory block including a plurality of memory cells that are coupled to a plurality of word lines, a peripheral circuit configured to perform a read operation by applying a read voltage to a selected word line, among the plurality of word lines, and applying a first pass voltage to target word lines, wherein the target word lines are adjacent to the selected word line, among unselected word lines other than the selected word line, and a control logic configured to decrease the read voltage based on a read voltage variation and to decrease the first pass voltage based on a pass voltage variation when the read voltage decreases, wherein the pass voltage variation is less than the read voltage variation.
G11C 16/26 - Sensing or reading circuits; Data output circuits
G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
The present disclosure relates to a storage device including a memory device having a plurality of memory cells and performing a program operation to store write data in the plurality of memory cells, a buffer memory device temporarily storing therein the write data, and a memory controller controlling the buffer memory device and the memory device to temporarily store in the buffer memory device, the write data received from a host memory included in a host and provide the write data from the buffer memory device to the memory device in response to a write command received from the host, wherein the memory controller comprises a buffer memory manager determining, based on a used capacity of the buffer memory device whether to transfer, to the host, a command completion with respect to the write command at a first time point or a second time point.
According to an embodiment of the present disclosure, a memory device, a peripheral circuit configured to perform a program operation, including a plurality of program loops, and a control logic configured to, in some of the plurality of loops of the program operation, control the peripheral circuit to apply a program voltage to a selected word line, apply a first pass voltage to adjacent word lines that are adjacent to the selected word line, and then apply a second pass voltage to adjacent word lines at a predetermined time point, wherein the second pass voltage has a different magnitude compared to the first pass voltage, and in the rest of the plurality of loops of the program operation, control the peripheral circuit to apply the second pass voltage to the adjacent word lines at a time point that is different from the predetermined time point from a selected loop.
A memory system includes memory blocks and a controller. The controller configured to perform a wear levelling operation on the memory blocks based on a reference count table and an erase count table.
An image sensing device includes a pixel array including a plurality of unit pixels consecutively arranged and structured to generate an electrical signal in response to incident light by performing photoelectric conversion of the incident light. The unit pixels are isolated from each other by first device isolation structures. Each of the unit pixels includes a photoelectric conversion element structured to generate photocharges by performing photoelectric conversion of the incident light, a floating diffusion region structured to receive the photocharges, a transfer transistor structured to transfer the photocharges generated by the photoelectric conversion element to the floating diffusion region, and a well tap region structured to apply a bias voltage to a well region. The well tap region is disposed at a center portion of a corresponding unit pixel.
A memory controller includes: a program operation controller configured to control a memory device to store data and individual mapping information; a mapping information storage configured to store therein mapping information; a mapping information update controller configured to control the memory device to store the mapping information in a second memory block; perform an update operation of updating the mapping information, and delay, when sequentiality of a predetermined number or more of logical addresses is maintained with respect to the predetermined time, the update operation until the sequentiality is broken; and a Sudden Power Off Recovery (SPOR) controller configured to receive the individual mapping information, recover the mapping information for the data stored in the page during a delay section and provide the recovered mapping information to the mapping information storage.
The present disclosure provides a semiconductor memory device and a method of manufacturing the same. The semiconductor memory device includes a channel layer including a plurality of channel pillars that pass through a gate stack and a channel connection portion that extends from each of the plurality of channel pillars to overlap with the gate stack, a memory layer including a vertical portion between the plurality of channel pillars and the gate stack and a horizontal portion that extends from the vertical portion between the gate stack and the channel connection portion, and a doped semiconductor layer contacting the channel connection portion and overlapping with the channel connection portion.
H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 27/11565 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the top-view layout
H01L 27/11573 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the peripheral circuit region
H01L 23/528 - Layout of the interconnection structure
13.
PLATFORM FOR NON-VOLATILE MEMORY STORAGE DEVICES SIMULATION
A system and associated method for simulating a storage device. In the system and method, a set of simulation entities (SEs) is provided including a host SE and storage component SEs corresponding to hardware and software components of the storage device to be simulated, SEs from the set of the SEs are selected, a logical relationship is determined between the selected SEs, sequential messages are propagated between the selected SEs and to the simulation core engine which determine whether conditions for a simulation are complete, and simulations are performed using the selected SEs.
A stack type semiconductor device including a first wafer and a second wafer. The first wafer including at least one first chip. The second wafer including at least one second chip electrically connected with the first chip. Each of the first and second chips including a test circuit block, at least one test bonding pad and a hybrid boning member. The test circuit block performing a test operation based on a test signal. The test bonding pad arranged on a bonding surface of each of the first and second chips to transmit the test signal and signals for driving the test circuit block between the first and second chips. The hybrid bonding member electrically connected between the test bonding pads.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 21/66 - Testing or measuring during manufacture or treatment
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices
15.
DELAY LINE, A DELAY LOCKED LOOP CIRCUIT AND A SEMICONDUCTOR APPARATUS USING THE DELAY LINE AND THE DELAY LOCKED LOOP CIRCUIT
A delay locked loop circuit includes a delay line, a phase detector, a selection controller, and a charge pump. The delay line delays, based on a delay control voltage, a reference clock signal to generate an internal clock signal and a feedback clock signal. The phase detector compares phases of the internal clock signal and the feedback clock signal to generate a first detection signal and a second detection signal. The selection controller provides the reference clock signal as an up-signal and a down-signal. The charge pump generates the delay control voltage based on the up-signal and the down-signal.
H03L 7/081 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop provided with an additional controlled phase shifter
H03K 5/134 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active-delay devices with field-effect transistors
H03L 7/089 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
16.
MEMRISTOR DEVICE, METHOD OF FABRICATING THE SAME, SYNAPTIC DEVICE INCLUDING THE SAME, AND NEUROMORPHIC DEVICE INCLUDING THE SYNAPTIC DEVICE
Korea Advanced Institute of Science and Technology (Republic of Korea)
Inventor
Park, Sang Su
Choi, Sung Yool
Cha, Jun Hwe
Oh, Jung Yeop
Abstract
A memristor device, a fabricating method thereof, a synaptic device including the memristor device, and a neuromorphic device including the synaptic device are provided. The memristor device includes a first electrode, a second electrode spaced apart from the first electrode, a resistance change layer disposed between the first electrode and the second electrode and including a polymer, and an insertion layer disposed between the first electrode and the resistance change layer and including an oxide. An electrochemical metallization mechanism (ECM) filament is formed in the resistance change layer, and a valence change mechanism (VCM) filament is formed in the insertion layer. The memristor device has a synaptic characteristic according to a change in resistance of the resistance change layer. The insertion layer includes an Al2O3 layer. The insertion layer includes an Al2O3 layer formed by an atomic layer deposition (ALD) process using a temperature of about 200° C. or higher.
An electronic device according to an embodiment of the present disclosure includes a substrate, a base electrode layer disposed over the substrate, first and second operating electrode layers disposed over the base electrode layer to be spaced apart from each other, a channel layer disposed between the first operating electrode layer and the second operating electrode layer over the base electrode layer, a proton conductive layer disposed over the first and second electrode layers and the channel layer, a hydrogen source layer disposed over the proton conductive layer, and a control electrode layer disposed over the hydrogen source layer.
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
A memory system includes a memory controller and a memory device. The memory controller accesses the memory device by providing a system clock signal, a data clock signal, and a chip selection signal and provides a data clock enable signal to the memory device after the access to the memory device. The memory device communicates with the memory controller based on the system clock signal, the data clock signal, and the data clock enable signal.
A storage device includes a memory device and a controller. The memory device includes a memory region which includes a first sub-region and a second sub-region. The controller reads assist data from a plurality of memory cells according to an assist read voltage during a read voltage adjusting operation on the first sub-region as a target sub-region, and re-utilizes the read assist data during the read voltage adjusting operation on the second sub-region as the target sub-region.
A method and system for LDPC decoding method. In the method and system, an LDPC codeword is decoded using a quasi-cyclic matrix. A first message for variable nodes in a circulant column of the quasi-cyclic matrix and a second message for check nodes belonging to the circulant column are computed. Parity and syndrome are computed using the computed first and second messages. A bit error rate is calculated for both a first mode with no error in a parity portion of a codeword and a second mode with errors in the parity portion of the codeword.
H03M 13/01 - Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
H03M 13/09 - Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
21.
MEMORY SYSTEM, MEMORY CONTROLLER AND OPERATING METHOD OF THE MEMORY SYSTEM FOR CONTROLLING GARBAGE COLLECTION
A memory system or memory controller may calculate a first data size, which is the sum of sizes of data requested to be written by write requests from outside the memory system after a first reference time point, calculate a second data size, which is the sum of sizes of data updated by the write requests among data already stored in the memory device from a second reference time point, and control execution of garbage collection on data stored in the memory device based on the first data size and the second data size.
There are provided a memory device and a manufacturing method of the memory device. The memory device includes: a source line; a stack structure formed on the source line; a cell plug penetrating the stack structure and contacting the source line; a slit separating the stack structure; a source contact formed in the slit, the source contact in contact with the source line; and a compensation plug formed below the cell plug in the source line, wherein the compensation plug contains an impurity that has a higher concentration than an impurity that is contained in the source line.
H01L 23/535 - Arrangements for conducting electric current within the device in operation from one component to another including internal interconnections, e.g. cross-under constructions
H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
23.
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SEMICONDUCTOR DEVICE
A semiconductor device, and a method of manufacturing the semiconductor device, includes: a gate structure including conductive layers and insulating layers, which are alternately stacked; at least one channel structure penetrating the gate structure, the at least one channel structure being aligned in a first direction; a first cutting structure extending in the first direction, the first cutting structure penetrating the at least one channel structure; a contact pad in contact with an upper surface of the at least one channel structure, the contact pad having a critical dimension greater than a critical dimension of the upper surface of the at least one channel structure; and a second cutting structure in contact with an upper surface of the first cutting structure and penetrating the contact pad.
H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 23/528 - Layout of the interconnection structure
H01L 27/11556 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 27/11519 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the top-view layout
H01L 27/11565 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the top-view layout
A semiconductor device includes: a first memory block having a first block pitch; and a second memory block belonging to a same plane as the first memory block, the second memory block located closer to a plane edge than the first memory block, the plane edge being an edge of the plane, wherein the second memory block has a second block pitch that is larger than the first block pitch.
G11C 5/02 - Disposition of storage elements, e.g. in the form of a matrix array
H01L 27/24 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier
25.
METHOD OF PROGRAMMING A SELECT TRANSISTOR OF A SEMICONDUCTOR MEMORY DEVICE
A semiconductor memory device includes a first cell string, a second cell string, a peripheral circuit, and a control logic. The first cell string includes first and second drain select transistors. The second cell string includes third and fourth drain select transistors. The peripheral circuit performs a program operation on the fourth drain select transistor included in the second cell string. The threshold voltage of the first drain select transistor is set through an ion implantation process. The threshold voltage of the fourth drain select transistor is set through the program operation.
The present disclosure relates to a memory device including a first memory block including a first group of cell plugs and a second group of cell plugs, a second memory block including a third group of cell plugs and a fourth group of cell plugs, a connection region located between the first and second memory blocks, a first source select line commonly coupled to the first group of cell plugs and third group of cell plugs, a second source select line coupled to the second group of cell plugs, and a third source select line coupled to the fourth group of cell plugs.
A memory system includes: a memory device including a plurality of pages each including a plurality of L-level cells, K planes each including the plurality of pages, and N memory dies each including the K planes; and a controller suitable for dividing logical addresses corresponding to write data, into a plurality of divided logical groups by grouping the logical addresses by a preset number, when performing a program operation of transferring the write data to the memory device to store, and mapping each of the plurality of divided logical groups to a reference logical unit in a first order of bits of the L-level cell, a second order of the N memory dies, and a third order of the K planes, according to a size of the write data, in order to decide an order in which the write data are to be transferred to the memory device.
There are provided a semiconductor device and a manufacturing method thereof. The semiconductor device includes: a stack structure including a plurality of conductive patterns and a plurality of interlayer insulating layers, which are alternately stacked on a substrate; a plurality of channel structures extending in a first direction substantially perpendicular to the substrate to penetrate the stack structure; at least one first slit extending in a second direction substantially horizontal to the substrate while penetrating conductive patterns for select lines among the plurality of conductive patterns; a second slit extending in the second direction while penetrating the conductive patterns for select lines; and a plurality of support structures disposed on a bottom of the second slit, the plurality of support structures penetrating conductive patterns for word lines among the plurality of conductive patterns.
H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 27/11565 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the top-view layout
H01L 27/11573 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the peripheral circuit region
29.
MEMORY DEVICE AND MANUFACTURING METHOD OF THE MEMORY DEVICE
There are provided a memory device and a manufacturing method of the memory device. The memory device includes: a source structure; and a stack structure over the source structure, the stack structure including a plug and a slit, wherein the slit includes a source contact being connected to the source structure.
H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H01L 27/11565 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the top-view layout
H01L 27/1157 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the memory core region with cell select transistors, e.g. NAND
A semiconductor device may include: a first conductive layer; a second conductive layer spaced apart from the first conductive layer; a tunnel insulating layer interposed between the first conductive layer and the second conductive layer and disposed adjacent to the first conductive layer; a charge blocking layer interposed between the first conductive layer and the second conductive layer and disposed adjacent to the second conductive layer; and a selector layer interposed between the tunnel insulating layer and the charge blocking layer, wherein the semiconductor device functions as a self-selecting memory.
H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 27/11568 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the memory core region
Disclosed is an image sensor including a first sub-pixel array including a plurality of first pixel groups, which are respectively coupled to a plurality of first readout lines extending in a first direction and are adjacent to one another in a second direction intersecting the first direction; and a plurality of first switches suitable for selectively coupling a plurality of first floating diffusion nodes included in the plurality of first pixel groups, based on a plurality of first control signals.
A semiconductor memory device includes a memory cell array, a peripheral circuit, and control logic. The memory cell array includes a plurality of memory cells. The peripheral circuit performs a program operation on selected memory cells among the plurality of memory cells. The control logic controls the program operation of the peripheral circuit. The control logic controls the peripheral circuit to perform the program operation on the selected memory cells by using a first program voltage determined based on a first step voltage during a first program period and controls the peripheral circuit to perform the program operation on the selected memory cells by using a second program voltage determined based on a second step voltage different from the first step voltage during a second program period after the first program period.
An internal voltage generation circuit includes an enable control circuit configured to generate a final enable signal by limiting an activation time point of an enable signal to a point in time after a reset time, after the enable signal is inactivated. The internal voltage generation circuit also includes a start-up control circuit configured to perform a reset operation during the reset time and generate a start-up signal based on the final enable signal, a reference voltage generation circuit configured to generate a reference voltage based on the start-up signal, a current generation circuit configured to generate a reference current based on the reference voltage, and a voltage generation circuit configured to generate an internal voltage based on the reference current.
G11C 11/4099 - Dummy cell treatment; Reference voltage generators
G11C 11/4074 - Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
34.
REDUNDANCY MANAGING METHOD AND APPARATUS FOR SEMICONDUCTOR MEMORIES
Korea University Research and Business Foundation (Republic of Korea)
Inventor
Park, Jong Sun
Bae, Kwan Ho
Song, Jun Hyun
Abstract
A redundancy managing method and apparatus for semiconductor memories is disclosed. The redundancy managing method for semiconductor memories utilizes bitmap type storage by defining an appropriate storage space according to the type of a fault.
A page buffer circuit may include: a data transfer circuit configured to transfer data, transferred to a first sensing node through a bit line, to a second sensing node during a data sensing operation; a first latch circuit configured to sense the data transferred to the first sensing node, and store the sensed data; and a second latch circuit configured to sense the data transferred to the second sensing node, and store the sensed data.
G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
G11C 7/12 - Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
A memory device includes a plurality of memory cells, where each memory cell is configured to be in an erased state or one of a plurality of program states according to data stored therein. The memory device also includes a peripheral circuit configured to, in a program operation on the plurality of memory cells, perform a first program voltage application operation on first memory cells, the first memory cells being to be programmed to first respective program states. The peripheral circuit is also configured to perform, after the first program voltage application operation, a pre-program voltage application operation on second memory cells, the second memory cells being to be programmed to second respective program states.
A semiconductor memory device is provided. The semiconductor memory device includes a source structure, a first drain select line spaced apart from the source structure, first to fourth bit lines of a first group of bit lines spaced apart from the first drain select line, first to fourth channel structures of a first column of channel structures extending from the source structure to pass through the first drain select line, and first to fourth contact plugs of the first contact group of contact plugs connecting the first to fourth channel structures of the first column of channel structures to the first to fourth bit lines of the first group of bit lines, respectively, and in which each of the first to fourth channel structures of the first column of channel structures extend to overlap the first to fourth bit lines of the first group of bit lines.
H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 27/11565 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the top-view layout
H01L 23/528 - Layout of the interconnection structure
38.
SEMICONDUCTOR DEVICE INCLUDING THROUGH VIAS WITH DIFFERENT WIDTHS AND METHOD OF MANUFACTURING THE SAME
There is provided a semiconductor device including through vias and a method of manufacturing the same. The semiconductor device includes a substrate including a first via hole and a second via hole, a first through via formed in the first via hole, a second through via formed in the second via hole, an insulating layer first portion formed between a sidewall surface of the first via hole and the first through via, and an insulating layer second portion formed between a sidewall surface of the second via hole and the second through via. The insulating layer second portion is thinner than the insulating layer first portion, and the second through via is wider than the first through via,
There are provided a semiconductor memory device and a manufacturing method of the semiconductor memory device. A semiconductor memory device includes a lower stack structure on the substrate and including a plurality of lower layers stacked in a vertical direction, an intermediate stack structure on the lower stack structure and including a plurality of intermediate layers stacked in the vertical direction, a plurality of grooves in the contact region and penetrating the intermediate stack structure, the plurality of grooves exposing the lower stack structure at different depths, and a plurality of steps formed along sidewalls of the grooves.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
40.
MEMORY DEVICE AND MANUFACTURING METHOD OF THE MEMORY DEVICE
A memory device includes isolation layers and gate structures alternately stacked on a lower structure and a tunnel isolation layer penetrating the isolation layers and the gate structures. The memory device also includes a channel layer formed along an inner wall of the tunnel isolation layer and a core plug formed along an inner wall of the channel layer. Each of the gate structures includes: a floating gate surrounding an outer wall of the tunnel isolation layer; a first dielectric layer surrounding an outer wall of the floating gate; a second dielectric layer surrounding an outer wall of the first dielectric layer; a third dielectric layer surrounding an outer wall of the second dielectric layer; and a gate line formed between the isolation layers, the gate line filling a region surrounded at least in part by the third dielectric layer.
H01L 27/11556 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 27/11519 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the top-view layout
H01L 27/11526 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the peripheral circuit region
According to one embodiment, a magnetic: memory device includes a stacked structure in which a magnetoresistance effect element and a switching element are stacked. The switching element is provided on a lower layer side of the magnetoresistance effect element, and when viewed in a stacking direction of the magnetoresistance effect element and the switching element, a pattern of the switching element is located inside a pattern of the magnetoresistance effect element.
H01L 27/22 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate using similar magnetic field effects
H01L 43/12 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
42.
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SEMICONDUCTOR DEVICE
There are provided a semiconductor device and a manufacturing method of the semiconductor device. The semiconductor device includes: a gate structure including conductive layers and insulating layers, which are alternately stacked; a plurality of channel structures penetrating the gate structure, the plurality of channel structures being arranged in a first direction; a plurality of cutting structures each isolating each of the plurality of channel structures, respectively, into a plurality of divided channel structures while penetrating each of the plurality of channel structures, respectively; and a plurality of interconnection lines located over the gate structure and extending in the first direction. Each of the plurality of cutting structures has substantially a cross (+) shape including extension parts extending in directions oblique to the first direction.
H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 23/528 - Layout of the interconnection structure
H01L 27/11556 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 27/11519 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the top-view layout
H01L 27/11565 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the top-view layout
43.
THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A three-dimensional (3D) semiconductor device may include a stack structure and a vertical channel structure. The stack structure may include a first insulation pattern, a conductive pattern and a second insulation pattern. The conductive pattern may be arranged on the first insulation pattern. The second insulation pattern may be configured to physically contact an upper surface of the conductive pattern. The second insulation pattern may have a property different from a property of the first insulation pattern. The vertical channel structure may be formed through the stack structure.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 23/535 - Arrangements for conducting electric current within the device in operation from one component to another including internal interconnections, e.g. cross-under constructions
44.
THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE THREE-DIMENSIONAL SEMICONDUCTOR DEVICE
A 3D semiconductor device may include a stack structure and a vertical channel structure. The stack structure may include a first insulation pattern, a lower conductive pattern and a second insulation pattern. The lower conductive pattern may be arranged on the first insulation pattern. The second insulation pattern may be arranged on the lower conductive pattern. The first insulation pattern may have a thickness thicker than a thickness of the second insulation pattern. The vertical channel structure may be arranged in the stack structure. The lower conductive pattern may have an upper surface directly in contact with a lower surface of the second insulation pattern.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
45.
DATA SAMPLING CIRCUIT AND DATA TRANSMITTER CIRCUIT
A data sampling circuit may include a pattern detection circuit configured to generate a slow signal by detecting a pattern of multibit data including input data, and a sampling circuit configured to sample the input data during an activation period of a sampling clock and having an operating speed of the sampling circuit reduced when the slow signal is activated.
Korea Advanced Institute of Science and Technology (Republic of Korea)
Inventor
Jang, Junhyeok
Kang, Seungkwan
Oh, Dongsuk
Jung, Myoungsoo
Abstract
A data storage device includes one or more nonvolatile memory devices each including a plurality of unit storage spaces; and an address recommending circuit configured to recommend a unit storage space among the plurality of unit storage spaces to process a write request, wherein the address recommending circuit applies feature data to a neural network to recommend the unit storage space, and wherein the feature data is generated based on request information for the write request, a target address corresponding to the write request, an address of data stored in the plurality of unit storage spaces.
G06F 12/0891 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
47.
THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A three-dimensional (3D) semiconductor device includes a plurality of stack structures, a plurality of channel plugs, a slit structure and a plurality of dummy channel plugs. The stack structures include at least two conductive layers and at least two insulation layers, each being alternately stacked. The channel plugs are vertically formed through the stack structure. The slit structure is arranged at one side of the stack structure. The plurality of dummy channel plugs is arranged in the stack structures to be adjacent to the slit structure. Each of the channel plugs includes a channel insulation layer and a channel layer. Each of the dummy channel plugs includes at least one of the channel insulation layer, the channel layer, and a material of the plurality of conductive layers.
H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 27/11565 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the top-view layout
48.
SEMICONDUCTOR MEMORY DEVICE MAINTAINING VERIFICATION DATA DURING PROGRAM SUSPEND, AND METHOD OF OPERATING THE SEMICONDUCTOR MEMORY DEVICE
A method of operating a semiconductor memory device includes starting a program operation on selected memory cells using a main verification voltage and an auxiliary verification voltage in response to a program command, receiving a program suspend command during the program operation, and changing at least one auxiliary voltage verification result information among threshold voltage states which are not program-passed to at least one data pattern among threshold voltage states which program-passed, in response to the program suspend command.
A three-dimeiisioiial semiconductor device including a memory block including a stack structure comprising a second sub stack formed over a first sub stack, a plurality of channel plugs formed through the stack structure, and a separation pattern formed in the memory block.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
Disclosed is an image sensing system including a first sub-pixel array having an arrangement of K×K pixels, where “K” is a natural number greater than 4, wherein the first sub-pixel array includes: first pixels disposed in a first diagonal direction and each having a green filter; second pixels disposed in a second diagonal direction that intersects the first diagonal direction and each having a red filter, and third pixels disposed in the second diagonal direction and each having a blue filter; and fourth pixels each having a white filter and disposed at the other positions except for arrangement positions of the first to third pixels disposed in the first and second diagonal directions, and fifth pixels suitable for measuring depth information, and the fourth pixels and the fifth pixels are disposed in a first pattern.
A stacked semiconductor device includes at least one upper chip including a plurality of channels each including first and second pseudo-channels; and a plurality of transfer control circuits respectively corresponding to the channels and each configured to output channel commands according to a channel designation signal designating one of the first and second pseudo-channels and a location information signal indicating a location of a corresponding channel of the channels, and transmit first and second data words between the corresponding channel and a lower chip according to the channel commands.
G11C 5/02 - Disposition of storage elements, e.g. in the form of a matrix array
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
Disclosed are a semiconductor package and a manufacturing method thereof. Semiconductor chips may be disposed on a package substrate with vent holes formed therethrough, and a molding layer including a lower molding portion connected to an upper molding portion may be formed. The package substrate may include a substrate body with a plurality of unit regions, ball lands disposed in the unit regions, and first and second dam patterns that cross the unit regions and extend into edge regions, which is outside of the unit regions.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 23/13 - Mountings, e.g. non-detachable insulating substrates characterised by the shape
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
A memory controller includes a data detection circuit configured to detect, when power is supplied after a sudden power-off (SPO), a lost write sequence index “M” among the plural write sequence indexes, and detect first data corresponding to a write sequence index “M−1” and second data corresponding to a write sequence index “M+1”; a barrier decision circuit configured to determine, based on whether first barrier information of the first data and second barrier information of the second data are identical with each other, whether a barrier request for the first data has been received from a host; and a data recovery operation determination circuit configured to determine whether to perform a recovery operation on target data corresponding to the write sequence index “M+1” and thereafter based on whether the barrier request for the first data has been received.
A semiconductor package includes a package substrate, first and second semiconductor chips stacked on the package substrate and wire-bonded to the package substrate. The first semiconductor chip includes first differential pair signal pads, a first option signal pad, and a first signal path control circuit. The second semiconductor chip includes second differential pair signal pads, a second option signal pad, and a second signal path control circuit. The first signal path control circuit changes a signal path of one of the differential pair signals of the first semiconductor chip by a first control signal. The second signal path control circuit changes a signal path of one of the differential pair signals of the second semiconductor chip by a second control signal.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
An operation method of a memory may include entering a self-refresh mode, increasing a level of a back-bias voltage in response to entering the self-refresh mode, performing self-refresh operations in a first cycle, confirming that the back-bias voltage reaches a level of a first threshold voltage, and performing the self-refresh operations in a second cycle longer than the first cycle in response to the confirmation.
G11C 11/406 - Management or control of the refreshing or charge-regeneration cycles
G11C 11/4074 - Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
A memory system may include a memory device including a plurality of memory areas each configured by a plurality of memory blocks; and a memory controller configured to generate zones each including at least one memory block selected from at least one of the memory areas included in the memory device, manage configuration information for each generated zone, sequentially store data from a first storage location of an open zone among the generated zones during a write operation on the open zone according to an external request, and determine a number of active target memory areas associated with the open zone on a basis of configuration information of the open zone.
A method for fabricating a semiconductor device includes: forming a first multi-layer stack including liner layers and a source sacrificial layer over a lower structure; forming a second multi-layer stack including dielectric layers and sacrificial layers over the first multi-layer stack; forming a vertical contact recess extending through the second multi-layer stack and the source sacrificial layer; replacing the source sacrificial layer with a source contact layer; forming a carbon-containing spacer on sidewall of the vertical contact recess; replacing the sacrificial layers with conductive layers; and forming a source contact plug in the vertical contact recess.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
58.
SEMICONDUCTOR MEMORY APPARATUS AND OPERATING METHOD THEREOF
A semiconductor memory apparatus includes: a page buffer circuit, a pass/fail determination circuit, and an operation control circuit. The page buffer circuit may include a sensing latch circuit and a data latch circuit. The pass/fail determination circuit determines a pass/fail for a memory cell. The operation control circuit controls a program operation and a program verify operation to be performed on the memory cell.
A semiconductor device may include: a mode input control signal generation circuit configured to generate a control pulse when a mode control operation is performed, generate a mode input control signal by delaying the control pulse by a mode delay period, and control the mode delay period on the basis of a restart signal; a read strobe signal generation circuit configured to generate a read strobe signal on the basis of the control pulse; a read delay circuit configured to generate the read input control signal by delaying the read strobe signal by a read delay period; and a read pipe circuit configured to receive mode data on the basis of the mode input control signal, and receive cell data on the basis of the read input control signal.
A memory device includes: a memory cell array including a plurality of memory cells; a peripheral circuit coupled to the memory cell array through word lines and bit lines, and suitable for performing one or more program loops on memory cells that are coupled to a selected word line of the word lines, each program loop including a program voltage application operation and a program verification operation; and a program control circuit suitable for controlling the peripheral circuit to decrease a level of a precharge voltage that is applied to the bit lines during the program verification operation when the number of program loops that are performed is greater than a reference number.
A semiconductor memory device includes a refresh counter generating a counting address that is sequentially increasing according to a refresh command; an active latch generating an active address corresponding to an input address according to an active command; and a refresh control circuit repeatedly performing a first refresh period and a second refresh period according to the refresh command, and controlling selective refresh of one or more word lines corresponding to the counting address selected based on one or more high bits of the active address during the first refresh period and controlling sequential refresh of the word lines corresponding to the counting address during the second refresh period.
Provided herein may be a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a peripheral circuit structure formed on a substrate including a cell region and a contact region, a cell stacked body formed over the peripheral circuit structure to overlap the cell region, a dummy stacked body formed over the peripheral circuit structure to overlap the contact region, a pillar structure configured to penetrate the cell stacked body, an etch stop layer located over the peripheral circuit structure and overlapping with a bottom surface of the pillar structure, a cutting structure penetrating the pillar structure in a vertical direction and contacting the etch stop layer, and a contact plug penetrating the dummy stacked body and extending to the peripheral circuit structure.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
63.
MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
Provided herein may be a memory device and a method of manufacturing the same. The memory device may include a plurality of insulating layers and a plurality of gate lines configured to be alternately stacked, and a cell plug configured to pass through the plurality of insulating layers and the plurality of gate lines, wherein the plurality of gate lines, each made of a conductive material, are etched together with the plurality of insulating layers, and the cell plug includes a blocking layer, a charge trap layer, a tunnel insulating layer, a channel layer, and a core pillar.
H01L 23/535 - Arrangements for conducting electric current within the device in operation from one component to another including internal interconnections, e.g. cross-under constructions
H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
64.
SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING OF THE SAME
An embodiment of the present invention provides a method of fabricating a semiconductor device capable of relieving a dangling bond. The semiconductor device comprises a device isolation layer defining a plurality of active regions in a substrate, the device isolation layer including a first region where the active regions are spaced apart from each other at a first interval along a first direction and a second region where the active regions are spaced apart from each other at a second interval along the first direction, the second interval being wider than the first interval; a gate trench extending in the first direction to cross the active regions and the device isolation layer; and a buried gate structure gap-filling the gate trench, wherein a portion of the device isolation layer includes an air gap acting as a hydrogen pocket in a lower portion.
A semiconductor device includes: a semiconductor layer, a gate insulating layer, and a gate electrode sequentially formed in a trench formed to a predetermined depth from a first surface of a first substrate; a third substrate bonded to a second surface opposite to the first surface of the first substrate; and an air gap interposed between the semiconductor layer and the first substrate and between the semiconductor layer and the third substrate.
A semiconductor device includes: a trench formed in a substrate; a gate dielectric layer covering sidewalls and a bottom surface of the trench; a first gate electrode gap-filling a bottom portion of the trench over the gate dielectric layer; a second gate electrode including a metal nitride which is the same as the first gate electrode over the first gate electrode and doped with a low work function adjusting element; a buffer layer covering a top surface of the second gate electrode and the gate dielectric layer exposed over second gate electrode; and a capping layer gap-filling the other portion of the trench over the buffer layer.
There are provided a semiconductor memory device and a manufacturing method of a semiconductor memory device. The semiconductor memory device includes a stack structure including a contact region with a stepped structure, a stepped groove having a sidewall formed of the stepped structure of the stack structure, a barrier insulating layer extending along a surface of the stepped structure, a filling insulating layer formed on the barrier insulating layer inside the stepped groove, and a conductive gate contact penetrating the stepped structure of the stack structure while penetrating the filling insulating layer and the barrier insulating layer.
H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 27/11573 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the peripheral circuit region
68.
SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR MEMORY DEVICE
The present technology includes a semiconductor memory device. The semiconductor memory device includes a source stack, a capacitor electrode including a metal layer buried in the source stack, a stack including first insulating layers and second insulating layers alternately stacked on the source stack, and a contact plug passing through the stack and extending to be connected to the metal layer.
H01L 27/11556 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 27/11519 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the top-view layout
H01L 27/11565 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the top-view layout
H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
69.
SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
A semiconductor device includes: a substrate including a gate trench; a gate dielectric layer formed along sidewalls and bottom surfaces of the gate trench; a high work function layer and a lower gate electrode that fill a bottom portion of the gate trench over the gate dielectric layer; an upper gate electrode including a low work function adjusting element over the lower gate electrode and including the same metal nitride as a material of the lower gate electrode; and a capping layer that gap-fills the other portion of the gate trench over the upper gate electrode.
A heat management circuit may include a throttling circuit configured to cool, for a predetermined time amount, at least one semiconductor functional circuit, which is designed to perform a predetermined function, when a plurality of first temperature signals respectively transmitted from a plurality of temperature sensors installed in the semiconductor functional circuit satisfy a throttling condition; and an analysis unit configured to receive, after lapse of the predetermined time amount, a plurality of second temperature signals from the respective temperature sensors, determine whether the cooling is successful or fails, and detect a temperature sensor having outputted a second temperature signal of abnormal value when the cooling is determined to fail.
A data transmission circuit may include a plurality of data transmission lines configured to transmit a victim data signal through a victim data transmission line, and transmit an adjacent data signal through an adjacent data transmission line disposed adjacent to the victim data transmission line; and a data input/output circuit configured to control a reference voltage level reflected into the victim data signal on the basis of data pattern information of the adjacent data signal, and compare the victim data signal to the reference voltage level and output the comparison result.
A memory system includes a non-volatile memory device structured to store data; and a controller in communication with the non-volatile memory device to control writing data in, and reading data from, the non-volatile memory device, and including a memory, wherein the controller is configured to check, in response to a status data transmission request provided from an external device, whether an update flag indicating any update of status data stored in the memory is in a set status, and is configured to store the status data into the non-volatile memory device according to a status of the update flag.
A method for operating a memory includes: performing an error check operation on first memory cells; performing an error check operation on second memory cells; detecting an error which is equal to or greater than a threshold value in a region including the first memory cells and the second memory cells; classifying the region as a bad region in response to the detection of an error which is equal to or greater than the threshold value; and performing an error check operation on the first memory cells and the second memory cells again in response to the classification of the bad region.
A memory device may include: a plurality of planes, each suitable for inputting/outputting data in units of pages, a latch suitable for performing a read operation on one or more planes of the plurality of planes in response to one or more read commands, receiving data from any one plane, among the plurality of planes, and storing the received data, and a logic controller suitable for comparing first plane information, corresponding to the data that is stored in the latch, to second plane information, corresponding to an output command that is received after the read command is received, in response to the output command, and suitable for selectively outputting the data of the latch.
A semiconductor device according to an embodiment of the present disclosure includes a read transistor and a write transistor that are electrically connected to each other over a substrate. The read transistor includes a read channel layer disposed on a plane over the substrate, a read gate dielectric layer disposed over the read channel layer, and a read gate electrode layer disposed over the read gate dielectric layer. The write transistor includes a write channel layer disposed over a portion of the read gate electrode layer, a write bit line disposed on an upper surface of the write channel layer, a write gate dielectric layer on a side surface of the write channel layer, and a write word line disposed to be adjacent to the write gate dielectric layer.
A semiconductor device according to an embodiment of the present disclosure includes a substrate, a gate electrode layer disposed over the substrate, a gate dielectric layer disposed on the gate electrode layer, a channel electrode layer disposed on the gate dielectric layer, a threshold switching layer disposed on the channel electrode layer, and a source electrode layer and a drain electrode layer that are disposed on the threshold switching layer to be spaced apart from each other.
H01L 27/24 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
77.
ELECTRONIC DEVICE AND METHOD OF OPERATING THE SAME
Provided herein may be an electronic device and a method of operating the same. The electronic device may include a memory device including a replay protected memory block (RPMB) configured to store security data, a memory controller configured to control the memory device, and a host device configured to verify, using a password, an external device coupled thereto wherein the memory controller controls the memory device to read, when the external device is verified, the security data, and wherein the host device is further configured to encrypt the read security data, and transmit, to the verified external device, the encrypted security data, a decryption key for decrypting the encrypted security data, and an RPMB key for accessing the security data.
A semiconductor device according to an embodiment of the present disclosure includes a first electrode, a first resistance change layer disposed on the first electrode, a conduction control layer disposed on the first resistance change layer, a second resistance change layer disposed on the conduction control layer, and a second electrode disposed on the second resistance change layer. The conduction control layer includes a metal-organic framework layer and metal particles embedded in the metal-organic framework layer.
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
H01L 27/24 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier
79.
CONTROLLER AND OPERATING METHOD OF THE CONTROLLER FOR DETERMINING RELIABILITY DATA BASED ON SYNDROME WEIGHT
A controller and an operating method of the controller may calculate a first syndrome weight which is syndrome weight for first read data, calculate a second syndrome weight which is syndrome weight for second read data, and determine first reliability data and second reliability data based on the first syndrome weight and the second syndrome weight. The first read data may be read from a memory area using a first read bias and the second read data may be read from the memory area using a second read bias different from the first read bias.
An embodiment of the present invention provides a semiconductor device capable of improving gate induced drain leakage and a method for fabricating the same, According to an embodiment of the present invention, a semiconductor device comprises a substrate including a trench; a gate insulating layer covering a bottom surface and a sidewall of the trench; and a gate electrode structure and a capping layer sequentially stacked on the gate insulating layer and filling the trench, wherein the gate electrode structure includes: a first gate electrode including a metal nitride; a second gate electrode formed over the first gate electrode, having the same metal nitride as the first gate electrode, and having a lower work function than that of the first gate electrode; and a third gate electrode formed over the second gate electrode, having a thickness smaller than that of the second gate electrode, and including a non-metal material.
A method for manufacturing an electronic device includes forming a first source layer including a trench, forming a first sacrificial layer in the trench, forming a first structure over the first source layer, wherein the first structure includes first material layers and second material layers which are alternately stacked over the each other, forming first openings passing through the first structure and extending to the first sacrificial layer, forming first channel layers in the first openings, forming a slit passing through the first structure and extending to the first sacrificial layer, forming a second opening by removing the first sacrificial layer through the slit, and forming a second source layer in the second opening, wherein the second source layer is coupled to the first channel layers.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
82.
METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE HAVING THREE-DIMENSIONAL CELL STRUCTURE
A method of manufacturing a semiconductor device comprises: providing a substrate having a base insulation layer; forming, over the base insulation layer, a plurality of first word line structures extending in a first lateral direction and a first switching functional layer disposed between the plurality of first word line structures, the plurality of first word line structures; forming a first interlayer insulation layer on the plurality of first word line structures and the first switching functional layer; forming a plurality of second word line structures and a second switching functional layer disposed between the plurality of second word line structures; performing selective etching to the second switching functional layer, the first interlayer insulation layer, the first switching functional layer, and the base insulation layer to form bit line contact holes; and providing a conductive material in the bit line contact holes to form bit line structures.
H10N 70/00 - Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
An internal voltage generation circuit includes a shifting source voltage generation circuit configured to generate a shifting source voltage having a voltage level that falls as a voltage level of a power supply voltage rises during a period when the power supply voltage is lower than a preset voltage level. The internal voltage generation circuit also includes an internal voltage regulator configured to generate a driving signal through a level shifting operation that is performed according to the shifting source voltage received when driving an internal voltage and configured to drive the internal voltage based on the driving signal.
G05F 1/46 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc
G05F 1/595 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices including plural semiconductor devices as final control devices for a single load semiconductor devices connected in series
A memory system includes a plurality of memories, each including a plurality of data input terminals; and a memory controller configured to continuously transfer a first codeword and a second codeword to the data input terminals of the memories during a write operation.
A storage system includes a master storage device for storing data based on a RAID level determined by a host, a slave storage device for storing the data according to a command distributed from the master storage device, and a controller hub for coupling the slave storage device to the master storage device, wherein the master storage device is further configured to transfer the command to the slave storage device through the controller hub when the master storage device receives a command processing request from the host, transmit a complete queue (CQ) to the host when operations of the master storage device and the slave storage device are completed in response to the command processing request, and request a host to allocate a capacity to each function in the master storage device and the at least one of the plurality of slave storage devices based on a reference capacity.
A semiconductor memory includes first variable resistance layers and insulating layers alternately stacked; conductive pillars passing through the first variable resistance layers and the insulating layers; a slit insulating layer vertically passing through the insulating layers, extending in a first direction, and being disposed in a second direction of the insulating layers, the second direction intersecting with the first direction; conductive layers disposed between the slit insulating layer and the first variable resistance layers; and electrode layers disposed between the conductive layers and the first variable resistance layers. The first variable resistance layers remain in an amorphous state during a program operation.
H01L 47/00 - Bulk negative resistance effect devices, e.g. Gunn-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
G11C 5/02 - Disposition of storage elements, e.g. in the form of a matrix array
G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
90.
MEMORY CONTROLLER AND MEMORY SYSTEM FOR EXECUTING ERROR CORRECTION OPERATION
A memory system may include: a memory device including a plurality of memory cells; and a memory controller configured to store, as a fail address, a first internal address that is generated during a first read operation when at least one memory cell that is accessed during the first read operation among the plurality of memory cells is determined to be a fail, and store, as alternative data, internal read data that is generated during the first read operation.
A three-dimensional semiconductor device includes a peripheral circuit device layer that includes a page buffer area, a pass transistor area adjacent to the page buffer layer, and a logic transistor area adjacent to the pass transistor area in the first direction, and a memory cell device layer that includes a cell area and a staircase area extending from the cell area. The peripheral circuit device layer includes transistors, peripheral circuit via plugs, and peripheral circuit interconnection layers on a substrate. The memory cell device layer includes word line stack including interlayer insulating layers and word lines alternately stacked, the word line stack including end portions stacked in a staircase in the staircase area; a bit line array including bit lines arranged in the cell area; and word line pillars electrically connected to the end portions of the word lines in the staircase area, respectively.
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
92.
SEMICONDUCTOR DEVICE FOR CALCULATING AND CALIBRATING DELAY AMOUNT
A semiconductor device includes a strobe transmission circuit configured to output an oscillation strobe signal, through a first delay path circuit, as a strobe signal when a first measurement operation is performed and configured to output the oscillation strobe signal through a second delay path circuit as the strobe signal when a second measurement operation is performed, and a calibration circuit configured to compare the number of times the strobe signal toggles during the first measurement operation to the number of times the strobe signal toggles during the second measurement operation to calibrate the delay amounts of the first and second delay path circuits to be the same.
G11C 7/22 - Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
H03K 5/133 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active-delay devices
A semiconductor device includes a first semiconductor chip including a memory cell array and a plurality of bit lines; a second semiconductor chip including a peripheral circuit, and bonded to the first semiconductor chip; and a shielding member including a link pattern that is configured in a bonding metal layer of any one of the first semiconductor chip and the second semiconductor chip, and has a grid shape or stripe shapes, and a plurality of island patterns that are configured in a bonding metal layer of the other one of the first semiconductor chip and the second semiconductor chip, and bonded to the link pattern.
H01L 23/552 - Protection against radiation, e.g. light
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
A semiconductor system includes a controller configured to output parity information that includes an expected value at which an error correction code (ECC) encoding operation has been performed on an address in a test mode of a semiconductor device and configured to receive failure information. The semiconductor system also includes the semiconductor device configured to store an internal parity generated by performing the ECC encoding operation on the address that is input in a normal mode of the semiconductor device and configured to output the failure information generated by comparing the parity information and an output parity generated from the internal parity that is stored in the semiconductor device in the test mode.
A semiconductor device includes: a word line stack disposed over a lower structure and including a plurality of word lines stacked in a direction vertical to a surface of the lower structure; and pillar-shaped slits penetrating edge parts of the word lines and including an etch stopper.
A method for fabricating a semiconductor device includes forming a trench in a substrate, forming a gate dielectric layer on a surface of the trench, forming a lower gate, which partially fills the trench, over the gate dielectric layer, forming a low work function layer over the lower gate, forming a spacer over the low work function layer, etching the low work function layer to be self-aligned with the spacer in order to form vertical gate on both upper edges of the lower gate, and forming an upper gate over the lower gate between inner sidewalls of the vertical gate.
A memory system may include: a nonvolatile memory device; and a controller suitable for generating first map information which maps physical addresses of the nonvolatile memory device to logical addresses received from a host, selecting some segments of the first map information as second map information, and outputting the second map information to the host, the controller may determine whether the second map information is updated, and may determine updated map segments as third map information, and the controller may output information to the host indicating the third map information corresponding to a command received from the host.
