H02H 7/085 - Circuits de protection de sécurité spécialement adaptés pour des machines ou appareils électriques de types particuliers ou pour la protection sectionnelle de systèmes de câble ou ligne, et effectuant une commutation automatique dans le cas d'un chan pour moteurs dynamo-électriques contre une charge excessive
Provided is a semiconductor switch device which performs square integration of load current and wire temperature estimation at low cost and with high precision, while reducing resources required for accurate wire temperature estimation. A semiconductor switch device 200 according to one or more examples of the present invention includes: switch units 206, 201, and 202 that are connected between a power source 300 connected from the outside of the semiconductor switch device 200 and a load 400 through a wire, and that turn on/off power supply to the load; load current detection units 203 and 204 that detect load current flowing through the switch units 206, 201, and 202; and a square operation unit 205 that outputs a squared value of a load current value detected by the current detection units 203 and 204. The switch unit 206 receives a control command from outside and turns on/off power supply to the load on the basis of the control command.
H02H 3/08 - Circuits de protection de sécurité pour déconnexion automatique due directement à un changement indésirable des conditions électriques normales de travail avec ou sans reconnexion sensibles à une surcharge
H02H 3/087 - Circuits de protection de sécurité pour déconnexion automatique due directement à un changement indésirable des conditions électriques normales de travail avec ou sans reconnexion sensibles à une surcharge pour des systèmes à courant continu
The present invention relates to controlling of an active clamp fly-back converter comprising a control unit 2 that turns on/off a clamp switch two times by two pulses during off-period of a main switch. The control unit 2 sets the on-period of the first pulse to half the resonant frequency of a clamp capacitor and a leakage inductor to the resonant frequency, inclusive, turns on the clamp switch when current does not flow through the body diode of the clamp switch and flows the resonant current of the clamp capacitor and the leakage inductor, flows current through the body diode after turning off the clamp switch, turns on the clamp switch after the magnetization current of a magnetizing inductor becomes zero by the second pulse and flows negative direction current through the magnetizing inductor, and performs zero-voltage switching of the main switch QL, thereby providing a high-efficiency and low noise converter.
H02M 3/28 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu avec transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrodes de commande pour produire le courant alternatif intermédiaire
The present invention drives a DC-DC converter without dead time and increases conversion efficiency. This DC-DC converter 100 is characterized by comprising: a first switching element 4; a second switching element 5; a first off-detection circuit 13 that has a control circuit 110 which the first switching element 4 and the second switching element 5 alternately on-off drive, causing the same to perform control such that an output voltage becomes a specified voltage, said control circuit 110 detecting turn-off of the first switching element 4; and a second off-detection circuit 16 that detects turn-off of the second switching element. The DC-DC converter 100 is further characterized in that when one among the first switching element 4 and the second switching element 5 transitions to turn-on from an off state, said switching element is on driven on the basis of an off signal from the first off detection circuit 13 or the second off detection circuit 16, which detects the turn-off of the other switching element.
H02M 3/155 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs
5.
SEMICONDUCTOR INTEGRATED CIRCUIT AND DATA TRANSMISSION-RECEPTION METHOD
The present invention provides a semiconductor integrated circuit and a data transmission-reception method with which the number of connection terminals between chips can be reduced without compromising functionality. The semiconductor integrated circuit includes a chip A and a chip B and performs transmission and reception of data between the chip A and the chip B. In the semiconductor integrated circuit, the transmission of data from the chip A to the chip B and the transmission of a trigger signal (trigger), which is a control signal, from the chip A to the chip B are performed by time-division multiplexing using a DOUT terminal that connects the chip A and the chip B to each other; and the transmission of data from the chip B to the chip A and the transmission of a status signal (status), which is a control signal, from the chip B to the chip A are performed by time-division multiplexing using a DIN terminal that connects the chip A and the chip B to each other.
H01L 25/04 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs sous-groupes différents du même groupe principal des groupes , ou dans une seule sous-classe de ,
H04J 3/00 - Systèmes multiplex à division de temps
The purpose of the present invention is to enhance the cross regulation accuracy of a DC-DC converter comprising a SEPIC circuit adapted for multiple outputs for supplying positive and negative output voltages. [Solution] In a multi-output SEPIC circuit 1 comprising: reactors Lin, L1, L2; a switching element Q1; coupling capacitors C1, C2; rectifying elements D1, D2; and output capacitors Co1, Co2, the connection of the coupling capacitor C2 and the reactor Lin is changed. The present invention is characterized by changing the connection of the coupling capacitor C2 so that the coupling capacitor C2 is connected to a node of the coupling capacitor C1, the anode of the rectifying element D1, and the reactor L1.
H02M 3/155 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs
[Problem] To provide a lateral semiconductor device having a high breakdown voltage. [Solution] On the surface of a high-breakdown-voltage diffusion layer island, a high-concentration floating diffusion layer (1E18 atoms/cc or more) having a conductivity type opposite to that of the high-breakdown-voltage diffusion layer island and connected to the high-breakdown-voltage diffusion layer island is formed concentrically around an electrode lead-out portion from the high-breakdown-voltage diffusion layer as a center. As a result, annular equipotential regions defined by the element structure can be designed in a concentric multistage configuration, and by increasing the number of stages, a stable high-breakdown-voltage structure can be easily realized. In addition, reliability problems such as a decrease in breakdown voltage during long-term use are less likely to occur.
SANKEN ELECTRIC KOREA CO.,LTD. (République de Corée)
Inventeur(s)
Park Changyoung
Lim Baeyoung
Abrégé
[Problem] Power modules require high heat-sinking performance, and hence, the objective of the present invention is to provide a four-sided cooling power module that can exhibit an enhanced heat-sinking performance as package structure. [Solution] This four-sided cooling power module comprises: a first base on which electronic parts are mounted; a second base that is opposed to the first base; and a sealing resin that seals the first base and the second base with respective portions thereof exposed. The first base consists of a first region, a second region and a third region. The electronic parts are mounted on the first region. The second region and the third region are oriented orthogonally to the first region. The second base is joined to some of the electronic parts mounted on the first region. The four sides that are the external sides of the first base and of the second base are exposed from the sealing resin.
Provided is a watchdog timer device capable of optimizing both a method that causes interruption and a method that causes resetting. This watchdog timer device comprises: a count value reception unit (2) that receives and holds CTOA and CTOB; a counter (3) that determines, in a WDT mode, occurrence of timeout when a count value with CTOA serving as an initial value is counted down to "0" without receiving input of a count clear request CCRA, and determines, in an RT mode, occurrence of timeout when a count value with CTOB serving as an initial value is counted down to "0" without receiving input of a count clear request CCRB; and a mode setting unit (4) that sets an initial state to the WDT mode, and causes the WDT mode to transition to the RT mode when determining occurrence of timeout in the WDT mode or causes the RT mode to transition to the WDT mode by receiving input of the count clear request CCRB in the RT mode.
[Problem] To provide a semiconductor device of a vertical trench gate MOS structure having high breakage resistance at a terminal portion. [Solution] A semiconductor device of a vertical trench gate MOS structure, wherein: a deep P layer is formed between a termination trench which has a single field plate inside the trench and an active trench which is adjacent to the termination trench and which has a gate electrode inside the trench and a field plate below the gate electrode; and the deep P layer is positioned between the field plate and the gate electrode of the adjacent active part trench.
[Problem] To provide a semiconductor device with improved heat dissipation. [Solution] A semiconductor device which, on the semiconductor chip back surface, has protrusions formed from the same semiconductor as that of the semiconductor chip, wherein the protrusions are covered with a metal that has good thermal conductivity. By covering the protrusions with a metal, the heat dissipation from the protruding portion is improved, and it is possible to improve heat dissipation of the entire semiconductor chip. Further, heat dissipation can be further improved by adopting structures in which the protrusions covered by a metal in the chip center portion are longer than the protrusions covered by metal in the chip in the peripheral portion, and structures in which the density of protrusions covered by metal in the chip center portion is higher than the density of the protrusions covered by metal in the chip peripheral portion.
SANKEN ELECTRIC KOREA CO.,LTD. (République de Corée)
Inventeur(s)
Park Changyoung
Park Hyungsang
Abrégé
[Problem] To provide a dual-side cooled power module, wherein a stepped structure provided with a thick metal layer on a substrate is used, whereby spacers and a bonding material between spacers can be omitted to reduce the number of components, packaging material costs and manufacturing steps can be reduced, the occurrence of defects can be prevented, and manufacturing costs can be reduced. [Solution] Provided is a structure wherein a first substrate and a second substrate are made to face each other, a semiconductor chip is bonded therebetween, and sealed with resin, each of the first and the second substrates being provided with a first metal layer, an insulating layer, and a second metal layer, a bonding part with the semiconductor chip of the second metal layer being provided with a CTE-modifiable metal.
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs sous-groupes différents du même groupe principal des groupes , ou dans une seule sous-classe de ,
H01L 23/373 - Refroidissement facilité par l'emploi de matériaux particuliers pour le dispositif
SANKEN ELECTRIC KOREA CO.,LTD. (République de Corée)
Inventeur(s)
Park Changyoung
Kim Juyoung
Abrégé
[Problem] To provide a semiconductor power module including a DBC substrate having metal patterns with different thicknesses, and thereby reduce the number of components, simplify the manufacturing process, and reduce the manufacturing cost of the semiconductor power module. The present invention also improves the flexibility of the structural design of a semiconductor power module. [Solution] In a package structure of this semiconductor power module in which a power chip and a control chip are mounted on a DBC substrate, metal patterns of the DBC substrate include a power chip mounting part (power part) and a control chip mounting part (signal part), and the metal thickness of the power chip mounting part is greater than the metal thickness of the control chip mounting part. Also, the power chip is a flip chip type and has a structure in which clip leads are provided in wiring.
H01L 23/12 - Supports, p.ex. substrats isolants non amovibles
H01L 23/36 - Emploi de matériaux spécifiés ou mise en forme, en vue de faciliter le refroidissement ou le chauffage, p.ex. dissipateurs de chaleur
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs sous-groupes différents du même groupe principal des groupes , ou dans une seule sous-classe de ,
14.
POWER SOURCE FOR DRIVING SYNCHRONOUS RECTIFICATION ELEMENT OF SEPIC CONVERTER
The present invention stably supplies a power source for driving a DC-DC converter including a synchronous rectification-type SEPIC circuit. A synchronous rectification-type SEPIC circuit 1, including inductors 2, 5, a switch element 3, a capacitor 4, a synchronous rectification element 6, and an output capacitor 7, is provided with a drive voltage switching unit 15 for stably supplying a drive signal voltage of the synchronous rectification element 6 regardless of whether an output voltage Vo is greater or less than a drive power voltage Vdrv of the synchronous rectification element 6. The drive voltage switching unit 15 is characterized by including a means for: switching connection so that power is supplied from the output voltage Vo to a second drive circuit 10 if the output voltage Vo is set higher than the drive power voltage Vdrv; and switching connection so that power is supplied from the drive voltage Vdrv if the output voltage Vo is set lower than the drive voltage Vdrv.
H02M 3/155 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs
Provided is an A/D conversion circuit with which it is possible to eliminate an offset error without increasing the layout area or the consumed current, even when a memory-cell-overwriting comparator is used. A sequential-comparison analog/digital conversion circuit (1) comprising a capacity DAC (2) that generates a potential for each bit on the basis of an analog input, a comparator (3) that compares the potentials generated by the capacity DAC (2), and a conversion data generator (4) that generates conversion data of a resolution bit on the basis of the result of comparison by the comparator (3), the analog/digital conversion circuit (1) converting the analog input to a digital conversion value and outputting the digital conversion value, wherein the comparator (3) is a memory-cell-overwriting comparator provided with a first-stage current-mirror-type operational amplifier (10) and a second-stage memory cell (20), and the analog/digital conversion circuit (1) also comprises a correction circuit (5) that corrects an output error of the conversion data originating from an offset error in the comparator (3) through addition/subtraction of an offset correction value, which is a fixed value, and that outputs the corrected conversion data as the digital conversion value.
H03M 1/46 - Valeur analogique comparée à des valeurs de référence uniquement séquentiellement, p.ex. du type à approximations successives avec convertisseur numérique/analogique pour fournir des valeurs de référence au convertisseur
H03K 5/08 - Mise en forme d'impulsions par limitation, par application d'un seuil, par découpage, c. à d. par application combinée d'une limitation et d'un seuil
Provided is an A/D conversion circuit capable of achieving increased speed by eliminating allocation of excessive [capacitive DAC settling time]. This successive comparison type A/D conversion circuit (10) converts analog input into a digital conversion value by repeating, for each resolution bit, a conversion data generating operation, a potential generating operation, and a comparison operation, and converts analog input into a digital conversion value by repeating, for each resolution bit, the conversion data generating operation carried out by a conversion data generator (40), the potential generating operation carried out by a capacitive DAC (2), and the comparison operation carried out by a comparator (3). The successive comparison type analog/digital conversion circuit (10) comprises a comparator operation signal generating circuit (5) that predicts, on the basis of the capacitance C0-C (n-1) used by the capacitive DAC (2) and the charging/discharging period for a capacitive element (51) having equivalent characteristics, the timing at which a potential generated by the capacitive DAC (2) will stabilize, and generates a comparator operation signal that causes the comparator (3) to start a comparison operation.
H03M 1/46 - Valeur analogique comparée à des valeurs de référence uniquement séquentiellement, p.ex. du type à approximations successives avec convertisseur numérique/analogique pour fournir des valeurs de référence au convertisseur
[Problem] To provide a trench-gate-type MOSFET having fast switching speed and high surge tolerance. [Solution] In the trench-gate-type MOSFET, the resistance value of the source region near the gate electrode is increased, and the resistance value of the source region far from the gate electrode is lowered. As a method for changing the resistance value, the concentration of diffused impurities may be made lower in the source region near the gate electrode than in the source region far from the gate electrode. Similarly, as the method for changing the resistance value, there is a method of having the same impurity concentration at the source region near the gate region and the source region far from the gate electrode, and inputting impurities having low mobility in the source region near the gate electrode and impurities having high mobility in the source region far from the gate electrode.
SANKEN ELECTRIC KOREA CO.,LTD. (République de Corée)
Inventeur(s)
Kim Woojin
Park Changyoung
Abrégé
[Problem] Since there is variation in the thicknesses of materials stacked on top of one another in a dual side cooling power module, stacking the materials one by one makes it difficult to keep the stacked thickness of the entire module constant. [Solution] In order to control the stacked height of this dual side cooling power module when the thickness tolerances of materials directly influence the thickness tolerance of the entire module, a die or the like is stacked on and attached to mutually facing insulated substrates, and thereafter a joining material (adhesive) attached lastly to the substrates is made to act as a cushioning joining layer (buffer adhesion layer) with a reflow process in which a special metal jig is used and pre-drying is not performed.
H01L 23/36 - Emploi de matériaux spécifiés ou mise en forme, en vue de faciliter le refroidissement ou le chauffage, p.ex. dissipateurs de chaleur
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs sous-groupes différents du même groupe principal des groupes , ou dans une seule sous-classe de ,
H01L 21/52 - Montage des corps semi-conducteurs dans les conteneurs
19.
DIMMING AGENT AND LIGHT-EMITTING DEVICE CONTAINING DIMMING AGENT
[Problem] The objective of the present invention is to provide a dimming agent and a light-emitting device, capable of limiting brightness without lowering the current value of a current being injected into an LED. [Solution] The invention is the dimming agent having a diffuse reflection intensity of 80% or lower at wavelengths from 400 nm to 750 nm, characterized by containing at least one among terbium, praseodymium, manganese, and titanium.
H01L 33/50 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails caractérisés par les éléments du boîtier des corps semi-conducteurs Éléments de conversion de la longueur d'onde
H01L 33/56 - Matériaux, p.ex. résine époxy ou silicone
20.
ABNORMALITY DETECTION CIRCUIT AND ABNORMALITY DETECTION METHOD
Provided are an abnormality detection circuit and an abnormality detection method which are capable of temporally and logically monitoring a program sequence. This abnormality detection circuit is equipped with: a seed value register (13) which is a seed value storage unit that stores a seed value (SEED) in such a manner that the seed value (SEED) can be read from a CPU (2); a calculation unit (14) which performs a predetermined calculation process on the seed value stored in the seed value register (13), and thereby generates a check key value (CKEY); a write key register (15) which is a key value storage unit to which a key value (WKEY) is written by the CPU (2); and a comparator (16) which compares the key value (WKEY) written to the write key register (15) with the check key value (CKEY). If the key value (WKEY) written to the write key register (15) matches the check key value (CKEY), then a counter (12) is reset, and the seed value (SEED) determined at the time of resetting the counter (12) is stored in the seed value register (13).
H01L 21/60 - Fixation des fils de connexion ou d'autres pièces conductrices, devant servir à conduire le courant vers le ou hors du dispositif pendant son fonctionnement
H01L 21/822 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants le substrat étant un semi-conducteur, en utilisant une technologie au silicium
H01L 27/04 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur
Provided is a power conversion device in which an output circuit can immediately stop the supply of power in a state in which a microcomputer can be stopped. The power conversion device is provided with: an output circuit (10) that executes a power conversion operation in which input power is converted to a prescribed output power and output; and a microcomputer (20) that is supplied power from an internal power supply (12) of the output circuit (10), and controls the power conversion operation by the output circuit (10). The microcomputer (20) outputs, to the output circuit (10), a state signal that provides notification of whether the microcomputer (20) is in a power supply stoppable period in which the power supply can be stopped, or in a power supply non-stoppable period in which the power supply cannot be stopped. The output circuit (10) is provided with a power supply stopping circuit (14) that stops the supply of power from the internal power supply (12) to the microcomputer (20) when, upon input of an operation stop signal instructing that the power conversion operation be stopped, it can be confirmed via the state signal that the microcomputer (20) is in a power supply stoppable period.
Provided are a processor and an event processing method which are capable of measuring, in real time, the time it takes to return to a RUN state after executing an EVTWAIT instruction, without consuming external timer resources. This processor is provided with: a timer counter TMR which starts counting from an initial value; an event input control unit (26) which detects an event input that indicates occurrence of an event; an EVTWAIT instruction detection unit (27) which detects a wait event in response to the event input; a state control unit (30) which, in response to an EVTWAIT instruction, causes a transition from a RUN state to a WAIT state and outputs a count start signal, and which, in response to the detection of the wait event, causes a transition from the WAIT state to the RUN state and outputs a count end signal; and a TMRCAP register (23) which retrieves and holds the count value of the timer counter TMR in response to the count end signal output from the state control unit (30).
G06F 1/14 - Dispositions pour le contrôle du temps, p.ex. horloge temps réel
G06F 1/3234 - Gestion de l’alimentation, c. à d. passage en mode d’économie d’énergie amorcé par événements Économie d’énergie caractérisée par l'action entreprise
In the present invention, a digital/analog converter included in an A/D conversion circuit is provided with: a plurality of bit circuits which include, so as to correspond to a plurality of bits, capacitors outputting comparative potential from one ends thereof and having capacity values increasing from lower-order bits to the higher-order bits of the plurality of bits, first switches positioned at the other ends of the capacitors and having applied thereto input potential, and series circuits comprising second switches and current amount control elements and positioned between the other ends of the capacitors and a reference power source; and a current amount control unit for controlling a current amount flowing through the current amount control elements provided to the bit circuits. In a case where the second switches are switched on, by digital values, sequentially from the higher-order bit in the respective bit circuits, and during a period in which a second switch in any one of the bit circuits that has a noise current equal to or higher than an allowable value is switched on, the noise current being proportional to electrical charge flowing from the corresponding capacitor to the reference power source, the current amount control unit regulates the noise current so to be lower than the allowable value by applying current control potential to a current amount control element in any one of the bit circuits.
H03M 1/46 - Valeur analogique comparée à des valeurs de référence uniquement séquentiellement, p.ex. du type à approximations successives avec convertisseur numérique/analogique pour fournir des valeurs de référence au convertisseur
H03M 1/08 - Compensation ou prévention continue de l'influence indésirable de paramètres physiques du bruit
The present invention is provided with: a voltage detection unit 1 for detecting an output voltage and converting the detected output voltage to a digital value having a predetermined number of bits; a digital filter 4 for performing a predetermined calculation on the basis of the error between a target value and the output of the voltage detection unit; a drive unit 5 for driving switching elements with a predetermined duty in a filter characteristic analysis period and controlling a main switching element with a duty based on the calculation result of the digital filter after the completion of the filter characteristic analysis period; a current detection unit 6 for detecting a current flowing through an inductor and outputting the detected current as a current detection signal; a filter characteristic analysis unit 7 for analyzing, on the basis of the current detection signal from the current detection unit, the characteristics of a filter constituted by the inductor and an output capacitor from the period of occurrence of a rush current flowing through the inductor in the filter analysis period; and a constant storage unit 8 having a plurality of digital filter constant tables in which a plurality of filter constants corresponding to a plurality of filter characteristics are stored, selecting a proper filter constant from among the plurality of digital filter constant tables in accordance with the filter characteristics after the completion of the filter characteristic analysis period, and supplying the selected filter constant to the digital filter.
H02M 3/155 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs
Task #: 946 / Project: Abstracts JA-EN 199617 / Asset: pctjp2018046755-ttad-000001-en-ja.xml This semiconductor device comprises: a drift region (30) having an SJ structure that is placed on a semiconductor substrate (10), for which a first columnar region (31) of a first electrically conductive type and a second columnar region (32) of a second electrically conductive type are placed in alternating fashion; a base region (40) of the second electrically conductive type that is placed on the drift region (30); a source region (50) of the first electrically conductive type that is placed on the base region (40); and gate electrodes (80) placed inside grooves that pass through the source region (50) and the base region (40). The second columnar region (32) of the drift region (30) is formed with the recombination center density of holes and electrons higher in an upper region (32A) than in a lower region (32B).
A semiconductor device, provided with a semiconductor substrate 10 in which an element region 110 and a periphery region 120 surrounding the element region 110 are defined on a main surface thereof. Outer peripheral trenches 20, having an insulating film 21 disposed on the inner wall surface of a groove and an electroconductor film 22 disposed on the insulating film 21 inside the groove, are disposed on the periphery region 120 so as to surround the element region 110. The electroconductor film 22 of the outer peripheral trenches 20 is set to a potential higher than the potential of the negative-side main electrode of a semiconductor element formed on the element region 110.
UHVHWHULVLWLULVLWLUHVHWHWH by upper/lower complementary switching with a dead time Td in between; a mask generation unit (56) for generating a mask period including the dead time Td; and a zero cross detection unit (51) for detecting a zero cross of back electromotive force in a period other than the mask period on the basis of the phase voltage in a non-conduction period.
H02P 6/182 - Dispositions de circuits pour détecter la position sans éléments séparés pour détecter la position utilisant la force contre-électromotrice dans les enroulements
The present invention is a processor that performs a pipeline process in which a plurality of threads are processed, and commands that include a wait command and correspond to the thread numbers of the threads are executed and processed in parallel. Pipeline processing units 1-4 comprise a fetching unit for fetching the commands of the threads for which an execution right has been obtained, a decoding unit for decoding the commands fetched by the fetching unit, and an operation execution unit for executing the commands decoded by the decoding unit. When the wait command of the threads for which the execution right has been obtained is executed, command holding units 14-0, 14-1 hold information on the command fetch of process commands processed subsequent to the wait command. An execution thread selection unit 5 selects the threads to be executed on the basis of a wait instruction, and when the wait state in effect from the time of execution of the wait command is canceled, executes the threads starting from the decoding of the process commands on the basis of the information on the command fetch of the process commands held in the command holding units.
G06F 9/30 - Dispositions pour exécuter des instructions machines, p.ex. décodage d'instructions
G06F 9/32 - Formation de l'adresse de l'instruction suivante, p.ex. par incrémentation du compteur ordinal
G06F 9/46 - Dispositions pour la multiprogrammation
G06F 12/0875 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p.ex. mémoires cache avec mémoire cache dédiée, p.ex. instruction ou pile
This semiconductor device includes a semiconductor substrate (10) which has, defined on a top surface thereof, an element region (110) and a surrounding region (120) that surrounds the element region (110). A plurality of trenches (20) are arranged surrounding the element region (110) in multiple layers in the surrounding region (120), each of the trenches (20) having an insulating film (21) that is disposed on an inner wall of a groove extending from the top surface of the semiconductor substrate (10) in the film thickness direction and a conductor film (22) that is disposed on the insulating film (21) inside the groove. The surrounding region (120) has an inner region (121) that is close to the element region (110) and an outer region (122) that is positioned around the inner region (121), and the widths of the semiconductor substrate (10) between adjoining trenches (20) are larger in the inner region (121) than in the outer region (122).
This semiconductor device is provided with: a second conductive-type embedded region (20) that is embedded in a part of the upper surface of a first conductive-type semiconductor substrate (10); a second conductive-type first semiconductor region (30) that is disposed above the semiconductor substrate (10) so as to cover the embedded region (20) and that has an impurity concentration lower than that of the embedded region (20); a first conducive-type connection region (40) that is embedded in a part of the upper surface of the semiconductor substrate (10) in a remaining region obtained by excluding the region where the first semiconductor region (30) is disposed, and that has a side surface connected to an extension region (31) which is a part of the lower part of the first semiconductor region (30); and a first conductive-type second semiconductor region (50) that is disposed on the upper surface of the connection region (40) and has a side surface connected to the first semiconductor region (30). The extension region (31) of the first semiconductor region (30) extends below the end of the second semiconductor region (50), and comes into contact with the side surface of the connection region (40).
A trench gate type IGBT, comprising: a first semiconductor area (10) of a first electrically conductive type; a second semiconductor area (20) of the first electrically conductive type placed on the main surface of the first semiconductor area (10), with a higher impurity concentration than the first semiconductor area (10); a third semiconductor area (30) of a second electrically conductive type, placed on the top surface of the second semiconductor area (20), with impurities of an impurity concentration profile having a plurality of peaks along the film thickness direction added; and a fourth semiconductor area (40) of the first electrically conductive type placed on the top surface of the third semiconductor area (30).
H01L 29/739 - Dispositifs du type transistor, c.à d. susceptibles de répondre en continu aux signaux de commande appliqués commandés par effet de champ
H01L 21/336 - Transistors à effet de champ à grille isolée
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
33.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME
A semiconductor device comprising: a semiconductor substrate (10); a first interlayer dielectric film (21) disposed on a major surface of the semiconductor substrate (10); a second interlayer dielectric film (22) disposed on the first interlayer dielectric film (21); and an electrical conductor film (30) which is embedded in an opening continuously penetrating through the first interlayer dielectric film (21) and the second interlayer dielectric film (22) and which is in contact with the major surface of the semiconductor substrate (10). A first inclination angle S1 formed by a side surface of the first interlayer dielectric film (21) and the major surface of the semiconductor substrate (10) is smaller than a second inclination angle S2 formed by an extension line of the side surface of the second interlayer dielectric film (22) and the major surface of the semiconductor substrate (10), and an upper surface of the second interlayer dielectric film (22) is inclined so as to approach the semiconductor substrate (10) gradually outward from the upper end of the opening.
A semiconductor device, provided with: a semiconductor substrate (10) having a first main surface (11) and a second main surface (12) opposite each other, a measurement pad being disposed on the first main surface (11); and a stress film (20) disposed on the first main surface (11) and/or the second main surface (12), the stress film (20) producing a stress in the semiconductor substrate (10) that causes warpage, in which the first main surface (11) becomes concave, so that the warpage amount of the semiconductor substrate (10) at room temperature is 30 to 60 μm. The stress is produced by the difference in thermal expansion coefficient between the semiconductor substrate (10) and the stress film (20).
A semiconductor device comprises: a second conductivity type buried region (20) buried in the upper surface of a first conductivity type semiconductor substrate (10); a second conductivity type first semiconductor region (30) that is disposed on the upper surface of the semiconductor substrate (10) so as to cover the buried region (20) and has a lower impurity concentration than the buried region (20); a first conductivity type second semiconductor region (40) disposed on the upper surface of the semiconductor substrate (10) in a remaining region of the region where the first semiconductor region (30) is disposed; a second conductivity type drain region (50) disposed on the upper surface of the first semiconductor region (30); a second conductivity type source region (60) disposed on the upper surface of the second semiconductor region (40); and a gate electrode (80) disposed above the second semiconductor region (40) between the drain region (50) and the source region (60), wherein the position, in plan view, of the opposite end of the buried region (20) facing the second semiconductor region (40) is between the end of the gate electrode (80) on the side closer to the drain region (50) and the drain region (50).
The present invention comprises: a plurality of processors 11a-11c for executing mutually different processes; a multiplexer 12-X for selecting one processor from within the plurality of processors; a checker processor 16; a comparator 14-X for comparing the external state of the processor selected by the multiplexer with the external state of the checker processor or comparing the internal state of the processor selected by the multiplexer with the internal state of the checker processor; and a controller 21 for determining, on the basis of the comparison result of the comparator, that the selected processor or the checker processor is abnormal when the external states or the internal states do not match.
G06F 11/16 - Détection ou correction d'erreur dans une donnée par redondance dans le matériel
G06F 11/18 - Détection ou correction d'erreur dans une donnée par redondance dans le matériel en utilisant un masquage passif du défaut des circuits redondants, p.ex. par logique combinatoire des circuits redondants, par circuits à décision majoritaire
An SJ power MOSFET 10 having a super-junction structure wherein, in order to achieve better speed increase in switching speed and stabilization of voltage resistance, the MOSFET 10 is configured so that a P–pillar layer 20 disposed between drift layers 13, which are N– pillar layers, is formed from a P column upper layer 21 and a P column lower layer 22, and when the defect density of the P column upper layer 21 is defined as Da, the impurity density of the P column upper layer 21 is defined as Ca, the defect density of the P column lower layer 22 is defined as Db, and the impurity density of the P column lower layer 22 is defined as Cb, the conditions Db > Da and Ca > Cb are satisfied.
0nn provided in correspondence to a plurality of power conversion units and each detecting an output current of each of the plurality of power conversion units as an individual current; and a pulse corrector (3) which generates an individual pulse signal for each of the plurality of power conversion units on the basis of the entire current, the individual current, and the reference pulse signal, and outputs the individual pulse signal for each of the plurality of power conversion units to each of the plurality of power conversion units as a drive signal for a switching element. The pulse corrector (3) determines a number N' of operation phases of the power conversion units on the basis of the entire current, and outputs the individual pulse signal to each of the determined number N' of operation phases of the power conversion units.
H02M 3/155 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs
H02M 7/483 - Convertisseurs munis de sorties pouvant chacune avoir plus de deux niveaux de tension
BRBGBBGBG is added, the light emitting device being configured such that, through use of the absorption characteristics of the blue–green phosphor 25, a blue light component in a short-wave-side blue region of the blue LED 10 is dimmed and a component extending from the nearest ultraviolet to the blue short-wavelength side is suppressed; and a lighting fixture using this light emitting device.
H01L 33/50 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails caractérisés par les éléments du boîtier des corps semi-conducteurs Éléments de conversion de la longueur d'onde
A light-emitting device (1) is provided with three light-emitting units (10, 20, 30) formed by storing, in packages (13, 23, 33), blue light emitting elements (11, 21, 31) having three different wavelength bands, and outputs white light having a predetermined chromaticity by performing color mixture of output light beams of the three light-emitting units (10, 20, 30). In an xy chromaticity diagram, the chromaticity of each of the output light beams of the three light-emitting units (10, 20, 30) is located at a fixed distance from a predetermined chromaticity, and a difference between the chromaticity for each of the output light beams of the three light-emitting units (10, 20, 30) and the predetermined chromaticity is set to 0.04 or less.
This semiconductor device is provided with a nitride semiconductor layer, and a switching element that includes: first portions of first electrodes formed on the nitride semiconductor layer; second electrodes formed on the nitride semiconductor layer; and first control electrodes, which are provided between the second electrodes and the first portions of the first electrodes, and which are formed on the nitride semiconductor layer. The semiconductor device is also provided with a driving transistor that includes: second portions of the first electrodes, said second portions connecting to each other the first portions of the first electrodes adjacent to each other, and being formed on the nitride semiconductor layer; a third electrode, which is formed on the nitride semiconductor layer, and which transmits a signal to the first control electrodes; and a second control electrode, which is provided between the third electrode and the second portions of the first electrodes, and which is formed on the nitride semiconductor layer. Consequently, when the switching element is turned off, the switching element is capable of holding the off-state even if a drain voltage applied to the switching element is fluctuated.
H01L 21/338 - Transistors à effet de champ à grille Schottky
H01L 27/095 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte à barrière Schottky
H01L 29/41 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
H01L 29/812 - Transistors à effet de champ l'effet de champ étant produit par une jonction PN ou une autre jonction redresseuse à grille Schottky
43.
SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREFOR
This semiconductor device comprises: a first nitride compound semiconductor layer; a second nitride compound semiconductor layer above the first nitride compound semiconductor layer; a two-dimensional electron gas layer near the interface between the first nitride compound semiconductor layer and second nitride compound semiconductor layer, a first electrode electrically connected to the two-dimensional electron gas layer; a second electrode electrically connected to the two-dimensional electron gas layer; a recessed portion provided on the surface of the second nitride compound semiconductor layer, between the first electrode and second electrode; and an auxiliary film comprising a p-type nitride semiconductor provided in the recessed portion, electrically connected to the first electrode and separated from the second electrode. On the above basis, a rise in on-resistance can be controlled against while also controlling against current collapse.
H01L 21/338 - Transistors à effet de champ à grille Schottky
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
H01L 29/812 - Transistors à effet de champ l'effet de champ étant produit par une jonction PN ou une autre jonction redresseuse à grille Schottky
The present invention comprises: a support substrate 10; a light-emitting element 20 which is disposed on the support substrate 10 and which includes a layered structure containing a second semiconductor layer 23 above a first semiconductor layer 21 with a light-emitting layer 22 therebetween; and a frame 100A which is disposed at a peripheral area above the support substrate 10 so as to cover the periphery of the light-emitting element 20, and which is penetrated so that the topmost surface of the layered structure is exposed.
H01L 33/48 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails caractérisés par les éléments du boîtier des corps semi-conducteurs
H01L 33/50 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails caractérisés par les éléments du boîtier des corps semi-conducteurs Éléments de conversion de la longueur d'onde
45.
LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING SAME
This light emitting device is provided with: a support substrate 10 which has a first major surface 101 and a second major surface 102; a light emitting element 20 which has a stacked structure having a second semiconductor layer 22 disposed over a first semiconductor layer 21, and which is disposed in a part of the first major surface 101; a metal oxide-containing resin 30 which is disposed on the first major surface 101 in a remaining region other than the region in which the light emitting element 20 is disposed, the metal oxide-containing resin 30 containing a metal oxide; and a light transmissive resin 40 disposed over the support substrate 10 with the light emitting element 20 interposed therebetween. The support substrate 10 and the light transmissive resin 40 are connected with the metal oxide-containing resin 30 interposed therebetween.
A switching power supply device of the present invention is provided with: a comparison value generation unit 2 that generates a first comparison value after starting up a power supply and raises a comparison value from the first comparison value up to a second comparison value larger than the first comparison value after an output voltage Vo reaches a first output voltage corresponding to the first comparison value; a digital filter 4 that performs a predetermined calculation on the error between the comparison value and the output voltage; a filter characteristic analysis unit 7 that analyzes, on the basis of a current detection signal output from a current detection unit 6 for detecting the current flowing through an inductor 103, the first output voltage, and a filter characteristic analysis period, a filter characteristic determined by the inductor and an output capacitor 104; and a filter constant storage unit 8 that selects, with reference to a plurality of digital filter constant tables 81, in a period during which the comparison value makes a transition from the first comparison value to the second comparison value, a filter constant according to the filter characteristic obtained from the filter characteristic analysis unit and supplies the selected filter constant to the digital filter.
H02M 3/155 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs
The present invention comprises: a substrate 40 in which a first arrangement area 41 and a second arrangement area 42 are defined on a main surface; a plurality of blue-light-emitting elements 10 which are arranged on the main surface of the substrate 40; and a fluorescent body sheet 30 containing a fluorescent body which emits excitation light excited by light emitted by the plurality of blue-light-emitting elements 10, and which is disposed above the plurality of blue-light-emitting elements 60. The plurality of blue-light-emitting elements 10 include: first blue-light-emitting elements 11 which are arranged in the first arrangement area 41, and which emit first emission light which has a first wavelength as the peak wavelength of the light emission spectrum; and second blue-light-emitting elements 12 which are arranged in the second arrangement area 42, and which emit second emission light which has, as the peak wavelength of the light emission spectrum, a second wavelength which is longer than the first wavelength by at least 10 nm.
H01L 33/50 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails caractérisés par les éléments du boîtier des corps semi-conducteurs Éléments de conversion de la longueur d'onde
Provided is a light-emitting device having a CSP structure, the light-emitting device being provided with: a support substrate 10; a first metallic film 40 disposed over the support substrate 10; a second metallic film 30 embedded in an upper portion of the first metallic film 40 and having side surfaces and a bottom surface covered by the first metallic film 40; and a light-emitting element 20 that covers the upper surface of the second metallic film 30 and is disposed over the first metallic film 40. The second metallic film 30 has a higher reflectivity for light exiting the light-emitting element 20 than the first metallic film 40, and migration is less likely to occur in the first metallic film 40 than in the second metallic film 30.
H01L 33/10 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails caractérisés par les corps semi-conducteurs ayant une structure réfléchissante, p.ex. réflecteur de Bragg en semi-conducteur
H01L 33/36 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails caractérisés par les électrodes
Provided is an AD conversion device with which it is possible to perform synchronization control of a plurality of AD converters independently of a higher-level device. An ADC (11, 12), provided with: an execution control unit (33) for controlling the execution of AD conversion; an event management unit 31 for switching a synchronization command signal SYNC to a high level and issuing a notification of a synchronization command when there has been a command for a simultaneous conversion event, in which a simultaneous conversion operation is set as an event; and an operation control unit (32). When there has been a notification of a synchronization command, and it has been confirmed that preparation for AD conversion is complete in the execution control unit (33), the operation control unit (32) switches the synchronization output signal SYNCOUT to a high level and notifies another ADC (12, 11) that the preparation for AD conversion is complete, and after confirming that all of the synchronization output signals SYNCOUT have switched to a high level and that preparation for AD conversion is complete in all of the ADCs (11, 12), commands the execution control unit (33) to execute a simultaneous conversion event.
This semiconductor device is equipped with a semiconductor substrate, a trench insulating film 50 that is disposed on the inner wall surface of a groove formed in the film thickness direction from the top surface of the semiconductor substrate and has a charged region which is positively charged, and a gate electrode 80 that is disposed above the trench insulating film 50 in the interior of the groove. The positive charge density of the charged region in a side portion of the trench insulating film 50 that is in the outer region touching the semiconductor substrate and is disposed on at least a side surface of the groove is higher than the positive charge density in the inner region of the trench insulating film opposite the outer region.
This semiconductor device is equipped with: a semiconductor substrate 10 in which a first groove 101 is formed as a mesh structure in plan view, and a second groove 102 is formed in each mesh opening section surrounded by the first groove 101; a first semiconductor element 1 that is formed on the semiconductor substrate 10 and provided with a first gate electrode 81 disposed in the interior of the first groove 101; and second semiconductor elements 2 that are each formed on the semiconductor substrate 10 and provided with a second gate electrode 82 disposed in the interior of the second groove 102 and surrounded by the first gate electrode 81.
H01L 27/04 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
52.
SUBSTRATE FOR SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SUBSTRATE FOR SEMICONDUCTOR DEVICE
The present invention is a substrate for a semiconductor device having a substrate, a buffer layer which is provided on the substrate and which comprises a nitride semiconductor, and a device active layer comprising a nitride semiconductor layer provided on the buffer layer, wherein the substrate for a semiconductor device is characterized in that: the buffer layer has a first region containing carbon and iron, and a second region which is located on the first region and which has a lower average concentration of iron than does the first region and a higher average concentration of carbon than does the first region; and the average concentration of carbon in the second region is lower than the average concentration of iron in the first region. Thereby provided is a substrate for a semiconductor device with which it is possible to suppress a lateral leak current during high-temperature operation of the device while suppressing a longitudinal leak current, and to suppress a current collapse phenomenon.
H01L 21/338 - Transistors à effet de champ à grille Schottky
H01L 21/20 - Dépôt de matériaux semi-conducteurs sur un substrat, p.ex. croissance épitaxiale
H01L 21/205 - Dépôt de matériaux semi-conducteurs sur un substrat, p.ex. croissance épitaxiale en utilisant la réduction ou la décomposition d'un composé gazeux donnant un condensat solide, c. à d. un dépôt chimique
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
H01L 29/812 - Transistors à effet de champ l'effet de champ étant produit par une jonction PN ou une autre jonction redresseuse à grille Schottky
This light-emitting device is provided with: a first light-emitting unit 10 including a first blue light-emitting element 11 which emits emitted light having a peak wavelength at a first wavelength, and a first fluorescent material layer 12, and which outputs white light having a first chromaticity; and a second light-emitting unit 20 including a second blue light-emitting element 21 which emits emitted light having a peak wavelength at a second wavelength that is longer than the first wavelength, and a second fluorescent material layer 22, and which outputs white light having a second chromaticity. The first chromaticity and the second chromaticity are positioned symmetrically, in an xy chromaticity diagram, with respect to a prescribed chromaticity, and the difference between the first chromaticity and the second chromaticity, and the prescribed chromaticity, is at most equal to 0.04.
H01L 33/50 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails caractérisés par les éléments du boîtier des corps semi-conducteurs Éléments de conversion de la longueur d'onde
Provided is a switching power supply device with which operation can be stabilized even if the output voltage greatly varies. This switching power supply device (1) generates a driving power supply Vcc for a primary-side control IC (10) that transmits to a secondary winding (S) input power (Vi) applied to a primary winding (P1), and returns power from the secondary winding (S) to an auxiliary winding (P2), thereby controlling the turning on/off of a switching element (Q1) from the auxiliary winding (P2). The power supply device is equipped with: a dropper circuit (30) that is turned on/off in accordance with the voltage of the auxiliary winding (P2), and that, when turned on, supplies to the primary-side control IC (10) a constant voltage obtained by stepping down the voltage of the auxiliary winding (P2), as the driving power supply Vcc; a dropper operation detection circuit (40) that detects the operation of the dropper circuit (30); and a condition changing circuit (an overcurrent detection condition correction circuit 50 and a gate resistance changing circuit 60) that, in accordance with the operation of the dropper circuit, uses a gate pulse for driving the switching element (Q1) to change the primary-side operating conditions.
H02M 3/28 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu avec transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrodes de commande pour produire le courant alternatif intermédiaire
The present invention comprises: a support substrate 10; a light-emitting element 20 arranged upon the support substrate 10 and having a laminated structure having a second semiconductor layer 23 arranged above a first semiconductor layer 21; a first electrode 41 arranged in a continuous manner from above a first side surface 101 of the support substrate 10 to above a first side surface 201 of the light-emitting element 20 and electrically connected to the first semiconductor layer 21; and a second electrode 42 arranged in a continuous manner from above a second side surface 102 of the support substrate 10 to above a second side surface 202 of the light-emitting element 20 and electrically connected to the second semiconductor layer 23.
The present invention comprises: a support substrate 10; a light-emitting element 20 arranged upon the support substrate 10 and having a laminated structure having a second semiconductor layer 23 arranged above a first semiconductor layer 21; a light-transmitting substrate 70 arranged above the light-emitting element 20; a first connection electrode 41 arranged in a continuous manner from above a first side surface 101 of the support substrate 10 to above a first side surface 701 of the light-transmitting substrate 70 and electrically connected to the first semiconductor layer 21; and a second connection electrode 42 arranged in a continuous manner from above a second side surface 102 of the support substrate 10 to above a second side surface 702 of the light-transmitting substrate 70 and electrically connected to the second semiconductor layer 23. The present invention is electrically connected to a mounting substrate via second side surfaces of the first connection electrode 41 and the second connection electrode 42, the second side surfaces being opposite first side surfaces facing the support substrate 10 and the light-transmitting substrate 70.
This semiconductor base body is characterized by being provided with: a silicon-based substrate; a buffer layer on the silicon-based substrate, said buffer layer including a layer wherein a first layer formed of a nitride compound semiconductor containing a first material, and a second layer formed of a nitride compound semiconductor containing a second material having a lattice constant that is larger than that of the first material are repeatedly provided; and a channel layer formed of a nitride compound semiconductor containing the second material, said channel layer being formed on the buffer layer. The semiconductor base body is also characterized in that: the buffer layer has, as at least one layer on the first layer, said one layer being between the first layer and the second layer, a first composition gradient layer formed of a nitride compound semiconductor, said first composition gradient layer having a second material composition ratio that is gradually increased in the upward direction, and a first material composition ratio that is gradually reduced in the upward direction, and, as at least one layer on the second layer, said one layer being between the second layer and the first layer, a second composition gradient layer formed of a nitride compound semiconductor, said second composition gradient layer having a first material composition ratio that is gradually increased in the upward direction, and a second material composition ratio that is gradually reduced in the upward direction; and the first composition gradient layer is thicker than the second composition gradient layer. Consequently, provided is the semiconductor base body capable of suppressing crystallinity deterioration and a crack length increase, even in the cases where the composition gradient layers are provided among the layers of the multilayer buffer layer, said component gradient layers having a lattice constant change quantity larger than 0.7%/nm.
H01L 21/338 - Transistors à effet de champ à grille Schottky
H01L 21/20 - Dépôt de matériaux semi-conducteurs sur un substrat, p.ex. croissance épitaxiale
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
H01L 29/812 - Transistors à effet de champ l'effet de champ étant produit par une jonction PN ou une autre jonction redresseuse à grille Schottky
The present invention provides a semiconductor device characterized by including a first conductive-type first semiconductor region, a second conductive-type second semiconductor region disposed on the first semiconductor region, a first conductive-type third semiconductor region disposed on the second semiconductor region, a second conductive-type fourth semiconductor region disposed on the third semiconductor region, a control electrode disposed so as to opposed to the third semiconductor region via an insulating film, a first electrode electrically connected to the first semiconductor region, a second electrode electrically connected to the fourth semiconductor region, a fifth semiconductor region disposed between the first semiconductor region and the second semiconductor region and having an impurity concentration that is higher than that of the second semiconductor region, and a sixth semiconductor region disposed between the first semiconductor region and the second semiconductor region and having an impurity concentration that is higher than that of the second semiconductor region but is lower than that of the fifth semiconductor region. As a result, a semiconductor device that hardly causes a latch-up phenomenon and that shows a low built-in potential can be provided.
H01L 29/739 - Dispositifs du type transistor, c.à d. susceptibles de répondre en continu aux signaux de commande appliqués commandés par effet de champ
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
59.
POWER FACTOR IMPROVEMENT CIRCUIT AND DC/DC CONVERTER
The present invention is provided with: a series circuit comprising a coil L1 connected to an output terminal of a rectifying circuit 2 and a switching element Q1; a rectifying and smoothing circuit comprising a rectifying element D1 and a smoothing capacitor Co; an arithmetic unit 33 which performs an arithmetic operation on a multiplied voltage and a voltage corresponding to a current flowing through the switching element or a current from the output terminal of the rectifying circuit, said multiplied voltage being obtained by multiplying an error voltage between an output voltage of the smoothing capacitor and a reference voltage by an output of the rectifying circuit; a superimposing circuit 36 which superimposes a signal based on the output of the rectifying circuit on a reference signal of a reference oscillator 32; and a control circuit 34 which generates a pulse signal by comparing an output of the superimposing circuit with an output from the arithmetic unit, and which turns on/off the switching element using the pulse signal.
H02M 7/06 - Transformation d'une puissance d'entrée en courant alternatif en une puissance de sortie en courant continu sans possibilité de réversibilité par convertisseurs statiques utilisant des tubes à décharge sans électrode de commande ou des dispositifs à semi-conducteurs sans éléctrode de commande
A semiconductor device of the present invention has an element region, in which a semiconductor element is formed, and an outer peripheral region disposed around the element region. The semiconductor device is provided with: first conductivity-type first semiconductor regions extending across the element region and the outer peripheral region; and second conductivity-type second semiconductor regions, each of which constitutes a super-junction structure wherein a pn junction is disposed between each of the first semiconductor regions and each of the second conductivity-type semiconductor regions. In the outer peripheral region, the total impurity quantity ratio of the total impurity quantity of the second conductivity-type second semiconductor regions with respect to the total impurity quantity of the first conductivity-type first semiconductor regions is closer to 1 than the total impurity quantity ratio in the element region.
The present invention is provided with: a first-conductivity-type first semiconductor region; second-conductivity-type second semiconductor regions which are arrayed apart from each other in the first semiconductor region so that a pn junction is formed between each of the second semiconductor regions and the first semiconductor region, and which stretch into a stripe pattern so that a super junction structure is formed in which the pn junctions are periodically arranged; a first main electrode which is arranged on the first main surface side of the first semiconductor region; a second main electrode which is arranged, in an element region, on the second main surface side of the first semiconductor region; a terminal electrode which is arranged at the outer edge of an outer periphery region on the second main surface side and which is electrically connected to the first main electrode; an insulating layer which is arranged, on the second main surface side, between the second main electrode and the terminal electrode; and a plurality of conductors which are arrayed apart from each other in the insulating layer, wherein the second main electrode and the terminal electrode are capacitively coupled by a capacitor group obtained by capacitors formed between the conductors being connected in series.
[Problem] To provide a switching power supply device capable of switching to a predetermined output voltage and maintaining high efficiency. [Solution] A switching power supply device that switches the setting of an output voltage thereof on the basis of an external signal is characterized by being equipped with: a transformer T1 having a primary winding P1 and secondary windings S1, S2; multiple synchronous rectification components SR1, SR2 corresponding to the number of the secondary windings, which are disposed in a secondary-side rectification section for rectifying respective pulse voltages of the secondary windings; a switch component SW2 for switching between the secondary windings S1, S2; and a control circuit 20 for on-off control of the synchronous rectification components SR1, SR2 and for turning on or off the switch component SW2, whereby the switch component SW2 is turned on or off according to whether the level of a voltage value set for an output voltage Vo is high or low, thereby selecting either one of the synchronous rectification components so as to perform synchronous rectification of the pulse voltage of the corresponding secondary winding, and when the output is stopped with the output voltage Vo being set to the high setting value, synchronous rectification component SR2 of the synchronous rectification components, which is located on the side for outputting the output voltage Vo having the high setting value, is caused to perform a switching operation so as to remain on until the output voltage Vo drops to the low voltage setting value.
H02M 3/28 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu avec transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrodes de commande pour produire le courant alternatif intermédiaire
63.
SEMICONDUCTOR DEVICE ON WHICH TWO-DIMENSIONAL CODE IS DISPLAYED
The purpose is to improve tracking of manufacturing information for a semiconductor device in which a two-dimensional code is seal-displayed on the mold surface. [Solution] A semiconductor device 1 internally provided with a power semiconductor 4 and a control IC 5 for ON/OFF-controlling the power semiconductor 4, wherein the semiconductor device 1 is characterized in being covered with a molding material for covering the power semiconductor 4 and the control IC 5, the power semiconductor element 4 and the control IC 5 being mounted so as to be set away from each other, and a two-dimensional code being formed on the molding material surface outside the surface on which the region in which the power semiconductor 4 is mounted is horizontally projected.
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/28 - Capsulations, p.ex. couches de capsulation, revêtements
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs sous-groupes différents du même groupe principal des groupes , ou dans une seule sous-classe de ,
64.
SEMICONDUCTOR BASE, SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SEMICONDUCTOR BASE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
The present invention is a semiconductor base characterized in being provided with: a substrate; a buffer layer comprising a nitride semiconductor, the buffer layer being provided on the substrate; and a channel layer comprising a nitride semiconductor, the channel layer being provided on the buffer layer; the buffer layer including a first region provided on the substrate side so that the concentration of boron is higher than the concentration of an acceptor element, and a second region provided on the first region so that the concentration of boron is lower than the first region and the concentration of the acceptor element is higher than the first region. Consequently, the semiconductor base is provided so that a high pit suppressing effect can be obtained while maintaining high longitudinal pressure resistance.
H01L 21/338 - Transistors à effet de champ à grille Schottky
H01L 21/205 - Dépôt de matériaux semi-conducteurs sur un substrat, p.ex. croissance épitaxiale en utilisant la réduction ou la décomposition d'un composé gazeux donnant un condensat solide, c. à d. un dépôt chimique
H01L 21/336 - Transistors à effet de champ à grille isolée
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 29/812 - Transistors à effet de champ l'effet de champ étant produit par une jonction PN ou une autre jonction redresseuse à grille Schottky
A light-emitting device is provided with: a first light-emitting diode which includes a first blue light emitting element emitting first emitted light having a relatively short peak wavelength and a first fluorescence material layer emitting first excited light by being excited by the first emitted light, and which outputs first mixed color light of first chromaticity in which the first emitted light and the first excited light are mixed; and a second light-emitting diode which includes a second blue light emitting element emitting second emitted light having a relatively long peak wavelength and a second fluorescence material layer emitting second excited light by being excited by the second emitted light, and which outputs second mixed color light of second chromaticity in which the second emitted light and the second excited light are mixed. The first chromaticity and the second chromaticity are located at symmetric positions with respect to a predetermined chromaticity along the color temperature characteristics of black-body radiation in an xy chromaticity diagram, and the first mixed color light and the second mixed color light are mixed to output output light of predetermined chromaticity.
H01L 33/50 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails caractérisés par les éléments du boîtier des corps semi-conducteurs Éléments de conversion de la longueur d'onde
The present invention is provided with a first semiconductor chip, a second semiconductor chip disposed so as to be electrically isolated from the first semiconductor chip, and a transmission transformer that is a chip transformer in which a conductor layer and an insulation layer are laminated, the transmission-side terminal of the transmission transformer connecting to the first semiconductor chip and the receiving-side terminal of the transmission transformer connecting to the second semiconductor chip. A control signal for controlling the operation of the second semiconductor chip is transmitted from the first semiconductor chip to the second semiconductor chip via the transmission transformer.
This semiconductor device is provided with: a first semiconductor chip and a second semiconductor chip, which are disposed by being electrically insulated from each other; and a first signal path and a second signal path, which transmit signals from the first semiconductor chip to the second semiconductor chip by means of magnetic field coupling in a chip transformer wherein a conductor layer and an insulating layer are laminated. Operations of the second semiconductor chip are controlled by means of first control signals transmitted via the first signal path, and second control signals transmitted via the second signal path.
The present invention is provided with: parallel converters in which a plurality of converters corresponding to a plurality of phases are connected in parallel to an output terminal of a rectifying circuit and each of the plurality of converters has a reactor, as well as a switching element and a diode connected in series to the reactor; a control circuit that generates a plurality of pulsed signals corresponding to the plurality of phases on the basis of an error voltage between the output voltage of a smoothing capacitor connected to the output terminals of the parallel converters and a reference voltage, as well as the output voltage of the rectifying circuit, and that turns on/off the switching elements in the plurality of converters according to the plurality of pulsed signals; and a plurality of current detectors that are provided so as to correspond to the plurality of converters and that detect electrical currents flowing in the switching elements. The control circuit improves the power factor and protects the switching elements on the basis of the electrical currents detected by the plurality of current detectors.
This semiconductor device substrate has: a substrate; a buffer layer, which is provided on the substrate, and is formed of a nitride semiconductor; and a device active layer configured from a nitride semiconductor layer provided on the buffer layer. The semiconductor device substrate is characterized in that: the buffer layer contains carbon and iron; the carbon concentration of the upper surface of the buffer layer is higher than the carbon concentration of the lower surface of the buffer layer; and the iron concentration of the upper surface of the buffer layer is lower than the iron concentration of the lower surface of the buffer layer. Consequently, provided is the semiconductor device substrate wherein a leak current in the lateral direction in high-temperature operation is reduced, while suppressing a leak current in the longitudinal direction.
H01L 21/338 - Transistors à effet de champ à grille Schottky
H01L 21/205 - Dépôt de matériaux semi-conducteurs sur un substrat, p.ex. croissance épitaxiale en utilisant la réduction ou la décomposition d'un composé gazeux donnant un condensat solide, c. à d. un dépôt chimique
H01L 21/336 - Transistors à effet de champ à grille isolée
H01L 29/207 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des composés AIIIBV caractérisés en outre par le matériau de dopage
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 29/812 - Transistors à effet de champ l'effet de champ étant produit par une jonction PN ou une autre jonction redresseuse à grille Schottky
[Problem] To provide a semiconductor device in which an increase in gate resistance is suppressed, and a decrease in voltage in an area between active regions caused by an imbalance among the voltage in an active region and the voltage in an area between active regions is suppressed. [Solution] In a plan view, a plurality of active regions are included in the direction in which grooves 100 extend. The grooves 100 are also formed in an area between active regions, and there is an auxiliary electrode in the area between active regions.
[Problem] To provide a current detection circuit capable of reducing computation and eliminating takeover of abnormal data. [Solution] The present invention comprises: a control unit (16) that PWM controls a switching element (Q1) for applying a current to a solenoid (L) at a prescribed PWM cycle; an A/D conversion unit (13) that samples and performs analog-to-digital conversion of a current value detected by a detecting unit (R1) at a cycle which is n-fold of the prescribed PWM cycle, and that outputs n times of AD conversion values every PWM cycle; and a moving average computation unit (14) that has a FIFO buffer (141) for storing the n times of AD conversion values from the A/D conversion unit. The moving average computation unit, to (n-1) times of AD conversion values obtained by subtracting the oldest AD conversion value from the FIFO buffer from the summation result of adding past n times of AD conversion values, adds the newest AD conversion value from the AD conversion unit and obtains a moving average total value for n times of AD conversion values, and divides the moving average total value by n to compute a moving average value.
G01R 19/25 - Dispositions pour procéder aux mesures de courant ou de tension ou pour en indiquer l'existence ou le signe utilisant une méthode de mesure numérique
G01R 19/00 - Dispositions pour procéder aux mesures de courant ou de tension ou pour en indiquer l'existence ou le signe
H02M 7/48 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant alternatif sans possibilité de réversibilité par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande
H02P 27/06 - Dispositions ou procédés pour la commande de moteurs à courant alternatif caractérisés par le type de tension d'alimentation utilisant une tension d’alimentation à fréquence variable, p.ex. tension d’alimentation d’onduleurs ou de convertisseurs utilisant des convertisseurs de courant continu en courant alternatif ou des onduleurs
H03K 17/687 - Commutation ou ouverture de porte électronique, c. à d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs les dispositifs étant des transistors à effet de champ
72.
LIGHT EMITTING LOAD DRIVING DEVICE AND LIGHT EMITTING DEVICE
Provided are a light emitting load driving device for driving, for example, an LED (light emitting diode) etc., and a light emitting device including the same, which include an abnormality detecting unit which enables reduction in power loss, enables reduction in mounting area, and is configured at a low cost. The light emitting load driving device 1 drives a light emitting load 2 which is composed of a first light emitting element D1 and a second light emitting element D2 connected in series and between both ends of which a first potential difference is applied. The light emitting load driving device 1 is provided with: a switching element M for controlling light of the light emitting load 2; a driving signal output unit 12 for switching and driving the switching element M; and an abnormality detection unit 13 connected to the first light emitting element D1 and driven by a second potential difference V2 which is smaller than the first potential difference V1.
EPITAXIAL SUBSTRATE FOR ELECTRONIC DEVICE, ELECTRONIC DEVICE, METHOD FOR PRODUCING EPITAXIAL SUBSTRATE FOR ELECTRONIC DEVICE, AND METHOD FOR PRODUCING ELECTRONIC DEVICE
The present invention is an epitaxial substrate for an electronic device, the epitaxial substrate having a Si-based substrate, an AlN initial layer provided on the Si-based substrate, and a buffer layer provided on the AlN initial layer, and the epitaxial substrate is characterized in that the roughness Sa of the surface on the buffer layer side of the AlN initial layer is 4 nm or more. Due to this configuration, provided is an epitaxial substrate for an electronic device, in which V-shaped pits in the buffer layer structure are prevented and longitudinal leak current characteristics can be improved when an electronic device is produced.
H01L 21/338 - Transistors à effet de champ à grille Schottky
H01L 21/20 - Dépôt de matériaux semi-conducteurs sur un substrat, p.ex. croissance épitaxiale
H01L 21/336 - Transistors à effet de champ à grille isolée
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 29/812 - Transistors à effet de champ l'effet de champ étant produit par une jonction PN ou une autre jonction redresseuse à grille Schottky
74.
EPITAXIAL WAFER, SEMICONDUCTOR ELEMENT, EPITAXIAL WAFER MANUFACTURING METHOD, AND SEMICONDUCTOR ELEMENT MANUFACTURING METHOD
This epitaxial wafer is characterized by having: a silicon-based substrate; a first buffer layer, which is disposed on the silicon-based substrate, and which has first multilayer structure buffer regions in each of which AlxGa1-xN layers and AlyGa1-yN layers (x>y) are alternately disposed, and first insertion layers each of which is configured from an AlzGa1-zN layer (x>z) that is thicker than the AlyGa1-yN layers, said first multilayer structure buffer regions and the first insertion layers being alternately disposed; a second buffer layer, which is disposed on the first buffer layer, and which has second multilayer structure buffer regions in each of which AlαGa1-αN layers and AlβGa1-βN layers (α>β) are alternately disposed, and second insertion layers each of which is configured from an AlγGa1-γN layer (α>γ) that is thicker than the AlβGa1-βN layers, said second multilayer structure buffer regions and second insertion layers being alternately disposed; and a channel layer, which is disposed on the second buffer layer, and which is thicker than the second insertion layer. The epitaxial wafer is also characterized in that the average Al composition of the second buffer layer is higher than the average Al composition of the first buffer layer. Consequently, the epitaxial wafer wherein warping of the wafer can be reduced and occurrence of internal cracks can be suppressed is provided.
H01L 21/205 - Dépôt de matériaux semi-conducteurs sur un substrat, p.ex. croissance épitaxiale en utilisant la réduction ou la décomposition d'un composé gazeux donnant un condensat solide, c. à d. un dépôt chimique
H01L 21/338 - Transistors à effet de champ à grille Schottky
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
H01L 29/812 - Transistors à effet de champ l'effet de champ étant produit par une jonction PN ou une autre jonction redresseuse à grille Schottky
Provided is a motor drive device capable of preventing worsening of motor efficiency, even when a Hall element is intermittently driven. The motor drive device 1 drives a 3-phase brushless DC motor M having arranged therein Hall elements 2U, 2V, 2W that detect the magnetic pole of a rotor and output a pair of Hall voltages having opposite polarity, as position detection means that detect rotor position. The motor drive device 1 comprises: an internal regulator 13 that intermittently outputs a drive voltage VReg to the Hall elements 2U, 2V, 2W and functions as a power supply between intermittently driven Hall sensors; and an electrical angle prediction unit 16 that predicts the zero cross timing for input Hall voltages. The internal regulator 13 switches to DC drive that outputs a constant drive voltage to the Hall elements 2U, 2V, 2W during a period from prior to Hall voltage zero cross to when the zero cross is detected, on the basis of the prediction results from the electrical angle prediction unit 16.
Provided is a motor drive device capable of preventing worsening of motor efficiency, even when a Hall element is intermittently driven. The motor drive device comprises: an internal regulator 13 that intermittently outputs a drive voltage to, and intermittently drives, Hall elements 2U, 2V, 2W; a drive circuit 11 that generates and outputs an applied voltage to drive windings LU, LV, LW for a three-phase brushless DC motor M; Hall amps AmpU, AmpV, AmpW that detect zero cross detection timing and generate Hall signals HU, HV, HW, said zero cross detection timing being the timing at which Hall voltages output from the Hall elements 2U, 2V, 2W zero cross; a rotation control unit 12 that drives the drive circuit 11; and an advance angle value generation unit 16 that generates an advance angle value that takes into account delays in zero cross detection timing caused by intermittent driving of the Hall elements 2U, 2V, 2W. The rotation control unit 12 advances the phase of the applied voltage on the basis of the advance angle value generated by the advance angle value generation unit 16.
A DC motor driving device of the present invention is equipped with: magnetic flux detection units (1 to 3) for detecting the magnetic fluxes of the rotor of a motor (11) and outputting magnetic flux detection signals; a rotor position detection circuit (13) for detecting rotor sectors on the basis of the magnetic flux detection signals; a control circuit (14) for outputting angle signals from the starting point to the ending point of the rotor sectors and for, when the magnetic flux detection signals indicate no movement of the rotor sectors, resuming the outputting of the angle signal for the same sector; a sine-wave generation circuit (15) for generating a sine-wave signal for driving the motor with a sine wave on the basis of the angle signal from the control circuit; and a motor driving unit (16) for creating a drive duty on the basis of the sine wave signal and turning on/off the switching elements according to the drive duty to drive the motor.
A semiconductor substrate of the present invention has: a substrate; a buffer layer on the substrate, said buffer layer being formed of a carbon-containing nitride semiconductor; a high-resistance layer on the buffer layer, said high-resistance layer being formed of a carbon-containing nitride semiconductor; and a channel layer on the high-resistance layer, said channel layer being formed of a nitride semiconductor. The semiconductor substrate is characterized in that the high-resistance layer has: a first region having a carbon concentration lower than that of the buffer layer; and a second region, which is provided between the first region and the channel layer, and which has a carbon concentration higher than that of the first region. Consequently, a leak current is reduced by improving crystallinity, while maintaining the high resistance of the high-resistance layer, and crystallinity of the channel layer formed on the high-resistance layer is also increased, thereby providing the semiconductor substrate wherein deterioration of electron mobility and generation of current collapse in the channel layer are suppressed.
H01L 21/338 - Transistors à effet de champ à grille Schottky
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
H01L 29/812 - Transistors à effet de champ l'effet de champ étant produit par une jonction PN ou une autre jonction redresseuse à grille Schottky
This semiconductor substrate comprises a substrate, a buffer layer on the substrate, a high-resistivity layer formed from a nitrogen semiconductor on the buffer layer and including a transition metal and carbon, and a channel layer formed from a nitrogen semiconductor on the high-resistivity layer. This semiconductor substrate is characterized in that the high-resistivity layer comprises a reduction layer which is in contact with the channel layer and in which the concentration of the transition metal reduces from the buffer layer side to the channel layer side, and the reduction ratio at which the carbon concentration reduces towards the channel layer is greater than the reduction ratio at which the concentration of the transition metal reduces towards the channel layer. By this means, it is possible to provide a semiconductor substrate with higher resistivity in the region of the high-resistivity layer facing the channel layer while reducing the transition metal concentration and the carbon concentration inside of the channel layer.
H01L 21/338 - Transistors à effet de champ à grille Schottky
H01L 21/205 - Dépôt de matériaux semi-conducteurs sur un substrat, p.ex. croissance épitaxiale en utilisant la réduction ou la décomposition d'un composé gazeux donnant un condensat solide, c. à d. un dépôt chimique
H01L 29/207 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des composés AIIIBV caractérisés en outre par le matériau de dopage
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
H01L 29/812 - Transistors à effet de champ l'effet de champ étant produit par une jonction PN ou une autre jonction redresseuse à grille Schottky
80.
SEMICONDUCTOR SUBSTRATE MANUFACTURING METHOD, SEMICONDUCTOR ELEMENT MANUFACTURING METHOD, SEMICONDUCTOR SUBSTRATE AND SEMICONDUCTOR ELEMENT
This method is for manufacturing a semiconductor substrate which comprises a substrate, an initial layer disposed on the substrate, a high-resistivity layer comprising a carbon-containing nitrogen semiconductor on the initial layer, and a channel layer comprising a nitrogen semiconductor and disposed on the high-resistivity layer. This method is characterized in that the step for forming the high-resistivity layer involves forming the high-resistivity layer such that the set temperature for heating a semiconductor substrate has a gradient and the set temperature at the start of formation of the high-resistivity layer and the set temperature at completion of formation of the high-resistivity layer are different. By this means, a semiconductor substrate manufacturing device is provided which can decrease the concentration gradient of the carbon concentration in a high-resistivity layer and can set the carbon concentration to a desired value.
H01L 21/338 - Transistors à effet de champ à grille Schottky
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
H01L 29/812 - Transistors à effet de champ l'effet de champ étant produit par une jonction PN ou une autre jonction redresseuse à grille Schottky
This semiconductor device is provided with: a collector region of a first conductivity type; a field stop region of a second conductivity type, which is arranged on the collector region; a drift region of the second conductivity type, which is arranged on the field stop region and has a lower impurity concentration than the field stop region; a base region of the first conductivity type, which is arranged on the drift region; and an emitter region of the second conductivity type, which is arranged on the base region. The impurity concentration gradient of the field stop region in the film thickness direction is larger in a region adjacent to the collector region than in a region adjacent to the drift region.
H01L 29/739 - Dispositifs du type transistor, c.à d. susceptibles de répondre en continu aux signaux de commande appliqués commandés par effet de champ
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
The present invention is provided with: a switching element (S1); a drive unit (10), which is connected to a gate of the switching element (S1), and which drives the switching element (S1); and an abnormality detection unit (20), which supplies a constant current to a control terminal of the switching element (S1), and which detects an abnormality of the switching element (S1) on the basis of a transient change of a control terminal voltage of the switching element (S1).
H03K 17/00 - Commutation ou ouverture de porte électronique, c. à d. par d'autres moyens que la fermeture et l'ouverture de contacts
H03K 17/687 - Commutation ou ouverture de porte électronique, c. à d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs les dispositifs étant des transistors à effet de champ
The present invention is provided with the following: a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type disposed on top of the first semiconductor region; a third semiconductor region of the first conductivity type disposed on top of the second semiconductor region; a fourth semiconductor region of the second conductivity type disposed on top of the third semiconductor region; an insulating film disposed on the inner walls of grooves that extend from the upper surface of the fourth semiconductor region and pass through the fourth semiconductor region and the third semiconductor region until reaching the second semiconductor region; control electrodes that are disposed on top of the insulating film on the side surfaces of the grooves and that face the third semiconductor region; a first main electrode that electrically connects to the first semiconductor region; a second main electrode that electrically connects to the fourth semiconductor region; and bottom-surface electrodes that are disposed on top of the insulating film at the bottom surfaces of the grooves and are disposed separated from the control electrodes. In a planar view, the length in the direction of extension of the grooves is greater than the width of the grooves, and the width of the grooves is greater than the spacing between adjacent grooves.
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 21/28 - Fabrication des électrodes sur les corps semi-conducteurs par emploi de procédés ou d'appareils non couverts par les groupes
H01L 21/336 - Transistors à effet de champ à grille isolée
H01L 29/41 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/739 - Dispositifs du type transistor, c.à d. susceptibles de répondre en continu aux signaux de commande appliqués commandés par effet de champ
84.
SEMICONDUCTOR SUBSTRATE, SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD
This semiconductor substrate is characterized by including a silicon substrate, a buffer layer provided on the silicon substrate and comprising a boron-containing, nitride-based semiconductor, and an active layer formed on the buffer layer, wherein the boron concentration in the buffer layer gradually decreases from the silicon-based substrate towards the active layer. By this means, a semiconductor substrate is provided in which the buffer layer contains sufficient boron to obtain a transition suppressing effect, but the boron does not diffuse to the active layer.
H01L 21/205 - Dépôt de matériaux semi-conducteurs sur un substrat, p.ex. croissance épitaxiale en utilisant la réduction ou la décomposition d'un composé gazeux donnant un condensat solide, c. à d. un dépôt chimique
H01L 21/338 - Transistors à effet de champ à grille Schottky
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
H01L 29/812 - Transistors à effet de champ l'effet de champ étant produit par une jonction PN ou une autre jonction redresseuse à grille Schottky
85.
SILICON-BASED SUBSTRATE, SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD
This silicon-based substrate is for forming a nitride-based compound semiconductor layer on the surface, and is characterized by comprising a surface-side first portion having a first impurity concentration, and a second portion having a second impurity concentration higher than the first impurity concentration and disposed inwards of the first portion, and is further characterized in that the first impurity concentration is greater than or equal to 1×1014 atoms/cm3 and less than 1×1019 atoms/cm3. By this means, a silicon-base substrate is provided which can satisfactorily maintain crystallinity of the nitride-based compound semiconductor layer formed on the top layer while ameliorating substrate warping.
H01L 21/20 - Dépôt de matériaux semi-conducteurs sur un substrat, p.ex. croissance épitaxiale
H01L 21/205 - Dépôt de matériaux semi-conducteurs sur un substrat, p.ex. croissance épitaxiale en utilisant la réduction ou la décomposition d'un composé gazeux donnant un condensat solide, c. à d. un dépôt chimique
H01L 21/336 - Transistors à effet de champ à grille isolée
H01L 21/338 - Transistors à effet de champ à grille Schottky
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 29/812 - Transistors à effet de champ l'effet de champ étant produit par une jonction PN ou une autre jonction redresseuse à grille Schottky
This semiconductor device is characterized by having: a silicon-based substrate; a first buffer layer provided on the silicon-based substrate and comprising alternately laminated first layers, which include an Al composition, and second layers, which have a lower content of Al than the first layers; a second buffer layer provided on the first buffer layer and comprising alternately laminated third layers, which include an Al composition, and fourth layers, which have a lower content of Al than the third layers; and a third buffer layer provided on the second buffer layer and comprising alternately laminated fifth layers, which include an Al composition, and sixth layers, which have a lower content of Al than the fifth layers. On the whole, the second buffer layer has a greater content of Al than the first buffer layer and the third buffer layer. By this means, a semiconductor device is provided which improves flatness of the top surface of the active layer and suppresses leaks while decreasing stress acting on the buffer layers.
H01L 21/338 - Transistors à effet de champ à grille Schottky
H01L 21/20 - Dépôt de matériaux semi-conducteurs sur un substrat, p.ex. croissance épitaxiale
H01L 21/205 - Dépôt de matériaux semi-conducteurs sur un substrat, p.ex. croissance épitaxiale en utilisant la réduction ou la décomposition d'un composé gazeux donnant un condensat solide, c. à d. un dépôt chimique
H01L 21/336 - Transistors à effet de champ à grille isolée
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 29/812 - Transistors à effet de champ l'effet de champ étant produit par une jonction PN ou une autre jonction redresseuse à grille Schottky
87.
SEMICONDUCTOR MANUFACTURING APPARATUS, SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD
An apparatus of the present invention is provided with a tray (12) disposed in a chamber, and a heater (20) that heats the tray (12) from the lower surface side, and the apparatus forms an electron supply layer (123) on a substrate (110) by heating the substrate (110) disposed on the tray (12) by means of the heater (20) via the tray (12), said electron supply layer being configured from a nitride compound semiconductor. This semiconductor manufacturing apparatus is characterized in being configured such that, at the time of forming the epitaxial growth layer (123), an amount of heat to be applied to the tray (12) from the heater (20) can be increased in a region where the distance between the lower surface of the substrate (110) and the upper surface of the tray (12) is large compared with a region where the distance between the lower surface of the substrate (110) and the upper surface of the tray (12) is small. Consequently, the semiconductor manufacturing apparatus, which is capable of reducing temperature distribution generated in the substrate at the time of forming the epitaxial growth layer, is provided.
H01L 21/205 - Dépôt de matériaux semi-conducteurs sur un substrat, p.ex. croissance épitaxiale en utilisant la réduction ou la décomposition d'un composé gazeux donnant un condensat solide, c. à d. un dépôt chimique
C23C 16/46 - Revêtement chimique par décomposition de composés gazeux, ne laissant pas de produits de réaction du matériau de la surface dans le revêtement, c. à d. procédés de dépôt chimique en phase vapeur (CVD) caractérisé par le procédé de revêtement caractérisé par le procédé utilisé pour le chauffage du substrat
C30B 25/10 - Chauffage de l'enceinte de réaction ou du substrat
A semiconductor device according to the present invention, having an Au based solder layer (3) sandwiched between a semiconductor element (1) and a Cu substrate (2) made mainly of Cu, wherein the semiconductor device comprises: a dense metal film (23) which is arranged between the Cu substrate (2) and the Au based solder layer (3), and has fine slits (24) patterned to have a prescribed shape in a plan view; and fine structures (4) with dumbbell-like cross section, which have Cu and Au as main elements, and are each buried in the fine slits of the Cu substrate (2), the Au based solder layer (3), and the dense metal film (23).
To provide a power semiconductor module which is capable of suppressing the transfer of the heat generated in a semiconductor element to the outside. This power semiconductor module is characterized by comprising a ceramic substrate (11), semiconductor elements (13a, 13b, 14a, 14b) arranged on one main surface (11a) of the ceramic substrate, terminals (22a-22g) connected to the semiconductor elements, a first heat dissipation member (41) that is arranged on the other main surface (11b) of the ceramic substrate, and a second heat dissipation member (61) that is arranged on the one main surface side of the ceramic substrate at a distance from the semiconductor elements. This power semiconductor module is also characterized in that the terminals are connected to the second heat dissipation member.
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 23/34 - Dispositions pour le refroidissement, le chauffage, la ventilation ou la compensation de la température
H01L 23/36 - Emploi de matériaux spécifiés ou mise en forme, en vue de faciliter le refroidissement ou le chauffage, p.ex. dissipateurs de chaleur
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs sous-groupes différents du même groupe principal des groupes , ou dans une seule sous-classe de ,
90.
INSULATING SUBSTRATE、MULTILAYER CERAMIC INSULATING SUBSTRATE, JOINED STRUCTURE OF POWER SEMICONDUCTOR DEVICE AND INSULATING SUBSTRATE, AND POWER SEMICONDUCTOR MODULE
This insulating substrate (100) has a ceramic substrate (21), and low-thermal expansion/contraction metal plates (12-1, 12-2) bonded to at least one surface of the ceramic substrate (21). The low-thermal expansion/contraction metal plates (12-1, 12-2) are provided with a pair of Cu plates (14, 15) of substantially equal thickness, and a low-thermal expansion metal plate (13) disposed between the pair of Cu plates (14, 15), and having a lower coefficient of thermal expansion than the Cu plates (14, 15).
H01L 23/12 - Supports, p.ex. substrats isolants non amovibles
H01L 23/13 - Supports, p.ex. substrats isolants non amovibles caractérisés par leur forme
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs sous-groupes différents du même groupe principal des groupes , ou dans une seule sous-classe de ,
H05K 1/09 - Emploi de matériaux pour réaliser le parcours métallique
The present invention is a method for manufacturing a nitride semiconductor device, wherein a III-V nitride semiconductor multilayer film is grown in a reaction furnace into which a group III element starting material gas and a group V element starting material gas are introduced. The method is characterized: by including a step for growing a first nitride semiconductor layer using a a first starting material gas flow rate for the group V element starting material gas and a first carrier gas flow rate, and a step for growing a second nitride semiconductor layer using a second starting material gas flow rate lower than the first starting material gas flow rate for the group V element starting material gas and a second carrier gas flow rate higher than the first carrier gas flow rate; and having the first nitride semiconductor layer and the second nitride semiconductor layer laminated to each other. Consequently, it is possible to provide a method for manufacturing a nitride semiconductor device whereby a laminated structure of III-V nitride semiconductor layers is grown at V/III ratios suitable for the respective layers.
H01L 21/205 - Dépôt de matériaux semi-conducteurs sur un substrat, p.ex. croissance épitaxiale en utilisant la réduction ou la décomposition d'un composé gazeux donnant un condensat solide, c. à d. un dépôt chimique
H01L 21/338 - Transistors à effet de champ à grille Schottky
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
H01L 29/812 - Transistors à effet de champ l'effet de champ étant produit par une jonction PN ou une autre jonction redresseuse à grille Schottky
H01L 33/32 - Matériaux de la région électroluminescente contenant uniquement des éléments du groupe III et du groupe V de la classification périodique contenant de l'azote
92.
EPITAXIAL SUBSTRATE, SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD
The present invention is an epitaxial substrate comprising a silicon substrate containing oxygen atoms at a concentration from 4 × 1017 cm-3 to 6 × 1017 cm-3 and boron atoms at a concentration from 5 × 1018 cm-3 to 6 × 1019 cm-3, and a semiconductor layer arranged on top of the silicon substrate having a coefficient of thermal expansion different from that of the silicon substrate. In this way, an epitaxial substrate can be provided which suppresses warping due to stress between the silicon substrate and the semiconductor layer.
H01L 21/20 - Dépôt de matériaux semi-conducteurs sur un substrat, p.ex. croissance épitaxiale
H01L 21/205 - Dépôt de matériaux semi-conducteurs sur un substrat, p.ex. croissance épitaxiale en utilisant la réduction ou la décomposition d'un composé gazeux donnant un condensat solide, c. à d. un dépôt chimique
This thermally insulated load jig (11) is characterized in that a solder material (14) that has a melting point or a solidus curve temperature within a range of no more than 100°C from the thermal resistance temperature of a semiconductor chip (13) is interposed between a circuit substrate (12) and the semiconductor chip (13), a thermal insulating body (17) is disposed on top of the semiconductor chip (13) being in the condition described above, a metal weight (16) is placed on top of the thermal insulating body (17), and a load is applied to the semiconductor chip (13) while the solder material (14) is being fused and hardened.
NATIONAL UNIVERSITY CORPORATION SHIMANE UNIVERSITY (Japon)
Inventeur(s)
Terui, Hiromitsu
Asuke, Hideki
Takano, Hideharu
Yamamoto, Masayoshi
Kawashima, Takahiro
Abrégé
A bidirectional DC-DC converter wherein: the winding (1a) of a reactor (L), a reactor (Lsat1), and a switch (Tr1) are connected in series and are connected to both ends of a direct current power supply (V1); a series circuit comprising a switch (Tr2) and a direct current power supply (V2) is connected to both ends of the transistor (Tr1); a winding (1b) of the reactor (L), a reactor (Lsat2), a switching switch (Sw1), and a diode (D3) are connected in series and are connected to both ends of a series circuit comprising the reactor (Lsat1) and the switch (Tr1); and a switching switch (Sw2), a diode (D4, V2) are connected in series and are connected to both ends of a series circuit comprising the switching switch (SW1) and the diode (D3). In addition, the bidirectional DC-DC converter has a control circuit (10) that turns on/off the switches (Tr1, Tr2) and the switching switches (SW1, SW2).
H02M 3/155 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs
NATIONAL UNIVERSITY CORPORATION SHIMANE UNIVERSITY (Japon)
Inventeur(s)
Terui, Hiromitsu
Asuke, Hideki
Takano, Hideharu
Yamamoto, Masayoshi
Imaoka, Jun
Abrégé
A DC-DC converter having: a coupling transformer having a winding (11) and a winding (12); switches (Tr1, Tr2) respectively connected to both ends of a direct current power supply (Vi) via the windings; series circuits connected to both ends of each switch and comprising a diode and a smoothing capacitor; and a control circuit (100) that alternately turns on the switch (Tr1) and the switch (Tr2), and simultaneously turns on the switch (Tr1) and the switch (Tr2) for a prescribed overlap period for every half-cycle. Furthermore, with the coupling transformer (1), an I-shaped core (4) is sandwiched between two E-shaped cores (2, 3), with a gap (5) being provided between the middle legs (2a, 3a) of the E-shaped cores (2, 3) and the I-shaped core (4), and the winding (11) and the winding (12) being wound around the I-shaped core (4).
H02M 3/155 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs
H01F 30/00 - Transformateurs fixes non couverts par le groupe
96.
EPITAXIAL SUBSTRATE, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
The present invention is provided with a silicon-based substrate (11) and an epitaxial growth layer (12) that has first and second nitride semiconductor layers that differ from each other in lattice constant and coefficient of thermal expansion alternately stacked and which is disposed on the silicon-based substrate (11) such that film thickness at the outer edge parts gradually becomes thinner. Thus, an epitaxial substrate in which occurrences of cracks at the outer edge parts are suppressed, a semiconductor device, and a method for manufacturing the semiconductor device are provided.
H01L 21/205 - Dépôt de matériaux semi-conducteurs sur un substrat, p.ex. croissance épitaxiale en utilisant la réduction ou la décomposition d'un composé gazeux donnant un condensat solide, c. à d. un dépôt chimique
A light fitting (10) is provided with: an annular lighting part (14) comprising a plurality of lighting units (30a-30h), having LEDs positioned so as to emit light downwards, connected in a ring shape; and a power supply (15) which is positioned in the central space of the annular lighting part (14) and which supplies power to the annular lighting part (14). The lighting units (30) form a shape such that there is no space between adjoining lighting units when said units are connected in a ring shape, and it is possible to produce and assemble a lighting part with a variety of variations without detracting from the appearance thereof, by making slight variations to device specifications with compact manufacturing equipment.
F21S 8/04 - Dispositifs d'éclairage destinés à des installations fixes destinés uniquement au montage sur un plafond ou sur une structure similaire en porte-à-faux
F21V 23/00 - Agencement des éléments du circuit électrique dans ou sur les dispositifs d’éclairage
F21V 29/00 - Protection des dispositifs d'éclairage contre les détériorations thermiques; Dispositions de refroidissement ou de chauffage spécialement adaptées aux dispositifs ou systèmes d'éclairage
F21Y 101/02 - Structure miniature, p. ex. diodes électroluminescentes (LED)
Provided is a gate drive circuit capable of reducing the effects of switching noise and common mode noise on a gate drive signal, the switching noise being generated when an IGBT is turned on and off. The gate drive circuit is electrically isolated by a pulse transformer (T) into a primary side and a secondary side and outputs a gate drive signal induced in the secondary winding (N2) of the pulse transformer (T) through a receiver (CMP) equipped with impedance matching resistors (R1 to R4) on the input side, the primary side of the pulse transformer (T) being connected to a first ground voltage level point (GND1), the secondary side of the pulse transformer (T) being connected to a second ground voltage level point (GND2) electrically isolated from the first ground voltage level point (GND1). In the gate drive circuit, an electrostatic shield plate (5) is equipped between the primary winding (N1) and secondary winding (N2) of the pulse transformer and is grounded to the second ground voltage level point (GND2).
H02M 1/08 - Circuits spécialement adaptés à la production d'une tension de commande pour les dispositifs à semi-conducteurs incorporés dans des convertisseurs statiques
H03K 17/16 - Modifications pour éliminer les tensions ou courants parasites
H01F 27/36 - Blindages ou écrans électriques ou magnétiques
The present invention provides an LED lighting circuit capable of being safely handled by immediately lowering the output voltage when the input voltage from, for example, a commercial power supply has disappeared. The LED lighting circuit converts an input voltage to a desired DC voltage and supplies the DC voltage to an LED. The LED lighting circuit comprises: a transformer having at least a primary winding and a secondary winding; a switching element; a controller; an output capacitor; an input voltage detector; and a discharger. The input voltage detector detects the input voltage and outputs a discharge signal depending on the level of the detected input voltage to the discharger. The discharger is connected to both ends of the output capacitor and discharges the charge stored on the output capacitor in response to the discharge signal output from the input voltage detector.
H01L 33/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails
H02M 3/28 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu avec transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrodes de commande pour produire le courant alternatif intermédiaire
A semiconductor module which is provided with: a pair of semiconductor elements (16, 18) which are connected in series with each other and have first terminals (12, 14) that are electrically connected to a first power system (BT) and a second terminal (13) that is electrically connected to a second power system (M); a heat sink (7); a first electrode (10) that is electrically connected to the first terminal (12), which is one of the first terminals, and one electrode of the semiconductor element (16), which is one of the pair of semiconductor elements; an output electrode (11) that is electrically connected to the second terminal (13) and one electrode of the semiconductor element (18), which is the other one of the pair of semiconductor elements; and a second electrode (9) that is electrically connected to the first terminal (14), which is the other one of the first terminals. The second electrode (9) is connected to the heat sink (7) via a first insulating member (8a), and the output electrode (11) is connected to the second electrode (9) via a second insulating member (8b).
H01L 23/36 - Emploi de matériaux spécifiés ou mise en forme, en vue de faciliter le refroidissement ou le chauffage, p.ex. dissipateurs de chaleur
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs sous-groupes différents du même groupe principal des groupes , ou dans une seule sous-classe de ,
brevets
