Infineon Technologies Austria AG

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H01L 29/66 - Types of semiconductor device 427
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate 420
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions 361
H01L 29/40 - Electrodes 290
H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion 258
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1.

SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING THEREOF

      
Application Number 18522816
Status Pending
Filing Date 2023-11-29
First Publication Date 2024-06-13
Owner Infineon Technologies Austria AG (Austria)
Inventor
  • Zmölnig, Christian
  • Kahn, Markus
  • Steinbrenner, Juergen
  • Humbel, Oliver
  • Koprowski, Angelika
  • Kurzmann, Thomas

Abstract

The application refers to a semiconductor device including: a semiconductor body having a first surface and a second surface; an active region having at least one semiconductor cell configured to conduct a load current between the first surface and the second surface; an edge termination region separating the active region from a chip edge; and a first layer within at least a part of the edge termination region. The first layer includes silicon, nitrogen and hydrogen. In atomic numbers, a ratio of the silicon to the nitrogen is at least 3.3 to 4 in at least a portion of the first layer. At least the portion of the first layer includes at most 16 percent hydrogen in atomic numbers.

IPC Classes  ?

  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions

2.

AN ELECTRONIC MODULE INCLUDING A SEMICONDUCTOR PACKAGE DISPOSED ON AN INTERPOSER LAYER

      
Application Number 18583955
Status Pending
Filing Date 2024-02-22
First Publication Date 2024-06-13
Owner Infineon Technologies Austria AG (Austria)
Inventor
  • Fuergut, Edward
  • Chiola, Davide
  • Gruber, Martin
  • Hable, Wolfram

Abstract

An electronic module includes a semiconductor package including a die carrier, a semiconductor transistor die disposed on the die carrier, an electrical conductor connected to the semiconductor die, and an encapsulant covering the die carrier, the semiconductor die, and the electrical conductor so that a portion of the electrical conductor extends to the outside of the encapsulant. The electronic module further includes an interposer layer on which the semiconductor package is disposed, and a heat sink through which a cooling medium can flow. The interposer layer is disposed on the heatsink.

IPC Classes  ?

  • H01L 23/473 - Arrangements for cooling, heating, ventilating or temperature compensation involving the transfer of heat by flowing fluids by flowing liquids
  • H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

3.

APPARATUS WITH ELECTRICALLY COUPLED OUTPUT INDUCTORS

      
Application Number 18079184
Status Pending
Filing Date 2022-12-12
First Publication Date 2024-06-13
Owner Infineon Technologies Austria AG (Austria)
Inventor
  • Zhou, Yong
  • Clavette, Danny
  • Pullen, Stephen Roy

Abstract

An apparatus is configured according to a transformer based step down topology is provided. The apparatus includes a first transformer that transfers energy from a primary side of the first transformer to a secondary side of the first transformer for driving a load at the secondary side. The apparatus includes a first inductor and a second inductor electrically coupled at the secondary side. The apparatus includes a primary side directional conducting element and a secondary side directional conducting element configured to perform a first phase of transferring the energy through the first inductor and a second phase of transferring the energy through the second inductor. The first inductor induces the second inductor to transfer energy during the first phase and the second inductor induces the first inductor to transfer energy during the second phase.

IPC Classes  ?

  • H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load

4.

SEMICONDUCTOR DEVICE AND CORRESPONDING METHODS OF MANUFACTURE

      
Application Number 18443354
Status Pending
Filing Date 2024-02-16
First Publication Date 2024-06-13
Owner Infineon Technologies Austria AG (Austria)
Inventor
  • Huang, Weichun
  • Poelzl, Martin
  • Feil, Thomas Martin
  • Roesch, Maximilian

Abstract

A semiconductor device includes a contact opening extending through a source region and at least into a body region formed in a semiconductor substrate. The contact opening forms at least one sidewall in the semiconductor substrate. An electrically insulative spacer partially covers the at least one sidewall. A contact plug is in the contact opening. A body contact region is formed in the semiconductor substrate adjacent a bottom of the contact opening.

IPC Classes  ?

  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H01L 29/40 - Electrodes
  • H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 29/872 - Schottky diodes

5.

SEMICONDUCTOR DEVICE HAVING A SHIELDING LAYER AND A METHOD OF FABRICATING THE SEMICONDUCTOR DEVICE

      
Application Number 18078597
Status Pending
Filing Date 2022-12-09
First Publication Date 2024-06-13
Owner Infineon Technologies Austria AG (Austria)
Inventor
  • Ma, Ling
  • Haase, Robert
  • Henson, Timothy

Abstract

A semiconductor device includes: a semiconductor substrate; a plurality of transistors cells in an active device region of the semiconductor substrate, each transistor cell having a gate electrode separated from the semiconductor substrate by a gate dielectric; a plurality of needle-shaped field plate trenches in the active device region and in a termination region of the semiconductor substrate that is devoid of fully functional transistor cells; a polysilicon layer that forms the gate electrodes in the active device region and extends over at least part of the termination region; and a shielding layer that separates the polysilicon layer from the semiconductor substrate in the termination region, the shielding layer having a higher dielectric strength than just the gate dielectric. A method of producing the semiconductor device is also described.

IPC Classes  ?

  • H01L 29/40 - Electrodes
  • H01L 21/8234 - MIS technology
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 23/528 - Layout of the interconnection structure
  • H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
  • H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched

6.

METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE PACKAGE COMPRISING A PIN IN THE FORM OF A DRILLING SCREW

      
Application Number 18442173
Status Pending
Filing Date 2024-02-15
First Publication Date 2024-06-06
Owner Infineon Technologies Austria AG (Austria)
Inventor
  • Scharf, Thorsten
  • Bemmerl, Thomas
  • Gruber, Martin
  • Meyer, Thorsten
  • Singer, Frank

Abstract

A method of fabricating a semiconductor device package includes: providing a die carrier; disposing at least one semiconductor die on the die carrier, the semiconductor die comprising at least one contact pad on a main face remote from the carrier; electrically connecting the semiconductor die or another electrical device with an electrical connector; applying an encapsulant above the semiconductor die, the die carrier, and the electrical connector; and screwing a metallic drilling screw through the encapsulant so that an end of the drilling screw contacts the electrical connector.

IPC Classes  ?

  • H01L 23/498 - Leads on insulating substrates
  • H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
  • H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

7.

GATE DRIVER DEVICE HAVING A DRIVER CIRCUIT FOR SUPPLYING A BACKGATE DRIVE SIGNAL

      
Application Number 18439174
Status Pending
Filing Date 2024-02-12
First Publication Date 2024-06-06
Owner Infineon Technologies Austria AG (Austria)
Inventor
  • Priefert, Dirk
  • Albertini, Matteo
  • Boguszewicz, Remigiusz Viktor

Abstract

A gate driver device includes a first field effect transistor and a first driver circuit. The first field effect transistor includes a first gate electrode and a first backgate structure. The first driver circuit supplies a first backgate drive signal to the first backgate structure.

IPC Classes  ?

  • H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
  • H01L 21/762 - Dielectric regions
  • H03K 17/06 - Modifications for ensuring a fully conducting state

8.

CURRENT MONITORING AND CIRCUIT TEMPERATURE MEASUREMENTS

      
Application Number 18075711
Status Pending
Filing Date 2022-12-06
First Publication Date 2024-06-06
Owner Infineon Technologies Austria AG (Austria)
Inventor Wu, Wei

Abstract

An apparatus includes a controller that measures a first voltage across a first circuit path including a series connection of a first switch and a shunt resistor. The first voltage generated based on first current supplied from a first winding of a motor including multiple windings. Based on the magnitude of the first voltage, the controller determines an ON-resistance of the first switch. The ON-resistance can be used final office action any suitable purpose. For example, the controller can be configured to use the determined ON-resistance of the first switch to controller operation of a motor including the first winding. For example, the determined ON-resistance can be used as a basis to determine an amount of current through first switch and corresponding first winding of the motor.

IPC Classes  ?

  • H02P 21/22 - Current control, e.g. using a current control loop
  • H02P 21/14 - Estimation or adaptation of machine parameters, e.g. flux, current or voltage

9.

Semiconductor Package with Insert

      
Application Number 17994743
Status Pending
Filing Date 2022-11-28
First Publication Date 2024-05-30
Owner INFINEON TECHNOLOGIES AUSTRIA AG (Austria)
Inventor
  • Schwab, Stefan
  • Juerss, Michael
  • Scharf, Thorsten

Abstract

A semiconductor package includes a semiconductor die thermally coupled to a planar metal pad, an encapsulant body that encapsulates the semiconductor die and includes a recess that extends from an outer upper side of the encapsulant body towards a rear side of the planar metal pad, and an insert arranged within the recess that is thermally coupled to the planar metal pad and extends to the outer upper side of the encapsulant body, wherein the insert that is arranged within the recess includes a curable polymer compound.

IPC Classes  ?

  • H01L 23/495 - Lead-frames
  • H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
  • H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 23/498 - Leads on insulating substrates

10.

POWER SEMICONDUCTOR DEVICE WITH VOLTAGE CLAMP CIRCUIT

      
Application Number 18070585
Status Pending
Filing Date 2022-11-29
First Publication Date 2024-05-30
Owner Infineon Technologies Austria AG (Austria)
Inventor Leong, Kennith Kin

Abstract

A power semiconductor device includes: a main power switch having a drain, source, and gate; and a voltage clamp circuit in parallel with the main power switch and having a clamp voltage less than a breakdown voltage of the main power switch. The voltage clamp circuit includes: a pulldown switch having a normally-on gate electrically connected to the source of the main power switch; a plurality of series-connected diodes electrically connected between the drain of the main power switch and a drain of the pulldown switch; a voltage clamp device electrically connected between a source of the pulldown switch and the source of the main power switch; and a second power switch having a normally-off gate electrically connected to the drain of the pulldown switch, a drain electrically connected to the drain of the main power switch, and a source electrically connected to the source of the pulldown switch.

IPC Classes  ?

  • H03K 17/08 - Modifications for protecting switching circuit against overcurrent or overvoltage
  • H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
  • H01L 29/772 - Field-effect transistors
  • H01L 29/866 - Zener diodes

11.

POWER CONVERTER HAVING A SOLID-STATE TRANSFORMER AND A HALF BRIDGE CONVERTER STAGE FOR EACH ISOLATED DC OUTPUT OF THE SOLID-STATE TRANSFORMER

      
Application Number 18072065
Status Pending
Filing Date 2022-11-30
First Publication Date 2024-05-30
Owner Infineon Technologies Austria AG (Austria)
Inventor
  • Escudero Rodriguez, Manuel
  • Kutschak, Matteo-Alessandro
  • Pevere, Alessandro
  • Meneses Herrera, David

Abstract

A power converter includes: a solid-state transformer having a DC input and isolated DC outputs; a half bridge converter stage for each isolated DC output of the solid-state transformer, wherein an input of each half bridge converter stage is connected to the corresponding isolated DC output and an output of the half bridge converter stages are electrically connected in a cascade configuration; an output inductor shared by the half bridge converter stages and configured to deliver an output current; and a controller configured to implement phase shift control of the half bridge converter stages relative to one another, based on the number of half bridge converter stages and an output voltage of the power converter being regulated, such that each half bridge converter stage processes the full output current but only a fraction of the output voltage. Methods of controlling the power converter are also described.

IPC Classes  ?

  • H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion
  • H02M 1/42 - Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
  • H02M 3/00 - Conversion of dc power input into dc power output

12.

MISMATCH REDUCTION OF CAPACITIVE CHANNELS IN A COMMUNICATION SYSTEM

      
Application Number 17994805
Status Pending
Filing Date 2022-11-28
First Publication Date 2024-05-30
Owner Infineon Technologies Austria AG (Austria)
Inventor
  • Távora, Filipe Esteves
  • Ferianz, Thomas
  • Della Fortuna, Salvatore Angelo

Abstract

A first link disposed in a first capacitive channel (path) and a second link disposed in a second capacitive channel (path) of a communication system support conveyance of a respective differential signal from the first communication circuit to the second communication circuit of the communication system during a non-test mode. A controller controls the communication system to temporarily operate in a test mode to facilitate communications in the non-test mode. For example, while in the test mode, the controller determines adjustment settings in which to apply to an impedance adjustment circuit of the communication system to provide better RLC matching of the first capacitive channel and the second capacitive channel. Subsequent to the test mode and calibration, application of the adjustments to the first capacitive channel and the second capacitive channel reduce effects of a parasitic capacitance mismatch associated with at least the first link and the second link.

IPC Classes  ?

  • H04L 1/00 - Arrangements for detecting or preventing errors in the information received

13.

GROUP III NITRIDE TRANSISTOR DEVICE

      
Application Number 18503770
Status Pending
Filing Date 2023-11-07
First Publication Date 2024-05-23
Owner Infineon Technologies Austria AG (Austria)
Inventor
  • Pandya, Bhargav
  • Sanders, Anthony
  • Leong, Kennith Kin
  • Beer, Thomas
  • Ostermaier, Clemens

Abstract

In an embodiment, a Group III nitride transistor device includes a Group III nitride-based semiconductor body having a Group III nitride barrier layer arranged on a Group III nitride channel layer and forming a heterojunction therebetween capable of supporting a two-dimensional charge gas. A switching Group III nitride transistor device and a current sense Group III nitride transistor device are formed in the Group III nitride-based semiconductor body. The current sense Group III nitride transistor device is electrically insulated from the switching Group III nitride transistor device by local interruption of the two-dimensional charge gas.

IPC Classes  ?

  • H01L 27/095 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being Schottky barrier gate field-effect transistors
  • H01L 23/482 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of lead-in layers inseparably applied to the semiconductor body
  • H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
  • H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
  • H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT

14.

Semiconductor Package Providing an Even Current Distribution and Stray Inductance Reduction and a Semiconductor Device Module

      
Application Number 18505644
Status Pending
Filing Date 2023-11-09
First Publication Date 2024-05-23
Owner Infineon Technologies Austria AG (Austria)
Inventor
  • Schmoelzer, Bernd
  • Scholz, Wolfgang
  • Nikitin, Ivan

Abstract

A semiconductor package includes: a semiconductor transistor die having an emitter/source contact pad, a drain/collector contact pad, and a gate contact pad; at least two electrical connectors disposed in a symmetrical manner on opposing lateral sides of the semiconductor die and connected with at least one of the contact pads; and an encapsulant embedding the semiconductor transistor die. The two or more electrical connectors extend through the encapsulant and form protruding sections above an upper surface of the encapsulant.

IPC Classes  ?

  • H01L 23/495 - Lead-frames
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

15.

Semiconductor Package with Current Sensing

      
Application Number 17992189
Status Pending
Filing Date 2022-11-22
First Publication Date 2024-05-23
Owner INFINEON TECHNOLOGIES AUSTRIA AG (Austria)
Inventor
  • Goh, Shu Hui
  • Camuso, Gianluca
  • Gan, Thai Kee
  • Raberg, Wolfgang
  • Scholz, Wolfgang
  • Shi, Elvis Wei
  • Teoh, Joo Teng
  • Goh, Hui Wen
  • Lim, Chiao Eing

Abstract

A semiconductor package includes a lead frame that includes a die pad and a first lead extending away from the die pad, a semiconductor die mounted on the die pad, a load path connection that electrically connects a first load terminal of the semiconductor die with the first lead, and a magnetic sensor arrangement mounted directly on a region of the lead frame which forms part of the load path connection, wherein the magnetic sensor arrangement comprises a magnetic current sensor that is configured to measure a current flowing through the load path connection and an electrical isolation layer that electrically isolates the magnetic current sensor from the lead frame.

IPC Classes  ?

  • H01L 23/495 - Lead-frames
  • G01R 15/20 - Adaptations providing voltage or current isolation, e.g. for high-voltage or high-current networks using galvano-magnetic devices, e.g. Hall-effect devices
  • H01L 43/08 - Magnetic-field-controlled resistors

16.

POWER SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAME

      
Application Number 18388559
Status Pending
Filing Date 2023-11-10
First Publication Date 2024-05-16
Owner Infineon Technologies Austria AG (Austria)
Inventor
  • Böhm, Marcus
  • Wötzel, Stefan
  • Grassmann, Andreas
  • Schmoelzer, Bernd
  • Schindler, Uwe

Abstract

A power semiconductor package comprises a leadframe comprising a first die pad, a second die pad and a plurality of external contacts. The first and second die pads are separated by a first gap. A power semiconductor die is arranged on and electrically coupled to a first side of the first die pad. A diode is arranged on and electrically coupled to a first side of the second die pad. A molded body encapsulates the power semiconductor die and the diode, the molded body having a first side, an opposite second side and lateral sides connecting the first and second sides. A second side of the first die pad is exposed from the second side of the molded body. A second side of the second die pad is completely covered by an electrically insulating material.

IPC Classes  ?

  • H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different main groups of groups , or in a single subclass of , , e.g. forming hybrid circuits
  • H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
  • H01L 23/495 - Lead-frames

17.

DIODE LAYER STACK FLIP-CHIP MOUNTED TO A LEADFRAME BY USE OF A COPPER NICKEL TIN METALLIZATION STACK AND DIFFUSION SOLDERING

      
Application Number 18388386
Status Pending
Filing Date 2023-11-09
First Publication Date 2024-05-16
Owner Infineon Technologies Austria AG (Austria)
Inventor Otremba, Ralf

Abstract

A method for fabricating a diode layer stack comprises providing a diode layer stack including a silicon carbide diode die including a first main surface at an anode side of the diode die and a second main surface opposite to the first main surface at a cathode side of the diode die, a layer stack on the first main surface of the diode die, the layer stack including a copper layer disposed on the first main surface of the diode die, and a tin or indium containing layer disposed above the copper layer; providing a die pad comprising a copper leadframe including a first main surface and a second main surface opposite to the first main surface; and performing a diffusion soldering process for connecting the diode layer stack with the layer stack to the first main surface of the die pad.

IPC Classes  ?

  • H01L 23/495 - Lead-frames
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

18.

PACKAGE FOR A LATERAL POWER TRANSISTOR

      
Application Number 18488084
Status Pending
Filing Date 2023-10-17
First Publication Date 2024-05-16
Owner Infineon Technologies Austria AG (Austria)
Inventor
  • Chua, Kok Yau
  • Jones, Edward Andrew
  • Mostofizadeh, Milad
  • Ng, Chee Yang
  • Schiess, Klaus
  • Tee, Guan Choon Matthew Nelson

Abstract

A transistor package includes a power transistor chip having first and second opposite sides. The first side has source, drain, and gate electrode metallizations. A multi-layer laminate substrate includes: a first structured metal layer facing the first side of the chip and electrically connected to the source electrode metallization, the drain electrode metallization, and the gate electrode metallization; a second structured metal layer having a source package terminal pad, a source sense package terminal pad, a drain package terminal pad, and a gate package terminal pad; at least one insulating layer between the structured metal layers; and vias running through the insulating layer and connecting segments of the first structured metal layer to the terminal pads of the second structured metal layer.

IPC Classes  ?

19.

SEMICONDUCTOR DIE AND METHOD OF MANUFACTURING THE SAME

      
Application Number 18497409
Status Pending
Filing Date 2023-10-30
First Publication Date 2024-05-16
Owner Infineon Technologies Austria AG (Austria)
Inventor
  • Maurer, Daniel
  • Konrad, Sabine
  • Sack, Steffen
  • Ostermann, Thomas

Abstract

The disclosure relates to a semiconductor die and a method for manufacturing the semiconductor die. The semiconductor includes: a semiconductor body having an active region with a p-channel device formed in the active region; an insulation layer formed on the semiconductor body; and a sodium stopper formed in the insulation layer and arranged laterally between the active region and a lateral edge of the semiconductor die. The sodium stopper has an insulation layer groove which intersects the insulation layer vertically and extends around the active region. The insulation layer groove is filled with a diffusion barrier material.

IPC Classes  ?

  • H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

20.

Semiconductor Package with Molded Heat Dissipation Plate

      
Application Number 17977640
Status Pending
Filing Date 2022-10-31
First Publication Date 2024-05-02
Owner Infineon Technologies Austria AG (Austria)
Inventor
  • Son, Joon Seo
  • Jong, Man Kyo

Abstract

A method of producing a semiconductor package includes providing a molded plate that is formed of a first mold compound, providing a lead frame assembly that includes a lead frame and a semiconductor die mounted on a die pad of the lead frame, arranging the lead frame assembly and the molded plate within a molding chamber of a molding tool such that the molded plate is interposed between the die pad and an interior surface of the molding chamber, and performing a molding process that fills the molding chamber with a second mold compound that encapsulates the semiconductor die.

IPC Classes  ?

  • H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
  • H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
  • H01L 23/18 - Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
  • H01L 23/29 - Encapsulation, e.g. encapsulating layers, coatings characterised by the material
  • H01L 23/495 - Lead-frames

21.

ELECTRONIC DEVICE INCLUDING A SUPERCONDUCTING ELECTRONIC CIRCUIT

      
Application Number 18489400
Status Pending
Filing Date 2023-10-18
First Publication Date 2024-05-02
Owner Infineon Technologies Austria AG (Austria)
Inventor
  • Brandl, Florian
  • Braumüller, Jochen

Abstract

A method of manufacturing an electronic device includes generating a superconducting electronic circuit on a substrate. Metal oxides from metal surfaces of the superconducting electronic circuit are removed in a process chamber with a substantially oxygen-free environment. At least a portion of the superconducting electronic circuit is covered in situ by hermetic encapsulation.

IPC Classes  ?

  • H10N 60/81 - Containers; Mountings
  • H10N 60/01 - Manufacture or treatment
  • H10N 60/12 - Josephson-effect devices
  • H10N 69/00 - Integrated devices, or assemblies of multiple devices, comprising at least one superconducting element covered by group

22.

RC-IGBT AND MANUFACTURING METHOD OF RC-IGBT

      
Application Number 18483826
Status Pending
Filing Date 2023-10-09
First Publication Date 2024-04-25
Owner Infineon Technologies Austria AG (Austria)
Inventor
  • Dainese, Matteo
  • Elsayed, Ahmed
  • Hinz, Aleksander
  • Sandow, Christian Philipp

Abstract

A reverse conducting insulated gate bipolar transistor (RC-IGBT) includes an active area in a semiconductor body. The active area includes an IGBT area, a diode area, a transition area laterally adjacent to the diode area, trenches extending into the semiconductor body from a first surface of the semiconductor body, and a drift region of a first conductivity type that includes lifetime killing impurities in the transition area. The active area further includes a barrier region of the first conductivity type between the drift region and the first surface. A maximum doping concentration in the barrier region is at least 100 times larger than an average doping concentration in the drift region. The barrier region laterally extends through at least part of the transition area, and laterally ends in or before the diode area. The RC-IGBT further includes an edge termination area at least partly surrounding the active area.

IPC Classes  ?

  • H01L 27/07 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
  • H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
  • H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect

23.

TRANSISTOR DEVICE AND METHOD OF FABRICATING CONTACTS TO A SEMICONDUCTOR SUBSTRATE

      
Application Number 18483915
Status Pending
Filing Date 2023-10-09
First Publication Date 2024-04-25
Owner Infineon Technologies Austria AG (Austria)
Inventor
  • Lee, Seung Hwan
  • Rösch, Maximilian

Abstract

A transistor includes a semiconductor substrate having a first and second opposing major surfaces, a drain region of a first conductivity type at the second surface, a drift region of the first conductivity on the drain region, a body region of a second conductivity type that opposes the first conductivity type on the drift region, and a source region of a first conductivity type on and/or in the body region. A trench formed in the first surface has a base and sidewalls. A gate electrode in the trench is electrically insulated from the semiconductor substrate by a gate insulating layer. A field plate in the trench under the gate electrode is electrically insulated from the gate electrode and the semiconductor substrate by a field insulator. The base of the trench is positioned at a depth d from the first major surface, where 250 nm≤d≤800 nm.

IPC Classes  ?

  • H01L 29/40 - Electrodes
  • H01L 21/311 - Etching the insulating layers
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

24.

METHOD FOR PRODUCING A SUPERJUNCTION DEVICE

      
Application Number 18392923
Status Pending
Filing Date 2023-12-21
First Publication Date 2024-04-18
Owner Infineon Technologies Austria AG (Austria)
Inventor
  • Tutuc, Daniel
  • Kuenle, Matthias
  • Muri, Ingo
  • Weber, Hans

Abstract

Disclosed is a method for producing a semiconductor device, the method including forming a plurality of semiconductor arrangements one above the other, wherein forming each of the plurality of semiconductor arrangements includes forming a semiconductor layer, forming a plurality of trenches in a first surface of the semiconductor layer, and implanting dopant atoms of at least one of a first type and a second type into at least one of a first sidewall and a second sidewall of each of the plurality of trenches. Forming of at least one of the plurality of semiconductor arrangements further includes forming a protective layer covering mesa regions between the plurality of trenches of the respective semiconductor layer, and covering a bottom, the first sidewall and the second sidewall of each of the plurality of trenches that are formed in the respective semiconductor layer.

IPC Classes  ?

  • H01L 29/66 - Types of semiconductor device
  • H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
  • H01L 21/8234 - MIS technology
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

25.

Semiconductor Device Having a Layer Stack, Semiconductor Arrangement and Method for Producing the Same

      
Application Number 18397457
Status Pending
Filing Date 2023-12-27
First Publication Date 2024-04-18
Owner Infineon Technologies Austria AG (Austria)
Inventor
  • Frank, Paul
  • Heinelt, Thomas
  • Schilling, Oliver
  • Schmidbauer, Sven
  • Wagner, Frank

Abstract

A semiconductor device includes a semiconductor wafer or a single semiconductor chip or die, and a layer stack. The layer stack comprises a first layer comprising NiSi, and a second layer comprising NiV, wherein the second layer is arranged between the first layer and the semiconductor wafer or single semiconductor chip or die.

IPC Classes  ?

  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices

26.

DEVICE FOR CONTROLLING TRAPPED IONS WITH INTEGRATED WAVEGUIDE

      
Application Number 18486273
Status Pending
Filing Date 2023-10-13
First Publication Date 2024-04-18
Owner
  • Infineon Technologies Austria AG. (Austria)
  • Joanneum Research Forschungsgesellschaft mbH (Austria)
  • Universität Innsbruck (Austria)
Inventor
  • Rössler, Clemens
  • Lamprecht, Bernhard
  • Monz, Thomas
  • Schindler, Philipp

Abstract

A micro-fabricated device for controlling trapped ions includes a first substrate having a main surface. A structured first metal layer is disposed over the main surface of the first substrate. The structured first metal layer includes electrodes of at least one ion trapping zone configured to trap an ion in a space above the structured first metal layer. A dielectric element is fixedly attached to the first substrate. The dielectric element includes at least one short-pulse-laser direct written (SPLDW) waveguide configured to direct laser light towards an ion trapped in the at least one ion trapping zone.

IPC Classes  ?

  • G21K 1/00 - Arrangements for handling particles or ionising radiation, e.g. focusing or moderating

27.

CURRENT MODE CONTROLLER AND CORRESPONDING METHOD OF OPERATION

      
Application Number 17961966
Status Pending
Filing Date 2022-10-07
First Publication Date 2024-04-18
Owner INFINEON TECHNOLOGIES AUSTRIA AG (Austria)
Inventor Neyra, Percy

Abstract

A current mode controller includes: an error amplifier configured to generate an error signal that corresponds to the difference between a reference voltage and a voltage indicative of an output voltage of a power converter; a first current measurement circuit configured to measure current flowing in a high-side switch device of the power converter; a second current measurement circuit configured to measure current flowing in a low-side switch device of the power converter; a comparator configured to indicate when a voltage derived by the first current measurement circuit exceeds the error signal in a peak current control mode, and when a voltage derived by the second current measurement circuit drops below the error signal in a valley current control mode; and circuitry configured to configure the comparator in either the peak current control mode or the valley current control mode for each switching cycle of the power converter.

IPC Classes  ?

  • H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
  • H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion

28.

TRANSFORMER-BASED DRIVE FOR GAN DEVICES

      
Application Number 17967431
Status Pending
Filing Date 2022-10-17
First Publication Date 2024-04-18
Owner Infineon Technologies Austria AG (Austria)
Inventor
  • Bernardon, Derek
  • Ferianz, Thomas
  • Leong, Kennith Kin

Abstract

A power stage includes: a first transformer; a second transformer; a third transformer; a GaN (gallium nitride) enhancement mode power transistor configured to conduct a load current when driven by a gate current derived from energy transferred by the first transformer; a GaN depletion mode transistor configured to turn off the GaN enhancement mode power transistor absent a threshold voltage applied across a gate and a source of the GaN depletion mode transistor; a voltage clamping device or circuit configured to turn off the GaN depletion mode transistor when reverse biased by a bias current derived from energy transferred by the second transformer; and a GaN enhancement mode transistor configured to turn on the GaN depletion mode transistor when driven by a gate current derived from energy transferred by the third transformer.

IPC Classes  ?

  • H03K 17/16 - Modifications for eliminating interference voltages or currents
  • H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
  • H02M 7/06 - Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes without control electrode or semiconductor devices without control electrode

29.

SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING A CAVITY IN A TRENCH

      
Application Number 18480195
Status Pending
Filing Date 2023-10-03
First Publication Date 2024-04-18
Owner Infineon Technologies Austria AG (Austria)
Inventor
  • Hutzler, Michael
  • Breymesser, Alexander
  • Juhasz, Laszlo

Abstract

In an embodiment, a semiconductor device is provided that includes a semiconductor substrate having a first major surface, one or more trenches formed in the first major surface and having a base and a side wall extending from the base to the first major surface, an anchoring layer, and a conductive member arranged in the one or more trenches and spaced apart from the side wall of the one or more trenches by a cavity formed in the one or more trenches . The anchoring layer extends from the first major surface of the semiconductor substrate over the cavity and onto an upper surface of the conductive member.

IPC Classes  ?

30.

GATE DRIVER

      
Application Number 17960363
Status Pending
Filing Date 2022-10-05
First Publication Date 2024-04-11
Owner Infineon Technologies Austria AG (Austria)
Inventor
  • Locatelli, Christian
  • Raffo, Diego
  • Chen, Zhou Jonah
  • Chu, Weidong

Abstract

A gate driver comprises an input terminal, an output terminal, and first logic configured to generate an output drive signal at the output terminal corresponding to an input drive signal received at the input terminal. A blanking unit is configured to connect a current sense terminal of the gate driver to a reference supply terminal responsive to a low value of the output drive signal and disconnect the current sense terminal from the reference supply terminal after a predetermined delay period responsive to a high value of the output drive signal.

IPC Classes  ?

  • H03K 17/16 - Modifications for eliminating interference voltages or currents

31.

BIDIRECTIONAL POWER SWITCH

      
Application Number 17961216
Status Pending
Filing Date 2022-10-06
First Publication Date 2024-04-11
Owner Infineon Technologies Austria AG (Austria)
Inventor
  • Leong, Kennith Kin
  • Aichriedler, Leo
  • Kim, Kyoung Seop

Abstract

A unidirectional power switch includes: a normally-on switch device having a normally-on gate, a source, and a drain; a normally-off switch device having a normally-off gate, a source, and a drain, the drain of the normally-off switch device being electrically connected to the source of the normally-on switch device in a cascode configuration; a first source terminal electrically connected to the source of the normally-off switch device; a second source terminal electrically connected to the source of the normally-on switch device; and a drain terminal electrically connected to the drain of the normally-on switch device. The unidirectional power switch is configurable as either a normally-off unidirectional switch or a normally-on unidirectional switch, depending on a configuration of external gate driver connections to the source terminals. Additional power switch embodiments and related methods of configuring the power switches are described, including a configurable bidirectional power switch.

IPC Classes  ?

  • H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors

32.

GATE CHARGE AND LEAKAGE MEASUREMENT TEST SEQUENCE FOR SOLID STATE DEVICES

      
Application Number 17961101
Status Pending
Filing Date 2022-10-06
First Publication Date 2024-04-11
Owner Infineon Technologies Austria AG (Austria)
Inventor
  • Aichriedler, Leo
  • Wriessnegger, Gerald

Abstract

An apparatus comprises a switch and a capacitor connected to the switch and to a gate driver that drives a gate of a solid state device. The gate driver is operated to perform a test sequence for the solid state device. The test sequence includes turning on a switch and charging a capacitor to a supply voltage during an initial phase. During a first phase, the switch and the solid state device are turned off, the gate driver is disconnected from the supply voltage, and the gate driver drives the gate of the solid state device based at least upon a charge of the capacitor. During a second phase, the gate driver drives the gate of the solid state device to turn on the solid state device. A gate charge at the gate of the solid state device is measured as an operational state of the solid state device.

IPC Classes  ?

33.

WAFER COMPOSITE, SEMICONDUCTOR DEVICE AND METHODS OF MANUFACTURING A SEMICONDUCTOR CIRCUIT

      
Application Number 18471698
Status Pending
Filing Date 2023-09-21
First Publication Date 2024-04-04
Owner Infineon Technologies Austria AG (Germany)
Inventor
  • Gruber, Hermann
  • Busch, Jörg
  • Debie, Derek
  • Fischer, Thomas
  • Porwol, Danie
  • Schmidt, Matthias

Abstract

A layer stack is formed that includes a device layer and an insulator layer. The device layer includes electronic elements. The insulator layer is adjacent to a back surface of the device layer. A spacer disk is adhesive bonded on the layer stack on a side opposite the device layer. The spacer disk and the layer stack form a wafer composite. The wafer composite is divided into a plurality of individual semiconductor chips. Each semiconductor chip includes a portion of the layer stack and a portion of the spacer disk.

IPC Classes  ?

  • H01L 21/784 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, each consisting of a single circuit element the substrate being a semiconductor body
  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 23/29 - Encapsulation, e.g. encapsulating layers, coatings characterised by the material
  • H01L 23/49 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of soldered or bonded constructions wire-like

34.

GATE DRIVER CIRCUIT AND POWER SWITCHING ASSEMBLY WITH GATE DRIVER CIRCUIT

      
Application Number 18474744
Status Pending
Filing Date 2023-09-26
First Publication Date 2024-04-04
Owner Infineon Technologies Austria AG (Austria)
Inventor
  • Mauder, Anton
  • Grasso, Massimo
  • Fürgut, Edward

Abstract

A power switching assembly includes a first driver circuit and a second driver circuit. The first driver circuit is supplied via a first internal supply node and a first reference node and drives a first gate signal. The second driver circuit is supplied via a second internal supply node and a second reference node and drives a second gate signal. The first gate signal and the second gate signal are configured to be in phase with each other. The first reference node and the second reference node are separated. A first buffer capacitor is electrically connected between the first internal supply node and the first reference node. A second buffer capacitor electrically connected between the second internal supply node and the second reference node.

IPC Classes  ?

  • H03K 17/06 - Modifications for ensuring a fully conducting state
  • H03K 17/082 - Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit
  • H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors

35.

POWER SUPPLY AND SETPOINT VOLTAGE GENERATION

      
Application Number 17954569
Status Pending
Filing Date 2022-09-28
First Publication Date 2024-04-04
Owner Infineon Technologies Austria AG (Austria)
Inventor
  • Sen, Sujata
  • Petruzzi, Luca
  • Srivastava, Aviral

Abstract

Digital-to-analog converter circuitry comprising a sequence of multiple current drive modules. The sequence may include a first current drive module and a second current drive module of a digital-to-analog converter. The first current drive module is switchable between: i) a first mode of producing a first reference current that is mirrored by a second current drive module coupled to the first current drive module; and ii) a second mode of mirroring a second reference current that is produced by the second current drive module or a third current drive module coupled to the first current drive module.

IPC Classes  ?

  • H03M 1/06 - Continuously compensating for, or preventing, undesired influence of physical parameters

36.

Voltage regulator module and method of operating the same

      
Application Number 18373501
Status Pending
Filing Date 2023-09-27
First Publication Date 2024-04-04
Owner Infineon Technologies Austria AG (Austria)
Inventor Domingo, Reynaldo

Abstract

A voltage regulator module may comprise a control signal generation module, a power stage, and a routing network. The control signal generation module may be configured to, in a first mode of operation, generate an internal control signal for controlling the power stage. The routing network may be configured to, in the first mode of operation, apply the internal control signal to a control node of the power stage. The routing network may be configured to, in a second mode of operation, electrically connect said control node to an input pin of the voltage regulator module such that the power stage is controllable by an external control signal applied to said input pin. Thus, in the second mode of operation, it becomes possible to control the power stage directly via the external control signal and use this power stage e.g. as a single phase of a multi-phase power converter.

IPC Classes  ?

  • H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion
  • H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
  • H02M 3/156 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators

37.

Semiconductor Device Comprising a Leadframe Adapted for Higher Current Output or Improved Placement of Additional Devices

      
Application Number 18374379
Status Pending
Filing Date 2023-09-28
First Publication Date 2024-04-04
Owner Infineon Technologies Austria AG (Austria)
Inventor
  • Schwab, Stefan
  • Treu, Julian

Abstract

A semiconductor device comprises a leadframe comprising a die pad and a plurality of leads, a semiconductor die disposed on the die pad, the semiconductor die including a contact pad on a first main face thereof, and one or more bond wires connected with the contact pad, wherein a lead of the plurality of leads is bent back and connected with at least one first bond wire of the one or more bond wires.

IPC Classes  ?

  • H01L 23/495 - Lead-frames
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,

38.

TRENCH GATE NMOS TRANSISTOR AND TRENCH GATE PMOS TRANSISTOR MONOLITHICALLY INTEGRATED IN SAME SEMICONDUCTOR DIE

      
Application Number 17957035
Status Pending
Filing Date 2022-09-30
First Publication Date 2024-04-04
Owner Infineon Technologies Austria AG (Austria)
Inventor
  • Naik, Harsh
  • Henson, Timothy
  • He, Honghai
  • Haase, Robert
  • Mirchandani, Ashita
  • Mojab, Alireza

Abstract

A semiconductor die includes: a silicon substrate; a trench gate NMOS transistor formed in a first device region of the silicon substrate; a trench gate PMOS transistor formed in a second device region of the silicon substrate and electrically connected to the trench gate NMOS transistor; and an isolation structure interposed between the first device region and the second device region. Methods of monolithically integrating the trench gate NMOS transistor and the trench gate PMOS transistor in the same semiconductor die are also described.

IPC Classes  ?

  • H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
  • H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
  • H01L 21/266 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation using masks
  • H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
  • H01L 29/40 - Electrodes
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H02M 1/088 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices

39.

SEMICONDUCTOR DEVICE AND METHOD

      
Application Number 18466432
Status Pending
Filing Date 2023-09-13
First Publication Date 2024-03-28
Owner Infineon Technologies Austria AG (Austria)
Inventor
  • Siemieniec, Thomas Ralf
  • Blank, Oliver

Abstract

A semiconductor device includes a semiconductor substrate having a major surface, a trench extending from the major surface into the substrate and having a base and a side wall extending form the base to the major surface, and a field plate arranged in the trench and having a height f. The field plate is electrically insulated from the substrate by a dielectric structure arranged in the trench. The dielectric structure includes a first portion having a first dielectric constant and a second portion having a second dielectric constant higher than the first dielectric constant. The first portion is arranged in a lower portion of the trench. The second portion is arranged in an upper portion of the trench, a thickness x, and overlaps the height of the field plate by a distance v1, where f*0.1≤v1≤f*0.8 or f*0.3≤v1≤f*0.6.

IPC Classes  ?

  • H01L 29/40 - Electrodes
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

40.

CIRCUIT AND CONNECTOR ELEMENT ALIGNMENT, CIRCUIT BOARD ASSEMBLIES

      
Application Number 17952895
Status Pending
Filing Date 2022-09-26
First Publication Date 2024-03-28
Owner Infineon Technologies Austria AG (Austria)
Inventor
  • Cho, Eung San
  • Clavette, Danny

Abstract

This disclosure includes multiple assemblies, sub-assemblies, etc., as well as one or more methods of fabricating same. For example, a first assembly includes a first circuit board. The first circuit board further includes first connector elements disposed on a first edge of the first circuit board and second connector elements disposed on a second edge of the first circuit board. The first edge may be disposed substantially opposite the second edge on the first circuit board. The apparatus may further include first circuitry affixed to the first circuit board. The first edge of the first circuit board aligns with a first axial end of the first circuitry and the second edge of the first circuit board aligns with a second axial end of the first circuitry. The first assembly is used to fabricate a second assembly.

IPC Classes  ?

  • H05K 1/18 - Printed circuits structurally associated with non-printed electric components
  • H02M 3/00 - Conversion of dc power input into dc power output
  • H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
  • H05K 1/14 - Structural association of two or more printed circuits
  • H05K 3/00 - Apparatus or processes for manufacturing printed circuits
  • H05K 3/30 - Assembling printed circuits with electric components, e.g. with resistor
  • H05K 3/36 - Assembling printed circuits with other printed circuits

41.

POWER SUPPLY AND CALIBRATION

      
Application Number 17954617
Status Pending
Filing Date 2022-09-28
First Publication Date 2024-03-28
Owner Infineon Technologies Austria AG (Austria)
Inventor
  • Sen, Sujata
  • Petruzzi, Luca
  • Srivastava, Aviral

Abstract

An apparatus includes a calibration circuit operative to produce an error signal indicative of an error associated with a current generator circuit generating a secondary current from a reference current. The secondary current is proportional to the reference current. The calibration circuit derives an adjustment value from the error signal and applies the adjustment value to the current generator circuit. Application of the adjustment value reduces a magnitude of the error signal.

IPC Classes  ?

  • G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
  • G05F 1/46 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc
  • G05F 3/26 - Current mirrors

42.

ION MOVEMENT CONTROL SYSTEM WITH LOW PASS FILTER IN ANALOG SWITCH

      
Application Number 17954699
Status Pending
Filing Date 2022-09-28
First Publication Date 2024-03-28
Owner Infineon Technologies Austria AG (Austria)
Inventor Brandl, Matthias

Abstract

An ion movement control apparatus with low pass filter switch , including a digital to analog converter (DAC) connected to a first port and enabled to provide a DAC voltage, an electrode element connected to a second port, the electrode element configured to provide an electrical field for controlling a position of an ion, and a filter switch between the first port and the second port and having a filter leg and a bypass leg in parallel, the filter leg having a filter leg switch and a filter portion between the first port and the second port and selectively coupling the first port through the filter leg to the second port to slow a voltage transient of the DAC voltage to the electrode element, and where the bypass leg has a bypass leg switch that selectively couples the first port directly to the second port.

IPC Classes  ?

  • G21K 1/00 - Arrangements for handling particles or ionising radiation, e.g. focusing or moderating
  • H03M 1/74 - Simultaneous conversion

43.

INTERLOCKED CIRCUIT BOARD ELEMENTS AND ASSEMBLIES

      
Application Number 17952859
Status Pending
Filing Date 2022-09-26
First Publication Date 2024-03-28
Owner Infineon Technologies Austria AG (Austria)
Inventor
  • Galipeau, Darryl
  • Clavette, Danny
  • Tschirhart, Darryl

Abstract

A circuit board assembly may include a first circuit board including a first slot. The circuit board assembly may include a second circuit board. The first circuit board may be interlocked with the second circuit board via interlocking provided by the second circuit board into the first slot.

IPC Classes  ?

  • H05K 1/14 - Structural association of two or more printed circuits
  • H02M 3/00 - Conversion of dc power input into dc power output
  • H05K 1/18 - Printed circuits structurally associated with non-printed electric components
  • H05K 3/36 - Assembling printed circuits with other printed circuits

44.

POWER SUPPLIES AND IMPROVED SIGNAL ADJUSTMENT

      
Application Number 17954589
Status Pending
Filing Date 2022-09-28
First Publication Date 2024-03-28
Owner Infineon Technologies Austria AG (USA)
Inventor
  • Srivastava, Aviral
  • Petruzzi, Luca
  • Tang, Benjamim

Abstract

A signal adjustor receives a first signal such as feedback associated with generation of an output voltage. The output voltage is regulated based on a selected setpoint reference voltage. The signal adjustor maps a magnitude of the selected setpoint reference voltage to a first set of signal adjustment information amongst multiple sets of signal adjustment information. The signal adjustor then applies the first signal adjustment information to the first signal to produce a second signal.

IPC Classes  ?

  • G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
  • G05F 1/46 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc

45.

Method for Fabricating a Power Semiconductor Device

      
Application Number 18522991
Status Pending
Filing Date 2023-11-29
First Publication Date 2024-03-21
Owner Infineon Technologies Austria AG (Austria)
Inventor
  • Otremba, Ralf
  • Langer, Gregor
  • Frank, Paul
  • Heinrich, Alexander
  • Ludsteck-Pechloff, Alexandra
  • Pedone, Daniel

Abstract

A method for fabricating a SiC power semiconductor device includes: providing a SiC power semiconductor die; depositing a metallization layer over the power semiconductor die, the metallization layer including a first metal; arranging the power semiconductor die over a die carrier such that the metallization layer faces the die carrier, the die carrier being at least partially covered by a plating that includes Ni; and diffusion soldering the power semiconductor die to the die carrier such that a first intermetallic compound is formed between the power semiconductor die and the plating, the first intermetallic compound including Ni3Sn4.

IPC Classes  ?

  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 23/495 - Lead-frames
  • H01L 23/498 - Leads on insulating substrates

46.

GATE DRIVER SYSTEM FOR DETECTING A SHORT CIRCUIT CONDITION

      
Application Number 17933615
Status Pending
Filing Date 2022-09-20
First Publication Date 2024-03-21
Owner Infineon Technologies Austria AG (Austria)
Inventor
  • Qiu, Yuqiang
  • Tian, Bin

Abstract

A driver system includes a first half-bridge that generates a first load current at a first output node, a second half-bridge that generates a second load current at a second output node, a first voltage charging device coupled to the first output node, and a second voltage charging device coupled to the second output node. A method of detecting a short circuit condition in the driver system includes detecting a first charging time at which a first charging voltage of the first voltage charging device is charged to a first threshold voltage; detecting a second charging time at which a second charging voltage of the second voltage charging device is charged to a second threshold voltage; and detecting the short circuit condition on a condition that a time difference between the first charging time and the second charging time is less than a time difference threshold.

IPC Classes  ?

  • H03K 17/081 - Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
  • H02J 7/00 - Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
  • H02M 7/5387 - Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
  • H02P 27/08 - Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using dc to ac converters or inverters with pulse width modulation

47.

SEMICONDUCTOR DEVICE

      
Application Number 18458627
Status Pending
Filing Date 2023-08-30
First Publication Date 2024-03-14
Owner Infineon Technologies Austria AG (Austria)
Inventor
  • Kim, Hyeongnam
  • Imam, Mohamed

Abstract

In an embodiment, a semiconductor device includes: a main bi-directional switch formed on a semiconductor substrate and including first and second gates, a first source electrically connected to a first voltage terminal, a second source electrically connected to a second voltage terminal, and a common drain; and a substrate control circuit. The substrate control circuit includes: a first diode and a second diode; a discharge circuit including a first transistor and a second transistor connected in a common source configuration to the semiconductor substrate; and a gate potential control circuit including a third diode and a fourth diode. The first diode has a forward voltage Vf1 and the third diode has a forward voltage Vf3, where Vf1≥1.1Vf4 or Vf1≥1.2Vf4 or Vf1≥1.5Vf4 or Vf1≥2Vf4.

IPC Classes  ?

  • H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
  • H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
  • H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
  • H01L 29/872 - Schottky diodes
  • H03K 17/56 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices

48.

DIODE INCLUDING A TRENCH ELECTRODE SUBDIVIDED INTO AT LEAST FIRST AND SECOND PARTS

      
Application Number 18510906
Status Pending
Filing Date 2023-11-16
First Publication Date 2024-03-14
Owner Infineon Technologies Austria AG (Austria)
Inventor
  • Sandow, Christian Philipp
  • Dainese, Matteo
  • Lapidus, Viktoryia

Abstract

A diode is proposed. The diode includes: a semiconductor body having opposing first and second main surfaces; an anode region and a cathode region, the anode region being arranged between the first main surface and the cathode region; an anode pad area electrically connected to the anode region; and trenches extending into semiconductor body from the first main surface. A first group of the trenches includes a first trench electrode. The first trench electrode is subdivided into at least a first part and a second part. A conductance per unit length of the first part along a longitudinal direction of the first trench electrode is by at least a factor of 1000 smaller than a conductance per unit length of the second part along the longitudinal direction of the first trench electrode. The second part is electrically coupled to the anode pad area via the first part.

IPC Classes  ?

  • H01L 29/861 - Diodes
  • H01L 27/07 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common

49.

POWER SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAME

      
Application Number 18453639
Status Pending
Filing Date 2023-08-22
First Publication Date 2024-03-14
Owner INFINEON TECHNOLOGIES AUSTRIA AG (Austria)
Inventor
  • Otremba, Ralf
  • Gan, Thai Kee
  • Lee, Teck Sim
  • Tommy Khoo, Chwee Pang
  • Schiele, Christian
  • Unterhofer, Katrin
  • Uredat, Patrick

Abstract

A power semiconductor package includes: a die carrier having first and second opposite sides; and first and second power semiconductor dies each having first and second power electrodes on opposite sides. The second power electrodes face and are electrically coupled to the first side of the carrier. A molded body at least partially encapsulates the dies and has a first and second opposite sides and lateral sides connecting the first and second sides. First and second power contacts and first and second control contacts are arranged laterally next to each other. The first power electrode of the first die is electrically coupled to the first power contact by a first electrical connector. The first power electrode of the second die is electrically coupled to the second power contact by a second electrical connector. A width of each power contact is at least four times the width of each control contact.

IPC Classes  ?

  • H01L 23/495 - Lead-frames
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices
  • H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,

50.

Semiconductor Package with Balanced Impedance

      
Application Number 17903512
Status Pending
Filing Date 2022-09-06
First Publication Date 2024-03-07
Owner INFINEON TECHNOLOGIES AUSTRIA AG (Austria)
Inventor
  • Luniewski, Peter
  • Neubert, Markus
  • Fuegl, Michael
  • Jakobi, Waldemar
  • Leipenat, Michael
  • Lamminger, Egbert

Abstract

A semiconductor package includes a substrate including a die pad, first and second discrete transistor dies mounted on the die pad, an encapsulant body that encapsulates the first and second discrete transistor dies, and a plurality of leads that are exposed from the encapsulant body, wherein the first and second discrete transistor dies are connected in parallel with one another by electrical interconnections that electrically connect common terminals of the first and second discrete transistor dies to one of the leads, and wherein at least one of the electrical interconnections has a balanced configuration that provides substantially identical electrical impedance as between the common terminals of the first and second discrete transistor dies and the lead to which they are connected.

IPC Classes  ?

  • H01L 23/495 - Lead-frames
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement

51.

VERTICAL JUNCTION FIELD EFFECT TRANSISTOR INCLUDING A PLURALITY OF MESA REGIONS

      
Application Number 18450078
Status Pending
Filing Date 2023-08-15
First Publication Date 2024-03-07
Owner Infineon Technologies Austria AG (Austria)
Inventor
  • Weber, Hans
  • Fischer, Björn

Abstract

A vertical junction field effect transistor includes mesa regions and trench structures extending along a first lateral direction in a semiconductor body and arranged alternately along a second lateral direction. The trench structures include a gate contact material electrically connected to a gate region of a first conductivity type in the semiconductor body. A width of the trench structures satisfies one or more of the following conditions: i) the width of at least one trench structure arranged outermost along the second lateral direction is smaller than in a more central part of the trench structures; or ii) the width of at least some trench structures is smaller along an end part in the first lateral direction than in the more central part, an extent of the end part along the first lateral direction being larger than a pitch between neighboring trench structures along the second lateral direction.

IPC Classes  ?

  • H01L 29/808 - Field-effect transistors with field effect produced by a PN or other rectifying junction gate with a PN junction gate
  • H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

52.

MULTI-FUNCTION CONTROL CIRCUIT AND PRE-CIRCUIT CONFIGURATION

      
Application Number 17903510
Status Pending
Filing Date 2022-09-06
First Publication Date 2024-03-07
Owner Infineon Technologies Austria AG (Austria)
Inventor
  • Rigoni, Fabio
  • Bernacchia, Giuseppe

Abstract

An apparatus may include an input pin\ and timing control circuitry coupled to the input pin. The timing control circuitry selectively executes one or more timing control functions based on a set of one or more hardware components coupled to the input pin. The set of one or more hardware components are disposed external to the apparatus. A configuration of the set of one or more hardware components determines which of one or more of the multiple timing control functions are enabled.

IPC Classes  ?

  • H02H 9/02 - Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess current
  • H02H 3/093 - Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition, with or without subsequent reconnection responsive to excess current with timing means
  • H03K 17/16 - Modifications for eliminating interference voltages or currents
  • H03K 17/284 - Modifications for introducing a time delay before switching in field-effect transistor switches

53.

Gate driver circuit with a limiting function to maintain control voltage under a rated limit

      
Application Number 17933163
Grant Number 11923832
Status In Force
Filing Date 2022-09-19
First Publication Date 2024-03-05
Grant Date 2024-03-05
Owner Infineon Technologies Austria AG (Austria)
Inventor
  • Xu, Kuiwei
  • Cao, Weiwei

Abstract

A gate driver system includes a transistor configured to be driven between switching states, the transistor including a control terminal controlled by a control voltage that has a maximum rated limit; and a gate driver coupled to the control terminal by a turn-on current path, the gate driver being configured to control the control voltage in order to drive the transistor between the switching states. The turn-on current path includes a resistor and a Zener diode connected in series, with an anode of the Zener diode connected to the control terminal and a cathode of the Zener diode connected to the resistor. The turn-on current path is configured to provide an on-current to increase the control voltage above a switching threshold. While the transistor is turned on, the Zener diode is configured to limit the control voltage to a voltage level limit that is less than the maximum rated limit.

IPC Classes  ?

  • H03K 3/00 - Circuits for generating electric pulses; Monostable, bistable or multistable circuits
  • H03K 17/00 - Electronic switching or gating, i.e. not by contact-making and -breaking
  • H03K 17/06 - Modifications for ensuring a fully conducting state
  • H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
  • H03K 17/693 - Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors

54.

ELECTRONIC CIRCUIT WITH A TRANSISTOR DEVICE AND A CLAMP CIRCUIT AND METHOD

      
Application Number 18446610
Status Pending
Filing Date 2023-08-09
First Publication Date 2024-02-29
Owner Infineon Technologies Austria AG (Austria)
Inventor
  • Finney, Adrian
  • Blank, Oliver
  • Prechtl, Gerhard
  • Ahlers, Dirk
  • Nöbauer, Gerhard
  • Bodea, Marius Aurel
  • Schönle, Joachim
  • Häberlen, Oliver

Abstract

An electronic circuit and a method are disclosed. The electronic circuit includes: a first transistor device having a load path between a first load path node and a second load path node; and a clamping circuit connected to the load path of the first transistor device. The clamping circuit includes: a second transistor device having a load path connected in parallel with the load path of the first transistor device, and a control node; and a drive circuit configured to drive the second transistor device. The drive circuit includes a clamping element and a resistor connected in series between the first and second load path nodes of the first transistor device. The drive circuit is configured to drive the second transistor device dependent on a voltage across the resistor. The first transistor device and the clamping circuit are integrated in a same semiconductor die.

IPC Classes  ?

  • H03K 17/06 - Modifications for ensuring a fully conducting state
  • H03K 17/081 - Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
  • H03K 17/10 - Modifications for increasing the maximum permissible switched voltage

55.

ISOLATED POWER CONVERTER HAVING A VOLTAGE SUPPLY CIRCUIT

      
Application Number 17893449
Status Pending
Filing Date 2022-08-23
First Publication Date 2024-02-29
Owner Infineon Technologies Austria AG (Austria)
Inventor
  • Saliva, Allan
  • Domingo, Roderick

Abstract

An isolated power converter includes: a transformer having primary winding and first and second auxiliary windings on the primary side; a converter stage configured to convert a DC input for driving the primary winding and having a resonant capacitor electrically connected to the primary winding; a controller configured to control switching of the converter stage; and a voltage supply circuit configured to select a first voltage as a supply voltage for the controller if a voltage proportional to a secondary side voltage of the transformer is at a first level or select a second voltage as the supply voltage if the voltage proportional to the secondary side voltage is at a second level greater than the first level. The first voltage corresponds to a summation of voltages across the first auxiliary winding and the resonant capacitor. The second voltage corresponds to a voltage across the second auxiliary winding.

IPC Classes  ?

  • H02M 3/335 - Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
  • H02M 3/00 - Conversion of dc power input into dc power output

56.

SILICON-ON-INSULATOR (SOI) DEVICE HAVING VARIABLE THICKNESS DEVICE LAYER AND CORRESPONDING METHOD OF PRODUCTION

      
Application Number 17898836
Status Pending
Filing Date 2022-08-30
First Publication Date 2024-02-29
Owner INFINEON TECHNOLOGIES AUSTRIA AG (Austria)
Inventor
  • Chandrika Reghunathan, Manoj
  • Datta, Devesh Kumar
  • Graetz, Eric Alois
  • Hasanudin, Muhammad Akmal
  • Ramadass, Vijay Anand

Abstract

A method of producing power semiconductor devices from a silicon-on-insulator (SOI) wafer is described. The SOI wafer includes a silicon device layer, a bulk silicon wafer, and a buried oxide layer separating the silicon device layer from the bulk silicon wafer. The method includes: forming a hard mask on the silicon device layer, wherein the hard mask covers one or more first regions of the silicon device layer and exposes one or more second regions of the silicon device layer; and before forming any field oxide structures and before implanting any device regions, selectively growing epitaxial silicon on the one or more second regions of the silicon device layer exposed by the hard mask such that the thickness of the one or more second regions is increased relative to the one or more first regions. Various devices produced according to the method are also described.

IPC Classes  ?

  • H01L 29/66 - Types of semiconductor device
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 29/80 - Field-effect transistors with field effect produced by a PN or other rectifying junction gate

57.

TRANSISTOR DEVICE

      
Application Number 18487255
Status Pending
Filing Date 2023-10-16
First Publication Date 2024-02-22
Owner Infineon Technologies Austria AG (Austria)
Inventor Hutzler, Michael

Abstract

In an embodiment, a transistor device includes: a support layer having a first major surface and a second major surface opposing the first major surface; a source contact arranged on the first major surface of the support layer; a drain contact arranged on the second major surface of the support layer; and a gate electrode arranged in a first trench formed in the first major surface of the support layer. The first trench has a base and a side wall extending from the base to the first major surface. The drain contact is arranged under the base of the first trench. A region with gate-controlled conductivity is formed between the source contact and the drain contact. The region with gate-controlled conductivity is formed in an organic semiconductor layer.

IPC Classes  ?

  • H10K 10/46 - Field-effect transistors, e.g. organic thin-film transistors [OTFT]
  • H10K 10/82 - Electrodes

58.

Semiconductor Device and Method of Manufacturing the Same

      
Application Number 18226321
Status Pending
Filing Date 2023-07-26
First Publication Date 2024-02-15
Owner Infineon Technologies Austria AG (Austria)
Inventor
  • Ferrara, Alessandro
  • Nöbauer, Gerhard Thomas

Abstract

The present application relates to a semiconductor device, including: a field electrode in a needle-shaped field electrode trench extending from a frontside of a semiconductor body into the semiconductor body; a lower metallization layer on the frontside of the semiconductor body and electrically connected to the field electrode; an insulating layer on the lower metallization layer; an upper metallization layer on the insulating layer, and a first interconnect electrically connecting the lower metallization layer to the upper metallization layer. The first interconnect is laterally offset to the field electrode trench. The lower metallization layer is not connected to the upper metallization layer in a region vertically above the field electrode trench.

IPC Classes  ?

  • H01L 29/40 - Electrodes
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device

59.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE

      
Application Number 18225472
Status Pending
Filing Date 2023-07-24
First Publication Date 2024-02-08
Owner Infineon Technologies Austria AG (Austria)
Inventor
  • Labrenz, Norbert
  • Karmous, Alim

Abstract

A semiconductor device is provided. The semiconductor device includes a substrate, an isolation region that is formed at a main surface of the substrate, and a recess in the isolation region. The semiconductor device further includes an active or passive device that is formed in the recess. The active or passive device includes a first semiconductor material region and a second semiconductor material region. The first semiconductor material region adjoins at least part of the second semiconductor material region in a first direction parallel to the main surface of the substrate. An upper surface of the first semiconductor material region is above an upper surface of the second semiconductor material region. The upper surface of the second semiconductor material region is below the main surface of the substrate.

IPC Classes  ?

  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 21/321 - After-treatment
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
  • H01L 21/762 - Dielectric regions

60.

Method of Forming a Semiconductor Module

      
Application Number 18381929
Status Pending
Filing Date 2023-10-19
First Publication Date 2024-02-08
Owner Infineon Technologies Austria AG (Austria)
Inventor
  • Kessler, Angela
  • Hoeglauer, Josef
  • Noebauer, Gerhard

Abstract

A method of forming a semiconductor module comprises forming a laminate structure having an electrically insulating core layer with opposing first and second sides, a first redistribution layer arranged on the first side and a second redistribution layer arranged on the second side. First and second transistor devices are coupled to form a half-bridge circuit. Bots transistor devices have a first side at which a cell field is arranged and an opposing second side. A control chip has a first side with contact pads. The transistor devices and control chip are arranged laterally adjacent one another and embedded in the core layer. The first side of the control chip and one transistor device and the second side of the other transistor device face towards the first redistribution layer on the first side of the core layer.

IPC Classes  ?

  • H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
  • H01L 23/498 - Leads on insulating substrates
  • H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices

61.

TRANSISTOR DEVICE HAVING A FIELD PLATE

      
Application Number 18487505
Status Pending
Filing Date 2023-10-16
First Publication Date 2024-02-08
Owner Infineon Technologies Austria AG (Austria)
Inventor
  • Tegen, Stefan
  • Kroenke, Matthias

Abstract

A transistor device includes a semiconductor substrate having a first major surface, a cell field and an edge termination region laterally surrounding the cell field. The cell field includes: elongate active trenches that extend from the first major surface into the semiconductor substrate, a field plate and a gate electrode being positioned in each elongate active trench, the gate electrode being arranged above and electrically insulated from the field plate; and elongate mesas, each elongate mesa being formed between neighbouring elongate active trenches, the elongate mesas comprising a drift region, a body region on the drift region and a source region on the body region.

IPC Classes  ?

  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 29/40 - Electrodes
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect

62.

GRAPHENE IN ELECTROMAGNETIC SYSTEMS

      
Application Number 17880031
Status Pending
Filing Date 2022-08-03
First Publication Date 2024-02-08
Owner Infineon Technologies Austria AG (Austria)
Inventor Granig, Wolfgang

Abstract

A transformer includes a winding configured to carry a current. The winding includes a conductor structure through which the current flows and a graphene layer arranged in direct contact with the conductor structure.

IPC Classes  ?

  • H01B 1/04 - Conductors or conductive bodies characterised by the conductive materials; Selection of materials as conductors mainly consisting of carbon-silicon compounds, carbon, or silicon
  • H01F 41/04 - Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils or magnets for manufacturing coils

63.

POWER SEMICONDUCTOR DEVICE HAVING COUNTER-DOPED REGIONS IN BOTH AN ACTIVE CELL REGION AND AN INACTIVE CELL REGION

      
Application Number 17882064
Status Pending
Filing Date 2022-08-05
First Publication Date 2024-02-08
Owner Infineon Technologies Austria AG (Austria)
Inventor
  • Haase, Robert
  • Amali, Adam
  • Henson, Timothy
  • Ma, Ling
  • Malani, Kishore Lakhmichand

Abstract

A power semiconductor device includes: trench gate structures in an active cell region of a semiconductor substrate and extending into an inactive cell region of the semiconductor substrate that adjoins the active cell region; an electrically insulating material covering the trench gate structures; first contact openings in the electrically insulating material between adjacent trench gate structures in the active cell region; second contact openings in the electrically insulating material vertically aligned with the trench gate structures in the inactive cell region; first counter-doped regions between the adjacent trench gate structures in the active cell region and vertically aligned with the first contact openings; second counter-doped regions underneath the trench gate structures in the inactive cell region and vertically aligned with the second contact openings; first contacts in the first contact openings; and second contacts in the second contact openings. Methods of producing the power semiconductor device are also described.

IPC Classes  ?

  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H01L 29/40 - Electrodes
  • H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
  • H01L 21/266 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation using masks
  • H01L 29/66 - Types of semiconductor device

64.

Semiconductor Device and Method for Fabricating a Semiconductor Device

      
Application Number 18378733
Status Pending
Filing Date 2023-10-11
First Publication Date 2024-02-01
Owner Infineon Technologies Austria AG (Austria)
Inventor Heinrich, Alexander

Abstract

A method for fabricating a semiconductor device includes providing a die with a metallization layer including a first metal with a high melting point; providing a die carrier including a second metal with a high melting point; providing a solder material including a third metal with a low melting point; providing a layer of a fourth metal with a high melting point on the semiconductor die or the die carrier; and soldering the semiconductor die to the die carrier and creating: a first intermetallic compound between the semiconductor die and the die carrier and including the first metal and the third metal; a second intermetallic compound between the first intermetallic compound and the die carrier and including the second metal and the third metal; and precipitates of a third intermetallic compound between the first intermetallic compound and the second intermetallic compound and including the third metal and the fourth metal.

IPC Classes  ?

  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices

65.

MULTI-PHASE POWER CONVERTER

      
Application Number 18221625
Status Pending
Filing Date 2023-07-13
First Publication Date 2024-02-01
Owner Infineon Technologies Austria AG (Austria)
Inventor
  • Meyer, Thorsten
  • Kessler, Agnela
  • Scharf, Thorsten

Abstract

The present document relates to multi-phase power converters. In particular, the present document relates to a multi-phase power converter comprising a first phase with a first power stage and a first inductor, a second phase with a second power stage and a second inductor, and a first substrate extending along a first substrate plane. The first power stage, the first inductor and the second inductor may be arranged above the first substrate. The second power stage may be arranged below the first substrate. By arranging the two power stages vertically shifted on different sides of the first substrate, it becomes possible to save space in the substrate plane and thus decrease the horizontal space required for a given number of phases of the multi-phase power converter

IPC Classes  ?

  • H02M 7/00 - Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
  • H05K 1/18 - Printed circuits structurally associated with non-printed electric components
  • H02M 1/084 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters using a control circuit common to several phases of a multi-phase system

66.

SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING A SEMICONDUCTOR PACKAGE FOR UPRIGHT MOUNTING

      
Application Number 18351170
Status Pending
Filing Date 2023-07-12
First Publication Date 2024-01-25
Owner Infineon Technologies Austria AG (Austria)
Inventor
  • Yuferev, Sergey
  • Höglauer, Josef
  • Nöbauer, Gerhard Thomas
  • Zhuang, Hao

Abstract

A semiconductor package includes low voltage and high voltage contact pads, an output contact pad, a half-bridge circuit, and first, second and third leads. The half bridge circuit includes first and second transistor devices coupled in series at an output node. Both transistor devices have a first major surface which extends substantially perpendicularly to the low voltage contact pad, the high voltage contact pad, and the output contact pad. Both transistor devices are arranged in a device portion of the package and are mounted on a first lead, the first lead providing the output contact pad and being arranged on a first side of the device portion. The second and third leads are arranged in a common plane on a second side of the device portion that opposes the first side. The second lead provides the low voltage pad and the third second lead provides the high voltage output pad.

IPC Classes  ?

  • H01L 23/495 - Lead-frames
  • H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
  • H01L 23/12 - Mountings, e.g. non-detachable insulating substrates

67.

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING A SEMICONDUCTOR DEVICE

      
Application Number 18352311
Status Pending
Filing Date 2023-07-14
First Publication Date 2024-01-25
Owner Infineon Technologies Austria AG (Austria)
Inventor
  • Prechtl, Gerhard
  • Häberlen, Oliver

Abstract

In an embodiment, a semiconductor device is provided that includes a Group III nitride transistor device and a Schottky barrier diode integrated in a Group III nitride body. A common drain/cathode finger is arranged on the Group III nitride body. Two or more source contacts are arranged on the Group III nitride body and spaced apart in a row, the row being spaced laterally apart from, and extending substantially parallel to, the common drain/cathode finger. A gate electrode structure and one or more Schottky metal contacts are arranged on the Group III nitride body. At least one Schottky metal contact is arranged between and spaced apart from neighbouring ones of the source contacts. The gate electrode structure includes a closed ring section for each source contact that laterally surrounds that source contact. Neighbouring closed ring sections are connected by a gate connection section.

IPC Classes  ?

  • H01L 27/07 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
  • H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
  • H01L 29/40 - Electrodes
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
  • H01L 29/872 - Schottky diodes
  • H01L 29/66 - Types of semiconductor device

68.

Gate charge profiler for power transistors

      
Application Number 17872125
Grant Number 11901888
Status In Force
Filing Date 2022-07-25
First Publication Date 2024-01-25
Grant Date 2024-02-13
Owner Infineon Technologies Austria AG (Austria)
Inventor
  • Chendake, Vedant Sadashiv
  • Bernacchia, Giuseppe
  • Yelamos Ruiz, Pablo

Abstract

A gate charge profiler for a power transistor may include a voltage comparator unit and a timer unit. An input signal may control a gate drive current input to a gate of the power transistor to control conduction between a drain and a source of the power transistor. The voltage comparator unit may be configured to compare an input voltage and a threshold voltage, and to output a comparison signal. The input voltage may be a drain-source voltage across the drain and the source of the power transistor or a gate-source voltage across the gate and the source of the power transistor. The timer unit may be configured to output a time value based on input of a transition of the input signal and input of the comparison signal.

IPC Classes  ?

  • H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
  • H03K 5/24 - Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude

69.

SEMICONDUCTOR DEVICE, BATTERY MANAGEMENT SYSTEM AND METHOD OF PRODUCING A SEMICONDUCTOR DEVICE

      
Application Number 18332330
Status Pending
Filing Date 2023-06-09
First Publication Date 2024-01-25
Owner Infineon Technologies Austria AG (Austria)
Inventor
  • Ranacher, Christian
  • Napetschnig, Evelyn
  • Ebner, Sandra
  • Pavier, Mark
  • Vitanov, Stanislav
  • Frank, Paul

Abstract

In an embodiment, a semiconductor device is provided that includes a semiconductor die having a front side, a rear side opposing the front side, and side faces, a first transistor device having a first source pad and a first gate pad on the front side, and a second transistor device having a second source pad and a second gate pad on the front side. The first and second transistor devices each have a drain that is electrically coupled to a common drain pad on the rear side of the semiconductor die. The drain pad has an upper surface and side faces and at least a central portion of the upper surface is covered by a first electrically insulating layer.

IPC Classes  ?

  • H01M 10/42 - Methods or arrangements for servicing or maintenance of secondary cells or secondary half-cells
  • H01L 23/29 - Encapsulation, e.g. encapsulating layers, coatings characterised by the material
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device

70.

SEMICONDUCTOR PACKAGE AND METHOD

      
Application Number 18351524
Status Pending
Filing Date 2023-07-13
First Publication Date 2024-01-25
Owner Infineon Technologies Austria AG (Austria)
Inventor
  • Irrgang, Christian
  • Behrens, Thomas
  • Heitzer, Ludwig
  • Hoglauer, Josef
  • Meyer, Thorsten
  • Scharf, Thorsten
  • Zudock, Frank

Abstract

In an embodiment, a semiconductor package includes a lower surface having a low voltage contact pad, a high voltage contact pad, an output contact pad, and at least one control contact pad. The semiconductor package further includes a half-bridge circuit including a first transistor device having a first major surface and a second transistor device having a first major surface, the first and second transistor devices being electrically coupled in series at an output node, and a control device that is electrically coupled to the first transistor device and the second transistor device. The first major surface of the first transistor device and of the second transistor device are arranged substantially perpendicularly to the lower surface of the semiconductor package.

IPC Classes  ?

  • H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different main groups of groups , or in a single subclass of , , e.g. forming hybrid circuits
  • H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices
  • H01L 23/495 - Lead-frames
  • H01L 23/498 - Leads on insulating substrates
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices

71.

SEMICONDUCTOR DIE WITH A TUNGSTEN RUNNER AND A GATE RUNNER

      
Application Number 17871260
Status Pending
Filing Date 2022-07-22
First Publication Date 2024-01-25
Owner INFINEON TECHNOLOGIES AUSTRIA AG (Austria)
Inventor
  • Neumann, Ingmar
  • Finney, Adrian
  • Bierbaumer, Pascal
  • Juhasz, Laszlo

Abstract

A semiconductor die includes: a semiconductor substrate having an active region and an edge termination region that separates the active region from an edge of the semiconductor substrate; a plurality of transistor cells formed in the active region; a structured power metallization above the semiconductor substrate and including a gate pad and a gate runner that extends from the gate pad along one or more but not all sides of the semiconductor die above the edge termination region, the gate runner electrically connecting the gate pad to gate electrodes of the transistor cells; and a tungsten runner that follows the gate runner and contacts an underside of the gate runner. The tungsten runner is present above the edge termination region along each side of the semiconductor die that is at least partly devoid of the gate runner. A Method of producing the semiconductor die is also described.

IPC Classes  ?

  • H01L 23/528 - Layout of the interconnection structure
  • H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
  • H01L 29/40 - Electrodes
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

72.

Ion shuttling system with compensation electrodes for ion trap

      
Application Number 17813809
Grant Number 11978619
Status In Force
Filing Date 2022-07-20
First Publication Date 2024-01-25
Grant Date 2024-05-07
Owner INFINEON TECHNOLOGIES AUSTRIA AG (Austria)
Inventor Brandl, Matthias

Abstract

An ion shuttling system includes a plurality of first electrodes connected to a system configured to selectively provide an ion movement control voltage to each electrode of the plurality of first electrodes, a voltage source configured to provide one or more compensation voltages, a plurality of compensation electrodes comprising a plurality of compensation electrode pairs, where each compensation electrode pair of the plurality of compensation electrode pairs is associated with one or more different first electrodes of the plurality of first electrodes, and a plurality of switches, where each switch of the plurality of switches is connected at a respective first node to a compensation electrode of the plurality of compensation electrodes and is configured to selectively connect the respective compensation electrode to the voltage source.

IPC Classes  ?

  • H01J 49/42 - Stability-of-path spectrometers, e.g. monopole, quadrupole, multipole, farvitrons

73.

THERMAL MANAGEMENT OF POWER STAGES FOR PASSIVE MOTOR BRAKING

      
Application Number 17863751
Status Pending
Filing Date 2022-07-13
First Publication Date 2024-01-18
Owner Infineon Technologies Austria AG (Austria)
Inventor Geike, Hannes Mathias

Abstract

A method of passively braking a motor to reduce a current motor speed includes generating at least one control signal to control a first load current generated by a first half bridge circuit and a second load current generated by a second half bridge circuit. During passive braking, the method includes synchronously driving a first high-side transistor and a second high-side transistor between their respective switching states at an alternating shorting frequency such that they are simultaneously in a same switching state, and synchronously driving a first low-side transistor and a second low-side transistor between their respective switching states at the alternating shorting frequency such that they are simultaneously in a same switching state, wherein the first high-side transistor and the second high-side transistor are driven in a complementary manner to the first low-side transistor and the second low-side transistor according to a predetermined duty cycle.

IPC Classes  ?

  • H02P 6/24 - Arrangements for stopping
  • H02P 6/12 - Monitoring commutation; Providing indication of commutation failure

74.

SEMICONDUCTOR DIE AND METHOD OF MANUFACTURING THE SAME

      
Application Number 18349536
Status Pending
Filing Date 2023-07-10
First Publication Date 2024-01-18
Owner Infineon Technologies Austria AG (Austria)
Inventor
  • Ferrara, Alessandro
  • Regenfeldner, Daniel
  • Siemieniec, Thomas Ralf

Abstract

A semiconductor die includes a semiconductor device and an edge termination structure laterally between the semiconductor device and a lateral edge of the die. The edge termination structure includes a first inner shield electrode region with a shield electrode in a trench extending into a semiconductor body, an outer shield electrode region with a shield electrode in a trench extending into the semiconductor body and disposed in a first lateral direction between the first inner shield electrode region and the lateral edge, and a well region formed in the semiconductor body adjacent the trench of the first inner shield electrode region. The shield electrode of the first inner shield electrode region is electrically connected to the well region to tap an electrical potential from the well region. The shield electrode of the outer shield electrode region is electrically connected to the shield electrode of the first inner shield electrode region.

IPC Classes  ?

  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/40 - Electrodes

75.

Semiconductor Package or a Printed Circuit Board, Both Modified to One or More of Reduce, Inverse or Utilize Magnetic Coupling Caused by the Load Current of a Semiconductor Transistor

      
Application Number 18217044
Status Pending
Filing Date 2023-06-30
First Publication Date 2024-01-11
Owner Infineon Technologies Austria AG (Austria)
Inventor
  • Fürgut, Edward
  • Scholz, Wolfgang
  • Baeumler, Christian
  • Basler, Thomas
  • Liu, Xing
  • Schmoelzer, Bernd

Abstract

A semiconductor package comprises a semiconductor transistor circuit comprising a semiconductor transistor die comprising die terminals, including a collector/drain, a source/emitter, a sense source/sense emitter, a gate, and a load path, a driver line connected with the gate, and a gate control loop in which the a sense source/sense emitter is connected with the driver line, a plurality of external contacts comprising at least one first external contact connected with the drain/collector, at least one second external contact connected with the source/emitter, a third external contact connected with the a sense source/sense emitter, and a fourth external contact connected with the gate, wherein the plurality of external contacts are arranged or configured to reduce or utilize the magnetic coupling induced by a load current flowing through the load path.

IPC Classes  ?

  • H01L 23/495 - Lead-frames
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H05K 1/02 - Printed circuits - Details

76.

System and method for pulsed gate control of a transistor

      
Application Number 17896183
Grant Number 11870428
Status In Force
Filing Date 2022-08-26
First Publication Date 2024-01-09
Grant Date 2024-01-09
Owner Infineon Technologies Austria AG (Austria)
Inventor
  • Cox, David Grant
  • Subotski, Aliaksandr
  • Ramirez Rivero, Jorge Arturo

Abstract

A method of controlling current through a transistor is provided. A voltage and current through the transistor are measured. A safe operating current for the voltage is determined. For each of a first sequence of current pulses, a voltage of a voltage pulse applied to a control node of the transistor using a feedback controller is adjusted until the current measured through the transistor is not greater than a first function of the safe operating current. For each of a second sequence of current pulses after the first sequence of current pulses, the voltage of the voltage pulse applied to the control node of the transistor using the feedback controller is adjusted until the current measured through the transistor is not greater than a second function of the safe operating current.

IPC Classes  ?

  • H03K 17/042 - Modifications for accelerating switching by feedback from the output circuit to the control circuit
  • H03K 17/082 - Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit
  • G01R 19/165 - Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values

77.

ASYMMETRIC HALF BRIDGE FLYBACK CONVERTER

      
Application Number 18209779
Status Pending
Filing Date 2023-06-14
First Publication Date 2024-01-04
Owner Infineon Technologies Austria AG (Austria)
Inventor
  • Medina-Garcia, Alfredo
  • Krüger, Martin
  • Fahlenkamp, Marc

Abstract

An asymmetric half bridge flyback converter, comprising a first primary side switching device and a second primary side switching device coupled in series between a supply voltage and a reference potential, a transformer, wherein one end of a primary side winding of the transformer is coupled to a node between the first primary side switching device and the second primary side switching device, a capacitor, wherein a resonant circuit including at least the primary side winding and the capacitor is coupled in parallel to the second primary side switching device, and a controller controlling the switches devices. The second primary side switching device is configured to prevent or reduce current flow in both directions when switched off.

IPC Classes  ?

  • H02M 3/335 - Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
  • H02M 1/088 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices

78.

METHOD AND CIRCUITRY TO APPLY AN INDIVIDUAL DC OFFSET TO ELECTRODES ON A LARGE-SCALE ION TRAP QUANTUM COMPUTER

      
Application Number 17856093
Status Pending
Filing Date 2022-07-01
First Publication Date 2024-01-04
Owner Infineon Technologies Austria AG (Austria)
Inventor Repp, Jens

Abstract

A device includes a plurality of digital-to-analog converters (DACs), a multiplexer, a plurality of electrodes including a first electrode, and a plurality of direct current (DC) offset circuits including a first DC offset circuit. At least one of the plurality of electrodes is located along a lane for movement of an ion. The multiplexer has multiple inputs coupled to the plurality of DACs and multiple outputs including a first output. The first output is configured to provide a first voltage. The first DC offset circuit is coupled between the first output and the first electrode. The first DC offset circuit is configured to add a first DC offset voltage to either the first voltage or the first voltage amplified by a first gain. The first DC offset voltage is configurable.

IPC Classes  ?

  • G21K 1/00 - Arrangements for handling particles or ionising radiation, e.g. focusing or moderating
  • H03M 1/66 - Digital/analogue converters

79.

SEMICONDUCTOR PACKAGE

      
Application Number 18327390
Status Pending
Filing Date 2023-06-01
First Publication Date 2023-12-28
Owner Infineon Technologies Austria AG (Austria)
Inventor Yuferev, Sergey

Abstract

A semiconductor package includes: a semiconductor die having opposing first and second surfaces, a first contact pad on the first surface, and a second contact pad on the second surface; a die pad and at least one lead spaced apart from the die pad, the first contact pad of the die being mounted on the die pad and the second contact pad being electrically connected to the at least one lead by a connector; a mold compound covering the die, connector, and an upper surface of the die pad and of the at least one lead; and a metallic member inductively coupled to the connector and electrically resistively insulated from the connector. The metallic member includes a web portion arranged above the second surface of the die and at least one peripheral rim portion that extends from the web portion in a direction towards the first surface of the die.

IPC Classes  ?

  • H01L 23/58 - Structural electrical arrangements for semiconductor devices not otherwise provided for
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
  • H01L 23/495 - Lead-frames

80.

POWER SEMICONDUCTOR MODULE ARRANGEMENT AND METHOD FOR FORMING THE SAME

      
Application Number 18332074
Status Pending
Filing Date 2023-06-09
First Publication Date 2023-12-28
Owner Infineon Technologies Austria AG (Austria)
Inventor
  • Bohnenberger, Timo
  • Heinrich, Alexander
  • Wille, Catharina

Abstract

A power semiconductor module arrangement includes a power semiconductor module. The power semiconductor module includes a substrate and a heat-conducting layer arranged on a lower surface of the power semiconductor module. The lower surface of the power semiconductor module is a surface that is configured to be mounted to a heat sink. The heat-conducting layer includes a metallic foam and an eutectic material filling cavities within the metallic foam.

IPC Classes  ?

  • H01L 23/373 - Cooling facilitated by selection of materials for the device
  • H01L 23/367 - Cooling facilitated by shape of device
  • H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups

81.

COUPLED INDUCTOR PATHS WITH ENHANCED THERMAL DISSIPATION

      
Application Number 17846925
Status Pending
Filing Date 2022-06-22
First Publication Date 2023-12-28
Owner Infineon Technologies Austrai AG (Austria)
Inventor
  • Clavette, Danny
  • Huang, Wenkang

Abstract

An inductor device includes a first face, a first inductive path, and magnetic permeable material. The first face couples the inductor device to a circuit board. The first inductive path extends between a first terminal on the first face to a second terminal on the first face. A portion of the first inductive path is exposed on a second face of the inductor device. The second face is disposed opposite the first face. The second face supports dissipation of heat conveyed by the first inductive path from the first face to the second face. The magnetic permeable material is disposed between the first face and the second face and carries magnetic flux associated with the first inductive path.

IPC Classes  ?

  • H01F 27/22 - Cooling by heat conduction through solid or powdered fillings
  • H01F 41/02 - Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils or magnets
  • H01F 27/06 - Mounting, supporting, or suspending transformers, reactors, or choke coils
  • H01F 27/24 - Magnetic cores
  • H05K 1/18 - Printed circuits structurally associated with non-printed electric components

82.

CURRENT LEAK DETECTION FOR SOLID STATE DEVICES

      
Application Number 17850713
Status Pending
Filing Date 2022-06-27
First Publication Date 2023-12-28
Owner Infineon Technologies Austria AG (Austria)
Inventor
  • Aichriedler, Leo
  • Wriessnegger, Gerald

Abstract

An apparatus comprises a solid state device and a switch in series with the solid state device. The apparatus comprises a leak detection component connected to the solid state device. The apparatus comprises a gate driver configured to drive a gate of the solid state device. The gate driver comprises test circuitry configured to apply a test voltage to the gate of the solid state device. The test voltage is less than a threshold voltage of the solid state device. The leak detection component is configured to detect a leakage of the solid state device.

IPC Classes  ?

  • G01R 31/52 - Testing for short-circuits, leakage current or ground faults

83.

SEMICONDUCTOR WAFER, CLIP AND SEMICONDUCTOR DEVICE

      
Application Number 18364483
Status Pending
Filing Date 2023-08-03
First Publication Date 2023-12-21
Owner Infineon Technologies Austria AG (Austria)
Inventor
  • Von Koblinski, Carsten
  • Pedone, Daniel
  • Piccin, Matteo
  • Rupp, Roland
  • Tai, Chiew Li
  • Wong, Jia Yi

Abstract

A semiconductor wafer includes: a first main surface and a second main surface opposite the first main surface; a detachment plane parallel to the first main surface inside the semiconductor wafer, the detachment plane defined by defects; electronic semiconductor components formed at the first main surface and between the first main surface and the detachment plane; and a glass structure attached to the first main surface. The glass structure includes openings, each of which leaves a respective area of the electronic semiconductor components uncovered. A method of processing the wafer, a clip, and a semiconductor device are also described.

IPC Classes  ?

  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices

84.

INDUCTIVE COUPLER WITH MAGNETIC MATERIAL

      
Application Number 17844524
Status Pending
Filing Date 2022-06-20
First Publication Date 2023-12-21
Owner Infineon Technologies Austria AG (Austria)
Inventor
  • Winzer, Annett
  • Kirsch, Michael
  • Mueller-Meskamp, Lars

Abstract

A semiconductor die includes: a semiconductor substrate; a transmitter or receiver circuit in the semiconductor substrate; a multi-layer stack on the semiconductor substrate, the multi-layer stack including a plurality of metallization layers separated from one another by an interlayer dielectric; and a transformer in the multi-layer stack and electrically coupled to the transmitter or receiver circuit. The transformer includes a first winding formed in a first metallization layer of the plurality of metallization layers and a second winding formed in a second metallization layer of the plurality of metallization layers. The first winding and the second winding are inductively coupled to one another. A magnetic material in the multi-layer stack is adjacent to at least part of the transformer.

IPC Classes  ?

  • H01F 17/00 - Fixed inductances of the signal type
  • H01F 27/28 - Coils; Windings; Conductive connections

85.

Multi-level power converter architecture

      
Application Number 17845879
Grant Number 11962249
Status In Force
Filing Date 2022-06-21
First Publication Date 2023-12-21
Grant Date 2024-04-16
Owner Infineon Technologies Austria AG (Austria)
Inventor
  • Abdelhamid, Eslam
  • Sanchez, Juan

Abstract

According to some embodiments, an apparatus comprises a multi-level power converter configured to convert an input voltage to an output voltage, wherein the multi-level power converter comprises one or more switching groups, wherein a switching group of the one or more switching groups comprises a pair of switches and a flying capacitor, and a controller configured to determine a duty reference for the switching group, determine a duty correction factor for the switching group based upon a flying capacitor voltage error of the flying capacitor, determine a sign correction signal based on a flying capacitor ripple voltage, and determine a duty command for activating the pair of switches based on the duty reference, the duty correction factor, and the sign correction signal.

IPC Classes  ?

  • H02M 7/483 - Converters with outputs that each can have more than two voltage levels
  • H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion

86.

SEMICONDUCTOR DEVICE WITH SEMICONDUCTOR MESAS BETWEEN ADJACENT GATE TRENCHES

      
Application Number 18453717
Status Pending
Filing Date 2023-08-22
First Publication Date 2023-12-07
Owner Infineon Technologies Austria AG (Austria)
Inventor
  • Brazzale, Anita
  • Haase, Robert
  • Leomant, Sylvain
  • Naik, Harsh

Abstract

A semiconductor device is described. The semiconductor device includes: a semiconductor substrate having a first main surface; a plurality of gate trenches extending from the first main surface into the semiconductor substrate; a semiconductor mesa between adjacent gate trenches; a first interlayer dielectric on the first main surface; a plurality of first metal contacts extending through the first interlayer dielectric and contacting gate electrodes disposed in the gate trenches; a plurality of second metal contacts extending through the first interlayer dielectric and contacting the semiconductor mesas; and an air gap or a dielectric material having a lower dielectric constant than the first interlayer dielectric between adjacent first and second metal contacts. Methods of producing the semiconductor device are also described.

IPC Classes  ?

  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/40 - Electrodes
  • H01L 29/45 - Ohmic electrodes
  • H01L 29/49 - Metal-insulator semiconductor electrodes
  • H01L 29/66 - Types of semiconductor device

87.

Protector Cap for Package with Thermal Interface Material

      
Application Number 18235104
Status Pending
Filing Date 2023-08-17
First Publication Date 2023-12-07
Owner Infineon Technologies Austria AG (Austria)
Inventor
  • Kasztelan, Christian
  • Khoo, Nee Wan

Abstract

A method of manufacturing a package includes mounting an electronic component on an electrically conductive carrier, encapsulating part of the carrier and the electronic component by an encapsulant, covering an exposed surface portion of the carrier with an electrically insulating and thermally conductive interface structure, and covering at least part of the interface structure by a protection cap.

IPC Classes  ?

  • H01L 23/04 - Containers; Seals characterised by the shape
  • H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
  • H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
  • H01L 23/367 - Cooling facilitated by shape of device
  • H01L 23/495 - Lead-frames

88.

Semiconductor Package with Releasable Isolation Layer Protection

      
Application Number 18235668
Status Pending
Filing Date 2023-08-18
First Publication Date 2023-12-07
Owner Infineon Technologies Austria AG (Austria)
Inventor
  • Chong, Li Fong
  • Daryl Yeow, Yee Beng
  • Hong, Chil Shang
  • Kassim, Azlina
  • Lit, Hui Kin

Abstract

A semiconductor device includes a semiconductor package, including a package body that includes an encapsulant portion and an isolation structure, a semiconductor die embedded within the package body, and a plurality of leads that protrude out from the encapsulant body, wherein the encapsulant portion and the isolation structure are each electrically insulating structures, wherein the isolation structure has a greater thermal conductivity than the encapsulant portion, and wherein the isolation structure is thermally coupled to the semiconductor die, and a releasable layer affixed to the semiconductor package, wherein a first outer face of the package body includes a first surface of the isolation structure, wherein the releasable layer at least partially covers the first surface of the isolation structure, and wherein the releasable layer is releasable from the semiconductor package.

IPC Classes  ?

  • H01L 23/433 - Auxiliary members characterised by their shape, e.g. pistons
  • H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
  • H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
  • H01L 23/495 - Lead-frames
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices

89.

VOLTAGE CONVERTER WITH SWITCH CONTROL CIRCUITRY

      
Application Number 17831493
Status Pending
Filing Date 2022-06-03
First Publication Date 2023-12-07
Owner Infineon Technologies Austria AG (Austria)
Inventor Bernardon, Derek

Abstract

A voltage converter is provided. The voltage converter comprises a switching circuit that includes a first pair of switches and a second pair of switches. The voltage converter comprises a transformer having a magnetizing inductance and a leakage inductance that are a function of a windings ratio of the transformer. The voltage converter comprises a capacitor coupled to the transformer and the switching circuit. The voltage converter comprises a switch control circuit configured to generate a frequency for controlling the first pair of switches and the second pair of switches. The frequency is set of a value to control the pairs of switches so that a peak capacitor voltage of the capacitor is a factor of an output voltage of the voltage converter and the windings ratio of the transformer.

IPC Classes  ?

  • H02M 3/335 - Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
  • H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion

90.

ELECTRONIC DEVICE MODULE AND A DEVICE MODULE BOTH HAVING AN ADHESION PROMOTER LAYER

      
Application Number 18315193
Status Pending
Filing Date 2023-05-10
First Publication Date 2023-11-23
Owner Infineon Technologies Austria AG (Austria)
Inventor
  • Fürgut, Edward
  • Sax, Harry
  • Schmoelzer, Bernd

Abstract

An electronic device module includes: a core layer having an opening; an electronic device disposed in the opening, one or both of the core layer and the electronic device being at least partially covered by an adhesion promoter layer; and an encapsulant layer at least partially embedding the core layer and the electronic device.

IPC Classes  ?

  • H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
  • H01L 23/29 - Encapsulation, e.g. encapsulating layers, coatings characterised by the material
  • H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings

91.

VOLTAGE REGULATOR MODULE WITH INDUCTOR-COOLED POWER STAGE

      
Application Number 17742442
Status Pending
Filing Date 2022-05-12
First Publication Date 2023-11-16
Owner INFINEON TECHNOLOGIES AUSTRIA AG (Austria)
Inventor
  • Deboy, Gerald
  • Chua, Kok Yau
  • Kessler, Angela
  • Leong, Kennith Kin
  • Ng, Chee Yang
  • Peluso, Luca

Abstract

A voltage regulator module includes: power input and output terminals at a same side of the voltage regulator module; a first power stage configured to receive an input voltage from the power input terminal and output a phase current at a switch node of the first power stage, the first power stage including an inductor having a vertical conductor embedded in a magnetic core, the vertical conductor having a first end which is electrically connected to the switch node and a second end opposite the first end; and a first metal clip which electrically connects the second end of the vertical conductor to the power output terminal such that power is delivered to and from the voltage regulator module at the same side of the voltage regulator module. A method of producing the voltage regulator module and electronic assembly that includes the voltage regulator module are also described.

IPC Classes  ?

  • H05K 1/02 - Printed circuits - Details
  • H05K 1/18 - Printed circuits structurally associated with non-printed electric components
  • H01F 27/24 - Magnetic cores
  • H05K 7/20 - Modifications to facilitate cooling, ventilating, or heating

92.

CHARGE REDISTRIBUTION FOR POWERING A DRIVEN SWITCH

      
Application Number 18225988
Status Pending
Filing Date 2023-07-25
First Publication Date 2023-11-16
Owner Infineon Technologies Austria AG (Austria)
Inventor
  • Fabbro, Simone
  • Giacomini, Davide
  • Frank, Wolfgang

Abstract

An apparatus comprises a power source connected to a buffer capacitor. The apparatus comprises a first switch connected between the buffer capacitor and a driven switch. The buffer capacitor is charged by the power source when the first switch is turned off. The apparatus comprises a comparator. The comparator monitors the charging of the buffer capacitor. In response to the buffer capacitor reaching a threshold amount of charge, the comparator turns on the first switch to initiate a charge redistribution of charge from the buffer capacitor to the driven switch.

IPC Classes  ?

  • H03K 17/284 - Modifications for introducing a time delay before switching in field-effect transistor switches

93.

POWER SEMICONDUCTOR MODULE ARRANGEMENT AND METHOD FOR PRODUCING THE SAME

      
Application Number 18316376
Status Pending
Filing Date 2023-05-12
First Publication Date 2023-11-16
Owner Infineon Technologies Austria AG (Austria)
Inventor
  • Bohnenberger, Timo
  • Roth, Alexander
  • Heinrich, Alexander

Abstract

A power semiconductor module arrangement includes a power semiconductor module, wherein the power semiconductor module includes a substrate for carrying at least one semiconductor body, and a heat-conducting layer arranged on a lower surface of the power semiconductor module, wherein the lower surface of the power semiconductor module is a surface that is configured to be mounted to a heat sink, and wherein the heat-conducting layer consists of a metallic and non-eutectic material that is solid at temperatures below a first threshold temperature, that is viscous at temperatures above the first threshold temperature and below a second threshold temperature, and that is fluid at temperatures above the second threshold temperature.

IPC Classes  ?

  • H01L 23/427 - Cooling by change of state, e.g. use of heat pipes
  • H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups

94.

TRANSISTOR DEVICE, SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING A TRANSISTOR DEVICE

      
Application Number 18142050
Status Pending
Filing Date 2023-05-02
First Publication Date 2023-11-16
Owner Infineon Technologies Austria AG (Austria)
Inventor
  • Pree, Elias
  • Lagger, Peter

Abstract

A transistor device includes a semiconductor substrate having a first major surface and transistor cells formed therein. Each transistor cell includes a drift region of a first conductivity type, a body region of an opposing second conductivity type arranged on the drift region, a source region of the first conductivity type arranged on the body region, a columnar field plate trench extending into the first major surface and including a field plate, and a gate trench structure extending into the first major surface and including a gate electrode. A first metallization structure on the first major surface provides a first contact pad for wire bonding. At least one of depth and doping level of the body region is locally increased within the transistor cells located within one or more first areas of the first major surface. One or more of the first areas are located underneath the first contact pad.

IPC Classes  ?

  • H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 29/66 - Types of semiconductor device
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions

95.

PARTIAL POWER CONVERTERS AND SPLIT PARTIAL POWER CONVERSION

      
Application Number 17735558
Status Pending
Filing Date 2022-05-03
First Publication Date 2023-11-09
Owner Infineon Technologies Austria AG (Austria)
Inventor
  • Peluso, Luca
  • Kasper, Matthias J.
  • Bernacchia, Giuseppe

Abstract

A first partial power converter implementation receives and converts an input voltage into multiple auxiliary voltages including a first auxiliary voltage and a second auxiliary voltage. The first partial power converter produces a first output voltage as a first summation of the first auxiliary voltage and the input voltage; the first partial power converter produces a second output voltage as a second summation of the second auxiliary voltage and the input voltage. A second partial power converter implementation as discussed herein receives a first auxiliary input voltage referenced with respect to an output voltage of the power converter. The second partial power converter also receives a second auxiliary input voltage referenced with respect to the output voltage. The second partial power converter converts the first auxiliary input voltage and the second auxiliary input voltage into the output voltage to power a load.

IPC Classes  ?

  • H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
  • H02J 9/06 - Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting in which the distribution system is disconnected from the normal source and connected to a standby source with automatic change-over

96.

METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE MODULE WITH INCREASED RELIABILITY AND A SEMICONDUCTOR DEVICE MODULE

      
Application Number 18140976
Status Pending
Filing Date 2023-04-28
First Publication Date 2023-11-09
Owner Infineon Technologies Austria AG (Austria)
Inventor
  • Schmoelzer, Bernd
  • Scholz, Wolfgang
  • Nikitin, Ivan
  • Fürgut, Edward

Abstract

A method for fabricating a semiconductor device module includes: providing a first encapsulant layer and a core layer disposed on the first encapsulant layer, the core layer having an opening; disposing a semiconductor device in the opening, the semiconductor device having a die carrier and a semiconductor die disposed on the die carrier; dispensing an encapsulant onto the semiconductor device; applying a second polymer layer onto the encapsulant so that the encapsulant is pressed into the opening; and laminating together the first and second encapsulant layers and the encapsulant.

IPC Classes  ?

  • H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
  • H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
  • H01L 23/29 - Encapsulation, e.g. encapsulating layers, coatings characterised by the material

97.

Measurement-Based Loudspeaker Excursion Limiting

      
Application Number 17735218
Status Pending
Filing Date 2022-05-03
First Publication Date 2023-11-09
Owner INFINEON TECHNOLOGIES AUSTRIA AG (Austria)
Inventor
  • Holm Hansen, Thomas
  • Garg, Pawan
  • Honda, Jun
  • Petersen, Niels

Abstract

A method for designing a loudspeaker excursion estimator comprises measuring an excursion-related parameter for a loudspeaker, for each of a plurality of loudspeaker input signal levels and each of a plurality of loudspeaker input signal frequencies. The method further comprises, for each of the loudspeaker input signal frequencies and based on the measured excursion-related parameters, identifying a respective loudspeaker input signal level corresponding to a target maximum excursion-related parameter value. The method further comprises determining a filter response, based on the identified loudspeaker input signal levels and their respective loudspeaker input signal frequencies, and implementing a filter, based on the calculated filter response, for generating an excursion estimation based on loudspeaker input signal levels.

IPC Classes  ?

  • H04R 3/00 - Circuits for transducers
  • H04R 3/04 - Circuits for transducers for correcting frequency response
  • H04R 29/00 - Monitoring arrangements; Testing arrangements

98.

POWER CONVERSION PHASES AND COUPLING INDUCTANCE

      
Application Number 17734339
Status Pending
Filing Date 2022-05-02
First Publication Date 2023-11-02
Owner Infineon Technologies Austria AG (Austria)
Inventor
  • Rizzolatti, Roberto
  • Chen, Cheng-Wei
  • Rainer, Christian
  • Ursino, Mario

Abstract

An apparatus such as a power converter includes a first flying capacitor operative to store a first flying capacitor voltage; a second flying capacitor operative to store a second flying capacitor voltage; an inductor providing coupling between the first flying capacitor and the second flying capacitor; and a network of switches operative to, in accordance with control signals, produce an output voltage via the first flying capacitor voltage and the second flying capacitor voltage.

IPC Classes  ?

  • H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion
  • H02M 1/088 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices

99.

HYBRID POWER CONVERTER AND POWER CONVERSION

      
Application Number 18219816
Status Pending
Filing Date 2023-07-10
First Publication Date 2023-11-02
Owner Infineon Technologies Austria AG (Austria)
Inventor
  • Rizzolatti, Roberto
  • Ursino, Mario

Abstract

This disclosure includes novel ways of implementing a voltage converter that powers a load. For example, the voltage converter includes a first power converter and a second power converter. The first power converter produces an intermediate voltage and a first output current derived from an input voltage. The first power converter supplies the intermediate voltage to the second power converter. The second power converter produces a second output current based on the intermediate voltage received from the first power converter. An output node of the voltage converter outputs a sum of the first output current and the second output current to produce an output voltage. A power supply can be configured to include any number of multiple voltage converters in parallel to power a load.

IPC Classes  ?

  • H02M 3/335 - Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
  • H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion
  • H02M 3/07 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
  • H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load

100.

POWER TRANSISTOR DEVICE AND METHOD OF FABRICATING A TRANSISTOR DEVICE

      
Application Number 18135788
Status Pending
Filing Date 2023-04-18
First Publication Date 2023-11-02
Owner Infineon Technologies Austria AG (Austria)
Inventor
  • Tegen, Stefan
  • Henson, Timothy

Abstract

In an embodiment, a power transistor device includes a substrate formed of crystalline silicon and having a first surface and a second surface opposing the first surface. A field plate formed of polysilicon is electrically connected with the substrate. An interfacial silicon nitride layer is arranged between the polysilicon of the field plate and the crystalline silicon of the substrate.

IPC Classes  ?

  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/51 - Insulating materials associated therewith
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