A semiconductor device includes a semiconductor wafer or a single semiconductor chip or die, and a layer stack. The layer stack comprises a first layer comprising NiSi, and a second layer comprising NiV, wherein the second layer is arranged between the first layer and the semiconductor wafer or single semiconductor chip or die.
Disclosed is a method for producing a semiconductor device, the method including forming a plurality of semiconductor arrangements one above the other, wherein forming each of the plurality of semiconductor arrangements includes forming a semiconductor layer, forming a plurality of trenches in a first surface of the semiconductor layer, and implanting dopant atoms of at least one of a first type and a second type into at least one of a first sidewall and a second sidewall of each of the plurality of trenches. Forming of at least one of the plurality of semiconductor arrangements further includes forming a protective layer covering mesa regions between the plurality of trenches of the respective semiconductor layer, and covering a bottom, the first sidewall and the second sidewall of each of the plurality of trenches that are formed in the respective semiconductor layer.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
A power stage includes: a first transformer; a second transformer; a third transformer; a GaN (gallium nitride) enhancement mode power transistor configured to conduct a load current when driven by a gate current derived from energy transferred by the first transformer; a GaN depletion mode transistor configured to turn off the GaN enhancement mode power transistor absent a threshold voltage applied across a gate and a source of the GaN depletion mode transistor; a voltage clamping device or circuit configured to turn off the GaN depletion mode transistor when reverse biased by a bias current derived from energy transferred by the second transformer; and a GaN enhancement mode transistor configured to turn on the GaN depletion mode transistor when driven by a gate current derived from energy transferred by the third transformer.
H03K 17/16 - Modifications for eliminating interference voltages or currents
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
H02M 7/06 - Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes without control electrode or semiconductor devices without control electrode
4.
DEVICE FOR CONTROLLING TRAPPED IONS WITH INTEGRATED WAVEGUIDE
Joanneum Research Forschungsgesellschaft mbH (Austria)
Universität Innsbruck (Austria)
Inventor
Rössler, Clemens
Lamprecht, Bernhard
Monz, Thomas
Schindler, Philipp
Abstract
A micro-fabricated device for controlling trapped ions includes a first substrate having a main surface. A structured first metal layer is disposed over the main surface of the first substrate. The structured first metal layer includes electrodes of at least one ion trapping zone configured to trap an ion in a space above the structured first metal layer. A dielectric element is fixedly attached to the first substrate. The dielectric element includes at least one short-pulse-laser direct written (SPLDW) waveguide configured to direct laser light towards an ion trapped in the at least one ion trapping zone.
In an embodiment, a semiconductor device is provided that includes a semiconductor substrate having a first major surface, one or more trenches formed in the first major surface and having a base and a side wall extending from the base to the first major surface, an anchoring layer, and a conductive member arranged in the one or more trenches and spaced apart from the side wall of the one or more trenches by a cavity formed in the one or more trenches . The anchoring layer extends from the first major surface of the semiconductor substrate over the cavity and onto an upper surface of the conductive member.
A unidirectional power switch includes: a normally-on switch device having a normally-on gate, a source, and a drain; a normally-off switch device having a normally-off gate, a source, and a drain, the drain of the normally-off switch device being electrically connected to the source of the normally-on switch device in a cascode configuration; a first source terminal electrically connected to the source of the normally-off switch device; a second source terminal electrically connected to the source of the normally-on switch device; and a drain terminal electrically connected to the drain of the normally-on switch device. The unidirectional power switch is configurable as either a normally-off unidirectional switch or a normally-on unidirectional switch, depending on a configuration of external gate driver connections to the source terminals. Additional power switch embodiments and related methods of configuring the power switches are described, including a configurable bidirectional power switch.
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
A gate driver comprises an input terminal, an output terminal, and first logic configured to generate an output drive signal at the output terminal corresponding to an input drive signal received at the input terminal. A blanking unit is configured to connect a current sense terminal of the gate driver to a reference supply terminal responsive to a low value of the output drive signal and disconnect the current sense terminal from the reference supply terminal after a predetermined delay period responsive to a high value of the output drive signal.
An apparatus comprises a switch and a capacitor connected to the switch and to a gate driver that drives a gate of a solid state device. The gate driver is operated to perform a test sequence for the solid state device. The test sequence includes turning on a switch and charging a capacitor to a supply voltage during an initial phase. During a first phase, the switch and the solid state device are turned off, the gate driver is disconnected from the supply voltage, and the gate driver drives the gate of the solid state device based at least upon a charge of the capacitor. During a second phase, the gate driver drives the gate of the solid state device to turn on the solid state device. A gate charge at the gate of the solid state device is measured as an operational state of the solid state device.
Digital-to-analog converter circuitry comprising a sequence of multiple current drive modules. The sequence may include a first current drive module and a second current drive module of a digital-to-analog converter. The first current drive module is switchable between: i) a first mode of producing a first reference current that is mirrored by a second current drive module coupled to the first current drive module; and ii) a second mode of mirroring a second reference current that is produced by the second current drive module or a third current drive module coupled to the first current drive module.
A layer stack is formed that includes a device layer and an insulator layer. The device layer includes electronic elements. The insulator layer is adjacent to a back surface of the device layer. A spacer disk is adhesive bonded on the layer stack on a side opposite the device layer. The spacer disk and the layer stack form a wafer composite. The wafer composite is divided into a plurality of individual semiconductor chips. Each semiconductor chip includes a portion of the layer stack and a portion of the spacer disk.
H01L 21/784 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, each consisting of a single circuit element the substrate being a semiconductor body
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 23/29 - Encapsulation, e.g. encapsulating layers, coatings characterised by the material
H01L 23/49 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of soldered or bonded constructions wire-like
11.
GATE DRIVER CIRCUIT AND POWER SWITCHING ASSEMBLY WITH GATE DRIVER CIRCUIT
A power switching assembly includes a first driver circuit and a second driver circuit. The first driver circuit is supplied via a first internal supply node and a first reference node and drives a first gate signal. The second driver circuit is supplied via a second internal supply node and a second reference node and drives a second gate signal. The first gate signal and the second gate signal are configured to be in phase with each other. The first reference node and the second reference node are separated. A first buffer capacitor is electrically connected between the first internal supply node and the first reference node. A second buffer capacitor electrically connected between the second internal supply node and the second reference node.
H03K 17/06 - Modifications for ensuring a fully conducting state
H03K 17/082 - Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
12.
Voltage regulator module and method of operating the same
A voltage regulator module may comprise a control signal generation module, a power stage, and a routing network. The control signal generation module may be configured to, in a first mode of operation, generate an internal control signal for controlling the power stage. The routing network may be configured to, in the first mode of operation, apply the internal control signal to a control node of the power stage. The routing network may be configured to, in a second mode of operation, electrically connect said control node to an input pin of the voltage regulator module such that the power stage is controllable by an external control signal applied to said input pin. Thus, in the second mode of operation, it becomes possible to control the power stage directly via the external control signal and use this power stage e.g. as a single phase of a multi-phase power converter.
H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
H02M 3/156 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
13.
Semiconductor Device Comprising a Leadframe Adapted for Higher Current Output or Improved Placement of Additional Devices
A semiconductor device comprises a leadframe comprising a die pad and a plurality of leads, a semiconductor die disposed on the die pad, the semiconductor die including a contact pad on a first main face thereof, and one or more bond wires connected with the contact pad, wherein a lead of the plurality of leads is bent back and connected with at least one first bond wire of the one or more bond wires.
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
14.
TRENCH GATE NMOS TRANSISTOR AND TRENCH GATE PMOS TRANSISTOR MONOLITHICALLY INTEGRATED IN SAME SEMICONDUCTOR DIE
A semiconductor die includes: a silicon substrate; a trench gate NMOS transistor formed in a first device region of the silicon substrate; a trench gate PMOS transistor formed in a second device region of the silicon substrate and electrically connected to the trench gate NMOS transistor; and an isolation structure interposed between the first device region and the second device region. Methods of monolithically integrating the trench gate NMOS transistor and the trench gate PMOS transistor in the same semiconductor die are also described.
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
H01L 21/266 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation using masks
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H02M 1/088 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
15.
CIRCUIT AND CONNECTOR ELEMENT ALIGNMENT, CIRCUIT BOARD ASSEMBLIES
This disclosure includes multiple assemblies, sub-assemblies, etc., as well as one or more methods of fabricating same. For example, a first assembly includes a first circuit board. The first circuit board further includes first connector elements disposed on a first edge of the first circuit board and second connector elements disposed on a second edge of the first circuit board. The first edge may be disposed substantially opposite the second edge on the first circuit board. The apparatus may further include first circuitry affixed to the first circuit board. The first edge of the first circuit board aligns with a first axial end of the first circuitry and the second edge of the first circuit board aligns with a second axial end of the first circuitry. The first assembly is used to fabricate a second assembly.
An apparatus includes a calibration circuit operative to produce an error signal indicative of an error associated with a current generator circuit generating a secondary current from a reference current. The secondary current is proportional to the reference current. The calibration circuit derives an adjustment value from the error signal and applies the adjustment value to the current generator circuit. Application of the adjustment value reduces a magnitude of the error signal.
G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
G05F 1/46 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc
An ion movement control apparatus with low pass filter switch , including a digital to analog converter (DAC) connected to a first port and enabled to provide a DAC voltage, an electrode element connected to a second port, the electrode element configured to provide an electrical field for controlling a position of an ion, and a filter switch between the first port and the second port and having a filter leg and a bypass leg in parallel, the filter leg having a filter leg switch and a filter portion between the first port and the second port and selectively coupling the first port through the filter leg to the second port to slow a voltage transient of the DAC voltage to the electrode element, and where the bypass leg has a bypass leg switch that selectively couples the first port directly to the second port.
A semiconductor device includes a semiconductor substrate having a major surface, a trench extending from the major surface into the substrate and having a base and a side wall extending form the base to the major surface, and a field plate arranged in the trench and having a height f. The field plate is electrically insulated from the substrate by a dielectric structure arranged in the trench. The dielectric structure includes a first portion having a first dielectric constant and a second portion having a second dielectric constant higher than the first dielectric constant. The first portion is arranged in a lower portion of the trench. The second portion is arranged in an upper portion of the trench, a thickness x, and overlaps the height of the field plate by a distance v1, where f*0.1≤v1≤f*0.8 or f*0.3≤v1≤f*0.6.
A circuit board assembly may include a first circuit board including a first slot. The circuit board assembly may include a second circuit board. The first circuit board may be interlocked with the second circuit board via interlocking provided by the second circuit board into the first slot.
A signal adjustor receives a first signal such as feedback associated with generation of an output voltage. The output voltage is regulated based on a selected setpoint reference voltage. The signal adjustor maps a magnitude of the selected setpoint reference voltage to a first set of signal adjustment information amongst multiple sets of signal adjustment information. The signal adjustor then applies the first signal adjustment information to the first signal to produce a second signal.
G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
G05F 1/46 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc
21.
Method for Fabricating a Power Semiconductor Device
A method for fabricating a SiC power semiconductor device includes: providing a SiC power semiconductor die; depositing a metallization layer over the power semiconductor die, the metallization layer including a first metal; arranging the power semiconductor die over a die carrier such that the metallization layer faces the die carrier, the die carrier being at least partially covered by a plating that includes Ni; and diffusion soldering the power semiconductor die to the die carrier such that a first intermetallic compound is formed between the power semiconductor die and the plating, the first intermetallic compound including Ni3Sn4.
A driver system includes a first half-bridge that generates a first load current at a first output node, a second half-bridge that generates a second load current at a second output node, a first voltage charging device coupled to the first output node, and a second voltage charging device coupled to the second output node. A method of detecting a short circuit condition in the driver system includes detecting a first charging time at which a first charging voltage of the first voltage charging device is charged to a first threshold voltage; detecting a second charging time at which a second charging voltage of the second voltage charging device is charged to a second threshold voltage; and detecting the short circuit condition on a condition that a time difference between the first charging time and the second charging time is less than a time difference threshold.
H03K 17/081 - Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
H02J 7/00 - Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
H02M 7/5387 - Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
H02P 27/08 - Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using dc to ac converters or inverters with pulse width modulation
In an embodiment, a semiconductor device includes: a main bi-directional switch formed on a semiconductor substrate and including first and second gates, a first source electrically connected to a first voltage terminal, a second source electrically connected to a second voltage terminal, and a common drain; and a substrate control circuit. The substrate control circuit includes: a first diode and a second diode; a discharge circuit including a first transistor and a second transistor connected in a common source configuration to the semiconductor substrate; and a gate potential control circuit including a third diode and a fourth diode. The first diode has a forward voltage Vf1 and the third diode has a forward voltage Vf3, where Vf1≥1.1Vf4 or Vf1≥1.2Vf4 or Vf1≥1.5Vf4 or Vf1≥2Vf4.
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
H03K 17/56 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices
24.
DIODE INCLUDING A TRENCH ELECTRODE SUBDIVIDED INTO AT LEAST FIRST AND SECOND PARTS
A diode is proposed. The diode includes: a semiconductor body having opposing first and second main surfaces; an anode region and a cathode region, the anode region being arranged between the first main surface and the cathode region; an anode pad area electrically connected to the anode region; and trenches extending into semiconductor body from the first main surface. A first group of the trenches includes a first trench electrode. The first trench electrode is subdivided into at least a first part and a second part. A conductance per unit length of the first part along a longitudinal direction of the first trench electrode is by at least a factor of 1000 smaller than a conductance per unit length of the second part along the longitudinal direction of the first trench electrode. The second part is electrically coupled to the anode pad area via the first part.
H01L 27/07 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
25.
POWER SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAME
A power semiconductor package includes: a die carrier having first and second opposite sides; and first and second power semiconductor dies each having first and second power electrodes on opposite sides. The second power electrodes face and are electrically coupled to the first side of the carrier. A molded body at least partially encapsulates the dies and has a first and second opposite sides and lateral sides connecting the first and second sides. First and second power contacts and first and second control contacts are arranged laterally next to each other. The first power electrode of the first die is electrically coupled to the first power contact by a first electrical connector. The first power electrode of the second die is electrically coupled to the second power contact by a second electrical connector. A width of each power contact is at least four times the width of each control contact.
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
A semiconductor package includes a substrate including a die pad, first and second discrete transistor dies mounted on the die pad, an encapsulant body that encapsulates the first and second discrete transistor dies, and a plurality of leads that are exposed from the encapsulant body, wherein the first and second discrete transistor dies are connected in parallel with one another by electrical interconnections that electrically connect common terminals of the first and second discrete transistor dies to one of the leads, and wherein at least one of the electrical interconnections has a balanced configuration that provides substantially identical electrical impedance as between the common terminals of the first and second discrete transistor dies and the lead to which they are connected.
A vertical junction field effect transistor includes mesa regions and trench structures extending along a first lateral direction in a semiconductor body and arranged alternately along a second lateral direction. The trench structures include a gate contact material electrically connected to a gate region of a first conductivity type in the semiconductor body. A width of the trench structures satisfies one or more of the following conditions: i) the width of at least one trench structure arranged outermost along the second lateral direction is smaller than in a more central part of the trench structures; or ii) the width of at least some trench structures is smaller along an end part in the first lateral direction than in the more central part, an extent of the end part along the first lateral direction being larger than a pitch between neighboring trench structures along the second lateral direction.
H01L 29/808 - Field-effect transistors with field effect produced by a PN or other rectifying junction gate with a PN junction gate
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
An apparatus may include an input pin\ and timing control circuitry coupled to the input pin. The timing control circuitry selectively executes one or more timing control functions based on a set of one or more hardware components coupled to the input pin. The set of one or more hardware components are disposed external to the apparatus. A configuration of the set of one or more hardware components determines which of one or more of the multiple timing control functions are enabled.
H02H 9/02 - Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess current
H02H 3/093 - Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition, with or without subsequent reconnection responsive to excess current with timing means
H03K 17/16 - Modifications for eliminating interference voltages or currents
H03K 17/284 - Modifications for introducing a time delay before switching in field-effect transistor switches
29.
Gate driver circuit with a limiting function to maintain control voltage under a rated limit
A gate driver system includes a transistor configured to be driven between switching states, the transistor including a control terminal controlled by a control voltage that has a maximum rated limit; and a gate driver coupled to the control terminal by a turn-on current path, the gate driver being configured to control the control voltage in order to drive the transistor between the switching states. The turn-on current path includes a resistor and a Zener diode connected in series, with an anode of the Zener diode connected to the control terminal and a cathode of the Zener diode connected to the resistor. The turn-on current path is configured to provide an on-current to increase the control voltage above a switching threshold. While the transistor is turned on, the Zener diode is configured to limit the control voltage to a voltage level limit that is less than the maximum rated limit.
H03K 3/00 - Circuits for generating electric pulses; Monostable, bistable or multistable circuits
H03K 17/00 - Electronic switching or gating, i.e. not by contact-making and -breaking
H03K 17/06 - Modifications for ensuring a fully conducting state
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
H03K 17/693 - Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors
30.
ELECTRONIC CIRCUIT WITH A TRANSISTOR DEVICE AND A CLAMP CIRCUIT AND METHOD
An electronic circuit and a method are disclosed. The electronic circuit includes: a first transistor device having a load path between a first load path node and a second load path node; and a clamping circuit connected to the load path of the first transistor device. The clamping circuit includes: a second transistor device having a load path connected in parallel with the load path of the first transistor device, and a control node; and a drive circuit configured to drive the second transistor device. The drive circuit includes a clamping element and a resistor connected in series between the first and second load path nodes of the first transistor device. The drive circuit is configured to drive the second transistor device dependent on a voltage across the resistor. The first transistor device and the clamping circuit are integrated in a same semiconductor die.
H03K 17/06 - Modifications for ensuring a fully conducting state
H03K 17/081 - Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
H03K 17/10 - Modifications for increasing the maximum permissible switched voltage
31.
ISOLATED POWER CONVERTER HAVING A VOLTAGE SUPPLY CIRCUIT
An isolated power converter includes: a transformer having primary winding and first and second auxiliary windings on the primary side; a converter stage configured to convert a DC input for driving the primary winding and having a resonant capacitor electrically connected to the primary winding; a controller configured to control switching of the converter stage; and a voltage supply circuit configured to select a first voltage as a supply voltage for the controller if a voltage proportional to a secondary side voltage of the transformer is at a first level or select a second voltage as the supply voltage if the voltage proportional to the secondary side voltage is at a second level greater than the first level. The first voltage corresponds to a summation of voltages across the first auxiliary winding and the resonant capacitor. The second voltage corresponds to a voltage across the second auxiliary winding.
H02M 3/335 - Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
H02M 3/00 - Conversion of dc power input into dc power output
32.
SILICON-ON-INSULATOR (SOI) DEVICE HAVING VARIABLE THICKNESS DEVICE LAYER AND CORRESPONDING METHOD OF PRODUCTION
A method of producing power semiconductor devices from a silicon-on-insulator (SOI) wafer is described. The SOI wafer includes a silicon device layer, a bulk silicon wafer, and a buried oxide layer separating the silicon device layer from the bulk silicon wafer. The method includes: forming a hard mask on the silicon device layer, wherein the hard mask covers one or more first regions of the silicon device layer and exposes one or more second regions of the silicon device layer; and before forming any field oxide structures and before implanting any device regions, selectively growing epitaxial silicon on the one or more second regions of the silicon device layer exposed by the hard mask such that the thickness of the one or more second regions is increased relative to the one or more first regions. Various devices produced according to the method are also described.
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/80 - Field-effect transistors with field effect produced by a PN or other rectifying junction gate
In an embodiment, a transistor device includes: a support layer having a first major surface and a second major surface opposing the first major surface; a source contact arranged on the first major surface of the support layer; a drain contact arranged on the second major surface of the support layer; and a gate electrode arranged in a first trench formed in the first major surface of the support layer. The first trench has a base and a side wall extending from the base to the first major surface. The drain contact is arranged under the base of the first trench. A region with gate-controlled conductivity is formed between the source contact and the drain contact. The region with gate-controlled conductivity is formed in an organic semiconductor layer.
The present application relates to a semiconductor device, including: a field electrode in a needle-shaped field electrode trench extending from a frontside of a semiconductor body into the semiconductor body; a lower metallization layer on the frontside of the semiconductor body and electrically connected to the field electrode; an insulating layer on the lower metallization layer; an upper metallization layer on the insulating layer, and a first interconnect electrically connecting the lower metallization layer to the upper metallization layer. The first interconnect is laterally offset to the field electrode trench. The lower metallization layer is not connected to the upper metallization layer in a region vertically above the field electrode trench.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
35.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE
A semiconductor device is provided. The semiconductor device includes a substrate, an isolation region that is formed at a main surface of the substrate, and a recess in the isolation region. The semiconductor device further includes an active or passive device that is formed in the recess. The active or passive device includes a first semiconductor material region and a second semiconductor material region. The first semiconductor material region adjoins at least part of the second semiconductor material region in a first direction parallel to the main surface of the substrate. An upper surface of the first semiconductor material region is above an upper surface of the second semiconductor material region. The upper surface of the second semiconductor material region is below the main surface of the substrate.
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
A method of forming a semiconductor module comprises forming a laminate structure having an electrically insulating core layer with opposing first and second sides, a first redistribution layer arranged on the first side and a second redistribution layer arranged on the second side. First and second transistor devices are coupled to form a half-bridge circuit. Bots transistor devices have a first side at which a cell field is arranged and an opposing second side. A control chip has a first side with contact pads. The transistor devices and control chip are arranged laterally adjacent one another and embedded in the core layer. The first side of the control chip and one transistor device and the second side of the other transistor device face towards the first redistribution layer on the first side of the core layer.
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
A transistor device includes a semiconductor substrate having a first major surface, a cell field and an edge termination region laterally surrounding the cell field. The cell field includes: elongate active trenches that extend from the first major surface into the semiconductor substrate, a field plate and a gate electrode being positioned in each elongate active trench, the gate electrode being arranged above and electrically insulated from the field plate; and elongate mesas, each elongate mesa being formed between neighbouring elongate active trenches, the elongate mesas comprising a drift region, a body region on the drift region and a source region on the body region.
A transformer includes a winding configured to carry a current. The winding includes a conductor structure through which the current flows and a graphene layer arranged in direct contact with the conductor structure.
H01B 1/04 - Conductors or conductive bodies characterised by the conductive materials; Selection of materials as conductors mainly consisting of carbon-silicon compounds, carbon, or silicon
H01F 41/04 - Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils or magnets for manufacturing coils
39.
POWER SEMICONDUCTOR DEVICE HAVING COUNTER-DOPED REGIONS IN BOTH AN ACTIVE CELL REGION AND AN INACTIVE CELL REGION
A power semiconductor device includes: trench gate structures in an active cell region of a semiconductor substrate and extending into an inactive cell region of the semiconductor substrate that adjoins the active cell region; an electrically insulating material covering the trench gate structures; first contact openings in the electrically insulating material between adjacent trench gate structures in the active cell region; second contact openings in the electrically insulating material vertically aligned with the trench gate structures in the inactive cell region; first counter-doped regions between the adjacent trench gate structures in the active cell region and vertically aligned with the first contact openings; second counter-doped regions underneath the trench gate structures in the inactive cell region and vertically aligned with the second contact openings; first contacts in the first contact openings; and second contacts in the second contact openings. Methods of producing the power semiconductor device are also described.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
A method for fabricating a semiconductor device includes providing a die with a metallization layer including a first metal with a high melting point; providing a die carrier including a second metal with a high melting point; providing a solder material including a third metal with a low melting point; providing a layer of a fourth metal with a high melting point on the semiconductor die or the die carrier; and soldering the semiconductor die to the die carrier and creating: a first intermetallic compound between the semiconductor die and the die carrier and including the first metal and the third metal; a second intermetallic compound between the first intermetallic compound and the die carrier and including the second metal and the third metal; and precipitates of a third intermetallic compound between the first intermetallic compound and the second intermetallic compound and including the third metal and the fourth metal.
The present document relates to multi-phase power converters. In particular, the present document relates to a multi-phase power converter comprising a first phase with a first power stage and a first inductor, a second phase with a second power stage and a second inductor, and a first substrate extending along a first substrate plane. The first power stage, the first inductor and the second inductor may be arranged above the first substrate. The second power stage may be arranged below the first substrate. By arranging the two power stages vertically shifted on different sides of the first substrate, it becomes possible to save space in the substrate plane and thus decrease the horizontal space required for a given number of phases of the multi-phase power converter
H02M 7/00 - Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
H05K 1/18 - Printed circuits structurally associated with non-printed electric components
H02M 1/084 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters using a control circuit common to several phases of a multi-phase system
A gate charge profiler for a power transistor may include a voltage comparator unit and a timer unit. An input signal may control a gate drive current input to a gate of the power transistor to control conduction between a drain and a source of the power transistor. The voltage comparator unit may be configured to compare an input voltage and a threshold voltage, and to output a comparison signal. The input voltage may be a drain-source voltage across the drain and the source of the power transistor or a gate-source voltage across the gate and the source of the power transistor. The timer unit may be configured to output a time value based on input of a transition of the input signal and input of the comparison signal.
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
H03K 5/24 - Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
43.
SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING A SEMICONDUCTOR PACKAGE FOR UPRIGHT MOUNTING
A semiconductor package includes low voltage and high voltage contact pads, an output contact pad, a half-bridge circuit, and first, second and third leads. The half bridge circuit includes first and second transistor devices coupled in series at an output node. Both transistor devices have a first major surface which extends substantially perpendicularly to the low voltage contact pad, the high voltage contact pad, and the output contact pad. Both transistor devices are arranged in a device portion of the package and are mounted on a first lead, the first lead providing the output contact pad and being arranged on a first side of the device portion. The second and third leads are arranged in a common plane on a second side of the device portion that opposes the first side. The second lead provides the low voltage pad and the third second lead provides the high voltage output pad.
In an embodiment, a semiconductor device is provided that includes a Group III nitride transistor device and a Schottky barrier diode integrated in a Group III nitride body. A common drain/cathode finger is arranged on the Group III nitride body. Two or more source contacts are arranged on the Group III nitride body and spaced apart in a row, the row being spaced laterally apart from, and extending substantially parallel to, the common drain/cathode finger. A gate electrode structure and one or more Schottky metal contacts are arranged on the Group III nitride body. At least one Schottky metal contact is arranged between and spaced apart from neighbouring ones of the source contacts. The gate electrode structure includes a closed ring section for each source contact that laterally surrounds that source contact. Neighbouring closed ring sections are connected by a gate connection section.
H01L 27/07 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
In an embodiment, a semiconductor device is provided that includes a semiconductor die having a front side, a rear side opposing the front side, and side faces, a first transistor device having a first source pad and a first gate pad on the front side, and a second transistor device having a second source pad and a second gate pad on the front side. The first and second transistor devices each have a drain that is electrically coupled to a common drain pad on the rear side of the semiconductor die. The drain pad has an upper surface and side faces and at least a central portion of the upper surface is covered by a first electrically insulating layer.
In an embodiment, a semiconductor package includes a lower surface having a low voltage contact pad, a high voltage contact pad, an output contact pad, and at least one control contact pad. The semiconductor package further includes a half-bridge circuit including a first transistor device having a first major surface and a second transistor device having a first major surface, the first and second transistor devices being electrically coupled in series at an output node, and a control device that is electrically coupled to the first transistor device and the second transistor device. The first major surface of the first transistor device and of the second transistor device are arranged substantially perpendicularly to the lower surface of the semiconductor package.
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different main groups of groups , or in a single subclass of , , e.g. forming hybrid circuits
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices
An ion shuttling system includes a plurality of first electrodes connected to a system configured to selectively provide an ion movement control voltage to each electrode of the plurality of first electrodes, a voltage source configured to provide one or more compensation voltages, a plurality of compensation electrodes comprising a plurality of compensation electrode pairs, where each compensation electrode pair of the plurality of compensation electrode pairs is associated with one or more different first electrodes of the plurality of first electrodes, and a plurality of switches, where each switch of the plurality of switches is connected at a respective first node to a compensation electrode of the plurality of compensation electrodes and is configured to selectively connect the respective compensation electrode to the voltage source.
A semiconductor die includes: a semiconductor substrate having an active region and an edge termination region that separates the active region from an edge of the semiconductor substrate; a plurality of transistor cells formed in the active region; a structured power metallization above the semiconductor substrate and including a gate pad and a gate runner that extends from the gate pad along one or more but not all sides of the semiconductor die above the edge termination region, the gate runner electrically connecting the gate pad to gate electrodes of the transistor cells; and a tungsten runner that follows the gate runner and contacts an underside of the gate runner. The tungsten runner is present above the edge termination region along each side of the semiconductor die that is at least partly devoid of the gate runner. A Method of producing the semiconductor die is also described.
H01L 23/528 - Layout of the interconnection structure
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
A method of passively braking a motor to reduce a current motor speed includes generating at least one control signal to control a first load current generated by a first half bridge circuit and a second load current generated by a second half bridge circuit. During passive braking, the method includes synchronously driving a first high-side transistor and a second high-side transistor between their respective switching states at an alternating shorting frequency such that they are simultaneously in a same switching state, and synchronously driving a first low-side transistor and a second low-side transistor between their respective switching states at the alternating shorting frequency such that they are simultaneously in a same switching state, wherein the first high-side transistor and the second high-side transistor are driven in a complementary manner to the first low-side transistor and the second low-side transistor according to a predetermined duty cycle.
A switch device comprises: a first power transistor die that includes a normally-on transistor having at most half a maximum rated drain-to-source voltage as the switch device; a second power transistor die that includes a normally-off transistor having at most half the maximum rated drain-to-source voltage as the switch device, wherein a drain of the normally-off transistor is electrically connected to a source of the normally-on transistor to form a cascode device; a voltage blocking device electrically connected between a gate of the normally-on transistor and a source of the normally-off transistor, and configured to block a portion of the voltage across the switch device when the cascode device is off; and an overvoltage protection device configured to turn off the normally-on transistor when the normally-off transistor turns off, such that the cascode device is actively controlled only by a gate of the normally-off transistor. Additional switch devices embodiments are described.
H03K 17/10 - Modifications for increasing the maximum permissible switched voltage
H03K 17/0814 - Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the output circuit
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
51.
CASCODE-BASED SWITCH DEVICE WITH VOLTAGE CLAMP CIRCUIT
A switch device includes: a first power transistor die including a normally-on power transistor; a second power transistor die including a normally-off power transistor having a drain electrically connected to a source of the normally-on power transistor to form a cascode device; and a capacitor electrically connected between a gate of the normally-on power transistor and a source of the normally-off power transistor. Both power transistors have at most half a maximum rated drain-to-source voltage as the switch device. The second power transistor die further includes a voltage clamp circuit having a normally-off clamp transistor with a drain electrically connected to the gate of the normally-on power transistor and a source electrically connected to the source of the normally-off power transistor, and diode(s) between the drain and a gate of the normally-off clamp transistor. Additional switch devices embodiments are described.
H03K 17/10 - Modifications for increasing the maximum permissible switched voltage
H03K 17/0814 - Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the output circuit
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
52.
SEMICONDUCTOR DIE AND METHOD OF MANUFACTURING THE SAME
A semiconductor die includes a semiconductor device and an edge termination structure laterally between the semiconductor device and a lateral edge of the die. The edge termination structure includes a first inner shield electrode region with a shield electrode in a trench extending into a semiconductor body, an outer shield electrode region with a shield electrode in a trench extending into the semiconductor body and disposed in a first lateral direction between the first inner shield electrode region and the lateral edge, and a well region formed in the semiconductor body adjacent the trench of the first inner shield electrode region. The shield electrode of the first inner shield electrode region is electrically connected to the well region to tap an electrical potential from the well region. The shield electrode of the outer shield electrode region is electrically connected to the shield electrode of the first inner shield electrode region.
Semiconductor Package or a Printed Circuit Board, Both Modified to One or More of Reduce, Inverse or Utilize Magnetic Coupling Caused by the Load Current of a Semiconductor Transistor
A semiconductor package comprises a semiconductor transistor circuit comprising a semiconductor transistor die comprising die terminals, including a collector/drain, a source/emitter, a sense source/sense emitter, a gate, and a load path, a driver line connected with the gate, and a gate control loop in which the a sense source/sense emitter is connected with the driver line, a plurality of external contacts comprising at least one first external contact connected with the drain/collector, at least one second external contact connected with the source/emitter, a third external contact connected with the a sense source/sense emitter, and a fourth external contact connected with the gate, wherein the plurality of external contacts are arranged or configured to reduce or utilize the magnetic coupling induced by a load current flowing through the load path.
A method of controlling current through a transistor is provided. A voltage and current through the transistor are measured. A safe operating current for the voltage is determined. For each of a first sequence of current pulses, a voltage of a voltage pulse applied to a control node of the transistor using a feedback controller is adjusted until the current measured through the transistor is not greater than a first function of the safe operating current. For each of a second sequence of current pulses after the first sequence of current pulses, the voltage of the voltage pulse applied to the control node of the transistor using the feedback controller is adjusted until the current measured through the transistor is not greater than a second function of the safe operating current.
An asymmetric half bridge flyback converter, comprising a first primary side switching device and a second primary side switching device coupled in series between a supply voltage and a reference potential, a transformer, wherein one end of a primary side winding of the transformer is coupled to a node between the first primary side switching device and the second primary side switching device, a capacitor, wherein a resonant circuit including at least the primary side winding and the capacitor is coupled in parallel to the second primary side switching device, and a controller controlling the switches devices. The second primary side switching device is configured to prevent or reduce current flow in both directions when switched off.
H02M 3/335 - Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
H02M 1/088 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
56.
METHOD AND CIRCUITRY TO APPLY AN INDIVIDUAL DC OFFSET TO ELECTRODES ON A LARGE-SCALE ION TRAP QUANTUM COMPUTER
A device includes a plurality of digital-to-analog converters (DACs), a multiplexer, a plurality of electrodes including a first electrode, and a plurality of direct current (DC) offset circuits including a first DC offset circuit. At least one of the plurality of electrodes is located along a lane for movement of an ion. The multiplexer has multiple inputs coupled to the plurality of DACs and multiple outputs including a first output. The first output is configured to provide a first voltage. The first DC offset circuit is coupled between the first output and the first electrode. The first DC offset circuit is configured to add a first DC offset voltage to either the first voltage or the first voltage amplified by a first gain. The first DC offset voltage is configurable.
A semiconductor package includes: a semiconductor die having opposing first and second surfaces, a first contact pad on the first surface, and a second contact pad on the second surface; a die pad and at least one lead spaced apart from the die pad, the first contact pad of the die being mounted on the die pad and the second contact pad being electrically connected to the at least one lead by a connector; a mold compound covering the die, connector, and an upper surface of the die pad and of the at least one lead; and a metallic member inductively coupled to the connector and electrically resistively insulated from the connector. The metallic member includes a web portion arranged above the second surface of the die and at least one peripheral rim portion that extends from the web portion in a direction towards the first surface of the die.
H01L 23/58 - Structural electrical arrangements for semiconductor devices not otherwise provided for
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
A power semiconductor module arrangement includes a power semiconductor module. The power semiconductor module includes a substrate and a heat-conducting layer arranged on a lower surface of the power semiconductor module. The lower surface of the power semiconductor module is a surface that is configured to be mounted to a heat sink. The heat-conducting layer includes a metallic foam and an eutectic material filling cavities within the metallic foam.
H01L 23/373 - Cooling facilitated by selection of materials for the device
H01L 23/367 - Cooling facilitated by shape of device
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
59.
COUPLED INDUCTOR PATHS WITH ENHANCED THERMAL DISSIPATION
An inductor device includes a first face, a first inductive path, and magnetic permeable material. The first face couples the inductor device to a circuit board. The first inductive path extends between a first terminal on the first face to a second terminal on the first face. A portion of the first inductive path is exposed on a second face of the inductor device. The second face is disposed opposite the first face. The second face supports dissipation of heat conveyed by the first inductive path from the first face to the second face. The magnetic permeable material is disposed between the first face and the second face and carries magnetic flux associated with the first inductive path.
H01F 27/22 - Cooling by heat conduction through solid or powdered fillings
H01F 41/02 - Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils or magnets
H01F 27/06 - Mounting, supporting, or suspending transformers, reactors, or choke coils
An apparatus comprises a solid state device and a switch in series with the solid state device. The apparatus comprises a leak detection component connected to the solid state device. The apparatus comprises a gate driver configured to drive a gate of the solid state device. The gate driver comprises test circuitry configured to apply a test voltage to the gate of the solid state device. The test voltage is less than a threshold voltage of the solid state device. The leak detection component is configured to detect a leakage of the solid state device.
A semiconductor die includes: a semiconductor substrate; a transmitter or receiver circuit in the semiconductor substrate; a multi-layer stack on the semiconductor substrate, the multi-layer stack including a plurality of metallization layers separated from one another by an interlayer dielectric; and a transformer in the multi-layer stack and electrically coupled to the transmitter or receiver circuit. The transformer includes a first winding formed in a first metallization layer of the plurality of metallization layers and a second winding formed in a second metallization layer of the plurality of metallization layers. The first winding and the second winding are inductively coupled to one another. A magnetic material in the multi-layer stack is adjacent to at least part of the transformer.
A semiconductor wafer includes: a first main surface and a second main surface opposite the first main surface; a detachment plane parallel to the first main surface inside the semiconductor wafer, the detachment plane defined by defects; electronic semiconductor components formed at the first main surface and between the first main surface and the detachment plane; and a glass structure attached to the first main surface. The glass structure includes openings, each of which leaves a respective area of the electronic semiconductor components uncovered. A method of processing the wafer, a clip, and a semiconductor device are also described.
According to some embodiments, an apparatus comprises a multi-level power converter configured to convert an input voltage to an output voltage, wherein the multi-level power converter comprises one or more switching groups, wherein a switching group of the one or more switching groups comprises a pair of switches and a flying capacitor, and a controller configured to determine a duty reference for the switching group, determine a duty correction factor for the switching group based upon a flying capacitor voltage error of the flying capacitor, determine a sign correction signal based on a flying capacitor ripple voltage, and determine a duty command for activating the pair of switches based on the duty reference, the duty correction factor, and the sign correction signal.
H02M 7/483 - Converters with outputs that each can have more than two voltage levels
H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion
64.
SEMICONDUCTOR DEVICE WITH SEMICONDUCTOR MESAS BETWEEN ADJACENT GATE TRENCHES
A semiconductor device is described. The semiconductor device includes: a semiconductor substrate having a first main surface; a plurality of gate trenches extending from the first main surface into the semiconductor substrate; a semiconductor mesa between adjacent gate trenches; a first interlayer dielectric on the first main surface; a plurality of first metal contacts extending through the first interlayer dielectric and contacting gate electrodes disposed in the gate trenches; a plurality of second metal contacts extending through the first interlayer dielectric and contacting the semiconductor mesas; and an air gap or a dielectric material having a lower dielectric constant than the first interlayer dielectric between adjacent first and second metal contacts. Methods of producing the semiconductor device are also described.
A method of manufacturing a package includes mounting an electronic component on an electrically conductive carrier, encapsulating part of the carrier and the electronic component by an encapsulant, covering an exposed surface portion of the carrier with an electrically insulating and thermally conductive interface structure, and covering at least part of the interface structure by a protection cap.
A semiconductor device includes a semiconductor package, including a package body that includes an encapsulant portion and an isolation structure, a semiconductor die embedded within the package body, and a plurality of leads that protrude out from the encapsulant body, wherein the encapsulant portion and the isolation structure are each electrically insulating structures, wherein the isolation structure has a greater thermal conductivity than the encapsulant portion, and wherein the isolation structure is thermally coupled to the semiconductor die, and a releasable layer affixed to the semiconductor package, wherein a first outer face of the package body includes a first surface of the isolation structure, wherein the releasable layer at least partially covers the first surface of the isolation structure, and wherein the releasable layer is releasable from the semiconductor package.
A voltage converter is provided. The voltage converter comprises a switching circuit that includes a first pair of switches and a second pair of switches. The voltage converter comprises a transformer having a magnetizing inductance and a leakage inductance that are a function of a windings ratio of the transformer. The voltage converter comprises a capacitor coupled to the transformer and the switching circuit. The voltage converter comprises a switch control circuit configured to generate a frequency for controlling the first pair of switches and the second pair of switches. The frequency is set of a value to control the pairs of switches so that a peak capacitor voltage of the capacitor is a factor of an output voltage of the voltage converter and the windings ratio of the transformer.
H02M 3/335 - Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion
68.
ELECTRONIC DEVICE MODULE AND A DEVICE MODULE BOTH HAVING AN ADHESION PROMOTER LAYER
An electronic device module includes: a core layer having an opening; an electronic device disposed in the opening, one or both of the core layer and the electronic device being at least partially covered by an adhesion promoter layer; and an encapsulant layer at least partially embedding the core layer and the electronic device.
A voltage regulator module includes: power input and output terminals at a same side of the voltage regulator module; a first power stage configured to receive an input voltage from the power input terminal and output a phase current at a switch node of the first power stage, the first power stage including an inductor having a vertical conductor embedded in a magnetic core, the vertical conductor having a first end which is electrically connected to the switch node and a second end opposite the first end; and a first metal clip which electrically connects the second end of the vertical conductor to the power output terminal such that power is delivered to and from the voltage regulator module at the same side of the voltage regulator module. A method of producing the voltage regulator module and electronic assembly that includes the voltage regulator module are also described.
A transistor device includes a semiconductor substrate having a first major surface and transistor cells formed therein. Each transistor cell includes a drift region of a first conductivity type, a body region of an opposing second conductivity type arranged on the drift region, a source region of the first conductivity type arranged on the body region, a columnar field plate trench extending into the first major surface and including a field plate, and a gate trench structure extending into the first major surface and including a gate electrode. A first metallization structure on the first major surface provides a first contact pad for wire bonding. At least one of depth and doping level of the body region is locally increased within the transistor cells located within one or more first areas of the first major surface. One or more of the first areas are located underneath the first contact pad.
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
An apparatus comprises a power source connected to a buffer capacitor. The apparatus comprises a first switch connected between the buffer capacitor and a driven switch. The buffer capacitor is charged by the power source when the first switch is turned off. The apparatus comprises a comparator. The comparator monitors the charging of the buffer capacitor. In response to the buffer capacitor reaching a threshold amount of charge, the comparator turns on the first switch to initiate a charge redistribution of charge from the buffer capacitor to the driven switch.
A power semiconductor module arrangement includes a power semiconductor module, wherein the power semiconductor module includes a substrate for carrying at least one semiconductor body, and a heat-conducting layer arranged on a lower surface of the power semiconductor module, wherein the lower surface of the power semiconductor module is a surface that is configured to be mounted to a heat sink, and wherein the heat-conducting layer consists of a metallic and non-eutectic material that is solid at temperatures below a first threshold temperature, that is viscous at temperatures above the first threshold temperature and below a second threshold temperature, and that is fluid at temperatures above the second threshold temperature.
H01L 23/427 - Cooling by change of state, e.g. use of heat pipes
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
73.
PARTIAL POWER CONVERTERS AND SPLIT PARTIAL POWER CONVERSION
A first partial power converter implementation receives and converts an input voltage into multiple auxiliary voltages including a first auxiliary voltage and a second auxiliary voltage. The first partial power converter produces a first output voltage as a first summation of the first auxiliary voltage and the input voltage; the first partial power converter produces a second output voltage as a second summation of the second auxiliary voltage and the input voltage. A second partial power converter implementation as discussed herein receives a first auxiliary input voltage referenced with respect to an output voltage of the power converter. The second partial power converter also receives a second auxiliary input voltage referenced with respect to the output voltage. The second partial power converter converts the first auxiliary input voltage and the second auxiliary input voltage into the output voltage to power a load.
H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H02J 9/06 - Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting in which the distribution system is disconnected from the normal source and connected to a standby source with automatic change-over
74.
METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE MODULE WITH INCREASED RELIABILITY AND A SEMICONDUCTOR DEVICE MODULE
A method for fabricating a semiconductor device module includes: providing a first encapsulant layer and a core layer disposed on the first encapsulant layer, the core layer having an opening; disposing a semiconductor device in the opening, the semiconductor device having a die carrier and a semiconductor die disposed on the die carrier; dispensing an encapsulant onto the semiconductor device; applying a second polymer layer onto the encapsulant so that the encapsulant is pressed into the opening; and laminating together the first and second encapsulant layers and the encapsulant.
A method for designing a loudspeaker excursion estimator comprises measuring an excursion-related parameter for a loudspeaker, for each of a plurality of loudspeaker input signal levels and each of a plurality of loudspeaker input signal frequencies. The method further comprises, for each of the loudspeaker input signal frequencies and based on the measured excursion-related parameters, identifying a respective loudspeaker input signal level corresponding to a target maximum excursion-related parameter value. The method further comprises determining a filter response, based on the identified loudspeaker input signal levels and their respective loudspeaker input signal frequencies, and implementing a filter, based on the calculated filter response, for generating an excursion estimation based on loudspeaker input signal levels.
An apparatus such as a power converter includes a first flying capacitor operative to store a first flying capacitor voltage; a second flying capacitor operative to store a second flying capacitor voltage; an inductor providing coupling between the first flying capacitor and the second flying capacitor; and a network of switches operative to, in accordance with control signals, produce an output voltage via the first flying capacitor voltage and the second flying capacitor voltage.
H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion
H02M 1/088 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
77.
POWER TRANSISTOR DEVICE AND METHOD OF FABRICATING A TRANSISTOR DEVICE
In an embodiment, a power transistor device includes a substrate formed of crystalline silicon and having a first surface and a second surface opposing the first surface. A field plate formed of polysilicon is electrically connected with the substrate. An interfacial silicon nitride layer is arranged between the polysilicon of the field plate and the crystalline silicon of the substrate.
In an embodiment, a semiconductor package is provided that includes a first package surface and a second package surface opposing the first surface, a plastic molding and one or more semiconductor dies. The first package surface includes a first surface of the plastic molding and a first metallic area exposed from the plastic molding. The first metallic area includes a first product marking including at least one alphanumeric character and the first surface of the plastic molding includes a second product marking including at least one alphanumeric character.
A semiconductor package includes a substrate, a first and a second semiconductor die arranged on the substrate, a molded body encapsulating the first and second semiconductor dies, the molded body including a first external side facing away from the substrate, a plurality of electrical connectors extending at least partially through the molded body from the first external side to the first and/or second semiconductor die, and a plurality of plated conductive tracks arranged in trenches within the molded body on the first external side. T conductive tracks are coupled to the first and/or second semiconductor die by the electrical connectors.
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 21/60 - Attaching leads or other conductive members, to be used for carrying current to or from the device in operation
This disclosure includes novel ways of implementing a voltage converter that powers a load. For example, the voltage converter includes a first power converter and a second power converter. The first power converter produces an intermediate voltage and a first output current derived from an input voltage. The first power converter supplies the intermediate voltage to the second power converter. The second power converter produces a second output current based on the intermediate voltage received from the first power converter. An output node of the voltage converter outputs a sum of the first output current and the second output current to produce an output voltage. A power supply can be configured to include any number of multiple voltage converters in parallel to power a load.
H02M 3/335 - Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion
H02M 3/07 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
A method is disclosed. The method includes switching off a power transistor circuit in an electronic circuit. The electronic circuit includes a power source and a load circuit. The power transistor circuit is connected between the power source and the load circuit. Switching off the power transistor circuit includes operating at least one power transistor included in the power transistor circuit in an Avalanche mode so that at least a portion of energy stored in the electronic circuit before switching off the power transistor circuit is dissipated in the at least one power transistor.
H03K 17/0812 - Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the control circuit
H03K 17/284 - Modifications for introducing a time delay before switching in field-effect transistor switches
A device for trapping ions includes: a first substrate having an upper multi-layer electrode structure implemented at a top side of the first substrate; a second substrate disposed over the first substrate and having a lower multi-layer electrode structure implemented at a bottom side of the second substrate; and one or more first level ion traps configured to trap ions in a space between the first substrate and the second substrate. The one or more first level ion traps includes the upper multi-layer electrode structure of the first substrate and the lower multi-layer electrode structure of the second substrate. A method of controlling trapped ions in a device is also described.
A semiconductor device is described. The semiconductor device includes: a semiconductor substrate; a trench formed in a first main surface of the semiconductor substrate; a field plate electrode in the trench and reaching a same level as the first main surface of the semiconductor substrate; an insulating material that separates the field plate electrode from the semiconductor substrate; and a material embedded in the field plate electrode. The field plate electrode is made of a different material than the material embedded in the field plate electrode. The trench adjoins a region of the semiconductor substrate through which current flows in a first direction during operation of the semiconductor device. Additional device embodiments and methods of producing the semiconductor device are also described.
A semiconductor device includes: a semiconductor substrate; an epitaxial layer or layer stack on the semiconductor substrate; a plurality of transistor cells of a first type formed in a first region of the epitaxial layer or layer stack and electrically coupled in parallel to form a vertical power transistor; a plurality of transistor cells of a second type different than the first type and formed in a second region of the epitaxial layer or layer stack; and an isolation structure that laterally and vertically delimits the second region of the epitaxial layer or layer stack. Sidewalls and a bottom of the isolation structure include a dielectric material that electrically isolates the plurality of transistor cells of the second type from the plurality of transistor cells of the first type in the epitaxial layer or layer stack. Methods of producing the semiconductor device are also described.
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 21/765 - Making of isolation regions between components by field-effect
H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
85.
MULTI-CHIP DEVICE WITH GATE REDISTRIBUTION STRUCTURE
A power device package includes first and second power transistor chips each having a control electrode, a first load electrode and a second load electrode. A control package terminal is electrically coupled to the control electrode of the first power transistor chip via a first wire bond connection and to the control electrode of the second power transistor chip via a second wire bond connection. A first package terminal is electrically coupled to the first load electrode of the first and second power transistor chips. A second package terminal is electrically coupled to the second load electrode of the first power transistor chip and/or the second power transistor chip. A length of the first wire bond connection is greater than a length of the second wire bond connection, and a cross-sectional area of the first wire bond connection is greater than a cross-sectional area of the second wire bond connection.
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
86.
MULTI DIMENSIONAL ELECTRODE CONTROLLER FOR QUANTUM COMPUTING
A method and apparatus for multidimensional ion shuttling, the apparatus including a first shuttling lane having first lane elements, a second shuttling lane having second lane elements with the second shuttling lane intersecting the first shuttling lane, first electrode elements along the first movement lane, second electrode elements along the second movement lane, an electrode control circuit connected to each of the first and second electrode elements, and a voltage control circuit connected to each electrode element of the first electrode elements and the second electrode elements. The voltage control circuit selectively provides at least one voltage to one or more electrode elements of the first electrode elements and of the second electrode elements according to signaling from the electrode control circuit, and the at least one voltage controls movement of an ion along at least one of the first shuttling lane or the second shuttling lane.
G06N 10/40 - Physical realisations or architectures of quantum processors or components for manipulating qubits, e.g. qubit coupling or qubit control
87.
CONTROLLER FOR AN ASYMMETRIC HALF BRIDGE FLYBACK CONVERTER,ASYMMETRIC HALF BRIDGE FLYBACK CONVERTER AND A METHOD OF CONTROLLING AN ASYMMETRIC HALF BRIDGE FLYBACK CONVERTER
A controller for an asymmetric half bridge flyback converter as discussed herein. The control may include control logic configured to control one of a high-side switch and low-side switch of a half bridge of the asymmetric half bridge flyback converter based on a peak current control. For example, the control logic can be configured to limit an on-time of the one of the high-side switch and the low-side switch based on a threshold value.
H02M 3/335 - Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
H02M 3/00 - Conversion of dc power input into dc power output
H02M 1/32 - Means for protecting converters other than by automatic disconnection
88.
SEMICONDUCTOR DEVICE HAVING A LATERAL TRANSISTOR DEVICE AND AN INVERTER THAT INCLUDES THE SEMICONDUCTOR DEVICE
In an embodiment, a semiconductor device is provided that includes a lateral transistor device having a source, a drain and a gate, and a monolithically integrated capacitor coupled between the gate and the drain.
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
89.
CIRCUIT FOR BI-DIRECTIONAL CONVERTER, BI-DIRECTIONAL CONVERTER AND OPERATION METHOD THEREOF
A circuit for a bi-directional DC-DC converter, a bi-directional DC-DC converter and a method for operating a bi-directional DC-DC converter are disclosed. The circuit comprises: a first input terminal and a second input terminal configured to receive a DC input; a DC output terminal; a first switch and a second switch; a first control interface configured to control the first switch to be switched on and off; a second control interface configured to control the second switch to be switched on and off; a first primary winding coupled in series with the first switch between the first input terminal and a common terminal; a second primary winding coupled in series with the second switch between the second input terminal and the common terminal; and a common secondary winding with one end coupled to the DC output terminal.
H02M 3/335 - Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion
90.
STACKED POWER SUPPLY TOPOLOGIES AND INDUCTOR DEVICES
According to one configuration, an inductor device comprises: core material and one or more electrically conductive paths. The core material is magnetically permeable and surrounds (envelops) the one or more electrically conductive paths. Each of the electrically conductive paths extends through the core material of the inductor device from a first end of the inductor device to a second end of the inductor device. The magnetically permeable core material is operative to confine (guide, carry, convey, localize, etc.) respective magnetic flux generated from current flowing through a respective electrically conductive path. The core material stores the magnetic flux energy (i.e., first magnetic flux) generated from the current flowing through the first electrically conductive path. One configuration herein includes a power converter assembly comprising a stack of components including the inductor device as previously described as well as a first power interface, a second power interface, and one or more switches.
H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H01F 41/02 - Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils or magnets
H01F 41/04 - Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils or magnets for manufacturing coils
H02M 7/00 - Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
H05K 1/18 - Printed circuits structurally associated with non-printed electric components
H05K 3/32 - Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
H02M 3/335 - Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
91.
CROSS CONDUCTION PROTECTION IN A VOLTAGE CONVERTER
A power supply includes a controller. The controller controls switching of a first switch and a second switch in a power supply to regulate conveyance of energy from a primary winding of a transformer to a secondary winding of the transformer to generate an output voltage. To control generation of the output voltage, the controller receives a first signal generated at a first node coupling the first switch and the second switch. As discussed herein, the controller controls activation of the first switch to an ON state depending on a magnitude of the first signal. This disclosure provides improved reliability of power supply components (such as one or more switches) because such components are no longer stressed (or overstressed) due to body diode cross conduction.
H02M 3/335 - Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
92.
Efficiency concept for driving a PMOS and NMOS full-bridge power stage
A circuit, which might be a full-bridge driver circuit, comprises a first PMOS high-side transistor device and a first NMOS low-side transistor device. The circuit further comprises turn-on circuitry configured to turn on the first PMOS high-side transistor device while simultaneously turning on the first NMOS low-side transistor device, by routing charge stored in a gate of the first PMOS high-side transistor device to a gate of the first NMOS low-side transistor device, to charge the gate of the first NMOS low-side transistor device.
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
H02P 7/03 - Arrangements for regulating or controlling the speed or torque of electric DC motors for controlling the direction of rotation of DC motors
Disclosed is a method for operating a rectifier circuit, a control circuit for operating a rectifier circuit, and a power converter. The method includes operating the rectifier circuit (2) in a PFC mode, wherein operating the rectifier circuit (2) in the PFC mode includes regulating an output voltage (Udc) of the rectifier circuit (2). Regulating the output voltage (Udc) includes operating a switch (26) of the rectifier circuit (2) at a fixed switching frequency (fsw), and regulating the output voltage (Udc) includes regulating the output voltage (Udc) dependent on at least one operating parameter of the rectifier circuit (2) such that the switch (26) is operated under ZVS conditions.
H02M 1/42 - Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion
H02M 7/217 - Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
In an embodiment, a transistor device is provided that includes: a semiconductor substrate having a front surface and an active area, the active area including a plurality of active transistor cells, each active transistor cell having a columnar trench with a field plate, a mesa, and a gate electrode; and a metallization structure arranged on the front surface, the metallization structure providing a gate pad and a source pad. At least a part of the gate pad is arranged above the active area.
In an embodiment, a semiconductor device is provided that includes: a vertical power FET configured to switch a load current and provide a channel of a first conductivity type; and a lateral FET configured to drive the vertical power FET and provide a channel of a second conductivity type opposing the first conductivity type. The vertical power FET and the lateral FET are monolithically integrated into a semiconductor substrate of the first conductivity type and a drain of the lateral FET is electrically coupled to a gate of the vertical power FET.
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
96.
SEMICONDUCTOR DIE HAVING A SODIUM STOPPER IN AN INSULATION LAYER GROOVE AND METHOD OF MANUFACTURING THE SAME
The application relates to a semiconductor die having a semiconductor body including an active region, an insulation layer on the semiconductor body, and a sodium stopper formed in the insulation layer. The sodium stopper is arranged in an insulation layer groove which intersects the insulation layer vertically and extends around the active region. The sodium stopper is formed of a tungsten material that at least partly fills the insulation layer groove. Both the insulation layer groove and the tungsten material extend into the semiconductor body.
In an embodiment, a semiconductor device includes a vertical power FET for switching a load current, the power FET including a channel region of a first conductivity type and a first lateral FET and a second lateral FET providing an output stage of gate driver circuitry for driving the power FET. The first lateral FET includes a channel region of the first conductivity type and the second lateral FET includes a channel region of a second conductivity type opposing the first conductivity type. The power FET and the first and second lateral FETs are monolithically integrated into a semiconductor substrate of the first conductivity type and that has a first surface. A drain of the first lateral FET and a source of the second lateral FET are electrically coupled to a gate of the power FET.
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
98.
Power Diode and Method of Manufacturing a Power Diode
A power diode includes a semiconductor body having an anode region and a drift region, the semiconductor body being coupled to an anode metallization of the power diode and to a cathode metallization of the power diode, and an anode contact zone and an anode damage zone, both implemented in the anode region, the anode contact zone being arranged in contact with the anode metallization, and the anode damage zone being arranged in contact with and below the anode contact zone, wherein fluorine is included within each of the anode contact zone and the anode damage zone at a fluorine concentration of at least 1016 atoms*cm-3.
An insulated gate bipolar transistor (IGBT) is proposed. The IGBT includes a semiconductor body having a first surface and a second surface. The IGBT further includes an active area and an edge termination area that at least partly surrounds the active area. The active area includes a first part of an active IGBT area and a second part of the active IGBT area. The IGBT further includes a contact on the second surface of the semiconductor body. A minimum vertical distance between the contact in the first part of the active IGBT area and a reference level at the first surface is larger than a minimum vertical distance between the contact in the second part of the active IGBT area and the reference level at the first surface.
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
A single chip power diode includes a semiconductor body having an anode region coupled to a first load terminal and a cathode region coupled to a second load terminal. An edge termination region surrounding an active region is terminated by a chip edge. The semiconductor body thickness is defined by a distance between at least one first interface area formed between the first load terminal and the anode region and a second interface area formed between the second load terminal and the cathode region. At least one inactive subregion is included in the active region. Each inactive subregion: has a blocking area with a minimal lateral extension of at least 20% of a drift region thickness; configured to prevent crossing of the load current between the first load terminal and the semiconductor body through the blocking area; and at least partially not arranged adjacent to the edge termination region.
