Toshiba Corporation

Japan

Back to Profile

1-100 of 11,772 for Toshiba Corporation and 8 subsidiaries Sort by
Query
Patent
United States - USPTO
Excluding Subsidiaries
Aggregations Reset Report
Owner / Subsidiary
[Owner] Toshiba Corporation 11,772
Toshiba TEC Corporation 1,504
Toshiba Digital Solutions Corporation 315
Toshiba Materials Co., Ltd. 190
Toshiba Lighting & Technology Corporation 74
See more
Date
New (last 4 weeks) 194
2023 September (MTD) 178
2023 August 62
2023 July 48
2023 June 64
See more
IPC Class
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate 464
H01L 29/66 - Types of semiconductor device 409
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions 354
G03G 15/00 - Apparatus for electrographic processes using a charge pattern 338
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched 291
See more
Status
Pending 1,646
Registered / In Force 10,126
Found results for  patents
  1     2     3     ...     100        Next Page

1.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

      
Application Number 17942019
Status Pending
Filing Date 2022-09-09
First Publication Date 2023-09-28
Owner
  • KABUSHIKI KAISHA TOSHIBA (Japan)
  • TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION (Japan)
Inventor Okawa, Naoki

Abstract

According to one embodiment, a semiconductor device includes a lead frame including a terminal; an element on a first surface of the lead frame; and a package member covering the lead frame and the semiconductor element. The terminal includes a back-side portion provided on a side of a second surface of the lead frame and exposed from the package member in a first direction perpendicular to the first surface, the second surface being opposite to the first surface, a lateral-side portion provided between the first surface and the back-side portion in the first direction and exposed from the package member in a second direction parallel to the first surface, and a recessed portion provided between the lateral-side portion and the back-side portion in the first direction.

IPC Classes  ?

  • H01L 23/498 - Leads on insulating substrates
  • H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
  • H01L 23/495 - Lead-frames
  • H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
  • H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
  • H01L 21/66 - Testing or measuring during manufacture or treatment

2.

SEMICONDUCTOR DEVICE

      
Application Number 18007227
Status Pending
Filing Date 2021-07-26
First Publication Date 2023-09-28
Owner
  • KABUSHIKI KAISHA TOSHIBA (Japan)
  • TOSHIBA INFRASTRUCTURE SYSTEMS & SOLUTIONS CORPORATION (Japan)
Inventor Sugimoto, Yuta

Abstract

A semiconductor device includes a semiconductor substrate, a first semiconductor layer on the semiconductor substrate, a second semiconductor layer on the first semiconductor layer, a first electrode on the second semiconductor layer, a second electrode arranged with the first electrode along a front surface of the second semiconductor layer, a third electrode between the first and second electrodes on the second semiconductor layer, a metal layer on a back surface of the semiconductor substrate at a side opposite to the first semiconductor layer, and a conductor extending inside the semiconductor substrate and electrically connecting the first electrode and the metal layer via the second semiconductor layer. The second semiconductor layer includes a first region including a first-conductivity-type impurity, and a second region including a first-conductivity-type impurity with a higher concentration than the first region; and the second region is between the conductor and the first electrode.

IPC Classes  ?

  • H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
  • H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/40 - Electrodes
  • H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements

3.

PRINTED CIRCUIT BOARD AND DISK DEVICE

      
Application Number 17899385
Status Pending
Filing Date 2022-08-30
First Publication Date 2023-09-28
Owner
  • KABUSHIKI KAISHA TOSHIBA (Japan)
  • TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION (Japan)
Inventor Akutsu, Kazuyoshi

Abstract

According to one embodiment, a printed circuit board includes a substrate and a shared pad group provided on the substrate and including a plurality of shared pads. The shared pads include a first area, a second area smaller in size than the first area, a port of which is overlap the first area and an other port of which is located to protrude from the first area to a side of another one of the shared pads, and a second side edge located on a side of another shared pad. The second pad side edge includes a first side edge defining the first area, a second side edge defining the second area and displaced on a side of another shared pad with respect to the first side edge, and a sloping side edge connecting the first side edge and the second side edge to each other.

IPC Classes  ?

  • H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
  • H05K 1/02 - Printed circuits - Details
  • G11B 5/82 - Disk carriers

4.

MULTIPLICATION DEVICE, MULTIPLY-ACCUMULATE OPERATION DEVICE, MATRIX OPERATION DEVICE, AND RESERVOIR DEVICE

      
Application Number 17820224
Status Pending
Filing Date 2022-08-16
First Publication Date 2023-09-28
Owner KABUSHIKI KAISHA TOSHIBA (Japan)
Inventor
  • Marukame, Takao
  • Mizushima, Koichi
  • Nishi, Yoshifumi
  • Nomura, Kumiko

Abstract

A multiplication device according to one embodiment includes a short-term memory circuit, a long-term memory circuit, a conversion circuit, and a control circuit. The short-term memory circuit generates a first control voltage in accordance with a weight value. The long-term memory circuit generates a second control voltage by a circuit with a larger time constant than the short-term memory circuit. The conversion circuit outputs an output current by multiplying an input voltage by a conductance. The output current is output by that, the first control voltage is applied to a control terminal of the conversion circuit, and an input voltage according to an input value is applied to an input terminal of the conversion circuit. The control circuit executes a calibration process of matching the first control voltage with the second control voltage by transferring an electric charge from the long-term memory circuit to the short-term memory circuit.

IPC Classes  ?

  • G06F 7/544 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices for evaluating functions by calculation
  • H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
  • G06F 17/16 - Matrix or vector computation

5.

SEMICONDUCTOR DEVICE

      
Application Number 17891671
Status Pending
Filing Date 2022-08-19
First Publication Date 2023-09-28
Owner
  • KABUSHIKI KAISHA TOSHIBA (Japan)
  • TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION (Japan)
Inventor Kono, Hiroshi

Abstract

A semiconductor device includes a first electrode, a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a second electrode, a third electrode, and a fourth semiconductor layer. The third electrode is located among the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer via an insulating film. The fourth semiconductor layer is located between the insulating film and the first semiconductor layer and between the insulating film and the second semiconductor layer. An impurity concentration of the fourth semiconductor layer is less than an impurity concentration of the first semiconductor layer and an impurity concentration of the second semiconductor layer.

IPC Classes  ?

  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
  • H01L 29/49 - Metal-insulator semiconductor electrodes

6.

GENERATION SYSTEM, GENERATION METHOD, AND STORAGE MEDIUM

      
Application Number 18168822
Status Pending
Filing Date 2023-02-14
First Publication Date 2023-09-28
Owner Kabushiki Kaisha Toshiba (Japan)
Inventor
  • Zhou, Xinyi
  • Takaki, Masaya
  • Sugiyama, Naomi
  • Shinji, Sayaka
  • Oka, Kazuhiro

Abstract

According to one embodiment, a generation system generates a production plan. The production plan is for producing products of product types by processes using production lines. The system includes an optimization calculation part, an input plan generator, and a verification part. The optimization calculation part generates a processing plan by an optimization calculation using first input data. The first input data includes a production plan amount of each of the product types and a processing capacity of each equipment. The input plan generator generates an input plan by using second input data. The second input data includes an input amount of workpieces to each of the production lines for each of the product types. The second input data further includes a processing route in the plurality of processes for each of the product types. The verification part determines an appropriateness of the processing plan and the input plan

IPC Classes  ?

  • G05B 19/418 - Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control (DNC), flexible manufacturing systems (FMS), integrated manufacturing systems (IMS), computer integrated manufacturing (CIM)

7.

MAGNETIC DISK DEVICE AND METHOD

      
Application Number 17903870
Status Pending
Filing Date 2022-09-06
First Publication Date 2023-09-28
Owner
  • Kabushiki Kaisha Toshiba (Japan)
  • Toshiba Electronic Devices & Storage Corporation (Japan)
Inventor Maruyama, Syosuke

Abstract

According to an embodiment, on a first track of a magnetic disk, a plurality of first sectors in each of which a data segment is stored, and a second sector in which a parity for first error correction is stored are arranged in this order from a first position. A controller executes a first operation of sequentially reading a first data segment from each of the plurality of first sectors, and storing a group of the read first data segments in a buffer memory. The controller obtains a first parity from the group of the read first data segments. The controller starts a second operation of writing each first data segment in the group of the first data segments stored in the buffer memory, to a first sector that is a read source among the plurality of first sectors, and writing the first parity to the second sector, before the magnetic head reaches the first position.

IPC Classes  ?

  • G11B 5/09 - Digital recording
  • G11B 5/008 - Recording on, or reproducing or erasing from, magnetic tapes or wires

8.

SEMICONDUCTOR DEVICE

      
Application Number 17942510
Status Pending
Filing Date 2022-09-12
First Publication Date 2023-09-28
Owner
  • KABUSHIKI KAISHA TOSHIBA (Japan)
  • TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION (Japan)
Inventor
  • Tsai, Yuning
  • Takahashi, Yoshiko

Abstract

According to one embodiment, a semiconductor device includes a package substrate including a package member and a first conductive portion; a semiconductor package provided on a first surface of the package substrate inside the package member and coupled to the first conductive portion; a first semiconductor chip provided on the first surface of the package substrate inside the package member and including a first terminal; a second semiconductor chip provided on the first surface of the package substrate inside the package member and including a second terminal; and a connection component that couples the first and second terminals to the first conductive portion inside the package member.

IPC Classes  ?

  • H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different main groups of groups , or in a single subclass of , , e.g. forming hybrid circuits
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices

9.

SILICON CARBIDE SEMICONDUCTOR DEVICE

      
Application Number 17897753
Status Pending
Filing Date 2022-08-29
First Publication Date 2023-09-28
Owner
  • Kabushiki Kaisha Toshiba (Japan)
  • Toshiba Electronic Devices & Storage Corporation (Japan)
Inventor
  • Suzuki, Takuma
  • Kono, Hiroshi
  • Tanaka, Katsuhisa

Abstract

According to one embodiment, a silicon carbide semiconductor device includes a first electrode, a second electrode, a first semiconductor layer, a plurality of first semiconductor pillar regions of a first conductivity type, a second semiconductor pillar region of a second conductivity type. The first semiconductor pillar regions include a first region has a first impurity concentration and second region has a second impurity concentration higher than the first impurity concentration. The second semiconductor pillar regions include a third region has a third impurity concentration and a fourth region has a fourth impurity concentration higher than the third impurity concentration.

IPC Classes  ?

  • H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions

10.

MAGNETIC DISK DEVICE AND METHOD

      
Application Number 17931647
Status Pending
Filing Date 2022-09-13
First Publication Date 2023-09-28
Owner
  • KABUSHIKI KAISHA TOSHIBA (Japan)
  • TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION (Japan)
Inventor Tawada, Fuyuki

Abstract

According to an embodiment, a magnetic disk is provided with a track, and the track is provided with a data sector. The data sector includes a plurality of servo regions in which servo data is written, and a plurality of first data regions. Each of the plurality of first data regions is disposed between two servo regions of the plurality of servo regions. The controller executes a first write operation of writing data sequentially to the plurality of first data regions using the magnetic head. After the first write operation, the controller executes a second write operation of retrying the writing to a second data region in which the write error is detected among the plurality of first data regions, and not retrying the writing to a third data region in which the write error is not detected among the plurality of first data regions.

IPC Classes  ?

  • G11B 19/04 - Arrangements for preventing, inhibiting, or warning against, double recording on the same blank, or against other recording or reproducing malfunctions
  • G11B 20/18 - Error detection or correction; Testing

11.

SEMICONDUCTOR DEVICE

      
Application Number 17940373
Status Pending
Filing Date 2022-09-08
First Publication Date 2023-09-28
Owner
  • TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION (Japan)
  • KABUSHIKI KAISHA TOSHIBA (Japan)
Inventor
  • Asaba, Shunsuke
  • Kono, Hiroshi

Abstract

A semiconductor device includes: a first conductive type first silicon carbide region including a first region, a second region and a third region both on the first region, the second region having impurity concentration equal to or higher than the first region, and the third region having impurity concentration higher than the second region; a second conductive type second silicon carbide region on the first silicon carbide region, the second silicon carbide region including a fourth region in contact with the second region and a fifth region in contact with the third region, and the fifth region having impurity concentration higher than the fourth region; a third silicon carbide region of a first conductive type on the second silicon carbide region; a first gate electrode; a first electrode having a first portion in contact with the second silicon carbide region and the third silicon carbide region; and a second electrode.

IPC Classes  ?

  • H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

12.

COMMUNICATION RELAY APPARATUS SND STORAGE MEDIUM STORING COMPUTER PROGRAM

      
Application Number 18153983
Status Pending
Filing Date 2023-04-11
First Publication Date 2023-09-28
Owner
  • KABUSHIKI KAISHA TOSHIBA (Japan)
  • Toshiba Infrastructure Systems & Solutions Corporation (Japan)
Inventor Tango, Toshihiro

Abstract

A communication relay apparatus and a storage medium storing a computer program that allow improvement of a quality of communication with a mobile station are provided. A communication relay apparatus includes a detector and a controller. The detector detects a mobile station located in a cover area formed by a plurality of remote units. The controller controls, for the remote units, communication resources used by the remote units for communication with the mobile station, based on a detection result of the detector.

IPC Classes  ?

  • H04B 7/026 - Co-operative diversity, e.g. using fixed or mobile stations as relays
  • H04B 7/155 - Ground-based stations

13.

SEMICONDUCTOR DEVICE, INVERTER CIRCUIT, DRIVING DEVICE, VEHICLE, AND ELEVATOR

      
Application Number 17823088
Status Pending
Filing Date 2022-08-30
First Publication Date 2023-09-28
Owner KABUSHIKI KAISHA TOSHIBA (Japan)
Inventor Shimizu, Tatsuo

Abstract

A semiconductor device according to an embodiment includes: a silicon carbide layer having a first surface and second surface parallel to a first direction and a second direction perpendicular to the first direction; a first trench and second trench extending in the first direction; an n-type first region in the silicon carbide layer; a p-type second region between the first region and the first surface in the silicon carbide layer; an n-type third region between the second region and the first surface in the silicon carbide layer; a p-type sixth region between the first region and the first trench in the silicon carbide layer; and a p-type eighth region located between the second region and the first trench, between the third region and the first trench, and in contact with the sixth region in the silicon carbide layer. The eighth regions are repeatedly disposed in the first direction.

IPC Classes  ?

  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
  • H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H02P 27/06 - Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using dc to ac converters or inverters

14.

MULTILAYER JUNCTION PHOTOELECTRIC CONVERSION ELEMENT AND METHOD FOR MANUFACTURING THE SAME

      
Application Number 18317466
Status Pending
Filing Date 2023-05-15
First Publication Date 2023-09-28
Owner
  • KABUSHIKI KAISHA TOSHIBA (Japan)
  • TOSHIBA ENERGY SYSTEMS & SOLUTIONS CORPORATION (Japan)
Inventor
  • Gotanda, Takeshi
  • Tobari, Tomohiro
  • Saita, Yutaka

Abstract

The present embodiment provides a semiconductor element that can generate power with high efficiency and has high durability. The present embodiment provides a semiconductor element that can generate power with high efficiency and has high durability. A multilayer junction photoelectric conversion element according to an embodiment comrises: a first electrode; a first photoactive layer including a perovskite semiconductor; a first passivation layer; a first doped layer; a second photoactive layer containing silicon; and a second electrode, in this order. The multilayer junction photoelectric conversion element further comprises a light scattering layer including a plurality of mutually separated silicon alloy layers that penetrate a part of the passivation layer and electrically connect the first photoactive layer and the first doped layer. The element can be manufactured by a method including forming a bottom cell including a second active layer and then forming a first photoactive layer by coating.

IPC Classes  ?

  • H01L 31/0224 - Electrodes
  • H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof

15.

METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE AND SILICON CARBIDE SEMICONDUCTOR DEVICE

      
Application Number 17892809
Status Pending
Filing Date 2022-08-22
First Publication Date 2023-09-28
Owner
  • Kabushiki Kaisha Toshiba (Japan)
  • Toshiba Electronic Devices & Storage Corporation (Japan)
Inventor Suzuki, Takuma

Abstract

According to one embodiment, a method for manufacturing a silicon carbide semiconductor device. The method includes forming a semiconductor layer on a substrate. The method includes forming a first semiconductor region by implanting an impurity of a first conductivity type into the semiconductor layer. The first semiconductor region has a first concentration of the first conductivity type. The method includes forming a first semiconductor pillar portion and a second semiconductor pillar portion by implanting an impurity of a second conductivity type into a plurality of locations of the first semiconductor region. The first semiconductor pillar portion is of the first conductivity type. The second semiconductor pillar portion has a second concentration of the second conductivity type and is adjacent to the first semiconductor pillar portion. The method includes repeating the forming of the semiconductor layer, forming of the first semiconductor region, and the first and second semiconductor pillar portions.

IPC Classes  ?

  • H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
  • H01L 29/66 - Types of semiconductor device
  • H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions

16.

DETECTION CIRCUIT AND COMMUNICATION SYSTEM

      
Application Number 17943007
Status Pending
Filing Date 2022-09-12
First Publication Date 2023-09-28
Owner
  • KABUSHIKI KAISHA TOSHIBA (Japan)
  • TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION (Japan)
Inventor Uo, Toyoaki

Abstract

According to one embodiment, there is provided a detection circuit including a first insulating element, a second insulating element, a first transmission test circuit, a second transmission test circuit, and a reception test circuit. The first transmission test circuit is connected to the first insulating element. The second transmission test circuit is connected to the second insulating element. The reception test circuit is connected to each of the first insulating element and the second insulating element to output a detection signal corresponding to a difference between a voltage of the first insulating element and a voltage of the second insulating element.

IPC Classes  ?

  • H04B 1/16 - Circuits
  • H01Q 1/38 - Structural form of radiating elements, e.g. cone, spiral, umbrella formed by a conductive layer on an insulating support
  • H04B 1/18 - Input circuits, e.g. for coupling to an antenna or a transmission line

17.

MAGNETIC DISK APPARATUS AND METHOD

      
Application Number 17943015
Status Pending
Filing Date 2022-09-12
First Publication Date 2023-09-28
Owner
  • KABUSHIKI KAISHA TOSHIBA (Japan)
  • TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION (Japan)
Inventor Ogawa, Kenji

Abstract

According to one embodiment, a magnetic disk apparatus includes a magnetic disk, a magnetic head, and a controller. The magnetic disk is provided with a track including a plurality of first sectors. The controller accesses the magnetic disk by using the magnetic head. The plurality of first sectors includes a plurality of second sectors where data segments are written and a third sector where parity and first information indicating effectiveness or ineffectiveness of protection by the parity are written.

IPC Classes  ?

  • G11B 5/012 - Recording on, or reproducing or erasing from, magnetic disks

18.

CRIMPING DETERMINATION DEVICE, CRIMPING DETERMINATION METHOD, CRIMPING DETERMINATION PROGRAM, WIRE HARNESS PROCESSING DEVICE, AND WIRE HARNESS PROCESSING METHOD

      
Application Number 18168761
Status Pending
Filing Date 2023-02-14
First Publication Date 2023-09-28
Owner Kabushiki Kaisha Toshiba (Japan)
Inventor
  • Tanaka, Akira
  • Watanabe, Masashi
  • Sato, Emi
  • Yang, Juhong

Abstract

A crimping determination device according to an embodiment includes a dropping unit, an image acquisition unit, and a control unit. The dropping unit drops a test solution to a wire harness. The wire harness includes a crimped portion in which an electric wire is crimped by a crimping terminal, a first electric wire portion in which the electric wire is exposed on a distal end side, and a second electric wire portion in which the electric wire is exposed on a proximal end side. The dropping unit drops the test solution to either one of the first electric wire portion and the second electric wire portion. The image acquisition unit acquires an image including the other one of the first electric wire portion and the second electric wire portion. The control unit determines a quality of a crimped state of the crimped portion based on the image.

IPC Classes  ?

  • G01N 15/08 - Investigating permeability, pore volume, or surface area of porous materials
  • G06T 7/00 - Image analysis

19.

PHOTODETECTOR

      
Application Number 17891799
Status Pending
Filing Date 2022-08-19
First Publication Date 2023-09-28
Owner
  • KABUSHIKI KAISHA TOSHIBA (Japan)
  • TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION (Japan)
Inventor Yasuda, Kensuke

Abstract

A photodetector according to an embodiment includes a plurality of cell regions disposed in an array, and an element isolation region provided between the cell regions, each of the cell regions including: a semiconductor layer having a first face and a second face opposite to the first face; a first semiconductor region of a first conductivity type provided in the semiconductor layer; a second semiconductor region of a second conductivity type provided between the first semiconductor region and the first face; an electrode in contact with the second semiconductor region; and a plurality of metal regions having a part surrounded by the first semiconductor region and another part surrounded by the second semiconductor region.

IPC Classes  ?

  • H01L 31/107 - Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier working in avalanche mode, e.g. avalanche photodiode
  • H01L 31/0224 - Electrodes
  • H01L 31/108 - Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier being of the Schottky type
  • G01T 1/24 - Measuring radiation intensity with semiconductor detectors

20.

ROTOR AND ROTATING ELECTRICAL MACHINE

      
Application Number 18325935
Status Pending
Filing Date 2023-05-30
First Publication Date 2023-09-28
Owner
  • KABUSHIKI KAISHA TOSHIBA (Japan)
  • TOSHIBA INFRASTRUCTURE SYSTEMS & SOLUTIONS CORPORATION (Japan)
Inventor
  • Uchida, Hidenori
  • Kano, Masaru

Abstract

According to one embodiment, a rotor includes, for each magnetic pole of a rotor iron core, first and second outer circumferential side bridge portions, and first and second inner circumferential side bridge portions. The first and second outer circumferential side bridge portions are provided such that a mutual interval is decreased from an outer circumferential side of the rotor iron core to an inner circumferential side. The first and second inner circumferential side bridge portions are provided such that a mutual interval is decreased from the outer circumferential side of the rotor iron core to the inner circumferential side, and are connected to the first and second outer circumferential side bridge portions, respectively.

IPC Classes  ?

  • H02K 1/276 - Magnets embedded in the magnetic core, e.g. interior permanent magnets [IPM]

21.

MAGNETIC DISK DEVICE AND METHOD

      
Application Number 17897062
Status Pending
Filing Date 2022-08-26
First Publication Date 2023-09-28
Owner
  • KABUSHIKI KAISHA TOSHIBA (Japan)
  • TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION (Japan)
Inventor Furuhashi, Kana

Abstract

A magnetic disk device includes a magnetic disk including a track having a plurality of sectors, a motor configured to rotate the magnetic disk, a magnetic head, and a controller. The controller is configured to perform a first read operation of reading target sectors among the sectors of the track, with the magnetic head during a first revolution of the magnetic disk, detect an off-track state of the magnetic head during the first revolution of the magnetic disk, perform a first error correction with respect to data read from the target sectors during the first read operation, and perform a second read operation of selectively reading a part of the target sectors for which the off-track state has been detected or the first error correction is unsuccessful, with the magnetic head during a second revolution of the magnetic disk.

IPC Classes  ?

  • G11B 21/10 - Track finding or aligning by moving the head
  • G11B 5/012 - Recording on, or reproducing or erasing from, magnetic disks

22.

MAGNETIC DISK DEVICE

      
Application Number 17941702
Status Pending
Filing Date 2022-09-09
First Publication Date 2023-09-28
Owner
  • KABUSHIKI KAISHA TOSHIBA (Japan)
  • TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION (Japan)
Inventor Yoshida, Susumu

Abstract

According to one embodiment, a magnetic disk device includes a magnetic disk, a magnetic head, an actuator, a first stopper, an acceleration sensor, and a controller. The magnetic head is configured to record and reproduce data on and from the magnetic disk. The actuator is configured to rotate about a rotation axis to move the magnetic head. The first stopper is configured to block the actuator in rotation to restrict the actuator from rotating about the rotation axis in a first direction. The acceleration sensor is configured to output an electric signal corresponding to applied acceleration. The controller is configured to, at a time when the actuator abuts against the first stopper, apply a first drive signal to the actuator to measure a first electric signal output from the acceleration sensor, the first drive signal being for driving the actuator in the first direction.

IPC Classes  ?

  • G11B 19/04 - Arrangements for preventing, inhibiting, or warning against, double recording on the same blank, or against other recording or reproducing malfunctions
  • G11B 5/55 - Track change, selection, or acquisition by displacement of the head
  • G11B 19/14 - Control of operating function, e.g. switching from recording to reproducing by sensing movement or position of head, e.g. means moving in correspondence with head movements

23.

SEMICONDUCTOR DEVICE

      
Application Number 17941725
Status Pending
Filing Date 2022-09-09
First Publication Date 2023-09-28
Owner
  • KABUSHIKI KAISHA TOSHIBA (Japan)
  • TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION (Japan)
Inventor
  • Kono, Hiroshi
  • Tanaka, Katsuhisa

Abstract

A semiconductor device of an embodiment includes a trench in a silicon carbide layer and extending in a first direction, a gate electrode in the trench, first, second, third and fourth silicon carbide regions disposed in the silicon carbide layer in the first direction in this order, first and third silicon carbide regions having first conductive type, second and fourth silicon carbide regions having second conductive type, fifth, sixth, seventh and eighth silicon carbide regions disposed in the silicon carbide layer in the first direction in this order above the first to fourth silicon carbide regions, fifth and seventh silicon carbide regions having first conductive type higher than first and third silicon carbide regions, sixth and eighth silicon carbide regions having second conductive type higher than second and fourth silicon carbide regions, a ninth silicon carbide region of a first conductive type above the fifth to eighth silicon carbide regions.

IPC Classes  ?

  • H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

24.

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR CIRCUIT

      
Application Number 17941756
Status Pending
Filing Date 2022-09-09
First Publication Date 2023-09-28
Owner
  • KABUSHIKI KAISHA TOSHIBA (Japan)
  • TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION (Japan)
Inventor
  • Matsudai, Tomoko
  • Iwakaji, Yoko
  • Gejo, Ryohei

Abstract

A semiconductor device according to the embodiment includes: a transistor region including a first trench, a first gate electrode provided in the first trench, a second trench, a second gate electrode provided in the second trench, a third trench, and a third gate electrode provided in the third trench; a diode region including a fifth trench and a conductive layer provided in the fifth trench; a boundary region including a fourth trench and a fourth gate electrode provided in the fourth trench, the boundary region being provided between the transistor region and the diode region; a first electrode pad electrically connected to the first gate electrode; a second electrode pad electrically connected to the second gate electrode; and a third electrode pad electrically connected to the third gate electrode and the fourth gate electrode.

IPC Classes  ?

  • H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
  • H01L 29/861 - Diodes
  • H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
  • H03K 17/567 - Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT

25.

DISK DEVICE

      
Application Number 17900473
Status Pending
Filing Date 2022-08-31
First Publication Date 2023-09-28
Owner
  • KABUSHIKI KAISHA TOSHIBA (Japan)
  • TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION (Japan)
Inventor Iwashiro, Masafumi

Abstract

A disk device includes a first controller configured to determine a first operation amount of a first actuator based on a difference between a current position and a target position of a head, a second controller configured to determine a second operation amount of a second actuator based on the difference, and a processor. The processor is configured to perform a first filtering to calculate a first filter value based on a vibration detected at multiple points in time and filter coefficients, perform a second filtering to generate a second filter value based on the vibration detected at each of the multiple points in time, and update the filter coefficients based on the second filter values and a difference between the target position and an updated position of the head.

IPC Classes  ?

  • G11B 21/08 - Track changing or selecting
  • G11B 5/012 - Recording on, or reproducing or erasing from, magnetic disks

26.

SEMICONDUCTOR DEVICE AND MOTOR DRIVE SYSTEM

      
Application Number 17901318
Status Pending
Filing Date 2022-09-01
First Publication Date 2023-09-28
Owner
  • KABUSHIKI KAISHA TOSHIBA (Japan)
  • TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION (Japan)
Inventor
  • Kobayashi, Kazuya
  • Odawara, Hiroshi

Abstract

A semiconductor device includes first to fifth terminals, an amplification circuit including a first input end connectable to the first terminal and the third terminal, a second input end connectable to the second terminal and the fourth terminal, and an output end, and a switching circuit. The switching circuit is configured to switch between a first state in which the first input end is connected to the first terminal and insulated from the third terminal and the second input end is connected to the second terminal and insulated from the fourth terminal, and a second state in which the first input end is connected to the third terminal and insulated from the first terminal and the second input end is connected to the fourth terminal and insulated from the second terminal.

IPC Classes  ?

  • H02P 23/14 - Estimation or adaptation of motor parameters, e.g. rotor time constant, flux, speed, current or voltage

27.

FET SENSOR USING ANTIOXIDANT

      
Application Number 17930415
Status Pending
Filing Date 2022-09-07
First Publication Date 2023-09-28
Owner KABUSHIKI KAISHA TOSHIBA (Japan)
Inventor
  • Sugizaki, Yoshiaki
  • Miki, Hiroko

Abstract

According to one embodiment, an FET sensor includes a sensitive film including a carbon allotrope, a liquid film disposed so as to cover the sensitive film, a source electrode and a drain electrode electrically connected to the sensitive film, and a gate electrode configured to apply an electric field to the sensitive film, wherein the liquid film comprises an antioxidant.

IPC Classes  ?

  • G01N 27/414 - Ion-sensitive or chemical field-effect transistors, i.e. ISFETS or CHEMFETS

28.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

      
Application Number 17901312
Status Pending
Filing Date 2022-09-01
First Publication Date 2023-09-28
Owner
  • KABUSHIKI KAISHA TOSHIBA (Japan)
  • TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION (Japan)
Inventor
  • Inoue, Emiko
  • Kishida, Motoya
  • Hayase, Shigeaki
  • Maeda, Kazushi

Abstract

A semiconductor device includes a semiconductor layer, a conductive film, a first insulating film, and a second insulating film. The semiconductor layer has an element region where a semiconductor element is provided and a termination region surrounding the element region. The conductive film is provided on the element region and the termination region. The first insulating film is provided on the conductive film on the termination region and a portion of the element region adjacent to the termination region. The second insulating film that is lower in resistivity than the first insulating film, and higher in resistivity than the conductive film, is provided on the first insulating film.

IPC Classes  ?

29.

ISOLATOR

      
Application Number 17901997
Status Pending
Filing Date 2022-09-02
First Publication Date 2023-09-28
Owner
  • Kabushiki Kaisha Toshiba (Japan)
  • Toshiba Electronic Devices & Storage Corporation (Japan)
Inventor
  • Imaizumi, Yusuke
  • Liu, Jia
  • Tamura, Yoshinari

Abstract

According to one embodiment, an isolator includes a first wiring board and a second wiring board. The first wiring board includes a first insulating layer including first and second principal surfaces; a first coil provided on the first principal surface; and a first pad provided on the first principal surface and electrically connected to the first coil. The second wiring board includes a second insulating layer including third and fourth principal surfaces; a second coil provided on the third principal surface; and a second pad provided on the fourth principal surface and electrically connected to the second coil. The first and second coils are arranged in such a manner as to face each other, and an external size of the second wiring board is smaller than an external size of the first wiring board.

IPC Classes  ?

  • H05K 1/16 - Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
  • H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
  • H05K 1/14 - Structural association of two or more printed circuits

30.

SECONDARY BATTERY

      
Application Number 17932410
Status Pending
Filing Date 2022-09-15
First Publication Date 2023-09-28
Owner KABUSHIKI KAISHA TOSHIBA (Japan)
Inventor Yamamoto, Kuniaki

Abstract

According to one embodiment, a secondary battery includes an outer container including long side walls and a lid, an electrode assembly including a group of electrodes and a current collecting tab and accommodated in the outer container, an output terminal, a lead including a junction opposing the lid and connected to the output terminal, a first extension portion extending from the junction along an inner surface of one of the long side walls and a second extending portion extending from the junction along an inner surface of the other long side wall, a first insulator including an inner surface engaged with the outer surface of the first extending portion, and a second insulator including an inner surface engaged with the outer surface of the second extending portion.

IPC Classes  ?

  • H01M 50/572 - Means for preventing undesired use or discharge
  • H01M 50/55 - Terminals characterised by the disposition of the terminals on the cells on the same side of the cell
  • H01M 50/536 - Electrode connections inside a battery casing characterised by the method of fixing the leads to the electrodes, e.g. by welding

31.

SECONDARY BATTERY

      
Application Number 17932422
Status Pending
Filing Date 2022-09-15
First Publication Date 2023-09-28
Owner KABUSHIKI KAISHA TOSHIBA (Japan)
Inventor Yamamoto, Kuniaki

Abstract

According to one embodiment, a secondary battery includes an outer container having a lid body, an electrode assembly including a current collecting tab and housed in the outer container, an output terminal provided in the lid body, and a lead provided between the electrode assembly and the lid body to electrically connect the current collecting tab and the output terminal. The output terminal includes a connection part that is exposed to the outside of the lid body and connectable with a connection member, an exposed part exposed to the outside of the lid body, and a through hole formed in the exposed part, and the exposed part is joined to the lead.

IPC Classes  ?

  • H01M 50/166 - Lids or covers characterised by the methods of assembling casings with lids
  • H01M 50/533 - Electrode connections inside a battery casing characterised by the shape of the leads or tabs
  • H01M 10/04 - Construction or manufacture in general
  • H01M 50/566 - Terminals characterised by their manufacturing process by welding, soldering or brazing
  • H01M 50/103 - Primary casings, jackets or wrappings of a single cell or a single battery characterised by their shape or physical structure prismatic or rectangular

32.

SECONDARY BATTERY

      
Application Number 17932415
Status Pending
Filing Date 2022-09-15
First Publication Date 2023-09-28
Owner KABUSHIKI KAISHA TOSHIBA (Japan)
Inventor Yamamoto, Kuniaki

Abstract

According to one embodiment, a secondary battery includes an outer container including a lid body, an electrode assembly, an output terminal provided in the lid and including a first external thread portion and a lead provided between the electrode assembly and the lid inside the outer container, and the lead includes a plate-shaped junction opposing the lid body and an internal thread portion provided to penetrate the junction, and the first external thread portion of the output terminal is threaded into the internal thread portion through the lid to be electrically connected to the junction.

IPC Classes  ?

  • H01M 50/567 - Terminals characterised by their manufacturing process by fixing means, e.g. screws, rivets or bolts
  • H01M 50/55 - Terminals characterised by the disposition of the terminals on the cells on the same side of the cell
  • H01M 50/553 - Terminals adapted for prismatic, pouch or rectangular cells
  • H01M 50/536 - Electrode connections inside a battery casing characterised by the method of fixing the leads to the electrodes, e.g. by welding

33.

COLD STORAGE MATERIAL, COLD STORAGE MATERIAL PARTICLE, GRANULATED PARTICLE, COLD STORAGE DEVICE, REFRIGERATOR, CRYOPUMP, SUPERCONDUCTING MAGNET, NUCLEAR MAGNETIC RESONANCE IMAGING APPARATUS, NUCLEAR MAGNETIC RESONANCE APPARATUS, MAGNETIC FIELD APPLICATION TYPE SINGLE CRYSTAL PULLING APPARATUS, AND HELIUM RE-CONDENSING DEVICE

      
Application Number 18323288
Status Pending
Filing Date 2023-05-24
First Publication Date 2023-09-28
Owner
  • KABUSHIKI KAISHA TOSHIBA (Japan)
  • TOSHIBA MATERIALS CO., LTD. (Japan)
Inventor
  • Kawamoto, Takahiro
  • Usui, Daichi
  • Hiramatsu, Ryosuke
  • Kondo, Hiroyasu
  • Taguchi, Seina

Abstract

A cold storage material of an embodiment includes a rare earth oxysulfide containing at least one rare earth element selected from the group consisting of Y, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu, and a first group element of 0.001 atom % or more and 10 atom % or less, in which a maximum value of volume specific heat in a temperature range of 2 K or more and 10 K or less is 0.5 J/(cm3·K) or more.

IPC Classes  ?

  • C09K 5/14 - Solid materials, e.g. powdery or granular
  • C01F 17/294 - Oxysulfides
  • G01R 33/38 - Systems for generation, homogenisation or stabilisation of the main or gradient magnetic field
  • F25B 9/14 - Compression machines, plants or systems, in which the refrigerant is air or other gas of low boiling point characterised by the cycle used, e.g. Stirling cycle
  • H01F 6/04 - Cooling
  • F17C 6/00 - Methods or apparatus for filling vessels not under pressure with liquefied or solidified gases

34.

MAGNETIC DISK APPARATUS AND METHOD

      
Application Number 17903905
Status Pending
Filing Date 2022-09-06
First Publication Date 2023-09-28
Owner
  • KABUSHIKI KAISHA TOSHIBA (Japan)
  • TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION (Japan)
Inventor Sogabe, Keigo

Abstract

According to a magnetic disk apparatus of one embodiment, threshold voltages of memory cell transistors of a flash memory are set to a first section for a first value or to a second section for a second value. The second section is on a lower voltage side than the first section. The controller performs bit inversion of second data held in a volatile memory and writes the second data onto the flash memory when a power loss occurs while the second data corresponds to third data in which a number of the first values is larger than that of the second values. The controller writes the second data onto the flash memory without bit inversion when a power loss occurs while the second data corresponds to fourth data. The fourth data is data in which a number of the first values is smaller than that of the second values.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers
  • G06F 12/02 - Addressing or allocation; Relocation
  • G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
  • G11C 11/401 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
  • G11C 16/06 - Auxiliary circuits, e.g. for writing into memory

35.

FLUORESCENT RARE EARTH COMPLEX AND SECURITY MEDIUM USING THE SAME

      
Application Number 18326054
Status Pending
Filing Date 2023-05-31
First Publication Date 2023-09-28
Owner
  • KABUSHIKI KAISHA TOSHIBA (Japan)
  • TOSHIBA INFRASTRUCTURE SYSTEMS & SOLUTIONS CORPORATION (Japan)
Inventor
  • Iwanaga, Hiroki
  • Miyazaki, Kenji

Abstract

The embodiments provide a fluorescent rare earth complex having strong emission intensity and excellent durability, and also provide a security medium using the complex. The rare earth complex according to the embodiment comprises a rare earth ion, a diphosphine dioxide ligand and a β-diketone ligand wherein two phosphorus atoms contained in the diphosphine dioxide ligand individually have substituents different from each other.

IPC Classes  ?

  • C09K 11/06 - Luminescent, e.g. electroluminescent, chemiluminescent, materials containing organic luminescent materials
  • F21K 2/00 - Non-electric light sources using luminescence; Light sources using electrochemiluminescence
  • C07F 9/53 - Organo-phosphine oxides; Organo-phosphine sulfides
  • C07F 5/00 - Compounds containing elements of Groups 3 or 13 of the Periodic System

36.

SEMICONDUCTOR DEVICE

      
Application Number 17889971
Status Pending
Filing Date 2022-08-17
First Publication Date 2023-09-28
Owner
  • KABUSHIKI KAISHA TOSHIBA (Japan)
  • TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION (Japan)
Inventor
  • Asaba, Shunsuke
  • Kono, Hiroshi

Abstract

A semiconductor device includes a first semiconductor layer of a first conductivity type, second to fifth semiconductor layers of a second conductivity type, and first and second electrodes. The first semiconductor layer is provided between the first and second electrodes, and includes a termination region. The second semiconductor layer is provided between the first semiconductor layer and the second electrode, and has a first thickness in a first direction from the first electrode toward the second electrode. The third to fifth semiconductor layers are provided in the termination region. The third semiconductor layer surrounds the second semiconductor layer, and has a second thickness in the first direction. The fourth semiconductor layer surrounds the third semiconductor layer, and has a third thickness in the first direction. The second thickness is greater than the first and third thicknesses. The fifth semiconductor layer is connected to the second to fourth semiconductor layers.

IPC Classes  ?

  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

37.

CAPACITOR AND ETCHING METHOD

      
Application Number 18315123
Status Pending
Filing Date 2023-05-10
First Publication Date 2023-09-28
Owner KABUSHIKI KAISHA TOSHIBA (Japan)
Inventor
  • Higuchi, Kazuhito
  • Shimokawa, Kazuo
  • Obata, Susumu
  • Sano, Mitsuo

Abstract

According to an embodiment, a capacitor includes a conductive substrate, a conductive layer, a dielectric layer therebetween, and first and second internal electrodes. The substrate has first and second main surfaces. One partial region of the first main surface is provided with first recesses. A region of the second surface corresponding to a combination of the one partial region and another partial region is provided with second recesses. The conductive layer covers the main surfaces and side walls and bottom surfaces of the recesses. The first internal electrode is provided on the one partial region and electrically connected to the conductive layer. The second internal electrode is provided on the another partial region and electrically connected to the substrate.

IPC Classes  ?

  • H01G 4/228 - Terminals
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01G 4/30 - Stacked capacitors
  • H01G 4/012 - Form of non-self-supporting electrodes
  • H01G 4/33 - Thin- or thick-film capacitors
  • H01G 4/38 - Multiple capacitors, i.e. structural combinations of fixed capacitors

38.

LASER WELDING METHOD

      
Application Number 18168471
Status Pending
Filing Date 2023-02-13
First Publication Date 2023-09-28
Owner
  • Kabushiki Kaisha Toshiba (Japan)
  • Toshiba Electronic Devices & Storage Corporation (Japan)
Inventor
  • Masuda, Lisa
  • Togawa, Ryuichi
  • Obara, Takashi

Abstract

A laser welding method according to an embodiment includes a preparation process and a welding process. The preparation process includes preparing a temporarily-welded member that includes multiple connection portions by temporarily welding a second member to a first member. The welding process includes welding the second member to the first member by irradiating a laser beam on the temporarily-welded member. In the welding process, a first process is performed, after which a second process is performed. The first process includes irradiating a laser beam from a prescribed position to a second connection portion, wherein the second connection portion is adjacent to a first connection portion, and the prescribed position is between the first connection portion and the second connection portion. The second process includes irradiating a laser beam from the first connection portion to the prescribed position.

IPC Classes  ?

39.

OPTICAL INSPECTION METHOD, NON-TRANSITORY STORAGE MEDIUM STORING OPTICAL INSPECTION PROGRAM, PROCESSING DEVICE, AND OPTICAL INSPECTION APPARATUS

      
Application Number 17823957
Status Pending
Filing Date 2022-09-01
First Publication Date 2023-09-28
Owner KABUSHIKI KAISHA TOSHIBA (Japan)
Inventor
  • Ohno, Hiroshi
  • Kano, Hiroya
  • Okano, Hideaki
  • Kamikawa, Takahiro

Abstract

According to the embodiment, an optical inspection method includes: acquiring an image by capturing the image, using light from a surface of an object, which passes through a wavelength selection portion configured to selectively pass light components of a plurality of predetermined wavelengths different from each other, the image sensor including color channels configured to discriminately receive the light components of the plurality of predetermined wavelengths, performing color count estimation processing configured to estimate the number of colors based on the intensity ratio of the color channels that have received the light in each pixel of the image, and performing scattered light distribution identification processing configured to identify a scattered light distribution as BRDF from the surface of the object based on the number of colors or surface state identification processing configured to identify a state of the surface of the object based on the number of colors.

IPC Classes  ?

  • G01N 21/47 - Scattering, i.e. diffuse reflection
  • G01N 21/27 - Colour; Spectral properties, i.e. comparison of effect of material on the light at two or more different wavelengths or wavelength bands using photo-electric detection
  • G01N 21/25 - Colour; Spectral properties, i.e. comparison of effect of material on the light at two or more different wavelengths or wavelength bands

40.

KEY MANAGEMENT DEVICE, QUANTUM CRYPTOGRAPHY COMMUNICATION SYSTEM, AND COMPUTER PROGRAM PRODUCT

      
Application Number 17821281
Status Pending
Filing Date 2022-08-22
First Publication Date 2023-09-28
Owner KABUSHIKI KAISHA TOSHIBA (Japan)
Inventor
  • Takahashi, Ririka
  • Tanizawa, Yoshimichi

Abstract

A key management device according to an embodiment includes one or more hardware processors configured to function as a determination unit, a generation unit, and a supply unit. The determination unit determines a type of request data requested by a request message transmitted from an application that performs encrypted data communication. The generation unit generates a response message including at least one of a random number and an encryption key shared by quantum key distribution (QKD) via a communication network according to a type of the request data. The supply unit supplies the response message to the application.

IPC Classes  ?

41.

SEMICONDUCTOR DEVICE

      
Application Number 17903894
Status Pending
Filing Date 2022-09-06
First Publication Date 2023-09-28
Owner
  • Kabushiki Kaisha Toshiba (Japan)
  • Toshiba Electronic Devices & Storage Corporation (Japan)
Inventor Shiraishi, Tatsuya

Abstract

A semiconductor device of an embodiment includes a first electrode, a first semiconductor layer of first conductivity type provided on the first electrode; a second semiconductor layer of first conductivity type provided on the first semiconductor layer; a first semiconductor region of second conductivity type provided on the second semiconductor layer; a first insulating film provided in a trench reaching the second semiconductor layer from above the first semiconductor region, a dielectric constant of an upper part of the first insulating film being higher than a dielectric constant of a lower part of the first insulating film; a second electrode provided in the trench, the second electrode facing the first semiconductor region; and a second insulating film provided between the second electrode and the first semiconductor region, the second insulating film being provided on the first insulating film in the trench.

IPC Classes  ?

  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 29/40 - Electrodes
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched

42.

REFERENCE VOLTAGE GENERATING CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE

      
Application Number 17903617
Status Pending
Filing Date 2022-09-06
First Publication Date 2023-09-28
Owner
  • Kabushiki Kaisha Toshiba (Japan)
  • Toshiba Electronic Devices & Storage Corporation (Japan)
Inventor Hirabayashi, Osamu

Abstract

A reference voltage generating circuit according to an embodiment includes: an original reference voltage generating unit that generates an original reference voltage; and a reference voltage correcting unit that decreases the original reference voltage as the temperature rises and outputs the original reference voltage as a reference voltage to a sense amplifier, and thus it is possible to perform highly reliable operation while the influence of the temperature is reduced.

IPC Classes  ?

43.

SEMICONDUCTOR DEVICE

      
Application Number 17903846
Status Pending
Filing Date 2022-09-06
First Publication Date 2023-09-28
Owner
  • KABUSHIKI KAISHA TOSHIBA (Japan)
  • TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION (Japan)
Inventor Tanaka, Atsushi

Abstract

According to one embodiment, a semiconductor device includes: a first frame; a first chip on the first frame; a second frame spaced apart from the first frame in a first direction; a second chip on the second frame; and a first joint terminal above the second chip. The first frame includes a first terminal portion extending toward the second frame. The first joint terminal includes a second terminal portion extending toward the first frame. The second terminal portion includes first and second projecting portions each of which projects toward the first frame and which are spaced apart from each other in a second direction. An end portion of the first projecting portion and an end portion of the second projecting portion are each joined on the first terminal portion.

IPC Classes  ?

44.

DISK DEVICE AND CONTROL METHOD

      
Application Number 17903845
Status Pending
Filing Date 2022-09-06
First Publication Date 2023-09-28
Owner
  • Kabushiki Kaisha Toshiba (Japan)
  • Toshiba Electronic Devices & Storage Corporation (Japan)
Inventor Iida, Ikuko

Abstract

According to one embodiment, a disk device includes a magnetic disk and a control circuit. The magnetic disk includes a shingled magnetic recording (SMR) region where data is recorded such that adjacent tracks are partially overlapped with each other by SMR. The control circuit writes, at a predetermined timing, dummy data to a location on the magnetic disk. The location is located after a position indicated by a write pointer. The control circuit executes scan processing after the writing of the dummy data.

IPC Classes  ?

  • G11B 5/02 - Recording, reproducing or erasing methods; Read, write or erase circuits therefor
  • G11B 27/34 - Indicating arrangements

45.

SEMICONDUCTOR DEVICE

      
Application Number 17870045
Status Pending
Filing Date 2022-07-21
First Publication Date 2023-09-28
Owner
  • Kabushiki Kaisha Toshiba (Japan)
  • Toshiba Electronic Devices & Storage Corporation (Japan)
Inventor Fujino, Yuhki

Abstract

According to one embodiment, a semiconductor device includes first and second electrodes, first to third semiconductor regions a plurality of conductive parts, and a gate electrode. The first semiconductor region is located on the first electrode and electrically connected with the first electrode. The conductive parts are located in the first semiconductor region with insulating parts interposed. The second semiconductor region is located on a portion of the first semiconductor region. The third semiconductor region is located on a portion of the second semiconductor region. The gate electrode is located on the second semiconductor region with a gate insulating layer interposed. The second electrode is located on the second and third semiconductor regions, and the gate electrode and electrically connected with the second and third semiconductor regions, and conductive parts.

IPC Classes  ?

  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H01L 29/40 - Electrodes

46.

SEMICONDUCTOR DEVICE

      
Application Number 17901890
Status Pending
Filing Date 2022-09-02
First Publication Date 2023-09-28
Owner
  • Kabushiki Kaisha Toshiba (Japan)
  • Toshiba Electronic Devices & Storage Corporation (Japan)
Inventor Matsushita, Kenichi

Abstract

A semiconductor device includes a first electrode, a first semiconductor region, a second semiconductor region, a third semiconductor region, a second electrode, a conductive part, and a fourth semiconductor region. The first semiconductor region is located above the first electrode. The second semiconductor region is located on the first semiconductor region. The third semiconductor region is located on the second semiconductor region. The second electrode is located on the second and third semiconductor regions. The second electrode is electrically connected with the second and third semiconductor regions. The conductive part includes a first conductive region and a second conductive region. The first conductive region faces the first to third semiconductor regions via an insulating film. The second conductive region is located around the second electrode. The fourth semiconductor region is located around the second semiconductor region. The fourth semiconductor region is electrically connected with the second semiconductor region.

IPC Classes  ?

  • H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect

47.

SEMICONDUCTOR DEVICE

      
Application Number 17942562
Status Pending
Filing Date 2022-09-12
First Publication Date 2023-09-28
Owner
  • KABUSHIKI KAISHA TOSHIBA (Japan)
  • TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION (Japan)
Inventor Sugiyama, Toru

Abstract

A semiconductor device includes a substrate, a first transistor of a depletion type, a second transistor of an enhancement type, and a gate control circuit. The first and second transistors are provided on the substrate and each include a channel region of a first conductivity type. The first and second transistors are connected in series. The channel region of the first transistor includes a nitride semiconductor. The second transistor operates via an inversion layer of a second conductivity type induced in the channel region thereof. The gate control circuit is connected to a gate electrode of the second transistor. The substrate includes a gate terminal and a power supply terminal. The gate terminal is electrically connected to a gate electrode of the first transistor. The power supply terminal is electrically connected to a connection part between the first transistor and the second transistor.

IPC Classes  ?

  • H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
  • H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
  • H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices

48.

SEMICONDUCTOR DEVICE

      
Application Number 17901632
Status Pending
Filing Date 2022-09-01
First Publication Date 2023-09-28
Owner
  • KABUSHIKI KAISHA TOSHIBA (Japan)
  • TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION (Japan)
Inventor Yoshikawa, Daiki

Abstract

A semiconductor device includes first to third electrodes, first to fifth semiconductor regions, and a first contact region. The third semiconductor region is located on the second semiconductor region. The fourth semiconductor region is located on a portion of the third semiconductor region. The third electrode extends in a second direction and faces the third semiconductor region via a first insulating film in a third direction. The first contact region is located on a portion of the third semiconductor region and is arranged with the third electrode in the third direction. The fifth semiconductor region includes a first portion and a second portion. The first portion is arranged in the third direction with a boundary portion between the first insulating film and the third semiconductor region between the second semiconductor region and the fourth semiconductor region. The second portion is arranged in the second direction with the boundary portion.

IPC Classes  ?

  • H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched

49.

MAGNETIC DISK APPARATUS AND METHOD

      
Application Number 17931679
Status Pending
Filing Date 2022-09-13
First Publication Date 2023-09-28
Owner
  • KABUSHIKI KAISHA TOSHIBA (Japan)
  • TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION (Japan)
Inventor Tsukahara, Wataru

Abstract

According to embodiments, a magnetic disk apparatus includes a magnetic disk, a magnetic head, a temperature sensor, and a controller. The magnetic disk has formed therein a servo sector in which servo data including a first post code and a second post code is recorded. In the positioning of the magnetic head, the controller performs a correction using a third post code that is based on the first and second post codes and a first temperature detected by the temperature sensor.

IPC Classes  ?

50.

INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, AND PACKAGE HANDLING SYSTEM

      
Application Number 18173728
Status Pending
Filing Date 2023-02-23
First Publication Date 2023-09-28
Owner
  • Kabushiki Kaisha Toshiba (Japan)
  • Toshiba Infrastructure Systems & Solutions Corporation (Japan)
Inventor
  • Sugiyama, Masaaki
  • Shibata, Masamitsu
  • Nakamata, Hirokazu
  • Matsumura, Atsushi
  • Otsuru, Yoshihide

Abstract

An information processing device for controlling a package handling system includes a first interface connected to a first logistics equipment, a second interface connected to a second logistics equipment, and a processor. The processor acquires flow rate data output by sensors of the first logistics equipment via the first interface, changes a format of the acquired flow rate data to a common format, acquires equipment information regarding the second logistics equipment via the second interface, changes a format of the equipment information to the common format, and generates a display screen showing flow rates at different points of the first logistics equipment, the equipment information, and a congestion state of the system, update the display screen after performing a simulation of the system, and issue a control signal in the first or second format to apply a change in an operating characteristic of the first or second logistics equipment.

IPC Classes  ?

  • G05B 19/418 - Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control (DNC), flexible manufacturing systems (FMS), integrated manufacturing systems (IMS), computer integrated manufacturing (CIM)
  • G05B 13/04 - Adaptive control systems, i.e. systems automatically adjusting themselves to have a performance which is optimum according to some preassigned criterion electric involving the use of models or simulators
  • G05B 19/042 - Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors

51.

ELECTROLYTIC DEVICE AND METHOD OF DRIVING ELECTROLYTIC DEVICE

      
Application Number 17821858
Status Pending
Filing Date 2022-08-24
First Publication Date 2023-09-28
Owner KABUSHIKI KAISHA TOSHIBA (Japan)
Inventor
  • Yamagiwa, Masakazu
  • Ono, Akihiko
  • Kudo, Yuki
  • Kiyota, Yasuhiro
  • Kofuji, Yusuke
  • Kitagawa, Ryota
  • Mikoshiba, Satoshi

Abstract

An electrolytic device, includes: an electrolysis cell including: a cathode; an anode; a cathode flow path facing the cathode; and an anode flow path facing the anode; a tank including: a first room; a second room; and an opening connecting the first and second rooms, the first and second rooms store a liquid containing at least one ion, the tank forms a level difference so that the first liquid level of the liquid in the first room is higher to the bottom of the second room than the second liquid level of the liquid in the second room, and thus cause an ion in the liquid to move from the first to the second room through the opening; a first flow path connecting an outlet of the cathode flow path and the first room; and a second flow path connecting the second room and an outlet of the anode flow path.

IPC Classes  ?

  • C25B 9/19 - Cells comprising dimensionally-stable non-movable electrodes; Assemblies of constructional parts thereof with diaphragms
  • C25B 1/23 - Carbon monoxide or syngas
  • C25B 3/26 - Reduction of carbon dioxide
  • C25B 1/27 - Ammonia
  • C25B 15/08 - Supplying or removing reactants or electrolytes; Regeneration of electrolytes

52.

FRAME SYNCHRONIZATION APPARATUS

      
Application Number 18310695
Status Pending
Filing Date 2023-05-02
First Publication Date 2023-09-28
Owner
  • KABUSHIKI KAISHA TOSHIBA (Japan)
  • Toshiba Infrastructure Systems & Solutions Corporation (Japan)
Inventor
  • Sugawara, Yukihiro
  • Shiratori, Masashi
  • Iwami, Keita

Abstract

A frame synchronization apparatus according to an embodiment includes a reception unit, a frame memory, a time generation unit, a reception time acquisition unit, a timestamp acquisition unit, and a control unit. The reception unit is configured to receive packet data including video data and a timestamp. The frame memory is configured to store the packet data. The time generation unit is configured to generate a time based on a reference synchronization signal. The reception time acquisition unit is configured to acquire a reception time of packet data satisfying a condition based on the time. The timestamp acquisition unit is configured to acquire a timestamp from the packet data satisfying the condition. The control unit is configured to read packet data from the frame memory in accordance with a variation in a difference between the reception time and a time indicated by the timestamp.

IPC Classes  ?

53.

CHARGING SYSTEM

      
Application Number 17891975
Status Pending
Filing Date 2022-08-19
First Publication Date 2023-09-28
Owner KABUSHIKI KAISHA TOSHIBA (Japan)
Inventor
  • Ogawa, Kenichirou
  • Shijo, Tetsu
  • Lin, Qiang
  • Kanekiyo, Yasuhiro

Abstract

According to one embodiment, a charging system charges a secondary battery provided in a mobile body. The charging system includes a controller which selects one of a first charge mode which charges the secondary battery by simulating a synchronous generator and a second charge mode which charges the secondary battery without simulating the synchronous generator, and a charger which charges the secondary battery by an operation corresponding to the first charge mode or the second charge mode selected by the controller.

IPC Classes  ?

  • B60L 53/10 - Methods of charging batteries, specially adapted for electric vehicles; Charging stations or on-board charging equipment therefor; Exchange of energy storage elements in electric vehicles characterised by the energy transfer between the charging station and the vehicle
  • B60L 53/50 - Charging stations characterised by energy-storage or power-generation means
  • B60L 53/62 - Monitoring or controlling charging stations in response to charging parameters, e.g. current, voltage or electrical charge
  • B60L 53/20 - Methods of charging batteries, specially adapted for electric vehicles; Charging stations or on-board charging equipment therefor; Exchange of energy storage elements in electric vehicles characterised by converters located in the vehicle

54.

TRANSMITTER DEVICE, RECEIVER DEVICE, TRANSMITTING METHOD, AND RECEIVING METHOD

      
Application Number 17939612
Status Pending
Filing Date 2022-09-07
First Publication Date 2023-09-28
Owner
  • KABUSHIKI KAISHA TOSHIBA (Japan)
  • TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION (Japan)
Inventor Kim, Taewon

Abstract

According to one embodiment, a transmitter device is configured to transmit to a receiver device including input and output terminals first setting data specifying input and output functions of the input and output terminals. The first setting data comprises first data common to the input and output terminals and second data inherent to each of the input and output terminals.

IPC Classes  ?

  • G06F 13/20 - Handling requests for interconnection or transfer for access to input/output bus

55.

SENSOR ATTACHMENT/DETACHMENT DEVICE, SENSOR ATTACHMENT/DETACHMENT SYSTEM, SENSOR ATTACHMENT METHOD AND SENSOR DETACHMENT METHOD

      
Application Number 17823873
Status Pending
Filing Date 2022-08-31
First Publication Date 2023-09-28
Owner KABUSHIKI KAISHA TOSHIBA (Japan)
Inventor
  • Watabe, Kazuo
  • Ueno, Keisuke
  • Takamine, Hidefumi
  • Li, Yongfang
  • Usui, Takashi
  • Hirokawa, Junko
  • Ueda, Yuki
  • Kugimiya, Tetsuya

Abstract

According to one embodiment, a sensor attachment/detachment device of the embodiment includes a sensor, a bonding member, a support portion, and a release execution portion. The bonding member is bonded to a first surface of the sensor and has a function of decreasing an adhesive force. The support portion can support the sensor by directly contacting a second surface of the sensor or via another functional portion. The release execution portion performs a process of releasing the bonding member from the object by decreasing the adhesive force of the bonding member after the sensor is attached to the object by the bonding member.

IPC Classes  ?

  • B23B 7/06 - Automatic or semi-automatic machines for turning of stock with sliding headstock
  • B23B 7/12 - Automatic or semi-automatic machines for turning of workpieces

56.

DISK DEVICE

      
Application Number 17941718
Status Pending
Filing Date 2022-09-09
First Publication Date 2023-09-28
Owner
  • KABUSHIKI KAISHA TOSHIBA (Japan)
  • TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION (Japan)
Inventor
  • Toukairin, Kouichi
  • Mizuochi, Kenji
  • Kuribara, Hirofumi
  • Minami, Hiroshi
  • Kato, Yasuhiko
  • Kinugawa, Yuya

Abstract

According to one embodiment, a disk device includes a magnetic disk and a rotary unit. The magnetic disk is rotatable about a first rotation axis extending in the first direction. The rotary unit includes a rotary member, a bearing, and a first filter. The bearing contains a lubricant and rotatably supports the rotary member about a second rotation axis. The first filter captures at least one component contained in the lubricant. The rotary member is provided with a hole and a first communication port. The hole extends along the second rotation axis to accommodate the bearing. The first communication port extends in a direction intersecting the second rotation axis to allow the hole to be in communication with an outside of the rotary member. The first filter is disposed in the first communication port or covers the first communication port.

IPC Classes  ?

  • G11B 19/20 - Driving; Starting; Stopping; Control thereof
  • G11B 25/04 - Apparatus characterised by the shape of record carrier employed but not specific to the method of recording or reproducing using flat record carriers, e.g. disc, card

57.

DRIVER CIRCUIT AND POWER CONVERSION SYSTEM

      
Application Number 17903793
Status Pending
Filing Date 2022-09-06
First Publication Date 2023-09-28
Owner
  • KABUSHIKI KAISHA TOSHIBA (Japan)
  • TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION (Japan)
Inventor Yamanaka, Yuji

Abstract

A driver circuit includes a drive circuit, a monitoring circuit, and a control circuit. The drive circuit includes a first current source and drives a switching element when the first current source is connected to a control terminal of the switching element. The monitoring circuit monitors a period of time from a start to an end of a change in a voltage drop across the switching element. The control circuit controls a current value of the first current source based on the monitored period of time such that a slew rate of the voltage drop across the switching element approaches a target value.

IPC Classes  ?

  • H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
  • H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion

58.

MAGNETIC DISK DEVICE

      
Application Number 17903785
Status Pending
Filing Date 2022-09-06
First Publication Date 2023-09-28
Owner
  • Kabushiki Kaisha Toshiba (Japan)
  • Toshiba Electronic Devices & Storage Corporation (Japan)
Inventor
  • Kondo, Yosuke
  • Furuhashi, Kana
  • Takada, Kazuya
  • Dunn, Eric R.

Abstract

According to an embodiment, each of a plurality of controller chips included in a magnetic disk device includes a buffer control circuit and an arbitration circuit, and controls a corresponding one of a plurality of actuator systems. The first controller chip is connected to a buffer memory via the buffer control circuit included in the first controller chip, and is connected to the second controller chip. The second controller chip is connected to the first controller chip and the third controller chip. The arbitration circuit included in the second controller chip performs arbitration between data transfer between the third controller chip and the first controller chip and data transfer between the first controller chip and an actuator system controlled by the second controller chip among the plurality of actuator systems.

IPC Classes  ?

  • G11B 5/012 - Recording on, or reproducing or erasing from, magnetic disks

59.

MAGNETIC DISK DEVICE AND CONTROL METHOD OF MAGNETIC DISK DEVICE

      
Application Number 17931707
Status Pending
Filing Date 2022-09-13
First Publication Date 2023-09-28
Owner
  • KABUSHIKI KAISHA TOSHIBA (Japan)
  • TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION (Japan)
Inventor Watanabe, Toru

Abstract

A magnetic disk device of an embodiment includes: a head structure including at least one reproducing head and main magnetic pole gap installation portion behind a flying slider and including at least two thermal actuators; and a control unit that can independently control the thermal actuators and that sets spacing of the reproducing head and the main magnetic pole gap installation portion with respect to a recording medium by setting a rotational speed at the time of contact, which rotational speed is a rotational speed of the recording medium, to be lower than a normal rotational speed when the reproducing head and the main magnetic pole gap installation portion are brought into contact with the recording medium.

IPC Classes  ?

  • G11B 5/127 - Structure or manufacture of heads, e.g. inductive
  • G11B 5/60 - Fluid-dynamic spacing of heads from record carriers

60.

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

      
Application Number 17929419
Status Pending
Filing Date 2022-09-02
First Publication Date 2023-09-28
Owner KABUSHIKI KAISHA TOSHIBA (Japan)
Inventor Shimizu, Tatsuo

Abstract

A method for manufacturing a semiconductor device according to an embodiment includes forming a first mask material having a first opening on a surface of a silicon carbide layer, performing first ion implantation of forming a first carbon region by implanting carbon (C) into the silicon carbide layer using the first mask material as a mask, forming, on the surface of the silicon carbide layer, a second mask material in which both end portions in a first direction parallel to the surface have second openings disposed inside both end portions in the first direction of the first carbon region, performing second ion implantation of forming a first impurity region by implanting a first impurity into the silicon carbide layer using the second mask material as a mask, and performing heat treatment at 1600° C. or higher.

IPC Classes  ?

  • H01L 21/266 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation using masks
  • H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation

61.

SEMICONDUCTOR DEVICE

      
Application Number 17931508
Status Pending
Filing Date 2022-09-12
First Publication Date 2023-09-28
Owner
  • Kabushiki Kaisha Toshiba (Japan)
  • Toshiba Electronic Devices & Storage Corporation (Japan)
Inventor
  • Fuse, Kaori
  • Kawamura, Keiko
  • Matsudai, Tomoko
  • Iwakaji, Yoko
  • Motai, Takako
  • Itokazu, Hiroko

Abstract

A semiconductor device includes a semiconductor part, first to fourth electrodes, and first and second insulating film. The first and second electrodes are provided on back and front surfaces of the semiconductor part, respectively. The third and fourth electrodes each extend into the semiconductor device form the front surface side. The third and fourth electrodes are electrically insulated from the semiconductor part by insulating films. The semiconductor part includes first to fourth layers. The first layer of a first conductivity type extends between the first and second electrodes. The second layer of a second conductivity type is provided between the first layer and the second electrode. The third layer of the second conductivity type is partially provided between the second layer and the second electrode. The fourth layer of the first conductivity type is provided in the second layer. The fourth layer is apart from the third layer.

IPC Classes  ?

  • H01L 29/861 - Diodes
  • H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
  • H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect

62.

SEMICONDUCTOR DEVICE

      
Application Number 17939025
Status Pending
Filing Date 2022-09-07
First Publication Date 2023-09-28
Owner
  • Kabushiki Kaisha Toshiba (Japan)
  • Toshiba Electronic Devices & Storage Corporation (Japan)
Inventor
  • Minamikawa, Kazuki
  • Yoshikawa, Daiki
  • Yasuhara, Norio
  • Nakamura, Kazutoshi

Abstract

A semiconductor device includes first and second electrodes, a semiconductor part, a structure body, and an insulating part. The semiconductor part includes first to fifth semiconductor regions. The structure body includes a gate part and a dummy part. The gate part includes at least one gate electrode. The dummy part includes at least two dummy electrodes. The gate part and the dummy part are alternately arranged. The insulating part is located between the gate electrode and the semiconductor part. The gate part is located in the fourth semiconductor region. A first potential is applied to the second electrode. A second potential that is greater than the first potential is applied to the gate electrode. A third potential that is greater than the first potential is applied to the dummy electrode located at a position next to the gate part.

IPC Classes  ?

  • H01L 29/40 - Electrodes
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect

63.

ELECTRONIC APPROVAL SYSTEM, ELECTRONIC APPROVAL SERVER, AND COMPUTER-READABLE STORAGE MEDIUM

      
Application Number 18174540
Status Pending
Filing Date 2023-02-24
First Publication Date 2023-09-28
Owner
  • KABUSHIKI KAISHA TOSHIBA (Japan)
  • Toshiba Infrastructure Systems & Solutions Corporation (Japan)
Inventor Toshimitsu, Kiyoshi

Abstract

According to an embodiment, an electronic approval system comprising at least one electronic approval device and an electronic approval server. The electronic approval device includes a biometric authentication unit and a security chip. The biometric authentication unit performs biometric authentication. The security chip generates reliability confirmation information using a private key stored in advance if a result of the biometric authentication is normal, and transmits the reliability confirmation information to the electronic approval server via the information processing device. The electronic approval server includes a processor. The processor stores an electronic approval record indicating that approval has been successfully performed in the electronic approval device based on a public key corresponding to the private key and the reliability confirmation information.

IPC Classes  ?

  • H04L 9/32 - Arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system
  • H04L 9/08 - Key distribution

64.

SEMICONDUCTOR DEVICE

      
Application Number 17902610
Status Pending
Filing Date 2022-09-02
First Publication Date 2023-09-28
Owner
  • KABUSHIKI KAISHA TOSHIBA (Japan)
  • TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION (Japan)
Inventor
  • Ogawa, Kodai
  • Ishitani, Hiroshi

Abstract

A semiconductor device according to an embodiment includes: an element region; and an outer peripheral region surrounding the element region, the outer peripheral region including a semiconductor layer having a first face and a second face opposite to the first face, a first annular conductor provided on a side of the first face with respect to the semiconductor layer and surrounding the element region, a second annular conductor provided on the side of the first face with respect to the semiconductor layer and surrounding the first annular conductor, and at least one first connection conductor provided between the first annular conductor and the second annular conductor and connected to the first annular conductor and the second annular conductor.

IPC Classes  ?

  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 23/58 - Structural electrical arrangements for semiconductor devices not otherwise provided for

65.

ANOMALY DETECTION SYSTEM, METHOD AND PROGRAM, AND DISTRIBUTED CO-SIMULATION SYSTEM

      
Application Number 17932638
Status Pending
Filing Date 2022-09-15
First Publication Date 2023-09-28
Owner
  • KABUSHIKI KAISHA TOSHIBA (Japan)
  • Toshiba Digital Solutions Corporation (Japan)
Inventor
  • Araki, Dai
  • Kitahara, Hirotaka
  • Takahashi, Katsumi
  • Nemoto, Masayuki

Abstract

An anomaly detection system according to an embodiment is an anomaly detection system that executes anomaly detection of each of one or a plurality of simulators by using a controller. The controller causes each simulator to start a process of simulation, to transmit to the controller an existence notification indicative of existence of the simulator, at a predetermined cycle until an end of the process of simulation, and to transmit to the controller an end notification indicative of an end of the process if the process ends; determines that the simulator that is a transmission source of the existence notification is normal; determines that the process of the simulator that is a transmission source of the end notification ends, upon receiving the end notification; and detects that an anomaly occurs in the simulator.

IPC Classes  ?

  • G06F 30/20 - Design optimisation, verification or simulation
  • G06F 11/07 - Responding to the occurrence of a fault, e.g. fault tolerance

66.

SEMICONDUCTOR DEVICE

      
Application Number 17882335
Status Pending
Filing Date 2022-08-05
First Publication Date 2023-09-28
Owner
  • KABUSHIKI KAISHA TOSHIBA (Japan)
  • TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION (Japan)
Inventor
  • Deguchi, Takafumi
  • Tomita, Kouta

Abstract

According to one embodiment, a semiconductor device includes first and second electrodes, first to third semiconductor regions, a first conductive part, a first gate electrode. The first semiconductor region is located on the first electrode and electrically connected with the first electrode. The second semiconductor region is located on the first semiconductor region. The third semiconductor region is located on a portion of the second semiconductor region. The first conductive part is located in the first semiconductor region with a first insulating part interposed. The first gate electrode is located on the first conductive part with a first inter-layer insulating part interposed. The first gate electrode faces the second semiconductor region via a first gate insulating layer. The second electrode is located on the second and third semiconductor regions and electrically connected with the second and third semiconductor regions, and the first conductive part.

IPC Classes  ?

  • H01L 29/40 - Electrodes
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 29/66 - Types of semiconductor device

67.

SEMICONDUCTOR DEVICE

      
Application Number 17901732
Status Pending
Filing Date 2022-09-01
First Publication Date 2023-09-28
Owner
  • KABUSHIKI KAISHA TOSHIBA (Japan)
  • TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION (Japan)
Inventor
  • Tanaka, Katsuhisa
  • Kono, Hiroshi

Abstract

A semiconductor device includes a first electrode, a first semiconductor region of a first conductivity type having first and second regions, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a gate electrode, a fourth semiconductor region of the second conductivity type between the first region and the gate electrode, fifth semiconductor regions of the second conductivity type, each having a first concentration of impurities of the second conductivity type, sixth semiconductor regions of the second conductivity type, each having a second concentration of impurities of the second conductivity type that is lower than the first concentration, and a second electrode. The fifth semiconductor regions are located around the fourth semiconductor region in a first plane perpendicular to the first direction. The sixth semiconductor regions are located around the second semiconductor region in a second plane perpendicular to the first direction.

IPC Classes  ?

  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes

68.

RANDOM NUMBER GENERATION CIRCUIT

      
Application Number 17901960
Status Pending
Filing Date 2022-09-02
First Publication Date 2023-09-28
Owner
  • Kabushiki Kaisha Toshiba (Japan)
  • Toshiba Electronic Devices & Storage Corporation (Japan)
Inventor
  • Nakano, Hiroo
  • Ali, Mdbelayet

Abstract

A random number generation circuit in an embodiment includes a sampling circuit configured to capture an oscillation output of a ring oscillator using a first clock and generate a random number value, a periodicity detection circuit configured to detect periodicity of an output of the sampling circuit, a randomness test circuit configured to perform a randomness test for the output of the sampling circuit, and a control circuit configured to change an oscillation period of the oscillation output based on a detection result of the periodicity detection circuit, divide a random number output based on the random number value into a plurality of divided random numbers to perform random number generation for each of the divided random numbers, and cause the randomness test circuit to execute the randomness test for each generation of the divided random numbers.

IPC Classes  ?

  • G06F 7/58 - Random or pseudo-random number generators

69.

CONDITION MONITORING APPARATUS, METHOD, AND STORAGE MEDIUM

      
Application Number 17942275
Status Pending
Filing Date 2022-09-12
First Publication Date 2023-09-21
Owner KABUSHIKI KAISHA TOSHIBA (Japan)
Inventor
  • Sudo, Takashi
  • Kanishima, Yasuhiro
  • Yanagihashi, Hiroyuki

Abstract

According to one embodiment, a condition monitoring apparatus includes a processing circuitry. The processing circuitry is configured to collect a sensor signal output from a sensor that monitors a condition of a mechanical device that is at least partially mobile. The processing circuitry is configured to diagnose a presence or absence of an anomaly in the mechanical device based on the sensor signal. The processing circuitry is configured to cut out the sensor signal in a time width according to any one or more of a speed, an acceleration, and a jerk of the mechanical device. The processing circuitry is configured to determine the presence or absence of an anomaly based on the cut out sensor signal.

IPC Classes  ?

  • G01M 13/00 - Testing of machine parts
  • G01P 15/00 - Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration
  • G01P 3/00 - Measuring linear or angular speed; Measuring differences of linear or angular speeds

70.

VOICE ACTIVITY DETECTION APPARATUS, LEARNING APPARATUS, AND STORAGE MEDIUM

      
Application Number 17820878
Status Pending
Filing Date 2022-08-18
First Publication Date 2023-09-21
Owner KABUSHIKI KAISHA TOSHIBA (Japan)
Inventor Kim, Uihyun

Abstract

According to one embodiment, a voice activity detection apparatus includes a processing circuit. The processing circuit acquires an acoustic signal and a non-acoustic signal, calculates an acoustic feature based on the acoustic signal, calculates a non-acoustic feature based on the non-acoustic signal, calculates a voice emphasized feature based on the acoustic signal and the non-acoustic signal, calculates a voice existence/non-existence feature on the basis of the acoustic feature and the non-acoustic feature, calculates a voice existence score based on the voice emphasized feature and the voice existence/non-existence feature, detects a voice section and/or a non-voice section based on comparison of the voice existence score with a threshold.

IPC Classes  ?

  • G10L 25/78 - Detection of presence or absence of voice signals
  • G10L 25/30 - Speech or voice analysis techniques not restricted to a single one of groups characterised by the analysis technique using neural networks
  • G10L 15/02 - Feature extraction for speech recognition; Selection of recognition unit

71.

ULTRASONIC WELDING DIAGNOSTIC METHOD, JOINING METHOD OF WELDING MEMBER, AND INSPECTION DEVICE

      
Application Number 17897567
Status Pending
Filing Date 2022-08-29
First Publication Date 2023-09-21
Owner KABUSHIKI KAISHA TOSHIBA (Japan)
Inventor
  • Usui, Takashi
  • Ueno, Keisuke
  • Shibuya, Mamoru
  • Hanafusa, Souichi
  • Sakaguchi, Tatsuhiko

Abstract

An ultrasonic welding diagnostic method includes: applying a pressing force to an object to be joined so as to generate a surface pressure on a joint surface of the object to be joined; inputting ultrasonic waves to the joint surface; detecting an elastic wave propagating through the object to be joined by at least one sensor at a plurality of different positions; analyzing a signal detected by the sensor to generate an envelope of the signal and calculating information about the envelope; and determining a joint state on the joint surface based on the calculation result of the information.

IPC Classes  ?

  • B23K 31/12 - Processes relevant to this subclass, specially adapted for particular articles or purposes, but not covered by any single one of main groups relating to investigating the properties, e.g. the weldability, of materials
  • B23K 20/10 - Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating making use of vibrations, e.g. ultrasonic welding
  • G01N 29/04 - Analysing solids

72.

DATA PROTECTION APPARATUS, ELECTRONIC APPARATUS, METHOD, AND STORAGE MEDIUM

      
Application Number 17903291
Status Pending
Filing Date 2022-09-06
First Publication Date 2023-09-21
Owner KABUSHIKI KAISHA TOSHIBA (Japan)
Inventor
  • Hashimoto, Mikio
  • Shimbo, Atsushi
  • Amemiya, Jiro

Abstract

According to one embodiment, a data protection apparatus includes a processor configured to execute an encryption process on log data including a data frame including a plurality of pieces of data generated along a time sequence. The processor is configured to encrypt each of the pieces of data with a corresponding encryption key among a first initial key and a first encryption keys generated in a forward direction to a time sequence of the pieces of data. The processor is configured to encrypt each of a plurality of pieces of data encrypted with the corresponding encryption key with a corresponding encryption key among a second initial key and a second encryption keys generated in a backward direction to a time sequence of the pieces of data.

IPC Classes  ?

  • H04L 9/32 - Arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system
  • H04L 9/08 - Key distribution
  • H04L 9/14 - Arrangements for secret or secure communications; Network security protocols using a plurality of keys or algorithms

73.

INTEGRATED CIRCUIT

      
Application Number 17892980
Status Pending
Filing Date 2022-08-22
First Publication Date 2023-09-21
Owner
  • Kabushiki Kaisha Toshiba (Japan)
  • Toshiba Electronic Devices & Storage Corporation (Japan)
Inventor Shimojo, Yoshimitsu

Abstract

An integrated circuit of an embodiment includes a plurality of AD conversion circuits including a first AD conversion circuit and a second AD conversion circuit, and a control circuit configured to delay a start time of sampling processing of the second AD conversion circuit as compared with a usual start time such that the first AD conversion circuit is not influenced by noise generated by the sampling processing of the second AD conversion circuit, and to shorten a sampling time period to control a termination time of the sampling processing of the second AD conversion circuit to be concurrent with a termination time in a case of performing usual sampling processing.

IPC Classes  ?

  • H03M 1/06 - Continuously compensating for, or preventing, undesired influence of physical parameters

74.

SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE

      
Application Number 17890554
Status Pending
Filing Date 2022-08-18
First Publication Date 2023-09-21
Owner
  • KABUSHIKI KAISHA TOSHIBA (Japan)
  • TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION (Japan)
Inventor Iguchi, Tomohiro

Abstract

A semiconductor device according to the embodiment includes: a frame body having a wall surface; an insulating substrate surrounded by the frame body, the insulating substrate having a first metal layer and a second metal layer on a surface, the second metal layer being located between the first metal layer and the wall surface; a semiconductor chip including an electrode and provided on the first metal layer; and a bonding wire having a first bond portion connected to the electrode, a second bond portion connected to the second metal layer, and an intermediate portion between the first bond portion and the second bond portion; wherein a second angle formed between a second direction in which the second bond portion extends and the wall surface is smaller than a first angle formed between a first direction in which the intermediate portion extends and the wall surface.

IPC Classes  ?

  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 23/047 - Containers; Seals characterised by the shape the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body the other leads being parallel to the base
  • H01L 23/373 - Cooling facilitated by selection of materials for the device
  • H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
  • H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices

75.

LEARNING APPARATUS, METHOD AND INFERENCE SYSTEM

      
Application Number 17823775
Status Pending
Filing Date 2022-08-31
First Publication Date 2023-09-21
Owner KABUSHIKI KAISHA TOSHIBA (Japan)
Inventor
  • Yaguchi, Atsushi
  • Nitta, Shuhei
  • Tanizawa, Akiyuki
  • Hirai, Ryusuke

Abstract

According to one embodiment, a learning apparatus includes a processor. The processor divides target data into pieces of partial data. The processor inputs the pieces of partial data into a first network model to output a first prediction result and calculates a first confidence indicating a degree of contribution to the first prediction result. The processor inputs the target data into a second network model to output a second prediction result and calculates a second confidence indicating a degree of contribution to the second prediction result. The processor updates a parameter of the first network model, based on the first prediction result, the second prediction result, the first confidence and the second confidence.

IPC Classes  ?

76.

LIGHT DETECTOR, LIGHT DETECTION SYSTEM, LIDAR DEVICE, AND MOBILE BODY

      
Application Number 17822417
Status Pending
Filing Date 2022-08-25
First Publication Date 2023-09-21
Owner KABUSHIKI KAISHA TOSHIBA (Japan)
Inventor
  • Kaneko, Ryomo
  • Shimizu, Mariko
  • Sasaki, Keita
  • Kwon, Honam
  • Fujiwara, Ikuo
  • Suzuki, Kazuhiro

Abstract

A light detector according to one embodiment, includes an element region, a light concentrator, a structure part and a light-shielding part. The element region includes a first semiconductor region of a first conductivity type, and a second semiconductor region of a second conductivity type. The light concentrator is separated from the element region in a first direction. The light concentrator is configured to concentrate light incident on the light concentrator. The structure part is arranged with the element region in a direction crossing the first direction. The structure part has a different refractive index from the element region. The light-shielding part is located between the element region and the light concentrator. The light-shielding part includes an opening. At least a portion of the light incident on the light concentrator is able to be incident on the element region by passing through the opening.

IPC Classes  ?

  • H01L 27/146 - Imager structures
  • G01S 17/89 - Lidar systems, specially adapted for specific applications for mapping or imaging

77.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

      
Application Number 17890041
Status Pending
Filing Date 2022-08-17
First Publication Date 2023-09-21
Owner
  • KABUSHIKI KAISHA TOSHIBA (Japan)
  • TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION (Japan)
Inventor
  • Asaba, Shunsuke
  • Suzuki, Takuma

Abstract

A semiconductor device includes a semiconductor part including a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type. The second semiconductor layer is provided in the first semiconductor layer. The semiconductor part includes first and second interfaces of the first semiconductor layer and the second semiconductor layer. The first interface intersects the second interface. The second semiconductor layer includes a plurality of sub-layers stacked in a direction orthogonal to the first interface. The second interface includes interfaces of the sub-layers of the second semiconductor layer and the first semiconductor layer. The second interface extending in a second direction inclined with respect to a first direction orthogonal to the first interface.

IPC Classes  ?

  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/04 - Semiconductor bodies characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
  • H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
  • H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
  • H01L 29/66 - Types of semiconductor device

78.

GAS DETECTION DEVICE

      
Application Number 18168838
Status Pending
Filing Date 2023-02-14
First Publication Date 2023-09-21
Owner Kabushiki Kaisha Toshiba (Japan)
Inventor
  • Hirono, Masatoshi
  • Saito, Shinji
  • Kakuno, Tsutomu
  • Hashimoto, Rei
  • Kaneko, Kei

Abstract

A gas detection device according to an embodiment includes a first light source irradiating infrared, a second light source irradiating visible light, a low-pass filter that transmits the infrared irradiated from the first light source, reflects the visible light irradiated from the second light source, and aligns an optical axis of the visible light with an optical axis of the infrared, a first retroreflector on which the infrared and the visible light having the aligned optical axes are incident, a first detecting part detecting the infrared reflected by the first retroreflector, and a scattering body located at a center of the first retroreflector.

IPC Classes  ?

  • G01N 21/3504 - Investigating relative effect of material at wavelengths characteristic of specific elements or molecules, e.g. atomic absorption spectrometry using infrared light for analysing gases, e.g. multi-gas analysis

79.

SEMICONDUCTOR DEVICE

      
Application Number 17902778
Status Pending
Filing Date 2022-09-02
First Publication Date 2023-09-21
Owner
  • KABUSHIKI KAISHA TOSHIBA (Japan)
  • TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION (Japan)
Inventor Takeda, Shun

Abstract

According to one embodiment, a semiconductor device includes a semiconductor circuit having an electrode on a first surface. A case part surrounds the semiconductor circuit. A matching part is provided including a signal terminal on an outside of the matching part and a lead on the inside of the matching part that is electrically connected to the signal terminal. The case part and matching part are configured to engage one another and be attached to one another when pressed together. The lead includes a contact portion that is in contact with the electrode when the matching part is attached to the case part, a first portion connecting between the signal terminal and the contact portion, and a spring portion between the first portion and the contact portion.

IPC Classes  ?

  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices

80.

ANALYSIS APPARATUS, METHOD, AND NON-TRANSITORY COMPUTER-READABLE STORAGE MEDIUM

      
Application Number 17930781
Status Pending
Filing Date 2022-09-09
First Publication Date 2023-09-21
Owner KABUSHIKI KAISHA TOSHIBA (Japan)
Inventor
  • Ike, Tsukasa
  • Yamauchi, Yasunobu
  • Hirai, Ryusuke
  • Fukunaga, Izumi

Abstract

According to one embodiment, an analysis apparatus includes processing circuitry. The processing circuitry acquires sensor data from a measurement target, calculates a state value based on the sensor data, sets, based on time-series data of the state value and predetermined criteria, a plurality of noticed sections in the time-series data, performs clustering using the state value regarding each of the noticed sections and generates a clustering result, and generates, based on the clustering result, stress information including characteristic information of each of a plurality of clusters.

IPC Classes  ?

  • G06V 10/762 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using clustering, e.g. of similar faces in social networks
  • G06V 10/62 - Extraction of image or video features relating to a temporal dimension, e.g. time-based feature extraction; Pattern tracking
  • G06V 10/74 - Image or video pattern matching; Proximity measures in feature spaces
  • G06V 10/80 - Fusion, i.e. combining data from various sources at the sensor level, preprocessing level, feature extraction level or classification level

81.

SEMICONDUCTOR DEVICE

      
Application Number 17901668
Status Pending
Filing Date 2022-09-01
First Publication Date 2023-09-21
Owner
  • KABUSHIKI KAISHA TOSHIBA (Japan)
  • TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION (Japan)
Inventor
  • Itokazu, Hiroko
  • Matsudai, Tomoko
  • Iwakaji, Yoko
  • Kawamura, Keiko
  • Fuse, Kaori

Abstract

A semiconductor device includes a semiconductor part, first and second electrodes and first-third and second-third electrodes. The semiconductor part is provided between the first and second electrodes. The semiconductor part includes a first semiconductor layer of a first conductivity type, second and third semiconductor layers of a second conductivity type. The second and third semiconductor layers are arranged between the first layer and the second electrode. The first-third and second-third electrodes are provided in the semiconductor part. The second semiconductor layer is provided between the first-third electrode and the second-third electrode. The second electrode includes a contact portion extending into the second semiconductor layer. The third semiconductor layer is provided on the second semiconductor layer between the contact portion and the second-third electrode. The second semiconductor layer includes a first portion facing the third semiconductor layer via the contact portion.

IPC Classes  ?

  • H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
  • H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect

82.

INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, COMPUTER PROGRAM PRODUCT, AND INFORMATION PROCESSING SYSTEM

      
Application Number 17823281
Status Pending
Filing Date 2022-08-30
First Publication Date 2023-09-21
Owner
  • KABUSHIKI KAISHA TOSHIBA (Japan)
  • TOSHIBA INFRASTRUCTURE SYSTEMS & SOLUTIONS CORPORATION (Japan)
Inventor
  • Aisu, Hideyuki
  • Sakakibara, Shizu
  • Kiribuchi, Daiki
  • Yoshida, Takufumi

Abstract

According to an embodiment, an information processing device includes a reception unit and a determination unit. The reception unit receives a plurality of pieces of rack data including first identification information of one or more kinds of products to be housed in a plurality of racks, and a plurality of pieces of order data including second identification information of one or more kinds of products to be picked from at least part of the plurality of racks. The determination unit, based on the rack data, determines a processing sequence of the plurality of pieces of order data such that a ratio of picking products assigned to pieces of the order data from a single rack is increased. The plurality of racks are able to be moved to a work station where housing containers corresponding to at least part of the plurality of pieces of order data are disposed.

IPC Classes  ?

  • G06Q 10/08 - Logistics, e.g. warehousing, loading or distribution; Inventory or stock management
  • G06F 16/28 - Databases characterised by their database models, e.g. relational or object models

83.

SEMICONDUCTOR DEVICE, INVERTER CIRCUIT, DRIVE DEVICE, VEHICLE, AND ELEVATOR

      
Application Number 17900993
Status Pending
Filing Date 2022-09-01
First Publication Date 2023-09-21
Owner KABUSHIKI KAISHA TOSHIBA (Japan)
Inventor
  • Kimoto, Shinichi
  • Iijima, Ryosuke
  • Harada, Shinsuke

Abstract

A semiconductor device of embodiments includes: a silicon carbide layer having a first face parallel to a first direction and a second direction crossing the first direction and a second face facing the first face; a first trench on a side of the first face extending in the first direction; a second trench extending in the first direction; a third trench extending in the second direction and continuous with the first trench and the second trench; a fourth trench extending in the first direction, disposed between the first trench and the second trench, and spaced from the third trench in the first direction; a gate electrode in the first to fourth trench; a gate insulating layer; a first conductive layer crossing the third trench and connected to the gate electrode; a first electrode disposed on the first face; and a second electrode disposed on the second face.

IPC Classes  ?

  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched

84.

CARBON DIOXIDE ELECTROLYTIC DEVICE AND METHOD OF CONTROLLING CARBON DIOXIDE ELECTROLYTIC DEVICE

      
Application Number 17821828
Status Pending
Filing Date 2022-08-24
First Publication Date 2023-09-21
Owner KABUSHIKI KAISHA TOSHIBA (Japan)
Inventor
  • Kiyota, Yasuhiro
  • Jung, Hyangmi
  • Kudo, Yuki
  • Mikoshiba, Satoshi
  • Kitagawa, Ryota

Abstract

A carbon dioxide electrolytic device includes: a carbon dioxide electrolysis cell having a cathode and an anode flow path, a cathode, an anode, and a first diaphragm; a first current regulator to supply a first current; a first gas/liquid separator to separate a first fluid from the anode flow path into a first liquid and gas; an electrodialysis cell having, first and second electrodes, first to fourth rooms, and second to fourth diaphragms; a second current regulator to supply a second current; at least one detector out of a first detector to detect a flow rate of the first gas or a concentration of carbon dioxide in the first gas, and a second detector to detect a pH or a concentration of at least one ion in the first fluid; and a first controller to regulate a second current, in accordance with at least one detection signal.

IPC Classes  ?

  • C25B 1/23 - Carbon monoxide or syngas
  • C25B 9/19 - Cells comprising dimensionally-stable non-movable electrodes; Assemblies of constructional parts thereof with diaphragms
  • C25B 13/00 - Diaphragms; Spacing elements
  • C25B 15/029 - Concentration
  • C25B 3/07 - Oxygen containing compounds
  • C25B 3/26 - Reduction of carbon dioxide
  • C25B 9/65 - Means for supplying current; Electrode connections; Electric inter-cell connections

85.

SEMICONDUCTOR DEVICE AND METHOD FOR CONTROLLING SEMICONDUCTOR DEVICE

      
Application Number 18168156
Status Pending
Filing Date 2023-02-13
First Publication Date 2023-09-21
Owner
  • KABUSHIKI KAISHA TOSHIBA (Japan)
  • TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION (Japan)
Inventor
  • Yasuzumi, Takenori
  • Hasegawa, Kohei
  • Tanaka, Tsuguhiro
  • Kawai, Shusuke

Abstract

According to one embodiment, a semiconductor device includes an n-layer and a p-layer arranged in a vertical trench structure in a drift layer. A depletion layer is formed to a depth of a trench of the vertical trench structure after a depletion layer spreads in a lateral direction between the n-layer and the p-layer when a voltage is applied between a drain and a source. A method for controlling the semiconductor device comprises detecting a voltage value between the drain and the source of the semiconductor device at turn-off and reducing a current value of a gate discharge current discharged from a gate in a first period. The first period starting before the detected voltage value greatly changes.

IPC Classes  ?

  • H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors

86.

METHOD OF MANUFACTURING STRUCTURE AND METHOD OF MANUFACTURING CAPACITOR

      
Application Number 18183534
Status Pending
Filing Date 2023-03-14
First Publication Date 2023-09-21
Owner KABUSHIKI KAISHA TOSHIBA (Japan)
Inventor
  • Sano, Mitsuo
  • Obata, Susumu
  • Higuchi, Kazuhito
  • Tajima, Takayuki

Abstract

In general, according to one embodiment, there is provided a method of manufacturing a structure. The method includes forming a recess in a semiconductor substrate; oxidizing at least a bottom inner surface of the recess; and providing at least the bottom inner surface of the recess with a liquid capable of dissolving an oxide of a semiconductor substrate material.

IPC Classes  ?

  • H01L 21/62 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having no potential-jump barriers or surface barriers
  • H01G 4/33 - Thin- or thick-film capacitors

87.

SEMICONDUCTOR DEVICE

      
Application Number 17864163
Status Pending
Filing Date 2022-07-13
First Publication Date 2023-09-21
Owner
  • KABUSHIKI KAISHA TOSHIBA (Japan)
  • TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION (Japan)
Inventor
  • Tanaka, Katsuhisa
  • Kono, Hiroshi

Abstract

According to one embodiment, a semiconductor device includes first and second electrodes, first to fifth semiconductor regions, and a gate electrode. The first semiconductor region is located on the first electrode. The first semiconductor region includes a first region. The gate electrode is located on the first semiconductor region with a gate insulating layer interposed. The second semiconductor region faces the gate electrode via the gate insulating layer in a second direction perpendicular to a first direction. The third semiconductor region is located between the first and second semiconductor regions. A length in the second direction of a lower portion of the third semiconductor region is greater than a length in the second direction of an upper portion of the third semiconductor region. The fourth semiconductor region is located between the third semiconductor region and the gate electrode. The fifth semiconductor region is located on the second semiconductor region.

IPC Classes  ?

  • H01L 29/36 - Semiconductor bodies characterised by the concentration or distribution of impurities

88.

INFORMATION PROCESSING DEVICE, MAGNETIC RECORDING AND REPRODUCING DEVICE, AND MAGNETIC RECORDING AND REPRODUCING SYSTEM

      
Application Number 17822753
Status Pending
Filing Date 2022-08-26
First Publication Date 2023-09-21
Owner KABUSHIKI KAISHA TOSHIBA (Japan)
Inventor
  • Takeda, Susumu
  • Yamada, Kenichiro

Abstract

According to one embodiment, an information processing device includes an acquisition part, and a processor. The acquisition part is configured to acquire a reproduction signal obtained from a recording part. The recording part includes a recording medium. The reproduction signal includes a first signal corresponding to information recorded in the recording medium. The processor is configured to derive a first output and a second output. The first output is obtained by first information being processed by a first processing model. The first information includes the first signal. The second output is obtained by the first information being processed by a second processing model. The processor is configured to output a result of processing the first information based on a third output. The third output is obtained based on the first output, the second output, and the first information.

IPC Classes  ?

  • G11B 5/012 - Recording on, or reproducing or erasing from, magnetic disks
  • G11B 5/127 - Structure or manufacture of heads, e.g. inductive

89.

PHOTOMASK, METHOD FOR MANUFACTURING LENS, AND METHOD FOR MANUFACTURING PHOTODETECTOR

      
Application Number 17822766
Status Pending
Filing Date 2022-08-26
First Publication Date 2023-09-21
Owner KABUSHIKI KAISHA TOSHIBA (Japan)
Inventor
  • Kwon, Honam
  • Shimizu, Mariko
  • Okamoto, Kazuaki
  • Suzuki, Kazuhiro

Abstract

According to one embodiment, a photomask includes a plurality of unit regions arranged in a first direction and a second direction crossing the first direction. Each of the unit regions includes a first region having a first light-shielding rate, and a second region having a second light-shielding rate different from the first light-shielding rate. The second region is provided around the first region. The unit regions include a first unit region and a second unit region having same size each other. A distance between the first unit region and a center of a range in which the unit regions are arranged is different from a distance between the second unit region and the center. A light-shielding rate of the first unit region is different from a light-shielding rate of the second unit region.

IPC Classes  ?

  • G03F 1/38 - Masks having auxiliary features, e.g. special coatings or marks for alignment or testing; Preparation thereof
  • H01L 27/146 - Imager structures

90.

AIR BATTERY

      
Application Number 17823651
Status Pending
Filing Date 2022-08-31
First Publication Date 2023-09-21
Owner KABUSHIKI KAISHA TOSHIBA (Japan)
Inventor
  • Ueda, Kakuya
  • Hoshina, Keigo

Abstract

According to one embodiment, provided is an air battery including a negative electrode, an air electrode to which oxygen is supplied, a solid electrolyte layer positioned between the negative electrode and the air electrode, an aqueous electrolyte layer positioned between the solid electrolyte layer and the air electrode, and a proton conduction layer positioned between the aqueous electrolyte layer and the air electrode. The aqueous electrolyte layer includes an aqueous electrolyte including a polyprotic acid having two or more carboxyl groups, an electrolyte salt, and water.

IPC Classes  ?

  • H01M 12/08 - Hybrid cells; Manufacture thereof composed of a half-cell of a fuel-cell type and a half-cell of the secondary-cell type
  • H01M 10/0562 - Solid materials
  • H01M 4/40 - Alloys based on alkali metals

91.

QUANTUM CRYPTOGRAPHIC COMMUNICATION SYSTEM, KEY MANAGEMENT DEVICE, AND KEY MANAGEMENT METHOD

      
Application Number 17899233
Status Pending
Filing Date 2022-08-30
First Publication Date 2023-09-21
Owner KABUSHIKI KAISHA TOSHIBA (Japan)
Inventor
  • Doi, Kazuaki
  • Nakashima, Toshiki
  • Matsumoto, Mari
  • Tanizawa, Yoshimichi

Abstract

According to an embodiment, a quantum cryptographic communication system includes a first quantum key distribution (QKD) device, and a first key management device. The first QKD device that shares a quantum encryption key with a second QKD device through QKD. The first key management device includes a reception unit and a first hardware security module (HSM). The reception unit receives the quantum encryption key from the first QKD device. The first HSM includes a storage unit, a generation unit, and a first encryption unit. The storage unit stores a first encryption key therein. The generation unit generates an application key used in an encryption process by a cryptographic application. The first encryption unit that encrypts, with the first encryption key, the application key transmitted to a second key management device connected to the second QKD device.

IPC Classes  ?

  • H04L 9/08 - Key distribution
  • H04L 9/06 - Arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for blockwise coding, e.g. D.E.S. systems

92.

SEMICONDUCTOR CHIP AND SEMICONDUCTOR DEVICE

      
Application Number 17902246
Status Pending
Filing Date 2022-09-02
First Publication Date 2023-09-21
Owner
  • KABUSHIKI KAISHA TOSHIBA (Japan)
  • TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION (Japan)
Inventor Minamikawa, Kazuki

Abstract

A semiconductor chip includes a semiconductor substrate, a plurality of first wirings extending in a first direction parallel to the upper surface of the semiconductor substrate and disposed entirely above the upper surface of the semiconductor substrate, a second wiring disposed between two of the first wirings that are adjacent to each other and entirely below the upper surface of the semiconductor substrate such that an upper surface of the second wiring is below a lower surface of the two first wirings, and a first insulating film provided on the second wiring and spaced apart from the two first wirings in a second direction that is perpendicular to the first direction, the first insulating film having an upper surface that is above the lower surface of the two first wirings.

IPC Classes  ?

  • H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
  • H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions

93.

LIGHT DETECTION DEVICE, LIGHT DETECTION SYSTEM, LIDAR DEVICE, MOBILE BODY, INSPECTION METHOD, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

      
Application Number 17823596
Status Pending
Filing Date 2022-08-31
First Publication Date 2023-09-21
Owner KABUSHIKI KAISHA TOSHIBA (Japan)
Inventor
  • Okamoto, Kazuaki
  • Kwon, Honam
  • Suzuki, Kazuhiro

Abstract

According to one embodiment, a light detection device includes a first region, a second region, a first electrode, and a second electrode. The first region includes a plurality of first semiconductor light detection elements, and a plurality of first lenses respectively located on the plurality of first semiconductor light detection elements. The second region includes a plurality of second semiconductor light detection elements. No lens is located directly above the plurality of second semiconductor light detection elements. The first electrode is electrically connected with the plurality of first semiconductor light detection elements. The second electrode is electrically connected with the plurality of second semiconductor light detection elements.

IPC Classes  ?

  • G01S 17/89 - Lidar systems, specially adapted for specific applications for mapping or imaging
  • H01L 31/107 - Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier working in avalanche mode, e.g. avalanche photodiode
  • H01L 27/144 - Devices controlled by radiation

94.

ADHESION/PEELING METHOD, AND ADHESION/PEELING DEVICE

      
Application Number 17929431
Status Pending
Filing Date 2022-09-02
First Publication Date 2023-09-21
Owner KABUSHIKI KAISHA TOSHIBA (Japan)
Inventor
  • Usui, Takashi
  • Kugimiya, Tetsuya
  • Watabe, Kazuo
  • Ueno, Keisuke
  • Takamine, Hidefumi
  • Hirokawa, Junko
  • Li, Yongfang
  • Ueda, Yuki

Abstract

An adhesion/peeling method according to an embodiment includes adhering a first surface side of an electrically peelable adhesive sheet to a predetermined position of a fixation target object, wherein the electrically peelable adhesive sheet is formed of an electro-peeling adhesive having adhesiveness on the first surface side and a second surface side thereof, and the adhesiveness of the electro-peeling adhesive is lowered due to an input of a voltage; adhering a first electrode of an adherend including the first electrode formed of a conductor to the second surface side of the electrically peelable adhesive sheet; containing a liquid at the predetermined position of the fixation target object to temporarily form a second electrode with conductivity on a surface of the fixation target object; and inputting a predetermined voltage between the first electrode and the second electrode to peel of the electrically peelable adhesive sheet from the fixation target object.

IPC Classes  ?

  • C09J 9/02 - Electrically-conducting adhesives

95.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING

      
Application Number 17900433
Status Pending
Filing Date 2022-08-31
First Publication Date 2023-09-21
Owner
  • KABUSHIKI KAISHA TOSHIBA (Japan)
  • TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION (Japan)
Inventor
  • Nishiwaki, Tatsuya
  • Gejo, Ryohei
  • Matsudai, Tomoko

Abstract

A semiconductor device includes a first electrode, a plurality of unit element regions, and a partitioning region. Each of the unit element regions includes a first semiconductor part, a second electrode, and a first conductive part. The first semiconductor part includes first to third semiconductor regions. The first semiconductor region is located above the first electrode. The second semiconductor region is located on the first semiconductor region. The third semiconductor region is located on the second semiconductor region. The second electrode is located on the second and third semiconductor regions. The first conductive part faces the second semiconductor region via a first insulating film. At least a portion of the plurality of unit element regions includes a common pattern. The partitioning region includes a second semiconductor part and partitions the plurality of unit element regions. The second semiconductor part is continuous with the first semiconductor part.

IPC Classes  ?

  • H01L 29/66 - Types of semiconductor device
  • H01L 29/36 - Semiconductor bodies characterised by the concentration or distribution of impurities
  • H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
  • H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/872 - Schottky diodes

96.

LiDAR DEVICE AND CONTROL METHOD FOR LiDAR DEVICE

      
Application Number 18176914
Status Pending
Filing Date 2023-03-01
First Publication Date 2023-09-21
Owner KABUSHIKI KAISHA TOSHIBA (Japan)
Inventor
  • Hirono, Masatoshi
  • Kubota, Hiroshi
  • Matsumoto, Nobu
  • Kimura, Katsuyuki

Abstract

A LiDAR device according to an embodiment includes a rotating mirror having reflective surfaces, first/second light emitters each emitting light toward the rotating mirror, and first/second light receivers each receiving light reflected by the rotating mirror and converting the received light into an electrical signal. The first light emitter emits light in an orientation where an upper section of a distance measurement range is scanned. The second light emitter emits light in an orientation where a lower section of the distance measurement range is scanned. The first light receiver is provided at a position where light emitted by the first light emitter and reflected at the distance measurement range is received via the rotating mirror. The second light receiver is provided at a position where light emitted by the second light emitter and reflected at the distance measurement range is received via the rotating mirror.

IPC Classes  ?

  • G01S 7/481 - Constructional features, e.g. arrangements of optical elements
  • G01S 17/10 - Systems determining position data of a target for measuring distance only using transmission of interrupted, pulse-modulated waves

97.

INFORMATION PROCESSING APPARATUS AND INFORMATION PROCESSING METHOD

      
Application Number 18183450
Status Pending
Filing Date 2023-03-14
First Publication Date 2023-09-21
Owner KABUSHIKI KAISHA TOSHIBA (Japan)
Inventor Nishiuchi, Hideo

Abstract

In an embodiment, an information processing apparatus relating to soldering of a component onto a substrate is provided. The information processing apparatus includes a determination unit determining, using a machine learning model that outputs an inspection result of a post-reflow inspection from an input of image data based on one or more pre-reflow images, whether or not defectiveness will occur in the post-reflow inspection from the image data based on the pre-reflow images acquired in real time.

IPC Classes  ?

  • G06T 7/00 - Image analysis
  • G06V 10/25 - Determination of region of interest [ROI] or a volume of interest [VOI]
  • G06V 10/56 - Extraction of image or video features relating to colour
  • G06V 10/70 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning

98.

ANALOG SWITCH CIRCUIT

      
Application Number 17897845
Status Pending
Filing Date 2022-08-29
First Publication Date 2023-09-21
Owner
  • Kabushiki Kaisha Toshiba (Japan)
  • Toshiba Electronic Devices & Storage Corporation (Japan)
Inventor Imai, Shigeo

Abstract

An analog switch circuit of an embodiment includes a CMOS analog switch, a first gate drive circuit, and a second gate drive circuit, a gate operating withstand voltage of the CMOS analog switch being VGT, an enable signal and a control signal being inputted to the first gate drive circuit and the second gate drive circuit. Assuming that VGT

IPC Classes  ?

  • H03K 17/06 - Modifications for ensuring a fully conducting state
  • H03K 17/16 - Modifications for eliminating interference voltages or currents

99.

SUPERCONDUCTING COIL, SUPERCONDUCTING DEVICE, AND LIQUID EPOXY RESIN COMPOSITION

      
Application Number 17929049
Status Pending
Filing Date 2022-09-01
First Publication Date 2023-09-21
Owner KABUSHIKI KAISHA TOSHIBA (Japan)
Inventor
  • Hayashi, Mariko
  • Sekiguchi, Yumiko
  • Eguchi, Tomoko
  • Fujii, Keiko

Abstract

A superconducting coil according to an embodiment includes: a winding frame; a superconducting wire wound around the winding frame and having a first region and a second region facing the first region in a coil radial direction; and a resin layer located between the first region and the second region and including particles, an epoxy resin surrounding the particles, and a region existing between the particle and the epoxy resin, the region including silane containing a phenylamino group. The average particle diameter of the particles is equal to or more than 1 μm and equal to or less than 5 μm, and the volume ratio of the particles in the resin layer is equal to or more than 50% and equal to or less than 66%.

IPC Classes  ?

  • H01F 6/06 - Coils, e.g. winding, insulating, terminating or casing arrangements therefor
  • H01L 39/12 - Devices using superconductivity or hyperconductivity; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof - Details characterised by the material
  • H01F 41/04 - Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils or magnets for manufacturing coils
  • H01F 41/12 - Insulating of windings

100.

METHOD OF ANALYZING ANTIMONY ION, INSPECTION TOOL USED FOR ANALYZING PENTAVALENT ANTIMONY ION, AND INSPECTION TOOL USED FOR ANALYZING ANTIMONY ION ACCORDING TO ITS VALENCE

      
Application Number 17887582
Status Pending
Filing Date 2022-08-15
First Publication Date 2023-09-21
Owner KABUSHIKI KAISHA TOSHIBA (Japan)
Inventor
  • Oki, Mitsuhiro
  • Morimoto, Sayaka

Abstract

A method of analyzing an antimony ion of an embodiment, the method includes using a first analysis solution or a second analysis solution, the first analysis solution containing trivalent antimony ions and pentavalent antimony ions, the second analysis solution being a solution obtained by mixing a first acid and the first analysis solution, and mixing the first analysis solution or the second analysis solution with a second acid to obtain a third analysis solution in which the pentavalent antimony ions are chlorinated and which contains [SbCl6]− ions, mixing the third analysis solution and a first organic solvent and phase-separating the mixture into a fourth analysis solution as an organic phase and an aqueous phase to obtain the fourth analysis solution, mixing the fourth analysis solution and a coloring liquid containing rhodamine B to obtain a fifth analysis solution, and evaluating a concentration of the pentavalent antimony ions in the first analysis solution from color of the fifth analysis solution. A total concentration of nitric acid, cerium (IV) nitrate, and cerium (IV) sulfate contained in the first analysis solution is 0.00 mol/L or more and 0.1 mol/L or less. The total concentration of nitric acid, cerium (IV) nitrate, and cerium (IV) sulfate contained in the first acid is 0.00 mol/L or more and 0.1 mol/L or less. The total concentration of nitric acid, cerium (IV) nitrate, and cerium (IV) sulfate contained in the second acid is 0.00 mol/L or more and 0.1 mol/L or less.

IPC Classes  ?

  • G01N 21/78 - Systems in which material is subjected to a chemical reaction, the progress or the result of the reaction being investigated by observing the effect on a chemical indicator producing a change of colour
  1     2     3     ...     100        Next Page