POSTECH Research and Business Development Foundation (Republic of Korea)
Inventor
Lee, Jaehyeong
Lee, Gilho
Kang, Jinhyoun
Shin, Jaeho
Lee, Seunghan
Han, Daeseok
Abstract
A superconducting quantum interferometric device (SQUID) includes: a conductive material region formed on a partial region of a substrate; a first superconducting material layer including a first loop including first and second extension units that are spaced apart from each other to form a proximity Josephson junction and that form a stack structure with the conductive material region; a second superconducting material layer including a second loop including first and second end units spaced apart from each other; and a tunnel Josephson junction formed by a stack structure including a tunnel thin film layer forming and the first and second end units, wherein at least a portion of the second loop forms a stack structure with the first loop.
Embodiments herein disclose methods and devices for managing data traffic on a receiver. A method disclosed herein includes detecting, by a receiver, at least one out of order radio link control (RLC) protocol data unit (PDU) in a plurality of RLC PDUs received from a transmitter, performing, by the receiver, a recovery action based on a Packet Data Convergence Protocol (PDCP) reordering time to recover the at least one out of order RLC PDU; and causing, by the receiver, an RLC layer to send a plurality of RLC service data units (SDUs) to a higher layer after the performing the recovery action, the plurality of RLC SDUs corresponding to the plurality of RLC PDUs.
The disclosure relates to a 5G or 6G communication system for supporting a higher data transmission rate. Embodiments herein is to provide a method for providing user consent for UE in a 5G network (1000) by a UE (300). The method includes receiving a request message from a network apparatus (200) to check with the UE (300) whether the network apparatus (200) can provide subscribed event information to a NWDAF (100). The request message includes the subscribed event information and a consumer NF ID to obtain consent from the UE (300). Further, the method includes determining, by the UE (300), using the preconfigured data whether a consent can be provided for the subscribed event information to the NWDAF (100). Further, the method includes sending, by the UE (300), a response message to the network apparatus (200), wherein the response message comprises a consent indication allowing the network apparatus (200) to provide the subscribed event information to the NWDAF (100).
H04W 8/18 - Processing of user or subscriber data, e.g. subscribed services, user preferences or user profiles; Transfer of user or subscriber data
H04L 41/082 - Configuration setting characterised by the conditions triggering a change of settings the condition being updates or upgrades of network functionality
4.
POWER SUPPLY APPARATUS AND CONTROLLING METHOD THEREOF
The present disclosure provides power supply apparatuses and controlling methods thereof. In some embodiments, a power supply apparatus includes a power factor correction (PFC) circuit, and a control circuit configured to control the PFC circuit. The PFC circuit includes a power inputter configured to receive alternating current voltage to be rectified, an inductor having an end coupled to an end of the power inputter, a first switching element configured to be turned on and off according to a first control signal, a second switching element configured to be turned on and off according to a second control signal, and an outputter configured to output a direct current voltage through an output capacitor. The control circuit is further configured to respectively apply the first and second control signals to the first and second switching elements such that the first and the second switching elements are alternately turned on.
A high endurance persistent storage device. In some embodiments, the persistent storage device includes: a controller circuit; persistent storage media, connected to the controller circuit; nonvolatile memory, connected to the controller circuit; and volatile memory, connected to the controller circuit.
An electrostatic discharge clamp circuit includes a resistor connected between a first node and a second node, a first capacitor connected between the second node and a third node, a second capacitor connected between a fourth node and the third node, a third capacitor connected between a fifth node and the third node, a first inverter providing a power supply voltage or a voltage of the fourth node based on a voltage of the second node, a second inverter providing an output voltage of the first inverter or a voltage of the fifth node based on the voltage of the fourth node, a third inverter configured to provide an output voltage of the second inverter or the ground voltage based on the voltage of the fifth node.
A semiconductor memory device includes a memory cell array with a plurality of rows of memory cells therein, and a row hammer management (RHM) circuit including a hammer address queue. The RHM circuit is configured to: (i) receive first access row addresses from an external memory controller during a reference time interval, (ii) store a first row address randomly selected from the first access row addresses and second row addresses consecutively received from the memory controller after selecting the first row address, in the hammer address queue as candidate hammer addresses, and (iii) sequentially output the candidate hammer addresses as a hammer address. A refresh control circuit is provided to receive the hammer address and to perform a hammer refresh operation on one or more victim memory cell rows, which are physically adjacent to a memory cell row corresponding to the hammer address.
An electronic device including: a connector including a voltage terminal; a battery; a corruption detection circuit configured to detect whether the connector is corrupted; a voltage cutoff circuit configured to electrically connect the voltage terminal with an internal node when corruption of the connector is not detected by the corruption detection circuit and to electrically disconnect the voltage terminal from the internal node when the corruption is detected by the corruption detection circuit; a charging pin connected with the internal node, and configured to transfer a voltage of the internal node to an external device when the charging pin is connected with the external device; and a power management integrated circuit connected between the internal node and the battery, and configured to charge the battery by using the voltage of the internal node or to generate the voltage of the internal node by using a voltage of the battery.
H02J 7/00 - Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
H02H 7/18 - Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from norm for accumulators
9.
METHOD OF EXTRACTING PROPERTIES OF A LAYER ON A WAFER
Provided is a method of extracting properties of a layer on a wafer, the method including emitting electromagnetic waves to a lower surface of the wafer, detecting a first electromagnetic wave, that passes through a target layer on an upper surface of the wafer, and a second electromagnetic wave, that is reflected from the target layer, among the electromagnetic waves to obtain data including information about the first electromagnetic wave and the second electromagnetic wave, and separating a first pulse of the first electromagnetic wave and a second pulse of the second electromagnetic wave from each other in the data and obtaining property data of the target layer.
Disclosed is a ramp signal generator. The ramp signal generator includes: a first unit current source including first sub-unit current sources, and configured to output a first unit current during a first time period; and a second unit current source including second sub-unit current sources, and configured to output a second unit current during a second time period. The first sub-unit current sources are configured to operate according to first sub-ramp control signals, respectively. The second sub-unit current sources are configured to operate according to second sub-ramp control signals, respectively. n first sub-ramp control signals among the first sub-ramp control signals are activated, and m sub-ramp control signals among the second sub-ramp control signals are activated, n and m being different natural numbers.
H04N 25/78 - Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
H03K 4/48 - Generating pulses having essentially a finite slope or stepped portions having triangular shape having sawtooth shape using as active elements semiconductor devices
A semiconductor measurement apparatus may include an illumination unit configured to irradiate light to the sample, an image sensor configured to receive light reflected from the sample and output multiple interference images representing interference patterns of polarization components of light, an optical unit in a path through which the image sensor receives light and including an objective lens above the sample, and a control unit configured to obtain, by processing the multi-interference image, measurement parameters determined from the polarization components at each of a plurality of azimuth angles defined on a plane perpendicular to a path of light incident to the image sensor. The control unit may be configured to determine a selected critical dimension to be measured from a structure in the sample based on measurement parameters. The illumination unit and/or the optical unit may include a polarizer and a compensator having a ¼ wave plate.
An electronic device includes: one or more processors; a memory storing instructions configured to cause the one or more processors to: install instrumentation points in respective tasks of an application, the instrumentation points including a source instrumentation point installed in a source task and a target instrumentation point installed in a target task, wherein the source task and the target task are configured to execute in parallel on the one or more processors, and wherein each task includes a respective sequence of instructions executable by the one or more processors, and determine a measure of a causal relationship between the source instrumentation point and the target instrumentation point based on observation of a delay in the target instrumentation point induced by a delay amount generated by the source instrumentation point.
Provided is a wafer processing apparatus including a plate having a plurality of support pins configured such that a wafer is mounted on the plurality of support pins and a plurality of vacuum ports positioned between the plurality of support pins, a heater configured to heat the plate, a flow regulator configured to provide a vacuum pressure for fixing the wafer to the plurality of vacuum ports, and configured to adjust a flow rate of a fluid flowing into the plurality of vacuum ports to be a target flow rate, and a chuck controller configured to control the target flow of the fluid set in the flow regulator, wherein the chuck controller is configured to generate a flow control signal for reducing the target flow rate of the fluid and send the flow control signal to the flow regulator during a heating process of the wafer.
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
An image sensor comprises a first sub-pixel comprising a first photoelectric conversion region, a first floating diffusion region, and a first transfer transistor to transfer charges accumulated in the first photoelectric conversion region to the first floating diffusion region; and a second sub-pixel adjacent to the first sub-pixel, and comprising a second photoelectric conversion region, a second floating diffusion region, and a second transfer transistor to transfer charges accumulated in the second photoelectric conversion region to the second floating diffusion region. The first photoelectric conversion region may comprise a first and a second sub-region partitioned by a potential level isolation region that blocks movement of charges, and the first transfer transistor may comprise a first sub-transfer transistor to transfer charges accumulated in the first sub-region to the first floating diffusion region, and a second sub-transfer transistor to transfer charges accumulated in the second sub-region to the first floating diffusion region.
The present disclosure provides semiconductor packages including a heat dissipation structure. In some embodiments, the semiconductor package includes a package substrate, a stacked chip disposed on the package substrate and including a lower chip and an upper chip, a memory chip disposed on the package substrate adjacent to the stacked chip, and an encapsulant encapsulating at least a portion of the stacked chip and the memory chip on the package substrate. An upper surface of the upper chip is exposed from the encapsulant. A dummy silicon chip is in contact with the upper chip on the lower chip.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different main groups of groups , or in a single subclass of , , e.g. forming hybrid circuits
16.
IMPROVEMENTS IN AND RELATING TO LOCALISATION IN A TELECOMMUNICATION NETWORK
A method of performing localisation of a User Equipment, UE, in a telecommunication network is provided. The method comprises receiving from a second network entity a location request, and identifying multiple Quality of Service, QoS, class for location services comprising a plurality of QoS requirements based on the location request.
A semiconductor device includes a first active pattern including a first lower pattern and first sheet patterns; a second active pattern including a second lower pattern and second sheet patterns, a height of the second lower pattern being smaller than a height of the first lower pattern; a first gate structure on the first lower pattern; a second gate structure on the second lower pattern; a first source/drain pattern on the first lower pattern and connected to the first sheet patterns; and a second source/drain pattern on the second lower pattern and connected to the second sheet patterns, wherein a width of an upper surface of the first lower pattern is different from a width of an upper surface of the second lower pattern, and wherein a number of first sheet patterns is different from a number of second sheet patterns.
H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
18.
SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAME
The present disclosure relates to a semiconductor package and a manufacturing method thereof, and a manufacturing method of a semiconductor package according to an embodiment includes: preparing a glass substrate that includes a groove and a hole positioned around the groove; forming a conductive connection member to fill inside the hole of the glass substrate; attaching a semiconductor chip inside the groove of the glass substrate; forming a first redistribution structure for connection with the semiconductor chip and the conductive connection member on a first side of the glass substrate; and forming a second redistribution structure for connection with the conductive connection member on a second side of the glass substrate.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
A semiconductor device may include an active pattern on a substrate; an isolation pattern on the substrate, the isolation pattern covering opposite sidewalls of the active pattern; a liner on the isolation pattern, a liner including a material different from the isolation pattern; a gate structure contacting an upper surface of the active pattern and an upper surface of the liner; and a plurality of channels spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate, each of the plurality of channels extending through the gate structure.
RECOMBINANT MICROORGANISM INCLUDING GENETIC MODIFICATION THAT INCREASES EXPRESSION OF IRON STORAGE PROTEIN WITH HEME STRUCTURE, AND METHOD OF REDUCING CONCENTRATION OF NITROGEN OXIDE IN SAMPLE USING THE SAME
Provided are a recombinant microorganisms having a genetic modification that increases the expression of bacterioferritin, a composition comprising the recombinant microorganism for use in reducing a nitrogen oxide concentration in a sample, and a method of reducing a nitrogen oxide concentration in a sample.
Image sensors and fabrication methods thereof. For example, the image sensor may include a first substrate having a first surface and a second surface that are opposite to each other, a plurality of pixels provided in the first substrate and arranged in pixel groups, each pixel group including four pixels arranged in two columns and two rows, a pixel separation structure in the first substrate and including a pixel group separation part that separates each pixel group from adjacent pixel groups and a pixel separation part that separates the pixels in each pixel group from each other, and a plurality of microlenses on the first surface and respectively overlapping the plurality of pixel groups. Each of the microlenses includes a central part that has a first curvature and an edge part that has a second curvature. The first curvature is less than the second curvature.
A bit line sense amplifier of a semiconductor memory device includes: sense amplifier blocks including a PMOS driver or an NMOS driver that detects and amplifies a signal difference between a bit line and a complimentary bit line, and sequentially arranged in a bit line extending direction; column selection units that connect the bit line and a local input/output line according to a first column selection signal; complimentary column selection units that connect the complimentary bit line and a complimentary local input/output line according to a second column selection signal; column selection lines that transmit the first column selection signal to each of the column selection units; and complimentary column selection lines that transmit the second column selection signal to each of the complimentary column selection units. The column selection units and the complimentary column selection units may be disposed to be distributed between the sense amplifier blocks.
A processor-implemented method includes: generating initial information comprising any one or any combination of any two or more of map information, departure information, and arrival information; generating a plurality of paths by inputting the initial information to a planner ensemble; and training a path distribution estimation model to output a path distribution corresponding to the plurality of paths.
A system and a method are disclosed for determining early termination during an iterative detection and decoding (IDD) procedure. The method may include computing, during the IDD procedure, one or more log-likelihood ratios (LLRs) of one or more cyclic-redundancy checks (CRC), and determining that at least one of the LLRs predict a failure of a CRC check and, in response, terminating the IDD procedure.
Disclosed is a semiconductor memory device including a peripheral gate structure on a substrate, bitlines disposed on the peripheral gate structure and extending in a first direction, a protruding insulating pattern including channel trenches, extending in a second direction intersecting the first direction, channel structures disposed on the bitlines in the channel trenches and including a metal oxide, first wordlines disposed on the channel structures and extending in the second direction, second wordlines disposed on the channel structures, extending in the second direction, and spaced apart from the first wordlines in the first direction, landing pads disposed on the channel structures and connected to the channel structures, pad separation patterns disposed on the protruding insulating pattern and separating the landing pads, first passage patterns connected to the protruding insulating pattern through pad separation patterns and formed of an oxide-based insulating material, and data storage patterns disposed on the landing pads.
A mobile device and a method of controlling the same. A control method according to an embodiment comprises displaying a user interface (UI) screen which includes a plurality of UI elements, detecting a first user input associated with a first UI element among the plurality of UI elements, identifying one or more identification codes associated with the first UI element based on the detecting of the first user input, detecting one or more neighboring devices based on the one or more identification codes, displaying a window which includes one or more UI elements associated with the one or more neighboring devices, detecting a second user input associated with a second UI element among the one or more UI elements, determining a neighboring device associated with the second UI element, among the one or more neighboring devices, as a controlled device controllable through the second UI element, based on detecting of the second user input, and transmitting a control command related to the first UI element to the neighboring device determined as the controlled device.
MULTI-WAVELENGTH SELECTION METHOD FOR OVERLAY MEASUREMENT, AND OVERLAY MEASUREMENT METHOD AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD USING MULTI-WAVELENGTHS
Provided are a method of selecting multi-wavelengths for overlay measurement, for accurately measuring overlay, and an overlay measurement method and a semiconductor device manufacturing method using the multi-wavelengths. The method of selecting multi-wavelengths for overlay measurement includes measuring an overlay at multiple positions on a wafer at each of a plurality of wavelengths within a set first wavelength range, selecting representative wavelengths that simulate the overlay of the plurality of wavelengths, from among the plurality of wavelengths, and allocating weights to the representative wavelengths, respectively.
G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
H01L 21/66 - Testing or measuring during manufacture or treatment
28.
SEMICONDUCTOR MEMORY DEVICE CAPABLE OF SYNCHRONIZING CLOCK SIGNALS IN CS GEARDOWN MODE
A semiconductor device includes a chip select signal flip-flop configured to: latch a chip select signal in-sync with a first propagation clock signal, and output a first chip select enable signal, and latch the chip select signal in-sync with a second propagation clock signal having a phase opposite to a phase of the first propagation clock signal, and output a second chip select enable signal; and a clock control circuit configured to generate the first propagation clock signal and the second propagation clock signal based on a clock signal, and selectively output one of the first propagation clock signal and the second propagation clock signal based on an enable level of the first chip select enable signal and an enable level of the second chip select enable signal.
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
A semiconductor device may include a substrate including an active pattern, a channel pattern on the active pattern, a source/drain pattern, a gate electrode, and an insulation pattern. The channel pattern may include semiconductor patterns that are spaced apart from each other and vertically stacked. A lowermost one of the semiconductor patterns may be a first semiconductor pattern. The source/drain pattern may be connected to the semiconductor patterns. The gate electrode may be on the semiconductor patterns and may include a plurality of inner electrodes below the semiconductor patterns except the first semiconductor pattern. The insulation pattern may be between the first semiconductor pattern and the active pattern. The insulation pattern may include a dielectric pattern and a protection layer. The protection layer may be between the dielectric pattern and the first semiconductor pattern. The protection layer may be between the dielectric pattern and the active pattern.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/24 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only inorganic semiconductor materials not provided for in groups , , or
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
The inventive concept provides a method of removing and collecting particles from a photomask including fabricating the photomask on a substrate, generating a first map indicating locations of particles on a surface of the photomask by inspecting the surface of the photomask using a probe tip, vertically moving the probe tip to a first vertical height that is lower than a height of the particle, horizontally moving the probe tip parallel to the surface of the photomask at the first vertical height, generating a second map indicating locations of particles on the surface of the photomask using the probe tip, vertically moving the probe tip to a second vertical height that is lower than the first vertical height, and horizontally moving the probe tip parallel to the surface of the photomask at the second vertical height.
A semiconductor device includes a substrate including first and second regions; a first active pattern including a first lower pattern and first sheet patterns; a second active pattern including a second lower pattern, a height of the second lower pattern being identical to a height of the first lower pattern, and second sheet patterns; a first gate structure including a first gate insulating film and a first gate electrode; a second gate structure including a second gate insulating film, and a second gate electrode, a width of the second gate electrode being greater than a width of the first gate electrode; a first source/drain pattern on the first lower pattern and connected to the first sheet patterns; and a second source/drain pattern on the second lower pattern and connected to the second sheet patterns, wherein a number of first sheet patterns is smaller than a number of second sheet patterns.
H10B 10/00 - Static random access memory [SRAM] devices
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
32.
SINGLE IMAGE SENSOR FOR RESTORING IMAGES CORRESPONDING TO VARIOUS FIELDS OF VIEW
An image sensor includes a color filter array including a first color filter including a first number of blue pass filtering elements, the first number of red pass filtering elements, and green pass filtering elements in a first pattern, wherein a number of the green pass filtering elements in the first pattern is twice the first number, and a second color filter including a second number of blue pass filtering elements, the second number of red pass filtering elements, and green pass filtering elements in a second pattern, wherein a number of green pass filtering elements in the second pattern is twice the second number, and the second number is greater than the first number. The second color filter may surround an area of the first color filter.
Systems and methods for persistent storage with a dual interface. In some embodiments, a persistent storage device includes: a processing circuit; a cache; and persistent storage. The processing circuit may be configured to perform a method, the method including: receiving a first write request according to a first protocol; saving a data payload of the first write request in a first portion of the cache; receiving a second write request according to a second protocol; and saving a data payload of the second write request in a second portion of the cache.
G06F 12/0831 - Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
G06F 12/0888 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using selective caching, e.g. bypass
G06F 12/0891 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
A black-box fuzzing testing method includes: generating a plurality of testcases; executing a target program based on each of the generated testcases to obtain a plurality of execution results; determining a plurality of execution paths of the target program using the execution results; and determining a code coverage of the target program from the execution paths.
A processor of a wearable device may display, based on identifying a location in a first area based on data of a sensor, a visual object. The processor may be configured to adjust, based on an input indicating selection of the visual object, the state of the camera to a first state for recording media. The processor may be configured to identify whether the location of the wearable device moves to a second area in the first area. The processor may be configured to obtain, based on identifying that the location of the wearable device moves into the second area, media based on the camera of the first state. The present disclosure relates to a metaverse service for enhancing interconnectivity between a real-world object and a virtual object, and the metaverse service may be provided over a network based on 5th generation (5G) and/or 6th generation (6G) communication systems.
G06V 10/764 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using classification, e.g. of video objects
G06V 20/40 - Scenes; Scene-specific elements in video content
H04N 23/667 - Camera operation mode switching, e.g. between still and video, sport and normal or high and low resolution modes
36.
SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
A semiconductor package includes: a first redistribution substrate; a semiconductor chip provided on the first redistribution substrate; a molding material molding the semiconductor chip and the first redistribution substrate; and a second redistribution substrate provided on the molding material, wherein the second redistribution substrate includes: at least one redistribution line; a metal pad; and a dielectric layer molding the at least one redistribution line and the metal pad, wherein the dielectric layer includes a marking region on the metal pad, and the metal pad includes a plurality of concave portions.
A computational storage device (CSD) and a method thereof are provided. The method includes receiving, from a user device, a computational storage (CS) request, identifying the CS request as an attack, comparing a total attack value of the user device to a threshold, wherein the total attack value is based on a number of attacks received from the user device, and identifying the user device as an attacker based on the comparison.
KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY (Republic of Korea)
Inventor
Youn, Chan-Hyun
Kim, Taewoo
Lee, Changha
Jeon, Minsu
Abstract
An electronic device includes a memory configured to store at least one instruction; and at least one processor configured to execute the at least one instruction to: input first data to a first artificial intelligence model including a plurality of convolution blocks sequentially connected with a pooling layer interposed therebetween to obtain a plurality of feature maps that are output by corresponding ones of the plurality of convolution blocks, input the first data and the plurality of feature maps to a second artificial intelligence model including a plurality of local attention blocks sequentially connected to obtain a plurality of attention maps that are output by corresponding ones of the plurality of local attention blocks, output an amplified feature map by amplifying a region corresponding to a last attention map among the plurality of attention maps in a last feature map among the plurality of feature maps, and input the amplified feature map to a classifier to output a classification result for the first data.
G06V 10/771 - Feature selection, e.g. selecting representative features from a multi-dimensional feature space
G06V 10/764 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using classification, e.g. of video objects
According to various embodiments, an electronic device comprises: at least one processor; and memory operatively connected to the at least one processor, wherein the memory may store instructions which, when executed by the at least one processor, cause the electronic device to: obtain, from a kernel, at least one address for a first memory area accessible through the kernel; store the at least one address in a second memory area accessible through a hypervisor; based on obtaining an address stored in a kernel stack from the kernel, identify whether the obtained address is defective, on the basis of the at least one stored address; and restore the defective address using at least one address stored in the second memory area in response to identifying the defect in the address.
A semiconductor package includes a first structure including a first semiconductor chip comprising a first semiconductor integrated circuit, and a second structure on the first structure. The second structure includes a second semiconductor chip including a second semiconductor integrated circuit, a semiconductor pattern horizontally spaced apart from the second semiconductor chip and on a side surface of the second semiconductor chip, an insulating pattern between the second semiconductor chip and the semiconductor pattern, and through-electrode structures. At least one of the through-electrode structures penetrates through at least a portion of the second semiconductor chip or penetrates through the semiconductor pattern. The semiconductor pattern has a first side surface facing the side surface of the second semiconductor chip and a second side surface opposing the first side surface. The second side surface of the semiconductor pattern is vertically aligned with a side surface of the first semiconductor chip.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
41.
ASYMMETRIC NAND GATE CIRCUIT, CLOCK GATING CELL AND INTEGRATED CIRCUIT INCLUDING THE SAME
A clock gating cell is provided. The clock gating cell includes: an inverter circuit configured to generate an inverted clock signal by inverting a clock signal; a first control circuit configured to receive the inverted clock signal, an enable signal, and a scan enable signal, and output a first internal signal at a first node; a second control circuit configured to receive the first internal signal, the clock signal, the enable signal, and the scan enable signal, and output a second internal signal at a second node; and an output driver configured to receive the second internal signal, and output an output clock signal to an output node and a third internal signal to a third node. The first control circuit and the second control circuit are configured to receive the third internal signal at the third node.
G06F 1/08 - Clock generators with changeable or programmable clock frequency
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
42.
METHOD AND APPARATUS FOR LOGGING EVENTS IN COMMUNICATION NETWORKS
A method and an apparatus for logging events in a communication system is provided. The method comprises receiving, from a network function, a request for creating a managed object instance (MOI) of an information object class (IOC) for registering logs associated with a plurality of management services of a communication network. The method further comprises creating a fragment of network resource model (NRM) for logging events associated with the plurality of management services, based on the MOI, wherein the NRM comprises a set of MOIs. Additionally, creating the fragment comprises generating the set MOIs for logging events related to the plurality of management services, wherein the set of MOIs comprise an MOI for registration of a log, an MOI for information of the log, and an MOI for entry of the log. Advantageously, the present disclosure enables logging of events in communication networks.
The disclosure relates to a wireless communication system, in which a method performed by a user equipment includes receiving, from a base station, information configuring a plurality of sounding reference signal (SRS) resources that are related with one channel state information-reference signal (CSI-RS) resource, receiving an SRS resource indicator (SRI) indicating at least one SRS resource from among the plurality of SRS resources, obtaining, based on an implicit precoding being indicated for an uplink channel, precoding information for the uplink channel based on the CSI-RS resource related with a most recently transmitted SRS of the at least one SRS resource indicated by the SRI, and transmitting, to the base station, the uplink channel based on the precoding information.
A semiconductor package includes: a chip-via composite substrate including a substrate, a semiconductor chip, and a plurality of through vias, wherein the substrate has a first surface and a second surface opposite to the first surface and includes a first region and a second region around the first region, wherein the semiconductor chip is provided in the first region and has chip pads and circuit patterns that are electrically connected to the chip pads, and wherein the plurality of through vias is provided in the second region and penetrate the substrate; a first redistribution wiring layer provided on the first surface of the substrate and having first redistribution wirings that are electrically connected to the chip pads and the through vias; and a second redistribution wiring layer provided on the second surface of the substrate and having second redistribution wirings that are electrically connected to the through vias.
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 25/10 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices having separate containers
Broadly speaking, embodiments of the present techniques provide a method for training a machine learning, ML, model to update global and local versions of a model. We propose a novel hierarchical Bayesian approach to Federated Learning (FL), where our models reasonably describe the generative process of clients' local data via hierarchical Bayesian modeling: constituting random variables of local models for clients that are governed by a higher-level global variate. Interestingly, the variational inference in our Bayesian model leads to an optimisation problem whose block-coordinate descent solution becomes a distributed algorithm that is separable over clients and allows them not to reveal their own private data at all, thus fully compatible with FL.
A method for validating a trained artificial intelligence (AI) model on a device is provided. The method includes deploying a validation model generated by applying a plurality of anticipated configurational changes associated with the trained AI model requiring validation. Further, the method includes providing input data to each of the validation model and the trained AI model for receiving an output from each of the validation model and the trained AI model, wherein the output of the validation model is further based on one or more actual configurational deviations that occurred during training of the trained AI model since deployment of the trained AI model on the device. Furthermore, the method includes combining the output of each of the validation model and the trained AI model to validate the trained AI model.
A semiconductor package includes a package substrate including a first pad; a first memory device arranged on the package substrate and including first and second semiconductor chips stacked in a vertical direction; and a first chip connecting member electrically connecting the first semiconductor chip to the package substrate. The first semiconductor chip includes a first cell structure; a first peripheral circuit structure; a first bonding pad; and a first input/output pad electrically connected to the first pad of the package substrate through the first chip connection member. The second semiconductor chip includes a second cell structure; and a second bonding pad connected to the first bonding pad. A part of the first peripheral circuit structure protrudes from a sidewall of the second semiconductor chip so as not to overlap the second semiconductor chip.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
A cooking apparatus includes a case, a cooking chamber formed inside the case, a camera configured to obtain an image inside of the cooking chamber, a transparent member, a camera cooling fan configured to blow air toward the camera, a motor configured to rotate the camera cooling fan, and a controller to be electrically connected to the camera and the motor. The controller is configured to operate the camera to obtain a first image inside of the cooking chamber, configured to identify foreign substance-related information of a lens of the camera or the transparent member based on the first image, and configured to control an operation of the motor to perform a cleaning mode, in which the camera cooling fan is rotated at a first rotation speed for a first rotation time, based on the determining that the foreign substance is present.
H04N 23/81 - Camera processing pipelines; Components thereof for suppressing or minimising disturbance in the image signal generation
F24C 15/00 - DOMESTIC STOVES OR RANGES; DETAILS OF DOMESTIC STOVES OR RANGES, OF GENERAL APPLICATION - Details
H04N 23/52 - Elements optimising image sensor operation, e.g. for electromagnetic interference [EMI] protection or temperature control by heat transfer or cooling elements
49.
SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
Provided is a method of manufacturing a semiconductor package, the method including forming a first wiring structure, coating a high transmittance photoresist on the first wiring structure a plurality of number of times, forming a plurality of openings by exposing and developing the high transmittance photoresist, forming a plurality of conductive posts by filling the plurality of openings with a conductive material, removing the high transmittance photoresist, disposing a semiconductor chip on the first wiring structure, forming an encapsulant surrounding the semiconductor chip and the plurality of conductive posts, and forming a second wiring structure on the encapsulant, wherein the light transmittance of the high transmittance photoresist at a portion where the first wiring structure and the high transmittance photoresist contact each other is greater than or equal to 3.2%.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
Provided is an electronic device including a transceiver configured to output a first transmission signal, a first radio frequency (RF) module configured to amplify the first transmission signal obtained from the transceiver to generate an amplified first transmission signal, a first antenna configured to transmit the amplified first transmission signal, and a main coupler provided outside the first RF module along a transmission path between the first RF module and the first antenna, and configured to output a first coupling signal corresponding to the first transmission signal. The first RF module includes at least one power amplifier configured to amplify the first transmission signal, and a switch configured to connect one of a plurality of input ports, including at least one input port connected to the main coupler and configured to receive the first coupling signal output by the main coupler, with an output port connected to the transceiver.
The present disclosure relates to a 5G or 6G communication system for supporting a higher data transmission rate. In addition, the present disclosure relates to a method carried out by a base station of a wireless communication system, and a device for carrying out same, the method comprising the steps of: determining whether a frequency band operated by a base station uses a bandwidth that is narrower than a preset bandwidth; if a bandwidth that is narrower than the preset bandwidth is used, determining a subcarrier spacing (SCS) that is narrower than a preset SCS; generating a synchronization signal block (SSB) using the determined SCS; and transmitting the SSB, wherein the determined SCS is smaller than 15 kHz.
A disclosed drum-type washing machine having a softening apparatus comprises: a cylindrical water tank accommodating laundry and having a rotating drum; a case for accommodating the water tank; and a softening apparatus having a hardness component remover for removing hardness components from washing water, and a regeneration agent accommodation unit spaced apart from the hardness component remover on opposite sides from a center of the tub, and for accommodating a regeneration agent that regenerates a function of the hardness component remover.
D06F 39/00 - LAUNDERING, DRYING, IRONING, PRESSING OR FOLDING TEXTILE ARTICLES - Details of washing machines not specific to a single type of machines covered by groups
C02F 1/42 - Treatment of water, waste water, or sewage by ion-exchange
D06F 23/02 - Washing machines with receptacles, e.g. perforated, having a rotary movement, e.g. oscillatory movement, the receptacle serving both for washing and for centrifugally separating water from the laundry and rotating or oscillating about a horizontal axis
D06F 34/22 - Condition of the washing liquid, e.g. turbidity
D06F 39/02 - Devices for adding soap or other washing agents
A semiconductor package, comprising: a first redistribution wiring layer including first and second surfaces opposite to each other, wherein the first redistribution wiring layer includes a first chip mounting region and a second chip mounting region adjacent to the first chip mounting region; a connection layer on the first surface of the first redistribution wiring layer; a first semiconductor chip on the first chip mounting region on the connection layer; a second semiconductor chip spaced apart from the first semiconductor chip on the second chip mounting region on the connection layer, wherein the second semiconductor chip includes through electrodes; a molding member on the first and second semiconductor chips on the connection layer; and a second redistribution wiring layer on the molding member, wherein the second redistribution wiring layer is electrically connected to the first redistribution wiring layer through the through electrodes.
H01L 25/10 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices having separate containers
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices
A robot, includes: a driver; a plurality of sensors; a memory; and at least one processor configured to transmit a first signal for identifying a presence or absence of an object within a sensing area of the plurality of sensors through a first sensor operating in the signal transmitting mode from among the plurality of sensors during a first time period, identify, a second sensor to transmit a second signal during a third time period after elapse of the second time period from among the plurality of sensors, transmit the second signal by operating the identified second sensor in the signal transmitting mode, identify a location of the object based on whether a second reflection signal corresponding to the second signal is received at the second sensor, and control the driver to travel by avoiding the object based on the identified location of the object.
A device for gathering image sets includes: N digital cameras including one or more ground truth cameras for capturing high quality ground truth images and one or more target cameras for capturing low quality target images, the N digital cameras being optically coupled via N−1 beam splitters, at least N−1 cameras of the N digital cameras being mounted on automatically adjustable mounts; and at least one computer readable storage device storing instructions executable by at least one processor. The instructions cause the at least one processor to adjust the at least N−1 cameras by actuating the automatically adjustable mounts on which the at least N−1 cameras are mounted; synchronize image capture by the digital cameras; and control the digital cameras to gather sets of N images. The at least N−1 cameras are adjusted based on at least one set of N images of the scene.
An image sensor includes a semiconductor substrate in which a plurality of photo-sensing elements are integrated, an organic active layer on the semiconductor substrate, an interlayer between the organic active layer and the semiconductor substrate, and optionally a color filter layer on the organic active layer. The organic active layer includes a singlet fission material. The interlayer includes a dielectric selected from an oxide, a nitride, oxynitride, fluoride, oxyfluoride, and any combination thereof.
An electronic device includes a display, a rear cover, a first frame including a first portion in which at least one speaker hole is formed in a region and a second portion extending from the first portion in a first direction, a second frame coupled to the second portion of the first frame, a speaker disposed in a space between the second frame and the second portion of the first frame, an acoustic duct formed in the first frame, a film including a conductive pattern, and a wireless communication circuit electrically coupled to the first conductive pattern. The acoustic duct includes a first acoustic duct portion and a second acoustic duct portion, at least one region of the first film covers an entirety of the opening, and the wireless communication circuit is configured to feed power to a point of the first conductive pattern to receive a signal of a first frequency band.
H01Q 1/24 - Supports; Mounting means by structural association with other equipment or articles with receiving set
H01Q 1/38 - Structural form of radiating elements, e.g. cone, spiral, umbrella formed by a conductive layer on an insulating support
H01Q 1/44 - ANTENNAS, i.e. RADIO AERIALS - Details of, or arrangements associated with, antennas using equipment having another main function to serve additionally as an antenna
H04M 1/02 - Constructional features of telephone sets
58.
ELECTRONIC APPARATUS FOR IDENTIFYING A REGION OF INTEREST IN AN IMAGE AND CONTROL METHOD THEREOF
An electronic apparatus includes a memory configured to store a neural network model including a first network and a second network. The electronic apparatus also includes at least one processor connected to the memory. The at least one processor is configured to obtain description information corresponding to a first image by inputting the first image to the first network, obtain a second image based on the description information, obtain a third image representing a region of interest of the first image by inputting the first image and the second image to the second network. The neural network model is a model trained based on a plurality of sample images, a plurality of sample description information corresponding to the plurality of sample images, and a sample region of interest of the plurality of sample images.
An electronic device according to an embodiment includes: a scaling server configured to execute a first event occurring in a first region allocated a plurality of cells, at least one game server configured to execute a second event occurring in at least one second region adjacent to the first region, and at least one processor configured to process the scaling server and the at least one game server. The at least one processor configured to control at least one of the scaling server or the at least one game server so that at least one cell is transferred between the first region and the second region, based on a first load by the first event and a second load by the second event.
A63F 13/77 - Game security or game management aspects involving data related to game devices or game servers, e.g. configuration data, software version or amount of memory
G06F 9/50 - Allocation of resources, e.g. of the central processing unit [CPU]
60.
ELECTRONIC DEVICE MEASURING REFERENCE SIGNAL RECEIVED POWER AND OPERATING METHOD OF THE ELECTRONIC DEVICE
A device may receive a first synchronization signal including at least one first synchronization signal block (SSB) from a serving base station and a second synchronization signal including at least one second SSB from a neighboring base station, where the second synchronization signal overlaps a slot through which data is transmitted from the serving base station. Additionally, the device may measure a first received power and a received reference signal received power (RSRP) of each of the first synchronization signal and the second synchronization signal received on the slot. The device may calculate an effective RSRP corresponding to at least one additional SSB received from the serving base station, the effective RSRP calculated based on a correlation power, where the correlation power is based on a cross correlation between the received RSRP, the first received power, the data, and the at least one additional SSB.
The present disclosure relates to a 5G communication system or a 6G communication system for supporting higher data rates beyond a 4G communication system such as long term evolution (LTE). A method performed by a base station in a wireless communication system may include determining a first synchronization signal block (SSB) beam sweeping pattern, based on distribution of a plurality of user equipments (UEs), transmitting information indicating the first SSB beam sweeping pattern to a neighbor base station and the plurality of UEs, transmitting an SSB to the plurality of UEs, based on the first SSB beam sweeping pattern, receiving information about an SSB beam sweeping pattern of the neighboring base station from the neighbor base station, receiving parameter information for updating the first SSB beam sweeping pattern from a core network, updating the first SSB beam sweeping pattern to a second SSB beam sweeping pattern, based on second location information received in response to a request transmitted to the plurality of UEs, based on the parameter information, transmitting information indicating the second SSB beam sweeping pattern to the neighbor base station and the plurality of UEs, and transmitting an SSB to the plurality of UEs, based on the second SSB beam sweeping pattern.
A semiconductor device includes a first element separation structure, a second element separation structure, and a third element separation structure sequentially disposed along a first direction and extending in a second direction intersecting the first direction; a first active pattern extending in the first direction between the first element separation structure and the second element separation structure; a second active pattern extending in the first direction between the second element separation structure and the third element separation structure and separated from the first active pattern by the second element separation structure; a first gate electrode extending in the second direction on the first active pattern; and a plurality of second gate electrodes extending in the second direction on the second active pattern, wherein a width of the first active pattern in the second direction is greater than a width of the second active pattern in the second direction.
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
63.
INTERNAL VOLTAGE GENERATION CIRCUIT OF SMART CARD AND SMART CARD INCLUDING THE SAME
An internal voltage generation circuit of a smart card to perform fingerprint authentication and a smart card includes a first contact switch, a second contact switch, a switched capacitor converter and a bidirectional switched capacitor converter. The first contact switch selectively switches a contact voltage to a first node based on a first switching enable signal, in a contact mode. The second contact switch selectively switches the contact voltage to a second node based on a second switching enable signal, in the contact mode. The bidirectional switched capacitor converter steps down a first driving voltage of the first node to provide a second voltage to the second node in the contactless mode and either steps down the first driving voltage or boosts a second driving voltage of the second node based on a level of the contact voltage to provide a boosted voltage to the first node in the contact mode.
G06K 19/07 - Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards with integrated circuit chips
G06K 19/077 - Constructional details, e.g. mounting of circuits in the carrier
H02M 3/335 - Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
64.
ELECTRONIC DEVICE, METHOD, AND NON-TRANSITORY COMPUTER READABLE STORAGE MEDIUM CONTROLLING EXECUTABLE OBJECT BASED ON VOICE SIGNAL
An electronic device is provided. The electronic device includes a microphone. The electronic device includes a display. The electronic device includes a processor. The processor is configured to display, via the display, a screen including a plurality of executable objects. The processor is configured to enable the microphone for the executable object based on an executable object focused on among the plurality of executable objects, and display at least one visual object indicating that the microphone is enabled for receiving an input on the executable object among the plurality of executable objects, via the display. The processor is configured to identify whether a voice signal obtained via the microphone while the at least one visual object is displayed corresponds to a voice command allocated to the executable object. The processor is configured to execute a function of the executable object associated with the voice command, based on the voice signal corresponding to the voice command.
G06F 3/01 - Input arrangements or combined input and output arrangements for interaction between user and computer
G06F 3/04817 - Interaction techniques based on graphical user interfaces [GUI] based on specific properties of the displayed interaction object or a metaphor-based environment, e.g. interaction with desktop elements like windows or icons, or assisted by a cursor's changing behaviour or appearance using icons
G06F 3/0488 - Interaction techniques based on graphical user interfaces [GUI] using specific features provided by the input device, e.g. functions controlled by the rotation of a mouse with dual sensing arrangements, or of the nature of the input device, e.g. tap gestures based on pressure sensed by a digitiser using a touch-screen or digitiser, e.g. input of commands through traced gestures
65.
METHOD AND APPARATUS FOR TRANSMITTING DATA TO A NETWORK NODE IN A WIRELESS COMMUNICATION SYSTEM
A method of operating a first node in a wireless communication network is provided. The method comprises: receiving an ingress data packet; determining routing; and transmitting the ingress data packet. Determining routing may comprise determining a next hop node for the ingress data packet taking account of first level routing information indicating target next hop nodes. Alternatively, determining routing may comprise determining, for a target next hop node, a channel on which to transmit the ingress data packet taking account of second level routing information.
H04W 40/22 - Communication route or path selection, e.g. power-based or shortest path routing using selective relaying for reaching a BTS [Base Transceiver Station] or an access point
H04W 28/02 - Traffic management, e.g. flow control or congestion control
66.
OVERLAY MEASURING METHOD AND SYSTEM, AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE USING THE SAME
In an overlay measurement method, an overlay mark having programmed overlay values is provided. The overlay mark is scanned with an electron beam to obtain a voltage contrast image. A defect function that changes according to the overlay value is obtained from voltage contrast image data. Self-cross correlation is performed on the defect function to determine an overlay.
G01B 15/00 - Measuring arrangements characterised by the use of electromagnetic waves or particle radiation, e.g. by the use of microwaves, X-rays, gamma rays or electrons
67.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A method of manufacturing a semiconductor device, includes forming a mask layer on a semiconductor structure having a plurality of gate lines and a plurality of intergate insulating portions, forming an opening that exposes a cut region of the plurality of gate lines in the mask layer, forming a separation hole by removing a portion of a gate capping layer exposed by the opening, forming a pyrolysis material pattern in the separation hole, forming an etch stop layer on an upper surface of the mask layer and on a side wall portion of the separation hole from which the pyrolysis material pattern is removed, while the pyrolysis material pattern is decomposed and removed, and removing a portion of the gate electrode exposed by the separation hole using the etch stop layer.
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
An apparatus includes a communication interface configured to receive a bitstream for a compressed video and a processor operably coupled to the communication interface. The processor is configured to identify a video format for the compressed video. The processor is also configured to determine, from one or more of at least one signaling element and the identified video format, a displacement data packing arrangement. The processor is also configured to retrieve displacement data according to the determined displacement data packing arrangement.
H04N 19/463 - Embedding additional information in the video signal during the compression process by compressing encoding parameters before transmission
H04N 19/136 - Incoming video signal characteristics or properties
H04N 19/186 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being a colour or a chrominance component
A semiconductor package includes a first semiconductor chip including a first wiring layer including a first wiring structure and providing a first rear surface, and a first through via for first through via for power electrically connected to the first wiring structure; and a second semiconductor chip including a second wiring layer including a second wiring structure and providing a second rear surface, and a second through via for second through via for power electrically connected to the second wiring structure, wherein the first and second semiconductor chips have different widths, wherein the first semiconductor chip receives power through the first wiring structure and the first through via for first through via for power, wherein the second semiconductor chip receives power through the second wiring structure and the second through via for second through via for power.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 25/10 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices having separate containers
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
70.
STORAGE DEVICE AND OPERATING METHOD OF STORAGE CONTROLLER
A storage device and an operating method thereof are provided. The storage device includes a non-volatile memory and a storage controller. The storage controller includes a command and address generator, an error detection module, and an interface circuit. The command and address generator generates a first command, an address, and a second command, the second command including an error detection signal for detecting a communication error in the first command and the address. The error detection module generates the error detection signal from the first command and the address. The interface circuit sequentially transmits the first command, the address, and the second command to the non-volatile memory. The first command indicates a type of a memory operation to be performed in the non-volatile memory, and the second command corresponds to a confirm command.
A semiconductor package includes a semiconductor chip including a semiconductor substrate having a first surface and a second surface opposite to the first surface, a chip pad located on the first surface and including a conductive layer, a support pad positioned on the first surface, spaced apart from the chip pad and including an insulating layer, a support bump connected to the support pad, a wiring substrate disposed to face the semiconductor substrate, a support bonding on trace (BOT) pad disposed on the wiring substrate and bonded to the support bump, and a dummy area disposed on the wiring substrate and spaced apart from the support BOT pad.
An example electronic device including a power supply circuit may include a battery; a display module including a display panel; a regulator; a power supply circuit configured to: based on an input voltage of the battery, provide a first voltage and a second voltage to the display module, and provide a third voltage to the regulator; and a switch control circuit configured to: control a switching operation of the power supply circuit, wherein the power supply circuit includes: a first power circuit and a second power circuit, wherein the first power circuit includes multiple switch elements, a first capacitor, a second capacitor, a third capacitor, and a first inductor, and is configured to: for a first time interval, based on a drive signal of the switch control circuit, charge the first capacitor and the second capacitor, based on a current of the first inductor and discharge the third capacitor to provide a first output current to the display module, and for a second time interval, based on a drive signal of the switch control circuit, charge the third capacitor and discharge the first capacitor and the second capacitor to provide the first output current and a second output current to the display module, and wherein the second power circuit is configured to: convert a voltage level of the input voltage of the battery to provide a second voltage to the display module.
G09G 3/3225 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
73.
APPARATUS AND METHOD OF ACQUIRING IMAGE BY EMPLOYING COLOR SEPARATION LENS ARRAY
INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY (Republic of Korea)
Inventor
Lee, Sangyun
Kang, Moongi
Yun, Seokho
Kim, Jonghyun
Jeong, Kyeonghoon
Abstract
An apparatus for acquiring images includes an image sensor and a signal processor. The image sensor may include a sensor substrate and a color separation lens array, wherein the sensor substrate includes a plurality of photo-sensing cells, and the color separation lens array may separate an incident light into a plurality of lights having different wavelengths and forms a phase distribution for condensing the plurality of lights having the different wavelengths on adjacent photo-sensing cells of the plurality of photo-sensing cells. The signal processor may perform deconvolution on sensing signals of the plurality of photo-sensing cells to obtain a sub-sampled image, perform demosaicing to restore a full resolution image having a full resolution from the sub-sampled image, and correct a color of the full resolution image using a point spread function (PSF) of the color separation lens array.
H04N 9/64 - Circuits for processing colour signals
H04N 23/84 - Camera processing pipelines; Components thereof for processing colour signals
H04N 23/88 - Camera processing pipelines; Components thereof for processing colour signals for colour balance, e.g. white-balance circuits or colour temperature control
H04N 25/13 - Arrangement of colour filter arrays [CFA]; Filter mosaics characterised by the spectral characteristics of the filter elements
74.
TERMINAL AND BASE STATION SUPPORTING MULTIPLE TRANSMISSION CONFIGURATION INDICATOR STATES AND OPERATING METHODS THEREOF
An operating method of a terminal to communicate with a base station, includes: detecting at least one overlapped third control channel element (CCE) in a plurality of first CCEs included in first search spaces corresponding to a first physical downlink control channel (PDCCH) received from a first transmission and reception point (TRP) of the base station, and in a plurality of second CCEs included in second search spaces corresponding to a second PDCCH received from the first TRP and a second TRP of the base station; determining, based on the at least one overlapped third CCE, object CCEs from the plurality of first CCEs and the plurality of second CCEs; and performing channel estimation of the object CCEs by using a first memory.
H04W 72/232 - Control channels or signalling for resource management in the downlink direction of a wireless link, i.e. towards a terminal the control data signalling from the physical layer, e.g. DCI signalling
H04W 72/56 - Allocation or scheduling criteria for wireless resources based on priority criteria
H04W 76/20 - Manipulation of established connections
75.
SPEAKER MODULE AND ELECTRONIC DEVICE INCLUDING THE SAME
A speaker module includes a yoke plate, a first speaker including a first magnet coupled to the yoke plate, a diaphragm spaced apart from the yoke plate and a first coil coupled to the diaphragm, and a second speaker including a housing coupled to the yoke plate and on a side of the first speaker, a second coil provided in the housing and coupled to the yoke plate, and a second magnet spaced apart from the second coil in the housing and coupled to the housing.
An electronic device includes processing circuitry configured to calculate an intra metric based on cross correlation of first reference signal symbols (RSs) included in a first precoding resource block group (PRG) to which a target resource element (RE) belongs, calculate an inter metric based on cross correlation of one or more second RSs and one or more among the first RSs, the one or more second RSs being included in a second PRG adjacent to the first PRG along a frequency axis of a physical channel, the one or more second RSs being in proximity to the target RE, and the physical channel being received from a base station, compare a first ratio between the intra metric and the inter metric with a threshold ratio to obtain a comparison result, and determine a channel estimation mode with respect to the target RE based on the comparison result.
A digital signal processing circuit includes an analog gain compensator that compensates for an analog gain of a baseband signal including a plurality of component carriers (CCs) to output a compensated baseband signal; an analog-to-digital converter (ADC) that converts the compensated baseband signal into a first digital signal; a plurality of filtering circuits that generate a second digital signal from the first digital signal; and a control circuit. Each filtering circuit sequentially filters the first digital signal so that a corresponding one of the second digital signals retains one CC among the CCs, compensates for a digital gain, and a performs down-sampling. The control circuit generates an analog gain control signal for controlling the analog gain based on the second digital signals and a digital gain control signal for controlling the digital gain.
A processor-implemented method with molecular dynamics simulation includes: setting a precision of first data used for a molecular dynamics simulation to be a first precision; setting a precision of second data used for the molecular dynamics simulation to be a second precision that is different from the first precision; and conducting the molecular dynamics simulation based on the first data of the first precision and the second data of the second precision.
G16C 10/00 - Computational theoretical chemistry, i.e. ICT specially adapted for theoretical aspects of quantum chemistry, molecular mechanics, molecular dynamics or the like
79.
METHOD AND DEVICE FOR SUPPORTING ENERGY SAVING IN WIRELESS COMMUNICATION SYSTEM
The disclosure relates to a 5G communication system or a 6G communication system for supporting higher data rates beyond a 4G communication system such as LTE. A method performed by a BS in a wireless communication system includes transmitting, to a UE, via an RRC signaling, first information configuring a DTX for an energy saving of the base station; transmitting, to the UE, DCI indicating an activation or deactivation of the DTX; and transmitting, to the UE, a downlink signal based on the activation or deactivation of the DTX.
A method of measuring an overlay offset, the method includes: providing a substrate including a lower pattern and an upper pattern, wherein the lower pattern is disposed in a cell area, and the upper pattern is disposed on the lower pattern; acquiring a first piece of overlay information about a first position of the lower pattern and a second position of the upper pattern by detecting a pupil image of a joint position that is between the upper pattern and the lower pattern; detecting an overlay offset of the second position of the upper pattern relative to the first position of the lower pattern through Zernike polynomial modeling; and acquiring compensation overlay information on the upper pattern from the overlay offset of the second position, wherein the overlay offset includes a radial tilting component.
An antenna module, according to various embodiments, may comprise: a first layer including a first etching region, a first via pad disposed to be spaced apart from an edge of the first etching region, and a first via hole disposed on one surface of the first via pad; and a second layer stacked on one surface of the first layer, and including a second etching region, a plurality of second via pads disposed to be spaced apart from an edge of the second etching region, a plurality of second via holes disposed on one surface of the plurality of second via pads, and a plurality of second dividing lines electrically connecting the plurality of second via pads.
Seoul National University R&DB Foundation (Republic of Korea)
Inventor
Shin, Hoon
Lee, Jaewook
Kim, Donghwee
Park, Rihae
Abstract
A memory device and an operating method of a memory controller are described in which the operating method includes determining that a NOT operation for data of a cell is to be performed by the memory device; forming, in a bit line connected to the cell, a reference voltage between a first voltage corresponding to the data and a second voltage corresponding to inversion data of the data; forming, in the bit line, a third voltage between the second voltage and the reference voltage by connecting the bit line and a bit line bar; forming the reference voltage in the bit line bar; and sensing the inversion data based on the third voltage formed in the bit line and the reference voltage formed in the bit line bar, wherein the inversion data comprises an output of the NOT operation for the data of the cell.
G11C 7/12 - Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
The present disclosure relates to a fifth generation (5G) communication system or a sixth generation (6G) communication system for supporting higher data rates beyond a 4G communication system such as long term evolution (LTE). In a wireless communication system, a method performed by a base station includes identifying a delay time caused by a radio unit (RU) buffer, determining an RIS offset value for synchronization of signals transmitted to a reconfigurable intelligent surface (RIS), based on the delay time caused by the RU buffer, transmitting, to the RIS, a first signal to be transmitted to a terminal through a reflection plane of the RIS at a first time point, and transmitting, to the RIS, a second signal for controlling a reflection pattern of the RIS at a second time point to which the RIS offset value is applied.
H04B 7/04 - Diversity systems; Multi-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas
84.
DEVICE AND METHOD TO MINIMIZE OFF-CHIP ACCESS BETWEEN HOST AND PERIPHERALS
A near-memory processing unit is configured to compress a page present in a normal memory space of a memory when receiving a swap-out command from a host, allocate a memory area in which the compressed page is to be stored in a compressed memory space which is a memory area previously allocated by the host, copy the compressed page into the allocated memory area, generate an entry corresponding to the compressed page, and insert the generated entry into an entry tree.
A semiconductor package includes a substrate. A pattern layer is disposed on a first surface of the substrate. The pattern layer includes a plurality of pads and a plating wire positioned between adjacent pads of the plurality of pads. A first protection layer is disposed on the first surface of the substrate to cover the pattern layer and expose the plurality of pads. At least one pad of the plurality of pads is physically separated from the plating wire.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
86.
LIGHTING APPARTUS AND METHOD OF CONTROLLING THE SAME
A lighting apparatus including a lighting module configured to emit light; and at least one processor configured to determine a color and a brightness of a current scene of content displayed on a display apparatus, and to control the lighting module to emit, in a space in which the display apparatus is located, light with a color and brightness corresponding to the determined color and brightness of the current scene of the content.
In one embodiment, a system includes a sensor and an airflow generator coupled to an airflow guide configured to direct airflow from the airflow generator toward and past the sensor. The system includes one or more processors and a non-transitory computer readable storage media embodying instructions coupled to the one or more processors, the one or more processors operable to execute the instructions to acquire data about an operational state of the system, wherein the operational state is related to at least one air contaminant generated by the system; and to control the airflow from the airflow generator based on the data about the operational state of the system.
A storage device includes a non-volatile memory device that includes memory blocks each including one or more memory cells, a combo integrated circuit (IC) that includes a temperature sensor and a memory, and a controller that is connected with the combo IC through first channels and controls the non-volatile memory device to write or read data in or from selected memory cells. When the controller determines that a first event occurs based on temperature data read from the combo IC, the controller records first event data in the memory of the combo IC. In a first operation mode, the combo IC outputs the first event data to the controller through the first channels. In a second operation mode, under control of an external host, the combo IC outputs the first event data to the external host through second channels different from the first channels.
An electronic device may include at least one antenna, at least one RF circuit including at least one RFIC, at least one PA, and at least one divider, a connection part, and at least one processor operatively connected to the connection part and the at least one RF circuit. The at least one processor may be configured to turn off the at least one PA based on a connection between the electronic device and an external electronic device (102; 200), convert, via the at least one RFIC, data for transmission to the external electronic device into an RF signal, and direct the RF signal to the connection part via the at least one divider, the RF signal being directed to the external electronic device via the connection part.
A method performed by a terminal in a wireless communication system is provided. The method includes receiving, from at least one other terminal, at least one physical sidelink shared channel (PSSCH), in response to the receiving of the at least one PSSCH, determining the number of at least one physical sidelink feedback channel (PSFCH) based on the maximum number of the at least one PSFCH for simultaneous transmission, and transmitting, to the at least one other terminal, one or more PSFCHs, based on the number of the at least one PSFCH.
H04W 52/24 - TPC being performed according to specific parameters using SIR [Signal to Interference Ratio] or other wireless path parameters
H04W 52/36 - Transmission power control [TPC] using constraints in the total amount of available transmission power with a discrete range or set of values, e.g. step size, ramping or offsets
A method performed by a user equipment (UE) in a wireless communication system is provided. The method includes transmitting, to an access and mobility function (AMF), a registration request message for moving to a first public land mobile network (PLMN) from a second PLMN, receiving, from the AMF, a registration accept message including first single-network slice selection assistance information (S-NSSAI) corresponding to the first PLMN of the AMF, determining whether second S-NSSAI associated with a protocol data unit (PDU) session established for the UE matches to the first S-NSSAI, wherein the second S-NSSAI corresponds to the second PLMN, and locally updating the PDU session based on a result of the determining.
A plasmonic device including a support layer extending along a first direction and a second direction, an insulating layer on the support layer, and a plasmonic layer on the insulating layer and defining a cavity extending along the first direction, the cavity having a three-dimensionally (3D) tapered structure and being configured to propagate an electromagnetic field along the first direction and to concentrate the electromagnetic field at a tip of the cavity, wherein the support layer, the insulating layer, and the plasmonic layer define an opening therein, the opening being at the tip of the cavity and being configured to pass-through target molecules of a solution present on the plasmonic layer.
A system and a method are disclosed for tracking a position of a body. The system and method including the steps of receiving combined movement data, the combined movement data including first movement data of the body and second movement data of an object connected to the body, wherein the second movement data is data of a movement occurring relative to the body; transforming the first movement data using a first transformation technique; transforming the second movement data using a second transformation technique that is different than the first transformation technique; determining a velocity estimation bias of the body based on a combination of the transformed first movement data and the transformed second movement data; and generating a velocity estimation of the body with the determined velocity estimation bias of the body.
G01S 19/39 - Determining a navigation solution using signals transmitted by a satellite radio beacon positioning system the satellite radio beacon positioning system transmitting time-stamped messages, e.g. GPS [Global Positioning System], GLONASS [Global Orbiting Navigation Satellite System] or GALILEO
Disclosed is a semiconductor package comprising lower and upper structure. The lower structure includes a first semiconductor substrate, first through vias vertically penetrating the first semiconductor substrate, first signal pads connected to the first through vias, first dummy pads between the first signal pads and electrically separated from the first through vias, and a first dielectric layer surrounding the first signal pads and the first dummy pads. The upper structure includes a second semiconductor substrate, second signal pads and second dummy pads, and a second dielectric layer surrounding the second signal pads and the second dummy pads. The first signal pad is in contact with one of the second signal pads. The first dummy pad is in contact with one of the second dummy pads. A first interval between the first dummy pads is 0.5 to 1.5 times a second interval between the first signal pads.
Provided is a flow path switching unit of a dryer configured to dry a drying material. The flow path switching unit includes a body portion, and a flow path guide dividing an internal space of the body portion to selectively form one of a first flow path of air for drying the drying material and a second flow path of air for dehumidifying outside air, according to an arrangement position of the body portion, and at a first position, the path switching unit provides the first flow path to guide air from a drum of the dryer toward a heat exchanger of the dryer, and at a second position, the path switching unit provides the second flow path to guide the outside air introduced from an outside of the dryer.
Provided is a plasma control method including applying gas to a chamber having a wafer loaded therein, generating plasma by applying both radio frequency (RF) power associated with a first voltage at a first frequency and a second voltage at a second frequency that is lower than the first frequency to the chamber for a first time, cutting off the RF power after the first time elapses, continuously applying the second voltage of the second frequency to the chamber for a second time, cutting off the second voltage after the second time elapses, continuously maintaining an off state of the RF power and an off state of the voltage for a third time, and performing an etching process on the wafer by using the plasma formed by the RF power and the second voltage after the third time elapses, wherein the RF power is a sine wave, and the second voltage is a square wave of a periodic pulse form.
A method performed by a distributed unit (DU) in a wireless communication system is provided. The method includes identifying a subblock in one section. The method includes generating a control plane (C-plane) message including section extension information including modulation compression information corresponding to the subblock. The method includes transmitting, to a radio unit (RU), the C-plane message through a fronthaul interface.
An electronic device includes a communication circuit, and at least one processor connected to the communication circuit. The at least one processor may be configured to broadcast a device identification (ID) of the electronic device and an Internet protocol (IP) address of the electronic device through the communication circuit. The at least one processor may be configured to receive a token encrypted by an external electronic device and data of the external electronic device through the communication circuit. The at least one processor may be configured to decrypt the encrypted token by using a private key of the electronic device. The at least one processor may be configured to transmit the data of the external electronic device to a server in a cloud by using the decrypted token through the communication circuit.
H04L 9/32 - Arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system
A circuit includes: an overcurrent limiting (OCL) detector configured to detect whether a level of an inductor current reaches an OCL level and to generate an OCL detection voltage; a control loop circuit configured to generate a reset voltage by comparing a ramp voltage reflecting the level of the inductor current with an error voltage generated based on an operating condition that is out of a preset operating condition; an adaptive OCL controller configured to generate an OCL control current by counting a number of pulses of the OCL detection voltage and a number of pulses of the reset voltage; an oscillator configured to generate an oscillation voltage wherein a frequency of the oscillation voltage varies based on a magnitude of the overcurrent limit control current; and a switching transistor for switching the inductor current based on the oscillation voltage.
An electronic device includes: a communication interface; and at least one processor configured to: maintain an inactivated state of a Peer-to-Peer (P2P) engine, and control a Neighbor Awareness Networking (NAN) engine in an activated state, generate sync complex data for a terminal device to search for the electronic device, by adding P2P Information Element (IE) data to sync beacon data, and control the communication interface to output the sync complex data using a predetermined cycle in a predetermined discovery window section through a discovery window channel.
patents
