Sony Semiconductor Solutions Corporation

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H01L 27/146 - Imager structures 1,586
H04N 5/369 - SSIS architecture; Circuitry associated therewith 822
H04N 5/374 - Addressed sensors, e.g. MOS or CMOS sensors 345
H04N 5/3745 - Addressed sensors, e.g. MOS or CMOS sensors having additional components embedded within a pixel or connected to a group of pixels within a sensor matrix, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components 337
H04N 5/378 - Readout circuits, e.g. correlated double sampling [CDS] circuits, output amplifiers or A/D converters 271
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1.

PHOTODETECTION ELEMENT

      
Application Number JP2023036709
Publication Number 2024/085018
Status In Force
Filing Date 2023-10-10
Publication Date 2024-04-25
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Okabe, Yuta
  • Takizawa, Syuuiti
  • Enoki, Osamu
  • Murata, Masaki
  • Hirano, Yoshiyuki

Abstract

A first photodetection element (10) according to one embodiment of the present disclosure comprises a first electrode (11), a second electrode (13) that is arranged opposite the first electrode (11), and a photoelectric conversion layer (12) that is arranged between the first electrode (11) and the second electrode (13), includes fluorine and binary semiconductor nanoparticles that include indium, and has an indium/fluorine atom count ratio of 100–150.

IPC Classes  ?

  • H01L 31/08 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
  • H01L 27/146 - Imager structures
  • H10K 39/32 - Organic image sensors

2.

IMAGE PROCESSING DEVICE, IMAGE PROCESSING METHOD, AND RECORDING MEDIUM

      
Application Number JP2023034009
Publication Number 2024/084879
Status In Force
Filing Date 2023-09-20
Publication Date 2024-04-25
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Hosoi, Izumu

Abstract

An image processing device includes circuitry that recognizes and extracts an object included in a captured image, and that converts, using an artificial intelligence (AI) model, a region image including the object to generate a feature image. The circuitry generates a mask image by combining the captured image with the feature image.

IPC Classes  ?

  • G06F 21/32 - User authentication using biometric data, e.g. fingerprints, iris scans or voiceprints
  • G06F 21/62 - Protecting access to data via a platform, e.g. using keys or access control rules

3.

PHOTODETECTOR, ELECTRONIC APPARATUS, AND OPTICAL ELEMENT

      
Application Number JP2023036440
Publication Number 2024/084991
Status In Force
Filing Date 2023-10-05
Publication Date 2024-04-25
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Katono, Haruka
  • Toumiya, Yoshinori
  • Saito, Hiroshi
  • Moriya, Yusuke

Abstract

There is provided a photodetector. The photodetector includes a light guide including a plurality of structures each having a size equal to or less than a wavelength of incident light, a first material, a second material, wherein a combination of the first material and the second material is provided above and/or between the plurality of structures and wherein the first material and the second material each has a refractive index different from a refractive index of the plurality of structures and a photoelectric converter that photoelectrically converts light incident via the light guide.

IPC Classes  ?

4.

DISPLAY DEVICE

      
Application Number JP2023030926
Publication Number 2024/084815
Status In Force
Filing Date 2023-08-28
Publication Date 2024-04-25
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Hanyu, Yuichiro

Abstract

This display device is provided with: a thin-film transistor that has a gate electrode and a first main electrode and second main electrode as a pair provided on the sides of the gate electrode in a gate length direction; a storage capacitor that is provided in a region overlapping the thin-film transistor and is electrically connected to the first main electrode; a first light-blocking body that is provided between the first main electrode and the storage capacitor and provided between the gate electrode and the first main electrode, and blocks incident light in the gate length direction; and a second light-blocking body that is provided between the second main electrode and the storage capacitor and provided between the gate electrode and the second main electrode, and blocks incident light in the gate length direction.

IPC Classes  ?

  • G02F 1/1368 - Active matrix addressed cells in which the switching element is a three-electrode device
  • G09F 9/30 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements

5.

SEMICONDUCTOR DEVICE

      
Application Number JP2023033323
Publication Number 2024/084865
Status In Force
Filing Date 2023-09-13
Publication Date 2024-04-25
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Nonaka, Yasuhiro
  • Akiyama, Kentaro
  • Ono, Toshiaki

Abstract

A semiconductor device comprising: a first semiconductor element having, in one surface thereof, a pixel region in which a plurality of pixels have been disposed; a second semiconductor element mounted on said surface in an area outside the pixel region and having a first circuit electrically connected to the pixels; and a third semiconductor element mounted on the reverse side of the second semiconductor element from the first semiconductor element and having a second circuit electrically connected to the pixels.

IPC Classes  ?

6.

PHOTODETECTION ELEMENT AND ELECTRONIC APPARATUS

      
Application Number JP2023035566
Publication Number 2024/084921
Status In Force
Filing Date 2023-09-29
Publication Date 2024-04-25
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Ohkawa Takeshi
  • Oyakawa Takeshi
  • Watanabe Akihiro
  • Sekiya Akito
  • Luo Dan

Abstract

[Problem] To provide a photodetection element and an electronic apparatus which can suppress a degradation in measurement accuracy due to a temperature change. [Solution] In order to address the problem, provided is a photodetection element which comprises: a photodiode which performs photoelectric conversion on incident light and outputs a photocurrent; and a control circuit which controls to change the potential of one end of the photodiode according to a temperature pertaining to the photodiode.

IPC Classes  ?

  • G01S 7/497 - Means for monitoring or calibrating
  • H04N 25/773 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising A/D, V/T, V/F, I/T or I/F converters comprising photon counting circuits, e.g. single photon detection [SPD] or single photon avalanche diodes [SPAD]
  • H01L 31/107 - Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier working in avalanche mode, e.g. avalanche photodiode
  • H01L 31/10 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by at least one potential-jump barrier or surface barrier, e.g. phototransistors

7.

DISPLAY APPARATUS AND ELECTRONIC DEVICE

      
Application Number JP2023033885
Publication Number 2024/084876
Status In Force
Filing Date 2023-09-19
Publication Date 2024-04-25
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Toyomura, Naobumi
  • Yoshida, Mayuko

Abstract

One purpose of the present invention is, for example, to improve contrast and reduce size of a display apparatus. Provided is a display apparatus including a pixel circuit having a light-emitting element, a first transistor that controls a current flowing through the light-emitting element in accordance with a voltage based on a pixel signal inputted via a signal line, and a second transistor and first capacitor connected in series between a node at a signal line potential and a node at an anode potential of the light-emitting element.

IPC Classes  ?

  • G09G 3/3233 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
  • G09G 3/20 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix

8.

PHOTODETECTOR

      
Application Number JP2023036586
Publication Number 2024/085005
Status In Force
Filing Date 2023-10-06
Publication Date 2024-04-25
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Yokogawa, Sozo

Abstract

A photodetector includes a wavelength separation structure including materials having different refractive indices. The materials are planarly and discretely provided for each of first pixels and second pixels on a first surface of a semiconductor substrate. The wavelength separation structure separates incident light on the first pixel into a first wavelength component and a wavelength component other than the first wavelength component and selectively guides the first wavelength component to the first pixel and separates incident light on the second pixel into a second wavelength component and a wavelength component other than the second wavelength component and selectively guides the second wavelength component to the second pixel.

IPC Classes  ?

9.

SIGNAL PROCESSING DEVICE, SIGNAL PROCESSING METHOD, AND STORAGE MEDIUM

      
Application Number JP2023036758
Publication Number 2024/085023
Status In Force
Filing Date 2023-10-10
Publication Date 2024-04-25
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Oniki, Kazumasa

Abstract

An image processing device includes processing circuitry configured to receive information indicating a single image, calculate respective densities for each person detected in the single image, select a target person from one or more people detected in the single image, determine whether another person of the one or more people in the single image overlaps the target person, and in response to a determination that the another person overlaps the target person, calculate a density for the target person based on the overlap, and output crowd density information for at least part of the single image, wherein the crowd density information for the at least part of the single image corresponds to a density of one or more people throughout the at least part of the single image and is based on a combination of the calculated density of the one or more people in the at least part of the single image.

IPC Classes  ?

  • G06V 20/52 - Surveillance or monitoring of activities, e.g. for recognising suspicious objects

10.

INFORMATION PROCESSING APPARATUS, PROGRAM, AND INFORMATION PROCESSING METHOD

      
Application Number JP2023035683
Publication Number 2024/084925
Status In Force
Filing Date 2023-09-29
Publication Date 2024-04-25
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Kurokawa, Tsubasa

Abstract

An information processing apparatus includes, a matching circuit that receives a first image indicating a field of view in a prescribed space based on three-dimensional point cloud data that represents the prescribed space by a point cloud and a second image captured in the prescribed space, and matches the second image and the first image, and a position information providing circuit that generates second position information based on first position information about an origin of the field of view indicated by the first image matched with the second image and provides the second position information to update the three-dimensional point cloud data.

IPC Classes  ?

  • G06T 7/73 - Determining position or orientation of objects or cameras using feature-based methods
  • G06T 7/80 - Analysis of captured images to determine intrinsic or extrinsic camera parameters, i.e. camera calibration
  • G06T 17/20 - Wire-frame description, e.g. polygonalisation or tessellation

11.

SOLID-STATE IMAGING DEVICE AND ELECTRONIC DEVICE

      
Application Number JP2023034018
Publication Number 2024/084880
Status In Force
Filing Date 2023-09-20
Publication Date 2024-04-25
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Nonaka Shin

Abstract

The present invention suppresses mixing of light. The present invention provides a solid-state imaging device that comprises a pixel array part in which a plurality of pixels including a pixel that is provided with a plurality of photoelectric conversion elements with respect to one on-chip lens are two-dimensionally arranged, wherein: the pixels each comprise a control member; the control member is composed of a first member which has a first refractive index and a second member which has a second refractive index that is lower than the first refractive index; the on-chip lens, the first member, the second member and the photoelectric conversion elements are sequentially stacked in this order; the second member has a first surface that faces the first member, and a second surface that faces the photoelectric conversion elements; the first surface comprises a projected part which protrudes toward the on-chip lens, or a recessed part which is recessed toward the photoelectric conversion elements; and in cases where the first surface comprises the recessed part, the surface is provided with a plurality of relief parts.

IPC Classes  ?

12.

PHOTODETECTION DEVICE, DISTANCE MEASUREMENT DEVICE, AND METHOD FOR CONTROLLING PHOTODETECTION DEVICE

      
Application Number JP2023030081
Publication Number 2024/084792
Status In Force
Filing Date 2023-08-22
Publication Date 2024-04-25
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Luo, Dan
  • Umakoshi, Keisuke
  • Oba, Kenji
  • Maekawa, Yuya

Abstract

The present invention reduces the circuit area in a photodetection device in which a plurality of pixels are arranged. A first detection circuit detects the incidence of photons on the basis of the voltage of one of the anode and cathode of a first photoelectric conversion element during a period that is not a predetermined detection halt period. A second detection circuit detects the incidence of photons on the basis of the voltage of one of the anode and cathode of a second photoelectric conversion element during a period that is not the detection halt period. A shared circuit controls the voltage of a gating pulse indicating the detection halt period.

IPC Classes  ?

  • H04N 25/773 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising A/D, V/T, V/F, I/T or I/F converters comprising photon counting circuits, e.g. single photon detection [SPD] or single photon avalanche diodes [SPAD]
  • G01S 17/10 - Systems determining position data of a target for measuring distance only using transmission of interrupted, pulse-modulated waves
  • G01S 17/894 - 3D imaging with simultaneous measurement of time-of-flight at a 2D array of receiver pixels, e.g. time-of-flight cameras or flash lidar
  • H01L 31/107 - Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier working in avalanche mode, e.g. avalanche photodiode
  • H04N 25/705 - Pixels for depth measurement, e.g. RGBZ

13.

WIRING AND ELECTRONIC DEVICE

      
Application Number JP2023029673
Publication Number 2024/079979
Status In Force
Filing Date 2023-08-17
Publication Date 2024-04-18
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Ochiai, Yasuhiro

Abstract

A wiring according to the present disclosure comprises a plurality of divided wirings through which AC current flows. The number of divided wirings is 4 or greater. If Sp denotes the inter-wiring space between two adjacent divided wirings, and Wd denotes the individual wiring width of each of the divided wirings, Sp/Wd is 0.2-0.55 when reverse-phase current is supplied as the AC current through the divided wirings, and Sp/Wd is 0.35-0.95 when in-phase current is supplied as the AC current through the divided wirings.

IPC Classes  ?

  • H01P 3/18 - Waveguides; Transmission lines of the waveguide type built-up from several layers to increase operating surface, i.e. alternately conductive and dielectric layers
  • H01L 21/3205 - Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layers; After-treatment of these layers
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 27/04 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body

14.

DISPLAY DEVICE WITH DETECTION FUNCTION

      
Application Number JP2023029854
Publication Number 2024/079989
Status In Force
Filing Date 2023-08-18
Publication Date 2024-04-18
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Tsukuda, Yasunori

Abstract

A display device with a detection function according to the present disclosure comprises: a display unit having a transmissive region through which light is transmitted; and a sensor unit having a light-emitting unit and a light-receiving unit disposed on the reverse surface side of the display unit, the sensor unit measuring the flight time for light emitted by the light-emitting unit to be transmitted through the transmissive region, reflected by the object within a specific distance range from the display unit, transmitted through the transmissive region, and received by the light-receiving unit, and thereby measuring the distance to the object within a specific distance range.

IPC Classes  ?

  • G01S 7/481 - Constructional features, e.g. arrangements of optical elements
  • G06F 3/041 - Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
  • G06F 3/042 - Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by opto-electronic means

15.

DISPLAY DEVICE, ELECTRONIC APPARATUS, AND METHOD FOR MANUFACTURING DISPLAY DEVICE

      
Application Number JP2023032313
Publication Number 2024/080039
Status In Force
Filing Date 2023-09-05
Publication Date 2024-04-18
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Fujimaki, Hiroshi

Abstract

Provided are a display device, an electronic apparatus, and a method for manufacturing a display device, which can prevent moisture or the like from penetrating into an effective pixel region. The display device includes a driving substrate that has an effective pixel region and a peripheral region between the effective pixel region and an outer edge. The effective pixel region includes a plurality of pixels. Each pixel includes: a first electrode; a second electrode that is disposed facing the first electrode; and a first organic layer that is provided between the first electrode and the second electrode and that includes a light-emitting layer. The peripheral region includes a second organic layer, which is separated from the first organic layer included in each of the pixels.

IPC Classes  ?

  • H10K 50/84 - Passivation; Containers; Encapsulations
  • H10K 59/122 - Pixel-defining structures or layers, e.g. banks
  • H10K 59/35 - Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
  • H10K 59/38 - Devices specially adapted for multicolour light emission comprising colour filters or colour changing media [CCM]
  • H10K 71/00 - Manufacture or treatment specially adapted for the organic devices covered by this subclass

16.

PHASE MODULATION DEVICE

      
Application Number JP2023033836
Publication Number 2024/080083
Status In Force
Filing Date 2023-09-19
Publication Date 2024-04-18
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Okazaki, Tsuyoshi

Abstract

A phase modulation device according to one embodiment of the present disclosure comprises: a phase modulation unit that has a plurality of pixels and that is capable of modulating the phase of light from a light source; and a generation unit that is capable of generating, on the basis of a phase pattern, first data pertaining to the phase modulation amount for each of the pixels in a first phase modulation range among the ranges of the phase modulation amount and second data pertaining to the phase modulation amount for each of the pixels in a second phase modulation range. The phase modulation unit is capable of modulating the phase of the light from the light source on the basis of the first data and modulating the phase of the light from the light source on the basis of the second data.

IPC Classes  ?

  • G09G 3/36 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix by control of light from an independent source using liquid crystals
  • G02F 1/13 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
  • G02F 1/133 - Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
  • G09G 3/20 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
  • G09G 3/34 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix by control of light from an independent source

17.

SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND OPTICAL DETECTION DEVICE

      
Application Number JP2023036116
Publication Number 2024/080192
Status In Force
Filing Date 2023-10-03
Publication Date 2024-04-18
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Yamamoto Ryusei
  • Hida Shota
  • Tazaki Masayuki

Abstract

Provided are: a semiconductor device configured so that the degradation of the characteristics thereof is suppressed; a method for manufacturing a semiconductor device; and an optical detection device. The semiconductor device comprises: a first semiconductor layer having a first face and a second face located on the opposite side of the first face; a first interlayer insulation film provided on the first face side of the first semiconductor layer; a first opening provided in the first interlayer insulation film that opens on the surface of the first interlayer insulation film; an electrode provided in the first opening; and an insulation film that covers at least the lateral surfaces of the first opening and that is provided at a distance from the lateral surfaces of the electrode.

IPC Classes  ?

  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 21/3205 - Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layers; After-treatment of these layers
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
  • H01L 27/146 - Imager structures
  • H04N 25/70 - SSIS architectures; Circuits associated therewith

18.

PHOTODETECTION ELEMENT AND ELECTRONIC APPARATUS

      
Application Number JP2023036443
Publication Number 2024/080226
Status In Force
Filing Date 2023-10-05
Publication Date 2024-04-18
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Mizoguchi, Kyoji

Abstract

The present invention reduces the impact of interference on a gradation signal or an event signal. This photodetection element has a pixel array unit, a row control unit and an overlap prediction row detection unit. The pixel array unit has a plurality of pixels which are arranged in a two-dimensional matrix and equipped with: an event signal generation unit for detecting a unidirectional change in the brightness of incident light as an event, and generating an event signal, which is a signal based on the detected event; and a gradation signal generation unit for generating a gradation signal, which is a signal which corresponds to the brightness of the incident light. The row control unit performs: a brightness signal generation control for sequentially performing, at a timing which is offset by row, a control for generating a gradation signal by jointly outputting a control signal to the gradation signal generation units of the pixels arranged in a row of the pixel array unit, and a control for reading out the gradation signals; and a control for detecting an event by outputting a control signal to an event signal generation unit and a control for reading out the event signal. The overlap prediction row detection unit detects an overlap prediction row, which is a row where an overlap of the intervals for gradation signal generation and event detection is predicted to occur.

IPC Classes  ?

19.

LIGHT DETECTION DEVICE AND ELECTRONIC APPARATUS

      
Application Number JP2023030034
Publication Number 2024/079990
Status In Force
Filing Date 2023-08-21
Publication Date 2024-04-18
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Yamazaki Tomohiro

Abstract

Provided is a light detection device that makes it possible to suppress the occurrence of defective pixels. Specifically, the light detection device comprises: a semiconductor substrate on which a plurality of photoelectric conversion units are formed; and a plurality of optical filters arranged on the light incidence surface-side of the semiconductor substrate. In addition, each of the optical filters has a metal structure comprising the same type of metal material. Furthermore, slits that spatially divide the metal structures are provided between the metal structures.

IPC Classes  ?

20.

SERVER DEVICE, TERMINAL DEVICE, INFORMATION PROCESSING METHOD, AND INFORMATION PROCESSING SYSTEM

      
Application Number JP2023036472
Publication Number 2024/080231
Status In Force
Filing Date 2023-10-06
Publication Date 2024-04-18
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Shimomura, Munehiro
  • Ishikawa, Hirotaka

Abstract

An information processing system configured to transmit a first command to a first electronic device requesting processing capability information of the first electronic device; receive first parameters from the first electronic device in response to the first command; divide a deep neural network (DNN) into at least a first DNN and a second DNN based on the first parameters received from the first electronic device; and transmit the first divided DNN to the first electronic device.

IPC Classes  ?

  • G06N 3/098 - Distributed learning, e.g. federated learning
  • G06N 3/0985 - Hyperparameter optimisation; Meta-learning; Learning-to-learn
  • G06N 3/082 - Learning methods modifying the architecture, e.g. adding, deleting or silencing nodes or connections
  • G06N 3/045 - Combinations of networks

21.

COUNTING MODE DECISION CIRCUITRY AND COUNTING MODE DECISION METHOD

      
Application Number EP2023076215
Publication Number 2024/074322
Status In Force
Filing Date 2023-09-22
Publication Date 2024-04-11
Owner
  • SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
  • SONY DEPTHSENSING SOLUTIONS SA/NV (Belgium)
Inventor Ding, Qing

Abstract

The present disclosure generally pertains to counting mode decision circuitry configured to: determine, for at least one imaging element, a photon number in a first photon counting mode of at least two photon counting modes which, in a standard operation mode, are applied after each other; and skip a second photon counting mode of the at least two photon counting modes, if the photon number in the first photon counting mode exceeds a predetermined threshold, thereby deviating from the standard operation mode.

IPC Classes  ?

  • H04N 25/589 - Control of the dynamic range involving two or more exposures acquired sequentially, e.g. using the combination of odd and even image fields with different integration times, e.g. short and long exposures
  • H04N 25/773 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising A/D, V/T, V/F, I/T or I/F converters comprising photon counting circuits, e.g. single photon detection [SPD] or single photon avalanche diodes [SPAD]

22.

LIGHT DETECTION DEVICE AND ELECTRONIC EQUIPMENT

      
Application Number JP2022037482
Publication Number 2024/075253
Status In Force
Filing Date 2022-10-06
Publication Date 2024-04-11
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Yamashita, Kazuyoshi

Abstract

A light detection device according to an embodiment of the present disclosure comprises: a first photoelectric conversion portion (12) that performs photoelectric conversion of light; a first light guide portion (30) that includes a first structure (31) of a size less than or equal to the wavelength of input light, and that the light that has passed through the first photoelectric conversion unit (12) enters; and a second photoelectric conversion portion (22) that performs photoelectric conversion of infrared light that enters the second photoelectric conversion portion (22) via the first light guide portion (30).

IPC Classes  ?

  • H01L 31/10 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by at least one potential-jump barrier or surface barrier, e.g. phototransistors

23.

CAMERA MODULE AND IMAGING DEVICE

      
Application Number JP2023029326
Publication Number 2024/075398
Status In Force
Filing Date 2023-08-10
Publication Date 2024-04-11
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Imayoshi, Kohei
  • Kunimitsu, Takayuki
  • Yukishige, Akihiro
  • Kasahara, Keijyu
  • Tsuruta, Takahiro

Abstract

The present invention reduces the device size of an imaging device that performs rotation correction. This camera module comprises a lens group, a translational actuator, a rotational actuator, and a mounting board. In this camera module, the translational actuator moves the lens group in parallel. The rotational actuator rotates the lens group. A part of a rigid flexible board deforms so as to follow the rotation of the lens group. Furthermore, the translational actuator is provided on one of both surfaces of the mounting board and the rigid flexible board is provided on the other one thereof.

IPC Classes  ?

  • G03B 5/00 - Adjustment of optical system relative to image or object surface other than for focusing of general interest for cameras, projectors or printers
  • G02B 7/02 - Mountings, adjusting means, or light-tight connections, for optical elements for lenses
  • G02B 7/04 - Mountings, adjusting means, or light-tight connections, for optical elements for lenses with mechanism for focusing or varying magnification
  • G03B 30/00 - Camera modules comprising integrated lens units and imaging units, specially adapted for being embedded in other devices, e.g. mobile phones or vehicles
  • H04N 23/50 - Constructional details
  • H04N 23/57 - Mechanical or electrical details of cameras or camera modules specially adapted for being embedded in other devices
  • H05K 1/02 - Printed circuits - Details

24.

SOLID-STATE IMAGING DEVICE

      
Application Number JP2023029670
Publication Number 2024/075405
Status In Force
Filing Date 2023-08-17
Publication Date 2024-04-11
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Tanaka, Daichi
  • Tomita, Chihiro

Abstract

This solid-state imaging device comprises: a first pixel that is arranged on a first surface side serving as a light incident side of a substrate, and that has a first photoelectric conversion element for converting light to a charge; a first transistor that is arranged, at a position corresponding to the first pixel, on a second surface side opposite the first surface of the substrate, that has a first gate electrode, and that has a pair of main electrodes, one of which is electrically connected to the first photoelectric conversion element; a floating diffusion that is arranged on the second surface side of the substrate and that is electrically connected to the other main electrode of the first transistor; and a low dielectric constant region that is arranged between the floating diffusion and the first gate electrode opposite the same, and that has a lower dielectric constant than that of a non-opposing region.

IPC Classes  ?

25.

PHOTODETECTION DEVICE

      
Application Number JP2023029830
Publication Number 2024/075409
Status In Force
Filing Date 2023-08-18
Publication Date 2024-04-11
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Ishii Hiroyasu
  • Moriyama Yusuke
  • Baba Tomohiro
  • Kaji Nobuaki
  • Wakayama Kazuyuki
  • Izuhara Kunihiko

Abstract

A device capable of improving characteristics of a light sensor by applying an appropriate bias voltage to the light sensor. A device according to one embodiment includes a first light source configured to emit a first light, a second light source configured to emit a second light having a first characteristic different from a second characteristic of the first light, a first light sensor configured to detect first reflected light that is the first light emitted from the first light source and reflected by an object, and a second light sensor configured to detect second reflected light that is the second light emitted from the second light source and reflected by a first member that is distinct from the object.

IPC Classes  ?

  • G01S 7/4863 - Detector arrays, e.g. charge-transfer gates
  • G01S 7/497 - Means for monitoring or calibrating
  • G01S 17/894 - 3D imaging with simultaneous measurement of time-of-flight at a 2D array of receiver pixels, e.g. time-of-flight cameras or flash lidar
  • G01S 7/481 - Constructional features, e.g. arrangements of optical elements

26.

SOLID-STATE IMAGING DEVICE, AND COMPARISON DEVICE

      
Application Number JP2023033578
Publication Number 2024/075492
Status In Force
Filing Date 2023-09-14
Publication Date 2024-04-11
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Azuhata Satoshi

Abstract

[Problem] To perform fast and high-performance signal comparison. [Solution] This solid-state imaging device comprises a comparison circuit, a first switch, a second switch, a third switch, a first capacitor, and a second capacitor. The comparison circuit is provided with a non-inverting input terminal and an inverting input terminal. The first switch is connected to the inverting input terminal. The second switch is connected to the inverting input terminal and is controlled at a different timing than the first switch. The third switch is connected between an output terminal of the comparison circuit and the inverting input terminal. One end of the first capacitor is connected to the inverting input terminal via the first switch, and a reference signal is applied to the other end of the first capacitor. One end of the second capacitor is connected to the inverting input terminal via the second switch, and the reference signal is applied to the other end of the second capacitor.

IPC Classes  ?

  • H04N 25/77 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
  • H04N 25/772 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising A/D, V/T, V/F, I/T or I/F converters

27.

IMAGING DEVICE

      
Application Number JP2023029334
Publication Number 2024/075399
Status In Force
Filing Date 2023-08-10
Publication Date 2024-04-11
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Hattori, Yuki
  • Yamamoto, Masahiro

Abstract

The present invention reduces a noise component caused by a dark current while eliminating the need for mechanical light shielding. This imaging device comprises: a pixel provided with a lateral overflow integration capacitor that accumulates an electrical charge which has overflowed from a photoelectric conversion unit; and a signal processing unit that carries out correction processing of a pixel signal read out from the pixel, on the basis of a virtual light shielding signal read out from the lateral overflow integration capacitor in a state in which an electrical charge which has been photoelectrically converted in the photoelectric conversion unit is not accumulated in the lateral overflow integration capacitor. The imaging device may further comprise a flow control unit that discharges an electrical charge so that an electrical charge which has been photoelectrically converted in the photoelectric conversion unit is not accumulated in the lateral overflow integration capacitor.

IPC Classes  ?

  • H04N 25/771 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion
  • H04N 25/63 - Noise processing, e.g. detecting, correcting, reducing or removing noise applied to dark current

28.

SOLID-STATE IMAGING DEVICE

      
Application Number JP2023034200
Publication Number 2024/075526
Status In Force
Filing Date 2023-09-21
Publication Date 2024-04-11
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Shirai Yuki
  • Nakamura Ryosuke
  • Yamachi Ryosuke
  • Saka Naoki

Abstract

The present disclosure relates to a solid-state imaging device which can have improved pixel characteristics. Provided is a solid-state imaging device including a pixel array part comprising two-dimensionally arranged pixels each having a photoelectric conversion element and a pixel transistor, the pixel transistor including a transistor having a structure in which an impurity has been injected into a channel that is non-linear in a plan view, using a self-alignment mask according to the gate electrodes. The present disclosure is applicable to, for example, CMOS-type solid-state imaging devices.

IPC Classes  ?

  • H01L 27/146 - Imager structures
  • H01L 21/8234 - MIS technology
  • H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
  • H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate

29.

DISPLAY DEVICE AND ELECTRONIC APPARATUS

      
Application Number JP2023029559
Publication Number 2024/070292
Status In Force
Filing Date 2023-08-16
Publication Date 2024-04-04
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Sato, Akihito

Abstract

A display device according to one embodiment of the present disclosure comprises: a display region in which a plurality of effective pixels are arranged in a matrix pattern; a non-display region including a plurality of dummy pixels provided in the vicinity of the display region; and a heat generating structure that absorbs incident light to generate heat, and is provided in the non-display region so as to surround the display region.

IPC Classes  ?

  • G02F 1/13 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells

30.

LENS OPTICAL SYSTEM AND IMAGING DEVICE

      
Application Number JP2023032953
Publication Number 2024/070611
Status In Force
Filing Date 2023-09-11
Publication Date 2024-04-04
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Ogino Shinpei
  • Murakami Daichi
  • Hanzawa Fumihiko
  • Takeuchi Haruki
  • Nakamura Masashi
  • Kimura Katsuji

Abstract

The present technology pertains to a lens optical system and an imaging device which make it possible to improve optical performance in a wide-angle lens optical system having a metasurface. The lens optical system comprises, in order from the light incident side, a metalens having positive refractive power and an optical lens having positive refractive power. The metalens has disposed thereon a metasurface formed from a plurality of nanostructures. An aperture diaphragm is disposed on the incident side of the metasurface. At least one optical surface of a second lens is aspherical. The present technology can be applicable to, for example, a wide-angle lens optical system or the like that condenses light from a subject to a solid-state imaging element.

IPC Classes  ?

  • G02B 13/00 - Optical objectives specially designed for the purposes specified below
  • G02B 5/18 - Diffracting gratings
  • G02B 13/18 - Optical objectives specially designed for the purposes specified below with lenses having one or more non-spherical faces, e.g. for reducing geometrical aberration

31.

SOLID-STATE IMAGING DEVICE, ELECTRONIC DEVICE, AND PROGRAM

      
Application Number JP2023033250
Publication Number 2024/070673
Status In Force
Filing Date 2023-09-12
Publication Date 2024-04-04
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Kazama Ryohei
  • Wakayama Kazuyuki
  • Kusakari Takashi

Abstract

[Problem] To improve the authentication accuracy. [Solution] A solid-state imaging device comprises a light source, a first light reception region, and a second light reception region. The light source is provided on the opposite side of a display from the display surface of the display, the light source emitting light in the IR region via the display. The first light reception region is provided on the opposite side of the display from the display surface, and is provided with pixels for receiving light in the visible light region and pixels for receiving at least light in the IR region emitted from the light source. The second light reception region is provided on the opposite side of the display from the display surface, and is provided with pixels for receiving at least light in the IR region emitted from the light source.

IPC Classes  ?

  • G01S 17/86 - Combinations of lidar systems with systems other than lidar, radar or sonar, e.g. with direction finders
  • G01S 17/89 - Lidar systems, specially adapted for specific applications for mapping or imaging

32.

RANGING DEVICE, AND METHOD FOR MANUFACTURING SAME

      
Application Number JP2023033872
Publication Number 2024/070803
Status In Force
Filing Date 2023-09-19
Publication Date 2024-04-04
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Suzuki Ryosuke
  • Fukunaga Hiroshi
  • Otake Yusuke
  • Wakano Toshifumi
  • Asayama Go

Abstract

[Problem] To perform ranging processing with low power consumption while enabling a reduction in size and cost. [Solution] This ranging device employs a light receiving unit to receive a reflected light signal resulting from a light pulse signal emitted from a light emitting unit being reflected by an object, and measures a distance to the object on the basis of the reflected light signal received by the light receiving unit, the ranging device comprising: a first board comprising a group 4 material on which the light receiving unit and the light emitting unit are disposed monolithically; and a second board which is stacked on the first board, and which has disposed thereon a readout circuit for reading out a light reception signal received by the light receiving unit.

IPC Classes  ?

  • G01S 7/481 - Constructional features, e.g. arrangements of optical elements
  • G01S 17/894 - 3D imaging with simultaneous measurement of time-of-flight at a 2D array of receiver pixels, e.g. time-of-flight cameras or flash lidar

33.

IMAGE PROCESSING DEVICE, IMAGE PROCESSING METHOD, AND PROGRAM

      
Application Number JP2023034433
Publication Number 2024/070925
Status In Force
Filing Date 2023-09-22
Publication Date 2024-04-04
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Sato, Taiki
  • Tabata, Hidenori
  • Yoneyama, Hisashi

Abstract

The objective of the present invention is to reduce an amount of calculation required for detection processing in a device that detects a three-dimensional shape of an object. An image processing device of the present disclosure includes an object detection region information generating portion. The object detection region information generating portion of the image processing device of the present disclosure generates object detection region information for detecting the three-dimensional shape of the object from a distance image including the object, on the basis of the distance image. Further, the object detection region information generated by an object region information generating portion of the image processing device of the present disclosure is information relating to a detection region of the object.

IPC Classes  ?

  • G01B 11/24 - Measuring arrangements characterised by the use of optical techniques for measuring contours or curvatures

34.

LIGHT DETECTING DEVICE, AND RANGING SYSTEM

      
Application Number JP2023035078
Publication Number 2024/071173
Status In Force
Filing Date 2023-09-27
Publication Date 2024-04-04
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Sekiya Akito
  • Hamamatsu Masamune
  • Endo Noriaki
  • Saito Yoshiyuki

Abstract

[Problem] To enable an improvement in ranging accuracy using a small number of light emissions and light receptions, irrespective of the distance to an object. [Solution] This light detecting device comprises: a light receiving unit for receiving, within a first time range, a first reflected light pulse signal resulting from a first light pulse signal emitted in a first time interval being reflected by an object, and receiving, within a second time range different from the first time range, a second reflected light pulse signal resulting from a second light pulse signal emitted in a second time interval different from the first time interval being reflected by the object; and a histogram generator for generating a first histogram in which reception frequencies of the first reflected light pulse signal received within the first time range are classified for each predetermined fixed unit period, and generating a second histogram in which the reception frequencies of the second reflected light pulse signals received within the second time range are classified for each unit period.

IPC Classes  ?

  • G01S 7/4863 - Detector arrays, e.g. charge-transfer gates
  • G01C 3/06 - Use of electric means to obtain final indication
  • G01S 17/894 - 3D imaging with simultaneous measurement of time-of-flight at a 2D array of receiver pixels, e.g. time-of-flight cameras or flash lidar

35.

APPARATUSES AND METHODS FOR POLARIZATION BASED SURFACE NORMAL IMAGING

      
Application Number EP2023075650
Publication Number 2024/068335
Status In Force
Filing Date 2023-09-18
Publication Date 2024-04-04
Owner
  • SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
  • UNIVERSITY OF ZURICH (Switzerland)
Inventor
  • Muglikar, Manasi
  • Moeys, Diederik Paul
  • Scaramuzza, Davide

Abstract

The present disclosure relates to an apparatus for polarization-based surface normal imaging, the apparatus comprising a linear polarizer configured to rotate and to subsequently pass light from a scene, an event-based vision sensor, EVS, configured to detect a set of events of the scene based on the rotation angle of the linear polarizer, and a shape estimation processor configured to compute surface normal information of the scene based on the set of events and the corresponding rotation angle of the polarizer.

IPC Classes  ?

  • G06T 7/55 - Depth or shape recovery from multiple images

36.

COMPUTATION DEVICE, IMAGING DEVICE AND COMPUTATION METHOD

      
Application Number JP2022036010
Publication Number 2024/069769
Status In Force
Filing Date 2022-09-27
Publication Date 2024-04-04
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Saito Daisuke
  • Hanzawa Katsuhiko
  • Sakakibara Masaki
  • Maeda Noriaki
  • Naganuma Hideki

Abstract

The present disclosure provides a computation device equipped with a first signal line, a first capacitor which is connected to the first signal line, one or more sub-arrays which are connected to the first signal line, and a readout circuit for generating a digital signal which corresponds to the charge of the first signal line, wherein the sub-arrays have a second signal line which is connected to the first signal line via a first switching element, a second capacitor which is connected to the second signal line, and one or more memory cells which are connected to the second signal line and capable of imparting a charge, which corresponds to a signal value to be stored, to said second signal line.

IPC Classes  ?

  • G11C 11/54 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using elements simulating biological cells, e.g. neuron
  • G06G 7/60 - Analogue computers for specific processes, systems, or devices, e.g. simulators for living beings, e.g. their nervous systems
  • G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
  • G11C 11/412 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only

37.

PHOTOELECTRIC CONVERSION ELEMENT, AND PHOTODETECTOR

      
Application Number JP2023029560
Publication Number 2024/070293
Status In Force
Filing Date 2023-08-16
Publication Date 2024-04-04
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Takaguchi, Ryotaro
  • Joei, Masahiro
  • Hirata, Shintarou
  • Yagi, Iwao
  • Suzuki, Ryosuke

Abstract

A first photoelectric conversion element according to one embodiment of the present disclosure comprises: an electrode layer including a first electrode and a second electrode that are arranged in parallel; a third electrode that is arranged to face the first electrode and the second electrode; a photoelectric conversion layer that is provided between the electrode layer and the third electrode; an oxide semiconductor layer that is provided between the electrode layer and the photoelectric conversion layer; and a first insulating layer that is provided between the electrode layer and the oxide semiconductor layer, wherein the first insulating layer has an opening which allows the entire upper surface of the first electrode to be in contact with the oxide semiconductor layer without having the first insulating layer therebetween.

IPC Classes  ?

  • H01L 27/146 - Imager structures
  • H01L 31/10 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by at least one potential-jump barrier or surface barrier, e.g. phototransistors
  • H10K 30/60 - Organic devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation in which radiation controls flow of current through the devices, e.g. photoresistors

38.

LIGHT DETECTION ELEMENT AND ELECTRONIC DEVICE

      
Application Number JP2023032304
Publication Number 2024/070523
Status In Force
Filing Date 2023-09-05
Publication Date 2024-04-04
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Uehara Takuya

Abstract

[Problem] To suppress detection of noise events and to detect events quickly and precisely. [Solution] This light detection element comprises: a first pixel region including a plurality of first pixels which each detect an event based on the amount of change in the amount of incident light; and a second pixel region disposed in the vicinity of the first pixel region and including second pixels which detect the event in the surroundings of first pixels among the plurality of first pixels which have detected the event.

IPC Classes  ?

  • H04N 25/707 - Pixels for event detection
  • H04N 25/772 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising A/D, V/T, V/F, I/T or I/F converters
  • H04N 25/77 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components

39.

INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND RECORDING MEDIUM

      
Application Number JP2023032951
Publication Number 2024/070609
Status In Force
Filing Date 2023-09-11
Publication Date 2024-04-04
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Ando Hideki
  • Miyoshi Hironori

Abstract

The present disclosure pertains to an information processing apparatus, an information processing method, and a recording medium enabling an apparatus interposed between a device and an application apparatus to properly provide data from the device to the application apparatus. A data service (DS) is provided with a control unit for: acquiring, with regard to a plurality of app apparatuses, link information with respect to a device that outputs data and an app apparatus that performs prescribed data processing using data; determining a destination to which to send data acquired from one or more devices on the basis of the acquired link information; and performing control to transmit the data to the one or more app apparatuses determined to be the destination. The features of the present disclosure can be applied, for example, to apparatuses for performing data communication conforming to the NICE standard.

IPC Classes  ?

  • H04L 67/2871 - Implementation details of single intermediate entities
  • G06F 15/00 - Digital computers in general; Data processing equipment in general
  • H04L 67/50 - Network services
  • H04M 11/00 - Telephonic communication systems specially adapted for combination with other electrical systems

40.

SOLID-STATE IMAGING DEVICE, COMPARATOR AND ELECTRONIC EQUIPMENT

      
Application Number JP2023033581
Publication Number 2024/070740
Status In Force
Filing Date 2023-09-14
Publication Date 2024-04-04
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Hayashi Yasuaki
  • Umeda Kengo
  • Moue Takashi
  • Naganokawa Haruhisa

Abstract

[Problem] To reduce noise in an image sensor. [Solution] This solid-state imaging device comprises a light receiving element, a first amplification circuit, a second amplification circuit and a control circuit. The first amplification circuit amplifies and outputs the difference between a reference signal and an input signal outputted from the light receiving element. The second amplification circuit amplifies and outputs the first amplified signal outputted by the first amplification circuit. The control circuit controls, on the basis of the reference signal, an active load of the first amplification circuit or the mutual conductance of at least one of amplification transistors of the second amplification circuit.

IPC Classes  ?

  • H04N 25/78 - Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
  • H01L 27/146 - Imager structures
  • H03M 1/08 - Continuously compensating for, or preventing, undesired influence of physical parameters of noise
  • H03M 1/56 - Input signal compared with linear ramp

41.

IMAGE PROCESSING DEVICE, IMAGE PROCESSING METHOD, PROGRAM, AND IMAGING DEVICE

      
Application Number JP2023034587
Publication Number 2024/070979
Status In Force
Filing Date 2023-09-22
Publication Date 2024-04-04
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Tabata, Hidenori

Abstract

In the present invention, the data volume of a distance image is reduced. This image processing device has a second distance image generation unit. The second distance image generation unit generates a second distance image. The second distance image has a plurality of second pixels provided with information on the distance of first pixels that are pixels of a first distance image that is a distance image of a region including an object. The plurality of second pixels are respectively disposed corresponding to emission regions of structured light having a prescribed emission region pattern projected on a region including the object in order to generate the first distance image. The information on the distance of the first pixels at the positions corresponding to the emission regions is provided to the second pixels at the positions corresponding to the emission regions.

IPC Classes  ?

  • G01B 11/25 - Measuring arrangements characterised by the use of optical techniques for measuring contours or curvatures by projecting a pattern, e.g. moiré fringes, on the object
  • G06T 7/50 - Depth or shape recovery

42.

IMAGING ELEMENT AND ELECTRONIC DEVICE

      
Application Number JP2023035436
Publication Number 2024/071309
Status In Force
Filing Date 2023-09-28
Publication Date 2024-04-04
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Masuda Yoshiaki
  • Hatano Keisuke
  • Nagata Kengo
  • Noudo Shinichiro
  • Furuhashi Takahisa
  • Ando Atsuhiro

Abstract

The present technology pertains to an imaging element and an electronic device which can reduce time and labor in performing inspection during manufacturing. The imaging element comprises: a pixel array in which pixels including photoelectric conversion elements are two-dimensionally arrayed; a pad having an opening in a first surface side to which the pixel array is provided; an electrode provided, in an exposed state, to the bottom of the pad; a through-electrode having an opening in a second surface opposite to the first surface; and a rewiring layer layered on the second surface. The inside of the through-electrode is hollow. The present technology can be applied to, for example, an imaging element in a wafer-level chip size package (WLCLP).

IPC Classes  ?

  • H01L 27/146 - Imager structures
  • H01L 23/12 - Mountings, e.g. non-detachable insulating substrates
  • H04N 25/70 - SSIS architectures; Circuits associated therewith

43.

MEASUREMENT DEVICE AND MEASUREMENT METHOD

      
Application Number JP2023033140
Publication Number 2024/070653
Status In Force
Filing Date 2023-09-12
Publication Date 2024-04-04
Owner
  • SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
  • SONY GROUP CORPORATION (Japan)
Inventor
  • Kondo Fumitaka
  • Yamamoto Ken
  • Nakagawa Kei
  • Hiyama Ayaka

Abstract

The present technology pertains to a measurement device and a measurement method which enable accurate measurement of the concentration of glucose (dextrose) contained in an object to be measured. The concentration of glucose in the object to be measured is calculated on the basis of the complex dielectric constant of the object to be measured and moisture content of the object to be measured. The moisture content can be calculated on the basis of an incident signal, which represents an electromagnetic wave incident on the object to be measured, and a reflection signal, which represents reflection by the object to be measured.

IPC Classes  ?

  • G01N 22/00 - Investigating or analysing materials by the use of microwaves or radio waves, i.e. electromagnetic waves with a wavelength of one millimetre or more
  • G01N 22/04 - Investigating moisture content

44.

IMAGE PROCESSING DEVICE, IMAGE PROCESSING METHOD, AND PROGRAM

      
Application Number JP2023033646
Publication Number 2024/070751
Status In Force
Filing Date 2023-09-15
Publication Date 2024-04-04
Owner
  • SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
  • SONY GROUP CORPORATION (Japan)
Inventor
  • Yoneyama, Hisashi
  • Tanaka, Satoshi

Abstract

The objective of the present invention is to improve the convenience of an image processing device that detects the entry of a moving object into a target region. The image processing device includes an entry detecting portion. The entry detecting portion of the image processing device detects the entry of the object into the detection target region on the basis of specific information relating to the detection target region. The detection target region of the entry detecting portion is a region in which the object is to be detected. A specific region of the entry detecting portion is some information relating to the object in the detection target region.

IPC Classes  ?

45.

SEMICONDUCTOR PACKAGE, SEMICONDUCTOR MODULE, ELECTRONIC DEVICE, AND SEMICONDUCTOR PACKAGE MANUFACTURING METHOD

      
Application Number JP2023024723
Publication Number 2024/062719
Status In Force
Filing Date 2023-07-04
Publication Date 2024-03-28
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Yasukawa, Hirohisa
  • Shigeta, Hiroyuki

Abstract

Disclosed herein is a semiconductor package including a semiconductor chip configured to have one of two surfaces thereof mounted with a circuit, the circuit formation surface constituting a circuit formation surface, a first shield layer configured to cover a side of the semiconductor chip and the other surface thereof, and a second shield layer configured to cover the circuit formation circuit.

IPC Classes  ?

  • H01L 23/552 - Protection against radiation, e.g. light
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 23/13 - Mountings, e.g. non-detachable insulating substrates characterised by the shape
  • H01L 23/498 - Leads on insulating substrates
  • H01L 23/50 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements for integrated circuit devices
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different main groups of groups , or in a single subclass of , , e.g. forming hybrid circuits

46.

ELECTRONIC DEVICE AND MANUFACTURING METHOD FOR ELECTRONIC DEVICE

      
Application Number JP2023025782
Publication Number 2024/062745
Status In Force
Filing Date 2023-07-12
Publication Date 2024-03-28
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Shigetoshi, Takushi

Abstract

An electronic device includes a substrate, a first through-hole penetrating the substrate, a capacitive element above the substrate, and a first conductor film. A first portion of the first conductor film traverses the substrate along a side wall of the first through-hole and a second portion of the first conductor film is in contact with the capacitive element.

IPC Classes  ?

  • H01G 4/33 - Thin- or thick-film capacitors
  • H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements

47.

INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, AND PROGRAM

      
Application Number JP2023031534
Publication Number 2024/062874
Status In Force
Filing Date 2023-08-30
Publication Date 2024-03-28
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Shibui, Shuichi
  • Nagumo, Masahiko
  • Nakada, Hitoshi
  • Kitami, Hirotaka
  • Saruta, Takashi

Abstract

An information processing device according to the present invention comprises an artificial intelligence (AI) image processing unit that: receives input of first image data and second image data as input data for an artificial intelligence model which has been trained with machine learning, said first image data being distance image data which is obtained on the basis of a light reception signal of a first sensor serving as a light-receiving sensor that performs a light reception operation for distance measurement, said second image data being image data obtained on the basis of a light reception signal of a second sensor that is a light-receiving sensor differing in type from the first sensor; and uses the artificial intelligence model to perform a process for inferring, as a correction target region, a distance measurement error region which appears in the first image data due to interference light that has been emitted from an outside object and that is in a light-reception wavelength band of the first sensor.

IPC Classes  ?

  • G01S 17/86 - Combinations of lidar systems with systems other than lidar, radar or sonar, e.g. with direction finders
  • G01S 7/495 - Counter-measures or counter-counter-measures
  • G01S 17/894 - 3D imaging with simultaneous measurement of time-of-flight at a 2D array of receiver pixels, e.g. time-of-flight cameras or flash lidar
  • G06N 20/00 - Machine learning

48.

MAGNETORESISTIVE ELEMENT, MEMORY DEVICE, AND ELECTRONIC APPLIANCE

      
Application Number JP2023033216
Publication Number 2024/062978
Status In Force
Filing Date 2023-09-12
Publication Date 2024-03-28
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Endo, Masaki

Abstract

A magnetoresistive element according to one embodiment of the present disclosure comprises a multilayer structure, a memory layer disposed on the multilayer structure and changeable in magnetization direction, a nonmagnetic layer disposed on the memory layer, and a reference layer disposed on the nonmagnetic layer and having a fixed magnetization direction. The multilayer structure comprises magnetic layers changeable in magnetization direction and nonmagnetic metal layers disposed on the magnetic layers.

IPC Classes  ?

  • H01L 29/82 - Types of semiconductor device controllable by variation of the magnetic field applied to the device
  • G11B 5/39 - Structure or manufacture of flux-sensitive heads using magneto-resistive devices
  • H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
  • H10N 50/10 - Magnetoresistive devices

49.

PHOTON COUNTING CIRCUITRY AND PHOTON COUNTING METHOD

      
Application Number EP2023075832
Publication Number 2024/061925
Status In Force
Filing Date 2023-09-19
Publication Date 2024-03-28
Owner
  • SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
  • SONY DEPTHSENSING SOLUTIONS SA/NV (Belgium)
Inventor Ding, Qing

Abstract

The present disclosure generally pertains to photon counting circuitry (11), configured to: determine, based on a degree of overlap in time of at least two pixel signals (CLK1, CLK2) of at least two pixels (SPAD1, SPAD2) of a photon counting time-of-flight sensor (10), whether a signal coincidence of the at least two pixel signals (CLK1, CLK2) is present, for setting a counting operation mode to a coincidence counting operation mode, if the signal coincidence is present, wherein counts of the at least two pixel signals are counted together in the coincidence counting operation mode; and generate a coincidence counting signal (YES) for setting the counting operation mode to the coincidence counting operation mode. Preferably, the coincidence counting signal corresponds to that pixel signal of the at least two pixel signals (CLK1, CLK2) which is later in time. For example, only one count would be recorded when there is no coincidence detection. However, a count number of a common counter may be multiplied by two to reproduce the real event number. Thereby, more counts may be accumulated which may optimize a signal to noise ratio. Moreover, silicon area may be saved by accounting for a correlation between/among adjacent/neighboring pixels in the sensor. It is made use of this correlation to save the total counter bit length of two or more pixels in a pixel group. Hence, this temporal correlation may be determined and coincident counts may be dynamically stored into a common (shared) counter.

IPC Classes  ?

  • G01S 7/4865 - Time delay measurement, e.g. time-of-flight measurement, time of arrival measurement or determining the exact position of a peak
  • G01S 17/894 - 3D imaging with simultaneous measurement of time-of-flight at a 2D array of receiver pixels, e.g. time-of-flight cameras or flash lidar

50.

WIRELESS COMMUNICATION DEVICE, AND METHOD FOR CONTROLLING WIRELESS COMMUNICATION DEVICE

      
Application Number JP2023027701
Publication Number 2024/062768
Status In Force
Filing Date 2023-07-28
Publication Date 2024-03-28
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Tanaka, Katsuyuki
  • Okamoto, Takuya

Abstract

The present invention improves the versatility and convenience of a wireless communication device that performs positioning on the basis of signals received using a plurality of antennas. A first transmission antenna transmits a first transmission signal including one of a request relating to a positioning scheme and a response to the request. A first reception antenna receives a first satellite signal. A second reception antenna receives a first reception signal including either the other of the request and the response, or a beacon signal. A selector selects either of the first satellite signal and the first reception signal and supplies the same as a selected signal. A first quadrature detection unit performs quadrature detection with respect to the selected signal. A processing unit measures a current position on the basis of either the first satellite signal or the beacon signal.

IPC Classes  ?

  • G01S 19/36 - Constructional details or hardware or software details of the signal processing chain relating to the receiver frond end
  • G01S 5/02 - Position-fixing by co-ordinating two or more direction or position-line determinations; Position-fixing by co-ordinating two or more distance determinations using radio waves
  • G01S 19/31 - Acquisition or tracking of other signals for positioning
  • H04B 1/40 - Circuits

51.

SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, SEMICONDUCTOR MODULE, AND ELECTRONIC EQUIPMENT

      
Application Number JP2023028883
Publication Number 2024/062789
Status In Force
Filing Date 2023-08-08
Publication Date 2024-03-28
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Morita, Shinya

Abstract

This semiconductor device comprises: a first compound semiconductor; a first electrode arranged on the first compound semiconductor and connected to the first compound semiconductor by Schottky contact; a second compound semiconductor arranged on the first compound semiconductor set apart from the first electrode, said second compound semiconductor having a higher impurity density than the first compound semiconductor; and a second electrode arranged on the second compound semiconductor, formed using the same conductive material as the first electrode, and connected to the second compound semiconductor by ohmic contact.

IPC Classes  ?

  • H01L 29/872 - Schottky diodes
  • H01L 21/329 - Multistep processes for the manufacture of devices of the bipolar type, e.g. diodes, transistors, thyristors the devices comprising one or two electrodes, e.g. diodes
  • H01L 21/337 - Field-effect transistors with a PN junction gate
  • H01L 21/338 - Field-effect transistors with a Schottky gate
  • H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
  • H01L 21/8234 - MIS technology
  • H01L 27/04 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
  • H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
  • H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
  • H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
  • H01L 29/47 - Schottky barrier electrodes
  • H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
  • H01L 29/808 - Field-effect transistors with field effect produced by a PN or other rectifying junction gate with a PN junction gate
  • H01L 29/812 - Field-effect transistors with field effect produced by a PN or other rectifying junction gate with a Schottky gate
  • H01L 29/861 - Diodes
  • H01L 29/868 - PIN diodes
  • H01L 29/87 - Thyristor diodes, e.g. Shockley diodes, break-over diodes

52.

SEMICONDUCTOR APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR APPARATUS

      
Application Number JP2023029301
Publication Number 2024/062796
Status In Force
Filing Date 2023-08-10
Publication Date 2024-03-28
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Shigetoshi, Takushi
  • Okamoto, Masaki
  • Hiratsuka, Tatsumasa
  • Hirano, Takaaki
  • Kugimiya, Katsuhisa
  • Matsumoto, Shun

Abstract

Provided is a semiconductor apparatus including a semiconductor substrate having a front surface on which a wiring layer is formed, a through hole that penetrates the semiconductor substrate, a through wire formed along a side surface of the through hole, and an annular trench that surrounds a circumference of the through hole when seen in a direction perpendicular to a rear surface of the semiconductor substrate which is on a side opposite to the front surface and that has formed therein a cavity when seen in a direction parallel to a rear surface.

IPC Classes  ?

  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements

53.

OPTICAL DETECTING DEVICE, AND OPTICAL DETECTING SYSTEM

      
Application Number JP2023029679
Publication Number 2024/062809
Status In Force
Filing Date 2023-08-17
Publication Date 2024-03-28
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Yoneyama Hisashi

Abstract

[Problem] To provide an optical detecting device and an optical detecting system capable of measuring a three-dimensional shape more quickly. [Solution] The present disclosure provides an optical detecting device comprising an imaging portion for imaging a measurement range in which a projected image including a predetermined pattern is being projected, and a signal processing portion for generating three-dimensional distance data of the measurement range on the basis of first captured image data having a first dynamic range captured by the imaging portion, and second captured image data having a second dynamic range different from the first dynamic range, wherein the signal processing portion includes a first processing portion for extracting a first feature point on the basis of the first captured image data, and a second processing portion for extracting a second feature point on the basis of the second captured image data, and the signal processing portion generates the three-dimensional distance data using at least one of the first feature point and the second feature point.

IPC Classes  ?

  • G01B 11/25 - Measuring arrangements characterised by the use of optical techniques for measuring contours or curvatures by projecting a pattern, e.g. moiré fringes, on the object

54.

IMAGING DEVICE AND ELECTRONIC EQUIPMENT

      
Application Number JP2023029792
Publication Number 2024/062813
Status In Force
Filing Date 2023-08-18
Publication Date 2024-03-28
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Takenaka Kyoichi
  • Kayashima Seiji

Abstract

The present invention reduces the manufacturing cost by simplifying the structure of switching electronic shutter systems. Provided is an imaging device comprising: a photoelectric conversion unit that converts light to charge; an overfloat transistor that is connected to the photoelectric conversion unit; a transfer transistor that is connected to the photoelectric conversion unit; a reset transistor that is connected to the transfer transistor; a capacitor that is connected between the transfer transistor and the reset transistor; and an amplification transistor that is connected between the transfer transistor and the reset transistor.

IPC Classes  ?

  • H04N 25/40 - Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled
  • H04N 5/33 - Transforming infrared radiation
  • H04N 25/77 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components

55.

SOLID-STATE IMAGING DEVICE

      
Application Number JP2023030862
Publication Number 2024/062842
Status In Force
Filing Date 2023-08-28
Publication Date 2024-03-28
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Takahashi Tomohiro

Abstract

[Problem] To provide a solid-state imaging device capable of rapidly processing events. [Solution] The solid-state imaging device of the present disclosure comprises: a pixel array region that includes a plurality of pixels for detecting an event, each of the plurality of pixels belonging to any of first to Nth (N is an integer of 2 or greater) groups; first to Nth arbiters that are respectively provided for the pixels of the first to Nth groups, the Kth (K is an integer satisfying 1≦K≦N) arbiter receiving a plurality of request signals output from a plurality of pixels of the Kth group, and outputting a request signal corresponding to any of the plurality of pixels of the Kth group; and first to Nth latch portions respectively provided for the pixels of the first to Nth groups, the Kth latch portion reading a pixel value from a pixel corresponding to the request signal output from the Kth arbiter.

IPC Classes  ?

56.

INFORMATION PROCESSING DEVICE, METHOD, AND PROGRAM

      
Application Number JP2023032462
Publication Number 2024/062920
Status In Force
Filing Date 2023-09-06
Publication Date 2024-03-28
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Ebihara Munetake

Abstract

The present technology relates to an information processing device, method, and program that make it possible to prove the contextual relationship of data even when troubleshooting has been carried out for equipment. This information processing device generates output data that includes data being verified in regard to a contextual relationship in time, the information processing device comprising a control unit that generates output data including a hash value calculated on the basis of the whole or part of output data immediately preceding in time, the data being verified, and a plurality of types of mutually differing ID information related to the data being verified. The present technology is applicable to cameras.

IPC Classes  ?

  • G06F 16/14 - File systems; File servers - Details of searching files based on file metadata
  • G06F 21/64 - Protecting data integrity, e.g. using checksums, certificates or signatures

57.

IMAGE PROCESSING DEVICE, IMAGE PROCESSING METHOD, AND PROGRAM

      
Application Number JP2023032626
Publication Number 2024/062929
Status In Force
Filing Date 2023-09-07
Publication Date 2024-03-28
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Agresti Gianluca
  • Rossi Mattia
  • Rad Saeed
  • Fujii Yusuke

Abstract

The present disclosure pertains to an image processing device, an image processing method, and a program which enable easy generation of 3D models provided with spectral information. A spectral 3D model is generated on the basis of a RGB image group, and spectral information of a spectral image group is mapped to generate a spectral 3D model in which the spectral information is mapped to the 3D model. The present disclosure can be applied to technology for generating spectral 3D images in which spectral information is superimposed on a 3D model.

IPC Classes  ?

  • G06T 17/00 - 3D modelling for computer graphics
  • G06T 7/55 - Depth or shape recovery from multiple images

58.

INFORMATION PROCESSING DEVICE AND INFORMATION PROCESSING METHOD

      
Application Number JP2023033196
Publication Number 2024/062976
Status In Force
Filing Date 2023-09-12
Publication Date 2024-03-28
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Yamanaka, Kazuhiro

Abstract

This information processing device comprises: a viewpoint conversion unit that converts the viewpoints of a plurality of images generated by a plurality of imaging units mounted on the front, rear, left, and right sides of a vehicle; and an overhead image generation unit that combines the plurality of images subjected to viewpoint conversion by the viewpoint conversion unit, thereby generating an overhead image. The overhead image generation unit executes a first combining process when generating a first overhead image to be displayed in the vehicle, and executes a second combining process different from the first combining process when generating a second overhead image for implementing a recognition process on the surroundings of the vehicle.

IPC Classes  ?

  • H04N 7/18 - Closed-circuit television [CCTV] systems, i.e. systems in which the video signal is not broadcast
  • G06T 1/00 - General purpose image data processing
  • G06T 7/00 - Image analysis

59.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

      
Application Number JP2023034565
Publication Number 2024/063164
Status In Force
Filing Date 2023-09-22
Publication Date 2024-03-28
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Shigetoshi, Takushi
  • Okamoto, Masaki
  • Hiratsuka, Tatsumasa
  • Hirano, Takaaki
  • Kugimiya, Katsuhisa
  • Matsumoto, Shun
  • Furuhashi, Takahisa

Abstract

Provided is a semiconductor device having an annular trench formed around a through-hole, wherein reliability is improved. In the present invention, a semiconductor device comprises a semiconductor substrate, through-wiring, a rear-surface insulating film, and an annular trench. A wiring layer is formed on the surface of the semiconductor substrate. The through-hole penetrates the semiconductor substrate. The through-wiring is formed along a side surface of the through-hole. The rear-surface insulating film covers a rear surface relative to the surface of the semiconductor substrate. The annular trench surrounds the through-hole as seen in a direction that is perpendicular to the rear surface, and has formed in an interior thereof a hollow portion that is closed by the rear-surface insulating film as seen in a direction that is parallel to the rear surface.

IPC Classes  ?

  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
  • H01L 27/146 - Imager structures

60.

PHOTODETECTION DEVICE, METHOD FOR PRODUCING SAME, AND ELECTRONIC APPARATUS

      
Application Number JP2022034521
Publication Number 2024/057470
Status In Force
Filing Date 2022-09-15
Publication Date 2024-03-21
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Hattori Hiroyuki

Abstract

The present disclosure relates to: a photodetection device which enables the achievement of a photoelectric conversion unit that has high quantum efficiency in an infrared region; a method for producing this photodetection device; and an electronic apparatus. This photodetection device comprises: a silicon germanium layer that is provided with a photoelectric conversion unit; an inter-pixel light-blocking film that is formed on a first surface side of the silicon germanium layer, the first surface side being the light incident surface side; and a MOS transistor that is formed on a second surface side of the silicon germanium layer, the second surface being on the reverse side of the first surface. The silicon germanium layer is formed so as to have a constant germanium concentration. This technology can be applied, for example, to a ToF sensor or an imaging sensor.

IPC Classes  ?

61.

TERMINAL, COMMUNICATION SYSTEM, AND TERMINAL SYNCHRONIZATION METHOD

      
Application Number JP2023026739
Publication Number 2024/057719
Status In Force
Filing Date 2023-07-21
Publication Date 2024-03-21
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Kitayama, Hideya
  • Nakahara, Kentaro

Abstract

The purpose of the present invention is to, in a communication system comprising a plurality of terminals, ascertain a power supply state of each of the terminals to make power consumption for each terminal uniform, thereby achieving conservation of electric power for the system as a whole. A power supply state assessment information acquisition unit acquires power supply state assessment information for assessing the power supply state of a terminal. A power supply state assessment information communication unit performs communication for mutually exchanging power supply state assessment information with another terminal. A representative terminal determination unit determines a representative terminal on the basis of the power supply state assessment information of the terminal and the other terminal. When the terminal corresponds to the representative terminal, a reference signal reception unit receives a reference signal necessary for synchronization and generates time information. A time information communication unit transmits the time information to the other terminal when the terminal corresponds to the representative terminal, and receives the time information from the representative terminal when the terminal does not correspond to the representative terminal.

IPC Classes  ?

  • H04W 52/02 - Power saving arrangements
  • G01S 19/14 - Receivers specially adapted for specific applications
  • G01S 19/34 - Power consumption
  • G16Y 10/05 - Agriculture
  • G16Y 20/10 - Information sensed or collected by the things relating to location
  • H04W 24/02 - Arrangements for optimising operational condition
  • H04W 56/00 - Synchronisation arrangements
  • H04W 92/18 - Interfaces between hierarchically similar devices between terminal devices

62.

IMAGING DEVICE AND ELECTRONIC APPARATUS

      
Application Number JP2023027050
Publication Number 2024/057724
Status In Force
Filing Date 2023-07-24
Publication Date 2024-03-21
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Takahashi, Seiki
  • Noudo, Shinichiro
  • Watanabe, Maho
  • Ikehara, Shigehiro

Abstract

[Problem] To further improve the separation ratio between a plurality of subpixels included in a pixel. [Solution] This imaging device comprises: a semiconductor substrate that includes photoelectric conversion sections provided respectively for two-dimensionally arranged pixels, and a pixel separation section that separates the photoelectric conversion sections from each other; color filters and on-chip lenses provided respectively for the pixels on one surface of the semiconductor substrate; an inter-filter separation section that is provided between the color filters to include a low-refractive-index material having a refractive index lower than that of the color filters, and that separates the color filters by pixel; and a sub-pixel separation section that separates, by sub-pixel, the photoelectric conversion sections of the pixels each including a plurality of sub-pixels.

IPC Classes  ?

63.

INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, AND PROGRAM

      
Application Number JP2023031090
Publication Number 2024/057904
Status In Force
Filing Date 2023-08-29
Publication Date 2024-03-21
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Ikeya Kensuke

Abstract

The present technology relates to an information processing device, an information processing method, and a program that enable accurate estimation of a distance value. An information processing device according to the present technology comprises a cost volume generation unit that generates a cost volume indicating a probability distribution of distances to an object shown in each pixel of a captured image on the basis of ranging data acquired by a ToF sensor. The present technology can be applied to an information processing system that upsamples distance values acquired by a ToF sensor, for example.

IPC Classes  ?

  • G01S 17/86 - Combinations of lidar systems with systems other than lidar, radar or sonar, e.g. with direction finders
  • G01S 17/89 - Lidar systems, specially adapted for specific applications for mapping or imaging

64.

SEMICONDUCTOR DEVICE

      
Application Number JP2023031772
Publication Number 2024/057949
Status In Force
Filing Date 2023-08-31
Publication Date 2024-03-21
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Taura Tadayuki

Abstract

The present disclosure relates to a semiconductor device that can be individually identified with a simpler configuration. The semiconductor device according to the present disclosure includes a main chip and at least one subchip that is stacked on one surface of the main chip and is smaller in size than the main chip. The subchip includes an ID chip having ID information that is capable of being identified without contact. The present disclosure can be applied to a stacked semiconductor device.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

65.

PHOTODETECTOR AND ELECTRONIC APPLIANCE

      
Application Number JP2023031773
Publication Number 2024/057950
Status In Force
Filing Date 2023-08-31
Publication Date 2024-03-21
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Hasegawa Kenta
  • Moriya Yusuke

Abstract

This technique relates to: a photodetector which makes it possible to improve the reliability of light condensation designs; and an electronic appliance. A photodetector according to one aspect of this technique comprises a semiconductor substrate having a photoelectric conversion part, a spacer layer disposed on the semiconductor substrate, a metasurface layer disposed on the spacer layer, and a sidewall-protecting film disposed at least on a sidewall of the spacer layer. This technique is applicable to image sensors equipped with metasurface layers.

IPC Classes  ?

66.

PHOTODETECTION ELEMENT AND ELECTRONIC APPARATUS

      
Application Number JP2023032306
Publication Number 2024/057995
Status In Force
Filing Date 2023-09-05
Publication Date 2024-03-21
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Mochizuki Futa
  • Niwa Atsumi
  • Yamada Kohei
  • Niida Yoshitaka
  • Imai Yotaro

Abstract

[Problem] To enable pixels to be reduced in size as compared with the prior art and enable on/off switching control to be carried out for each function. [Solution] This photodetection element comprises a photoelectric conversion element that stores electric charges corresponding to the luminous energy of incident light, and a pixel circuit that outputs a pixel signal corresponding to the electric charge stored in the photoelectric conversion element, the pixel circuit including at least one current path and at least two current cutoff switching units that switch whether the current path is cut off.

IPC Classes  ?

  • H04N 25/44 - Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled by partially reading an SSIS array
  • H04N 25/47 - Image sensors with pixel address output; Event-driven image sensors; Selection of pixels to be read out based on image data
  • H04N 25/707 - Pixels for event detection

67.

DISPLAY DEVICE AND ELECTRONIC APPARATUS

      
Application Number JP2023026567
Publication Number 2024/057712
Status In Force
Filing Date 2023-07-20
Publication Date 2024-03-21
Owner
  • SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
  • SONY GROUP CORPORATION (Japan)
Inventor
  • Yokoyama, Kazuki
  • Tsuchiya, Haruki

Abstract

One purpose of the present invention is to improve contrast. The present invention is a display device comprising a pixel circuit that includes: a light-emitting element; a first transistor for supplying a current based on a pixel signal to the light-emitting element; and a second transistor for settingthe potential of an anode of the light-emitting element to an initialization potential when ON, wherein during the period when the light-emitting element is emitting light, the second transistor is turned ON at least once.

IPC Classes  ?

  • G09G 3/3233 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
  • G09F 9/30 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
  • G09G 3/20 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix

68.

INFORMATION PROCESSING DEVICE AND INFORMATION PROCESSING METHOD

      
Application Number EP2023074531
Publication Number 2024/056499
Status In Force
Filing Date 2023-09-07
Publication Date 2024-03-21
Owner
  • SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
  • SONY DEPTHSENSING SOLUTIONS SA/NV (Belgium)
Inventor
  • Gil-Cacho, Jose Manuel
  • Perhavc, Jernej
  • Belokonskiy, Victor

Abstract

An information processing device for processing spot time-of-flight data acquired by a spot time-of-flight device in a time-of-flight measurement, the spot time-of-flight device including a spot illuminator configured to illuminate a scene with spotted light and an image sensor configured to detect spotted light reflected from the scene, the information processing device comprising circuitry configured to: obtain first and second spot time-of-flight data acquired using a first and second measurement configuration of the spot time-of-flight device, respectively, wherein the first measurement configuration differs from the second measurement configuration; detect first spots associated with first pixel positions in the first spot time-of-flight data; detect second spots associated with second pixel positions in the second spot time-of-flight data; and determine spot pairs between the first spots and the second spots, wherein the spot pairs are determined based on the first and second pixel positions.

IPC Classes  ?

  • G01S 7/481 - Constructional features, e.g. arrangements of optical elements
  • G01S 17/32 - Systems determining position data of a target for measuring distance only using transmission of continuous waves, whether amplitude-, frequency-, or phase-modulated, or unmodulated
  • G01S 7/4914 - Detector arrays, e.g. charge-transfer gates
  • G01S 17/894 - 3D imaging with simultaneous measurement of time-of-flight at a 2D array of receiver pixels, e.g. time-of-flight cameras or flash lidar

69.

PHOTOELECTRIC CONVERSION ELEMENT, SOLID-STATE IMAGING ELEMENT, AND RANGING SYSTEM

      
Application Number JP2022034522
Publication Number 2024/057471
Status In Force
Filing Date 2022-09-15
Publication Date 2024-03-21
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Maekawa, Nobue

Abstract

A photoelectric conversion element according to one aspect of the present disclosure comprises a semiconductor layer that is a SiGe layer or a Ge layer and a photodiode formed in the semiconductor layer. This solid-state imaging element further comprises a transistor and a Si layer. The transistor has a source region and a drain region in the semiconductor layer and has a gate electrode in contact with the semiconductor layer via a gate insulating film. The Si layer is formed at the interface between the semiconductor layer and the gate insulating film.

IPC Classes  ?

70.

SEMICONDUCTOR PACKAGE AND ELECTRONIC DEVICE

      
Application Number JP2023026524
Publication Number 2024/057709
Status In Force
Filing Date 2023-07-20
Publication Date 2024-03-21
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Koyama, Toshiki
  • Miyaki, Harumi
  • Kumon, Satoshi

Abstract

Provided is a semiconductor package which bonds a substrate to a support body by means of an adhesive, wherein the adhesive is suppressed from flowing out of the specified area. The semiconductor package comprises a substrate, a semiconductor chip, a support body, and a first adhesive. In this semiconductor package, the semiconductor chip is placed on the substrate plane of the substrate and electrically connected to the substrate. In addition, in the semiconductor package, a portion of the first adhesive flows into a gap between the substrate plane and the semiconductor chip and bonds the substrate to the support body.

IPC Classes  ?

71.

ELECTRONIC DEVICE AND IMAGING APPARATUS

      
Application Number JP2023027100
Publication Number 2024/057729
Status In Force
Filing Date 2023-07-25
Publication Date 2024-03-21
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Tokito, Toshihiro
  • Owaki, Hirofumi
  • Tanaka, Haruki

Abstract

This electronic device comprises: a first chassis that is made of an electrically conductive material and includes a first base portion and a first side wall and a second side wall that are provided on the first base portion and are opposite each other in any one direction orthogonal to a first direction, the first chassis having a box portion for housing a substrate unit; a first case that includes a bottom surface and a first opening portion opposing each other in the first direction, the first case housing the first chassis so that the first base portion opposes the bottom surface in the first direction, the first case achieving electrical connection of the first side wall and the second side wall when at least one of the first side wall and the second side wall is pressed by the inner surface of the first case in at least the any one direction orthogonal to the first direction; and a second case that includes a second opening portion that is joined to the first opening portion, and fixes the first chassis and the second chassis so that the first chassis and the second chassis are electrically connected in a state in which the first opening portion and the second opening portion are joined in the first direction.

IPC Classes  ?

  • H05K 9/00 - Screening of apparatus or components against electric or magnetic fields
  • G02B 7/02 - Mountings, adjusting means, or light-tight connections, for optical elements for lenses
  • G03B 15/00 - Special procedures for taking photographs; Apparatus therefor
  • G03B 17/02 - Bodies
  • G03B 30/00 - Camera modules comprising integrated lens units and imaging units, specially adapted for being embedded in other devices, e.g. mobile phones or vehicles
  • H04N 23/50 - Constructional details
  • H05K 5/00 - Casings, cabinets or drawers for electric apparatus
  • H05K 5/04 - Metal casings

72.

IMAGING ELEMENT AND ELECTRONIC DEVICE

      
Application Number JP2023027181
Publication Number 2024/057732
Status In Force
Filing Date 2023-07-25
Publication Date 2024-03-21
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Komatsu, Yoshihide
  • Date, Koshiro
  • Tagami, Hiroyasu

Abstract

The present invention achieves a low power consumption of an imaging element installed in an electronic device such as a smartphone. An imaging element according to the present technology comprises: an analog circuit part including pixels that perform photoelectric conversion; a logic circuit part that processes signals read out from the pixels; a body electric potential generation part that applies a body electric potential in a direction of reducing a threshold voltage to a well of each of transistors forming the logic circuit part, the well being doped so as to enclose a transistor structure; and a control part that controls the body electric potential for each externally specified operation mode.

IPC Classes  ?

  • H04N 25/70 - SSIS architectures; Circuits associated therewith
  • H04N 25/709 - Circuitry for control of the power supply

73.

LIGHT DETECTION DEVICE AND ELECTRONIC APPARATUS

      
Application Number JP2023027431
Publication Number 2024/057735
Status In Force
Filing Date 2023-07-26
Publication Date 2024-03-21
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Takase Hiroaki

Abstract

The present invention provides a light detection device which is capable of suppressing optical color mixing because of the light reflected by a partition wall part between color filters. Specifically, this light detection device has a configuration that comprises: a semiconductor substrate which is provided with a plurality of photoelectric conversion parts; a color filter layer which comprises a plurality of color filters that are arranged on the light incident surface side of the semiconductor substrate, and a partition wall part that is arranged between the color filters, while being formed of a material that has a lower refractive index than the color filters; a plurality of microlenses which are arranged on the light incident surface side of the color filter layer; and a high-refractive-index structure which is arranged on the optical path of the light collected by the microlenses. In addition, the high-refractive-index structure is formed of a material that has a higher refractive index than a member which is in contact with the light incident surface of the high-refractive-index structure.

IPC Classes  ?

74.

LIGHT DETECTION DEVICE, METHOD FOR MANUFACTURING LIGHT DETECTION DEVICE, AND ELECTRONIC APPARATUS

      
Application Number JP2023027645
Publication Number 2024/057739
Status In Force
Filing Date 2023-07-27
Publication Date 2024-03-21
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Kodama Yoshinori
  • Honda Takayoshi
  • Inoue Toshinori

Abstract

Provided is a light detection device that can reduce the number of steps for a pixel separation part and reduce light scattering in a pixel structure forming an on-chip lens for each of a plurality of pixels. The light detection device comprises a semiconductor substrate, a pixel separation part, and an on-chip lens. The pixel separation part is provided on the semiconductor substrate and separates adjacent pixels from each other. The on-chip lens is disposed in every pixel group composed of two or more pixels on a light incident surface side of the semiconductor substrate, and condenses light from outside onto the pixel groups. The pixel separation part includes an intra-pixel group separation part disposed between adjacent pixels of the pixel groups and having a first dug region extending in the thickness direction of the semiconductor substrate, and a second dug region differing from the first dug region at a position where light is condensed by the on-chip lens. In the intra-pixel separation part, the width of the second dug region is formed narrower than the width of the first dug region in a plan view.

IPC Classes  ?

75.

IMAGING ELEMENT AND ELECTRONIC DEVICE

      
Application Number JP2023029557
Publication Number 2024/057805
Status In Force
Filing Date 2023-08-16
Publication Date 2024-03-21
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Kawamura, Tomohiko
  • Uchida, Tetsuya

Abstract

An imaging element according to an embodiment of the present disclosure comprises: a semiconductor substrate having a photoelectric conversion part for each pixel; one or more pixel transistors provided on one surface of the semiconductor substrate; and a first element separation part and a second element separation part that are embedded in the one surface of the semiconductor substrate, that delimit active regions of the one or more pixel transistors, and that have different depths. In the one or more pixel transistors, a portion of gate electrodes is embedded in at least one of the first and second element separation parts at a different depth.

IPC Classes  ?

76.

IMAGING DEVICE AND ELECTRONIC APPARATUS

      
Application Number JP2023029558
Publication Number 2024/057806
Status In Force
Filing Date 2023-08-16
Publication Date 2024-03-21
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Shiihara, Yu

Abstract

The imaging device according to one embodiment of the present disclosure comprises: a semiconductor substrate having a first surface and a second surface facing each other, and a pixel array unit in which a plurality of unit pixels are arranged in an array in the row direction and the column direction; a photoelectric conversion unit that is provided on the second surface side of the semiconductor substrate for each unit pixel and generates a charge according to the amount of received light by photoelectric conversion; a charge holding unit provided on the first surface side of the semiconductor substrate for each unit pixel and holding charges transferred from the photoelectric conversion unit; and a first light-shielding unit provided on the semiconductor substrate, located between the photoelectric conversion unit and the charge holding unit, and that includes a first horizontal light-shielding part extending in the in-plane direction of the semiconductor substrate and a first vertical light-shielding part orthogonal to the first horizontal light-shielding portion, wherein the first vertical light-shielding part consists of a first row light-shielding part and a first column light-shielding part formed respectively along two adjacent sides of a rectangular unit pixel, and is provided for each unit pixel located in every other column and diagonally at 45°, and in plan view, the first horizontal light-shielding part is the end portion located at or near the intersection of the first row light-shielding part and the first column light-shielding part provided for each unit pixel located in every other column and diagonally at 45°.

IPC Classes  ?

  • H04N 25/62 - Detection or reduction of noise due to excess charges produced by the exposure, e.g. smear, blooming, ghost image, crosstalk or leakage between pixels
  • H04N 25/70 - SSIS architectures; Circuits associated therewith
  • H01L 27/146 - Imager structures

77.

IMAGING DEVICE, IMAGING SYSTEM, AND IMAGING DEVICE DRIVING METHOD

      
Application Number JP2023029594
Publication Number 2024/057810
Status In Force
Filing Date 2023-08-16
Publication Date 2024-03-21
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Ishikawa, Tatsuya
  • Hanzawa, Katsuhiko

Abstract

An imaging device according to one embodiment of the present disclosure comprises a first photoelectric conversion unit, a first floating diffusion, a first transfer transistor, a first readout circuit, and a voltage control unit. The voltage control unit is capable of executing control for supplying a first voltage to the first readout circuit, when a first signal is read out with the first transfer transistor in an off state, and is capable of executing control for supplying, to the first readout circuit, a second voltage lower than the first voltage, when the first signal is read out with the first transfer transistor in an on state.

IPC Classes  ?

  • H04N 25/70 - SSIS architectures; Circuits associated therewith

78.

LIGHT-DETECTION DEVICE AND ELECTRONIC INSTRUMENT

      
Application Number JP2023029672
Publication Number 2024/057814
Status In Force
Filing Date 2023-08-17
Publication Date 2024-03-21
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Uchida, Tetsuya

Abstract

A light-detection device according to one embodiment of the present disclosure comprises: a semiconductor layer having a plurality of photoelectric conversion units that perform photoelectric conversion of light; a pad provided on a first surface side of the semiconductor layer; a via that penetrates through the semiconductor layer and electrically connects to the pad; and a first trench that penetrates through the semiconductor layer at the outer perimeter of the via and is provided so as to surround the via. The first trench is provided in a grid pattern at the outer perimeter of the via in a plan view.

IPC Classes  ?

79.

SOLID-STATE IMAGING DEVICE

      
Application Number JP2023030152
Publication Number 2024/057842
Status In Force
Filing Date 2023-08-22
Publication Date 2024-03-21
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Takeuchi Koichi

Abstract

Provided is a solid-state imaging device that can suppress reflection of light by an upper section of a separation barrier. This solid-state imaging device is provided with pixels, each of which includes: a first light receiving section and a second light receiving section, which are mutually adjacent and receive light in the same wavelength band; and a separation barrier disposed between the first light receiving section and the second light receiving section. The first light receiving section comprises a first photoelectric conversion element and a first phase imparting structure that is disposed on the side where the light enters of the first photoelectric conversion element and that imparts a first phase to the light that has entered. The second light receiving section comprises a second photoelectric conversion element and a second phase imparting structure that is disposed on the side where the light enters of the second photoelectric conversion element and that imparts a second phase, different from the first phase, to the light that has entered.

IPC Classes  ?

80.

INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, AND PROGRAM

      
Application Number JP2023032381
Publication Number 2024/058009
Status In Force
Filing Date 2023-09-05
Publication Date 2024-03-21
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Nakada, Hitoshi
  • Nagumo, Masahiko
  • Shibui, Shuichi
  • Kitami, Hirotaka
  • Saruta, Takashi

Abstract

An information processing device according to the present technology comprises a correction processing unit that has an inference device resulting from an artificial intelligence model that takes, as input data, a stereoscopic captured image, which is a captured image obtained by two cameras for stereo ranging that perform imaging resulting from respectively different focal positions, and parallax that is calculated on the basis of the stereoscopic captured image, the inference device obtaining correction information for the parallax as output data, and the information processing unit performing correction of parallax on the basis of the correction information.

IPC Classes  ?

  • G01C 3/06 - Use of electric means to obtain final indication
  • G03B 35/08 - Stereoscopic photography by simultaneous recording
  • H04N 5/222 - Studio circuitry; Studio devices; Studio equipment
  • H04N 23/45 - Cameras or camera modules comprising electronic image sensors; Control thereof for generating image signals from two or more image sensors being of different type or operating in different modes, e.g. with a CMOS sensor for moving images in combination with a charge-coupled device [CCD] for still images
  • H04N 23/60 - Control of cameras or camera modules

81.

LIGHT DETECTION DEVICE AND ELECTRONIC APPARATUS

      
Application Number JP2023032397
Publication Number 2024/058010
Status In Force
Filing Date 2023-09-05
Publication Date 2024-03-21
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Yoshiba Ippei

Abstract

Provided is a light detection device with which it is possible to suppress deterioration of captured images. This light detection device comprises: a semiconductor layer that has a plurality of cell regions arrayed in the row and column directions in a pixel region, one surface of the semiconductor layer being an element-forming surface, and the other surface of the semiconductor layer being a light incidence surface; and a deflection layer that is provided to a position facing the light incidence surface of the cell regions or provided to a light-incidence-surface-side section of the cell regions. Within the cell regions, there are provided a photoelectric conversion element, a light-shielding film that extends along a direction perpendicular to the thickness direction of the semiconductor layer, and a charge-holding unit that is positioned closer to the element-forming surface than the light-shielding film in the thickness direction of the semiconductor layer. The deflection layer includes, for each cell region, a first region having a first refractive index and a second region having a second refractive index that is higher than the first refractive index, the first and second regions being located at different positions in plan view. The second region is located at a position overlapping the light-shielding film in plan view.

IPC Classes  ?

82.

LIGHT DETECTION DEVICE AND ELECTRONIC APPARATUS

      
Application Number JP2023028395
Publication Number 2024/053299
Status In Force
Filing Date 2023-08-03
Publication Date 2024-03-14
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Soeda, Takaaki
  • Watanabe, Maho

Abstract

A light detection device according to one embodiment of the present disclosure comprises: a semiconductor substrate that has an opposing first surface and second surface, and in which a plurality of pixels are arranged in a matrix, and for each pixel, a photoelectric conversion unit is formed in an embedded manner, said photoelectric conversion unit using photoelectric conversion to generate a charge corresponding to the amount of received light; a microlens that is positioned on the first surface side, straddling a plurality of neighboring pixels; and a plurality of scatterers that are layered on the focusing optical path of the microlens and have different refractive indices.

IPC Classes  ?

  • H01L 27/146 - Imager structures
  • H01L 31/0232 - Optical elements or arrangements associated with the device
  • H04N 25/61 - Noise processing, e.g. detecting, correcting, reducing or removing noise the noise originating only from the lens unit, e.g. flare, shading, vignetting or "cos4"
  • H04N 25/70 - SSIS architectures; Circuits associated therewith

83.

SOLID-STATE IMAGING ELEMENT AND MANUFACTURING METHOD, AND ELECTRONIC DEVICE

      
Application Number JP2023029937
Publication Number 2024/053372
Status In Force
Filing Date 2023-08-21
Publication Date 2024-03-14
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Ishizaki Takeshi

Abstract

The present disclosure relates to a solid-state imaging element and a manufacturing method, and an electronic device that enable a higher image quality to be achieved. The solid-state imaging element comprises: a plurality of pixels; a capacitor that is provided to each pixel and that is configured to have a three-dimensional shape between upper wiring and lower wiring of a wiring layer of the pixel; and a separating part that electrically separates the capacitors of adjacent pixels. Further, the separating part is provided to each pixel so as to surround the capacitor. An interlayer insulating film is provided between the separating parts of the respective pixels. The present technology can be applied to CMOS image sensors, for example.

IPC Classes  ?

  • H01L 27/146 - Imager structures
  • H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
  • H01L 27/04 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body

84.

INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, COMPUTER-READABLE NON-TRANSITORY STORAGE MEDIUM, AND TERMINAL DEVICE

      
Application Number JP2023031153
Publication Number 2024/053479
Status In Force
Filing Date 2023-08-29
Publication Date 2024-03-14
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Matsumoto, Nana
  • Fujita, Takafumi

Abstract

This information processing device is equipped with a control unit. The control unit evaluates the equivalence between a first learning model before weight reduction according to a weight reduction method occurs, and a second learning model after weight reduction according to the weight reduction method occurs. The control unit determines the second learning model on the basis of the evaluation results.

IPC Classes  ?

85.

SEMICONDUCTOR DEVICE, ELECTRONIC DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

      
Application Number JP2023031374
Publication Number 2024/053497
Status In Force
Filing Date 2023-08-30
Publication Date 2024-03-14
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Sakamoto, Akihisa
  • Sugimori, Yusaku

Abstract

A semiconductor device according to one embodiment of the present disclosure comprises: a semiconductor substrate having a first insulating layer and a plurality of first terminals provided in the first insulating layer; and semiconductor elements stacked on the semiconductor substrate and each having a second insulating layer and a plurality of second terminals provided in the second insulating layer and connected to the plurality of first terminals, respectively. The first insulating layer or the second insulating layer has a third insulating layer formed of a material different from that of the first insulating layer and bonding the semiconductor substrate and the semiconductor elements.

IPC Classes  ?

  • H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/3205 - Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layers; After-treatment of these layers
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
  • H01L 27/00 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate

86.

LIGHT-EMITTING DEVICE AND ELECTRONIC EQUIPMENT

      
Application Number JP2023032254
Publication Number 2024/053611
Status In Force
Filing Date 2023-09-04
Publication Date 2024-03-14
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Miura, Kiwamu
  • Toyoda, Takashi

Abstract

Provided is a light-emitting device with which it is possible to ensure a carrier path in a direction away from a light-emitting region while increasing the contact area between a first electrode and a contact electrode. This light-emitting device includes a plurality of light-emitting elements in a light-emitting region, the light-emitting device comprising a contact electrode that is provided to a peripheral region positioned at the periphery of the light-emitting region, and a first electrode that is extended from the light-emitting region to the peripheral region and is connected to the contact electrode. The contact electrode has a plurality of first structures in a section where the first electrode is connected, the plurality of first structures being extended in a direction away from the light-emitting region.

IPC Classes  ?

  • G09F 9/30 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
  • H05B 33/02 - Electroluminescent light sources - Details
  • H05B 33/06 - Electrode terminals
  • H10K 50/10 - OLEDs or polymer light-emitting diodes [PLED]
  • H10K 59/00 - Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group

87.

LIGHT DETECTION DEVICE

      
Application Number JP2023032601
Publication Number 2024/053695
Status In Force
Filing Date 2023-09-07
Publication Date 2024-03-14
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Onodera, Takumi
  • Kamei, Takahiro
  • Sakamoto, Akihisa
  • Akiyama, Katsuya
  • Ogawa, Naoki
  • Osako, Toru
  • Ishii, Yoshiyuki
  • Matsugai, Hiroyasu

Abstract

This light detection device comprises: a substrate that includes a light detection element; chips that are provided to the substrate; a buried layer that is provided so as to cover the chips; a seam portion that occurs in the buried layer and extends to the surface of the buried layer; and a sealing layer that is provided so as to cover the buried layer and the seam portion.

IPC Classes  ?

  • H01L 23/29 - Encapsulation, e.g. encapsulating layers, coatings characterised by the material
  • H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
  • H01L 27/146 - Imager structures

88.

WIRELESS COMMUNICATION TERMINAL, BASE STATION, AND WIRELESS COMMUNICATION SYSTEM

      
Application Number JP2023025876
Publication Number 2024/053247
Status In Force
Filing Date 2023-07-13
Publication Date 2024-03-14
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Motoyama, Hideshi
  • Nakamura, Kazuya

Abstract

The present invention reduces the power consumption of a wireless communication terminal during positioning processing. This wireless communication terminal comprises: a wireless communication unit that performs wireless communication; a positioning processing unit that performs positioning processing on the basis of reception data received via the wireless communication unit; and a control unit that controls power consumption pertaining to the positioning processing on the basis of control information that pertains to the positioning processing and has been acquired via the wireless communication unit. The wireless communication terminal further comprises an amplifier that amplifies a signal received via an antenna. The wireless communication unit transmits position information obtained by the positioning processing unit. The control unit may control operation of the amplifier on the basis of the control information that pertains to the positioning processing and has been acquired via the wireless communication unit.

IPC Classes  ?

  • G01S 19/34 - Power consumption
  • G01S 19/14 - Receivers specially adapted for specific applications
  • H04W 52/02 - Power saving arrangements
  • H04W 64/00 - Locating users or terminals for network management purposes, e.g. mobility management
  • H04W 88/06 - Terminal devices adapted for operation in multiple networks, e.g. multi-mode terminals

89.

INFORMATION PROCESSING DEVICE, PROGRAM, AND INFORMATION PROCESSING METHOD

      
Application Number JP2023027195
Publication Number 2024/053271
Status In Force
Filing Date 2023-07-25
Publication Date 2024-03-14
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Kuwabara, Akito
  • Yoshimura, Shinichi

Abstract

[Problem] To further improve convenience for a user in detecting a change in the surrounding environment based on sensing data. [Solution] Provided is an information processing device comprising: a determination result acquisition unit which acquires a determination result of whether a change in the surrounding environment of a sensor unit indicated by sensing data acquired from the sensor unit satisfies a predetermined condition; and a recognition unit which starts a recognition process for recognizing the situation of the surrounding environment of the sensor unit on the basis of acquisition of the determination result which is acquired from the determination acquisition unit and indicates that the predetermined condition is satisfied.

IPC Classes  ?

  • G06F 3/01 - Input arrangements or combined input and output arrangements for interaction between user and computer
  • G06F 3/16 - Sound input; Sound output

90.

LIGHT DETECTION APPARATUS, DIGITAL DEVICE, AND METHOD FOR PRODUCING LIGHT DETECTION APPARATUS

      
Application Number JP2023030367
Publication Number 2024/053401
Status In Force
Filing Date 2023-08-23
Publication Date 2024-03-14
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Yoshida Shinichi
  • Hojo Naoto

Abstract

Provided is a light detection apparatus capable of improving the saturation charge amount Qs of a photoelectric conversion unit. Specifically, the light detection apparatus is configured to comprise: a semiconductor substrate on which a plurality of photoelectric conversion units are formed; and an element separation part which has a trench part formed between photoelectric conversion units on the semiconductor substrate, a semiconductor layer disposed in the trench part and covering side walls of the trench part, and a functional layer disposed in a space in the trench part covered by the semiconductor layer. The photoelectric conversion units are configured to have an N-type semiconductor region in a region contacting the semiconductor layer. The semiconductor layer has a P-type impurity concentration of not more than 1e16/cm3. The functional layer induces holes in the functional layer side of the semiconductor layer.

IPC Classes  ?

  • H01L 27/146 - Imager structures
  • H01L 31/10 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by at least one potential-jump barrier or surface barrier, e.g. phototransistors

91.

SEMICONDUCTOR DEVICE AND ELECTRONIC EQUIPMENT

      
Application Number JP2023031052
Publication Number 2024/053466
Status In Force
Filing Date 2023-08-28
Publication Date 2024-03-14
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Dong Wenshuang
  • Tanaka Yuto
  • Kanatake Mitsuhito
  • Kakoiyama Naoki
  • Hareyama Kosuke

Abstract

This semiconductor device: enables a reduction in the stress on a connecting member that electrically connects a substrate and a semiconductor element to each other; and enables miniaturization of a package. This semiconductor device comprises: a substrate; a semiconductor element provided on the substrate; and a connecting member that electrically connects the substrate and the semiconductor element. The substrate has: a first surface to which the semiconductor element is attached; and a second surface that is positioned on the upper side of the first surface in the vertical direction, and that has disposed thereon an electrode to which the connecting member is connected.

IPC Classes  ?

  • H01L 23/02 - Containers; Seals
  • H01L 23/10 - Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
  • H01L 27/146 - Imager structures

92.

PHOTODETECTION ELEMENT AND ELECTRONIC DEVICE

      
Application Number JP2023031513
Publication Number 2024/053512
Status In Force
Filing Date 2023-08-30
Publication Date 2024-03-14
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Mori, Hiroyuki

Abstract

Provided is a photodetection element comprising: a photoelectric conversion unit that is provided on a semiconductor substrate, and generates charges in accordance with incident light; a first storage unit that stores the charges generated by the photoelectric conversion unit; an amplification transistor that generates an input signal according to the amount of the charges stored in the first storage unit; a second storage unit to which saturated charges are transferred from the photoelectric conversion unit via the first storage unit; a conversion efficiency switching transistor that transfers the saturated charges to the second storage unit and switches conversion efficiency; a reset transistor that resets the charges stored in the first storage unit and the saturated charges stored in the second storage unit; and a differential input circuit that compares the input signal generated by the amplification transistor with a reference signal to output a comparison result, wherein the second storage unit includes an MIM capacitor having a three-dimensional structure.

IPC Classes  ?

  • H04N 25/772 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising A/D, V/T, V/F, I/T or I/F converters
  • H04N 25/70 - SSIS architectures; Circuits associated therewith
  • H04N 25/771 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion
  • H01L 27/146 - Imager structures

93.

HIGH ELECTRON MOBILITY TRANSISTOR

      
Application Number JP2022032732
Publication Number 2024/047783
Status In Force
Filing Date 2022-08-31
Publication Date 2024-03-07
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Taketomo, Mikihiro
  • Mori, Kunihiko
  • Yanagita, Masashi

Abstract

A high electron mobility transistor according to an embodiment of the present disclosure comprises a heterojunction structure that includes a GaN channel layer in which two recesses are formed with a predetermined gap therebetween. The high electron mobility transistor further comprises a regrowth layer that is formed so as to bury the recesses, source and drain electrodes that are in ohmic contact with the regrowth layer, and a gate electrode that is disposed at a location between the two recesses of the GaN channel layer with a gate insulating film interposed therebetween. The regrowth layer is configured to include a first GaN layer that is doped with Si at a relatively high concentration, and one or a plurality of second GaN layers that are doped with Si at a relatively low concentration, the second GaN layer being formed inside the first GaN layer.

IPC Classes  ?

  • H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
  • H01L 21/338 - Field-effect transistors with a Schottky gate
  • H01L 29/812 - Field-effect transistors with field effect produced by a PN or other rectifying junction gate with a Schottky gate

94.

INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, AND VEHICLE CONTROL SYSTEM

      
Application Number JP2023028210
Publication Number 2024/048180
Status In Force
Filing Date 2023-08-02
Publication Date 2024-03-07
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Suzuki, Motohiro
  • Nishida, Keiji

Abstract

The information processing device according to the present disclosure comprises: a line-of-sight acquisition portion that acquires the driver's line-of-sight information from a line-of-sight detection unit that detects the driver's line of sight; an audio acquisition portion that acquires audio information of the driver from a sound collection unit; an operation reception portion; and a risk calculation portion. The operation reception portion receives operation instructions uttered by the driver when the audio of the driver includes a prescribed wake word. The risk calculation portion calculates the risk levels for the vehicle being driven by the driver and the surroundings of the vehicle. The operation reception portion has a wake word omission function that, when the driver continues to visually observe a prescribed area inside the vehicle, receives operation instructions uttered by the driver even when the wake word is not included in the audio of the driver, and if the risk level calculated by the risk calculation portion is greater than or equal to a prescribed threshold value, the wake word omission function is disabled.

IPC Classes  ?

95.

COMMUNICATION DEVICE, COMMUNICATION METHOD, AND PROGRAM

      
Application Number JP2023029486
Publication Number 2024/048263
Status In Force
Filing Date 2023-08-15
Publication Date 2024-03-07
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Sato Kanta
  • Mahara Kumiko

Abstract

The present technology relates to a communication device, a communication method, and a program that make it possible to detect data abnormality in a signal portion of a predetermined pattern for serial communication. The communication device of the present technology performs I2C communication with an external communication device serving as a master, and detects abnormality in a signal portion of a predetermined pattern generated by the external communication device, on the basis of at least one of a first temporal restriction that is set with respect to a low period of a clock signal after completion of transmission of a response signal following data, and a second temporal restriction that is set with respect to a high period thereof. The present technology may be applied to an image sensor.

IPC Classes  ?

  • G06F 13/42 - Bus transfer protocol, e.g. handshake; Synchronisation
  • G06F 13/36 - Handling requests for interconnection or transfer for access to common bus or bus system
  • G06F 13/38 - Information transfer, e.g. on bus
  • G06F 21/55 - Detecting local intrusion or implementing counter-measures

96.

PHOTODETECTOR AND RANGING DEVICE

      
Application Number JP2023029493
Publication Number 2024/048267
Status In Force
Filing Date 2023-08-15
Publication Date 2024-03-07
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Tsugawa, Hidenobu
  • Nakamura, Ryoichi

Abstract

A photodetector comprising: a first semiconductor substrate having a first surface and a second surface opposing each other and a pixel array section in which a plurality of pixels is arranged in an array; a light receiving section that is provided inside the first semiconductor substrate for each pixel and generates carriers through photoelectric conversion according to the amount of light received; a multiplier section that is provided on the first surface for each pixel and avalanche multiplies the carriers generated in the light receiving section; an insulating layer laminated on the first surface and having one or a plurality of openings at predetermined positions; one or a plurality of polysilicon films that is provided along the boundary of adjacent pixels on the first surface side with the insulating layer interposed therebetween and that is electrically connected to the light receiving section through the one or the plurality of openings; one or a plurality of first wirings provided along the outer shape of the pixels on the first surface side; and one or a plurality of first connection wirings that is provided along the outer shape of the pixels on the first surface side and electrically connects the one or the plurality of polysilicon films and the one or the plurality of first wirings.

IPC Classes  ?

  • H01L 27/146 - Imager structures
  • G01C 3/06 - Use of electric means to obtain final indication
  • G01S 7/4863 - Detector arrays, e.g. charge-transfer gates
  • G01S 7/4914 - Detector arrays, e.g. charge-transfer gates
  • H01L 31/107 - Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier working in avalanche mode, e.g. avalanche photodiode

97.

DISPLAY DEVICE, ELECTRONIC EQUIPMENT, AND DISPLAY DEVICE DRIVING METHOD

      
Application Number JP2023029502
Publication Number 2024/048268
Status In Force
Filing Date 2023-08-15
Publication Date 2024-03-07
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Inaba, Shusei

Abstract

A display device according to one aspect of the present disclosure comprises a plurality of pixels and a driving unit, each of the plurality of pixels includes a light-emitting element, a capacitor, a write transistor that stores a voltage corresponding to a pixel signal in the capacitor, a drive transistor that supplies a current corresponding to the voltage stored in the capacitor to the light-emitting element, a light emission control transistor that controls whether to supply the current from the drive transistor to the light-emitting element, and an initialization transistor in which one of a source node and a drain node is connectable to the anode of the light-emitting element, and the other is connectable to the cathode of the light-emitting element, and the drive unit turns off the initialization transistors provided in all of the plurality of pixels at or before the timing at which the light emission control transistors provided in the pixels that emit light at the same time, among the plurality of transistors, are turned off.

IPC Classes  ?

  • G09G 3/3233 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
  • G09F 9/30 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
  • G09G 3/20 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
  • H05B 33/02 - Electroluminescent light sources - Details
  • H10K 50/10 - OLEDs or polymer light-emitting diodes [PLED]
  • H10K 59/00 - Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group

98.

INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, AND VEHICLE INTERIOR MONITORING DEVICE

      
Application Number JP2023029551
Publication Number 2024/048275
Status In Force
Filing Date 2023-08-16
Publication Date 2024-03-07
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Seta, Shoji

Abstract

An information processing device according to the present disclosure comprises a control unit that controls operation of a plurality of light sources which are each included in a module and which emit light into a vehicle interior and/or an imaging unit which images at least part of a region irradiated with the light and which acquires imaging information, wherein, when the temperature of the module exceeds a first threshold value, the control unit controls the operation of the plurality of light sources and/or the imaging unit and restricts a function of the module.

IPC Classes  ?

  • G01S 7/497 - Means for monitoring or calibrating
  • B60R 1/29 - Real-time viewing arrangements for drivers or passengers using optical image capturing systems, e.g. cameras or video systems specially adapted for use in or on vehicles for viewing an area inside the vehicle, e.g. for viewing passengers or cargo

99.

LIGHT DETECTION ELEMENT AND ELECTRONIC DEVICE

      
Application Number JP2023029717
Publication Number 2024/048301
Status In Force
Filing Date 2023-08-17
Publication Date 2024-03-07
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Nakamura, Ryosuke
  • Hattori, Yuki

Abstract

This light detection element comprises: a plurality of pixels which are disposed in the planar direction; and a separation part which extends between adjacent pixels in a direction intersecting the planar direction such that adjacent pixels among a plurality of pixels are separated from each other, wherein the plurality of pixels each include a photoelectric conversion element and a plurality of transistors, and, in a plan view, gate electrodes of respective specific transistors among the plurality of transistors of each of adjacent pixels are disposed opposite to each other with the separation part therebetween, and are connected to each other across the separation part.

IPC Classes  ?

  • H01L 27/146 - Imager structures
  • H04N 25/70 - SSIS architectures; Circuits associated therewith
  • H04N 25/77 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
  • H04N 25/771 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion

100.

OBJECT RECOGNITION SYSTEM, OBJECT RECOGNITION DEVICE, AND OBJECT RECOGNITION METHOD

      
Application Number JP2023029980
Publication Number 2024/048346
Status In Force
Filing Date 2023-08-21
Publication Date 2024-03-07
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Kumagai, Isao

Abstract

An object recognition system according to one embodiment of the present disclosure comprises: a plurality of light sources that irradiate an object with light including infrared rays; a control unit that turns on the plurality of light sources at mutually different timings; and an imaging unit that acquires a distance image and an infrared image of the object at each timing. The control unit superimposes the distance images from each timing to generate a composite distance image and superimposes the infrared images from each timing to generate a composite infrared image, and recognizes the object on the basis of the composite distance image and the composite infrared image.

IPC Classes  ?

  • G01B 11/24 - Measuring arrangements characterised by the use of optical techniques for measuring contours or curvatures
  • G01C 3/06 - Use of electric means to obtain final indication
  • G01S 17/04 - Systems determining the presence of a target
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