Sony Semiconductor Solutions Corporation

Japan

Back to Profile

1-100 of 8,770 for Sony Semiconductor Solutions Corporation Sort by
Query
Aggregations
IP Type
        Patent 8,768
        Trademark 2
Jurisdiction
        World 4,674
        United States 4,087
        Canada 9
Date
New (last 4 weeks) 121
2024 April (MTD) 88
2024 March 124
2024 February 140
2024 January 150
See more
IPC Class
H01L 27/146 - Imager structures 3,040
H04N 5/369 - SSIS architecture; Circuitry associated therewith 1,164
H04N 5/3745 - Addressed sensors, e.g. MOS or CMOS sensors having additional components embedded within a pixel or connected to a group of pixels within a sensor matrix, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components 703
H04N 5/378 - Readout circuits, e.g. correlated double sampling [CDS] circuits, output amplifiers or A/D converters 623
H04N 5/374 - Addressed sensors, e.g. MOS or CMOS sensors 586
See more
NICE Class
09 - Scientific and electric apparatus and instruments 2
10 - Medical apparatus and instruments 2
42 - Scientific, technological and industrial services, research and design 2
Status
Pending 1,642
Registered / In Force 7,128
  1     2     3     ...     88        Next Page

1.

PIXEL SUBSTRATE AND LIGHT RECEIVING APPARATUS

      
Application Number 18277772
Status Pending
Filing Date 2022-02-17
First Publication Date 2024-04-25
Owner Sony Semiconductor Solutions Corporation (Japan)
Inventor
  • Moradi Khanshan, Tohid
  • Kawazu, Naoki

Abstract

A pixel substrate includes a photoelectric conversion element. The photoelectric conversion element includes a doped region and a substrate region. The doped region and the substrate region form a pn junction. A pixel circuit is electrically connected to a first supply line and the photoelectric conversion element. A protection circuit is configured to short-circuit the first supply line and the substrate region when a voltage difference between the first supply line and the substrate region falls below a negative threshold voltage.

IPC Classes  ?

  • H04N 25/709 - Circuitry for control of the power supply
  • H04N 25/77 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components

2.

DISPLAY DEVICE, DRIVE METHOD FOR DISPLAY DEVICE, AND ELECTRONIC APPARATUS

      
Application Number 18389682
Status Pending
Filing Date 2023-12-19
First Publication Date 2024-04-25
Owner Sony Semiconductor Solutions Corporation (Japan)
Inventor Toyomura, Naobumi

Abstract

A display device includes at least display elements arranged in a two-dimensional matrix, data lines provided for respective display element columns, and a source driver that supplies a video signal voltage to the data lines, in which a display element row includes a display element belonging to a first group and a display element belonging to a second group different from the first group, the source driver includes a ramp signal generating circuit and a switch circuit that causes a data line to hold a video signal voltage, and when output of the ramp signal generating circuit and a data line are switched from a connected state to a disconnected state in order to cause the data line corresponding to a certain display element to hold a video signal voltage, a data line corresponding to a display element belonging to a group different from the group, to which the certain display element belongs, and output of the ramp signal generating circuit are switched from the disconnected state to the connected state.

IPC Classes  ?

  • G09G 3/3275 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] - Details of drivers for data electrodes
  • G09G 3/3266 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] - Details of drivers for scan electrodes
  • G09G 3/36 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix by control of light from an independent source using liquid crystals

3.

IMAGING DEVICE AND ELECTRONIC APPARATUS

      
Application Number 18546255
Status Pending
Filing Date 2022-01-25
First Publication Date 2024-04-25
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor He, Yilun

Abstract

An imaging device of an embodiment of the disclosure includes: a semiconductor substrate in which multiple sensor pixels are arranged in array, the semiconductor substrate having a first surface serving as a light incident surface and a second surface opposed thereto; a photoelectric conversion section provided on a side of the first surface inside the semiconductor substrate and generating electric charge corresponding to a light reception amount by photoelectric conversion; a charge-holding section provided on a side of the second surface inside the semiconductor substrate and holding the electric charge transferred from the photoelectric conversion section; a first light-blocking section extending in an in-plane direction of the semiconductor substrate between the photoelectric conversion section and the charge-holding section; and a light-condensing optical system provided on the side of the first surface and condensing incident light on a substantial geometric center of the first light-blocking section in a plan view.

IPC Classes  ?

4.

SOLID-STATE IMAGING DEVICE, METHOD FOR MANUFACTURING COVER GLASS, AND ELECTRONIC APPARATUS

      
Application Number 18548268
Status Pending
Filing Date 2022-02-25
First Publication Date 2024-04-25
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Takahashi, Katsunori
  • Hirooka, Shoichi

Abstract

A solid-state imaging device with high versatility having a cavity-less CSP structure capable of reducing the occurrence of flare and also being applied to chip size reduction, a method for manufacturing a cover glass, and an electronic apparatus. A solid-state imaging device includes: a sensor substrate in which a plurality of pixels is arranged; a semiconductor substrate having an upper surface on which the sensor substrate is mounted, the semiconductor substrate being configured to connect an electric signal converted by the pixel to a bump or an external connection terminal disposed on a lower surface; a microlens array disposed on an upper surface of the sensor substrate; a resin disposed on an upper surface of the microlens array; and a cover glass bonded to the microlens array via the resin and having a moth-eye structure on a surface of the cover glass.

IPC Classes  ?

  • G02B 1/118 - Anti-reflection coatings having sub-optical wavelength surface structures designed to provide an enhanced transmittance, e.g. moth-eye structures
  • H01L 27/146 - Imager structures

5.

IMAGING DEVICE AND ANALOG-TO-DIGITAL CONVERSION CIRCUIT

      
Application Number 18548278
Status Pending
Filing Date 2022-02-01
First Publication Date 2024-04-25
Owner Sony Semiconductor Solutions Corporation (Japan)
Inventor Togasaki, Yusuke

Abstract

An imaging device of the present disclosure includes a first pixel circuit and a generation circuit. The first pixel circuit includes a first light-receiving circuit, a first comparator, a first control circuit, and a first latch circuit. The first light-receiving circuit is configured to generate a first pixel signal corresponding to the amount of received light. The first comparator is configured to generate a first comparison signal by comparing the first pixel signal with a first reference signal having a ramp waveform. The first control circuit is configured to generate a first comparison output signal by turning on and off an output of the first comparison signal on the basis of a first control signal. The first latch circuit is configured to latch a time code on the basis of transition of the first comparison output signal. The generation circuit is configured to generate the first control signal.

IPC Classes  ?

  • H04N 25/772 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising A/D, V/T, V/F, I/T or I/F converters
  • H03M 1/56 - Input signal compared with linear ramp
  • H04N 25/76 - Addressed sensors, e.g. MOS or CMOS sensors

6.

CHARGING SYSTEM

      
Application Number 18547708
Status Pending
Filing Date 2022-01-13
First Publication Date 2024-04-25
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Uno, Karin

Abstract

The charging system of the present disclosure includes: an electronic device having a first battery; and a charging device, in which the charging device includes a second battery that charges the first battery, a determination unit that determines whether or not the first battery is chargeable to a fully charged state, on the basis of a remaining charge amount of the first battery and a remaining charge amount of the second battery, and a charging control unit that controls a start of charging of the first battery by the second battery, on the basis of a result of the determination of the determination unit.

IPC Classes  ?

  • H02J 7/00 - Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries

7.

PHOTODETECTION ELEMENT

      
Application Number JP2023036709
Publication Number 2024/085018
Status In Force
Filing Date 2023-10-10
Publication Date 2024-04-25
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Okabe, Yuta
  • Takizawa, Syuuiti
  • Enoki, Osamu
  • Murata, Masaki
  • Hirano, Yoshiyuki

Abstract

A first photodetection element (10) according to one embodiment of the present disclosure comprises a first electrode (11), a second electrode (13) that is arranged opposite the first electrode (11), and a photoelectric conversion layer (12) that is arranged between the first electrode (11) and the second electrode (13), includes fluorine and binary semiconductor nanoparticles that include indium, and has an indium/fluorine atom count ratio of 100–150.

IPC Classes  ?

  • H01L 31/08 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
  • H01L 27/146 - Imager structures
  • H10K 39/32 - Organic image sensors

8.

IMAGE PROCESSING DEVICE, IMAGE PROCESSING METHOD, AND RECORDING MEDIUM

      
Application Number JP2023034009
Publication Number 2024/084879
Status In Force
Filing Date 2023-09-20
Publication Date 2024-04-25
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Hosoi, Izumu

Abstract

An image processing device includes circuitry that recognizes and extracts an object included in a captured image, and that converts, using an artificial intelligence (AI) model, a region image including the object to generate a feature image. The circuitry generates a mask image by combining the captured image with the feature image.

IPC Classes  ?

  • G06F 21/32 - User authentication using biometric data, e.g. fingerprints, iris scans or voiceprints
  • G06F 21/62 - Protecting access to data via a platform, e.g. using keys or access control rules

9.

PHOTODETECTOR, ELECTRONIC APPARATUS, AND OPTICAL ELEMENT

      
Application Number JP2023036440
Publication Number 2024/084991
Status In Force
Filing Date 2023-10-05
Publication Date 2024-04-25
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Katono, Haruka
  • Toumiya, Yoshinori
  • Saito, Hiroshi
  • Moriya, Yusuke

Abstract

There is provided a photodetector. The photodetector includes a light guide including a plurality of structures each having a size equal to or less than a wavelength of incident light, a first material, a second material, wherein a combination of the first material and the second material is provided above and/or between the plurality of structures and wherein the first material and the second material each has a refractive index different from a refractive index of the plurality of structures and a photoelectric converter that photoelectrically converts light incident via the light guide.

IPC Classes  ?

10.

DISPLAY DEVICE

      
Application Number JP2023030926
Publication Number 2024/084815
Status In Force
Filing Date 2023-08-28
Publication Date 2024-04-25
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Hanyu, Yuichiro

Abstract

This display device is provided with: a thin-film transistor that has a gate electrode and a first main electrode and second main electrode as a pair provided on the sides of the gate electrode in a gate length direction; a storage capacitor that is provided in a region overlapping the thin-film transistor and is electrically connected to the first main electrode; a first light-blocking body that is provided between the first main electrode and the storage capacitor and provided between the gate electrode and the first main electrode, and blocks incident light in the gate length direction; and a second light-blocking body that is provided between the second main electrode and the storage capacitor and provided between the gate electrode and the second main electrode, and blocks incident light in the gate length direction.

IPC Classes  ?

  • G02F 1/1368 - Active matrix addressed cells in which the switching element is a three-electrode device
  • G09F 9/30 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements

11.

SEMICONDUCTOR DEVICE

      
Application Number JP2023033323
Publication Number 2024/084865
Status In Force
Filing Date 2023-09-13
Publication Date 2024-04-25
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Nonaka, Yasuhiro
  • Akiyama, Kentaro
  • Ono, Toshiaki

Abstract

A semiconductor device comprising: a first semiconductor element having, in one surface thereof, a pixel region in which a plurality of pixels have been disposed; a second semiconductor element mounted on said surface in an area outside the pixel region and having a first circuit electrically connected to the pixels; and a third semiconductor element mounted on the reverse side of the second semiconductor element from the first semiconductor element and having a second circuit electrically connected to the pixels.

IPC Classes  ?

12.

PHOTODETECTION ELEMENT AND ELECTRONIC APPARATUS

      
Application Number JP2023035566
Publication Number 2024/084921
Status In Force
Filing Date 2023-09-29
Publication Date 2024-04-25
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Ohkawa Takeshi
  • Oyakawa Takeshi
  • Watanabe Akihiro
  • Sekiya Akito
  • Luo Dan

Abstract

[Problem] To provide a photodetection element and an electronic apparatus which can suppress a degradation in measurement accuracy due to a temperature change. [Solution] In order to address the problem, provided is a photodetection element which comprises: a photodiode which performs photoelectric conversion on incident light and outputs a photocurrent; and a control circuit which controls to change the potential of one end of the photodiode according to a temperature pertaining to the photodiode.

IPC Classes  ?

  • G01S 7/497 - Means for monitoring or calibrating
  • H04N 25/773 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising A/D, V/T, V/F, I/T or I/F converters comprising photon counting circuits, e.g. single photon detection [SPD] or single photon avalanche diodes [SPAD]
  • H01L 31/107 - Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier working in avalanche mode, e.g. avalanche photodiode
  • H01L 31/10 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by at least one potential-jump barrier or surface barrier, e.g. phototransistors

13.

DISPLAY APPARATUS AND ELECTRONIC DEVICE

      
Application Number JP2023033885
Publication Number 2024/084876
Status In Force
Filing Date 2023-09-19
Publication Date 2024-04-25
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Toyomura, Naobumi
  • Yoshida, Mayuko

Abstract

One purpose of the present invention is, for example, to improve contrast and reduce size of a display apparatus. Provided is a display apparatus including a pixel circuit having a light-emitting element, a first transistor that controls a current flowing through the light-emitting element in accordance with a voltage based on a pixel signal inputted via a signal line, and a second transistor and first capacitor connected in series between a node at a signal line potential and a node at an anode potential of the light-emitting element.

IPC Classes  ?

  • G09G 3/3233 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
  • G09G 3/20 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix

14.

LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING LIGHT EMITTING DEVICE

      
Application Number 18548126
Status Pending
Filing Date 2022-02-21
First Publication Date 2024-04-25
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Miura, Toshihiro
  • Hasegawa, Toshiaki
  • Sasaki, Toru
  • Kashihara, Hiroyuki

Abstract

A light emitting device includes a substrate and a light emitting body. The light emitting body includes a plurality of light emitting elements and an insulating body in which the plurality of light emitting elements is embedded except for a light emitting surface of the plurality of light emitting elements. The plurality of light emitting elements is formed from a singulated compound semiconductor layer and is arranged in a row direction and a column direction. The substrate includes a drive circuit, a first terminal, and a second terminal and is joined to the light emitting body. The drive circuit drives the plurality of light emitting elements. The first terminal and the second terminal electrically couple the drive circuit and the plurality of light emitting elements to each other.

IPC Classes  ?

  • H01L 33/62 - Arrangements for conducting electric current to or from the semiconductor body, e.g. leadframe, wire-bond or solder balls
  • H01L 25/075 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different main groups of groups , or in a single subclass of , , e.g. forming hybrid circuits
  • H01L 27/15 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier, specially adapted for light emission
  • H01L 33/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof
  • H01L 33/42 - Transparent materials
  • H01L 33/46 - Reflective coating, e.g. dielectric Bragg reflector
  • H01L 33/50 - Wavelength conversion elements
  • H01L 33/58 - Optical field-shaping elements

15.

IMAGING DEVICE AND ELECTRONIC APPARATUS

      
Application Number 18548412
Status Pending
Filing Date 2021-03-30
First Publication Date 2024-04-25
Owner Sony Semiconductor Solutions Corporation (Japan)
Inventor Sasano, Keiji

Abstract

An imaging device of an embodiment of the present disclosure includes: a pixel array part in which a plurality of pixels is disposed in a row direction and a column direction; a photoelectric conversion layer including a compound semiconductor; and an optical member in which a first refractive index portion and a second refractive index portion having mutually different refractive indices are disposed alternately from a central part to an outer peripheral part. The optical member is disposed on side of a light entering surface of the photoelectric conversion layer to straddle the plurality of pixels adjacent at least in the row direction or the column direction.

IPC Classes  ?

16.

INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND SENSING SYSTEM

      
Application Number 18546009
Status Pending
Filing Date 2021-12-17
First Publication Date 2024-04-25
Owner Sony Semiconductor Solutions Corporation (Japan)
Inventor
  • Kawamura, Yuusuke
  • Kitano, Kazutoshi
  • Takahashi, Kousuke
  • Kubota, Takeshi

Abstract

An information processing apparatus according to an embodiment includes a first recognition unit (122) that performs recognition processing based on a point group output by a photodetection distance measurement unit (11), and outputs three-dimensional recognition information of a target object, the photodetection distance measurement unit (11) including a light transmission unit (101) that transmits light modulated by a frequency continuous modulation wave and a light reception unit (103) that receives light and outputs a reception signal, and outputting, based on the reception signal, a point group including a plurality of points each having velocity information, a generation unit (125) that generates vibration distribution information indicating a vibration distribution of the target object based on the velocity information and the three-dimensional recognition information, and a detection unit (20) that detects an abnormality of the target object based on the vibration distribution information.

IPC Classes  ?

  • G01H 9/00 - Measuring mechanical vibrations or ultrasonic, sonic or infrasonic waves by using radiation-sensitive means, e.g. optical means

17.

SOLID-STATE IMAGING ELEMENT AND ELECTRONIC EQUIPMENT

      
Application Number 18548034
Status Pending
Filing Date 2022-01-25
First Publication Date 2024-04-25
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Okawa, Tatsuya
  • Satake, Yosuke

Abstract

A solid-state imaging element having an array of light receiving pixels is disclosed. A light receiving pixel includes a pair of photoelectric conversion units, a first separation region, and a second separation region. The pair of photoelectric conversion units is disposed adjacent to each other and has a shared floating diffusion (FD). The first separation region surrounds the pair of photoelectric conversion units. The second separation region is disposed between the pair of photoelectric conversion units. The first separation region has a rectangular shape in plan view and extends from a surface on the opposite side to a light incident surface of the semiconductor layer toward the light incident surface. The second separation region is disposed along a diagonal line of the first separation region extends from the surface on the opposite side to the light incident surface of the semiconductor layer toward the light incident surface.

IPC Classes  ?

18.

INFORMATION PROCESSING DEVICE AND METHOD

      
Application Number 18263666
Status Pending
Filing Date 2022-01-13
First Publication Date 2024-04-25
Owner Sony Semiconductor Solutions Corporation (Japan)
Inventor
  • Kitamura, Takuya
  • Nagumo, Takefumi

Abstract

The present disclosure relates to an information processing device and an information processing method achieving suppression of a drop of coding efficiency. The present disclosure relates to an information processing device and an information processing method achieving suppression of a drop of coding efficiency. A depth value that wraps around a predetermined value range is quantized by using a predetermined quantization step. A difference value between the quantized depth value and a predicted value of the depth value is derived. A turnback value of the depth value is quantized by using the quantization step. The derived difference value is appropriately corrected by using the quantized turnback value. The appropriately corrected difference value is coded. For example, the present disclosure is applicable to an information processing device, an image processing device, electronic equipment, an information processing method, an image processing method, a program, or others.

IPC Classes  ?

  • G01S 7/4914 - Detector arrays, e.g. charge-transfer gates

19.

TIME-OF-FLIGHT DATA GENERATION CIRCUITRY AND TIME-OF-FLIGHT DATA GENERATION METHOD

      
Application Number 18278178
Status Pending
Filing Date 2022-02-25
First Publication Date 2024-04-25
Owner Sony Semiconductor Solutions Corporation (Japan)
Inventor
  • Isler, Stefan
  • Cambareri, Valerio

Abstract

The present disclosure generally pertains to time-of-flight data generation circuitry, configured to: acquire a time-of-flight (ToF) data stream using a ToF camera; acquire a brightness change event data stream using an event-based vision sensor (EVS), camera; correlate the time-of-flight data stream with the brightness change event data stream in time with each other for generating at least one time-of-flight data frame; and generate the at least one time-of-flight data frame based on the correlation.

IPC Classes  ?

  • G01S 17/894 - 3D imaging with simultaneous measurement of time-of-flight at a 2D array of receiver pixels, e.g. time-of-flight cameras or flash lidar
  • G01S 7/4861 - Circuits for detection, sampling, integration or read-out
  • G01S 7/4865 - Time delay measurement, e.g. time-of-flight measurement, time of arrival measurement or determining the exact position of a peak
  • G01S 17/66 - Tracking systems using electromagnetic waves other than radio waves

20.

ELECTRONIC DEVICE, METHOD AND COMPUTER PROGRAM

      
Application Number 18276254
Status Pending
Filing Date 2022-02-10
First Publication Date 2024-04-25
Owner Sony Semiconductor Solutions Corporation (Japan)
Inventor
  • Gimeno, Cecilia
  • Ding, Qing

Abstract

An electronic device comprising circuitry, the circuitry comprising a mix driver (MVD) for providing a modulation In signal to pixels of a time of flight pixel chip (P500), and at least one Save and Share current circuitry (51, S2) connected to the mix driver (MVD), wherein the Save and Share circuitry (S1, S2) is configured to save charge provided by a power supply (VDD) in a capacitor (CS1, CS2) and to share the saved charge to the pixels of the time of flight pixel chip (P500). A logic chip (L500) comprises an input (l_in) and a buffer block (CLT500), where a modulation signal (GDA) is supplied to the input (1_in) and is delivered to the pixel chip (P500) via the buffer block (CLT500). Capacitors (CS1, CS2) help the mix driver (MVD) with the charging and discharging, respectively, of the pixel units in the pixel chip (P500). Frequencies used for the modulation signal (GDA) may be in the range of several tens of MHz to several hundreds of MHz. The buffer block (CLT500) comprises two inverting buffers (1501, 1502), and the Mix driver (MVD). The total average and peak to peak current consumption may be reduced, and the rising and falling slopes are also improved. The electronic device may for example be an image sensor, e.g. an image sensor of an indirect time of flight camera, iToF. An indirect time of flight camera may resolve distance by measuring a phase shift of an emitted light and a back scattered light.

IPC Classes  ?

  • G01S 7/4861 - Circuits for detection, sampling, integration or read-out
  • G01S 7/4865 - Time delay measurement, e.g. time-of-flight measurement, time of arrival measurement or determining the exact position of a peak
  • G01S 17/894 - 3D imaging with simultaneous measurement of time-of-flight at a 2D array of receiver pixels, e.g. time-of-flight cameras or flash lidar

21.

SOLID-STATE IMAGING DEVICE, MANUFACTURING METHOD THEREOF, AND CAMERA WITH ALTERNATIVELY ARRANGED PIXEL COMBINATIONS

      
Application Number 18400105
Status Pending
Filing Date 2023-12-29
First Publication Date 2024-04-25
Owner Sony Semiconductor Solutions Corporation (Japan)
Inventor
  • Ishiwata, Hiroaki
  • Ha, Sanghoon

Abstract

A solid-state imaging device includes a semiconductor substrate; and a pixel unit having a plurality of pixels on the semiconductor substrate, wherein the pixel unit includes first pixel groups having two or more pixels and second pixel groups being different from the first pixel groups, wherein a portion of the pixels in the first pixel groups and a portion of the pixels in the second pixel groups share a floating diffusion element.

IPC Classes  ?

  • H01L 27/146 - Imager structures
  • H04N 25/13 - Arrangement of colour filter arrays [CFA]; Filter mosaics characterised by the spectral characteristics of the filter elements
  • H04N 25/75 - Circuitry for providing, modifying or processing image signals from the pixel array
  • H04N 25/76 - Addressed sensors, e.g. MOS or CMOS sensors
  • H04N 25/77 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components

22.

TRANSMISSION APPARATUS, RECEPTION APPARATUS, AND DATA PROCESSING METHOD

      
Application Number 18402211
Status Pending
Filing Date 2024-01-02
First Publication Date 2024-04-25
Owner
  • SONY CORPORATION (Japan)
  • SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Takahashi, Kazuyuki
  • Okada, Satoshi
  • Ohno, Takeshi

Abstract

This technology relates to a transmission apparatus, a reception apparatus, and a data processing method for easily implementing circuits on the receiving side. This technology relates to a transmission apparatus, a reception apparatus, and a data processing method for easily implementing circuits on the receiving side. There is provided a transmission apparatus including a processing section configured to process a stream with respect to each of multiple PLPs included in a broadcast signal, the stream being constituted by packets, the processing section further causing a header of each of the packets to include mapping information mapped to identification information identifying the PLP to which each of the packets belongs. This technology may be applied to data transmission methods such as the IP transmission method or the MPEG2-TS method, for example.

IPC Classes  ?

  • H04N 21/434 - Disassembling of a multiplex stream, e.g. demultiplexing audio and video streams or extraction of additional data from a video stream; Remultiplexing of multiplex streams; Extraction or processing of SI; Disassembling of packetised elementary stream
  • H04N 21/236 - Assembling of a multiplex stream, e.g. transport stream, by combining a video stream with other content or additional data, e.g. inserting a URL [Uniform Resource Locator ] into a video stream, multiplexing software data into a video stream; Remultiplexing of multiplex streams; Insertion of stuffing bits into the multiplex stream, e.g. to obtain a constant bit-rate; Assembling of a packetised elementary stream
  • H04N 21/2381 - Adapting the multiplex stream to a specific network, e.g. an IP [Internet Protocol] network
  • H04N 21/438 - Interfacing the downstream path of the transmission network originating from a server, e.g. retrieving MPEG packets from an IP network

23.

PHOTODETECTOR

      
Application Number JP2023036586
Publication Number 2024/085005
Status In Force
Filing Date 2023-10-06
Publication Date 2024-04-25
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Yokogawa, Sozo

Abstract

A photodetector includes a wavelength separation structure including materials having different refractive indices. The materials are planarly and discretely provided for each of first pixels and second pixels on a first surface of a semiconductor substrate. The wavelength separation structure separates incident light on the first pixel into a first wavelength component and a wavelength component other than the first wavelength component and selectively guides the first wavelength component to the first pixel and separates incident light on the second pixel into a second wavelength component and a wavelength component other than the second wavelength component and selectively guides the second wavelength component to the second pixel.

IPC Classes  ?

24.

SIGNAL PROCESSING DEVICE, SIGNAL PROCESSING METHOD, AND STORAGE MEDIUM

      
Application Number JP2023036758
Publication Number 2024/085023
Status In Force
Filing Date 2023-10-10
Publication Date 2024-04-25
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Oniki, Kazumasa

Abstract

An image processing device includes processing circuitry configured to receive information indicating a single image, calculate respective densities for each person detected in the single image, select a target person from one or more people detected in the single image, determine whether another person of the one or more people in the single image overlaps the target person, and in response to a determination that the another person overlaps the target person, calculate a density for the target person based on the overlap, and output crowd density information for at least part of the single image, wherein the crowd density information for the at least part of the single image corresponds to a density of one or more people throughout the at least part of the single image and is based on a combination of the calculated density of the one or more people in the at least part of the single image.

IPC Classes  ?

  • G06V 20/52 - Surveillance or monitoring of activities, e.g. for recognising suspicious objects

25.

INFORMATION PROCESSING APPARATUS, PROGRAM, AND INFORMATION PROCESSING METHOD

      
Application Number JP2023035683
Publication Number 2024/084925
Status In Force
Filing Date 2023-09-29
Publication Date 2024-04-25
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Kurokawa, Tsubasa

Abstract

An information processing apparatus includes, a matching circuit that receives a first image indicating a field of view in a prescribed space based on three-dimensional point cloud data that represents the prescribed space by a point cloud and a second image captured in the prescribed space, and matches the second image and the first image, and a position information providing circuit that generates second position information based on first position information about an origin of the field of view indicated by the first image matched with the second image and provides the second position information to update the three-dimensional point cloud data.

IPC Classes  ?

  • G06T 7/73 - Determining position or orientation of objects or cameras using feature-based methods
  • G06T 7/80 - Analysis of captured images to determine intrinsic or extrinsic camera parameters, i.e. camera calibration
  • G06T 17/20 - Wire-frame description, e.g. polygonalisation or tessellation

26.

SOLID-STATE IMAGING DEVICE AND ELECTRONIC DEVICE

      
Application Number JP2023034018
Publication Number 2024/084880
Status In Force
Filing Date 2023-09-20
Publication Date 2024-04-25
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Nonaka Shin

Abstract

The present invention suppresses mixing of light. The present invention provides a solid-state imaging device that comprises a pixel array part in which a plurality of pixels including a pixel that is provided with a plurality of photoelectric conversion elements with respect to one on-chip lens are two-dimensionally arranged, wherein: the pixels each comprise a control member; the control member is composed of a first member which has a first refractive index and a second member which has a second refractive index that is lower than the first refractive index; the on-chip lens, the first member, the second member and the photoelectric conversion elements are sequentially stacked in this order; the second member has a first surface that faces the first member, and a second surface that faces the photoelectric conversion elements; the first surface comprises a projected part which protrudes toward the on-chip lens, or a recessed part which is recessed toward the photoelectric conversion elements; and in cases where the first surface comprises the recessed part, the surface is provided with a plurality of relief parts.

IPC Classes  ?

27.

PHOTODETECTION DEVICE, DISTANCE MEASUREMENT DEVICE, AND METHOD FOR CONTROLLING PHOTODETECTION DEVICE

      
Application Number JP2023030081
Publication Number 2024/084792
Status In Force
Filing Date 2023-08-22
Publication Date 2024-04-25
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Luo, Dan
  • Umakoshi, Keisuke
  • Oba, Kenji
  • Maekawa, Yuya

Abstract

The present invention reduces the circuit area in a photodetection device in which a plurality of pixels are arranged. A first detection circuit detects the incidence of photons on the basis of the voltage of one of the anode and cathode of a first photoelectric conversion element during a period that is not a predetermined detection halt period. A second detection circuit detects the incidence of photons on the basis of the voltage of one of the anode and cathode of a second photoelectric conversion element during a period that is not the detection halt period. A shared circuit controls the voltage of a gating pulse indicating the detection halt period.

IPC Classes  ?

  • H04N 25/773 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising A/D, V/T, V/F, I/T or I/F converters comprising photon counting circuits, e.g. single photon detection [SPD] or single photon avalanche diodes [SPAD]
  • G01S 17/10 - Systems determining position data of a target for measuring distance only using transmission of interrupted, pulse-modulated waves
  • G01S 17/894 - 3D imaging with simultaneous measurement of time-of-flight at a 2D array of receiver pixels, e.g. time-of-flight cameras or flash lidar
  • H01L 31/107 - Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier working in avalanche mode, e.g. avalanche photodiode
  • H04N 25/705 - Pixels for depth measurement, e.g. RGBZ

28.

SEMICONDUCTOR DEVICE

      
Application Number 18263931
Status Pending
Filing Date 2022-01-05
First Publication Date 2024-04-18
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Murashima, Akihiko

Abstract

The present disclosure relates to a semiconductor device capable of reducing design load. The present disclosure relates to a semiconductor device capable of reducing design load. Provided is a semiconductor device including: a first substrate; and a second substrate bonded to the first substrate with a bonding portion where a bump is bonded, in which the bump pairs up with a predetermined function to constitute a unit. The present disclosure is applicable to, for example, a photodetection device such as a solid-state imaging device.

IPC Classes  ?

  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 23/528 - Layout of the interconnection structure
  • H01L 27/146 - Imager structures

29.

IMAGING DEVICE

      
Application Number 17768405
Status Pending
Filing Date 2020-07-15
First Publication Date 2024-04-18
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Oshiyama, Itaru
  • Ogata, Ryo

Abstract

There is provided an imaging device including: a semiconductor substrate including a photoelectric conversion section provided for each of pixels that are two-dimensionally arranged, in which the photoelectric conversion section performs photoelectric conversion on incident light; and an uneven structure provided on a light-receiving-side principal surface of the semiconductor substrate, in which the uneven structure includes a plurality of pillars arranged at a period shorter than a wavelength of light belonging to a visible light band.

IPC Classes  ?

30.

WIRING AND ELECTRONIC DEVICE

      
Application Number JP2023029673
Publication Number 2024/079979
Status In Force
Filing Date 2023-08-17
Publication Date 2024-04-18
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Ochiai, Yasuhiro

Abstract

A wiring according to the present disclosure comprises a plurality of divided wirings through which AC current flows. The number of divided wirings is 4 or greater. If Sp denotes the inter-wiring space between two adjacent divided wirings, and Wd denotes the individual wiring width of each of the divided wirings, Sp/Wd is 0.2-0.55 when reverse-phase current is supplied as the AC current through the divided wirings, and Sp/Wd is 0.35-0.95 when in-phase current is supplied as the AC current through the divided wirings.

IPC Classes  ?

  • H01P 3/18 - Waveguides; Transmission lines of the waveguide type built-up from several layers to increase operating surface, i.e. alternately conductive and dielectric layers
  • H01L 21/3205 - Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layers; After-treatment of these layers
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 27/04 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body

31.

DISPLAY DEVICE WITH DETECTION FUNCTION

      
Application Number JP2023029854
Publication Number 2024/079989
Status In Force
Filing Date 2023-08-18
Publication Date 2024-04-18
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Tsukuda, Yasunori

Abstract

A display device with a detection function according to the present disclosure comprises: a display unit having a transmissive region through which light is transmitted; and a sensor unit having a light-emitting unit and a light-receiving unit disposed on the reverse surface side of the display unit, the sensor unit measuring the flight time for light emitted by the light-emitting unit to be transmitted through the transmissive region, reflected by the object within a specific distance range from the display unit, transmitted through the transmissive region, and received by the light-receiving unit, and thereby measuring the distance to the object within a specific distance range.

IPC Classes  ?

  • G01S 7/481 - Constructional features, e.g. arrangements of optical elements
  • G06F 3/041 - Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
  • G06F 3/042 - Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by opto-electronic means

32.

DISPLAY DEVICE, ELECTRONIC APPARATUS, AND METHOD FOR MANUFACTURING DISPLAY DEVICE

      
Application Number JP2023032313
Publication Number 2024/080039
Status In Force
Filing Date 2023-09-05
Publication Date 2024-04-18
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Fujimaki, Hiroshi

Abstract

Provided are a display device, an electronic apparatus, and a method for manufacturing a display device, which can prevent moisture or the like from penetrating into an effective pixel region. The display device includes a driving substrate that has an effective pixel region and a peripheral region between the effective pixel region and an outer edge. The effective pixel region includes a plurality of pixels. Each pixel includes: a first electrode; a second electrode that is disposed facing the first electrode; and a first organic layer that is provided between the first electrode and the second electrode and that includes a light-emitting layer. The peripheral region includes a second organic layer, which is separated from the first organic layer included in each of the pixels.

IPC Classes  ?

  • H10K 50/84 - Passivation; Containers; Encapsulations
  • H10K 59/122 - Pixel-defining structures or layers, e.g. banks
  • H10K 59/35 - Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
  • H10K 59/38 - Devices specially adapted for multicolour light emission comprising colour filters or colour changing media [CCM]
  • H10K 71/00 - Manufacture or treatment specially adapted for the organic devices covered by this subclass

33.

PHASE MODULATION DEVICE

      
Application Number JP2023033836
Publication Number 2024/080083
Status In Force
Filing Date 2023-09-19
Publication Date 2024-04-18
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Okazaki, Tsuyoshi

Abstract

A phase modulation device according to one embodiment of the present disclosure comprises: a phase modulation unit that has a plurality of pixels and that is capable of modulating the phase of light from a light source; and a generation unit that is capable of generating, on the basis of a phase pattern, first data pertaining to the phase modulation amount for each of the pixels in a first phase modulation range among the ranges of the phase modulation amount and second data pertaining to the phase modulation amount for each of the pixels in a second phase modulation range. The phase modulation unit is capable of modulating the phase of the light from the light source on the basis of the first data and modulating the phase of the light from the light source on the basis of the second data.

IPC Classes  ?

  • G09G 3/36 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix by control of light from an independent source using liquid crystals
  • G02F 1/13 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
  • G02F 1/133 - Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
  • G09G 3/20 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
  • G09G 3/34 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix by control of light from an independent source

34.

SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND OPTICAL DETECTION DEVICE

      
Application Number JP2023036116
Publication Number 2024/080192
Status In Force
Filing Date 2023-10-03
Publication Date 2024-04-18
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Yamamoto Ryusei
  • Hida Shota
  • Tazaki Masayuki

Abstract

Provided are: a semiconductor device configured so that the degradation of the characteristics thereof is suppressed; a method for manufacturing a semiconductor device; and an optical detection device. The semiconductor device comprises: a first semiconductor layer having a first face and a second face located on the opposite side of the first face; a first interlayer insulation film provided on the first face side of the first semiconductor layer; a first opening provided in the first interlayer insulation film that opens on the surface of the first interlayer insulation film; an electrode provided in the first opening; and an insulation film that covers at least the lateral surfaces of the first opening and that is provided at a distance from the lateral surfaces of the electrode.

IPC Classes  ?

  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 21/3205 - Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layers; After-treatment of these layers
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
  • H01L 27/146 - Imager structures
  • H04N 25/70 - SSIS architectures; Circuits associated therewith

35.

PHOTODETECTION ELEMENT AND ELECTRONIC APPARATUS

      
Application Number JP2023036443
Publication Number 2024/080226
Status In Force
Filing Date 2023-10-05
Publication Date 2024-04-18
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Mizoguchi, Kyoji

Abstract

The present invention reduces the impact of interference on a gradation signal or an event signal. This photodetection element has a pixel array unit, a row control unit and an overlap prediction row detection unit. The pixel array unit has a plurality of pixels which are arranged in a two-dimensional matrix and equipped with: an event signal generation unit for detecting a unidirectional change in the brightness of incident light as an event, and generating an event signal, which is a signal based on the detected event; and a gradation signal generation unit for generating a gradation signal, which is a signal which corresponds to the brightness of the incident light. The row control unit performs: a brightness signal generation control for sequentially performing, at a timing which is offset by row, a control for generating a gradation signal by jointly outputting a control signal to the gradation signal generation units of the pixels arranged in a row of the pixel array unit, and a control for reading out the gradation signals; and a control for detecting an event by outputting a control signal to an event signal generation unit and a control for reading out the event signal. The overlap prediction row detection unit detects an overlap prediction row, which is a row where an overlap of the intervals for gradation signal generation and event detection is predicted to occur.

IPC Classes  ?

36.

WIRING MODULE AND IMAGING APPARATUS

      
Application Number 18540173
Status Pending
Filing Date 2023-12-14
First Publication Date 2024-04-18
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Yamashita, Yutaro

Abstract

A wiring module according to an embodiment of the present technology includes: a wiring board and a heat dissipation member. The wiring board includes a body portion and one or more heat dissipation vias, the body portion including a front surface layer to which a device package is connected and a rear surface layer opposite to the front surface layer, the one or more heat dissipation vias penetrating the body portion from the front surface layer to the rear surface layer. The heat dissipation member is connected to the rear surface layer so as to thermally bond with the one or more heat dissipation vias.

IPC Classes  ?

37.

INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING SYSTEM, INFORMATION PROCESSING METHOD, AND RECORDING MEDIUM

      
Application Number 18547161
Status Pending
Filing Date 2022-02-16
First Publication Date 2024-04-18
Owner Sony Semiconductor Solutions Corporation (Japan)
Inventor
  • Ishikawa, Hirotaka
  • Yonezawa, Kota

Abstract

An edge device (20) that is an example of an information processing device of an embodiment according to the present disclosure includes a transmitting section that transmits, to a server device (10) that generates a neural network, information related to a processing capability for processing the neural network supplied from the server device (10), wherein the information related to the processing capability includes at least one of capacity information of the neural network, filter size information of a favorite convolutional neural network, hardware architecture type information, chip information, and device model number information.

IPC Classes  ?

38.

SEMICONDUCTOR DEVICE, ELECTRONIC DEVICE, AND METHOD OF CONTROLLING SEMICONDUCTOR DEVICE

      
Application Number 18279148
Status Pending
Filing Date 2022-02-16
First Publication Date 2024-04-18
Owner Sony Semiconductor Solutions Corporation (Japan)
Inventor
  • Okamoto, Koichi
  • Mogi, Hideaki
  • Masuda, Takashi
  • Saeki, Shinichirou
  • Tabata, Mitsushi

Abstract

A semiconductor device (10) according to one aspect of the present disclosure includes: a driving section (40) that drives an object to be driven; an abnormality detecting circuit (30), which is one example of an instruction circuit that outputs an instruction signal to the driving section (40); and a light amount detecting section (20) that detects an amount of incident light and invalidates the instruction signal output from the abnormality detecting circuit (30) in accordance with the amount of incident light.

IPC Classes  ?

39.

LIGHT RECEIVING DEVICE, DISTANCE MEASURING DEVICE, AND SIGNAL PROCESSING METHOD IN LIGHT RECEIVING DEVICE

      
Application Number 18264465
Status Pending
Filing Date 2022-01-26
First Publication Date 2024-04-18
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Sakaguchi, Hiroaki
  • Hasegawa, Koichi

Abstract

A light receiving device (20) according to one aspect of the present disclosure includes: a light receiving section (22) including a plurality of photon-counting light receiving elements that receives reflected light from a distance measurement target (40) based on irradiation pulsed light from a light source section (10); a selecting section (23) that selects individual detection values of the plurality of light receiving elements at a predetermined time; an addition section (24) that generates 2N−1 binary values (N is a positive integer) from the individual detection values of the plurality of light receiving elements at the predetermined time selected by the selecting section (23) and that calculates an N-bit pixel value by adding up all the 2N−1 binary values; and a computing section (26) that performs computation related to distance measurement using the N-bit pixel value calculated by the addition section (24).

IPC Classes  ?

  • G01S 17/10 - Systems determining position data of a target for measuring distance only using transmission of interrupted, pulse-modulated waves
  • G01S 7/4863 - Detector arrays, e.g. charge-transfer gates
  • G01S 7/4865 - Time delay measurement, e.g. time-of-flight measurement, time of arrival measurement or determining the exact position of a peak

40.

Solid-State Imaging Device and Solid-State Imaging Apparatus

      
Application Number 18394741
Status Pending
Filing Date 2023-12-22
First Publication Date 2024-04-18
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Fukui, Hironobu

Abstract

A solid-state imaging device including: a semiconductor substrate having a first surface and a second surface opposed to each other, and including a photoelectric converter provided for each of pixel regions; an impurity diffusion region provided, for each of the pixel regions, in proximity to the first surface of the semiconductor substrate; and a contact electrode embedded in the semiconductor substrate from the first surface, and provided over and in contact with the impurity diffusion regions each provided for each of the pixel regions adjacent to each other.

IPC Classes  ?

41.

SEMICONDUCTOR DEVICE AND ELECTRONIC APPARATUS

      
Application Number 17769556
Status Pending
Filing Date 2020-07-21
First Publication Date 2024-04-18
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Kudou, Tomoaki
  • Otake, Yusuke

Abstract

Provided is a semiconductor device capable of improving quantum efficiency and time resolution. In the semiconductor device, each of a plurality of pixels includes an APD element formed in a semiconductor layer, and a first metal wiring provided on a first surface of the semiconductor layer. The APD element includes: a multiplication portion which includes a first electrode region of a first conductivity type provided on the first surface side of the semiconductor layer and a second electrode region of a second conductivity type provided at a position shallower than the first electrode region to form a pn junction with the first electrode region, and in which an avalanche multiplication region is formed at an interface of the pn junction; and a first contact region of the second conductivity type which is provided in contact with the second electrode region between the first surface of the semiconductor layer and the second electrode region, and of which the contour is located inside a contour of the second electrode region in a plan view. The first metal wiring is electrically connected to the first contact region, and a contour thereof is located between the contour of the second electrode region and the contour of the first contact region in a plan view.

IPC Classes  ?

  • H01L 27/146 - Imager structures
  • H04N 25/773 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising A/D, V/T, V/F, I/T or I/F converters comprising photon counting circuits, e.g. single photon detection [SPD] or single photon avalanche diodes [SPAD]

42.

LIGHT DETECTION DEVICE AND ELECTRONIC APPARATUS

      
Application Number JP2023030034
Publication Number 2024/079990
Status In Force
Filing Date 2023-08-21
Publication Date 2024-04-18
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Yamazaki Tomohiro

Abstract

Provided is a light detection device that makes it possible to suppress the occurrence of defective pixels. Specifically, the light detection device comprises: a semiconductor substrate on which a plurality of photoelectric conversion units are formed; and a plurality of optical filters arranged on the light incidence surface-side of the semiconductor substrate. In addition, each of the optical filters has a metal structure comprising the same type of metal material. Furthermore, slits that spatially divide the metal structures are provided between the metal structures.

IPC Classes  ?

43.

SERVER DEVICE, TERMINAL DEVICE, INFORMATION PROCESSING METHOD, AND INFORMATION PROCESSING SYSTEM

      
Application Number JP2023036472
Publication Number 2024/080231
Status In Force
Filing Date 2023-10-06
Publication Date 2024-04-18
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Shimomura, Munehiro
  • Ishikawa, Hirotaka

Abstract

An information processing system configured to transmit a first command to a first electronic device requesting processing capability information of the first electronic device; receive first parameters from the first electronic device in response to the first command; divide a deep neural network (DNN) into at least a first DNN and a second DNN based on the first parameters received from the first electronic device; and transmit the first divided DNN to the first electronic device.

IPC Classes  ?

  • G06N 3/098 - Distributed learning, e.g. federated learning
  • G06N 3/0985 - Hyperparameter optimisation; Meta-learning; Learning-to-learn
  • G06N 3/082 - Learning methods modifying the architecture, e.g. adding, deleting or silencing nodes or connections
  • G06N 3/045 - Combinations of networks

44.

DISPLAY DEVICE

      
Application Number 18251546
Status Pending
Filing Date 2021-10-29
First Publication Date 2024-04-11
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Yagi, Keiichi
  • Miura, Kiwamu
  • Hamachi, Chugen

Abstract

A display device includes a first substrate (41), a second substrate (42), a plurality of light emitting elements (10) provided in a display region, and a sealing part (50) that is provided in a peripheral region surrounding the display region and seals between the first substrate (41) and the second substrate (42), wherein the sealing part (50) includes main sealing parts (51) and a sub sealing part (52) positioned between the main sealing parts, an alignment mark (55) is provided between the sub sealing part (52) and the first substrate (41), each of the main sealing part (51) has a stacked structure of a light shielding member layer (56, 57) and a sealing member layer (53) from the first substrate side, and the sub sealing part (52) has a stacked structure (53) of a base material layer (54) formed of a non-light shielding member and the sealing member layer from the first substrate side.

IPC Classes  ?

  • H10K 59/38 - Devices specially adapted for multicolour light emission comprising colour filters or colour changing media [CCM]
  • H10K 59/126 - Shielding, e.g. light-blocking means over the TFTs
  • H10K 59/127 - Active-matrix OLED [AMOLED] displays comprising two substrates, e.g. display comprising OLED array and TFT driving circuitry on different substrates
  • H10K 59/80 - Constructional details

45.

DISPLAY DEVICE AND ELECTRONIC DEVICE

      
Application Number 18260370
Status Pending
Filing Date 2022-02-10
First Publication Date 2024-04-11
Owner Sony Semiconductor Solutions Corporation (Japan)
Inventor
  • Sudo, Shoji
  • Sawabe, Tomoaki

Abstract

Display devices that suppress complications due to uneven shape of a surface on which a semi-transmissive reflective layer is formed are disclosed. In one example, a display device includes first sub-pixels, second sub-pixels, and third sub-pixels. The first sub-pixel includes a first light emitting element that emits first light and third light, the second sub-pixel includes a second light emitting element that emits second light, and the third sub-pixel includes a third light emitting element that emits first light and third light. The light emitting elements respectively include a first electrode, an organic layer including a light emitting layer, a second electrode, and a semi-transmissive reflective layer, and a resonator structure is configured by the first electrode and the semi-transmissive reflective layer. The heights of the semi-transmissive reflective layers in the first light emitting element and the third light emitting element are the same.

IPC Classes  ?

  • H10K 59/80 - Constructional details
  • H10K 59/38 - Devices specially adapted for multicolour light emission comprising colour filters or colour changing media [CCM]

46.

SOLID-STATE IMAGING DEVICE AND IMAGING APPARATUS

      
Application Number 18263729
Status Pending
Filing Date 2022-01-28
First Publication Date 2024-04-11
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Hanzawa, Katsuhiko
  • Miyake, Shinichi
  • Tomida, Kazuyuki

Abstract

A solid-state imaging device (200) includes a photoelectric conversion device (211), a current-voltage conversion circuit (310), and an output circuit. The photoelectric conversion device (211) performs photoelectric conversion of incident light. The current-voltage conversion circuit (310) includes a first transistor (311) that converts an amount of electric charge generated by photoelectric conversion into a voltage signal. The output circuit includes a second transistor having an S value smaller than an S value of the first transistor (311) and generates an output signal based on the voltage signal.

IPC Classes  ?

47.

IMAGING APPARATUS AND IMAGING METHOD

      
Application Number 18263774
Status Pending
Filing Date 2022-01-25
First Publication Date 2024-04-11
Owner Sony Semiconductor Solutions Corporation (Japan)
Inventor Mahara, Kumiko

Abstract

An imaging apparatus according to an embodiment includes a pixel array unit (101) including a plurality of pixels arranged in a matrix array, each of the pixels generating a pixel signal corresponding to light received by exposure, the pixel array unit acquiring image data based on each of the pixel signals respectively generated by the plurality of pixels, a compression unit (1020) configured to compress a data amount of the image data to generate compressed image data, a signature generation unit (1021) configured to generate signature data based on the compressed image data; and an output unit (104,131,132) configured to output the image data and authenticity proof data obtained by adding the signature data to the compressed image data.

IPC Classes  ?

  • H04N 19/467 - Embedding additional information in the video signal during the compression process characterised by the embedded information being invisible, e.g. watermarking
  • G06F 21/64 - Protecting data integrity, e.g. using checksums, certificates or signatures
  • H04N 25/11 - Arrangement of colour filter arrays [CFA]; Filter mosaics
  • H04N 25/79 - Arrangements of circuitry being divided between different or multiple substrates, chips or circuit boards, e.g. stacked image sensors

48.

SOLID-STATE IMAGING DEVICE AND ELECTRONIC APPARATUS

      
Application Number 18544833
Status Pending
Filing Date 2023-12-19
First Publication Date 2024-04-11
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Yamashita, Hirofumi
  • Shimada, Shohei
  • Otake, Yusuke
  • Tanaka, Yusuke
  • Wakano, Toshifumi

Abstract

To provide a solid-state imaging device and an electronic apparatus capable of achieving both of a high dynamic range operation and an auto focus operation in a pixel configuration in which a plurality of unit pixels includes two or more subpixels. There is provided a solid-state imaging device including: a first pixel separation region that separates a plurality of unit pixels including two or more subpixels; a second pixel separation region that separates each of the plurality of unit pixels separated by the first pixel separation region; and an overflow region that causes signal charges accumulated in the subpixels to overflow to at least one of adjacent subpixels, in which the overflow region is formed between a first subpixel and a second subpixel.

IPC Classes  ?

  • H04N 25/704 - Pixels specially adapted for focusing, e.g. phase difference pixel sets
  • H01L 27/146 - Imager structures
  • H04N 25/711 - Time delay and integration [TDI] registers; TDI shift registers
  • H04N 25/772 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising A/D, V/T, V/F, I/T or I/F converters

49.

PHOTODETECTION DEVICE AND ELECTRONIC APPARATUS

      
Application Number 18546252
Status Pending
Filing Date 2022-02-21
First Publication Date 2024-04-11
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Moriya, Yusuke
  • Yamamoto, Atsushi
  • Yukawa, Tomiyuki
  • Nishimura, Kotaro
  • Ikehara, Shigehiro
  • Otani, Shogo
  • Kato, Hiroshi

Abstract

The present disclosure relates to a photodetection device and an electronic apparatus that allow for reducing surface reflection from an on-chip microlens and suppressing deterioration of image quality. Provided is a photodetection device including: a plurality of pixels that have photoelectric conversion units; on-chip microlenses that are formed in such a way as to correspond to the individual pixels; and an antireflection film that is formed on a surface of the on-chip microlens, in which the antireflection film is constituted by a stacking of: a first inorganic film that is formed by a metal oxide film; and a second inorganic film that is formed on a surface of the first inorganic film and has a lower refractive index than the first inorganic film. The present disclosure can be applied to, for example, a CMOS solid-state imaging device.

IPC Classes  ?

50.

LIQUID CRYSTAL DISPLAY ELEMENT, DISPLAY DEVICE, ELECTRONIC DEVICE, DRIVE SUBSTRATE, AND METHOD FOR MANUFACTURING DRIVE SUBSTRATE

      
Application Number 18251581
Status Pending
Filing Date 2021-11-02
First Publication Date 2024-04-11
Owner
  • SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
  • SONY GROUP CORPORATION (Japan)
Inventor
  • Sakairi, Takashi
  • Honda, Tomoaki

Abstract

Provided is a liquid crystal display element capable of reducing the decrease in light utilization efficiency caused by the increase in definition. Provided is a liquid crystal display element capable of reducing the decrease in light utilization efficiency caused by the increase in definition. A liquid crystal display element includes: a drive substrate having pixel electrodes having light-reflective properties and arranged in a matrix; a counter substrate arranged opposite to the drive substrate; and a liquid crystal material layer sandwiched between the drive substrate and the counter substrate, in which the pixel electrodes are arranged on a display surface side of the drive substrate in a state of being separated from each other with a slit portion interposed therebetween, an entire surface including surfaces on the pixel electrodes is covered with a first dielectric film formed on the pixel electrodes and a second dielectric film formed in the slit portion, and the second dielectric film has a hollow portion extending along the slit portion.

IPC Classes  ?

  • G02F 1/1335 - Structural association of cells with optical devices, e.g. polarisers or reflectors

51.

COUNTING MODE DECISION CIRCUITRY AND COUNTING MODE DECISION METHOD

      
Application Number EP2023076215
Publication Number 2024/074322
Status In Force
Filing Date 2023-09-22
Publication Date 2024-04-11
Owner
  • SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
  • SONY DEPTHSENSING SOLUTIONS SA/NV (Belgium)
Inventor Ding, Qing

Abstract

The present disclosure generally pertains to counting mode decision circuitry configured to: determine, for at least one imaging element, a photon number in a first photon counting mode of at least two photon counting modes which, in a standard operation mode, are applied after each other; and skip a second photon counting mode of the at least two photon counting modes, if the photon number in the first photon counting mode exceeds a predetermined threshold, thereby deviating from the standard operation mode.

IPC Classes  ?

  • H04N 25/589 - Control of the dynamic range involving two or more exposures acquired sequentially, e.g. using the combination of odd and even image fields with different integration times, e.g. short and long exposures
  • H04N 25/773 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising A/D, V/T, V/F, I/T or I/F converters comprising photon counting circuits, e.g. single photon detection [SPD] or single photon avalanche diodes [SPAD]

52.

LIGHT DETECTION DEVICE AND ELECTRONIC EQUIPMENT

      
Application Number JP2022037482
Publication Number 2024/075253
Status In Force
Filing Date 2022-10-06
Publication Date 2024-04-11
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Yamashita, Kazuyoshi

Abstract

A light detection device according to an embodiment of the present disclosure comprises: a first photoelectric conversion portion (12) that performs photoelectric conversion of light; a first light guide portion (30) that includes a first structure (31) of a size less than or equal to the wavelength of input light, and that the light that has passed through the first photoelectric conversion unit (12) enters; and a second photoelectric conversion portion (22) that performs photoelectric conversion of infrared light that enters the second photoelectric conversion portion (22) via the first light guide portion (30).

IPC Classes  ?

  • H01L 31/10 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by at least one potential-jump barrier or surface barrier, e.g. phototransistors

53.

CAMERA MODULE AND IMAGING DEVICE

      
Application Number JP2023029326
Publication Number 2024/075398
Status In Force
Filing Date 2023-08-10
Publication Date 2024-04-11
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Imayoshi, Kohei
  • Kunimitsu, Takayuki
  • Yukishige, Akihiro
  • Kasahara, Keijyu
  • Tsuruta, Takahiro

Abstract

The present invention reduces the device size of an imaging device that performs rotation correction. This camera module comprises a lens group, a translational actuator, a rotational actuator, and a mounting board. In this camera module, the translational actuator moves the lens group in parallel. The rotational actuator rotates the lens group. A part of a rigid flexible board deforms so as to follow the rotation of the lens group. Furthermore, the translational actuator is provided on one of both surfaces of the mounting board and the rigid flexible board is provided on the other one thereof.

IPC Classes  ?

  • G03B 5/00 - Adjustment of optical system relative to image or object surface other than for focusing of general interest for cameras, projectors or printers
  • G02B 7/02 - Mountings, adjusting means, or light-tight connections, for optical elements for lenses
  • G02B 7/04 - Mountings, adjusting means, or light-tight connections, for optical elements for lenses with mechanism for focusing or varying magnification
  • G03B 30/00 - Camera modules comprising integrated lens units and imaging units, specially adapted for being embedded in other devices, e.g. mobile phones or vehicles
  • H04N 23/50 - Constructional details
  • H04N 23/57 - Mechanical or electrical details of cameras or camera modules specially adapted for being embedded in other devices
  • H05K 1/02 - Printed circuits - Details

54.

SOLID-STATE IMAGING DEVICE

      
Application Number JP2023029670
Publication Number 2024/075405
Status In Force
Filing Date 2023-08-17
Publication Date 2024-04-11
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Tanaka, Daichi
  • Tomita, Chihiro

Abstract

This solid-state imaging device comprises: a first pixel that is arranged on a first surface side serving as a light incident side of a substrate, and that has a first photoelectric conversion element for converting light to a charge; a first transistor that is arranged, at a position corresponding to the first pixel, on a second surface side opposite the first surface of the substrate, that has a first gate electrode, and that has a pair of main electrodes, one of which is electrically connected to the first photoelectric conversion element; a floating diffusion that is arranged on the second surface side of the substrate and that is electrically connected to the other main electrode of the first transistor; and a low dielectric constant region that is arranged between the floating diffusion and the first gate electrode opposite the same, and that has a lower dielectric constant than that of a non-opposing region.

IPC Classes  ?

55.

PHOTODETECTION DEVICE

      
Application Number JP2023029830
Publication Number 2024/075409
Status In Force
Filing Date 2023-08-18
Publication Date 2024-04-11
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Ishii Hiroyasu
  • Moriyama Yusuke
  • Baba Tomohiro
  • Kaji Nobuaki
  • Wakayama Kazuyuki
  • Izuhara Kunihiko

Abstract

A device capable of improving characteristics of a light sensor by applying an appropriate bias voltage to the light sensor. A device according to one embodiment includes a first light source configured to emit a first light, a second light source configured to emit a second light having a first characteristic different from a second characteristic of the first light, a first light sensor configured to detect first reflected light that is the first light emitted from the first light source and reflected by an object, and a second light sensor configured to detect second reflected light that is the second light emitted from the second light source and reflected by a first member that is distinct from the object.

IPC Classes  ?

  • G01S 7/4863 - Detector arrays, e.g. charge-transfer gates
  • G01S 7/497 - Means for monitoring or calibrating
  • G01S 17/894 - 3D imaging with simultaneous measurement of time-of-flight at a 2D array of receiver pixels, e.g. time-of-flight cameras or flash lidar
  • G01S 7/481 - Constructional features, e.g. arrangements of optical elements

56.

SOLID-STATE IMAGING DEVICE, AND COMPARISON DEVICE

      
Application Number JP2023033578
Publication Number 2024/075492
Status In Force
Filing Date 2023-09-14
Publication Date 2024-04-11
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Azuhata Satoshi

Abstract

[Problem] To perform fast and high-performance signal comparison. [Solution] This solid-state imaging device comprises a comparison circuit, a first switch, a second switch, a third switch, a first capacitor, and a second capacitor. The comparison circuit is provided with a non-inverting input terminal and an inverting input terminal. The first switch is connected to the inverting input terminal. The second switch is connected to the inverting input terminal and is controlled at a different timing than the first switch. The third switch is connected between an output terminal of the comparison circuit and the inverting input terminal. One end of the first capacitor is connected to the inverting input terminal via the first switch, and a reference signal is applied to the other end of the first capacitor. One end of the second capacitor is connected to the inverting input terminal via the second switch, and the reference signal is applied to the other end of the second capacitor.

IPC Classes  ?

  • H04N 25/77 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
  • H04N 25/772 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising A/D, V/T, V/F, I/T or I/F converters

57.

IMAGING APPARATUS, ELECTRONIC DEVICE, AND SIGNAL PROCESSING METHOD

      
Application Number 18554043
Status Pending
Filing Date 2022-02-22
First Publication Date 2024-04-11
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Saito, Daisuke

Abstract

To provide an imaging apparatus which enables sophisticated calculations to be realized at lower power. An imaging apparatus according to an embodiment of the present disclosure includes: a first substrate group in which is arranged a light source cell array portion configured to generate a light signal; and a second substrate group in which is arranged a pixel array portion configured to photoelectrically convert the light signal and output a pixel signal representing a result of a sum-of-product computation. The first substrate group and the second substrate group are stacked so that at least a part of the light source cell array portion overlaps with the pixel array portion.

IPC Classes  ?

  • H04N 25/77 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
  • H04N 25/10 - Circuitry of solid-state image sensors [SSIS]; Control thereof for transforming different wavelengths into image signals

58.

IMAGE CAPTURING APPARATUS AND ELECTRONIC DEVICE

      
Application Number 18554342
Status Pending
Filing Date 2022-03-29
First Publication Date 2024-04-11
Owner Sony Semiconductor Solutions Corporation (Japan)
Inventor
  • Naganokawa, Haruhisa
  • Umeda, Kengo

Abstract

Image capturing that suppresses a drop in numerical aperture and achieves a smaller size is disclosed. In one example, an image capturing apparatus includes pixels each having a photoelectric conversion unit, a floating diffusion that outputs a voltage according to a charge obtained from photoelectric conversion by the photoelectric conversion unit, and a current amplification unit that amplifies a current according to the voltage of the floating diffusion. The region in which the photoelectric conversion units are disposed and the region in which the current amplification units are disposed transmit and receive the voltages of the floating diffusions through a corresponding signal transmission unit.

IPC Classes  ?

  • H04N 25/75 - Circuitry for providing, modifying or processing image signals from the pixel array
  • H04N 25/772 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising A/D, V/T, V/F, I/T or I/F converters
  • H04N 25/778 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself

59.

IMAGING DEVICE AND ELECTRONIC APPARATUS

      
Application Number 18554893
Status Pending
Filing Date 2022-03-29
First Publication Date 2024-04-11
Owner Sony Semiconductor Solutions Corporation (Japan)
Inventor Kurihara, Shinichiro

Abstract

[Problem] To provide an imaging device capable of suppressing color mixing and an electronic apparatus using the imaging device. [Problem] To provide an imaging device capable of suppressing color mixing and an electronic apparatus using the imaging device. [Solution] An imaging device of the present disclosure includes a photoelectric conversion layer disposed on a semiconductor substrate, a transparent electrode layer disposed on the photoelectric conversion layer, a first light-shielding portion that separates the photoelectric conversion layer into a plurality of pixels arranged in a first direction and a second direction that intersects the first direction, and is disposed along a boundary between the separated pixels, and a second light-shielding portion disposed along the boundary between the separated pixels inside the transparent electrode layer and disposed so that a portion of the boundary between adjacent pixels is interrupted.

IPC Classes  ?

60.

LIGHT EMITTING DEVICE AND DISPLAY DEVICE

      
Application Number 18264374
Status Pending
Filing Date 2022-02-16
First Publication Date 2024-04-11
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Nishinaka, Ippei
  • Naito, Hiroki
  • Tomoda, Katsuhiro

Abstract

For example, deterioration in image quality due to end-surface vignetting is suppressed. A light emitting device includes at least two light emitting elements provided on a substrate, and a transparent resin part provided so as to cover the light emitting elements, in which in a sectional view, when the size of the width of the light emitting element positioned at an end part is a (μm), a surface distance between the light emitting element and a surface of the transparent resin part is x (μm), an end surface distance between the light emitting element and an end surface of the transparent resin part closest to the light emitting element is y (μm), and the refractive index of the transparent resin part is λm, an expression (1) below or expressions (2) and (3) below are satisfied. For example, deterioration in image quality due to end-surface vignetting is suppressed. A light emitting device includes at least two light emitting elements provided on a substrate, and a transparent resin part provided so as to cover the light emitting elements, in which in a sectional view, when the size of the width of the light emitting element positioned at an end part is a (μm), a surface distance between the light emitting element and a surface of the transparent resin part is x (μm), an end surface distance between the light emitting element and an end surface of the transparent resin part closest to the light emitting element is y (μm), and the refractive index of the transparent resin part is λm, an expression (1) below or expressions (2) and (3) below are satisfied. y<(1.44λm−0.76)×x+(0.08λm−0.04)×a−0.02λm−0.47  (Expression 1) For example, deterioration in image quality due to end-surface vignetting is suppressed. A light emitting device includes at least two light emitting elements provided on a substrate, and a transparent resin part provided so as to cover the light emitting elements, in which in a sectional view, when the size of the width of the light emitting element positioned at an end part is a (μm), a surface distance between the light emitting element and a surface of the transparent resin part is x (μm), an end surface distance between the light emitting element and an end surface of the transparent resin part closest to the light emitting element is y (μm), and the refractive index of the transparent resin part is λm, an expression (1) below or expressions (2) and (3) below are satisfied. y<(1.44λm−0.76)×x+(0.08λm−0.04)×a−0.02λm−0.47  (Expression 1) y<(1.44λm−0.76)×x+(0.08λm−0.04)×a−0.02λm−0.47  (Expression 2) For example, deterioration in image quality due to end-surface vignetting is suppressed. A light emitting device includes at least two light emitting elements provided on a substrate, and a transparent resin part provided so as to cover the light emitting elements, in which in a sectional view, when the size of the width of the light emitting element positioned at an end part is a (μm), a surface distance between the light emitting element and a surface of the transparent resin part is x (μm), an end surface distance between the light emitting element and an end surface of the transparent resin part closest to the light emitting element is y (μm), and the refractive index of the transparent resin part is λm, an expression (1) below or expressions (2) and (3) below are satisfied. y<(1.44λm−0.76)×x+(0.08λm−0.04)×a−0.02λm−0.47  (Expression 1) y<(1.44λm−0.76)×x+(0.08λm−0.04)×a−0.02λm−0.47  (Expression 2) y<(1.44λm−0.76)×x+(0.15λm−0.08)×a−0.06λm−0.61  (Expression 3)

IPC Classes  ?

  • H01L 33/56 - Materials, e.g. epoxy or silicone resin
  • H01L 27/15 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier, specially adapted for light emission
  • H01L 33/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof

61.

LIGHT RECEIVING DEVICE, ELECTRONIC APPARATUS, AND LIGHT RECEIVING METHOD

      
Application Number 17767694
Status Pending
Filing Date 2020-10-05
First Publication Date 2024-04-11
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Suzuki, Nobuharu

Abstract

An increase in a load current in a processing circuit is reduced. A light receiving device includes an imaging unit that photoelectrically converts light received in a plurality of pixels to acquire an analog image signal, a conversion unit that converts the analog image signal acquired by the imaging unit into digital image data, and a data processing unit that executes data processing on the digital image data and reduces a load of the data processing in a period in which the conversion unit executes conversion as compared to a period in which the conversion unit does not execute conversion.

IPC Classes  ?

  • H04N 25/78 - Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters

62.

IMAGING DEVICE

      
Application Number JP2023029334
Publication Number 2024/075399
Status In Force
Filing Date 2023-08-10
Publication Date 2024-04-11
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Hattori, Yuki
  • Yamamoto, Masahiro

Abstract

The present invention reduces a noise component caused by a dark current while eliminating the need for mechanical light shielding. This imaging device comprises: a pixel provided with a lateral overflow integration capacitor that accumulates an electrical charge which has overflowed from a photoelectric conversion unit; and a signal processing unit that carries out correction processing of a pixel signal read out from the pixel, on the basis of a virtual light shielding signal read out from the lateral overflow integration capacitor in a state in which an electrical charge which has been photoelectrically converted in the photoelectric conversion unit is not accumulated in the lateral overflow integration capacitor. The imaging device may further comprise a flow control unit that discharges an electrical charge so that an electrical charge which has been photoelectrically converted in the photoelectric conversion unit is not accumulated in the lateral overflow integration capacitor.

IPC Classes  ?

  • H04N 25/771 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion
  • H04N 25/63 - Noise processing, e.g. detecting, correcting, reducing or removing noise applied to dark current

63.

SOLID-STATE IMAGING DEVICE

      
Application Number JP2023034200
Publication Number 2024/075526
Status In Force
Filing Date 2023-09-21
Publication Date 2024-04-11
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Shirai Yuki
  • Nakamura Ryosuke
  • Yamachi Ryosuke
  • Saka Naoki

Abstract

The present disclosure relates to a solid-state imaging device which can have improved pixel characteristics. Provided is a solid-state imaging device including a pixel array part comprising two-dimensionally arranged pixels each having a photoelectric conversion element and a pixel transistor, the pixel transistor including a transistor having a structure in which an impurity has been injected into a channel that is non-linear in a plan view, using a self-alignment mask according to the gate electrodes. The present disclosure is applicable to, for example, CMOS-type solid-state imaging devices.

IPC Classes  ?

  • H01L 27/146 - Imager structures
  • H01L 21/8234 - MIS technology
  • H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
  • H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate

64.

NONVOLATILE MEMORY DEVICE AND MANUFACTURING METHOD THEREOF

      
Application Number 18261655
Status Pending
Filing Date 2021-12-07
First Publication Date 2024-04-04
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Sumino, Jun
  • Aratani, Katsuhisa
  • Sone, Takeyuki
  • Mizuguchi, Tetsuya

Abstract

Provided is a nonvolatile memory device that makes it possible to achieve high performance. The nonvolatile memory device includes a first electrode, a memory material layer, a second electrode, and a first buffer layer. The memory material layer includes a first element and is provided on the first electrode. The second electrode is provided on the memory material layer. The first buffer layer is provided between the memory material layer and the second electrode. In the first buffer layer, a segregation of the first element is smaller than a segregation of the first element in the second electrode.

IPC Classes  ?

  • H10B 63/00 - Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
  • H10N 70/00 - Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching

65.

WIRELESS SYSTEM

      
Application Number 18264638
Status Pending
Filing Date 2022-01-13
First Publication Date 2024-04-04
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Uno, Masahiro

Abstract

A wireless system according to an embodiment of the present disclosure includes: one or a plurality of distributed units each including an antenna, a wireless circuit, and a camera, the wireless circuit transmitting and receiving a wireless signal via the antenna, the camera outputting an image signal; and a central unit that is line-coupled to each of the distributed units. The each of the distributed units transmits the wireless signal from the wireless circuit and image information based on the image signal outputted from the camera to the central unit using one line. The central unit includes a radio resource control circuit, a baseband circuit that performs signal processing on the wireless signal from the each of the distributed units on a basis of control performed by the radio resource control circuit, and a processing circuit that performs a process based on the image information from the each of the distributed units.

IPC Classes  ?

  • H04B 10/2575 - Radio-over-fibre, e.g. radio frequency signal modulated onto an optical carrier
  • G06V 20/50 - Context or environment of the image
  • G06V 40/20 - Movements or behaviour, e.g. gesture recognition
  • H04W 16/28 - Cell structures using beam steering
  • H04W 28/06 - Optimising, e.g. header compression, information sizing

66.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

      
Application Number 18264725
Status Pending
Filing Date 2022-01-13
First Publication Date 2024-04-04
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Makino, Hirofumi

Abstract

A semiconductor device according to the present technology includes a semiconductor chip, and a wiring board portion having the semiconductor chip mounted thereon and having an external connection terminal for establishing electrical connection to the outside, the external connection terminal being formed on its back surface which is a surface opposite to its front surface which is a surface on which the semiconductor chip is mounted, in which the semiconductor chip is connected to a terminal formed on the front surface of the wiring board portion through a bonding wire to be wire-bonded to the wiring board portion, and a heat dissipation member is disposed between the bonding wire and the wiring board portion.

IPC Classes  ?

  • H01L 23/427 - Cooling by change of state, e.g. use of heat pipes
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 23/053 - Containers; Seals characterised by the shape the container being a hollow construction and having an insulating base as a mounting for the semiconductor body
  • H01L 23/29 - Encapsulation, e.g. encapsulating layers, coatings characterised by the material
  • H01L 23/373 - Cooling facilitated by selection of materials for the device
  • H01L 27/146 - Imager structures

67.

DISPLAY DEVICE AND ELECTRONIC APPARATUS

      
Application Number JP2023029559
Publication Number 2024/070292
Status In Force
Filing Date 2023-08-16
Publication Date 2024-04-04
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Sato, Akihito

Abstract

A display device according to one embodiment of the present disclosure comprises: a display region in which a plurality of effective pixels are arranged in a matrix pattern; a non-display region including a plurality of dummy pixels provided in the vicinity of the display region; and a heat generating structure that absorbs incident light to generate heat, and is provided in the non-display region so as to surround the display region.

IPC Classes  ?

  • G02F 1/13 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells

68.

LENS OPTICAL SYSTEM AND IMAGING DEVICE

      
Application Number JP2023032953
Publication Number 2024/070611
Status In Force
Filing Date 2023-09-11
Publication Date 2024-04-04
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Ogino Shinpei
  • Murakami Daichi
  • Hanzawa Fumihiko
  • Takeuchi Haruki
  • Nakamura Masashi
  • Kimura Katsuji

Abstract

The present technology pertains to a lens optical system and an imaging device which make it possible to improve optical performance in a wide-angle lens optical system having a metasurface. The lens optical system comprises, in order from the light incident side, a metalens having positive refractive power and an optical lens having positive refractive power. The metalens has disposed thereon a metasurface formed from a plurality of nanostructures. An aperture diaphragm is disposed on the incident side of the metasurface. At least one optical surface of a second lens is aspherical. The present technology can be applicable to, for example, a wide-angle lens optical system or the like that condenses light from a subject to a solid-state imaging element.

IPC Classes  ?

  • G02B 13/00 - Optical objectives specially designed for the purposes specified below
  • G02B 5/18 - Diffracting gratings
  • G02B 13/18 - Optical objectives specially designed for the purposes specified below with lenses having one or more non-spherical faces, e.g. for reducing geometrical aberration

69.

SOLID-STATE IMAGING DEVICE, ELECTRONIC DEVICE, AND PROGRAM

      
Application Number JP2023033250
Publication Number 2024/070673
Status In Force
Filing Date 2023-09-12
Publication Date 2024-04-04
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Kazama Ryohei
  • Wakayama Kazuyuki
  • Kusakari Takashi

Abstract

[Problem] To improve the authentication accuracy. [Solution] A solid-state imaging device comprises a light source, a first light reception region, and a second light reception region. The light source is provided on the opposite side of a display from the display surface of the display, the light source emitting light in the IR region via the display. The first light reception region is provided on the opposite side of the display from the display surface, and is provided with pixels for receiving light in the visible light region and pixels for receiving at least light in the IR region emitted from the light source. The second light reception region is provided on the opposite side of the display from the display surface, and is provided with pixels for receiving at least light in the IR region emitted from the light source.

IPC Classes  ?

  • G01S 17/86 - Combinations of lidar systems with systems other than lidar, radar or sonar, e.g. with direction finders
  • G01S 17/89 - Lidar systems, specially adapted for specific applications for mapping or imaging

70.

RANGING DEVICE, AND METHOD FOR MANUFACTURING SAME

      
Application Number JP2023033872
Publication Number 2024/070803
Status In Force
Filing Date 2023-09-19
Publication Date 2024-04-04
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Suzuki Ryosuke
  • Fukunaga Hiroshi
  • Otake Yusuke
  • Wakano Toshifumi
  • Asayama Go

Abstract

[Problem] To perform ranging processing with low power consumption while enabling a reduction in size and cost. [Solution] This ranging device employs a light receiving unit to receive a reflected light signal resulting from a light pulse signal emitted from a light emitting unit being reflected by an object, and measures a distance to the object on the basis of the reflected light signal received by the light receiving unit, the ranging device comprising: a first board comprising a group 4 material on which the light receiving unit and the light emitting unit are disposed monolithically; and a second board which is stacked on the first board, and which has disposed thereon a readout circuit for reading out a light reception signal received by the light receiving unit.

IPC Classes  ?

  • G01S 7/481 - Constructional features, e.g. arrangements of optical elements
  • G01S 17/894 - 3D imaging with simultaneous measurement of time-of-flight at a 2D array of receiver pixels, e.g. time-of-flight cameras or flash lidar

71.

IMAGE PROCESSING DEVICE, IMAGE PROCESSING METHOD, AND PROGRAM

      
Application Number JP2023034433
Publication Number 2024/070925
Status In Force
Filing Date 2023-09-22
Publication Date 2024-04-04
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Sato, Taiki
  • Tabata, Hidenori
  • Yoneyama, Hisashi

Abstract

The objective of the present invention is to reduce an amount of calculation required for detection processing in a device that detects a three-dimensional shape of an object. An image processing device of the present disclosure includes an object detection region information generating portion. The object detection region information generating portion of the image processing device of the present disclosure generates object detection region information for detecting the three-dimensional shape of the object from a distance image including the object, on the basis of the distance image. Further, the object detection region information generated by an object region information generating portion of the image processing device of the present disclosure is information relating to a detection region of the object.

IPC Classes  ?

  • G01B 11/24 - Measuring arrangements characterised by the use of optical techniques for measuring contours or curvatures

72.

LIGHT DETECTING DEVICE, AND RANGING SYSTEM

      
Application Number JP2023035078
Publication Number 2024/071173
Status In Force
Filing Date 2023-09-27
Publication Date 2024-04-04
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Sekiya Akito
  • Hamamatsu Masamune
  • Endo Noriaki
  • Saito Yoshiyuki

Abstract

[Problem] To enable an improvement in ranging accuracy using a small number of light emissions and light receptions, irrespective of the distance to an object. [Solution] This light detecting device comprises: a light receiving unit for receiving, within a first time range, a first reflected light pulse signal resulting from a first light pulse signal emitted in a first time interval being reflected by an object, and receiving, within a second time range different from the first time range, a second reflected light pulse signal resulting from a second light pulse signal emitted in a second time interval different from the first time interval being reflected by the object; and a histogram generator for generating a first histogram in which reception frequencies of the first reflected light pulse signal received within the first time range are classified for each predetermined fixed unit period, and generating a second histogram in which the reception frequencies of the second reflected light pulse signals received within the second time range are classified for each unit period.

IPC Classes  ?

  • G01S 7/4863 - Detector arrays, e.g. charge-transfer gates
  • G01C 3/06 - Use of electric means to obtain final indication
  • G01S 17/894 - 3D imaging with simultaneous measurement of time-of-flight at a 2D array of receiver pixels, e.g. time-of-flight cameras or flash lidar

73.

PHOTODETECTION DEVICE AND PHOTODETECTION SYSTEM

      
Application Number 18249387
Status Pending
Filing Date 2021-09-02
First Publication Date 2024-04-04
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Ikeda, Yasuji

Abstract

A photodetection device according to the present disclosure includes a plurality of light-receiving sections that each generates a pulse signal including a pulse corresponding to a result of light reception, a plurality of edge detectors that each generates a detection signal by detecting an edge of the pulse in the pulse signal generated by a corresponding light-receiving section, and an adder that generates a detection value indicating number of the pulses on the basis of a plurality of the detection signals. The edge detectors each include a first latch circuit that generates a first signal by latching the pulse signal on the basis of a first clock signal, a second latch circuit that generates a second signal by latching the first signal on the basis of a second clock signal that is an inverted signal of the first clock signal, a combination circuit that generates a third signal on the basis of the pulse signal, the first signal, and the second signal, and a third latch circuit that generates the detection signal by latching the third signal on the basis of the first clock signal.

IPC Classes  ?

  • G01S 7/4863 - Detector arrays, e.g. charge-transfer gates
  • G01S 7/481 - Constructional features, e.g. arrangements of optical elements
  • G01S 7/487 - Extracting wanted echo signals

74.

PIXEL CIRCUIT, DISPLAY DEVICE, AND DRIVING METHOD

      
Application Number 18255585
Status Pending
Filing Date 2021-11-26
First Publication Date 2024-04-04
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Toyomura, Naobumi

Abstract

Provided are a pixel circuit, a display device, and a driving method that suppress a decrease in luminance. A pixel circuit according to the present disclosure includes a first transistor configured to control a current supplied to a light emitting element according to a voltage supplied to a first terminal, a first capacitor configured to hold the voltage supplied to the first terminal, a second transistor configured to sample a signal voltage of a video signal line, a second capacitor configured to hold the signal voltage sampled by the second transistor, and a third transistor configured to connect the second capacitor and the first capacitor and set a voltage corresponding to the signal voltage to the first capacitor by transferring electric charges accumulated in the second capacitor to the first capacitor.

IPC Classes  ?

  • G09G 3/3233 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element

75.

SOLID-STATE IMAGING DEVICE AND ELECTRONIC DEVICE

      
Application Number 18264707
Status Pending
Filing Date 2022-02-03
First Publication Date 2024-04-04
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Tojinbara, Hiroki

Abstract

A solid-state imaging device as disclosed includes a semiconductor layer having a light incidence surface and an element formation surface. The semiconductor layer includes a plurality of photoelectric conversion units including a first photoelectric conversion portion, a second photoelectric conversion portion, an isolation portion, a charge accumulation region, a first transfer transistor capable of transferring a signal charge from the first photoelectric conversion portion to the charge accumulation region, and a second transfer transistor capable of transferring a signal charge from the second photoelectric conversion portion to the charge accumulation region. The isolation portion includes a first region formed by an insulating material extending in a thickness direction of the semiconductor layer from the element formation surface side, and a second region provided on the light incidence surface side of the first region and formed by a semiconductor region into which impurities exhibiting a first conductivity type are implanted.

IPC Classes  ?

76.

ELECTRONIC DEVICE

      
Application Number 18264719
Status Pending
Filing Date 2022-01-28
First Publication Date 2024-04-04
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Imahigashi, Takashi

Abstract

An electronic device according to the present disclosure includes a semiconductor substrate, a chip, a bump, and a sidewall portion. The bump connects a plurality of connection pads provided on the opposing main surfaces of the semiconductor substrate and the chip. The sidewall portion includes a porous metal layer and that annularly surrounds a region where a plurality of bumps is provided, and connects the semiconductor substrate and the chip. The chip has a thermal expansion coefficient different from that of the semiconductor substrate by 0.1 ppm/° C. or more. The chip is a semiconductor laser, and the semiconductor substrate includes a drive circuit that drives the semiconductor laser.

IPC Classes  ?

  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01S 5/0234 - Up-side down mountings, e.g. Flip-chip, epi-side down mountings or junction down mountings
  • H01S 5/026 - Monolithically integrated components, e.g. waveguides, monitoring photo-detectors or drivers

77.

IMAGING ELEMENT AND IMAGING DEVICE

      
Application Number 18264724
Status Pending
Filing Date 2022-01-27
First Publication Date 2024-04-04
Owner Sony Semiconductor Solutions Corporation (Japan)
Inventor Okazaki, Tetsushi

Abstract

Imaging elements and devices that maintain the linearity of image signals with respect to the amount of incident light are disclosed. In one example, an imaging element includes a pixel, a photoelectric conversion unit connecting unit, a charge holding unit, charge transfer units, an image signal generating unit. The pixel includes photoelectric conversion units formed on a semiconductor substrate, the semiconductor substrate including a wiring region disposed on a front surface side, the photoelectric conversion units performing photoelectric conversion of incident light from an object to generate charges. The photoelectric conversion unit connecting unit connects the photoelectric conversion units to each other. The charge transfer units transfer the charges generated by the photoelectric conversion units to the charge holding unit. The image signal generating unit generates an image signal based on the held charges.

IPC Classes  ?

78.

OPTICAL MODULE AND DISTANCE MEASURING DEVICE

      
Application Number 18276347
Status Pending
Filing Date 2021-12-23
First Publication Date 2024-04-04
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Kobayashi, Takashi
  • Oiwa, Tatsuya
  • Xu, Jialun
  • Kimura, Motoi

Abstract

To improve resolution while suppressing the number of light emitting elements arranged in an optical module. To improve resolution while suppressing the number of light emitting elements arranged in an optical module. The optical module is provided with an optical element that converts a light beam emitted from the light emitting element into a substantially parallel light beam or a light beam having a predetermined angular width, and a diffraction element that diffracts the light beam to separate into a plurality of light beams. The diffraction element generates diffracted lights in n direction, and an angle θx formed between one diffraction direction and a side in a direction in which the light emitting element is arranged satisfies tan−1 (b/3a). A diffraction angle φx of the diffracted light satisfies m·sgrt((3φa){circumflex over ( )}2+φb{circumflex over ( )}2)/(2(2n+1)). Note that, φa and φb are angular differences of two light beams caused by inter-light emission distances a and b. Furthermore, n is a natural number, and m is a natural number excluding an integral multiple of 2n+1.

IPC Classes  ?

  • G01S 7/481 - Constructional features, e.g. arrangements of optical elements

79.

APPARATUSES AND METHODS FOR POLARIZATION BASED SURFACE NORMAL IMAGING

      
Application Number EP2023075650
Publication Number 2024/068335
Status In Force
Filing Date 2023-09-18
Publication Date 2024-04-04
Owner
  • SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
  • UNIVERSITY OF ZURICH (Switzerland)
Inventor
  • Muglikar, Manasi
  • Moeys, Diederik Paul
  • Scaramuzza, Davide

Abstract

The present disclosure relates to an apparatus for polarization-based surface normal imaging, the apparatus comprising a linear polarizer configured to rotate and to subsequently pass light from a scene, an event-based vision sensor, EVS, configured to detect a set of events of the scene based on the rotation angle of the linear polarizer, and a shape estimation processor configured to compute surface normal information of the scene based on the set of events and the corresponding rotation angle of the polarizer.

IPC Classes  ?

  • G06T 7/55 - Depth or shape recovery from multiple images

80.

COMPUTATION DEVICE, IMAGING DEVICE AND COMPUTATION METHOD

      
Application Number JP2022036010
Publication Number 2024/069769
Status In Force
Filing Date 2022-09-27
Publication Date 2024-04-04
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Saito Daisuke
  • Hanzawa Katsuhiko
  • Sakakibara Masaki
  • Maeda Noriaki
  • Naganuma Hideki

Abstract

The present disclosure provides a computation device equipped with a first signal line, a first capacitor which is connected to the first signal line, one or more sub-arrays which are connected to the first signal line, and a readout circuit for generating a digital signal which corresponds to the charge of the first signal line, wherein the sub-arrays have a second signal line which is connected to the first signal line via a first switching element, a second capacitor which is connected to the second signal line, and one or more memory cells which are connected to the second signal line and capable of imparting a charge, which corresponds to a signal value to be stored, to said second signal line.

IPC Classes  ?

  • G11C 11/54 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using elements simulating biological cells, e.g. neuron
  • G06G 7/60 - Analogue computers for specific processes, systems, or devices, e.g. simulators for living beings, e.g. their nervous systems
  • G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
  • G11C 11/412 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only

81.

PHOTOELECTRIC CONVERSION ELEMENT, AND PHOTODETECTOR

      
Application Number JP2023029560
Publication Number 2024/070293
Status In Force
Filing Date 2023-08-16
Publication Date 2024-04-04
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Takaguchi, Ryotaro
  • Joei, Masahiro
  • Hirata, Shintarou
  • Yagi, Iwao
  • Suzuki, Ryosuke

Abstract

A first photoelectric conversion element according to one embodiment of the present disclosure comprises: an electrode layer including a first electrode and a second electrode that are arranged in parallel; a third electrode that is arranged to face the first electrode and the second electrode; a photoelectric conversion layer that is provided between the electrode layer and the third electrode; an oxide semiconductor layer that is provided between the electrode layer and the photoelectric conversion layer; and a first insulating layer that is provided between the electrode layer and the oxide semiconductor layer, wherein the first insulating layer has an opening which allows the entire upper surface of the first electrode to be in contact with the oxide semiconductor layer without having the first insulating layer therebetween.

IPC Classes  ?

  • H01L 27/146 - Imager structures
  • H01L 31/10 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by at least one potential-jump barrier or surface barrier, e.g. phototransistors
  • H10K 30/60 - Organic devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation in which radiation controls flow of current through the devices, e.g. photoresistors

82.

LIGHT DETECTION ELEMENT AND ELECTRONIC DEVICE

      
Application Number JP2023032304
Publication Number 2024/070523
Status In Force
Filing Date 2023-09-05
Publication Date 2024-04-04
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Uehara Takuya

Abstract

[Problem] To suppress detection of noise events and to detect events quickly and precisely. [Solution] This light detection element comprises: a first pixel region including a plurality of first pixels which each detect an event based on the amount of change in the amount of incident light; and a second pixel region disposed in the vicinity of the first pixel region and including second pixels which detect the event in the surroundings of first pixels among the plurality of first pixels which have detected the event.

IPC Classes  ?

  • H04N 25/707 - Pixels for event detection
  • H04N 25/772 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising A/D, V/T, V/F, I/T or I/F converters
  • H04N 25/77 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components

83.

INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND RECORDING MEDIUM

      
Application Number JP2023032951
Publication Number 2024/070609
Status In Force
Filing Date 2023-09-11
Publication Date 2024-04-04
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Ando Hideki
  • Miyoshi Hironori

Abstract

The present disclosure pertains to an information processing apparatus, an information processing method, and a recording medium enabling an apparatus interposed between a device and an application apparatus to properly provide data from the device to the application apparatus. A data service (DS) is provided with a control unit for: acquiring, with regard to a plurality of app apparatuses, link information with respect to a device that outputs data and an app apparatus that performs prescribed data processing using data; determining a destination to which to send data acquired from one or more devices on the basis of the acquired link information; and performing control to transmit the data to the one or more app apparatuses determined to be the destination. The features of the present disclosure can be applied, for example, to apparatuses for performing data communication conforming to the NICE standard.

IPC Classes  ?

  • H04L 67/2871 - Implementation details of single intermediate entities
  • G06F 15/00 - Digital computers in general; Data processing equipment in general
  • H04L 67/50 - Network services
  • H04M 11/00 - Telephonic communication systems specially adapted for combination with other electrical systems

84.

SOLID-STATE IMAGING DEVICE, COMPARATOR AND ELECTRONIC EQUIPMENT

      
Application Number JP2023033581
Publication Number 2024/070740
Status In Force
Filing Date 2023-09-14
Publication Date 2024-04-04
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Hayashi Yasuaki
  • Umeda Kengo
  • Moue Takashi
  • Naganokawa Haruhisa

Abstract

[Problem] To reduce noise in an image sensor. [Solution] This solid-state imaging device comprises a light receiving element, a first amplification circuit, a second amplification circuit and a control circuit. The first amplification circuit amplifies and outputs the difference between a reference signal and an input signal outputted from the light receiving element. The second amplification circuit amplifies and outputs the first amplified signal outputted by the first amplification circuit. The control circuit controls, on the basis of the reference signal, an active load of the first amplification circuit or the mutual conductance of at least one of amplification transistors of the second amplification circuit.

IPC Classes  ?

  • H04N 25/78 - Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
  • H01L 27/146 - Imager structures
  • H03M 1/08 - Continuously compensating for, or preventing, undesired influence of physical parameters of noise
  • H03M 1/56 - Input signal compared with linear ramp

85.

IMAGE PROCESSING DEVICE, IMAGE PROCESSING METHOD, PROGRAM, AND IMAGING DEVICE

      
Application Number JP2023034587
Publication Number 2024/070979
Status In Force
Filing Date 2023-09-22
Publication Date 2024-04-04
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Tabata, Hidenori

Abstract

In the present invention, the data volume of a distance image is reduced. This image processing device has a second distance image generation unit. The second distance image generation unit generates a second distance image. The second distance image has a plurality of second pixels provided with information on the distance of first pixels that are pixels of a first distance image that is a distance image of a region including an object. The plurality of second pixels are respectively disposed corresponding to emission regions of structured light having a prescribed emission region pattern projected on a region including the object in order to generate the first distance image. The information on the distance of the first pixels at the positions corresponding to the emission regions is provided to the second pixels at the positions corresponding to the emission regions.

IPC Classes  ?

  • G01B 11/25 - Measuring arrangements characterised by the use of optical techniques for measuring contours or curvatures by projecting a pattern, e.g. moiré fringes, on the object
  • G06T 7/50 - Depth or shape recovery

86.

IMAGING ELEMENT AND ELECTRONIC DEVICE

      
Application Number JP2023035436
Publication Number 2024/071309
Status In Force
Filing Date 2023-09-28
Publication Date 2024-04-04
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Masuda Yoshiaki
  • Hatano Keisuke
  • Nagata Kengo
  • Noudo Shinichiro
  • Furuhashi Takahisa
  • Ando Atsuhiro

Abstract

The present technology pertains to an imaging element and an electronic device which can reduce time and labor in performing inspection during manufacturing. The imaging element comprises: a pixel array in which pixels including photoelectric conversion elements are two-dimensionally arrayed; a pad having an opening in a first surface side to which the pixel array is provided; an electrode provided, in an exposed state, to the bottom of the pad; a through-electrode having an opening in a second surface opposite to the first surface; and a rewiring layer layered on the second surface. The inside of the through-electrode is hollow. The present technology can be applied to, for example, an imaging element in a wafer-level chip size package (WLCLP).

IPC Classes  ?

  • H01L 27/146 - Imager structures
  • H01L 23/12 - Mountings, e.g. non-detachable insulating substrates
  • H04N 25/70 - SSIS architectures; Circuits associated therewith

87.

MEASUREMENT DEVICE AND MEASUREMENT METHOD

      
Application Number JP2023033140
Publication Number 2024/070653
Status In Force
Filing Date 2023-09-12
Publication Date 2024-04-04
Owner
  • SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
  • SONY GROUP CORPORATION (Japan)
Inventor
  • Kondo Fumitaka
  • Yamamoto Ken
  • Nakagawa Kei
  • Hiyama Ayaka

Abstract

The present technology pertains to a measurement device and a measurement method which enable accurate measurement of the concentration of glucose (dextrose) contained in an object to be measured. The concentration of glucose in the object to be measured is calculated on the basis of the complex dielectric constant of the object to be measured and moisture content of the object to be measured. The moisture content can be calculated on the basis of an incident signal, which represents an electromagnetic wave incident on the object to be measured, and a reflection signal, which represents reflection by the object to be measured.

IPC Classes  ?

  • G01N 22/00 - Investigating or analysing materials by the use of microwaves or radio waves, i.e. electromagnetic waves with a wavelength of one millimetre or more
  • G01N 22/04 - Investigating moisture content

88.

IMAGE PROCESSING DEVICE, IMAGE PROCESSING METHOD, AND PROGRAM

      
Application Number JP2023033646
Publication Number 2024/070751
Status In Force
Filing Date 2023-09-15
Publication Date 2024-04-04
Owner
  • SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
  • SONY GROUP CORPORATION (Japan)
Inventor
  • Yoneyama, Hisashi
  • Tanaka, Satoshi

Abstract

The objective of the present invention is to improve the convenience of an image processing device that detects the entry of a moving object into a target region. The image processing device includes an entry detecting portion. The entry detecting portion of the image processing device detects the entry of the object into the detection target region on the basis of specific information relating to the detection target region. The detection target region of the entry detecting portion is a region in which the object is to be detected. A specific region of the entry detecting portion is some information relating to the object in the detection target region.

IPC Classes  ?

89.

SOLID-STATE IMAGING ELEMENT AND ELECTRONIC APPARATUS

      
Application Number 18256289
Status Pending
Filing Date 2021-12-07
First Publication Date 2024-03-28
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Kugimiya, Katsuhisa

Abstract

A solid-state imaging element (1) according to the present disclosure includes a pixel array unit (10) in which a plurality of light receiving pixels (11) is two-dimensionally arranged. Each of the light receiving pixels (11) includes an organic photoelectric conversion unit (61) and another photoelectric conversion unit. The organic photoelectric conversion unit (61) includes a photoelectric conversion layer (63) made of an organic semiconductor material, a first electrode (62) located on a light incident side of the photoelectric conversion layer (63), and a second electrode (65) located on a side opposite to the light incident side of the photoelectric conversion layer (63). The other photoelectric conversion unit is located on a side opposite to the light incident side of the organic photoelectric conversion unit (61), and performs photoelectric conversion in a wavelength region different from a wavelength region of the organic photoelectric conversion unit (61). The second electrode (65) is connected to a connection wiring (51) including a metal wiring (54) made of metal and a transparent wiring (53) made of a transparent conductive film. The metal wiring (54) extends in a horizontal direction from a peripheral portion of the light receiving pixel (11) to a peripheral portion of the pixel array unit (10).

IPC Classes  ?

  • H10K 39/32 - Organic image sensors
  • H10K 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one organic radiation-sensitive element covered by group
  • H10K 39/38 - Interconnections, e.g. terminals

90.

INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND SENSING SYSTEM

      
Application Number 18264862
Status Pending
Filing Date 2021-12-23
First Publication Date 2024-03-28
Owner Sony Semiconductor Solutions Corporation (Japan)
Inventor
  • Takahashi, Kousuke
  • Kitano, Kazutoshi
  • Kawamura, Yuusuke
  • Kubota, Takeshi

Abstract

An information processing apparatus according to an embodiment includes: a recognition unit (122) configured to perform recognition processing on the basis of a point cloud output from a photodetection ranging unit (11) using a frequency modulated continuous wave to determine a designated area in a real object, the photodetection ranging unit being configured to output the point cloud including velocity information and three-dimensional coordinates of the point cloud on the basis of a reception signal reflected by an object and received, and configured to output three-dimensional recognition information including information indicating the determined designated area, and a correction unit (125) configured to correct three-dimensional coordinates of the designated area in the point cloud on the basis of the three-dimensional recognition information output by the recognition unit.

IPC Classes  ?

  • G01S 7/48 - RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES - Details of systems according to groups , , of systems according to group
  • G01S 17/42 - Simultaneous measurement of distance and other coordinates
  • G01S 17/58 - Velocity or trajectory determination systems; Sense-of-movement determination systems
  • G06F 3/01 - Input arrangements or combined input and output arrangements for interaction between user and computer

91.

THREE-DIMENSIONAL IMAGE CAPTURING ACCORDING TO TIME-OF-FLIGHT MEASUREMENT AND LIGHT SPOT PATTERN MEASUREMENT

      
Application Number 18273546
Status Pending
Filing Date 2022-01-26
First Publication Date 2024-03-28
Owner Sony Semiconductor Solutions Corporation (Japan)
Inventor
  • Cacho, Pepe Gil
  • Louveaux, Sebastien

Abstract

An electronic device comprising circuitry configured to disambiguate a first phase delay obtained according to an indirect Time-of-Flight principle to obtain a second phase delay, wherein the circuitry is configured to disambiguate the first phase delay based on a captured spot position.

IPC Classes  ?

  • G01S 17/36 - Systems determining position data of a target for measuring distance only using transmission of continuous waves, whether amplitude-, frequency-, or phase-modulated, or unmodulated with phase comparison between the received signal and the contemporaneously transmitted signal
  • G01S 17/46 - Indirect determination of position data
  • G01S 17/894 - 3D imaging with simultaneous measurement of time-of-flight at a 2D array of receiver pixels, e.g. time-of-flight cameras or flash lidar

92.

PIXEL CIRCUIT AND SOLID-STATE IMAGING DEVICE

      
Application Number 18275221
Status Pending
Filing Date 2022-02-17
First Publication Date 2024-03-28
Owner Sony Semiconductor Solutions Corporation (Japan)
Inventor
  • Zeituni, Golan
  • Eshel, Noam Zeev

Abstract

A pixel circuit (100) includes a photoelectric conversion circuit (110), an integration capacitor (Cint) and a supplementary circuit (120). The photoelectric conversion circuit (110) generates and outputs a photocurrent (Iphoto). The integration capacitor (Cint) includes a storage electrode (CintS) and a reference electrode (CintR), wherein the reference electrode (CintR) is connected to a first supply potential (VSUP1), and wherein the integration capacitor (Cint) is configured to integrate the photocurrent on the storage electrode (CintS) in an integration period (Tint). The supplementary circuit (120) pre-charges a working node (WN) between the photoelectric conversion circuit (110) and the storage electrode (CintS) to a pre-charge potential (Vpre) that differs from the first supply potential (VSUP1).

IPC Classes  ?

  • H04N 25/78 - Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
  • H01L 27/146 - Imager structures
  • H04N 25/709 - Circuitry for control of the power supply
  • H04N 25/771 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion

93.

COLUMN SIGNAL PROCESSING UNIT AND SOLID-STATE IMAGING DEVICE

      
Application Number 18276647
Status Pending
Filing Date 2022-02-17
First Publication Date 2024-03-28
Owner Sony Semiconductor Solutions Corporation (Japan)
Inventor
  • Zeituni, Golan
  • Eshel, Noam Zeev

Abstract

A column signal processing unit includes a current control circuit (110) and a feedback circuit (120). The current control circuit (110) is electrically connected between a data signal line (VSL) and a supply reference potential (GND). The feedback circuit (120) is configured to reduce a capacitive load of the data signal line (VSL). A feedback path (121) of the feedback circuit (120) includes a series connection of a feedback capacitor (122) and a delay element (123), wherein the delay element (123) is configured to increase a time delay in the feedback path (121).

IPC Classes  ?

  • H04N 25/78 - Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters

94.

IMAGING ELEMENT AND ELECTRONIC APPARATUS

      
Application Number 18529579
Status Pending
Filing Date 2023-12-05
First Publication Date 2024-03-28
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Nomura, Hirotoshi

Abstract

The present disclosure relates to an imaging element and an electronic apparatus configured to achieve higher-resolution image taking. The imaging element includes: a photoelectric conversion portion provided in a semiconductor substrate for each pixel that performs photoelectric conversion on light that enters through a filter layer; an element isolation portion configured to separate the photoelectric conversion portions of adjacent pixels; and an inter-pixel light shielding portion disposed between the pixels in a layer and provided between the semiconductor substrate and the filter layer and separated from a light receiving surface of the semiconductor substrate by a predetermined interval. Moreover, an interval between the light receiving surface of the semiconductor substrate and a tip end surface of the inter-pixel light shielding portion is smaller than a width of the tip end surface of the inter-pixel light shielding portion. The present technology is applicable to back-illuminated CMOS image sensors, for example.

IPC Classes  ?

95.

SOLID-STATE IMAGING DEVICE, METHOD FOR DRIVING THE SAME, AND ELECTRONIC DEVICE

      
Application Number 18531208
Status Pending
Filing Date 2023-12-06
First Publication Date 2024-03-28
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Hatano, Keisuke
  • Koga, Fumihiko
  • Yamaguchi, Tetsuji
  • Izawa, Shinichiro

Abstract

The present disclosure relates to a solid-state imaging device, a method for driving the solid-state imaging device, and an electronic device capable of improving auto-focusing accuracy by using a phase difference signal obtained by using a photoelectric conversion film. The solid-state imaging device includes a pixel including a photoelectric conversion portion having a structure where a photoelectric conversion film is interposed by an upper electrode on the photoelectric conversion film and a lower electrode under the photoelectric conversion film. The upper electrode is divided into a first upper electrode and a second upper electrode. The present disclosure can be applied to, for example, a solid-state imaging device or the like.

IPC Classes  ?

  • H04N 23/663 - Remote control of cameras or camera parts, e.g. by remote control devices for controlling interchangeable camera parts based on electronic image sensor signals
  • G02B 7/34 - Systems for automatic generation of focusing signals using different areas in a pupil plane
  • H01L 27/146 - Imager structures
  • H04N 23/67 - Focus control based on electronic image sensor signals
  • H04N 25/13 - Arrangement of colour filter arrays [CFA]; Filter mosaics characterised by the spectral characteristics of the filter elements
  • H04N 25/704 - Pixels specially adapted for focusing, e.g. phase difference pixel sets
  • H04N 25/778 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself
  • H10K 39/32 - Organic image sensors

96.

LIGHT-RECEIVING DEVICE, IMAGING DEVICE, AND DISTANCE MEASUREMENT DEVICE

      
Application Number 18531446
Status Pending
Filing Date 2023-12-06
First Publication Date 2024-03-28
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Ito, Kyosuke
  • Otake, Yusuke

Abstract

A light-receiving device according to an embodiment of the present disclosure includes a pixel array including light-receiving elements provided in respective pixels. The light-receiving elements each include a high electric field region and a photoelectric conversion region. A plurality of the light-receiving elements provided in the respective pixels includes a plurality of types of elements that have temperature regions having high photon detection efficiency (PDE). The temperature regions are different from each other and partially overlap each other.

IPC Classes  ?

  • H04N 23/52 - Elements optimising image sensor operation, e.g. for electromagnetic interference [EMI] protection or temperature control by heat transfer or cooling elements
  • G01S 7/481 - Constructional features, e.g. arrangements of optical elements
  • H04N 23/65 - Control of camera operation in relation to power supply

97.

SEMICONDUCTOR PACKAGE, SEMICONDUCTOR MODULE, ELECTRONIC DEVICE, AND SEMICONDUCTOR PACKAGE MANUFACTURING METHOD

      
Application Number JP2023024723
Publication Number 2024/062719
Status In Force
Filing Date 2023-07-04
Publication Date 2024-03-28
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Yasukawa, Hirohisa
  • Shigeta, Hiroyuki

Abstract

Disclosed herein is a semiconductor package including a semiconductor chip configured to have one of two surfaces thereof mounted with a circuit, the circuit formation surface constituting a circuit formation surface, a first shield layer configured to cover a side of the semiconductor chip and the other surface thereof, and a second shield layer configured to cover the circuit formation circuit.

IPC Classes  ?

  • H01L 23/552 - Protection against radiation, e.g. light
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 23/13 - Mountings, e.g. non-detachable insulating substrates characterised by the shape
  • H01L 23/498 - Leads on insulating substrates
  • H01L 23/50 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements for integrated circuit devices
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different main groups of groups , or in a single subclass of , , e.g. forming hybrid circuits

98.

ELECTRONIC DEVICE AND MANUFACTURING METHOD FOR ELECTRONIC DEVICE

      
Application Number JP2023025782
Publication Number 2024/062745
Status In Force
Filing Date 2023-07-12
Publication Date 2024-03-28
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Shigetoshi, Takushi

Abstract

An electronic device includes a substrate, a first through-hole penetrating the substrate, a capacitive element above the substrate, and a first conductor film. A first portion of the first conductor film traverses the substrate along a side wall of the first through-hole and a second portion of the first conductor film is in contact with the capacitive element.

IPC Classes  ?

  • H01G 4/33 - Thin- or thick-film capacitors
  • H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements

99.

INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, AND PROGRAM

      
Application Number JP2023031534
Publication Number 2024/062874
Status In Force
Filing Date 2023-08-30
Publication Date 2024-03-28
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Shibui, Shuichi
  • Nagumo, Masahiko
  • Nakada, Hitoshi
  • Kitami, Hirotaka
  • Saruta, Takashi

Abstract

An information processing device according to the present invention comprises an artificial intelligence (AI) image processing unit that: receives input of first image data and second image data as input data for an artificial intelligence model which has been trained with machine learning, said first image data being distance image data which is obtained on the basis of a light reception signal of a first sensor serving as a light-receiving sensor that performs a light reception operation for distance measurement, said second image data being image data obtained on the basis of a light reception signal of a second sensor that is a light-receiving sensor differing in type from the first sensor; and uses the artificial intelligence model to perform a process for inferring, as a correction target region, a distance measurement error region which appears in the first image data due to interference light that has been emitted from an outside object and that is in a light-reception wavelength band of the first sensor.

IPC Classes  ?

  • G01S 17/86 - Combinations of lidar systems with systems other than lidar, radar or sonar, e.g. with direction finders
  • G01S 7/495 - Counter-measures or counter-counter-measures
  • G01S 17/894 - 3D imaging with simultaneous measurement of time-of-flight at a 2D array of receiver pixels, e.g. time-of-flight cameras or flash lidar
  • G06N 20/00 - Machine learning

100.

MAGNETORESISTIVE ELEMENT, MEMORY DEVICE, AND ELECTRONIC APPLIANCE

      
Application Number JP2023033216
Publication Number 2024/062978
Status In Force
Filing Date 2023-09-12
Publication Date 2024-03-28
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Endo, Masaki

Abstract

A magnetoresistive element according to one embodiment of the present disclosure comprises a multilayer structure, a memory layer disposed on the multilayer structure and changeable in magnetization direction, a nonmagnetic layer disposed on the memory layer, and a reference layer disposed on the nonmagnetic layer and having a fixed magnetization direction. The multilayer structure comprises magnetic layers changeable in magnetization direction and nonmagnetic metal layers disposed on the magnetic layers.

IPC Classes  ?

  • H01L 29/82 - Types of semiconductor device controllable by variation of the magnetic field applied to the device
  • G11B 5/39 - Structure or manufacture of flux-sensitive heads using magneto-resistive devices
  • H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
  • H10N 50/10 - Magnetoresistive devices
  1     2     3     ...     88        Next Page