Current-accelerated voltage transition in a wireless communication circuit is disclosed. The wireless communication circuit includes a power management integrated circuit (PMIC) configured to generate a voltage, such as an average power tracking (APT) voltage, for amplifying a radio frequency (RF) signal in multiple continuous voltage modulation intervals. In a non-limiting example, each of the voltage modulation intervals can be an orthogonal frequency division multiplexing (OFDM) symbol or a timeslot with multiple OFDM symbols. According to embodiments disclosed herein, the PMIC can generate an acceleration current with an appropriate polarity to accelerate a transition of the voltage quickly between consecutive voltage modulation intervals. By supporting the current-accelerated voltage transition, the wireless transmission circuit can enable fast voltage adaptation to thereby improve operating efficiency of a power amplifier circuit.
Intra-symbol voltage change acceleration in a wireless transmission circuit is disclosed. The wireless transmission circuit includes a power amplifier circuit that amplifies a radio frequency (RF) signal based on an average power tracking (APT) voltage supplied by a power management integrated circuit (PMIC). The RF signal is modulated in multiple modulation symbols, such as orthogonal frequency division multiplex (OFDM) symbols. To prevent distortion (e.g., amplitude clipping) in the RF signal, the PMIC is configured to increase the APT voltage during each of the modulation symbols whenever the RF signal exceeds a predefined power threshold. Further, the PMIC is configured according to various acceleration embodiments to complete each APT volage change within a defined temporal limit (e.g., < 1 μs). By supporting intra-symbol voltage change acceleration, the wireless transmission circuit can enable fast APT voltage adaptation to thereby improve operating efficiency of the power amplifier circuit.
The present disclosure relates to a bulk acoustic wave (BAW) resonator, which includes a bottom electrode, a top electrode, and a piezoelectric layer sandwiched between the bottom electrode and the top electrode. Herein, an active region of the BAW resonator is divided into a central region, a recessed border (BO) region laterally contiguous to and surrounding the central region, and a mass loading BO region laterally contiguous to and surrounding the recessed BO region. A height of the recessed BO region is less than a height of the central region and less than a height of the mass loading BO region. A first portion of the piezoelectric layer, which is confined in the mass loading BO region, has a zero electromechanical coupling tensor, while a central portion of the piezoelectric layer, which is confined in the central region, has a non-zero electromechanical coupling tensor.
Systems and methods for providing dynamic data rates through dynamic header encoding are disclosed. In one aspect, a header for a data packet may be split into multiple parts, with a first part having a data rate encoded therein being sent at a first, slow data rate, with a remainder of the header being sent at a higher date indicated by the encoded data from the first part. By providing the data rate early in the packet header and then switching to a higher rate for the remainder of the header, the length of time required to transmit the header may be reduced. Since less time is required to the send the header, the data transmission is shorter, allowing the device to enter an inactive state so as to allow entry into a low-power mode.
Memory distortion neutralization in a power amplifier circuit (58) is provided. The power amplifier circuit (58) includes one or more amplifier stages (40, 42) each configured to amplify a radio frequency (RF) signal based on a time-variant modulated voltage received at a respective collector node. Notably, each of the amplifier stages (40, 42) can inherently cause a derivative of the time-variant modulated voltage (a.k.a. a modulated current) to be leaked from the respective collector node into a respective input node, which can create unwanted remodulation terms that can degrade an adjacent channel leakage ratio (ACLR) of the power amplifier circuit (58). Herein, a neutralization circuit (54, 60) is configured to inject a neutralization current to the respective input node to cancel at least a portion of the leaked modulated current.
Voltage switching in a power management integrated circuit (PMIC) is provided. The PMIC is required to increase or decrease a modulated voltage from a present voltage level in a present one of multiple time intervals to a future voltage level in an upcoming one of the time intervals with a very short switching interval. Herein, the PMIC determines whether to change the modulated voltage based on a first voltage transition scheme or a second voltage transition scheme, and toggle between the first voltage transition scheme and the second voltage transition scheme dynamically from one time interval to another. By employing the first voltage transition scheme or the second voltage transition scheme, the PMIC can switch the modulated voltage in a timely manner. Further, by opportunistically employing the first voltage transition scheme whenever possible, the PMIC can also help reduce potential power loss associated with switching the modulated voltage.
H03F 1/02 - Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
H03F 3/19 - High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
H03F 3/24 - Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
7.
ACOUSTIC WAVE DEVICE FOR ASYMMETRIC FREQUENCY BANDS AND MANUFACTURING METHOD, CHARGE WHEN COMPRESSED, TWISTED, OR DISTORTED, AND SIMILARLY COMPRESS, TWIST, OR DISTORT WHEN A CHARGE IS APPLIED
The present disclosure relates to an acoustic wave device for asymmetric frequency bands and a manufacturing process for making the same. The disclosed acoustic wave device includes at least one first electrode (102:152), at least one second electrode (104:152), a first piezoelectric layer (114) with a recess (116), and a second piezoelectric layer (118) fully covering the recess. Herein, the at least one first electrode is formed over the first piezoelectric layer, and the at least one second electrode is formed over the second piezoelectric layer and confined within the recess. The second piezoelectric layer does not cover a portion of the first piezoelectric layer, which is vertically underneath the at least one first electrode. The first piezoelectric layer and the second piezoelectric layer are formed of different piezoelectric materials.
H03H 3/02 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
A power management circuit is provided. Herein, a transceiver circuit is configured to generate a modulated differential signal that includes information related to a time-variant amplitude of a radio frequency (RF) signal. Accordingly, a power management integrated circuit (PMIC) can generate a modulated voltage, a modulated phase correction voltage, and a modulated amplitude correction voltage based on the modulated differential signal. The modulated voltage is provided to a power amplifier circuit for amplifying the RF signal, and the modulated phase correction voltage and the modulated amplitude correction voltage are provided to a power amplifier circuit to cause phase and amplitude adjustment in the RF signal. By performing phase and amplitude adjustment in the RF signal, it is possible to ensure proper aliment between the modulated voltage and the time-variant amplitude of the RF signal to thereby avoid potential distortion in the RF signal.
The present disclosure provides a method of fabricating radio frequency (RF) circuits using three-dimensional (3D), hybrid wafer-level bonded wafers. In one aspect, a first, bottom silicon-on-insulator (SOI) wafer and a second, top SOI wafer are provided. Complementary metal-oxide semiconductor processing is then performed on both the first and second SOI wafers to fabricate transistors and form RF circuits on each wafer. The second wafer is then bonded to the first wafer to electrically couple the RF circuits together. In an aspect, the 3D fabrication method enables RF circuits that are designed using transistor structures stacked in a three-dimensional (3D) folded configuration using a plurality of wafers. In one aspect, the RF circuit uses mirrored portions that are folded together during the wafer bonding process. In another aspect, the RF circuit uses asymmetric portions between the top versus bottom wafers.
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
H01L 21/66 - Testing or measuring during manufacture or treatment
10.
RADIO FREQUENCY (RF) BLOCKER DETECTION IN AN RF FRONTEND CIRCUIT
Radio frequency (RF) blocker detection in an RF frontend circuit is provided. In embodiments disclosed herein, the RF frontend circuit includes multiple detector circuits configured to measure strength of a received RF signal at multiple measurement points of an RF receive path and report the measured strength at each of the measurement points to a blocker detection circuit. Based on the measured strength at various measurement points, the blocker detection circuit can determine a presence and location of an RF blocker(s) inside or outside a signal passband of the received RF signal. Accordingly, the blocker detection circuit can take a corrective action locally and/or report the detected RF blocker(s) to a transceiver circuit to trigger proper corrective actions in the transceiver circuit. As a result, it is possible to block or suppress the RF blocker(s) around the signal passband to help improve receiver sensitivity of the RF receive path.
The present disclosure relates to a radio frequency (RF) module with a protection structure for enhanced ruggedness and reliability. The disclosed RF module includes a power amplifier (PA), a bias circuit configured to provide a direct current (DC) supply to the PA, and a protection structure coupled between the PA and the bias circuit. Herein, the protection structure is configured to generate a detector voltage by sensing reverse power reflected from an antenna back to at least the PA. The protection structure is configured to control the bias circuit to reduce the DC supply to the PA based on a comparison result between the detector voltage and a threshold voltage.
A supply voltage based analog predistortion (APD) circuit for a power amplifier is disclosed. In an exemplary aspect, the power amplifier is in a front end module (FEM) of a radio frequency (RF) transceiver. An APD circuit operates within an amplifier chain to normalize the distortion profile of the amplifier chain based on a supply voltage. A baseband processor (BBP) performs digital predistortion (DPD) on signals being sent from the BBP to the FEM. As a result of the APD circuit, the DPD may assume a normalized profile for the FEM, allowing for simplification of the DPD despite many possible distortions introduced by the amplifier chain based on the supply voltage.
An analog predistortion (APD) circuit is disclosed. In one aspect, the power amplifier is in a front-end module (FEM) of a radio frequency transceiver. An APD circuit operates within an amplifier chain to normalize the distortion of the amplifier chain. A baseband processor (BBP) performs digital predistortion (DPD) on signals being sent from the BBP to the FEM. As a result of the APD, the DPD may assume a normalized profile for the FEM, allowing for simplification of the DPD despite many possible distortions introduced by the amplifier chain.
Systems and methods for providing a protection loop for a power amplifier (PA CELL) are disclosed. In one aspect, an over voltage condition is detected (214, 216) at an output of the power amplifier (PA CELL), and a short circuit is selectively created at a base or gate of a transistor within the power amplifier (PA CELL) to debias the transistor and prevent an over voltage condition from damaging the transistor. Provision of such a fast acting over voltage protection option more readily accommodates and protects the power amplifier (PA CELL) in situations with high peak-to-average ratio conditions. This protection may prevent the transistor from being damaged by rapid power fluctuations that may occur, particularly in current cellular standards.
A fast-switching power management integrated circuit (PMIC) is provided. The PMIC is configured to provide an average power tracking (APT) voltage to a power amplifier circuit for amplifying a radio frequency (RF) signal modulated in multiple time intervals. Herein, the PMIC is configured to increase or decrease the APT voltage from a present voltage level in a present one of the time intervals to a future voltage level in an upcoming one of the time intervals with very short switching interval (e.g., < 20 nanoseconds). When the APT voltage transitions from the present voltage level to the future voltage level, the PMIC opportunistically activates a voltage amplifier to help ensure proper operation of the power amplifier circuit (e.g., maintain the APT voltage at the present level and reduce ripple in the APT voltage). As a result, the PMIC can switch the APT voltage frequently and rapidly with reduced inrush current.
Beamforming phase correction in a wireless communication circuit is provided. The wireless communication circuit is configured to emit multiple processed signals, which are generated by applying a codeword to a radio frequency (RF) signal. The codeword defines a set of complex-valued coefficients that will cause each of the processed signals to be associated with a respective one of multiple defined phases such that the processed signals can form an RF beam when emitted simultaneously from multiple antenna elements. However, some or all of the defined phases can be changed, for example, when the processed signals are amplified. In this regard, in embodiments disclosed herein, a phase correction circuit is configured to determine one or more phase correction terms and apply the determined phase correction terms to one or more of the processed signals to thereby correct undesired phase changes and restore coherency among the processed signals.
H04B 7/06 - Diversity systems; Multi-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station
A transceiver circuit operable in a dynamic power range is provided. In embodiments disclosed herein, the transceiver circuit is configured to generate a radio frequency (RF) signal and a target voltage that is adapted according to a power range of the RF signal. More specifically, the transceiver circuit is configured to generate the target voltage differently when the power range of the RF signal is higher (e.g., ≥ 18dBm) or lower (e.g., < 18 dBm). By adapting the target voltage based on the power range of the RF signal, it is possible to suppress a potential voltage ripple in a modulated voltage generated according to the target voltage to thereby achieve a desired adjacent channel leakage ratio (ACLR) when the RF signal is amplified at a power amplifier circuit based on the modulated voltage.
Methods and systems for thinning a device wafer to tens of micron, micron, or sub-micron thicknesses are disclosed. Device wafers are thinned by using a two-step grinding process and a chemical mechanical polish (CMP) process. One or more first grinding parameters associated with the first grinding process are determined, received, and/or adjusted before and/or during the performance of the first grinding process. One or more second grinding parameters associated with the second grinding process are determined, received and/or adjusted before and/or during the performance of the second grinding process. One or more polishing parameters associated with the CMP process are determined and/or adjusted before and/or during the performance of the CMP process.
H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting
B24B 7/04 - Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor involving a rotary work-table
19.
BIDIRECTIONAL COMMUNICATION FOR FRONT END MODULE (FEM)
Systems and method for bidirectional communication for front end modules (FEM) are disclosed. In one aspect, a bidirectional communication path tunneling through an existing communication bus between a FEM and a baseband processor is created. In a particular aspect, a driver may be hosted by an external processor and communicate with the baseband processor to effectuate the desired tunneled communication through the bus between the baseband processor and the FEM. The bidirectional communication may allow the FEM to adjust settings to optimize performance based on the information provided by the baseband processor. Likewise, information from the FEM may be used to adjust operation of the baseband processor.
Acoustic resonators with piston mode patches are disclosed. In one aspect, an interdigitated acoustic resonator (300) having plural fingers (308(1)-308(N)) or digits includes a modified piston mode rail. In particular, the piston mode rail is replaced with individual piston mode patches (320(1)-320(N); 322(1)-322(N)) that may be uniform or varied in size. Selection of patch size allows spurious modes to be suppressed to have a smooth filter passband with low overall insertion loss and minimal ripple. Further, the patches may be made through a monolithic process, which reduces overall production cost, complexity and cycle time.
An amplifier is disclosed having a carrier amplifier and a peaking amplifier coupled in parallel with the carrier amplifier, wherein the peaking amplifier has peaking output transistors. A peaking power supply adaptive bias generator is coupled to bias control terminals of the peaking output transistors. The peaking power supply adaptive bias generator is configured to sense supply voltage to the peaking amplifier and increase bias currents to the peaking output transistors as the supply voltage decreases.
Systems and methods for a hybrid technique for risk mitigation of platform software migration are provided. In some embodiments, a method for mitigating risk of platform software changes includes one or more of: detecting change using static code analysis; and detecting dynamic/runtime behavioral changes. In some embodiments, early detection of code base migration issues (long before the actual hardware availability) reduces OEM resource requirements for solving software integration issues. Since OEMs have NDAs with platform providers that prohibit OEMs from sharing material with third parties, some embodiments of the current disclosure allow solving platform code base migration issues early during software integration in the OEM environment without having access to a vast majority of the code base; and/or without the luxury of actually being able to see/touch the problem.
A power amplifier includes an over-current protection loop and/or an over-voltage protection loop to assist in preventing operation outside a safe operating zone. In particular, a trigger threshold for the protection loop may dynamically change as a function of another parameter associated with the transmission. Exemplary parameters include, but are not necessarily limited to: supply voltage, temperature, frequency, modulation, voltage standing wave ratio (VSWR), or combinations thereof. In still further exemplary aspects, the over-voltage protection loop may operate independently of the over-current protection current loop, or the over-voltage protection loop contribute to an over-current protection signal.
Systems and methods for fine ranging (FiRa) slot scheduling in ultra-wideband (UWB) enabled devices are disclosed. In particular, a control circuit may allocate slots within a UWB data phase based on required quality of service (QoS) parameters. More particularly, a control circuit may set up one or more connections based on connection requests that are accompanied by QoS indicators. The control circuit may then allocate slots according to the QoS indicator, where slots are initially allocated to connections with the highest QoS indicator and then allocated through connections with increasingly lower QoS indications. In this manner, the QoS guarantees are satisfied, improving the overall user experience.
A virtual radio frequency (VRF) equalizer for an envelope tracking integrated circuit (ETIC) is disclosed. In one aspect, an ETIC provides envelope tracking (ET) for a barely Doherty (BD) power amplifier stage. The VRF equalizer includes circuitry that provides ripple cancelation that is caused by load modulation of the BD power amplifier stage. Additional circuitry is included to compensate for an amplifier within the ETIC. By canceling the ripple within the ETIC, the overall performance and efficiency of the BD power amplifier stage is improved, resulting in better performance of a transmitter in a wireless communication device. Still further, frequency equalization may be achieved using the circuits disclosed herein.
A power amplification circuit (600) includes an amplifier circuit (100) and a circuit (602) protecting the amplifier circuit (100) from destructive voltage. The amplifier circuit includes a first cascode transistor (104(1)) coupled to an output node, a last cascode transistor (104(5)) coupled to a reference voltage node (GND), and one or more cascode transistors (104(2)-104(4)) coupled between the first cascode transistor (104(1)) and the last cascode transistor (104(5)). Circuit protecting the amplifier circuit (100) may include a protection circuit (602) to provide a feedback signal to a bias circuit (606) to reduce the bias voltage on the last cascode transistor (104(5) ) and/or a stress control circuit (604) coupled to a control terminal of the first cascode transistor (104(1)) to increase the bias voltage on a control terminal of the first cascode transistor (104(1)) to avoid a destructive voltage.
H03F 1/22 - Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively
H03F 1/52 - Circuit arrangements for protecting such amplifiers
H03F 3/193 - High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only with field-effect devices
27.
CASCODE POWER AMPLIFICATION CIRCUITS, INCLUDING VOLTAGE PROTECTION CIRCUITS
A power amplification circuit includes an amplifier circuit (800) comprising cascode transistors coupled in series between an output node (816) and a reference voltage node. A bias control circuit includes an on-state bias control circuit (806), a first off-state bias control circuit, and a second off-state bias control circuit to provide bias voltages to control terminals of the plurality of cascode transistors. The on-state bias control circuit (806) controls the bias voltages during operation. In a first off-state, an electrostatic charge may cause a destructive voltage on the output node (816). The first off-state bias circuit (808) generates bias voltages based on the electrostatic charge. A second off-state condition occurs in an inactive amplifier circuit coupled to an output node on which a voltage is generated by a parallel active amplifier circuit coupled to the output node (816).
H03F 1/22 - Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively
H03F 1/52 - Circuit arrangements for protecting such amplifiers
H03F 3/193 - High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only with field-effect devices
H03F 1/30 - Modifications of amplifiers to reduce influence of variations of temperature or supply voltage
A multi-transmission envelope tracking (ET) circuit is provided. The multi-transmission ET circuit includes multiple voltage circuits configured to generate multiple modulated voltages for amplifying multiple radio frequency (RF) signals, respectively. Each of the voltage circuits is configured to generate a respective modulated voltage based on a respective supply voltage so generated to prevent amplitude distortion in the respective modulated voltage. In this regard, a control circuit is provided to determine an appropriate supply voltage for each of the voltage amplifiers. In embodiments disclosed herein, the control circuit determines a respective supply voltage for each of the voltage circuits based on a respective peak-to-peak range of the respective modulated voltage. As a result, it is possible to improve operating efficiency of the voltage circuits concurrent to reducing amplitude distortion, energy waste, and heat dissipation.
A power amplifier with analog predistortion is disclosed. In one aspect, a signal in the transmission chain is sampled to determine if an amplitude distortion (expansion or compression) is present. Information about the sampled signal is provided to a control circuit, which uses an analog predistortion circuit to inject a correction signal into the transmission chain so as to offset or compensate for the amplitude distortion. In an exemplary aspect, the analog predistortion circuit adjusts a bias signal provided to the power amplifier. This detection and adjustment may be done in the front end of the transmission chain so as to avoid reliance on a baseband processor. Use of such analog predistortion helps maintain desired linear operation over the large bandwidths of emerging wireless communication standards.
A hybrid power amplifier circuit is provided. The hybrid power amplifier circuit includes a carrier amplifier and a peak amplifier configured to collectively amplify a radio frequency (RF) signal from a time-variant input power to a time-variant output power based on an envelope tracking (ET) modulated voltage. A control circuit is provided in the hybrid power amplifier circuit to bias the peak amplifier based on a reference voltage (e.g., a battery voltage) to present a modulated load impedance to the carrier amplifier to thereby cause the carrier amplifier to operate in compression in response to an average of the ET modulated voltage being substantially equal to the reference voltage. By using the ET modulated voltage to cause the carrier amplifier to operate in compression, it is possible to improve efficiency of the carrier amplifier and the hybrid power amplifier circuit as a whole.
A power amplifier with analog predistortion is disclosed. In one aspect, a signal in the transmission chain is sampled to determine if a phase distortion (delay or advancement) is present. Information about the sampled signal is provided to a control circuit, which uses an analog predistortion circuit to inject a correction signal into the transmission chain so as to offset or compensate for the phase distortion. In an exemplary aspect, the analog predistortion circuit may use a variable capacitor to generate the correction signal that is injected. This detection and adjustment may be done in the front end of the transmission chain so as to avoid reliance on a baseband processor. Use of such analog predistortion helps maintain desired linear operation over the large bandwidths of emerging wireless communication standards.
Systems and methods for fine ranging (FiRa) link layer control in ultra-wideband (UWB) enabled devices are disclosed. In one aspect, a link layer control plane acts as a black box to an application developer requiring minimal inputs therefrom, but allows connections to be created, paused, resumed, and/or deleted as needed or desired. Exemplary inputs include a qualify of service indicator, target bitrate, disorder metrics, maximum burst size and the like. By implementing aspects of the present disclosure, an application developer does not have to allocate UWB resources, simplifying the design process for the application developer. Further and more specifically, exemplary aspects of the present disclosure allow the link layer to establish, stop, or resume connections and high-level requests from an application may be translated into MAC or link layer parameters.
H04L 69/321 - Interlayer communication protocols or service data unit [SDU] definitions; Interfaces between layers
H04L 69/324 - Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions in the data link layer [OSI layer 2], e.g. HDLC
H04W 4/80 - Services using short range communication, e.g. near-field communication [NFC], radio-frequency identification [RFID] or low energy communication
A bias circuit (3300) for a power amplifier (3310) is disclosed. The bias circuit (3300) may select between different power sources based on a power need for the power amplifier (3310). As voltage levels between the different power sources may differ at the moment of transition, additional circuitry is provided to smooth the transition between the differing power levels. Further, the bias circuit (3300) may provide bias signals to multiple stacked transistors in the power amplifier (3310) in such a manner so as to avoid collapsing any of the transistors. One such approach is a piecewise linear bias signal. Still further, the bias circuit (3300) may interoperate with predistortion circuitry to assist in linear operation of the power amplifier (3310). Still further, the bias circuit (3300) may interoperate with protection circuitry to prevent over current, over voltage, or over power conditions that may damage the power amplifier (3310).
H03F 1/22 - Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively
H03F 1/52 - Circuit arrangements for protecting such amplifiers
H03F 3/193 - High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only with field-effect devices
H03F 1/30 - Modifications of amplifiers to reduce influence of variations of temperature or supply voltage
H03F 1/02 - Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
H03F 1/32 - Modifications of amplifiers to reduce non-linear distortion
34.
VOLTAGE RIPPLE CANCELLATION IN A TRANSMISSION CIRCUIT
Voltage ripple cancellation in a transmission circuit is provided. The transmission circuit includes a power amplifier circuit that amplifies a radio frequency (RF) signal based on a modulated voltage and a modulated current. Specifically, the modulated current is generated inside the power amplifier circuit based on a time-variant input power of the RF signal, and the modulated voltage is generated by an envelope tracking integrated circuit (ETIC) based on a time-variant target voltage and provided to the power amplifier circuit via a conductive path. Collectively, the ETIC and the conductive path present a total inductive impedance that interacts with the modulated current to cause a ripple in the modulated voltage at the power amplifier circuit. Herein, a transceiver circuit is configured to add a compensation term to the modulated target voltage to cancel the ripple in the modulated voltage to thereby improve overall RF performance of the transmission circuit.
Systems and methods for front-end linearization using information from a baseband circuit are disclosed. In one aspect, a baseband circuit provides information to a front-end module that uses the information to adjust operating parameter settings such as how an analog predistortion (APD) circuit or power management integrated circuit behaves to provide more linear operation of the front-end module across the frequencies of interest. In exemplary aspects, the front-end module may receive raw information from which the front-end module determines what changes should be made. In alternate exemplary aspects, the baseband circuit provides instructions or coefficients that are then used by the front-end module to make the changes. In either event, the front-end module may optimize operation to reduce power consumption and provide more linear operation so that the transceiver may better operate within the parameters of a given wireless protocol.
Hybrid predistortion in a wireless transmission circuit is provided. The wireless transmission circuit includes a transceiver circuit that generates a radio frequency (RF) signal and a power amplifier circuit than amplifies the RF signal for transmission. In aspects disclosed herein, the transceiver circuit is configured to perform a digital predistortion(s) (DPD) on a digital version of the RF signal and the power amplifier circuit is configured to perform an analog predistortion(s) (APD) on the RF signal to collectively cancel varies types of distortions in the RF signal. By concurrently performing a combination of DPD and APD (a.k.a. hybrid predistortion) across the transceiver circuit and the power amplifier circuit, it is possible to effectively restore linearity in the RF signal and improve overall performance of the wireless transmission circuit with reduced footprint, cost, and computational complexity.
A compact electrostatic discharge (ESD) structure comprises a substrate; a sub-collector region over the substrate; a collector region over a first portion of the substrate; and a base region over the collector region; an emitter region over the base region, wherein the emitter region, the base region, and the collector region form a bipolar transistor. A cathode region is provided over a second portion of the substrate. An anode contact is provided over the cathode region, wherein the cathode region and the anode contact form a Schottky diode. An emitter/anode bridge electrically couples the emitter region to the anode contact, wherein the collector region and the cathode region are electrically coupled via the sub-collector region such that the bipolar transistor and the Schottky diode are connected in an anti-parallel.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
A power amplifier system having a power amplifier stage with dynamic bias circuitry is disclosed. Also included is bias control circuitry having a compression sensor having a sensor input coupled to a RF signal output and a sensor output, wherein the compression sensor is configured to generate a gain deviation signal in response to a sensed deviation from a flat gain profile of the power amplifier stage. Further included is a bias driver that is configured to drive dynamic bias circuitry to adjust bias to the power amplifier stage to maintain the flat gain profile in response to the gain deviation signal.
Disclosed is a power amplifier having an output stage (12) having a radio frequency (RF) output (14) and an RF input (16) and a driver stage (18) having a driver input (20) coupled to the RF input (16), a control input (22), and a driver output (24), wherein the driver stage (18) is configured to have a controllable soft compression characteristic that substantially neutralizes a gain expansion characteristic of the output stage (12). Also included is a controller (26) having a control output (28) coupled to the control input (22) of the driver stage (18), wherein the controller (26) is configured to generate a control signal at the control output (28) that controls the soft compression characteristic of the driver stage (18).
H03F 1/02 - Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
H03F 1/22 - Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively
H03F 3/193 - High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only with field-effect devices
H03F 3/24 - Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
H03G 3/30 - Automatic control in amplifiers having semiconductor devices
A power amplifier system is disclosed having an N number of transistors coupled together drain-to-source between a supply node and a fixed voltage node, wherein a first one of the N number of transistors coupled nearest to the fixed voltage node is configured to operate as an amplifying device in an ON-mode, and remaining ones of the N number of transistors are configured to operate as cascode devices in the ON-mode and to operate as turned-off switches in an OFF-mode. A controller is configured to place the N number of transistors in the first mode when a radio frequency (RF) signal is to be amplified by the first one of the N number of transistors and to place the N number of transistors in the second mode when the RF signal is not to be amplified by the first one of the N number of transistors.
H03F 1/22 - Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively
Power amplifiers having improved gate oxide integrity are disclosed. In particular, a dynamic asymmetric cascode bias circuit is used to provide a bias signal to a cascode power amplifier stage. The bias signal swings in synchronicity with an output signal from the power amplifier stage. By having this dynamic bias signal, the gate-drain stress on the device is reduced, preserving gate oxide integrity. Preserving gate oxide integrity helps preserve the operational profile and extend device life, providing an enhanced user experience.
H03F 1/22 - Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively
H03F 1/52 - Circuit arrangements for protecting such amplifiers
A self-organized mesh network is disclosed. In a non-limiting example, the self-organized mesh network can be an ultra-wideband (UWB) based mesh network. Herein, the self-organized mesh network includes multiple node clusters, each anchored by a respective coordinating node. In an embodiment, the coordinating node can detect a secure node(s) and a secure bridge node(s) among the secure node(s) in a respective node cluster and establish secure communication links (e.g., based on UWB protocol) with the detected secure node(s) and secure bridge node(s). Further, through the detected secure bridge node(s), the coordinating node can further detect adjacent and non-adjacent node clusters. Accordingly, the coordinating node can establish secure communications with the detected adjacent and/or non-adjacent node clusters.
Intra-symbol voltage modulation in a wireless communication circuit is disclosed. In a wireless communication circuit, a power amplifier circuit is configured to amplify a radio frequency (RF) signal based on a modulated voltage that tracks a time-variant input power of the RF signal. Herein, intra-symbol voltage modulation means that the modulated voltage can be adapted within a voltage modulation interval(s), such as an orthogonal frequency division multiplexing (OFDM) symbol duration. In embodiments disclosed herein, the voltage modulation interval(s) is divided into multiple voltage modulation subintervals and a respective voltage target is determined for each of the voltage modulation subintervals. Accordingly, the modulated voltage can be adapted in each of the voltage modulation subintervals according to the respective voltage target. By performing intra-symbol voltage modulation during the voltage modulation interval(s), the power amplifier circuit can operate with higher efficiency and prevent distortion (e.g., amplitude clipping) when amplifying the RF signal.
A cascode circuit is formed using a high voltage transistor in series with a low voltage transistor. A clamp switch device is used to discharge the gate of the high voltage transistor when the cascode is off. Rate limiting devices may be used control turn on and turn off characteristics of the cascode. Rate limiting devices may be include resistors and/or transistors. The high voltage transistor may be a normally on silicon carbide JFET, for example, and the low voltage transistor may be a silicon MOSFET.
H03K 17/16 - Modifications for eliminating interference voltages or currents
H03K 17/567 - Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT
H03K 17/06 - Modifications for ensuring a fully conducting state
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
A power amplifier includes an over-current protection loop (202) and an over-voltage protection loop (204) to assist in preventing operation outside a safe operation zone. In a further exemplary aspect, triggering of the over-current protection loop (202) adjusts a threshold voltage for the over-voltage protection loop (204). In further exemplary aspects, the over-current protection loop (202) may adjust not only a bias regulator, but also provide an auxiliary control signal that further limits signals reaching the power amplifier. In still further exemplary aspects, the over-voltage protection loop (204) may operate independently of the over-current protection current loop (202) or the over-voltage protection loop (204) contribute to an over-current protection signal.
A power amplifier circuit (520) comprising a power amplifier (206) comprising an output stage (208) configured to provide an amplified output signal; a power detector circuit (528) coupled to the power amplifier (206) and configured to provide an overpower protection signal (530) to a circuit that uses the overpower protection signal to control a bias signal for the output stage (208), wherein the circuit comprises a regulator circuit (218) configured to control a bias circuit (214) coupled to the output stage (208) through a resistor (216); and a current detector circuit (220) coupled to the power amplifier (206) and configured to provide an overcurrent protection signal (222) to the bias regulator circuit (218) that uses the overcurrent protection signal (222) to control the bias circuit (214) for the output stage (208).
A transceiver circuit (68) generates a radio frequency (RF) signal from a time-variant modulation vector and a power amplifier circuit (36) amplifies the RF signal based on a modulated voltage. The transceiver circuit (68) is configured to apply an equalization filter to the time¬ variant modulation vector to thereby compensate for a voltage distortion filter created at the output stage of the power amplifier circuit (36). In embodiments disclosed herein, a calibration circuit can be configured to calibrate the equalization filter across multiple frequencies within a modulation bandwidth of the power amplifier circuit (36) to generate a gain offset LUT (72) and a delay LUT (74). As a result, the equalization filter can be dynamically adapted to reduce undesired instantaneous excessive compression and/or spectrum regrowth resulting from the voltage distortion filter across the modulation bandwidth of the power amplifier circuit (36).
Systems and methods for detecting and classifying types of physical inputs on an input surface of a human machine interface (HMI) input structure are disclosed. In response to a physical input on the input surface, one or more sensor signals are received from respective sensors associated with the HMI input structure. One or more features are determined for each received sensor signal. Based on the one or more features for each sensor signal, a position on the input surface is determined by classifying the one or more sensor signals. The classification of the one or more sensor signals can be performed by one or more machine learning algorithms. Based on a classification of the physical input, an action associated with the determined location is executed.
G06F 3/041 - Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
G06F 3/0354 - Pointing devices displaced or positioned by the user; Accessories therefor with detection of 2D relative movements between the device, or an operating part thereof, and a plane or surface, e.g. 2D mice, trackballs, pens or pucks
H01L 41/113 - Piezo-electric or electrostrictive elements with mechanical input and electrical output
A power management circuit supporting fast voltage switching with reduced rush current is provided. The power management circuit is configured to provide an average power tracking (APT) voltage to a power amplifier circuit for amplifying an analog signal. Moreover, the power management circuit must be able to adapt the APT voltage frequently and rapidly to enable such application as dynamic power control. In embodiments disclosed herein, the power management circuit can be configured to opportunistically activate a voltage amplifier, which is typically used to generate an envelope tracking (ET) voltage, at an appropriate time to help support fast switching of the APT voltage. As a result, the power management circuit is able to adapt the APT voltage frequently and rapidly. Furthermore, by utilizing the voltage amplifier to support fast switching of the APT voltage, it is also possible to reduce rush current in the power management circuit.
A phasor-based signal detector includes a signal processor to detect symbols in a received signal in the presence of an offset between the carrier frequency and an oscillator frequency of the signal processor. The signal processor calculates a phasor that indicates a phase difference between a first sample in a first symbol group and a second sample in a second symbol group. The first and second samples each include a real part and an imaginary part corresponding to a same sample position within the first and second symbol groups. Calculating the phasor includes a complex multiplication of one of the samples and a conjugate of the other one of the samples. A phase difference indicated by a phasor meeting a criteria may be used to estimate a carrier frequency offset (CFO). If the CFO is within a supported range, the signal processor may coherently accumulate symbols.
Various arrangements for a microelectromechanical (MEMS) die and a controller die in vertically stacked structures are disclosed. The orientations of the MEMS die and the controller die vary in the various arrangements. In one embodiment, a backside surface of the MEMS die is operably connected to a frontside surface of the controller die. In another embodiment, a backside surface of the MEMS die is operably connected to a backside surface of the controller die. In another embodiment, a frontside surface of the MEMS die is operably connected to a backside surface of the controller die. In yet another embodiment, a frontside surface of the MEMS die is operably connected to a frontside surface of the controller die.
A Doherty amplifier system (10) is disclosed having a carrier amplifier (12) with a carrier drain bias input (14), and a peak amplifier (24) having a peak drain bias input (26), and a peak gate bias input (28). Also included is a programmable bias controller (40) having a data interface configured to receive peak-to-average power ratio (PAPR) data associated with a basestation. The programmable bias controller (40) further includes a processor (46) coupled to the data interface and configured, in response to the PAPR data, to determine and apply bias levels to the carrier drain bias input (14), the peak drain bias input (26), and the peak gate bias input (28) to provide an amplifier efficiency between 30% and 78.5%.
The present disclosure describes an amplification stage (12) which includes a top amplification structure (16) having a top collector and a bottom amplification structure (18) having a bottom collector. The top amplification structure (16) and the bottom amplification structure (18) are identical. A transforming circuitry (44) is connected to the amplification stage (12) at the top collector and the bottom collector and includes a common mode change structure (50). Herein, the common mode change structure (50) includes a first primary capacitor (46-1), a second primary capacitor (46-2), and a shunt inductor (48). The first primary capacitor (46-1) and the second primary capacitor (46-2) are identical and electrically coupled in series between the top collector and the bottom collector. The shunt inductor (48) is electrically coupled between a connection point of the first primary capacitor (46-1) and the second primary capacitor (46-2) and ground.
The present disclosure relates to a fabricating procedure of a radio frequency device, in which a precursor wafer including active layers, SiGe layers, and a silicon handle substrate is firstly provided. Each active layer is formed from doped epitaxial silicon and underneath a corresponding SiGe layer. The silicon handle substrate is over each SiGe layer. Next, the silicon handle substrate is removed completely, and the SiGe layer is removed completely. An etch passivation film is then formed over each active layer. Herein, removing each SiGe layer and forming the etch passivation film over each active layer utilize a same reactive chemistry combination, which reacts differently to the SiGe layer and the active layer. The reactive chemistry combination is capable of producing a variable performance, which is an etching performance of the SiGe layer or a forming performance of the etch passivation film over the active layer.
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 23/433 - Auxiliary members characterised by their shape, e.g. pistons
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
55.
ISOLATION PROVISION FROM MULTIPLE ANTENNAS TO A SINGLE ANTENNA
A directional coupler is operably connected to each antenna of a transmitting transceiver that has multiple antennas, and a tunable load is operably connected to each directional coupler. The directional couplers act to couple a co-located receiving transceiver to the antennas of the transmitting transceiver. Each tunable load is constructed based on a reflection coefficient (Γ) that is determined for that tunable load, in that the type of components and/or the values of some or all of the components that are used in the tunable load are determined based on the reflection coefficient (Γ) associated with that tunable load. The tunable loads cancel or reduce interferences experienced by the co- located receiving transceiver when the transmitting transceiver is transmitting using at least one of the multiple antennas.
H04B 1/525 - Hybrid arrangements, i.e. arrangements for transition from single-path two-direction transmission to single-direction transmission on each of two paths or vice versa with means for reducing leakage of transmitter signal into the receiver
H01Q 1/52 - Means for reducing coupling between antennas; Means for reducing coupling between an antenna and another structure
Disclosed is an ultra-wideband integrated circuit (10) having a transmitter (12), a receiver (14), and a non-volatile memory (16) configured to store a time-of-flight between the transmitter (12) and receiver (14). Also included is a digital interface (18) configured to communicate with a processor (20) configured to calculate the time-of-flight. Further included is a digital transceiver (22) configured, in response to a loopback mode, to cause the transmitter (12) to transmit a plurality of ultra-wideband frames directly to the receiver (14), measure a time-of-flight for each of the plurality of ultra-wideband frames received by the receiver (14) and generate a data set for calculating the time-of-flight associated with each measured time-of-flight, send the data set to the processor (20), receive from the processor (20) the time-of-flight calculated from the data set, and store the time-of-flight in the non-volatile memory (16).
An edge enabled void isolator (EEVI) for antennas is provided. In particular, two or more antennas are separated from one another by respective EEVI to provide isolation between the antennas. This isolation allows the antennas to be placed in close proximity, keeping the footprint of the antenna system relatively small for ease of use in small wireless devices. While two monopole antennas are specifically contemplated, the disclosure may be extended to more than two antennas and these antennas may be monopole, dipole, F, or the like.
An antenna in a lightbulb may include a conductive plane (e.g., a ground plane) that includes an edge-enabled void antenna (EEVA) with the EEVA including a corresponding edge-enabled void isolator (EEVI). Use of both the EEVA and the EEVI allows for a small antenna footprint for incorporation into a lightbulb. Optionally, two EEVAs, each with a corresponding EEVI may be used. Various arrangements are provided to illustrate possible compromises between structural integrity and cooling. Further, by using two EEVAs, diversity reception and transmission is possible, increasing the utility of the lightbulb by expanding directionality of the transmission/reception and/or improving communication through spatial diversity.
H01Q 21/28 - Combinations of substantially independent non-interacting antenna units or systems
H01Q 1/44 - ANTENNAS, i.e. RADIO AERIALS - Details of, or arrangements associated with, antennas using equipment having another main function to serve additionally as an antenna
F21K 9/232 - Retrofit light sources for lighting devices with a single fitting for each light source, e.g. for substitution of incandescent lamps with bayonet or threaded fittings specially adapted for generating an essentially omnidirectional light distribution, e.g. with a glass bulb
F21K 9/238 - Arrangement or mounting of circuit elements integrated in the light source
F21V 29/71 - Cooling arrangements characterised by passive heat-dissipating elements, e.g. heat-sinks using a combination of separate elements interconnected by heat-conducting means, e.g. with heat pipes or thermally conductive bars between separate heat-sink elements
F21Y 103/10 - Elongate light sources, e.g. fluorescent tubes comprising a linear array of point-like light-generating elements
Systems and methods of the present disclosure are directed to an electronic substrate. The electronic substrate includes a base layer, first feature(s) formed from a first metal layer and a second metal layer, and second feature(s) formed from the first metal layer. The electronic substrate includes a polymerized photodielectric layer over the first feature(s) and the second feature(s). The polymerized photodielectric layer exposes a portion of the second metal layer of the first feature(s), and at least a portion of the first metal layer of the second feature(s).
H05K 3/34 - Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
A field effect transistor (FET) transconductance device with varying gate lengths is disclosed. In one aspect, the varying effective gate lengths are used in a differential architecture to obtain linear even and odd order operation simultaneously. In a particular aspect, the effective gate lengths may be varied according to a differential Multi-Tanh-like architecture. This variation of effective gate lengths enables a compact implementation particularly as compared to varying gate width or emitter areas while also providing linear even and odd order operation simultaneously.
A power management apparatus operable with multiple configurations is disclosed. In embodiments disclosed herein, the power management apparatus can be configured to concurrently generate multiple modulated voltages based on a configuration including a single power management integrated circuit (PMIC) or a configuration including a PMIC and a distributed PMIC. Regardless of the configuration, the power management apparatus employs a single switcher circuit, wherein multiple reference voltage circuits are configured to share a multi-level charge pump (MCP). As a result, it is possible to reduce footprint of the power management apparatus while improving isolation between the multiple modulated voltages.
A signal processing apparatus and related transceiver circuit are disclosed. The signal processing apparatus includes a power amplifier circuit and a transceiver circuit. The transceiver circuit is configured to generate multiple composite signals each having a respective one of multiple inverted intermodulation product terms. The power amplifier circuit includes multiple power amplifiers each configured to amplify a respective one of the composite signals. By including the inverted intermodulation product terms in the composite signals prior to amplifying the composite signals, it is possible to offset intermodulation product terms inherently caused by nonlinear responses of the power amplifiers, thus helping to reduce spectrum degradation in the signal processing apparatus.
A fast-switching power management circuit operable to prolong battery life is provided. The power management circuit includes a voltage circuit that can generate an output voltage for amplifying an analog signal in a number of time intervals and a pair of hybrid circuits each causing the output voltage to change in any of the time intervals. A control circuit is configured to activate any one of the hybrid circuits during a preceding one of the time intervals to cause the output voltage to change in an immediately succeeding one of the time intervals. By starting the output voltage change earlier in the preceding time interval, it is possible to complete the output voltage change within a switching window in the succeeding time interval while concurrently reducing rush current associated with the output voltage change, thus helping to prolong battery life in a device employing the power management circuit.
H03F 3/00 - Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
H04B 1/00 - TRANSMISSION - Details of transmission systems not characterised by the medium used for transmission
G06F 1/00 - ELECTRIC DIGITAL DATA PROCESSING - Details not covered by groups and
H02J 7/00 - Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
H02M 3/156 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
A broadband low noise amplifier (LNA) structure (10) includes a main LNA (12), an offset LNA (14), an input splitter (16), and an output combiner (18). The input splitter (16) is configured to split a radio frequency (RF) input signal into a first RF input signal and a second RF input signal with difference phases, which are fed to the main LNA (12) and the offset LNA (14), respectively. Based on the first RF input signal, the main LNA (12) is configured to provide a first RF output signal, and based on the second RF input signal, the offset LNA (14) is configured to provide a second RF output signal. The output combiner (18) is configured to re-align the first RF output signal and the second RF output signal, and configured to combine the first and second RF output signals to provide a combined RF output signal.
H03F 1/22 - Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively
65.
MICROELECTRONICS PACKAGE WITH VERTICALLY STACKED WAFER SLICES AND PROCESS FOR MAKING THE SAME
The present disclosure relates to a microelectronics package with a vertically stacked structure of two or more wafer slices. A first wafer slice includes a first device region and a through-via connected to the first device region through a first connecting layer. A second wafer slice, which is vertically stacked underneath the first wafer slice, includes a second device region and a top via connected to the second device region through a second connecting layer. The top via in the second wafer slice is in contact with the through-via in the first wafer slice, such that the first device region is electrically connected to the second first device region. Herein, silicon crystal, which has no germanium, nitrogen, or oxygen content, does not exist between the first device region and the second device region.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
66.
MULTI-LEVEL 3D STACKED PACKAGE AND METHODS OF FORMING THE SAME
The present disclosure relates to a multi-level three-dimensional (3D) package with multiple package levels vertically stacked. Each package level includes a redistribution structure and a die section over the redistribution structure. Each die section includes a thinned die that includes substantially no silicon substrate and has a thickness between several micrometers and several tens of micrometers, a mold compound, and an intermediary mold compound. Herein, the thinned die and the mold compound are deposed over the redistribution structure, the mold compound surrounds the thinned die and extends vertically beyond a top surface of the thinned die to define an opening over the thinned die and within the mold compound, the intermediary mold compound resides over the thinned die and fills the opening within the inner mold compound, such that a top surface of the intermediary mold compound and a top surface of the mold compound are coplanar.
H01L 25/10 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices having separate containers
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 23/552 - Protection against radiation, e.g. light
67.
3D PACKAGING WITH SILICON DIE AS THERMAL SINK FOR HIGH-POWER LOW THERMAL CONDUCTIVITY DIES
The present disclosure relates to a three-dimensional (3D) package that has a die-on-die configuration, and includes a first die and at least one second die deposed underneath the first die. The first die includes a back-end-of-line (BEOL) portion, a device region over the BEOL portion, a substrate over the device region, and a substrate tie structure that extends through the device region and at least extends into the substrate. The substrate and the substrate tie structure each has a high thermal conductivity higher than 50W/mK. The at least one second die is configured to be coupled to the BEOL portion of the first die, such that heat generated by the second die can propagate through the BEOL portion and the substrate tie structure, and radiate out of the first substrate.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/03 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes
The present disclosure describes a front-end module (FEM) and a process for making the same. In the disclosed FEM, a thinned flip-chip die, which includes a device region with a metal layer, resides over a module carrier. A mold compound resides over the module carrier, surrounds the thinned flip-chip die, and extends beyond a top surface of the thinned flip-chip die to define an opening over the top surface of the thinned flip-chip die and within the mold compound. A ferrimagnetic portion resides over the top surface of the thinned flip-chip die and within the opening, and a permanent magnetic portion resides over the ferrimagnetic portion and within the opening. Herein, the permanent magnetic portion, the ferrimagnetic portion, and the metal layer of the device region are vertically aligned, and form a circulator vertically stacked with the thinned flip-chip die.
A power management integrated circuit (PMIC) is disclosed. The PMIC is configured to generate multiple voltages during a voltage generation period(s). In embodiments disclosed herein, the voltage generation period(s) is divided into multiple voltage generation intervals. A voltage generation circuit is configured to generate and maintain a respective one of the voltages during a respective one of the voltage generation intervals based on a reference voltage modulated for the respective one of the voltage generation intervals to thereby make the voltages concurrently available during the voltage generation period(s). Moreover, a voltage modulation circuit is configured to modulate the reference voltage in each of the voltage generation intervals based on a single direct-current to direct-current (DC-DC) power inductor. As a result, the PMIC can concurrently support multiple load circuits (e.g., power amplifiers) with significantly reduced footprint.
H03F 1/02 - Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
H02M 3/155 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
H03F 3/19 - High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
H03F 3/21 - Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
70.
PIEZOELECTRIC LAYER ARRANGEMENTS IN ACOUSTIC WAVE DEVICES AND RELATED METHODS
Acoustic wave devices, and particularly piezoelectric layer arrangements in acoustic wave devices and related methods are disclosed. Acoustic wave devices may include a piezoelectric layer on a carrier substrate. The piezoelectric layer is formed with a thickness that is varied or shaped across different portions of the carrier substrate. Different piezoelectric layer thicknesses on a common carrier substrate may be provided for different surface acoustic wave (SAW) filter structures that are formed monolithically, for different sets of resonators within a single filter structure, and for different regions within a single SAW device in one or more of the transverse direction or the propagation directions. Shaping piezoelectric layers may include selectively removing or adding portions of the piezoelectric layer. In this manner, piezoelectric layer thicknesses at different hierarchy levels within SAW devices and filters may be tailored to provide different acoustic resonator properties without requiring separately formed devices on separate substrates.
H03H 3/08 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves
71.
ENVELOPE TRACKING RADIO FREQUENCY FRONT-END CIRCUIT
An envelope tracking (ET) radio frequency (RF) front-end circuit receives a single tracking signal (e.g., Vramp) from a baseband transceiver and generates a plurality of control signals (Vcc). The control signals are created by a multiple control signal generator circuit based on a calculated load estimate for each relevant power amplifier. The load estimate may be calculated from a sensed current and voltage. By providing control signals optimized for loads presented to the power amplifiers, the overall efficiency of the transmitter is improved.
An envelope tracking (ET) integrated circuit (ETIC) operable across wide modulation bandwidth is disclosed. The ETIC includes at least two auxiliary voltage outputs coupled to a high-bandwidth power amplifier circuit that has a lower equivalent capacitance, and thus a higher impedance resonance frequency. The ETIC also includes a pair of ET voltage circuits configured to generate a pair of ET voltages, respectively. To help mitigate potential distortion in the ET voltages, a control circuit is configured to couple the ET voltage circuits exclusively to the auxiliary voltage outputs when the ETIC needs to operate with a high modulation bandwidth (e.g., ≥ 200 MHz). Given the higher impedance resonance frequency of the high-bandwidth power amplifier circuit, it is possible to increase separation between an energy spectrum of a voltage disturbance and an energy spectrum of the high modulation bandwidth, thus helping to reduce the potential distortion in the ET voltages.
An equalizer circuit in an envelope tracking (ET) integrated circuit (ETIC) is disclosed. The ETIC (26) is configured to generate an ET voltage based on a target voltage (VTGT) for amplifying a radio frequency (RF) signal(s). Since the ETIC has inherent impedance and group delay that can cause distortion in the ET voltage, an equalizer circuit (24) is provided in the ETIC to equalize the target voltage prior to generating the ET voltage. Specifically, the equalizer circuit generates an equalized target voltage to offset the inherent impedance and a modified target voltage to mitigate the group delay. Accordingly, the equalizer circuit can output a processed target voltage, which can include the equalized target voltage and/or the modified target voltage, for generating the ET voltage. As a result, it is possible to reduce distortion resulted from the inherent impedance and group delay, especially when the RF signal(s) is modulated in a wide modulation bandwidth.
An acoustic filter providing negative capacitance for use in multiplexers is provided that may include a first resonator and a second resonator. The second resonator may be a three terminal element that includes two sub-resonator elements having opposite polarities that are mechanically coupled such that as one sub-resonator expands, the other contracts. The second resonator may act as a negative capacitance element relative to the first resonator such that the second resonator provides cancelation at specific frequencies. This structure may further reduce the order of an N-multiplexer ladder network and reduce total insertion loss.
A progressive envelope tracking (ET) with delay compensation includes an ET integrated circuit (IC) (ETIC) that is a progressive ETIC that switches between different driver amplifiers having different associated offset voltages based on a tracking signal (e.g., Vramp) from a baseband transceiver. To make sure that desired changes to the offset voltage occur contemporaneously with an input signal for the driver amplifiers, a delay may be added to the input signal for the driver amplifiers. By adding and controlling this delay to the input to the driver amplifiers, the changes to the offset voltage will track the changes to the input signal at the driver amplifiers and overall efficiency of the ETIC may be improved.
A power management circuit operable with multiple supply voltages is disclosed. In embodiments disclosed herein, the power management circuit includes a supply voltage circuit(s) capable of simultaneously generating multiple supply voltages at different voltage levels. The power management circuit also includes multiple envelope tracking (ET) voltage circuits each configured to generate a respective one of multiple ET voltages based on the multiple supply voltages. In this regard, each ET voltage circuit can dynamically use different supply voltages from time to time to generate the respective ET voltage. As a result, it is possible to prevent distortion (e.g., amplitude clipping) in any of the ET voltages, especially when large peak-to-average ratio (PAR) is expected in the ET voltages.
A hybrid bus communication circuit is provided. The hybrid bus communication circuit includes at least two different types of communication buses. The hybrid bus communication circuit also includes a hybrid bridge circuit and several multi-bus slave circuits each coupled to the two different types of communication buses. In a non-limiting example, each of the multi-bus slave circuits may communicate timing critical information via a first type communication bus and non-timing critical information via a second type communication bus. The hybrid bridge circuit is configured to receive a configuration command via the first type communication bus and, accordingly, configure a configuration parameter(s) in any of the multi-bus slave circuits via the second type communication bus. As such, it is possible to make time constrained configuration changes in any of the multi-bus slave circuits without interfering with the timing critical communication conducted via the first type communication bus.
The disclosure is directed to an electronic device with an embedded multi-layered heat slug. The electronic device includes a substrate having a substrate body with a laminate layer. The substrate further includes a heat slug embedded within the substrate body. The heat slug includes a top layer having a first thermal conductivity and a first thermal expansion coefficient, a bottom layer having a second thermal conductivity and a second thermal expansion coefficient, and a core layer having a third thermal conductivity and a third thermal expansion coefficient. The third thermal conductivity is less than the first thermal conductivity and the second thermal conductivity, and the third thermal expansion coefficient is less than the first thermal expansion coefficient and the second thermal expansion coefficient. In certain embodiments, the top layer and the bottom layer comprise copper, and the core layer comprises copper-molybdenum.
A symmetric dual direction coupler has a layout that is controlled such that there is an axis of symmetry between ports and that any switches used within the dual direction coupler are also symmetrical. That is, for a dual direction coupler having a transmitted port, an input port, an isolated port, and a coupled port with switches used to control forward mode or reverse mode for the coupler, the transmitted port and the input port are symmetrical across the axis of symmetry; the isolated port and coupled port are symmetrical across the axis of symmetry; and the switch layout is symmetrical across the axis of symmetry.
H01P 5/18 - Conjugate devices, i.e. devices having at least one port decoupled from one other port consisting of two coupled guides, e.g. directional couplers
H01P 5/04 - Coupling devices of the waveguide type with variable factor of coupling
The disclosure is directed to an electronic device with a solder interconnect and multiple material encapsulant. The electronic device (10) includes a die last assembly with the die (14) assembled to an electronic packaging substrate (12) by a solder interconnect (44). At least a portion of a first dielectric material (46) and the die are milled or ground, with a second dielectric material (60) applied over an exposed portion (52) of the die (14). A shield (80) is then positioned over and electrically insulated from the die. Accordingly, such a configuration reduces a thickness or height of an electronic device with shielding and a die last assembly.
H03H 3/02 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/42 - Fillings or auxiliary members in containers selected or arranged to facilitate heating or cooling
81.
CONTROL METHOD FOR SWITCHES BASED ON DUAL PHASE MATERIALS
The present disclosure relates to a switch system that provides a control method for switches based on dual-phase materials. The disclosed switch system includes a heat resistor, a power management (PM) unit configured to provide a control voltage at a voltage port coupled to the heat resistor, and a phase-change-based switch. Herein, the heat resistor is underneath the phase-change-based switch, and configured to generate heat energy from the control voltage and provide the heat energy to the phase-change-based switch. The phase-change-based switch is capable of being switched on and off by switching between a crystalline phase and an amorphous phase based on the heat energy provided by the heat resistor. The control voltage provided by the PM unit contains waveform information of target heat energy required for switching on and off the phase-change-based switch.
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
H05K 7/20 - Modifications to facilitate cooling, ventilating, or heating
A semiconductor device is disclosed. The semiconductor device has a substrate with a gallium nitride layer (14) disposed over the substrate. A scandium aluminum nitride layer (10) is disposed over the gallium nitride layer. A source (18) is in contact with the gallium nitride layer, and a drain (20) is spaced from the source, wherein the drain is in contact with the gallium nitride layer.
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
H01L 21/338 - Field-effect transistors with a Schottky gate
H01L 29/205 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds in different semiconductor regions
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
83.
MULTI-MODE ANTENNA TUNER CIRCUIT AND RELATED APPARATUS
A multi-mode antenna tuner circuit and related apparatus are provided. The multi-mode antenna tuner circuit can be configured to operate in a low- current mode or a high-power mode. When operating in the high-power mode, the multi-mode antenna tuner circuit can provide full-fledged functionalities and consume a higher amount of current. In contrast, in the low-current mode, the multi-mode antenna tuner circuit provides reduced functionality and consumes a lower amount of current. In this regard, in a wireless communication apparatus employing multiple multi-mode antenna tuner circuits, it is possible to opportunistically configure some multi-mode antenna tuner circuits to operate in the low-current mode based on an operating environment (e.g., frequency band, location, etc.) and internal state (e.g., battery level, signal strength, etc.) of the wireless communication apparatus. As a result, it may be possible to reduce consumption and heat dissipation without compromising performance of the wireless communication apparatus.
A connector assembly and method of attaching the same to one or more biosensor module boards. The connector assembly includes a body portion defining a first surface and a second surface opposite the first surface. The connector assembly also includes a coaxial RF connector positioned in the body portion and extending between the first surface and the second surface. The coaxial RF connector includes a ground ring, an RF pin positioned within the ground ring, and dielectric therebetween. The connector assembly is configured to be coupled to an RF detection board such that the coaxial RF connector is operably coupled thereto. The connector assembly is also configured to be connected to a biosensor module board such that the coaxial RF connector is operably connected thereto.
A solid mount resonator sensor has a substrate. An anti-reflector stack is disposed proximate the substrate. The anti-reflector stack includes one or more acoustic interference layers. A first electrode is disposed proximate the anti-reflector stack. A second electrode having a first surface facing towards the first electrode and an opposing second surface facing away from the first electrode. A substantially quarter-wave piezoelectric material layer is disposed between the first and second electrodes.
Disclosed is a tunable inductor device having a substrate, a planar spiral conductor having a plurality of spaced-apart turns disposed over the substrate, and a phase change switch (PCS) having a patch of a phase change material (PCM) disposed over the substrate between and in contact with a pair of adjacent segments of the plurality of spaced-apart turns, wherein the patch of the PCM is electrically insulating in an amorphous state and electrically conductive in a crystalline state. The PCS further includes a thermal element disposed adjacent to the patch of PCM, wherein the thermal element is configured to maintain the patch of the PCM to within a first temperature range until the patch of the PCM converts to the amorphous state and maintain the patch of the PCM within a second temperature range until the first patch of PCM converts to the crystalline state.
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
H01L 27/24 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier
H01F 21/12 - Variable inductances or transformers of the signal type discontinuously variable, e.g. tapped
A fluidic device and a method of preventing isolation material from bleed-out therein is described herein. The fluidic device includes a bulk acoustic wave resonator structure defining at least one surface area region on which a functionalization material is disposed and the resonator structure includes a repelling area. The fluidic device also includes isolation material disposed on the resonator structure and away from the at least one surface area region. The repelling area is configured to prevent the isolation material from extending into the at least one surface area region. Further, an electronic board may be operably attached to the resonator structure and the isolation material may be disposed in a gap therebetween to electrically isolate electrical contacts and form a fluidic channel.
G01N 33/536 - Immunoassay; Biospecific binding assay; Materials therefor with immune complex formed in liquid phase
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 41/04 - SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR - Details thereof - Details of piezo-electric or electrostrictive elements
H03B 5/32 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator
Disclosed is a reconfigurable transistor device having a substrate, a plurality of first transistor fingers disposed in a first region over the substrate, and a phase change switch (PCS) having a patch of a phase change material (PCM) disposed over the substrate in a second region to selectively couple a first set of the plurality of first transistor fingers to a bus, wherein the patch of the PCM is electrically insulating in an amorphous state and electrically conductive in a crystalline state. The PCS further includes a thermal element disposed adjacent to the patch of PCM, wherein the first thermal element is configured to maintain the patch of the PCM to within a first temperature range until the patch of the PCM converts to the amorphous state and maintain the patch of the PCM within a second temperature range until the first patch of PCM converts to the crystalline state.
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
H01L 27/24 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier
89.
PIEZOELECTRIC BULK LAYERS WITH TILTED C-AXIS ORIENTATION AND METHODS FOR MAKING THE SAME
A structure includes a substrate including a wafer or a portion thereof; and a piezoelectric bulk material layer comprising a first portion deposited onto the substrate and a second portion deposited onto the first portion, the second portion comprising an outer surface having a surface roughness (Ra) of 4.5 nm or less. Methods for depositing a piezoelectric bulk material layer include depositing a first portion of bulk layer material at a first incidence angle to achieve a predetermined c-axis tilt, and depositing a second portion of the bulk material layer onto the first portion at a second incidence angle that is smaller than the first incidence angle. The second portion has a second c-axis tilt that substantially aligns with the first c-axis tilt.
An envelope tracking (ET) power amplifier apparatus is provided. The multi-mode power amplifier apparatus includes a pair of power amplifiers configured to amplify a radio frequency (RF) signal(s) and an output circuit that outputs the amplified RF signal(s) to a signal output(s). In examples disclosed herein, a control circuit can cause the multi-mode power amplifier apparatus to operate in different power management modes by changing a load impedance coupled to the signal output(s). In a non-limiting example, the control circuit can change a power management mode of the multi-mode power amplifier apparatus based on modulation bandwidth of the RF signal(s). As a result, the multi-mode power amplifier apparatus can operate across a wide range of modulation bandwidth without compromising efficiency and performance.
A multi-amplifier envelope tracking (ET) apparatus is provided. The multi- amplifier ET apparatus includes an ET integrated circuit (ETIC). The ETIC includes a first voltage circuit that generates the first ET voltage based on a first supply voltage and a first time-variant target voltage. The ETIC also includes a second voltage circuit that generates the second ET voltage based on a second supply voltage and a second time-variant target voltage. In embodiments disclosed herein, the ETIC is configured to determine the first supply voltage and the second supply voltage in accordance to the first time-variant target voltage and the second time-variant target voltage, respectively. As a result, both the first and the second voltage circuits can operate with optimal efficiency, thus helping to improve overall operating efficiency of the multi-amplifier ET apparatus.
A method of manufacturing a MEMS device. The MEMS device has a cavity in which a beam will move to change the capacitance of the device. After most of the device build-up has occurred, sacrificial material is removed to free the beam within the MEMS device cavity. Thereafter, exposed ruthenium contacts are exposed to fluorine to either: dope exposed ruthenium and reduce surface adhesive forces, form fluorinated Self-Assembled Monolayers on the exposed ruthenium surfaces, deposit a nanometer passivating film on exposed ruthenium, or alter surface roughness of the ruthenium. Due to the fluorine treatment, low resistance, durable contacts are present, and the contacts are less susceptible to stiction events.
A reconfigurable amplifier configured to decrease radio frequency (RF) signal distortion and increase dynamic range is disclosed. The reconfigurable amplifier includes an amplifier having an RF signal input, an RF signal output, and a bias signal input. A distortion detection network has a detector input coupled to the RF signal output and a detector output, wherein the distortion detector network is configured to generate a detection signal that is proportional to distortion at the RF signal output. A bias controller has a detection signal input coupled to the detector output and a bias output coupled to the bias signal input. The bias controller is configured to generate a bias signal that dynamically shifts level at the bias output to reduce the distortion at the RF signal output in response to the detection signal.
H03F 1/02 - Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
H03F 1/22 - Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively
H03F 3/193 - High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only with field-effect devices
H03F 1/56 - Modifications of input or output impedances, not otherwise provided for
H03F 1/32 - Modifications of amplifiers to reduce non-linear distortion
H03F 1/34 - Negative-feedback-circuit arrangements with or without positive feedback
H03F 3/21 - Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
A multi-mode power management apparatus is provided. In embodiments disclosed herein, the multi-mode power management apparatus can be configured to operate in different power management modes across a wide range of modulation bandwidth (e.g., 80 KHz to over 200 MHz). The multi-mode power management apparatus includes a power management integrated circuit (PMIC) and an envelope tracking integrated (ET) circuit (ETIC), which are implemented in separate dies. The PMIC is configured to generate a low- frequency current and a low-frequency voltage. The ETIC is configured to generate a pair of ET voltages. Depending on the power management mode, the multi-mode power management apparatus can selectively output one or more of the ET voltages and the low-frequency voltage to different stages (e.g., driver stage and output stage) of a power amplifier circuit, thus helping to maintain optimal efficiency and linearity of the power amplifier circuit across the wide range of modulation bandwidth.
A method of manufacturing a MEMS device, wherein the MEMS device has a cavity in which a beam will move to change the capacitance of the device. After most of the device build-up has occurred, sacrificial material is removed to free the beam within the MEMS device cavity. Thereafter, exposed ruthenium contacts are etched back with an etchant comprising chlorine to remove the top surface of both the top and bottom contacts. Due to this etch back process, low contact resistance can be achieved with less susceptibility to stiction events. Stiction performance can be further improved by conditioning the ruthenium contacts in a fluorine based plasma. The fluorine based plasma process, or fluorine treatment, can be performed prior to or after etch-back process of the ruthenium contacts.
An aperture antenna tuning technique is used in an antenna array to improve the performance and, therefore, enhance the overall system efficiency for wireless devices. The aperture tuning occurs by using an aperture tuner to change the phase response of the antenna array radiation pattern. The aperture tuning improves the signal to noise ratio (SNR) by enhancing an array radiation pattern in a desired direction.
H01Q 5/378 - Combination of fed elements with parasitic elements
H01Q 9/42 - Resonant antennas with feed to end of elongated active element, e.g. unipole with folded element, the folded parts being spaced apart a small fraction of the operating wavelength
H01Q 21/29 - Combinations of different interacting antenna units for giving a desired directional characteristic
H01Q 21/06 - Arrays of individually energised antenna units similarly polarised and spaced apart
Laminate structures and configurations of fiducials for laminates structures for electronic devices are disclosed. Fiducials are formed in laminate structures to provide increased visibility and contrast, thereby improving detection of the fiducials with optical detection equipment of automated machines commonly used in the electronics industry. Fiducials are disclosed that are defined by openings in laminate structures that extend to depths within the laminate structures to provide sufficient contrast. Openings for fiducials may be arranged to extend through multiple metal layers and dielectric layers of the laminate structures. The fiducials may be formed by laser drilling or other subtractive processing techniques. Fiducials as disclosed herein may be coated with additional layers or coatings, such as a metal coating that includes an electromagnetic shield for electronic devices, and the fiducials are configured with sufficient visibility and contrast to remain detectable through the additional layers or coatings.
H05K 3/34 - Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
H05K 3/00 - Apparatus or processes for manufacturing printed circuits
98.
RF SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
The present disclosure relates to a radio frequency device that includes a mold device die and a multilayer redistribution structure underneath the mold device die. The mold device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion, a barrier layer, and a first mold compound. The FEOL portion includes isolation sections and an active layer surrounded by the isolation sections. The barrier layer formed of silicon nitride resides over the active layer and top surfaces of the isolation sections. The first mold compound resides over the barrier layer. Herein, silicon crystal does not exist between the first mold compound and the active layer. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the mold device die.
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
The present disclosure relates to a radio frequency (RF) device that includes a mold device die and a multilayer redistribution structure underneath the mold device die. The mold device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion, and a first mold compound. The FEOL portion includes an active layer, a contact layer, and isolation sections. Herein, the active layer and the isolation sections reside over the contact layer, and the active layer is surrounded by the isolation sections. The first mold compound resides over the active layer without silicon crystal, which has no germanium content, in between. The multilayer redistribution structure includes redistribution interconnections and a number of bump structures that are at bottom of the multilayer redistribution structure and electrically coupled to the mold device die via the redistribution interconnections.
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
The present disclosure relates to a radio frequency (RF) device that includes a mold device die and a multilayer redistribution structure underneath the mold device die. The mold device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion, and a first mold compound. The FEOL portion includes an active layer formed from a strained silicon epitaxial layer, in which a lattice constant is greater than 5.461 at a temperature of 300K. The first mold compound resides over the active layer. Herein, silicon crystal does not exist between the first mold compound and the active layer. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the mold device die.
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
patents
