A delay-compensating power management circuit is provided. The power management circuit includes a power management integrated circuit (PMIC) configured to generate a time-variant voltage(s) based on a time-variant target voltage(s) for amplifying an analog signal(s) associated with a time-variant power envelope(s). A voltage processing circuit is provided in the power management circuit to determine a temporal offset, which can be positive or negative, between the time-variant power envelope(s) and the time-variant target voltage(s). Accordingly, the voltage processing circuit modifies the time-variant target voltage(s) to substantially reduce the determined temporal offset and thereby realign the time-variant target voltage(s) with the time-variant power envelope(s). By realigning the time variant target voltage(s) with the time-variant power envelope(s), it is possible to align the time-variant voltage(s) with the time-variant power envelope(s) to reduce distortions (e.g., amplitude clipping) during amplification of the analog signal.
An antenna in a lightbulb may include a conductive plane (e.g., a ground plane) that includes an edge-enabled void antenna (EEVA) with the EEVA including a corresponding edge-enabled void isolator (EEVI). Use of both the EEVA and the EEVI allows for a small antenna footprint for incorporation into a lightbulb. Optionally, two EEVAs, each with a corresponding EEVI may be used. Various arrangements are provided to illustrate possible compromises between structural integrity and cooling. Further, by using two EEVAs, diversity reception and transmission is possible, increasing the utility of the lightbulb by expanding directionality of the transmission/reception and/or improving communication through spatial diversity.
H01Q 1/44 - ANTENNAS, i.e. RADIO AERIALS - Details of, or arrangements associated with, antennas using equipment having another main function to serve additionally as an antenna
H01Q 1/02 - Arrangements for de-icing; Arrangements for drying-out
H01Q 1/36 - Structural form of radiating elements, e.g. cone, spiral, umbrella
A structure includes a substrate including a wafer or a portion thereof; and a piezoelectric bulk material layer comprising a first portion deposited onto the substrate and a second portion deposited onto the first portion, the second portion comprising an outer surface having a surface roughness (Ra) of 4.5 nm or less. Methods for depositing a piezoelectric bulk material layer include depositing a first portion of bulk layer material at a first incidence angle to achieve a predetermined c-axis tilt, and depositing a second portion of the bulk material layer onto the first portion at a second incidence angle that is smaller than the first incidence angle. The second portion has a second c-axis tilt that substantially aligns with the first c-axis tilt.
C23C 14/00 - Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
H03H 3/04 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks for obtaining desired frequency or temperature coefficient
Embodiments of an amplifier and method of operating an amplifier are disclosed. In some embodiments, the amplifier includes an active device having an input terminal and an output terminal. A harmonic termination is coupled in shunt with respect to the input terminal or the output terminal, wherein the harmonic termination includes a capacitor-shunt inductor-capacitor or similar network. In this manner, the harmonic terminator shapes the waveform of the RF signal without introducing large amounts of capacitance at the fundamental/center operating frequency.
An edge enabled void isolator (EEVI) for antennas is provided. In particular, two or more antennas are separated from one another by respective EEVI to provide isolation between the antennas. This isolation allows the antennas to be placed in close proximity, keeping the footprint of the antenna system relatively small for ease of use in small wireless devices. While two monopole antennas are specifically contemplated, the disclosure may be extended to more than two antennas and these antennas may be monopole, dipole, F, or the like.
An apparatus including at least one deflecting element and at least one strain sensor is configured for determining relative velocity, fluid flow, or angle of attack between a fluid and a body having a fluid-contacting surface and an opposing non-fluid-contacting surface. The deflecting element is joined to the body and extends from the fluid-contacting surface into the fluid, while the strain sensor is coupled to the non-fluid-contacting surface and is configured to detect strain imparted on the body by deflection of the at least one deflecting element. An output signal of the at least one strain sensor permits calculation of at least one of relative velocity, fluid flow, or angle of attack between the fluid and the body. By measuring deflection of a surface of the body, the at least one strain sensor may be mounted on or along the non-fluid-contacting surface where the environment is controllable, such that the sensor is not subject to deleterious environmental effects.
G01P 5/04 - Measuring speed of fluids, e.g. of air stream; Measuring speed of bodies relative to fluids, e.g. of ship, of aircraft by measuring forces exerted by the fluid on solid bodies, e.g. anemometer using deflection of baffle-plates
G01F 1/20 - Measuring the volume flow or mass flow of fluid or fluent solid material wherein the fluid passes through a meter in a continuous flow by using mechanical effects by detection of dynamic effects of the flow
G01F 15/02 - Compensating or correcting for variations in pressure, density, or temperature
7.
RECONFIGURABLE ACOUSTIC WAVE RESONATORS AND FILTERS
Reconfigurable bulk acoustic wave (BAW) devices include one or more ferroelectric materials as the transduction layer(s). A polarization state of at least one of the ferroelectric material(s) is adjusted by applying a bias voltage across electrodes of the BAW device. The application of the bias voltage can change one or more properties of the ferroelectric material, which in turn may change a response of the BAW device.
The present disclosure relates to filter circuitry, which includes a first node and a second node, a series resonator coupled between the first node and the second node, and a compensation circuit coupled in parallel with the series resonator and located between the first node and the second node. Herein, the compensation circuit includes a tunable acoustic resonator with at least one transduction structure. The at least one transduction structure includes at least one ferroelectric material, and polarization of the at least one ferroelectric material varies with an electric field across the at least one ferroelectric material. Upon adjusting a direct current voltage applied to the tunable acoustic resonator, the compensation circuit is capable of providing a variable negative equivalent capacitance to at least partially cancel out an equivalent capacitance presented by the series resonator between the first node and the second node.
Methods for polishing bulk silicon are disclosed. In one aspect, mechanical polishing is facilitated by cyclically alternating between a silicon reactive slurry and deionized water while a mechanical polishing head operates on a surface. In exemplary aspects, the polishing head is polishing a bulk silicon carrier wafer to expose a backside of a radio frequency (RF) complementary metal oxide semiconductor (CMOS) switch, although other semiconductors may also benefit from exemplary aspects of the present disclosure. While the silicon slurry is present, a reaction between the bulk silicon and the slurry takes place allowing the polishing head to remove the bulk silicon. The deionized water interrupts this reaction and helps prevent overpolishing which might otherwise damage the device.
H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching
B24B 7/22 - Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor characterised by a special design with respect to properties of the material of non-metallic articles to be ground for grinding inorganic material, e.g. stone, ceramics, porcelain
An acoustic transformer in a transmitter chain is disclosed. In one aspect, a differential power amplifier may produce a differential signal that is provided to a first transformer. A differential output of this first transformer is provided to an acoustic transformer that provides a single ended output signal for use by an acoustic filter. By making the second transformer an acoustic transformer, the second transformer may be integrated into the same circuitry that forms the acoustic filter, thereby simplifying the die. Further, the acoustic transformer may be tuned if ferroelectric resonators are used, which provides strong out-of-band signal cancelation.
A ferroelectric acoustic resonator structure is provided. The tunable ferroelectric acoustic resonator structure includes a pair of ferroelectric acoustic resonator networks coupled in parallel between a signal input and a signal output. The ferroelectric acoustic resonator networks are tuned by a pair of pulse voltages to resonate in a desired series resonance frequency. However, the pair of pulse voltages can change an equivalent capacitance to therefore cause a parallel resonance frequency of the tunable ferroelectric acoustic resonator structure to shift. Herein, the pair of pulse voltages are determined to cause one of the ferroelectric acoustic resonator networks to increase the equivalent capacitance and to cause another one of the ferroelectric acoustic resonator networks to decrease the equivalent capacitance by an equal amount. As a result, it is possible to keep the overall equivalent capacitance, and therefore the parallel resonance frequency, of the tunable ferroelectric acoustic resonator structure unchanged.
This disclosure describes methods and devices that assist in forming biosensors. Specifically, features that align solutions containing molecules to be immobilized on biosensors. A retaining structure may be disposed at least partially around a target surface of a substrate. A resonating structure may be disposed on the target surface. A droplet of functionalized material may be disposed on the resonating structure and the target surface, which may be auto-aligned and retained by the retaining structure on the target surface to consistently cover the resonating structure.
G01N 29/22 - Investigating or analysing materials by the use of ultrasonic, sonic or infrasonic waves; Visualisation of the interior of objects by transmitting ultrasonic or sonic waves through the object - Details
The present disclosure relates to a bulk acoustic wave (BAW) resonator that includes a bottom electrode, a piezoelectric layer over the bottom electrode, and a top electrode structure with a top electrode and the dual-step BO ring structure. Herein, the dual-step BO structure is formed over the piezoelectric layer and about a periphery of the top electrode structure, such that a central portion of the piezoelectric layer is not covered by the dual-step BO structure. The dual-step BO structure is formed of an oxide material and includes an inner BO ring with a first height and an outer BO ring with a second height that is larger than the first height, such that the dual-step BO structure decreases in height toward the central portion of the piezoelectric layer. The top electrode is formed over the central portion of the piezoelectric layer and extends over the dual-step BO structure.
The present disclosure relates to a bulk acoustic wave (BAW) resonator that includes a bottom electrode, a top electrode structure with a border ring (BO) structure, a piezoelectric layer sandwiched between the bottom electrode and the top electrode, and a reflector with a high acoustic impedance layer embedded in a low acoustic impedance region. Herein, the BO structure is formed about a periphery of the top electrode structure and defines a BO region of the BAW resonator. The high acoustic impedance layer is vertically underneath the bottom electrode and is separated from the bottom electrode by a first portion of the low acoustic impedance region. A width of the first high acoustic impedance layer is smaller than a width of the top electrode structure, such that the first high acoustic impedance layer does not extend completely through the BO region of the BAW resonator.
A field effect transistor (FET) transconductance device with varying gate lengths is disclosed. In one aspect, the varying effective gate lengths are used in a differential architecture to obtain linear even and odd order operation simultaneously. In a particular aspect, the effective gate lengths may be varied according to a differential Multi-Tanh-like architecture. This variation of effective gate lengths enables a compact implementation particularly as compared to varying gate width or emitter areas while also providing linear even and odd order operation simultaneously.
A circuit package with improved thermal management is disclosed. In one aspect, a ceramic insert is provided within a package having heat-producing circuitry thereon. The ceramic insert replaces traditional laminate inserts and provides a better thermal path to remove heat from leads and/or traces within the package. More particularly, the ceramic insert more readily transfers and/or dissipates heat that might otherwise accumulate at an output port where a solder junction may be made to couple the output port to external elements.
A passive acoustic sensor circuit and related wireless sensing system are provided. The passive acoustic sensor circuit is configured to induce an electrical current in response to receiving a radio frequency signal. The passive acoustic sensor circuit includes a sensor circuit, which can detect a sensory event (e.g., a touch or key press) and cause a variation in the electrical current in response to the sensory event. In contrast, the sensor circuit will not cause the variation in the electrical current in absence of the sensory event. In this regard, the presence or absence of the current variation, which can be detected remotely and wirelessly, will serve as an indication of the sensory event. By detecting the current variation remotely and wirelessly, it is possible to reduce physical wiring in an electronic device (e.g., smartphone, smartwatch, etc.) to help reduce design and manufacturing complexity of the electronic device.
G01H 11/06 - Measuring mechanical vibrations or ultrasonic, sonic or infrasonic waves by detecting changes in electric or magnetic properties by electric means
18.
VEHICLE-MOUNTED RANGING SYSTEM AND METHOD OF OPERATING THE SAME
Disclosed is a vehicle-mounted ranging system and method. The vehicle-mounted ranging system has a communication transceiver configured to wirelessly communicate with at least one external communication transceiver and a plurality of ultra-wideband (UWB) transceivers configured to transmit and receive ranging pulses to and from at least one external UWB transceiver associated with the at least one external communication transceiver. A controller is interfaced between the communication transceiver and the plurality of UWB transceivers. The controller is configured to communicate with the associated at least one external communication transceiver to schedule transmission of ranging pulses between the plurality of UWB transceivers and the at least one external UWB transceiver and to calculate ranges between each of the plurality of UWB transceivers and the at least one external UWB transceiver based upon time-of-arrival of ranging pulses transmitted between the plurality of UWB ranging transceivers and the at least one external UWB transceiver.
The present disclosure relates to a three-dimensional (3D) package that has a die-on-die configuration, and includes a first die and at least one second die deposed underneath the first die. The first die includes a back-end-of-line (BEOL) portion, a device region over the BEOL portion, a substrate over the device region, and a substrate tie structure that extends through the device region and at least extends into the substrate. The substrate and the substrate tie structure each has a high thermal conductivity higher than 50 W/mK. The at least one second die is configured to be coupled to the BEOL portion of the first die, such that heat generated by the second die can propagate through the BEOL portion and the substrate tie structure, and radiate out of the first substrate.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
A reinforcement learning receiver front-end (RL-RXFE) is disclosed having a low-noise amplifier (LNA) with adjustable supply voltage and adjustable bias voltages, a frequency selective limiter (FSL) coupled to the LNA and configured to attenuate undesired radio frequency (RF) bands and for sensing RF band power, and a combination of an analog-to-digital converter configured to convert an RF signal amplified by the LNA to a digital signal, a digital signal processor configured to generate spectrum information from the digital signal, and a baseband distortion by-product detector/sensor configured to generate distortion by-product information, and LNA dynamic information. A reinforcement learning processing circuitry receives and uses this information to perform reinforcement learning and to output control signals to the FSL and the LNA to maximize linearity and efficiency.
An echo-cancelling acoustic delay circuit, which can be provided in a wireless device operable to detect a nearby object, is disclosed. Given the close proximity of the object, an echo of the emitted pulse(s) may be reflected instantaneously toward the antenna to potentially overlap with the emitted pulse(s), thus causing difficulty in detecting the reflected pulse(s). In this regard, the echo-cancelling acoustic delay circuit is provided in the wireless device to add a temporal delay in the emitted pulse(s) and the reflected pulse(s) to prevent the reflected pulse(s) from overlapping with the emitted pulse(s). In addition, the echo-cancelling acoustic delay circuit is further configured to cancel a reflection echo(s) in the emitted pulse(s) and the reflected pulse(s), thus allowing the wireless device to accurately receive the reflected pulse(s) to thereby detect the nearby object.
G01S 7/28 - RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES - Details of systems according to groups , , of systems according to group - Details of pulse systems
H04B 1/7163 - Spread spectrum techniques using impulse radio
G01S 13/02 - Systems using reflection of radio waves, e.g. primary radar systems; Analogous systems
The present disclosure relates to a fabricating procedure of a radio frequency device, in which a precursor wafer including active layers, SiGe layers, and a silicon handle substrate is firstly provided. Each active layer is formed from doped epitaxial silicon and underneath a corresponding SiGe layer. The silicon handle substrate is over each SiGe layer. Next, the silicon handle substrate is removed completely, and the SiGe layer is removed completely. An etch passivation film is then formed over each active layer. Herein, removing each SiGe layer and forming the etch passivation film over each active layer utilizes a same reactive chemistry combination, which reacts differently to the SiGe layer and the active layer. The reactive chemistry combination is capable of producing a variable performance, which is an etching performance of the SiGe layer or a forming performance of the etch passivation film over the active layer.
A power management integrated circuit (PMIC) is disclosed. The PMIC is configured to generate multiple voltages during a voltage generation period(s). In embodiments disclosed herein, the voltage generation period(s) is divided into multiple voltage generation intervals. A voltage generation circuit is configured to generate and maintain a respective one of the voltages during a respective one of the voltage generation intervals based on a reference voltage modulated for the respective one of the voltage generation intervals to thereby make the voltages concurrently available during the voltage generation period(s). Moreover, a voltage modulation circuit is configured to modulate the reference voltage in each of the voltage generation intervals based on a single direct-current to direct-current (DC-DC) power inductor. As a result, the PMIC can concurrently support multiple load circuits (e.g., power amplifiers) with significantly reduced footprint.
A broadband low noise amplifier (LNA) structure (10) includes a main LNA (12), an offset LNA (14), an input splitter (16), and an output combiner (18). The input splitter (16) is configured to split a radio frequency (RF) input signal into a first RF input signal and a second RF input signal with difference phases, which are fed to the main LNA (12) and the offset LNA (14), respectively. Based on the first RF input signal, the main LNA (12) is configured to provide a first RF output signal, and based on the second RF input signal, the offset LNA (14) is configured to provide a second RF output signal. The output combiner (18) is configured to realign the first RF output signal and the second RF output signal, and configured to combine the first and second RF output signals to provide a combined RF output signal.
This disclosure relates to a cooling apparatus and a method for cooling semiconductor devices, wherein the cooling apparatus is disposed over a top surface and a bottom surface of a printed circuit board. The disclosed cooling apparatus comprises a printed circuit board, a first semiconductor device comprising a first thermal pad and mounted on a top surface of the printed circuit, a second semiconductor device comprising a second thermal pad and mounted on a bottom surface of the printed circuit, a first heat sink, a first thermal interface structure thermally coupled between the first thermal pad and the first heat sink, a second heat sink, and a second thermal interface structure thermally coupled between the second thermal pad and the second heat sink.
H01L 23/40 - Mountings or securing means for detachable cooling or heating arrangements
H01L 25/11 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group
H05K 1/18 - Printed circuits structurally associated with non-printed electric components
H05K 7/20 - Modifications to facilitate cooling, ventilating, or heating
H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
26.
MICROELECTRONICS PACKAGE WITH VERTICALLY STACKED WAFER SLICES AND PROCESS FOR MAKING THE SAME
The present disclosure relates to a microelectronics package with a vertically stacked structure of two or more wafer slices. A first wafer slice includes a first device region and a through-via connected to the first device region through a first connecting layer. A second wafer slice, which is vertically stacked underneath the first wafer slice, includes a second device region and a top via connected to the second device region through a second connecting layer. The top via in the second wafer slice is in contact with the through-via in the first wafer slice, such that the first device region is electrically connected to the second first device region. Herein, silicon crystal, which has no germanium, nitrogen, or oxygen content, does not exist between the first device region and the second device region.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
27.
WIRELESS DEVICE OPERABLE TO DETECT A NEARBY OBJECT
A wireless device operable to detect a nearby object is disclosed. Herein, an object is considered a nearby object when a roundtrip propagation duration of a pulse(s) between an antenna and the object is less than two nanoseconds (2 ns). Given the close proximity of the object, an echo of the emitted pulse(s) may be reflected instantaneously toward the antenna to potentially overlap with the emitted pulse(s), thus causing difficulty in detecting the reflected pulse(s). In this regard, in embodiments disclosed herein, an acoustic delay circuit is provided in the wireless device to add a temporal delay in the emitted pulse(s) and the reflected pulse(s) to prevent the reflected pulse(s) from overlapping with the emitted pulse(s). As a result, the wireless device can accurately receive the reflected pulse(s) to thereby detect the nearby object.
G01S 7/28 - RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES - Details of systems according to groups , , of systems according to group - Details of pulse systems
G01S 13/02 - Systems using reflection of radio waves, e.g. primary radar systems; Analogous systems
G01S 13/04 - Systems determining presence of a target
28.
POWER MANAGEMENT APPARATUS OPERABLE WITH MULTIPLE CONFIGURATIONS
A power management apparatus operable with multiple configurations is disclosed. In embodiments disclosed herein, the power management apparatus can be configured to concurrently generate multiple modulated voltages based on a configuration including a single power management integrated circuit (PMIC) or a configuration including a PMIC and a distributed PMIC. Regardless of the configuration, the power management apparatus employs a single switcher circuit, wherein multiple reference voltage circuits are configured to share a multi-level charge pump (MCP). As a result, it is possible to reduce footprint of the power management apparatus while improving isolation between the multiple modulated voltages.
H03F 1/02 - Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
H03F 3/21 - Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
H02M 3/07 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion
29.
MULTI-LEVEL 3D STACKED PACKAGE AND METHODS OF FORMING THE SAME
The present disclosure relates to a multi-level three-dimensional (3D) package with multiple package levels vertically stacked. Each package level includes a redistribution structure and a die section over the redistribution structure. Each die section includes a thinned die that includes substantially no silicon substrate and has a thickness between several micrometers and several tens of micrometers, a mold compound, and an intermediary mold compound. Herein, the thinned die and the mold compound are deposed over the redistribution structure, the mold compound surrounds the thinned die and extends vertically beyond a top surface of the thinned die to define an opening over the thinned die and within the mold compound, the intermediary mold compound resides over the thinned die and fills the opening within the inner mold compound, such that a top surface of the intermediary mold compound and a top surface of the mold compound are coplanar.
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
30.
TEMPERATURE COEFFICIENT OF OFFSET COMPENSATION FOR RESISTANCE BRIDGE
Systems and methods for temperature coefficient of offset compensation for a resistance bridge are disclosed. In one aspect, one or more current sources are added in parallel to resistance elements within a resistance bridge. The current source(s) may be selectively switched on and adjusted by a control circuit based on readings from a temperature sensor. In this fashion, the temperature induced variations in the resistance may be canceled or corrected allowing for better performance of the resistance bridge.
G01L 1/22 - Measuring force or stress, in general by making use of electrokinetic cells, i.e. liquid-containing cells wherein an electrical potential is produced or varied upon the application of stress using resistance strain gauges
G01L 9/06 - Measuring steady or quasi-steady pressure of a fluid or a fluent solid material by electric or magnetic pressure-sensitive elements; Transmitting or indicating the displacement of mechanical pressure-sensitive elements, used to measure the steady or quasi-steady pressure of a fluid or fluent solid material, by electric or magnetic means by making use of variations in ohmic resistance, e.g. of potentiometers of piezo-resistive devices
G01L 9/04 - Measuring steady or quasi-steady pressure of a fluid or a fluent solid material by electric or magnetic pressure-sensitive elements; Transmitting or indicating the displacement of mechanical pressure-sensitive elements, used to measure the steady or quasi-steady pressure of a fluid or fluent solid material, by electric or magnetic means by making use of variations in ohmic resistance, e.g. of potentiometers of resistance strain gauges
31.
EQUALIZER CIRCUIT IN AN ENVELOPE TRACKING INTEGRATED CIRCUIT
An equalizer circuit in an envelope tracking (ET) integrated circuit (ETIC) is disclosed. The ETIC (26) is configured to generate an ET voltage based on a target voltage (VTGT) for amplifying a radio frequency (RF) signal(s). Since the ETIC has inherent impedance and group delay that can cause distortion in the ET voltage, an equalizer circuit (24) is provided in the ETIC to equalize the target voltage prior to generating the ET voltage. Specifically, the equalizer circuit generates an equalized target voltage to offset the inherent impedance and a modified target voltage to mitigate the group delay. Accordingly, the equalizer circuit can output a processed target voltage, which can include the equalized target voltage and/or the modified target voltage, for generating the ET voltage. As a result, it is possible to reduce distortion resulted from the inherent impedance and group delay, especially when the RF signal(s) is modulated in a wide modulation bandwidth.
A signal processing apparatus and related transceiver circuit are disclosed. The signal processing apparatus includes a power amplifier circuit and a transceiver circuit. The transceiver circuit is configured to generate multiple composite signals each having a respective one of multiple inverted intermodulation product terms. The power amplifier circuit includes multiple power amplifiers each configured to amplify a respective one of the composite signals. By including the inverted intermodulation product terms in the composite signals prior to amplifying the composite signals, it is possible to offset intermodulation product terms inherently caused by nonlinear responses of the power amplifiers, thus helping to reduce spectrum degradation in the signal processing apparatus.
A power management circuit operable with multiple supply voltages is disclosed. In embodiments disclosed herein, the power management circuit includes a supply voltage circuit(s) capable of simultaneously generating multiple supply voltages at different voltage levels. The power management circuit also includes multiple envelope tracking (ET) voltage circuits each configured to generate a respective one of multiple ET voltages based on the multiple supply voltages. In this regard, each ET voltage circuit can dynamically use different supply voltages from time to time to generate the respective ET voltage. As a result, it is possible to prevent distortion (e.g., amplitude clipping) in any of the ET voltages, especially when large peak-to-average ratio (PAR) is expected in the ET voltages.
Systems and methods for reduced interpath interference for ultrawideband (UWB) wireless communication are disclosed. In one aspect, a wireless communication device employs a systematic and non-random pulse-hopping scheme to introduce variable distances between pulses to reduce collision rates from interpath interference. In exemplary aspects, the scheme optimizes avoidance of collision rates for distances between paths of up to thirty nanoseconds (30 ns). The use of an optimized grid will be stable regardless of position of the user, thereby avoiding transmission drops and improving the user experience.
An envelope tracking (ET) integrated circuit (ETIC) operable across wide modulation bandwidth is disclosed. The ETIC includes at least two auxiliary voltage outputs coupled to a high-bandwidth power amplifier circuit that has a lower equivalent capacitance, and thus a higher impedance resonance frequency. The ETIC also includes a pair of ET voltage circuits configured to generate a pair of ET voltages, respectively. To help mitigate potential distortion in the ET voltages, a control circuit is configured to couple the ET voltage circuits exclusively to the auxiliary voltage outputs when the ETIC needs to operate with a high modulation bandwidth (e.g., ≥200 MHz). Given the higher impedance resonance frequency of the high-bandwidth power amplifier circuit, it is possible to increase separation between an energy spectrum of a voltage disturbance and an energy spectrum of the high modulation bandwidth, thus helping to reduce the potential distortion in the ET voltages.
H03F 3/24 - Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
H03F 3/393 - Dc amplifiers with modulator at input and demodulator at output; Modulators or demodulators specially adapted for use in such amplifiers with semiconductor devices only with field-effect devices
H03F 3/50 - Amplifiers in which input is applied to, or output is derived from, an impedance common to input and output circuits of the amplifying element, e.g. cathode follower
A multi-passband frequency acoustic structure is provided. The multi-passband frequency acoustic structure includes an acoustic resonator structure configured to pass a signal to a signal output in a built-in series resonance frequency (a.k.a. built-in passband frequency). Notably, the built-in serial resonance frequency is typically fixed and determined by the mass and/or structure of the acoustic resonator structure. In embodiments disclosed herein, the multi-passband frequency acoustic structure further includes a tuning circuit, which can be tuned to bypass the acoustic resonator structure in a tunable serial resonance frequency (a.k.a. tunable passband frequency) to pass the signal directly to the signal output, or to forward the signal to the acoustic resonator structure outside the tunable serial resonance frequency (e.g., in the built-in serial resonance frequency). As such, the multi-passband frequency acoustic structure can operate with multiple serial resonance frequencies to thereby support multiple passband frequencies.
Embodiments described herein may provide a surface acoustic wave (SAW) device, methods of fabricating the SAW device, and a system incorporating the SAW device. The SAW device may include a piezoelectric substrate and individual resonators may be formed by a plurality of electrodes on the surface of the piezoelectric substrate. A dielectric layer having a positive thermal coefficient of frequency (TCF) may be formed on each of the plurality of electrodes. In various embodiments, temperature compensation may be achieved by providing more or less of the dielectric layer on at least one resonator than on the other resonators based on a configuration of the resonators. In various embodiments, temperature compensation may be achieved by providing at least one resonator with a different duty factor than the other resonators based on a configuration of the resonators.
G10K 11/18 - Methods or devices for transmitting, conducting or directing sound
H03H 3/02 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
H03H 9/25 - Constructional features of resonators using surface acoustic waves
H03H 9/54 - Filters comprising resonators of piezoelectric or electrostrictive material
H10N 30/06 - Forming electrodes or interconnections, e.g. leads or terminals
38.
DUAL DIRECTIONAL COUPLER WITH MULTIPLE COUPLINGS FOR SYMMETRICAL PERFORMANCE
A dual directional coupler with multiple couplings for symmetrical performance is provided. The dual directional couplers implemented in radio frequency (RF) front-end modules often deliver different RF performance in terms of coupling factor and directivity between the forward and reverse modes. The performance asymmetry between these modes generally has multiple origins, where the two most relevant can be ascribed to the die layout (asymmetric die layout) and module routing (e.g., the antenna and coupler out pads are next to each other and experience mutual coupling). Embodiments described herein aim to improve the performance symmetry of dual directional couplers by employing a novel asymmetric layout which symmetrizes performance by adding mutual couplings that compensate the undesired ones. A novel circuit topology is also presented, which enables the forward and reverse modes to be tuned independently, adding a further degree of freedom during the design phase.
H01P 5/18 - Conjugate devices, i.e. devices having at least one port decoupled from one other port consisting of two coupled guides, e.g. directional couplers
H03F 3/24 - Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
An antenna structure is disclosed that is well suited for use in dual- or multi-band wireless environments and sized so that it may be used in an antenna array for angle of arrival (AoA) detection. More specifically, an antenna may include a first antenna element, which may be an antenna element such as a patch antenna. The first antenna element is positioned in a first plane and positioned on first side of a substrate. On an opposite side of the substrate, a ground plane may be positioned in a second plane. The ground plane shapes the radiation pattern of the first antenna element to operate as a directional antenna. Sandwiched between the ground plane and the first antenna element is an intermediate antenna element constructed to act as a metamaterial that increases an effective distance between the ground plane and the first antenna element.
G01S 3/04 - Direction-finders for determining the direction from which infrasonic, sonic, ultrasonic, or electromagnetic waves, or particle emission, not having a directional significance, are being received using radio waves - Details
A progressive envelope tracking (ET) with delay compensation includes an ET integrated circuit (IC) (ETIC) that is a progressive ETIC that switches between different driver amplifiers having different associated offset voltages based on a tracking signal (e.g., Vramp) from a baseband transceiver. To make sure that desired changes to the offset voltage occur contemporaneously with an input signal for the driver amplifiers, a delay may be added to the input signal for the driver amplifiers. By adding and controlling this delay to the input to the driver amplifiers, the changes to the offset voltage will track the changes to the input signal at the driver amplifiers and overall efficiency of the ETIC may be improved.
An envelope tracking (ET) radio frequency (RF) front-end circuit receives a single tracking signal (e.g., Vramp) from a baseband transceiver and generates a plurality of control signals (Vcc). The control signals are created by a multiple control signal generator circuit based on a calculated load estimate for each relevant power amplifier. The load estimate may be calculated from a sensed current and voltage. By providing control signals optimized for loads presented to the power amplifiers, the overall efficiency of the transmitter is improved.
An analog predistortion system for power amplifiers is disclosed. In one aspect, the system may apply analog predistortion to offset memory effects that may occur as a function of frequencies that operate faster than time constants of the related circuits. In a particular aspect, the analog predistortion is applied at least to a phase of the signal to be amplified, but may also be applied to a gain of the signal to be amplified. When such memory focused analog predistortion is combined with memoryless or low depth memory digital predistortion, overall linearity and performance of the power amplifier is improved.
Systems and methods for analog predistortion (APD) in power amplifiers are disclosed. In one aspect, APD may be provided in a front-end module (FEM) of a transmitter. More specifically, the APD may include different predistortions based on where within a frequency band the signal to be distorted is operating (i.e., sub-band APD). The APD in the FEM may further be based on operating conditions such as temperature within the FEM. Still further, the FEM may be configured to apply different APD based on whether or not a baseband processor (BBP) applies digital predistortion (DPD). At a minimum, the provision of the APD may make the operation of a power amplifier in FEM more linear. Further, where DPD is present, the use of the APD may simplify the requirements for the DPD provided in the BBP.
The present disclosure relates to an amplifier system having an output amplifier stage with a signal input and output, and a varactor with a capacitive output that is coupled to the signal input for adjusting input capacitance. The amplifier system also includes push varactor bias circuitry with a bias level output that is coupled to a tuning input, and a bias control input. The push varactor bias circuitry is configured to adjust bias voltage at the tuning input and thereby adjust the capacitance at the signal input by way of the varactor and reduce signal distortion at the signal output in response to a distortion compensation signal received at the bias control input.
The present disclosure pertains to a power amplifier system that promotes enhanced signal linearity and overall system efficiency. The system includes a power amplifier with an amplification path for a radio frequency (RF) signal, and detector circuitry operationally linked to sample locations along this path. The detector circuitry captures and transmits signal characteristics of the RF signal. A voltage standing wave ratio (VSWR) quadrant data generator in communication with the detector circuitry generates VSWR quadrant data based on the detected signal characteristics. The baseband circuitry, comprised of a memory unit preconfigured with digital pre-distortion (DPD) coefficients and a DPD processor, controls the shaping of pre-distortion applied to the RF signal based on the VSWR data, thereby enhancing signal linearity. The components of the system interconnect and collaboratively function to optimize the performance and efficiency of the power amplifier system.
An acoustic filter providing negative capacitance for use in multiplexers is provided that may include a first resonator and a second resonator. The second resonator may be a three terminal element that includes two sub-resonator elements having opposite polarities that are mechanically coupled such that as one sub-resonator expands, the other contracts. The second resonator may act as a negative capacitance element relative to the first resonator such that the second resonator provides cancelation at specific frequencies. This structure may further reduce the order of an N-multiplexer ladder network and reduce total insertion loss.
The present disclosure relates to a resonator structure including stacked resonators, which share a same reflector. The disclosed resonator structure includes a first resonator and a second resonator, which is vertically stacked with the first resonator and shares a common reflector with the first resonator. Herein, the first resonator is at least composed of a first top electrode, a first piezoelectric layer underneath the first top electrode, and the common reflector underneath the first piezoelectric layer. The second resonator is at least composed of the common reflector, a second piezoelectric layer underneath the common reflector, and a second bottom electrode underneath the second piezoelectric layer. The first resonator and the second resonator are acoustically isolated from each other.
Acoustic wave devices, and particularly piezoelectric layer arrangements in acoustic wave devices and related methods are disclosed. Acoustic wave devices may include a piezoelectric layer on a carrier substrate. The piezoelectric layer is formed with a thickness that is varied or shaped across different portions of the carrier substrate. Different piezoelectric layer thicknesses on a common carrier substrate may be provided for different surface acoustic wave (SAW) filter structures that are formed monolithically, for different sets of resonators within a single filter structure, and for different regions within a single SAW device in one or more of the transverse direction or the propagation directions. Shaping piezoelectric layers may include selectively removing or adding portions of the piezoelectric layer. In this manner, piezoelectric layer thicknesses at different hierarchy levels within SAW devices and filters may be tailored to provide different acoustic resonator properties without requiring separately formed devices on separate substrates.
H03H 3/08 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves
H03H 9/145 - Driving means, e.g. electrodes, coils for networks using surface acoustic waves
49.
ANTENNA ASSEMBLIES AND ANTENNA MODULES FOR USE IN WIRELESS COMMUNICATION SYSTEMS
A wireless communication system comprising one or more cross polarized antenna assemblies with optimized propagation delay that form part of an antenna module having two dominant perpendicular polarizations. Isolation or crosstalk in each antenna module is minimized through an implementation of a sectorized planar isolation and correlation enhancer in the form of a ground plane opening structure.
A system in package (SiP) with an air cavity is disclosed. In one aspect, a technique to bond a lid over the air cavity that reduces the risk of cavity integrity failure is provided. More specifically, an epoxy seal is created on four walls of a lid enclosing the cavity. A further sputtered metal layer is added over the epoxy seal to provide additional structural rigidity, electromagnetic emission suppression and to assist in preventing leaks through the epoxy seal.
H01L 23/053 - Containers; Seals characterised by the shape the container being a hollow construction and having an insulating base as a mounting for the semiconductor body
H01L 21/52 - Mounting semiconductor bodies in containers
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
51.
PROCESS FOR MAKING LAMINATE SUBSTRATE WITH SINTERED COMPONENTS
The present disclosure relates to a process to integrate sintered components in a laminate substrate. The disclosed process starts with providing a precursor substrate, which includes a substrate body having an opening through the substrate body, and a first foil layer. Herein, the first foil layer is formed underneath the substrate body, so as to fully cover a bottom of the opening. Next, a sinterable base material is applied into the opening and over the first foil layer, and then sintered at a first sintering temperature to create a sintered base component. A sinterable contact material is applied over the sintered base component, and then sintered at a second sintering temperature to create a sintered contact film. The sintered base component is confined within the opening by the substrate body on sides, by the first foil layer on bottom, and by the sintered contact film on top.
H01F 41/04 - Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils or magnets for manufacturing coils
C04B 35/581 - Shaped ceramic products characterised by their composition; Ceramic compositions; Processing powders of inorganic compounds preparatory to the manufacturing of ceramic products based on non-oxides based on borides, nitrides or silicides based on aluminium nitride
C04B 35/47 - Shaped ceramic products characterised by their composition; Ceramic compositions; Processing powders of inorganic compounds preparatory to the manufacturing of ceramic products based on oxides based on titanium oxides or titanates based on titanates based on alkaline earth metal titanates based on strontium titanates
C04B 35/468 - Shaped ceramic products characterised by their composition; Ceramic compositions; Processing powders of inorganic compounds preparatory to the manufacturing of ceramic products based on oxides based on titanium oxides or titanates based on titanates based on alkaline earth metal titanates based on barium titanates
C04B 35/10 - Shaped ceramic products characterised by their composition; Ceramic compositions; Processing powders of inorganic compounds preparatory to the manufacturing of ceramic products based on oxides based on aluminium oxide
B22F 7/04 - Manufacture of composite layers, workpieces, or articles, comprising metallic powder, by sintering the powder, with or without compacting of composite layers with one or more layers not made from powder, e.g. made from solid metal
C04B 41/50 - Coating or impregnating with inorganic materials
A symmetric dual direction coupler has a layout that is controlled such that there is an axis of symmetry between ports and that any switches used within the dual direction coupler are also symmetrical. That is, for a dual direction coupler having a transmitted port, an input port, an isolated port, and a coupled port with switches used to control forward mode or reverse mode for the coupler, the transmitted port and the input port are symmetrical across the axis of symmetry; the isolated port and coupled port are symmetrical across the axis of symmetry; and the switch layout is symmetrical across the axis of symmetry.
H01P 5/18 - Conjugate devices, i.e. devices having at least one port decoupled from one other port consisting of two coupled guides, e.g. directional couplers
53.
DIFFERENTIAL AMPLIFIER WITH IMPEDANCE TERMINATIONS
A differential amplifier is disclosed with harmonic terminations. The differential amplifier has a first transistor having a first emitter coupled to a fixed voltage node, a first base, and a first collector. A second transistor has a second emitter coupled to the fixed voltage node, a second base, and a second collector. A first capacitor and a first inductor are coupled in series between the first collector and a virtual ground node. A second inductor and a second capacitor are coupled in series between the second collector and the virtual ground node, and a third inductor is coupled between the virtual ground node and the fixed voltage node. The first and second capacitors and first, second, and third inductors have capacitances and inductances, respectively, that are sized to realize second and third harmonic traps for a radio frequency signal being amplified by the differential amplifier.
An electrical arrangement for performing radio frequency isolation for microelectromechanical relay switches. A microelectromechanical relay switch comprises a beam configured to switch from a first position connected to an upper voltage source to a second position connected to a lower voltage source. The microelectromechanical relay switch further comprises at least one frequency isolation circuit or resistor disposed adjacent to the beam. The at least one frequency isolation circuit or resistor biases a direct current potential to allow for electrostatic actuation and further provides a path for transient electrical currents during switching.
Power protection loops for amplifier chain elements are disclosed. In one aspect, an amplifier chain may have a power detection circuit detect power within the amplifier chain. When the power exceeds a threshold, a control circuit limits amplification provided by amplifier element(s) within the amplifier chain to throttle or lower power levels within the amplifier chain, thereby protecting elements within the amplifier chain. In this fashion, not only may the amplifier element(s) be protected, but also acoustic filter elements may be protected. The threshold used to throttle or lower the power levels may be based on one or more of: a supply voltage, a sensed temperature, and a mode (e.g., 2G, 3G, 4G, 5G). By protecting these elements, these elements survive power surges instead of failing.
The present disclosure describes a front-end module (FEM) and a process for making the same. In the disclosed FEM, a thinned flip-chip die, which includes a device region with a metal layer, resides over a module carrier. A mold compound resides over the module carrier, surrounds the thinned flip-chip die, and extends beyond a top surface of the thinned flip-chip die to define an opening over the top surface of the thinned flip-chip die and within the mold compound. A ferrimagnetic portion resides over the top surface of the thinned flip-chip die and within the opening, and a permanent magnetic portion resides over the ferrimagnetic portion and within the opening. Herein, the permanent magnetic portion, the ferrimagnetic portion, and the metal layer of the device region are vertically aligned, and form a circulator vertically stacked with the thinned flip-chip die.
Voltage ripple reduction in a power management circuit is disclosed. The power management circuit includes a power amplifier circuit configured to amplify a radio frequency (RF) signal based on a modulated voltage and an envelope tracking integrated circuit (ETIC) configured to provide the modulated voltage to the power amplifier circuit via a conductive path. Notably, an output impedance presenting at an input of the power amplifier circuit can interact with a modulated load current in the power amplifier circuit to create a voltage ripple in the modulated voltage to potentially cause an undesirable error in the RF signal. In this regard, a notch circuit is provided, preferably in the ETIC, to reduce the voltage ripple within a modulation bandwidth of the RF signal. As a result, it is possible to minimize the undesirable error, such as root-mean-square (RMS) error vector magnitude (EVM), within the modulation bandwidth of the RF signal.
An on-chip capacitance measurement method and associated systems and devices are provided. Embodiments described herein rely on using the capacitor under test in an on-chip relaxation oscillator configuration whose charging/discharging currents, supply voltage, and output frequency are measured individually in a measurement block. The voltage thresholds of the relaxation oscillation are calculated from the circuit elements and the measured supply voltage. Because the oscillation frequency of the relaxation oscillator is a function of the capacitance under test, the charging/discharging currents, and the supply voltage (via voltage thresholds), the capacitance under test can be calculated using the measured values of the other quantities. Embodiments described herein provide an accurate, low-power, small-area on-chip system capable of measuring capacitance with high accuracy. An algorithm employing the above method and apparatus for tuning a crystal oscillator is also provided. Relevant circuit implementations used in the on-chip measurement system are also disclosed.
G01R 27/26 - Measuring inductance or capacitance; Measuring quality factor, e.g. by using the resonance method; Measuring loss factor; Measuring dielectric constants
H03B 5/24 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising resistance and either capacitance or inductance, e.g. phase-shift oscillator active element in amplifier being semiconductor device
A Doherty amplifier system is disclosed. The Doherty amplifier system includes a carrier amplifier having a carrier input and a carrier output, and a peaking amplifier having a peaking input coupled to the carrier input and a peaking output coupled to the carrier output. Analog pre-distortion circuitry is configured to linearize the carrier amplifier and linearize the peaking amplifier by compensating for base-to-collector capacitance loading of the carrier amplifier and the peaking amplifier during operation.
Equalizer circuitry includes a differential target voltage input, an equalizer output, a first operational amplifier, and a second operational amplifier. The differential target voltage input includes a target voltage input node and an inverted target voltage input node. The first operational amplifier and the second operational amplifier are coupled in series between the differential target voltage input and the equalizer output. The first operational amplifier is configured to receive a target voltage signal and provide an intermediate signal based on the target voltage input signal. The second operational amplifier is configured to receive the intermediate signal and an inverted target voltage signal and provide an output signal to the equalizer output. The first operational amplifier and the second operational amplifier are interconnected with one or more passive components such that a transfer function between the differential target voltage input and the equalizer output is a second-order complex-zero function.
Methods of depositing material onto substrate comprising: depositing a first seed material onto a wafer substrate, the wafer substrate having a face that defines a normal to the substrate, wherein the first seed material is deposited at a pressure of 10 to 20 mTorr to form a pre-seed layer on the wafer substrate, wherein the pre-seed layer has a surface roughness from 1 to 10 nm; depositing a second seed material onto at least a portion of the pre-seed layer at an off-normal incidence angle to form a seed layer on at least a portion of the pre-seed layer; and depositing a bulk piezoelectric material onto at least a portion of the seed layer to form a bulk piezoelectric layer having a c-axis tilt of 35 degrees or greater and a surface roughness of 4.5 nm or less. Structures and bulk acoustic wave resonators containing same are also included.
H10N 30/079 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by depositing piezoelectric or electrostrictive layers, e.g. aerosol or screen printing using intermediate layers, e.g. for growth control
H10N 30/00 - Piezoelectric or electrostrictive devices
A bridge-T filter is disclosed. In one aspect, the bridge-T filter may include one or more inductors associated with acoustic resonators to assist in providing out-of-band rejection while improving fractional bandwidth of the filter. In specific aspects, the additional inductors may be placed in series or parallel to the acoustic resonators. The improved fractional bandwidth and better out-of-band rejection reduces unwanted signals and improves the user experience.
Assemblies including a bulk acoustic wave acoustic sensor die having a first and an opposing second major surface, the die including a piezoelectric structure, a first and a second electrode electrically connected to the piezoelectric structure, and an active surface on the first major surface of the die; a printed circuit board (PCB), the PCB having a first major surface and an opposing second major surface and including a slot spanning from the first major surface to the second major surface through the PCB; a first bond electrically and mechanically connecting the die to the PCB; and a second bond electrically and mechanically connecting the die to the PCB, wherein the first and the second bonds are located on either side of the slot through the PCB and the active surface of the die is above the slot in the PCB.
A low-noise amplifier is disclosed having a first transistor with a first current terminal coupled to a supply voltage rail through a load resistor and a second current terminal coupled to an input node, wherein a bias resistor is coupled between the input node and a fixed voltage node. A second transistor has a third current terminal coupled to an output node and a fourth current terminal coupled to the fixed voltage node. A feedback capacitor is coupled between the input node and the output node, wherein capacitance of the feedback capacitor is sized to eliminate the need for coupling an input impedance matching inductor to the input node.
Low noise amplifiers (LNAs) are disclosed. In one aspect, an LNA may have distortion cancellation that is orthogonally implemented relative to noise cancellation such that changes to the distortion cancellation do not affect the noise cancellation. In further exemplary aspects, cancellation circuitry is added in parallel to a main or primary LNA path. The cancellation circuitry may include an initial impedance matching amplifier that effectuates noise cancellation and a second amplifier that effectuates distortion cancellation. Variations in the placement and composition of the second amplifier are provided. By providing a second path that allows for independent control of noise and distortion cancellation, overall performance of the LNA is improved.
Systems and method for location determination in a distributed system are disclosed. In one aspect, the distributed system operates at frequencies where obstacles and distance may preclude direct connection between a system node and a remote mobile device. The system may determine the location of the remote mobile device using an intermediate device and thus be a location system. Specifically, a position of the intermediate device relative to the system node is calculated and a position of the remote mobile device relative to the intermediate device is calculated. The two positions may be combined to determine a position of the remote mobile device relative to the system node. Once the location of the remote mobile device is known relative to the system node, a variety of location services become available.
H04W 64/00 - Locating users or terminals for network management purposes, e.g. mobility management
G01S 5/02 - Position-fixing by co-ordinating two or more direction or position-line determinations; Position-fixing by co-ordinating two or more distance determinations using radio waves
An asymmetrical power amplifier circuit is provided. The asymmetrical power amplifier circuit includes a carrier amplifier and a peak amplifier. The carrier amplifier is always active to amplify a radio frequency (RF) to a carrier output power, while the peak amplifier is only active to amplify the RF signal to a peak output power when a time-variant output power of the RF signal is higher than a predefined power threshold. The RF signal in the carrier output power is summed with the RF signal in the peak output power to thereby output the amplified RF signal in the time-variant output power. Unlike a conventional symmetrical power amplifier, the carrier output power and the peak output power are different at a peak of the time-variant output power. As such, the carrier amplifier and the peak amplifier can both operate with optimal efficiency based on a same modulated voltage.
An antenna tuning circuit is disclosed. The antenna tuning circuit is configured to make multiple estimates on an antenna impedance at an antenna port and determine an optimum tuning state for antenna tuning based on the antenna impedance estimates. The antenna tuning circuit may be further configured according to various embodiments of the present disclosure to minimize impedance estimation error, reduce magnitude and/or phase disturbance during antenna tuning, and extrapolate antenna impedance estimates for both transmit and receive frequencies. As a result, the antenna tuning circuit can accomplish autonomous antenna tuning optimization to thereby improve transmit and receive performance in a wireless communication device.
H01Q 5/335 - Individual or coupled radiating elements, each element being fed in an unspecified way using frequency dependent circuits or components, e.g. trap circuits or capacitors at the feed, e.g. for impedance matching
A switchable RF transmit/receive (TX/RX) multiplexer, which includes a group of RF TX bandpass filters, a group of RF TX switching elements, and a group of RF RX bandpass filters; is disclosed. The group of RF TX bandpass filters includes a first RF TX bandpass filter and a second RF TX bandpass filter, such that each of the first RF TX bandpass filter and the second RF TX bandpass filter is coupled to a first filter connection node. The group of RF TX switching elements includes a first RF TX switching element coupled between the first filter connection node and a first common connection node, which is coupled to a first RF antenna. Each of the group of RF RX bandpass filters is coupled to the first common connection node.
A concurrent multistandard detection receiver with prepacket transmission detection capabilities is disclosed. In one aspect, a receiver is configured to switch between two different wireless protocols, alternately listening for incoming messages on one then the other protocol. For at least one listening period, the receiver uses two pretransmission detectors that are configured to detect predictable pretransmission emissions. A third detector may detect traditional transmissions. On detection of a signal that matches a predictable pretransmission emission or a traditional transmission, the receiver confirms that an incoming signal according to that standard is being received and acts in accordance with that signal. If no such emission or transmission was received, or if after trying to confirm the presence of an incoming signal fails, the receiver switches back to listening according to the other protocol.
A transistor is disclosed having a substrate, a device layer disposed over the substrate, a gate electrode disposed over the device layer, and a drain electrode disposed over the substrate and spaced from the gate electrode. A first source electrode is disposed over the substrate opposite the drain electrode and spaced from the gate electrode. A second source electrode is disposed over the substrate spaced from the drain electrode opposite the gate electrode. A dielectric is disposed over the device layer, the gate electrode, and the drain electrode between the first source electrode and the second source electrode. A conductive interconnect couples the first source electrode and the second electrode and extends over the dielectric. The conductive interconnect comprises a shield wall that extends from the conductive interconnect into the dielectric between the gate electrode and the drain electrode with a distal end that is spaced above the device layer.
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
Embodiments described herein may provide a surface acoustic wave (SAW) device, methods of fabricating the SAW device, and a system incorporating the SAW device. The SAW device may include a piezoelectric substrate and individual resonators may be formed by a plurality of electrodes on the surface of the piezoelectric substrate. A dielectric layer having a positive thermal coefficient of frequency (TCF) may be formed on each of the plurality of electrodes. In various embodiments, temperature compensation may be achieved by providing more or less of the dielectric layer on at least one resonator than on the other resonators based on a configuration of the resonators. In various embodiments, temperature compensation may be achieved by providing at least one resonator with a different duty factor than the other resonators based on a configuration of the resonators.
H03H 3/02 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
H10N 30/06 - Forming electrodes or interconnections, e.g. leads or terminals
Disclosed is a low noise amplifier system. Included is a main amplifier having a main input coupled to a RF input and a main output connected to an RF output and an impedance amplifier having an impedance input coupled to the RF input and an impedance output coupled to the RF output, wherein the impedance amplifier is configured to provide input impedance matching to the main amplifier. The impedance amplifier also provides a first noise path that passes through the impedance amplifier such that the noise generated by the impedance amplifier is substantially out of phase with the noise that passes through a second noise path that passes through the main amplifier. A neutralization amplifier is configured to reduce parasitic capacitive loading within the first noise path.
The present disclosure relates to a semiconductor package with a thermally enhanced molding compound. The disclosed semiconductor package includes a module carrier having an upper surface, a die formed over the upper surface of the module carrier, and a thermally enhanced molding compound component formed over the upper surface of module carrier to encapsulate the die. Herein, the thermally enhanced molding compound is formed from a molding compound mixed with a thermal additive and has no air pockets or voids. The thermal additive includes a number of carbon flakes or a number of carbon spherical particles. The thermal additive has a thermal conductivity larger than 450 W/m·K and an electrical resistivity larger than 90 μΩ.cm. In one embodiment, the thermal additive includes a number of graphene flakes, a number of graphene particles, a number of graphite flakes, or a number of graphite particles.
Disclosed is a low noise amplifier system. Included is a main amplifier having a main input coupled to a RF input and a main output connected to an RF output and an impedance amplifier having an impedance input coupled to the RF input and an impedance output coupled to the RF output, wherein the impedance amplifier is configured to provide input impedance matching to the main amplifier. The impedance amplifier also provides a first noise path that passes through the impedance amplifier such that the noise generated by the impedance amplifier is substantially out of phase with the noise that passes through a second noise path that passes through the main amplifier.
Multichip module thermal management through backside metal systems and methods are disclosed. In one aspect, a multichip module includes one or more flip chip integrated circuits (ICs), each having a backside to which a metal heat conductor or spreader is attached. The presence of the metal heat conductor on the backside of the flip chip ICs allows for a better thermal path to remove heat from the ICs relative to the substrate. The improved thermal path reduces the likelihood of damage to the ICs or delamination of the module. A variety of methods are proposed to construct the backside metal systems. Additionally, a variety of capture features may be used to assist in structural integrity.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
77.
AMPLITUDE MODULATION-PHASE MODULATION (AM-PM) LINEARIZATION IN A POWER AMPLIFIER USING BIAS CIRCUITRY
Amplitude modulation-phase modulation (AM-PM) linearization in a power amplifier using bias circuitry, which fixes a bias of a cascode transistor within a power amplifier is disclosed. In particular, the cascode transistor may switch between operation in a saturation mode and a triode mode. The bias is set such that the cascode transistor operates at a fixed duty cycle in the triode mode relative to the saturation mode for a wide range of signal levels from small-signal to large-signal. An exemplary duty cycle is fifty percent (50%), although other duty cycles may be used. This bias will result in a constant capacitance contributed by the cascode device to the power amplifier over a wide signal level range.
Amplitude modulation-phase modulation (AM-PM) linearization in power amplifier techniques are disclosed. In one aspect, a fixed capacitor is placed in parallel to a cascode device within a power amplifier. The sum of capacitances from the cascode device and the parallel capacitor may be relatively fixed across voltage swings, allowing for small phase changes across a wide range of signal amplitudes passing through the power amplifier. The small phase changes across voltage swings make it easier to provide compensation for such phase changes resulting in a more efficient device.
H03F 1/22 - Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively
H03F 3/24 - Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
H03F 1/32 - Modifications of amplifiers to reduce non-linear distortion
79.
LAMINATE SUBSTRATE WITH EMBEDDED MULTI-LAYERED HEAT SLUG
The disclosure is directed to an electronic device with an embedded multi-layered heat slug. The electronic device in includes a substrate having a substrate body with a laminate layer. The substrate further includes a heat slug embedded within the substrate body. The heat slug includes a top layer having a first thermal conductivity and a first thermal expansion coefficient, a bottom layer having a second thermal conductivity and a second thermal expansion coefficient, and a core layer having a third thermal conductivity and a third thermal expansion coefficient. The third thermal conductivity is less than the first thermal conductivity and the second thermal conductivity, and the third thermal expansion coefficient is less than the first thermal expansion coefficient and the second thermal expansion coefficient. In certain embodiments, the top layer and the bottom layer comprise copper, and the core layer comprises copper-molybdenum.
Systems and methods for low-power auto-correlation antenna selection for multi-antenna systems are disclosed. In particular, a computing device, such as an Internet of Things (IoT) computing device, may include a transceiver operating with multiple antennas. For example, the computing device may operate under a low-power wireless standard such as Long Range BLUETOOTH LOW ENERGY (LR BLE). In an exemplary aspect, an antenna from amongst the multiple antennas may be selected based on which antenna is receiving a best copy of a periodic signal. The periodic signal is likely indicative of a preamble pattern and, as such, may be used to activate a cross-correlation circuit for signal detection confirmation. Power consumption is reduced by delaying activation of the cross-correlation circuit until a likely signal is detected by detection of the periodic signal.
H04B 7/08 - Diversity systems; Multi-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the receiving station
H04B 7/06 - Diversity systems; Multi-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station
81.
DELAMINATION/CRACKING IMPROVEMENT AT SOLDER JOINTS IN MICROELECTRONICS PACKAGE
The present disclosure relates to a microelectronics package with significantly reduced delamination/cracking at solder joints, and a process for making the same. The disclosed microelectronics package includes a carrier, a solder joint region over the carrier, a top intermetallic (IMC) layer over the solder joint region, and a device die over the top IMC layer. Herein, the device die includes a substrate, an active device over the substrate, a top barrier layer underneath the substrate, and a backside metal layer vertically between the top IMC layer and the top barrier layer. The backside metal layer is formed of gold (Au) with a thickness at least 0.5 μm. The top IMC layer comprises gold nickel tin (AuNiSn) or gold platinum tin (AuPtSn), and the solder joint region comprises an Au-rich gold-tin (Au5Sn) and gold-tin (AuSn) eutectic mixture.
A substrate includes a heat slug that is disposed in a cavity in the substrate. An engineered filler material is disposed in the cavity over, under, and/or around the heat slug. The engineered filler material is a thermally conductive particle material having a composition that can be adjusted based on a desired coefficient of thermal expansion. An electronic device can be attached to the substrate over the heat slug and the engineered filler material. The heat slug and the engineered filler material provide, or are part of, a heat transfer dissipation path for the electronic device.
H01L 21/54 - Providing fillings in containers, e.g. gas fillings
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
In some embodiments, a printed circuit board is disclosed. The printed circuit board includes a substrate, a conductive plane, and at least one switch. The conductive plane includes an edge enabled void construction (EEVC) along a geometric perimeter of the conductive plane, the EEVC having an EEVC void that defines an EEVC perimeter that extends into the conductive plane.
Disclosed is a power amplifier system having a main amplifier with an input coupled to a main radio frequency (RF) input and an output connected to a main RF output, wherein the main amplifier exhibits a nonlinear gain characteristic with compression. At least one compression compensating amplifier has a signal input coupled to the common RF input and a signal output coupled to the common RF output.
A hybrid bus communication circuit is provided. The hybrid bus communication circuit includes at least two different types of communication buses. The hybrid bus communication circuit also includes a hybrid bridge circuit and several multi-bus slave circuits each coupled to the two different types of communication buses. In a non-limiting example, each of the multi-bus slave circuits may communicate timing critical information via a first type communication bus and non-timing critical information via a second type communication bus. The hybrid bridge circuit is configured to receive a configuration command via the first type communication bus and, accordingly, configure a configuration parameter(s) in any of the multi-bus slave circuits via the second type communication bus. As such, it is possible to make time constrained configuration changes in any of the multi-bus slave circuits without interfering with the timing critical communication conducted via the first type communication bus.
Power efficiency can be optimized in a direct current (DC)-DC converter in discontinuous conduction mode (DCM) if a transition from a state of decreasing inductor current to a state of zero inductor current occurs as close as possible to the decreasing inductor current reaching zero. The timing of a zero current indication is affected by a voltage offset and a propagation delay of a comparator. A DC-DC converter, including a control circuit for accurate detection of zero inductor current, is disclosed. A control circuit calibrates an offset voltage for a load, stores a corresponding offset value, and in response to powering the load, provides an offset voltage to the comparator based on the stored offset value. In some examples, the control circuit determines an offset voltage and stores an offset value for each voltage and switch width combination. Using stored offset values increases accuracy of zero inductor current detection.
H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion
H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
A control system is configured to control an output power of a power amplifier. The control system is operable to detect when the power amplifier is in first state and responsively provide first additional bias to the power amplifier. The first additional bias assists or enables the power amplifier in increasing the output power. The control system is also operable to detect when the power amplifier is in a second state and responsively provide second additional bias to the power amplifier. The second additional bias assists or enables the power amplifier in increasing the amount of output power.
A reactance cancelling radio frequency (RF) circuit array is disclosed. The reactance cancelling RF circuit array includes multiple RF circuits each coupled to one or two adjacent RF circuits by one or two pairs of coupling mediums each having a respective length less than one-quarter wavelength. In one aspect, an RF input signal is first split across the RF circuits and then combined to form an RF output signal. As a result, each RF circuit requires a lower power handling capability to process a portion of the RF input signal. In another aspect, each pair of the coupling mediums can cause reactance cancellation in each reactance-cancelling pair of the RF circuits. By coupling the RF circuits via the coupling mediums and enabling splitting-combining among the RF circuits, it is possible to miniaturize the reactance cancelling RF circuit array for improved performance across a wide frequency spectrum.
H01Q 5/314 - Individual or coupled radiating elements, each element being fed in an unspecified way using frequency dependent circuits or components, e.g. trap circuits or capacitors
H03F 1/56 - Modifications of input or output impedances, not otherwise provided for
89.
HIGH POWER BACK-OFF EFFICIENCY ASYMMETRIC-STACKED DIFFERENTIAL QUADRATURE LOAD MODULATION PA
A load modulation amplifier is disclosed having a first power amplifier configured to amplify a first portion of a radio frequency signal below a threshold level. A second power amplifier has an N stack of transistor devices configured in a cascode configuration to amplify a second portion of the radio frequency signal that is above the threshold level, wherein N is a counting number that is greater than one.
A programmable acoustic filter circuit is provided. Herein, the programmable acoustic filter circuit can be dynamically controlled to toggle between two different passbands, such as different unlicensed national information infrastructure (UNII) bands. The programmable acoustic filter circuit includes an insertion element, a main filter, and a notch circuit. The insertion element is coupled in series with the main filter with very low insertion loss. Specifically, the notch circuit can be dynamically decoupled from the insertion element to thereby cause the main filter to pass a radio frequency (RF) signal in a main passband or be coupled to the insertion element to thereby cause the main filter to pass the RF signal in an alternative passband different from the main passband. As a result, it is possible to flexibly configure the programmable acoustic filter circuit to provide adequate out-of-band rejection with lowest possible insertion loss in various coexisting and concurrent operations.
A hybrid global location tracking system is disclosed. The hybrid global location tracking system includes an anchor device(s) and multiple tag devices, each including an ultra-wideband (UWB) transceiver circuit. The anchor device(s) can broadcast a location request to wake up the tag devices for location update. Each of the tag devices can measure a distance and an angle based on the received location request and report the measured distance and angle to the anchor device(s), either directly or through another tag device(s) located within communication range of the anchor device(s). Herein, the anchor device(s) can also determine its own global positioning coordinate and orientation. Accordingly, a global positioning location can be determined for each tag device based on the global positioning coordinate and the orientation of the anchor device(s), and the distance and angle reported by the tag device, without requiring a global positioning receiver in the tag device.
An average power tracking (APT) power management circuit is provided. The APT power management circuit is configured to generate a first APT voltage(s) for a first power amplifier(s) and a second APT voltage(s) for a second power amplifier(s). The APT power management circuit further includes a pair of switcher circuits that can generate a pair of reference voltages. Depending on various operating scenarios of the APT power management circuit, it is possible to selectively output any of the reference voltages as any one or more of the first APT voltage(s) and the second APT voltage(s). As such, it is possible to flexibly configure the APT power management circuit to support the various operating scenarios based on a minimum possible number of the switcher circuits, thus helping to reduce footprint and cost of the APT power management circuit.
The present disclosure relates to a package architecture and a method for making the same. The disclosed package architecture includes a package carrier, a first device die and a second device die mounted on the package carrier, and a heat spreader. The first device die includes a first device body with a thickness between 5 µm and 130 µm, a die carrier, and an attachment section between the first device body and the die carrier, while the second device die includes a second device body. The first device body and the second device body are formed of different materials. A top surface of the die carrier of the first device die and a top surface of the second device body of the second device die are substantially coplanar. The heat spreader resides over the top surface of the die carrier and the top surface of the second device body.
H01L 23/367 - Cooling facilitated by shape of device
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
Described herein is a MEMS force sensor with stress concentration design. The stress concentration can be performed by providing slots, whether through or blind, and/or selective thinning of the substrate. The MEMS force sensor is in chip scale package with solder bumps or metal pillars and there are sensing elements formed on the sensor substrate at the stress concentrate area. The stress concentration can be realized through slots, selective thinning and a combination of both.
G01L 1/18 - Measuring force or stress, in general using properties of piezo-resistive materials, i.e. materials of which the ohmic resistance varies according to changes in magnitude or direction of force applied to the material
B81B 3/00 - Devices comprising flexible or deformable elements, e.g. comprising elastic tongues or membranes
95.
Concurrent multistandard detection receiver with prepacket transmission detection
A concurrent multistandard detection receiver with prepacket transmission detection capabilities is disclosed. In one aspect, a receiver is configured to switch between two different wireless protocols, alternately listening for incoming messages on one then the other protocol. For at least one listening period, the receiver uses two pretransmission detectors that are configured to detect predictable pretransmission emissions. A third detector may detect traditional transmissions. On detection of a signal that matches a predictable pretransmission emission or a traditional transmission, the receiver confirms that an incoming signal according to that standard is being received and acts in accordance with that signal. If no such emission or transmission was received, or if after trying to confirm the presence of an incoming signal fails, the receiver switches back to listening according to the other protocol.
Embedded blocking capacitor structures for wideband amplifier circuits are disclosed. A wideband amplifier circuit includes transistors that output radio frequency (RF) signals. An embedded blocking capacitor structure is operably connected between the terminals of the transistors and an RF output. The embedded blocking capacitor structure distributes a bias voltage to the terminals of the transistors and blocks the bias voltage from passing to the RF output. The embedded blocking capacitor structure also propagates an RF signal to an RF output.
Systems and methods of assessing a plausibility of a ranging measurement are provided. In some embodiments, a method of assessing a plausibility of a ranging measurement includes: obtaining the ranging measurement from a remote device; obtaining one or more measurements associated with the ranging measurement; and based on the one or more measurements associated with the ranging measurement, determining the plausibility of the ranging measurement. The embodiments disclosed herein determine the reliability of the measured range and thus enforce the security level of Ultra-WideBand (UWB) transactions to be secured. Some embodiments are based on existing and standardized metrics. Some embodiments include a capability to auto-assess whether it is reliable to estimate the plausibility of the transaction range. In some embodiments, the computations needed are relatively simple and can be performed by relatively simple devices.
A semiconductor device is disclosed. The semiconductor device has a substrate with a gallium nitride layer (14) disposed over the substrate. A scandium aluminum nitride layer (10) is disposed over the gallium nitride layer. A source (18) is in contact with the gallium nitride layer, and a drain (20) is spaced from the source, wherein the drain is in contact with the gallium nitride layer.
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
H01L 29/205 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds in different semiconductor regions
Lateral field excitation acoustic resonators and methods of manufacture are disclosed. In one aspect, an acoustically resonating material such as a piezoelectric film or membrane is spaced from a substrate by electrodes having an air gap therebetween. When current flows through the electrodes, lateral field acoustic waves are excited in the resonating material with relatively good coupling and adequate heat dissipation.
H03H 3/04 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks for obtaining desired frequency or temperature coefficient
H03H 9/13 - Driving means, e.g. electrodes, coils for networks consisting of piezoelectric or electrostrictive materials
100.
ANTENNA STRUCTURES FOR SPATIAL POWER-COMBINING DEVICES
Power-combining devices and, more particularly, antenna structures for spatial power-combining devices are disclosed. Spatial power-combining devices include amplifier assemblies with amplifiers and antenna structures supported by body structures. Body structures may include inner surfaces that are closer to a center axis of the spatial power-combining device where the inner surfaces have peripheral edges that are inset from remainders of the body structures. Antenna structures are disclosed that are arranged within inset portions such that the antenna structures are bounded on one end by the body structures. When assembled, a portion of a coaxial waveguide section that engages with the amplifier assemblies may bound opposing ends of the antenna structures. By not having body structures bound both ends of antenna structures, amplifier assembly design may be improved to allow smaller sizes for higher frequency operation along with improved manufacturability.
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