The invention relates to a system for manufacturing a plurality of integrated circuits, IC, mounted on a common support, the system comprising:
an input station configured (adapted, arranged) to receive at least one common support;
an output station configured (adapted, arranged) to receive at least one common support having a plurality of integrated circuits formed thereon;
a plurality of processing modules each module being operable (configured, arranged, adapted) to perform at least one of the processing steps (e.g. deposition, patterning, etching) for forming an integrated circuit on the common support;
a transfer means operable (configured, arranged, adapted) to transfer the at least one common support from the input station to the output station and to one or more of the processing modules therebetween;
control means (e.g. a control system, or at least one controller, control unit, or control module) operable to direct the at least one common support from the input station to the output station through one or more of the plurality of processing modules according to at least one processing protocol comprising a selected one of a plurality of changeable pre-programmed protocols;
the control means being operable to direct the movement of a common support from the input station to the output station and through one or more of the processing modules independently of any other common support. The invention also relates to a method for manufacturing a plurality of integrated circuits, IC, mounted on a common support.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
C23C 14/56 - Apparatus specially adapted for continuous coating; Arrangements for maintaining the vacuum, e.g. vacuum locks
C23C 16/54 - Apparatus specially adapted for continuous coating
H01L 21/677 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for conveying, e.g. between different work stations
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
A transistor is disclosed, comprising: a layer of semiconductor material comprising a first portion, a second portion, and a third portion connecting the first portion to the second portion and providing a semiconductive channel between the first portion and the second portion; a conductive first terminal covering and in electrical contact with said first portion of the layer of semiconductor material; a conductive second terminal covering and in electrical contact with said second portion of the layer of semiconductor material; a conductive gate terminal comprising a first overlapping portion covering at least part of the first terminal, and a channel portion covering the third portion of the layer of semiconductor material; and a layer of a first dielectric material, having a first dielectric constant, arranged between the first overlapping portion and the first terminal, and between the channel portion of the gate terminal and the third portion of the layer of semiconductor material. The transistor further comprises a layer of a second dielectric material having a second dielectric constant, the second dielectric constant being lower than the first dielectric constant, the layer of second dielectric material being arranged between at least part of the first overlapping portion and the first terminal, whereby at least part of the first overlapping portion of the gate terminal is separated from the first terminal by the layer of first dielectric material and the layer of second dielectric material.
A structure is disclosed, comprising: a first field effect transistor, FET, comprising a first source terminal, a first drain terminal, a first layer or body of semiconductive material arranged to provide a first semiconductive channel connecting the first source terminal to the first drain terminal, and a gate terminal arranged with respect to the first semiconductive channel such that a conductivity of the first semiconductive channel may be controlled by application of a voltage to the gate terminal; and a second FET comprising a second source terminal, a second drain terminal, a second layer or body of semiconductive material arranged to provide a second semiconductive channel connecting the second source terminal to the second drain terminal, and the gate terminal, the second conductive channel being arranged with respect to the gate terminal such that a conductivity of the second channel may be controlled by application of a voltage to the gate terminal. Methods of manufacturing such structures are also disclosed.
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/027 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or
H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching
H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
A Schottky diode comprises: a first electrode; a second electrode; and a body of semiconductive material connected to the first electrode at a first interface and connected to the second electrode at a second interface, wherein the first interface comprises a first planar region lying in a first plane and the first electrode has a first projection onto the first plane in a first direction normal to the first plane, the second interface comprises a second planar region lying in a second plane and the second electrode has a second projection onto the first plane in said first direction, at least a portion of the second projection lies outside the first projection, said second planar region is offset from the first planar region in said first direction, and one of the first interface and the second interface provides a Schottky contact.
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
H01L 29/24 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only inorganic semiconductor materials not provided for in groups , , or
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 29/22 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIBVI compounds
5.
ELECTRONIC CIRCUITS AND THEIR METHODS OF MANUFACTURE
An electronic circuit comprises a first resistor (1) and a second resistor (2). The first resistor comprises: a first sheet (10) of resistive material; and a first pair (11, 12) of conductive contacts, each arranged in electrical contact with the first sheet, and arranged such that a shortest resistive path in the first sheet between the first pair of contacts passes through the first sheet and has a length equal to a thickness (LI) of the first sheet. The second resistor comprises: a second sheet (20) of resistive material; and a second pair (21, 22) of conductive contacts, each arranged in electrical contact with the second sheet, and arranged such that a shortest resistive path (L2) in the second sheet between the second pair of contacts passes along at least a portion of a length of the second sheet.
H01L 27/01 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate comprising only passive thin-film or thick-film elements formed on a common insulating substrate
H01L 27/13 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body combined with thin-film or thick-film passive components
6.
ELECTRONIC DEVICE AND ASSOCIATED METHOD OF MANUFACTURE
An electronic device is disclosed that comprises a substrate and an electronic circuit with a layer between them. The layer comprises an electrically insulating medium containing a spatial distribution of conductive elements. The electronic circuit comprises memory contacts arranged for electrical connection to a corresponding contact on the substrate when at least one of the conductive element forms a connection between a memory contact and the corresponding contact but for electrical insulation from the corresponding contact when no conductive elements forms such a connection. A selection of the memory contacts, that is at least partially random, is thus electrically connected to the corresponding contact on the substrate. Memory circuitry is configured to store a representation of a respective electrical connection status of the memory contacts.
The present invention relates to a method of connecting circuit elements and a corresponding system for connecting circuit elements. The method includes providing a plurality of flexible circuit elements on a carrier element; forming a connecting structure. The formed connecting structure includes at least two contact points; and operative connections between each of the plurality of flexible circuit elements and the at least two contact points. The method further includes severing the operative connection between at least one of the plurality of flexible circuit elements and the at least two contact points.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
G06K 19/077 - Constructional details, e.g. mounting of circuits in the carrier
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
H05K 1/18 - Printed circuits structurally associated with non-printed electric components
A method, apparatus and system for secure one-way RFID tag identification is provided. The method comprising generating, at an RFID tag, an auxiliary identifier; generating, at an RFID tag, a secure representation based on the auxiliary identifier; transmitting, from the RFID tag and receiving at an RFID reader, one or more representations of the auxiliary identifier and the tag identifier including the secure representation; and verifying the identity of the RFID tag based on the received representations.
H04L 9/32 - Arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system
H04W 12/47 - Security arrangements using identity modules using near field communication [NFC] or radio frequency identification [RFID] modules
9.
INTEGRATED CIRCUIT ON FLEXIBLE SUBSTRATE MANUFACTURING PROCESS
The present invention provides processes for manufacturing a plurality of discrete integrated circuits (ICs) on a carrier, the process comprising the steps of: providing a carrier for a flexible substrate; depositing a flexible substrate of uniform thickness on said carrier; removing at least a portion of the thickness of the flexible substrate from at least a portion of the IC connecting areas to form channels in the flexible substrate and a plurality of IC substrate units spaced apart from one another on the carrier by said channels; forming an integrated circuit on at least one of the IC substrate units.
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
10.
ELECTRONIC CIRCUIT COMPRISING TRANSISTOR AND RESISTOR
A method of manufacturing an electronic circuit (or circuit module) (100) is disclosed. The electronic circuit comprises a transistor (1) and a resistor (2), the transistor comprising a source terminal (11), a drain terminal (12), a gate terminal (13), and a first body (10) of material providing a controllable semi-conductive channel between the source and drain terminals, and the resistor comprises a first resistor terminal (21), a second resistor terminal (22), and a second body (20) of material providing a resistive current path between the first resistor terminal and the second resistor terminal. The method comprises: forming the first body (10); and forming the second body (20), wherein the first body comprises a first quantity (100) of a metal oxide and the second body comprises a second quantity (200) of said metal oxide. Corresponding electronic circuits are disclosed.
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
H01C 1/14 - Terminals or tapping points specially adapted for resistors; Arrangements of terminals or tapping points on resistors
The present invention provides for a RFID tag assembly that is suitable for operation with at least one RFID reader assembly. The RFID tag assembly comprises, inter alia, an antenna member for transmitting and/or receiving an RFID signal, and at least one integrated circuit (IC) for processing the RFID signal and which is configured to communicate, alternatingly and sequentially in time, a first signal transmission and at least one second signal transmission, each defined by a plurality of predetermined signal transmission parameters, to the at least one RFI D reader assembly, utilising time-division multiplexing, wherein the at least one first signal transmission differs from the at least one second signal transmission in at least one of said plurality of predetermined signal transmission parameters.
G06K 19/07 - Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards with integrated circuit chips
G06K 7/10 - Methods or arrangements for sensing record carriers by corpuscular radiation
A method of manufacturing an electronic circuit comprising a first device and at least a second device is disclosed. The first device comprises a first terminal, a second terminal, and a first body of semiconductive material providing a semiconductive path between the first and second terminals, and the second device comprises a third terminal, a fourth terminal, and a second body of material providing a resistive or semiconductive current path between the third terminal and the fourth terminal. The method comprises: forming the first body; and forming the second body, wherein the first body comprises a first quantity of a metal oxide and the second body comprises a second quantity of said metal oxide. Corresponding electronic circuits are disclosed.
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 29/24 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only inorganic semiconductor materials not provided for in groups , , or
H01L 21/8256 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using technologies not covered by one of groups , or
A thin-film resistor and a method for fabricating a thin-film resistor are provided. The thin-film resistor comprises a first terminal, a second terminal, and a resistor body providing a resistive current path between the first terminal and the second terminal, and the method comprises depositing a first layer of conductive material onto at least one of the supporting structure and the resistor body, applying a first lithographic mask to the first layer, and etching the first layer to form the first terminal; and depositing a second layer of conductive material onto at least one of the supporting structure and the resistor body, applying a second lithographic mask to the second layer, and etching the second layer to form the second terminal, wherein the first lithographic mask is different to the second lithographic mask, and a lateral separation of the first terminal and the second terminal is less than an in-plane minimum feature size of the first and second lithographic masks
H01C 17/00 - Apparatus or processes specially adapted for manufacturing resistors
H01C 7/00 - Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material
H01C 17/075 - Apparatus or processes specially adapted for manufacturing resistors adapted for coating resistive material on a base by thin-film techniques
A thin-film electronic component includes a first terminal, a second terminal, and a first current path between the first terminal and the second terminal, wherein the first current path is formed from a first segment of a first material and a first segment of a second material arranged in series between the first terminal and the second terminal.
H01L 27/13 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body combined with thin-film or thick-film passive components
A thin-film integrated circuit comprising a first semiconductor device, a second semiconductor device, a first resistor, and a second resistor is provided. A semiconducting region of the first semiconductor device, a resistor body of the first resistor, a semiconducting region of the second semiconductor device, and a resistor body of the second resistor are formed from at least one of a first source material and a second source material, and a material of the resistor body of the first resistor and a material of the resistor body of the second resistor have different electrical properties.
H01C 7/00 - Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
There is provided a flexible electronic structure for bonding with an external circuit, comprising a flexible substrate, having a first surface, configured for bonding with the external circuit, and an opposing second surface, configured for engagement with a bonding tool, comprising at least one electronic component; at least one contact member, operatively coupled with said at least one electronic component and provided at said first surface of said flexible substrate, and adapted to operably interface with the external circuit after bonding, and at least one shield member, provided at said first surface so as to shieldingly overlap at least a portion of said at least one electronic component, adapted to withstand a predetermined pressure applied to said first surface and/or said opposing second surface during bonding with the external circuit.
There is provided a flexible electronic structure for bonding with an external circuit. The flexible electronic structure comprising: a flexible body having a first surface, the flexible body comprising at least one electronic component; at least one contact element configured to bond with the external circuit, the at least one contact element operatively coupled with the at least one electronic component and provided at the first surface of the flexible body, and arranged to operably interface with the external circuit after bonding, and at least one support element provided at the first surface of the flexible body, each support element arranged to contact a corresponding surface element disposed on a first surface of an external structure comprising the external circuit.
A method for fabricating a thin-film integrated circuit, IC, including a plurality of electronic components, the method comprising: forming, using a first fabrication technique, the plurality of electronic components, and forming, using a second fabrication technique, a conductive layer on the plurality of electronic components to form a redistribution layer, RDL, wherein the first fabrication technique includes photolithographic patterning, and the first fabrication technique is different to the second fabrication technique.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
An AND gate comprises: a first input; a second input; an output; and a plurality of field effect transistors, FETs, each having a respective first terminal, a respective second terminal, and a respective gate terminal to which a voltage may be applied to control a conductivity of a respective channel between the respective first terminal and the respective second terminal. The plurality of FETs comprises: a first FET having its first terminal directly connected to the first input, its second terminal directly connected to the output, and its gate terminal directly connected to the second input; a second FET having its first terminal directly connected to the first input, its second terminal directly connected to the output, and its gate terminal directly connected to the output; and a third FET having its first terminal directly connected to the second input, its second terminal directly connected to the output, and its gate terminal directly connected to the output. Also disclosed is a clock divider stage for receiving a first clock signal oscillating at a first frequency and a second clock signal, the second clock signal being an inversion of the first clock signal, and generating a first output clock signal oscillating at half of the first frequency.
e, 108, 110), having a second voltage response characteristic that is inversely correlated to said first voltage response characteristic, operatively coupled with said first signal delay circuit and configured to provide a predetermined second propagation delay, and wherein said predetermined first propagation delay and said predetermined second propagation delay are temporally matched, so as to generate an oscillating output signal (Out) of a predetermined frequency.
There is provided a dual-slope analog-to-digital converter (ADC), comprising an input signal terminal, configured to provide an analog signal, and a reference signal terminal, configured to provide a predetermined reference signal. The ADC further comprises an integrator, that is operatively coupled to said input signal terminal and said reference signal terminal via a first switch unit, said first switch unit being configured to selectively connect and disconnect said integrator to and from any one of said input signal terminal and said reference signal terminal. In addition, a voltage supply is operatively coupled to said integrator and configured to selectively provide at least one first supply voltage to said integrator via a second switch unit, a comparator is operatively coupled to an output of said integrator at a first comparator input and a predetermined threshold voltage at a second comparator input, configured to provide an actuation signal at a comparator output in accordance with a predetermined comparator logic, and a controller is adapted to control any one of said first switch unit and said second switch unit. The ADC is further adapted to provide a first voltage to said integrator from said voltage supply, so as to integrate over a first time period a first current corresponding to one of said reference signal and said analog signal, and, following said first time period, to provide a second voltage to said integrator from said voltage supply, so as to integrate over a second time period a second current corresponding to the other one of said reference signal and said analog signal, in order to generate a digital output signal corresponding to said analog signal, and wherein said first current and said second current flow in the same direction during respective said first time period and said second time period.
The present invention provides for an interposer subassembly that is suitable for an electronic system having at least one integrated circuit (1C) component. The interposer subassembly comprises a flexible base layer, having a first surface and an opposing second surface, at least one active electronic circuit component, operatively integrated within said flexible base layer, and at least one first patterned contact layer, provided on any one of said first surface and said second surface of said flexible base layer and which is configured to operably interface with said at least one active electronic circuit component and the at least one 1C component.
H01L 23/367 - Cooling facilitated by shape of device
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
23.
RFID system with improved signal transmission characteristics
A RFID (Radio Frequency Identification) system is provided, comprising at least one tag assembly having at least one tag inductance element that is operatively coupled to an integrated circuit (IC). The RFID system further comprises at least one reader assembly having at least one reader inductance element that is configured to operatively and communicatively couple with the tag assembly, and a resonance assembly having at least one first resonance element that is inductively coupleable to the at least one tag inductance element and/or at least one second resonance element that is inductively coupleable to the at least one reader inductance element, and which is adapted to provide coupled magnetic resonance signal transmission between the reader assembly and the tag assembly.
G06K 7/10 - Methods or arrangements for sensing record carriers by corpuscular radiation
G06K 19/07 - Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards with integrated circuit chips
G06K 19/077 - Constructional details, e.g. mounting of circuits in the carrier
H04B 5/00 - Near-field transmission systems, e.g. inductive loop type
An RFID tag for capacitively coupled RFID communication with an RFID reader. The RFID tag comprising an integrated circuit (IC), the IC including a first RFID tag electrode arranged to capacitively couple with a first electrode of the RFID reader to form a first capacitor, and a second RFID tag electrode arranged to capacitively couple with a second electrode of the RFID reader to form a second capacitor when the RFID tag is in a first position relative to the RFID reader; power supply circuitry configured to extract power from a first time-varying signal received from the RFID reader via at least one of the first RFID tag electrode and the second RFID tag electrode, and supply the extracted power to circuitry of the RFID tag; and data transmission circuitry configured to receive the extracted power from the power supply circuitry, and transmit data to the RFID reader via at least one of the first RFID tag electrode and the second RFID tag electrode.
G06K 7/08 - Methods or arrangements for sensing record carriers by means detecting the change of an electrostatic or magnetic field, e.g. by detecting change of capacitance between electrodes
G06K 7/10 - Methods or arrangements for sensing record carriers by corpuscular radiation
G06K 19/07 - Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards with integrated circuit chips
An electronic circuit is described, comprising: a first power rail; a second power rail; and a field effect transistor, FET, the FET comprising: a first terminal coupled directly or indirectly to the first power rail; a second terminal coupled directly or indirectly to the second power rail; a channel of semiconductive material connecting the first terminal to the second terminal; a gate terminal to which a voltage may be applied to control a conductivity of the channel, the channel providing a conduction path from the first terminal to the second terminal; and a gate dielectric arranged to insulate the gate terminal from the channel. The circuit further comprises a layer or other body of dielectric material, the gate dielectric being a first portion of the layer or other body of dielectric material. The first power rail comprises a first rail portion arranged on a first side of a second portion of the layer or other body of dielectric material, and the second power rail comprises a second rail portion arranged on a second side of the second portion of the layer or other body of dielectric material, the second side being opposite the first side. The second portion of the layer or other body of dielectric material separates the first and second rail portions and with the first and second rail portions provides a capacitance to the circuit.
H01L 23/528 - Layout of the interconnection structure
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
The invention relates to a thermode for connecting at least two components, comprising a tip having a body portion with at least two contact surface portions connected to and spaced apart from one another by a recess configured to receive a portion of one of the at least two components; and a support portion having at least one supporting surface portion configured to support a further component (being the other of the at least two components, wherein the contact surface portions and the supporting surface portion are configured to receive the at least two components between them and wherein one or both of the contact surface portions and the supporting surface portion are moveable relative to and towards one another to exert heat and/or pressure on the at least two components located between the contact surface portions and the supporting portion.
H01L 21/50 - Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
H05K 3/32 - Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
H01L 21/60 - Attaching leads or other conductive members, to be used for carrying current to or from the device in operation
A structure is disclosed, comprising: a first field effect transistor, FET, comprising a first source terminal, a first drain terminal, a first layer or body of semiconductive material arranged to provide a first semiconductive channel connecting the first source terminal to the first drain terminal, and a gate terminal arranged with respect to the first semiconductive channel such that a conductivity of the first semiconductive channel may be controlled by application of a voltage to the gate terminal; and a second FET comprising a second source terminal, a second drain terminal, a second layer or body of semiconductive material arranged to provide a second semiconductive channel connecting the second source terminal to the second drain terminal, and the gate terminal, the second conductive channel being arranged with respect to the gate terminal such that a conductivity of the second channel may be controlled by application of a voltage to the gate terminal. Methods of manufacturing such structures are also disclosed.
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/027 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or
H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching
H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
The present invention relates to a method of connecting circuit elements and a corresponding system for connecting circuit elements. The method includes providing a plurality of flexible circuit elements on a carrier element; forming a connecting structure. The formed connecting structure includes at least two contact points; and operative connections between each of the plurality of flexible circuit elements and the at least two contact points. The method further includes severing the operative connection between at least one of the plurality of flexible circuit elements and the at least two contact points.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
H01L 21/66 - Testing or measuring during manufacture or treatment
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
An AND gate comprises: a first input; a second input; an output; and a plurality of field effect transistors, FETs, each having a respective first terminal, a respective second terminal, and a respective gate terminal to which a voltage may be applied to control a conductivity of a respective channel between the respective first terminal and the respective second terminal. The plurality of FETs comprises: a first FET having its first terminal directly connected to the first input, its second terminal directly connected to the output, and its gate terminal directly connected to the second input; a second FET having its first terminal directly connected to the first input, its second terminal directly connected to the output, and its gate terminal directly connected to the output; and a third FET having its first terminal directly connected to the second input, its second terminal directly connected to the output, and its gate terminal directly connected to the output. Also disclosed is a clock divider stage for receiving a first clock signal oscillating at a first frequency and a second clock signal, the second clock signal being an inversion of the first clock signal, and generating a first output clock signal oscillating at half of the first frequency.
An electronic circuit comprises a first resistor (1) and a second resistor (2). The first resistor comprises: a first sheet (10) of resistive material; and a first pair (11, 12) of conductive contacts, each arranged in electrical contact with the first sheet, and arranged such that a shortest resistive path in the first sheet between the first pair of contacts passes through the first sheet and has a length equal to a thickness (LI) of the first sheet. The second resistor comprises: a second sheet (20) of resistive material; and a second pair (21, 22) of conductive contacts, each arranged in electrical contact with the second sheet, and arranged such that a shortest resistive path (L2) in the second sheet between the second pair of contacts passes along at least a portion of a length of the second sheet.
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 27/08 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
31.
ELECTRONIC DEVICE AND ASSOCIATED METHOD OF MANUFACTURE
An electronic device is disclosed that comprises a substrate and an electronic circuit with a layer between them. The layer comprises an electrically insulating medium containing a spatial distribution of conductive elements. The electronic circuit comprises memory contacts arranged for electrical connection to a corresponding contact on the substrate when at least one of the conductive element forms a connection between a memory contact and the corresponding contact but for electrical insulation from the corresponding contact when no conductive elements forms such a connection. A selection of the memory contacts, that is at least partially random, is thus electrically connected to the corresponding contact on the substrate. Memory circuitry is configured to store a representation of a respective electrical connection status of the memory contacts.
H04L 9/32 - Arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system
G06F 21/73 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by creating or determining hardware identification, e.g. serial numbers
32.
Capacitive detection, energy transfer, and/or data transfer system
A system is disclosed, comprising a base and at least a first moveable entity, the first moveable entity being moveable with respect to the base and positionable in at least a first position with respect to the base. The base comprises a first base electrode and a second base electrode, and the moveable entity comprises a first moveable entity electrode and a second moveable entity electrode. The electrodes are arranged such that when the moveable entity is in the first position the first base electrode and the first moveable entity electrode align to form a first capacitor and the second base electrode and second moveable entity electrode align to form a second capacitor. The first moveable entity further comprises a first resistor connecting the first moveable entity electrode to the second moveable entity electrode, and the base further comprises: signal supply means arranged to supply a time-varying electrical signal to the first base electrode; and signal detection means arranged to detect an electrical signal from the second base electrode.
G01D 5/241 - Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using electric or magnetic means influencing the magnitude of a current or voltage by varying capacitance by relative movement of capacitor electrodes
33.
ELECTRONIC CIRCUIT COMPRISING TRANSISTOR AND RESISTOR
A method of manufacturing an electronic circuit (or circuit module) (100) is disclosed. The electronic circuit comprises a transistor (1) and a resistor (2), the transistor comprising a source terminal (11), a drain terminal (12), a gate terminal (13), and a first body (10) of material providing a controllable semi-conductive channel between the source and drain terminals, and the resistor comprises a first resistor terminal (21), a second resistor terminal (22), and a second body (20) of material providing a resistive current path between the first resistor terminal and the second resistor terminal. The method comprises: forming the first body (10); and forming the second body (20), wherein the first body comprises a first quantity (100) of a metal oxide and the second body comprises a second quantity (200) of said metal oxide. Corresponding electronic circuits are disclosed.
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
A thin-film electronic component includes a first terminal, a second terminal, and a first current path between the first terminal and the second terminal, wherein the first current path is formed from a first segment of a first material and a first segment of a second material arranged in series between the first terminal and the second terminal.
H01C 7/00 - Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material
A method of manufacturing an electronic circuit comprising a first device and at least a second device is disclosed. The first device comprises a first terminal, a second terminal, and a first body of semiconductive material providing a semiconductive path between the first and second terminals, and the second device comprises a third terminal, a fourth terminal, and a second body of material providing a resistive or semiconductive current path between the third terminal and the fourth terminal. The method comprises: forming the first body; and forming the second body, wherein the first body comprises a first quantity of a metal oxide and the second body comprises a second quantity of said metal oxide. Corresponding electronic circuits are disclosed.
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
A thin-film resistor and a method for fabricating a thin-film resistor are provided. The thin-film resistor comprises a first terminal, a second terminal, and a resistor body providing a resistive current path between the first terminal and the second terminal, and the method comprises depositing a first layer of conductive material onto at least one of the supporting structure and the resistor body, applying a first lithographic mask to the first layer, and etching the first layer to form the first terminal; and depositing a second layer of conductive material onto at least one of the supporting structure and the resistor body, applying a second lithographic mask to the second layer, and etching the second layer to form the second terminal, wherein the first lithographic mask is different to the second lithographic mask, and a lateral separation of the first terminal and the second terminal is less than an in-plane minimum feature size of the first and second lithographic masks
H01C 7/00 - Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material
A thin-film integrated circuit comprising a first semiconductor device, a second semiconductor device, a first resistor, and a second resistor is provided. A semiconducting region of the first semiconductor device, a resistor body of the first resistor, a semiconducting region of the second semiconductor device, and a resistor body of the second resistor are formed from at least one of a first source material and a second source material, and a material of the resistor body of the first resistor and a material of the resistor body of the second resistor have different electrical properties.
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
38.
Integrated circuit on flexible substrate manufacturing process
The present invention provides processes for manufacturing a plurality of discrete integrated circuits (ICs) on a carrier, the process comprising the steps of: providing a carrier for a flexible substrate; depositing a flexible substrate of uniform thickness on said carrier; removing at least a portion of the thickness of the flexible substrate from at least a portion of the IC connecting areas to form channels in the flexible substrate and a plurality of IC substrate units spaced apart from one another on the carrier by said channels; forming an integrated circuit on at least one of the IC substrate units.
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
Measurement apparatus, for generating a first output signal indicative of a measurand, comprises: a first oscillator circuit and a second oscillator circuit, each oscillator circuit being arranged to generate a respective oscillating output signal and comprising at least a respective first component having a property determining a respective output frequency of the respective oscillating output signal; a sensor for sensing said measurand, the sensor comprising said first component of the first oscillator circuit, said property of said first component of the first oscillator circuit being dependent upon said measurand; and circuitry arranged to receive said oscillating output signals and generate said first output signal, said first output signal being indicative of a number of cycles of one of the first and second oscillating output signals in a time period determined by a period of the other of said first and second oscillating output signals.
G01K 7/24 - Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat using resistive elements the element being a non-linear resistance, e.g. thermistor in a specially-adapted circuit, e.g. bridge circuit
G01L 1/14 - Measuring force or stress, in general by measuring variations in capacitance or inductance of electrical elements, e.g. by measuring variations of frequency of electrical oscillators
G01N 27/12 - Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating impedance by investigating resistance of a solid body in dependence upon reaction with a fluid
G01N 27/22 - Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating impedance by investigating capacitance
G01K 7/34 - Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat using capacitative elements
G01L 1/22 - Measuring force or stress, in general by making use of electrokinetic cells, i.e. liquid-containing cells wherein an electrical potential is produced or varied upon the application of stress using resistance strain gauges
There is provided a flexible electronic structure for bonding with an external circuit, comprising a flexible substrate, having a first surface, configured for bonding with the external circuit, and an opposing second surface, configured for engagement with a bonding tool, comprising at least one electronic component; at least one contact member, operatively coupled with said at least one electronic component and provided at said first surface of said flexible substrate, and adapted to operably interface with the external circuit after bonding, and at least one shield member, provided at said first surface so as to shieldingly overlap at least a portion of said at least one electronic component, adapted to withstand a predetermined pressure applied to said first surface and/or said opposing second surface during bonding with the external circuit.
There is provided a flexible electronic structure for bonding with an external circuit. The flexible electronic structure comprising: a flexible body having a first surface, the flexible body comprising at least one electronic component; at least one contact element configured to bond with the external circuit, the at least one contact element operatively coupled with the at least one electronic component and provided at the first surface of the flexible body, and arranged to operably interface with the external circuit after bonding, and at least one support element provided at the first surface of the flexible body, each support element arranged to contact a corresponding surface element disposed on a first surface of an external structure comprising the external circuit.
A method for fabricating a thin-film integrated circuit, IC, including a plurality of electronic components, the method comprising: forming, using a first fabrication technique, the plurality of electronic components, and forming, using a second fabrication technique, a conductive layer on the plurality of electronic components to form a redistribution layer, RDL, wherein the first fabrication technique includes photolithographic patterning, and the first fabrication technique is different to the second fabrication technique.
One exemplary aspect relates to a process and apparatus for selectively changing adhesion strength between a flexible substrate and a carrier at specific locations to facilitate shipping and subsequent removal of the flexible substrate from the carrier. The process includes providing a flexible substrate comprising a plurality of integrated circuits thereon providing a carrier for the flexible substrate and adhering the flexible substrate to the carrier by creating an interface between the flexible substrate and the carrier. The process further includes changing the adhesion force between the flexible substrate and the carrier at selected locations by non-uniform treatment of the interface between the flexible substrate and the carrier with an electromagnetic radiation source (e.g. a laser, flashlamp, high powered LED, an infrared radiation source or the like) so as to decrease or increase the adhesion force between a portion of the flexible substrate and the carrier at the selected location.
A Schottky diode comprises: a first electrode; a second electrode; and a body of semiconductive material connected to the first electrode at a first interface and connected to the second electrode at a second interface, wherein the first interface comprises a first planar region lying in a first plane and the first electrode has a first projection onto the first plane in a first direction normal to the first plane, the second interface comprises a second planar region lying in a second plane and the second electrode has a second projection onto the first plane in said first direction, at least a portion of the second projection lies outside the first projection, said second planar region is offset from the first planar region in said first direction, and one of the first interface and the second interface provides a Schottky contact.
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
H01L 51/05 - Solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part; Processes or apparatus specially adapted for the manufacture or treatment of such devices, or of parts thereof specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 29/22 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIBVI compounds
H01L 29/24 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only inorganic semiconductor materials not provided for in groups , , or
There is provided an oscillator, having an input terminal (In) and an output terminal (Out), comprising a first signal delay circuit (104a- d), having a first voltage response characteristic, configured to provide a predetermined first propagation delay; a second signal delay circuit (104e, 108, 110), having a second voltage response characteristic that is inversely correlated to said first voltage response characteristic, operatively coupled with said first signal delay circuit and configured to provide a predetermined second propagation delay, and wherein said predetermined first propagation delay and said predetermined second propagation delay are temporally matched, so as to generate an oscillating output signal (Out) of a predetermined frequency.
There is provided a dual-slope analog-to-digital converter (ADC), comprising an input signal terminal, configured to provide an analog signal, and a reference signal terminal, configured to provide a predetermined reference signal. The ADC further comprises an integrator, that is operatively coupled to said input signal terminal and said reference signal terminal via a first switch unit, said first switch unit being configured to selectively connect and disconnect said integrator to and from any one of said input signal terminal and said reference signal terminal. In addition, a voltage supply is operatively coupled to said integrator and configured to selectively provide at least one first supply voltage to said integrator via a second switch unit, a comparator is operatively coupled to an output of said integrator at a first comparator input and a predetermined threshold voltage at a second comparator input, configured to provide an actuation signal at a comparator output in accordance with a predetermined comparator logic, and a controller is adapted to control any one of said first switch unit and said second switch unit. The ADC is further adapted to provide a first voltage to said integrator from said voltage supply, so as to integrate over a first time period a first current corresponding to one of said reference signal and said analog signal, and, following said first time period, to provide a second voltage to said integrator from said voltage supply, so as to integrate over a second time period a second current corresponding to the other one of said reference signal and said analog signal, in order to generate a digital output signal corresponding to said analog signal, and wherein said first current and said second current flow in the same direction during respective said first time period and said second time period.
The present invention provides for an interposer subassembly that is suitable for an electronic system having at least one integrated circuit (1C) component. The interposer subassembly comprises a flexible base layer, having a first surface and an opposing second surface, at least one active electronic circuit component, operatively integrated within said flexible base layer, and at least one first patterned contact layer, provided on any one of said first surface and said second surface of said flexible base layer and which is configured to operably interface with said at least one active electronic circuit component and the at least one 1C component.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
transferring the flexible first structure, comprising the electronic circuits, between the heated surface and the opposing surface such that the adhesive is cured by application of heat and pressure from the heated surface and the opposing surface thereby adhering the IC onto the respective first portion.
H05K 3/36 - Assembling printed circuits with other printed circuits
H05K 3/00 - Apparatus or processes for manufacturing printed circuits
H05K 3/32 - Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
A method, apparatus and system for secure one-way RFID tag identifications provided. The method comprising generating, at an RFID tag, an auxiliary identifier; generating, at an RFID tag, a secure representation based on the auxiliary identifier; transmitting, from the RFID tag and receiving at an RFID reader, one or more representations of the auxiliary identifier and the tag identifier including the secure representation; and verifying the identity of the RFID tag based on the received representations.
H04L 9/32 - Arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system
H04W 12/47 - Security arrangements using identity modules using near field communication [NFC] or radio frequency identification [RFID] modules
50.
AN RFID SYSTEM WITH IMPROVED SIGNAL TRANSMISSION CHARACTERISTICS
A RFID (Radio Frequency Identification) system is provided, comprising at least one tag assembly having at least one tag inductance element that is operatively coupled to an integrated circuit (IC). The RFID system further comprises at least one reader assembly having at least one reader inductance element that is configured to operatively and communicatively couple with the tag assembly, and a resonance assembly having at least one first resonance element that is inductively couple able to the at least one tag inductance element and/or at least one second resonance element that is inductively couple able to the at least one reader inductance element, and which is adapted to provide coupled magnetic resonance signal transmission between the reader assembly and the tag assembly.
G06K 7/10 - Methods or arrangements for sensing record carriers by corpuscular radiation
G06K 19/07 - Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards with integrated circuit chips
inter alia inter alia, an antenna member for transmitting and/or receiving an RFID signal, and at least one integrated circuit (1C) for processing the RFID signal and which is configured to communicate, alternatingly and sequentially in time, a first signal transmission and at least one second signal transmission, each defined by a plurality of predetermined signal transmission parameters, to the at least one RFI D reader assembly, utilising time-division multiplexing, wherein the at least one first signal transmission differs from the at least one second signal transmission in at least one of said plurality of predetermined signal transmission parameters.
G06K 19/07 - Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards with integrated circuit chips
52.
Capacitive detection, energy transfer, and/or data transfer system
A system is disclosed, comprising a base and at least a first moveable entity, the first moveable entity being moveable with respect to the base and positionable in at least a first position with respect to the base. The base comprises a first base electrode and a second base electrode, and the movable entity comprises a first moveable entity electrode and a second moveable entity electrode. The electrodes are arranged such that when the moveable entity is in the first position the first base electrode and the first moveable entity electrode align to form a first capacitor and the second base electrode and second moveable entity electrode align to form a second capacitor. The first moveable entity further comprises a first resistor connecting the first moveable entity electrode to the second moveable entity electrode, and the base further comprises: signal supply means arranged to supply a time-varying electrical signal to the first base electrode; and signal detection means arranged to detect an electrical signal from the second base electrode.
G01D 5/241 - Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using electric or magnetic means influencing the magnitude of a current or voltage by varying capacitance by relative movement of capacitor electrodes
53.
Apparatus and method for manufacturing plurality of electronic circuits
A method of manufacturing a plurality of electronic circuits is disclosed. Each electronic circuit comprises a respective first portion, comprising a respective group of contact pads, and a respective integrated circuit, IC, comprising a respective group of terminals and mounted on the respective group of contact pads with each terminal in electrical contact with a respective contact pad. The method comprises: providing a first structure comprising the plurality of first portions; providing a second structure comprising the plurality of ICs and a common support arranged to support the plurality of ICs; transferring said ICs from the common support onto a first roller having a removable surface portion; and transferring said ICs from the first roller onto the first structure such that each group of terminals is mounted on a respective group of contact pads.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices
An electronic circuit is described, comprising: a first power rail; a second power rail; and a field effect transistor, FET, the FET comprising: a first terminal coupled directly or indirectly to the first power rail; a second terminal coupled directly or indirectly to the second power rail; a channel of semiconductive material connecting the first terminal to the second terminal; a gate terminal to which a voltage may be applied to control a conductivity of the channel, the channel providing a conduction path from the first terminal to the second terminal; and a gate dielectric arranged to insulate the gate terminal from the channel. The circuit further comprises a layer or other body of dielectric material, the gate dielectric being a first portion of the layer or other body of dielectric material. The first power rail comprises a first rail portion arranged on a first side of a second portion of the layer or other body of dielectric material, and the second power rail comprises a second rail portion arranged on a second side of the second portion of the layer or other body of dielectric material, the second side being opposite the first side. The second portion of the layer or other body of dielectric material separates the first and second rail portions and with the first and second rail portions provides a capacitance to the circuit.
H01L 23/528 - Layout of the interconnection structure
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
The invention relates to a thermode for connecting at least two components, comprising a tip having a body portion with at least two contact surface portions connected to and spaced apart from one another by a recess configured to receive a portion of one of the at least two components; and a support portion having at least one supporting surface portion configured to support a further component (being the other of the at least two components, wherein the contact surface portions and the supporting surface portion are configured to receive the at least two components between them and wherein one or both of the contact surface portions and the supporting surface portion are moveable relative to and towards one another to exert heat and/or pressure on the at least two components located between the contact surface portions and the supporting portion.
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H05K 3/32 - Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
An RFID tag for capacitively coupled RFID communication with an RFID reader. The RFID tag comprising an integrated circuit (IC), the IC including a first RFID tag electrode arranged to capacitively couple with a first electrode of the RFID reader to form a first capacitor, and a second RFID tag electrode arranged to capacitively couple with a second electrode of the RFID reader to form a second capacitor when the RFID tag is in a first position relative to the RFID reader; power supply circuitry configured to extract power from a first time-varying signal received from the RFID reader via at least one of the first RFID tag electrode and the second RFID tag electrode, and supply the extracted power to circuitry of the RFID tag; and data transmission circuitry configured to receive the extracted power from the power supply circuitry, and transmit data to the RFID reader via at least one of the first RFID tag electrode and the second RFID tag electrode.
A structure is disclosed, comprising: a first field effect transistor, FET, comprising a first source terminal, a first drain terminal, a first layer or body of semiconductive material arranged to provide a first semiconductive channel connecting the first source terminal to the first drain terminal, and a gate terminal arranged with respect to the first semiconductive channel such that a conductivity of the first semiconductive channel may be controlled by application of a voltage to the gate terminal; and a second FET comprising a second source terminal, a second drain terminal, a second layer or body of semiconductive material arranged to provide a second semiconductive channel connecting the second source terminal to the second drain terminal, and the gate terminal, the second conductive channel being arranged with respect to the gate terminal such that a conductivity of the second channel may be controlled by application of a voltage to the gate terminal. Methods of manufacturing such structures are also disclosed.
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/027 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or
H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching
H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
An AND gate comprises:a first input;a second input;an output; and a plurality of field effect transistors, FETs, each having a respective first terminal, a respective second terminal, and a respective gate terminal to which a voltage may be applied to control a conductivity of a respective channel between the respective first terminal and the respective second terminal. The plurality of FETs comprises: a first FET having its first terminal directly connected to the first input, its second terminal directly connected to the output, and its gate terminal directly connected to the second input; a second FET having its first terminal directly connected to the first input, its second terminal directly connected to the output, and its gate terminal directly connected to the output; and a third FET having its first terminal directly connected to the second input, its second terminal directly connected to the output, and its gate terminal directly connected to the output. Also disclosed is a clock divider stage for receiving a first clock signal oscillating at a first frequency and a second clock signal, the second clock signal being an inversion of the first clock signal, and generating a first output clock signal oscillating at half of the first frequency.
H03K 3/012 - Modifications of generator to improve response time or to decrease power consumption
H03K 19/094 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
H03K 19/0944 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET
Measurement apparatus, for generating a first output signal indicative of a measurand, comprises: a first oscillator circuit and a second oscillator circuit, each oscillator circuit being arranged to generate a respective oscillating output signal and comprising at least a respective first component having a property determining a respective output frequency of the respective oscillating output signal; a sensor for sensing said measurand, the sensor comprising said first component of the first oscillator circuit, said property of said first component of the first oscillator circuit being dependent upon said measurand; and circuitry arranged to receive said oscillating output signals and generate said first output signal, said first output signal being indicative of a number of cycles of one of the first and second oscillating output signals in a time period determined by a period of the other of said first and second oscillating output signals.
The present invention provides processes for manufacturing a plurality of discrete integrated circuits (ICs) on a carrier, the process comprising the steps of: providing a carrier for a flexible substrate; depositing a flexible substrate of uniform thickness on said carrier; removing at least a portion of the thickness of the flexible substrate from at least a portion of the IC connecting areas to form channels in the flexible substrate and a plurality of IC substrate units spaced apart from one another on the carrier by said channels; forming an integrated circuit on at least one of the IC substrate units.
H01L 51/00 - Solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part; Processes or apparatus specially adapted for the manufacture or treatment of such devices, or of parts thereof
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
61.
SYSTEM AND METHOD FOR MANUFACTURING PLURALITY OF INTEGRATED CIRCUITS
The invention relates to a system for manufacturing a plurality of integrated circuits, IC, mounted on a common support, the system comprising: an input station configured (adapted, arranged) to receive at least one common support; an output station configured (adapted, arranged) to receive at least one common support having a plurality of integrated circuits formed thereon; a plurality of processing modules each module being operable (configured, arranged, adapted) to perform at least one of the processing steps (e.g. deposition, patterning, etching) for forming an integrated circuit on the common support; a transfer means operable (configured, arranged, adapted) to transfer the at least one common support from the input station to the output station and to one or more of the processing modules therebetween; control means (e.g. a control system, or at least one controller, control unit, or control module) operable to direct the at least one common support from the input station to the output station through one or more of the plurality of processing modules according to at least one processing protocol comprising a selected one of a plurality of changeable pre-programmed protocols; the control means being operable to direct the movement of a common support from the input station to the output station and through one or more of the processing modules independently of any other common support. The invention also relates to a method for manufacturing a plurality of integrated circuits, IC, mounted on a common support.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 21/677 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for conveying, e.g. between different work stations
A comparator is disclosed, for comparing a first input voltage with a second input voltage and generating a corresponding output voltage. The comparator includes a follower stage coupled to a first supply rail and a second supply rail, a follower stage input terminal for the second input voltage, and a follower stage output terminal. The comparator also includes an inverter stage comprising a first inverter stage supply terminal coupled to the first supply rail, a second inverter stage supply terminal coupled to the follower stage output terminal, an inverter stage input terminal for the first input voltage, and an inverter stage output terminal for providing an inverter stage output voltage having a first range. A signal conditioning means is coupled to the inverter stage output terminal and generates a comparator output voltage at a comparator output terminal having a second range larger than the first range.
H03K 5/24 - Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
H03K 19/094 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
A Schottky diode comprises:a first electrode;a second electrode; and a body of semiconductive material connected to the first electrode at a first interface and connected to the second electrode at a second interface,wherein the first interface comprises a first planar region lying in a first plane and the first electrode has a first projection onto the first plane in a first direction normal to the first plane, the second interface comprises a second planar region lying in a second plane and the second electrode has a second projection onto the first plane in said first direction, at least a portion of the second projection lies outside the first projection, said second planar region is offset from the first planar region in said first direction, and one of the first interface and the second interface provides a Schottky contact.
H01L 21/329 - Multistep processes for the manufacture of devices of the bipolar type, e.g. diodes, transistors, thyristors the devices comprising one or two electrodes, e.g. diodes
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
H01L 51/05 - Solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part; Processes or apparatus specially adapted for the manufacture or treatment of such devices, or of parts thereof specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/24 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only inorganic semiconductor materials not provided for in groups , , or
H01L 29/22 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIBVI compounds
A method of manufacturing an electronic circuit comprises: providing an electronic circuit having a first configuration in which the circuit comprises a resistive element having a first resistance, and irradiating at least a part of the resistive element with electromagnetic radiation to change the resistance of the resistive element from the first resistance to a second resistance, the second resistance being lower than the first resistance. A method of storing data comprises: receiving a piece of data to be stored; determining a number according to the data; and irradiating at least part of a resistive element with that number of pulses of electromagnetic radiation to change a resistance of the resistive element from a first resistance to a second resistance, the second resistance being lower than the first resistance. A difference between the first resistance and the second resistance is dependent on the number. Corresponding circuits and data storage systems are disclosed.
G11C 13/04 - Digital stores characterised by the use of storage elements not covered by groups , , or using optical elements
G11B 11/12 - Recording on, or reproducing from, the same record carrier wherein for these two operations the methods or means are covered by different main groups of groups or by different subgroups of group ; Record carriers therefor using recording by optical means
G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
G11B 9/04 - Recording or reproducing using a method or means not covered by one of the main groups ; Record carriers therefor using record carriers having variable electric resistance; Record carriers therefor
G11B 11/08 - Recording on, or reproducing from, the same record carrier wherein for these two operations the methods or means are covered by different main groups of groups or by different subgroups of group ; Record carriers therefor using recording by electric charge or by variation of electric resistance or capacitance
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
H01C 17/242 - Apparatus or processes specially adapted for manufacturing resistors adapted for trimming by removing or adding resistive material by laser
A method, apparatus and system for secure one-way RFID tag identifications provided. The method comprising generating, at an RFID tag, an auxiliary identifier; generating, at an RFID tag, a secure representation based on the auxiliary identifier; transmitting, from the RFID tag and receiving at an RFID reader, one or more representations of the auxiliary identifier and the tag identifier including the secure representation; and verifying the identity of the RFID tag based on the received representations.
H04L 9/32 - Arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system
The invention relates to a process and apparatus for selectively changing adhesion strength between a flexible substrate and a carrier at specific locations in order to facilitate shipping and subsequent removal of the flexible substrate from the carrier, the process comprising the steps of: providing a flexible substrate comprising a plurality of integrated circuits thereon; providing a carrier for the flexible substrate and adhering the flexible substrate to the carrier by creating an interface between the flexible substrate and the carrier; changing the adhesion force between the flexible substrate and the carrier at selected locations by non-uniform treatment of the interface between the flexible substrate and the carrier with an electromagnetic radiation source (e.g. a laser, flashlamp, high powered LED, an infrared radiation source or the like) so as to decrease or increase the adhesion force between a portion of the flexible substrate and the carrier at the selected location.
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
67.
METHODS AND APPARATUS FOR MANUFACTURING A PLURALITY OF ELECTRONIC CIRCUITS
The present invention relates to a method and apparatus for manufacturing a plurality of electronic circuits (7), each electronic circuit (7) comprising a respective flexible first portion (5), comprising a respective group of contact pads (contacts) (35), and a respective flexible electronic component (a flexible integrated circuit, IC) (3), comprising a respective group of terminals (37) and mounted on the respective group of contact pads (35) with each terminal (37) in electrical contact with a respective contact pad (35), the method comprising: • providing (e.g. manufacturing) a flexible first structure (flexible substrate) (15), e.g. a flexible web, comprising the plurality of flexible first portions (5); • providing (e.g. manufacturing) a second structure comprising the plurality of flexible ICs (3) and a common support (11) arranged to support the plurality of flexible ICs (3); • dispensing an adhesive (9) onto the flexible first structure (15) and/ or onto the flexible ICs (3); • transferring said flexible ICs (3) from the common support (11) onto the flexible first structure (15) such that each group of terminals (37) is mounted on (brought into electrical contact with) a respective group of contact pads (35) to form an electronic circuit (7), • providing a heated surface (23a) and an opposing surface (23b, 117) (a pair of nip rollers (17a, 17b) or a roller (17a) and a planar surface (117)) together having a gap (19) therebetween, • transferring the flexible first structure (15), comprising the electronic circuits (7), between the heated surface (23a) and the opposing surface (23b, 117) such that the adhesive (9) is cured by application of heat and pressure from the heated surface (23a) and the opposing surface (23b, 117), thereby adhering the IC (3) onto the respective first portion (5). A silicone paper layer (26) may be located between the electronic circuits (7) and the heated surface (23a) to protect the heated surface (23a) from fouling with excess adhesive.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 21/60 - Attaching leads or other conductive members, to be used for carrying current to or from the device in operation
H01L 21/68 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for positioning, orientation or alignment
68.
Apparatus and method for manufacturing plurality of electronic circuits
A method of manufacturing a plurality of electronic circuits is disclosed. Each electronic circuit comprises a respective first portion, comprising a respective group of contact pads, and a respective integrated circuit, IC, comprising a respective group of terminals and mounted on the respective group of contact pads with each terminal in electrical contact with a respective contact pad. The method comprises: providing a first structure comprising the plurality of first portions; providing a second structure comprising the plurality of ICs and a common support arranged to support the plurality of ICs; transferring said ICs from the common support onto a first roller; transferring said ICs from the first roller onto a second roller; and transferring said ICs from the second roller onto the first structure such that each group of terminals is mounted on a respective group of contact pads.
A method of manufacturing a plurality of electronic circuits is disclosed. Each electronic circuit comprises a respective first portion, comprising a respective group of contact pads, and a respective integrated circuit, IC, comprising a respective group of terminals and mounted on the respective group of contact pads with each terminal in electrical contact with a respective contact pad. The method comprises: providing a first structure comprising the plurality of first portions; providing a second structure comprising the plurality of ICs and a common support arranged to support the plurality of ICs; transferring said ICs from the common support onto a first roller having a removable surface portion; and transferring said ICs from the first roller onto the first structure such that each group of terminals is mounted on a respective group of contact pads.
A structure is disclosed, comprising: a first field effect transistor, FET, comprising a first source terminal, a first drain terminal, a first layer or body of semiconductive material arranged to provide a first semiconductive channel connecting the first source terminal to the first drain terminal, and a gate terminal arranged with respect to the first semiconductive channel such that a conductivity of the first semiconductive channel may be controlled by application of a voltage to the gate terminal; and a second FET comprising a second source terminal, a second drain terminal, a second layer or body of semiconductive material arranged to provide a second semiconductive channel connecting the second source terminal to the second drain terminal, and the gate terminal, the second conductive channel being arranged with respect to the gate terminal such that a conductivity of the second channel may be controlled by application of a voltage to the gate terminal. Methods of manufacturing such structures are also disclosed.
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
A transistor is disclosed, comprising: a layer of semiconductor material comprising a first portion, a second portion, and a third portion connecting the first portion to the second portion and providing a semiconductive channel between the first portion and the second portion; a conductive first terminal covering and in electrical contact with said first portion of the layer of semiconductor material; a conductive second terminal covering and in electrical contact with said second portion of the layer of semiconductor material; a conductive gate terminal comprising a first overlapping portion covering at least part of the first terminal, and a channel portion covering the third portion of the layer of semiconductor material; and a layer of a first dielectric material, having a first dielectric constant, arranged between the first overlapping portion and the first terminal, and between the channel portion of the gate terminal and the third portion of the layer of semiconductor material. The transistor further comprises a layer of a second dielectric material having a second dielectric constant, the second dielectric constant being lower than the first dielectric constant, the layer of second dielectric material being arranged between at least part of the first overlapping portion and the first terminal, whereby at least part of the first overlapping portion of the gate terminal is separated from the first terminal by the layer of first dielectric material and the layer of second dielectric material.
A method of manufacturing an electronic device comprising a first terminal (e.g. a source terminal), a second terminal (e.g. a drain terminal), a semiconductor channel connecting the first and second terminals and a gate terminal to which a potential may be applied to control a conductivity of the channel. The method comprises a first exposure of a photoresist from above the substrate using a mask and a second exposure from below, wherein in the second exposure the first and second terminals shield a part of the photoresist from exposure. An intermediate step reduces the solubility of the photoresist exposed in the first exposure. A window is formed in the photoresist at the location which was shielded by the mask, but exposed to radiation from below. Semiconductor material, dielectric material and conductor material are deposited inside the window to form a semiconductor channel, gate dielectric, and a gate terminal, respectively.
H01L 27/22 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate using similar magnetic field effects
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
An antenna comprises: a first terminal; a second terminal; and a winding, having an inductance, comprising a plurality of turns and connected between the first and second terminals such that a change in magnetic flux linking the winding generates a corresponding voltage between said terminals. The winding comprises a conductive element connected to the first and second terminals and extending around said turns from the first terminal to the second terminal and having a thickness not exceeding X μm along a length of the conductive element from the first to the second terminal and a width not exceeding X μm along said length, where X is less than or equal to 10, whereby said conductive element is substantially non-visible to a naked human eye.
H01Q 1/44 - ANTENNAS, i.e. RADIO AERIALS - Details of, or arrangements associated with, antennas using equipment having another main function to serve additionally as an antenna
H01Q 1/22 - Supports; Mounting means by structural association with other equipment or articles
H01Q 7/00 - Loop antennas with a substantially uniform current distribution around the loop and having a directional radiation pattern in a plane perpendicular to the plane of the loop
G06K 19/077 - Constructional details, e.g. mounting of circuits in the carrier
G06K 7/10 - Methods or arrangements for sensing record carriers by corpuscular radiation
G08B 13/24 - Electrical actuation by interference with electromagnetic field distribution
H04B 5/00 - Near-field transmission systems, e.g. inductive loop type
74.
APPARATUS AND METHOD FOR MANUFACTURING PLURALITY OF ELECTRONIC CIRCUITS
A method of manufacturing a plurality of electronic circuits is disclosed. Each electronic circuit comprises a respective first portion, comprising a respective group of contact pads, and a respective integrated circuit, IC, comprising a respective group of terminals and mounted on the respective group of contact pads with each terminal in electrical contact with a respective contact pad. The method comprises: providing a first structure comprising the plurality of first portions; providing a second structure comprising the plurality of ICs and a common support arranged to support the plurality of ICs; transferring said ICs from the common support onto a first roller; transferring said ICs from the first roller onto a second roller; and transferring said ICs from the second roller onto the first structure such that each group of terminals is mounted on a respective group of contact pads.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 21/60 - Attaching leads or other conductive members, to be used for carrying current to or from the device in operation
75.
Capacitive detection, energy transfer, and/or data transfer system
A system is disclosed, comprising a base and at least a first moveable entity, the first moveable entity being moveable with respect to the base and positionable in at least a first position with respect to the base. The base comprises a first base electrode and a second base electrode, and the moveable entity comprises a first moveable entity electrode and a second moveable entity electrode. The electrodes are arranged such that when the moveable entity is in the first position the first base electrode and the first moveable entity electrode align to form a first capacitor and the second base electrode and second moveable entity electrode align to form a second capacitor. The first moveable entity further comprises a first resistor connecting the first moveable entity electrode to the second moveable entity electrode, and the base further comprises: signal supply means arranged to supply a time-varying electrical signal to the first base electrode; and signal detection means arranged to detect an electrical signal from the second base electrode.
G01D 5/241 - Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using electric or magnetic means influencing the magnitude of a current or voltage by varying capacitance by relative movement of capacitor electrodes
76.
Semiconductor electronic devices and methods of manufacture thereof
A method of manufacturing an electronic device comprises: providing a layer of semiconductor material comprising a first portion, a second portion, and a third portion, the third portion connecting the first portion to the second portion and providing a semiconductive channel for electrical current flow between the first and second portions; providing a gate terminal arranged with respect to said third portion such that a voltage may be applied to the gate terminal to control an electrical conductivity of said channel; and processing at least one of the first and second portions so as to have an electrical conductivity greater than an electrical conductivity of the channel when no voltage is applied to the gate terminal. In certain embodiments, the processing comprises exposing at least one of the first and second portions to electromagnetic radiation. The first and second portions may be laser annealed to increase their conductivities.
H01L 51/00 - Solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part; Processes or apparatus specially adapted for the manufacture or treatment of such devices, or of parts thereof
H01L 21/428 - Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
H01L 51/10 - Solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part; Processes or apparatus specially adapted for the manufacture or treatment of such devices, or of parts thereof specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier - Details of devices
A method of manufacturing an electronic circuit comprises: providing an electronic circuit having a first configuration in which the circuit comprises a resistive element having a first resistance, and irradiating at least a part of the resistive element with electromagnetic radiation to change the resistance of the resistive element from the first resistance to a second resistance, the second resistance being lower than the first resistance. A method of storing data comprises: receiving a piece of data to be stored; determining a number according to the data; and irradiating at least part of a resistive element with that number of pulses of electromagnetic radiation to change a resistance of the resistive element from a first resistance to a second resistance, the second resistance being lower than the first resistance. A difference between the first resistance and the second resistance is dependent on the number. Corresponding circuits and data storage systems are disclosed.
G02F 1/13 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
G11C 13/04 - Digital stores characterised by the use of storage elements not covered by groups , , or using optical elements
G11B 11/12 - Recording on, or reproducing from, the same record carrier wherein for these two operations the methods or means are covered by different main groups of groups or by different subgroups of group ; Record carriers therefor using recording by optical means
G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
G11B 9/04 - Recording or reproducing using a method or means not covered by one of the main groups ; Record carriers therefor using record carriers having variable electric resistance; Record carriers therefor
G11B 11/08 - Recording on, or reproducing from, the same record carrier wherein for these two operations the methods or means are covered by different main groups of groups or by different subgroups of group ; Record carriers therefor using recording by electric charge or by variation of electric resistance or capacitance
An electronic circuit comprises: an input terminal; an output terminal; first and second supply rails; first, second, third, and fourth field effect transistors, FETs, each of a first type and each having respective gate, source and drain terminals; and first and second loads. The source of the first FET is connected to the first supply rail, the drain of the first FET and the source of the second FET are connected to the output terminal, the drain of the second FET is connected to the second supply rail, the gate of the third FET and the gate of the fourth FET are connected to the input terminal, the drain of the third FET is connected to the second supply rail, the first load is connected between the first supply rail and the source of the third FET, and the second load is connected between the drain of the fourth FET and the second supply rail. In one aspect of the invention, the gate of the first FET is connected to a node between the source of the third FET and the first load such that a voltage at the source of the third FET is applied to the gate of the first FET, and the gate of the second FET is connected to a node between the drain of the fourth FET and the second load such that a voltage at the drain of the fourth FET is applied to the gate of the second FET.
H03K 19/0944 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET
H03K 17/16 - Modifications for eliminating interference voltages or currents
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
A comparator is disclosed, for comparing a first input voltage (e+) with a second input voltage (e-) and generating a corresponding output voltage (out). The comparator comprises: a first input terminal (e+) for receiving the first input voltage: a second input terminal (e-) for receiving the second input voltage; an output terminal (out) for outputting the output voltage; a first supply rail (VCC) for providing a first supply voltage; and a second supply rail (VDD) for providing a second supply voltage. The comparator further comprises: a follower stage comprising a first follower stage supply terminal coupled to the first supply rail, a second follower stage supply terminal coupled to the second supply rail, a follower stage input terminal coupled to the second input terminal, and a follower stage output terminal for providing a follower stage output voltage; and an inverter stage comprising a first inverter stage supply terminal coupled to the first supply rail, a second inverter stage supply terminal coupled to the follower stage output terminal, an inverter stage input terminal coupled to the first input terminal, and an inverter stage output terminal for providing an inverter stage output voltage and coupled to the output terminal.
H03K 5/24 - Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
H03K 19/094 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
A method of manufacturing an electronic device comprising a first terminal (e.g. a source terminal), a second terminal (e.g. a drain terminal), a semiconductor channel connecting the first and second terminals and a gate terminal to which a potential may be applied to control a conductivity of the channel. The method comprises a first exposure of a photoresist from above the substrate using a mask and a second exposure from below, wherein in the second exposure the first and second terminals shield a part of the photoresist from exposure. An intermediate step reduces the solubility of the photoresist exposed in the first exposure. A window is formed in the photoresist at the location which was shielded by the mask, but exposed to radiation from below. Semiconductor material, dielectric material and conductor material are deposited inside the window to form a semiconductor channel, gate dielectric, and a gate terminal, respectively.
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
A system is disclosed, comprising a base and at least a first moveable entity, the first moveable entity being moveable with respect to the base and positionable in at least a first position with respect to the base. The base comprises a first base electrode and a second base electrode, and the moveable entity comprises a first moveable entity electrode and a second moveable entity electrode. The electrodes are arranged such that when the moveable entity is in the first position the first base electrode and the first moveable entity electrode align to form a first capacitor and the second base electrode and second moveable entity electrode align to form a second capacitor. The first moveable entity further comprises a first resistor connecting the first moveable entity electrode to the second moveable entity electrode, and the base further comprises: signal supply means arranged to supply a time-varying electrical signal to the first base electrode; and signal detection means arranged to detect an electrical signal from the second base electrode.
G01D 5/241 - Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using electric or magnetic means influencing the magnitude of a current or voltage by varying capacitance by relative movement of capacitor electrodes
A method of manufacturing an electronic circuit comprises: providing an electronic circuit having a first configuration in which the circuit comprises a resistive element having a first resistance,and irradiating at least a part of the resistive element with electromagnetic radiation to change the resistance of the resistive element from the first resistance to a second resistance, the second resistance being lower than the first resistance.A method of storing data comprises: receiving a piece of data to be stored; determining a number according to the data; and irradiating at least part of a resistive element with that number of pulses of electromagnetic radiation to change a resistance of the resistive element from a first resistance to a second resistance, the second resistance being lower than the first resistance. A difference between the first resistance and the second resistance is dependent on the number. Corresponding circuits and data storage systems are disclosed.
G11C 13/04 - Digital stores characterised by the use of storage elements not covered by groups , , or using optical elements
G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
G11B 11/12 - Recording on, or reproducing from, the same record carrier wherein for these two operations the methods or means are covered by different main groups of groups or by different subgroups of group ; Record carriers therefor using recording by optical means
An antenna comprises: a first terminal; a second terminal; and a winding, having an inductance, comprising a plurality of turns and connected between the first and second terminals such that a change in magnetic flux linking the winding generates a corresponding voltage between said terminals. The winding comprises a conductive element connected to the first and second terminals and extending around said turns from the first terminal to the second terminal and having a thickness not exceeding Χμm along a length of the conductive element from the first to the second terminal and a width not exceeding Χμm along said length, where X is less than or equal to 10, whereby said conductive element is substantially non-visible to a naked human eye.
H01Q 1/38 - Structural form of radiating elements, e.g. cone, spiral, umbrella formed by a conductive layer on an insulating support
H01Q 1/44 - ANTENNAS, i.e. RADIO AERIALS - Details of, or arrangements associated with, antennas using equipment having another main function to serve additionally as an antenna
H01Q 7/00 - Loop antennas with a substantially uniform current distribution around the loop and having a directional radiation pattern in a plane perpendicular to the plane of the loop
H01Q 1/22 - Supports; Mounting means by structural association with other equipment or articles
G08B 13/24 - Electrical actuation by interference with electromagnetic field distribution
An electronic circuit comprises: an input terminal; an output terminal; first and second supply rails; first, second, third, and fourth field effect transistors, FETs, each of a first type and each having respective gate, source and drain terminals; and first and second loads. The source of the first FET is connected to the first supply rail, the drain of the first FET and the source of the second FET are connected to the output terminal, the drain of the second FET is connected to the second supply rail, the gate of the third FET and the gate of the fourth FET are connected to the input terminal, the drain of the third FET is connected to the second supply rail, the first load is connected between the first supply rail and the source of the third FET, and the second load is connected between the drain of the fourth FET and the second supply rail. In one aspect of the invention, the gate of the first FET is connected to a node between the source of the third FET and the first load such that a voltage at the source of the third FET is applied to the gate of the first FET, and the gate of the second FET is connected to a node between the drain of the fourth FET and the second load such that a voltage at the drain of the fourth FET is applied to the gate of the second FET.
H03K 19/0944 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET
85.
Substantially planar electronic devices and circuits
A method of manufacturing a substantially planar electronic device is disclosed. The method employs a resist having three different thicknesses used for defining different structures in a single masking step. Exemplary structures are substantially planar transistors having side-gates and diodes.
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
H01L 51/40 - Processes or apparatus specially adapted for the manufacture or treatment of such devices or of parts thereof
H01L 21/336 - Field-effect transistors with an insulated gate
A method of manufacturing a transistor comprising: providing a substrate, a region of semiconductive material supported by the substrate, and a region of electrically conductive material supported by the region of semiconductive material; forming at least one layer of resist material over said regions to form a covering of resist material over said regions; forming a depression in a surface of the covering of resist material, said depression extending over a first portion of said region of conductive material, said first portion separating a second portion of the conductive region from a third portion of the conductive region; removing resist material located under said depression so as to form a window, through said covering, exposing said first portion of the electrically conductive region; removing said first portion to expose a connecting portion of the region of semiconductive material, said connecting portion connecting the second portion to the third portion of the conductive region; forming a layer of dielectric material over the exposed portion of the region of semiconductive material; and depositing electrically conductive material to form a layer of electrically conductive material over said layer of dielectric material, the layer of dielectric material electrically isolating the layer of electrically conductive material from the second and third portions of the conductive region.
H01L 21/12 - Application of an electrode to the exposed surface of the selenium or tellurium after the selenium or tellurium has been applied to the foundation plate
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 21/027 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or
H01L 31/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
B82Y 10/00 - Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
B82Y 30/00 - Nanotechnology for materials or surface science, e.g. nanocomposites
B82Y 40/00 - Manufacture or treatment of nanostructures
H01L 51/05 - Solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part; Processes or apparatus specially adapted for the manufacture or treatment of such devices, or of parts thereof specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 51/00 - Solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part; Processes or apparatus specially adapted for the manufacture or treatment of such devices, or of parts thereof
88.
Semiconductor electronic devices and methods of manufacture thereof
A method of manufacturing an electronic device comprises: providing a layer of semiconductor material comprising a first portion, a second portion, and a third portion, the third portion connecting the first portion to the second portion and providing a semiconductive channel for electrical current flow between the first and second portions; providing a gate terminal arranged with respect to said third portion such that a voltage may be applied to the gate terminal to control an electrical conductivity of said channel; and processing at least one of the first and second portions so as to have an electrical conductivity greater than an electrical conductivity of the channel when no voltage is applied to the gate terminal. In certain embodiments, the processing comprises exposing at least one of the first and second portions to electromagnetic radiation. The first and second portions may be laser annealed to increase their conductivities.
A method of manufacturing a substantially planar electronic device is disclosed. The method employs a resist having three different thicknesses used for defining different structures in a single masking step. Examplary structures are substantially planar transistors having side-gates and diodes.
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
A method of manufacturing an electronic device comprising a first terminal (e.g. a source terminal), a second terminal (e.g. a drain terminal), a semiconductor channel connecting the first and second terminals and a gate terminal to which a potential may be applied to control a conductivity of the channel. The method comprises a first exposure of a photoresist from above the substrate using a mask and a second exposure from below the substrate, wherein in the second exposure the first and second terminals shield a part of the photoresist from exposure. An intermediate step reduces the solubility of the photoresist exposed in the first exposure. A window is formed in the photoresist at the location which was shielded by the mask, but exposed to radiation from below. Semiconductor material, dielectric material and conductor material are deposited inside the window to form a semiconductor channel, gate dielectric, and a gate terminal, respectively.
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
A transistor includes a substrate, a source terminal and a drain terminal, each terminal being supported by the substrate, and the source and drain terminal being separated by a portion of the substrate, a layer of semiconductive material deposited so as to cover the portion of the substrate and to connect the source terminal to the drain terminal, a layer of dielectric material deposited so as to cover at least a portion of the layer of semiconductive material, and a layer of electrically conductive material deposited so as to cover at least a portion of the layer of dielectric material. The layer of electrically conductive material providing a gate terminal to which a potential may be applied to control a conductivity of the layer of semiconductive material connecting the source and drain terminals.
H01L 51/05 - Solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part; Processes or apparatus specially adapted for the manufacture or treatment of such devices, or of parts thereof specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
A method of manufacturing a transistor comprising: providing a substrate, a region of semiconductive material supported by the substrate, and a region of electrically conductive material supported by the region of semiconductive material;forming at least one layer of resist material over said regions to form a covering of resist material over said regions; forming a depression in a surface of the covering of resist material, said depression extending over a first portion of said region of conductive material, said first portion separating a second portion of the conductive region from a third portion of the conductive region;removing resist material located under said depression so as to form a window, through said covering, exposing said first portion of the electrically conductive region;removing said first portion to expose a connecting portion of the region of semiconductive material, said connecting portion connecting the second portion to the third portion of the conductive region;forming a layer of dielectric material over the exposed portion of the region of semiconductive material; and depositing electrically conductive material to form a layer of electrically conductive material over said layer of dielectric material, the layer of dielectric material electrically isolating the layer of electrically conductive material from the second and third portions of the conductive region.
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
93.
Electronic circuits including planar electronic devices
filling said first hole at least partly with electrically conductive material so as to provide an electrical connection between the first conductive track and one of the first and second terminals.
A method of manufacturing an electronic device comprises: providing a layer of semiconductor material comprising a first portion, a second portion, and a third portion, the third portion connecting the first portion to the second portion and providing a semiconductive channel for electrical current flow between the first and second portions; providing a gate terminal arranged with respect to said third portion such that a voltage may be applied to the gate terminal to control an electrical conductivity of said channel; and processing at least one of the first and second portions so as to have an electrical conductivity greater than an electrical conductivity of the channel when no voltage is applied to the gate terminal. In certain embodiments, the processing comprises exposing at least one of the first and second portions to electromagnetic radiation. The first and second portions may be laser annealed to increase their conductivities.
A method of manufacturing an electronic device, comprising a layer of semiconductive material and at least one insulative feature arranged to interrupt the layer of semiconductive material, comprises: providing a layer of semiconductive material, and a layer of compressible material supporting the layer of semiconductive material; and forming the or each insulative feature by a method comprising displacing a respective selected portion of the layer of semiconductive material towards the compressible material so as to compress compressible material under the or each displaced portion and separate at least partly the or each displaced portion from undisplaced semiconductive material.
H01L 51/00 - Solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part; Processes or apparatus specially adapted for the manufacture or treatment of such devices, or of parts thereof
H01L 27/28 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including components using organic materials as the active part, or using a combination of organic materials with other materials as the active part
H01L 51/05 - Solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part; Processes or apparatus specially adapted for the manufacture or treatment of such devices, or of parts thereof specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier
A method of manufacturing a structure comprising substantially planar electronic devices comprises providing an active material layer having a plurality of insulative features formed therein. The features at least partly inhibit electrical current flow and define at least a first substantially planar electronic device in the layer having at least first and second terminals comprising an area of the active material layer. A patterned dielectric layer having an exposed surface patterned with at least a first depression arranged over the first terminal is formed over the active material layer. Dielectric material is removed from at least a base of the first depression to expose a first terminal surface and form a hole through the dielectric material to the first terminal. The hole is at least partly filled with electrically conductive material to form an electrical connection to the first terminal. Corresponding structures and electrical circuits are also described and claimed.
A method of manufacturing a transistor comprises: providing a substrate and a region of electrically conductive material supported by the substrate; forming at least one layer of resist material over said region to form a covering of resist material over said region; forming a depression in a surface of the covering of resist material, said depression extending over a first portion of said region, said first portion separating a second portion of the region from a third portion of the region; removing resist material located under said depression so as to form a window, through said covering, exposing said first portion of the electrically conductive region; removing said first portion to expose a portion of substrate separating the second portion from the third portion of the region; depositing semiconductive material at least inside the window to form a layer of semiconductive material connecting the second portion to the third portion; depositing dielectric material to form a layer of dielectric material over said layer of semiconductive material; depositing electrically conductive material to form a layer of electrically conductive material over said layer of dielectric material; and removing resist material at least from around said window so as to expose the second and third portions, whereby said second and third portions provide a source terminal and a drain terminal respectively and the layer of electrically conductive material provides a gate terminal to which a potential may be applied to control a conductivity of the layer of semiconductive material connecting the second and third portions. In another aspect, the method begins with separate source and drain terminals provided on a common substrate. Corresponding transistors, logic gates, arrays, and electronic circuits are described.
H01L 21/336 - Field-effect transistors with an insulated gate
H01L 21/77 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
98.
ELECTRONIC CIRCUITS INCLUDING PLANAR ELECTRONIC DEVICES
A method comprises: forming a structure comprising a layer of active material (1), a first conductive track (2) separated from the layer of active material by a layer of insulative material ( 3 ), the layer of active material having a plurality of insulative features (110) formed therein, the insulative features defining at least a first substantially planar electronic device comprising at least a respective first terminal (11) and a respective second terminal (12), and at least a portion of said first conductive track overlapping one of the first and second terminals; forming a first hole (4) extending through the layer of insulative material and connecting an overlapping portion of the first conductive track to one of the first and second terminals; and filling said first hole at least partly with electrically conductive material.
A method of manufacturing a structure comprising at least one substantially planar electronic device is provided. The method comprises: providing a layer of active material (10) having a plurality of insulative features (12) formed therein, each insulative feature at least partly inhibiting electrical current flow in said layer, and the plurality of insulative features defining at least a first substantially planar electronic device in said layer having at least a respective first terminal (31) and a respective second terminal (32), each terminal comprising a respective area of the layer of active material; forming a patterned layer of dielectric material (2) over the layer of active material, the patterned layer of dielectric material having an exposed surface patterned with at least a first depression (221) arranged over said first terminal; removing dielectric material at least from a base of said first depression to expose a surface of the first terminal and form a first hole (201) through the dielectric material to the first terminal; and filling, at least partly, said first hole with electrically conductive material (4) to form an electrical connection to the first terminal. Corresponding structures and electrical circuits are also described and claimed.
A method of manufacturing an electronic device, comprising a layer of semiconductive material and at least one insulative feature arranged to interrupt the layer of semiconductive material, comprises: providing a layer of semiconductive material, and a layer of compressible material supporting the layer of semiconductive material; and forming the or each insulative feature by a method comprising displacing a respective selected portion of the layer of semiconductive material towards the compressible material so as to compress compressible material under the or each displaced portion and separate at least partly the or each displaced portion from undisplaced semiconductive material.
H01L 51/00 - Solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part; Processes or apparatus specially adapted for the manufacture or treatment of such devices, or of parts thereof
H01L 27/28 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including components using organic materials as the active part, or using a combination of organic materials with other materials as the active part
H01L 51/05 - Solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part; Processes or apparatus specially adapted for the manufacture or treatment of such devices, or of parts thereof specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier
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