A method to drive a digital to analog converter (DAC), the method including setting a reference current for the DAC with a reference current source, a base voltage being responsive to changes in a reference voltage at a reference node coupled with the reference current source; sensing a change in the reference voltage; and adaptively steadying the base voltage based on the change in the reference voltage to maintain proportionality between an output current of the DAC and the reference current.
In an embodiment, a method includes: providing a voltage setpoint to a voltage converter; generating an output voltage at a voltage rail with the voltage converter based on the voltage setpoint; when the voltage setpoint is transitioning from a first voltage setpoint to a second voltage setpoint that has a lower magnitude than the first voltage setpoint, providing a first constant current to a first node coupled to a control terminal of an output transistor to turn on the output transistor, where the output transistor includes a source terminal coupled to a first terminal of a first resistor, and where a current path of the output transistor is coupled to the voltage rail; and turning off the output transistor after the output voltage reaches the target output voltage corresponding to the second voltage setpoint.
G05F 1/56 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
3.
BIAXIAL MICROELECTROMECHANICAL MIRROR DEVICE WITH PIEZOELECTRIC ACTUATION
A microelectromechanical-mirror device has a fixed structure defining an external frame delimiting a cavity, an internal frame arranged above the cavity and defining a window, and a tiltable structure with a reflective surface and arranged in the window. Elastically coupled to the internal frame by first and second coupling elastic elements. An actuation structure is coupled to the internal frame to cause the rotation of the tiltable structure around first and second axes. The actuation structure has a first pair of driving arms, elastically coupled to the internal frame and carrying piezoelectric material regions to cause rotation of the tiltable structure around the first axis, and a further pair of driving arms carrying piezoelectric material regions to cause rotation of the tiltable structure around the second axis and interposed between the fixed structure and the internal frame, to which they are elastically coupled by first and second suspension elastic elements.
G02B 26/08 - Optical devices or arrangements for the control of light using movable or deformable optical elements for controlling the direction of light
B81B 3/00 - Devices comprising flexible or deformable elements, e.g. comprising elastic tongues or membranes
G03B 21/00 - Projectors or projection-type viewers; Accessories therefor
4.
METHOD OF CALIBRATING A CLOCK SIGNAL, AND CORRESPONDING ELECTRONIC DEVICE AND SYSTEM
A method includes providing a reference clock signal having a reference period, providing a sampling clock signal having a sampling clock period shorter than the reference period of the reference clock signal, measuring the first subperiod as a first ratio of the first subperiod to the period of the sampling clock signal, measuring the second subperiod as a second ratio of the second subperiod to the period of the sampling clock signal, detecting a starting edge of a clock signal having a clock period greater than the reference period, producing a reconstructed reference signal based on the first ratio, the second ratio, and the detected starting edge, comparing the clock period of the clock signal with a period of the reconstructed reference signal to obtain a differential signal indicating a difference therebetween, and providing the differential signal to user circuitry for calibrating the clock signal.
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
H03K 5/26 - Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being duration, interval, position, frequency, or sequence
5.
DEVICE WITH CLIENT CONFIGURATION AND RELATED METHOD
A device includes an interface, which, in operation, couples to a non-volatile memory. The device includes circuitry coupled to the interface. The circuitry, in operation: reads a data configuration structure stored on the non-volatile memory, the data configuration structure being associated with a client circuit of a plurality of client circuits; and configures the client circuit, the configuring including writing data words of the data configuration structure to the client circuit, the writing including determining an address of the client circuit, the address being associated with at least one of the data words, the determining being based on number of data words in the data configuration structure.
An ESD protection circuit includes a terminal connected to the cathode of a first diode and to the anode of a second diode, where the cathode of the second diode is not made of epitaxial silicon.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
A device that provides high impedance contact pads for an electrostatic charge sensor. The contact pads are shared between the electrostatic charge sensor and drivers. The contact pads are set to a high impedance state by reducing current leakage through the drivers. Compared to electrostatic charge sensor with low impedance contact pads, the electrostatic charge sensor disclosed herein has high sensitivity, and is able to detect weak electrostatic fields.
A system for determining a fly height includes a first head of a disk drive, a second head of the disk drive, a capacitive sensor circuit coupled to the first head and the second head, and a logic device coupled to the capacitive sensor circuit. The capacitive sensor circuit is configured to measure a first capacitance between the first head and the first disk, remove noise from the first capacitance using a second capacitance between the second head and the second disk, and based thereon determine a corrected first capacitance. The logic device is configured to determine the fly height between the first head and the first disk using the corrected first capacitance.
A slave provides second data bits and ECC bits in response to a master read request. First data bits are generated by selecting between the second data bits and third data bits produced from error correcting the second data bits. The third data bits are generated with a delay of one clock cycle with respect to the second data bits. If an address of the read request is stored to a memory, a control signal is set indicating that the first data bits are invalid and this drives selection of the third data bits (with the first data bits now being valid in a following clock cycle). If an error signal is asserted when the address is not stored to the memory, action is taken to store the address to the memory and a further control signal is set to indicate that the read request should be repeated.
A system a ring oscillator configured to produce a set of clock signals having the same clock period and a mutual time delay between respective clock signal edges. Comparator circuits are coupled to first and second input nodes and produce a set of comparison signals according to a respective sequence of comparison phases. A set of synchronization circuits is coupled to the ring oscillator and to the plurality of comparator circuits. The synchronization circuits allot, to each one of the comparator circuits, respective time windows for communication over respective communication lines of the comparison signals. The respective time windows are synchronized based on the clock signals. A multiplexer couples the respective communication lines to an output line to sequentially enable each of the comparator circuits to sequentially output respective comparison signals over the output line for the respective time windows thereby forming a composite comparison signal evolving over time.
H03K 5/24 - Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
A device for detecting UV radiation, comprising: a SiC substrate having an N doping; a SiC drift layer having an N doping, which extends over the substrate; a cathode terminal; and an anode terminal. The anode terminal comprises: a doped anode region having a P doping, which extends in the drift layer; and an ohmic-contact region including one or more carbon-rich layers, in particular graphene and/or graphite layers, which extends in the doped anode region. The ohmic-contact region is transparent to the UV radiation to be detected.
H01L 31/103 - Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier being of the PN homojunction type
H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
A control module is used to control a switching buck-boost converter that includes an inductor, a capacitor, a first top switch and a second top switch, a first bottom switch and a second bottom switch and a diode coupled to the second top switch. The control module controls the switching buck-boost converter so as to alternate: first time periods, in which the second top switch is open and cycles of charge and discharge of the inductor are carried out, during which the inductor is traversed by a current that also passes through the diode and charges the capacitor; and second time periods, in which the first and second top switches are open and the first and second bottom switches are closed so that the current in the inductor recirculates, and the capacitor is discharged by a current that flows in the load.
H02M 1/32 - Means for protecting converters other than by automatic disconnection
H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion
H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
13.
PROCESSING SYSTEM, RELATED INTEGRATED CIRCUIT, SYSTEM AND METHOD
A UART communication interface manages transmission/reception at a baud rate using a baud-rate detection circuit. An edge detector detects edges in a reception signal and resets a count value in a digital counter circuit indicating a time between two consecutive edges. In the absence of a detected edge, the digital counter circuit increases the count value. At a newly detected edge, a validation circuit verifies the count value by asserting a second control signal when the count value is smaller than a maximum, and otherwise de-asserting the second control signal. A register provides a threshold signal by storing the count value when the second control signal is asserted. The threshold signal stored by the register is updated when the time is in a permitted range corresponding to the duration of a single bit. The baud rate may be determined as a function of the threshold signal.
The present disclosure is directed to input detection for electronic devices using electrostatic charge sensors. The devices and methods disclosed herein utilize electrostatic charge sensors to detect various touch gestures, such as long and short touches, single/double/triple taps, and swipes; and perform in-ear detection.
A pressure sensor device is provided with: a pressure detection structure made in a first die of semiconductor material; a package, configured to internally accommodate the pressure detection structure in an impermeable manner, the package having a base structure and a body structure, arranged on the base structure, with an access opening in contact with an external environment and internally defining a housing cavity, in which the first die is arranged covered with a coating material. The pressure sensor device is also provided with a heating structure, accommodated in the housing cavity and for allowing heating of the pressure detection structure from the inside of the package.
G01L 19/04 - Means for compensating for effects of changes of temperature
G01L 9/00 - Measuring steady or quasi-steady pressure of a fluid or a fluent solid material by electric or magnetic pressure-sensitive elements; Transmitting or indicating the displacement of mechanical pressure-sensitive elements, used to measure the steady or quasi-steady pressure of a fluid or fluent solid material, by electric or magnetic means
G01L 19/00 - MEASURING FORCE, STRESS, TORQUE, WORK, MECHANICAL POWER, MECHANICAL EFFICIENCY, OR FLUID PRESSURE - Details of, or accessories for, apparatus for measuring steady or quasi-steady pressure of a fluent medium insofar as such details or accessories are not special to particular types of pressure gauges
An HEMT device includes a heterostructure, an insulation layer that extends on the heterostructure and has a thickness along a first direction, and a gate region. The gate region has a first portion that extends through the insulation layer, throughout the thickness of the insulation layer, and has a second portion that extends in the heterostructure. The first portion of the gate region has a first width along a second direction transverse to the first direction. The second portion of the gate region has a second width, along the second direction, that is different from the first width.
A gyroscopic sensor unit detects a phase drift between a demodulated output signal and demodulation signal during output of a quadrature test signal. A delay calculator detects the phase drift based on changes in the demodulated output signal during application of the quadrature test signal. A delay compensation circuit compensates for the phase drift by delaying the demodulation signal by the phase drift value.
G01C 25/00 - Manufacturing, calibrating, cleaning, or repairing instruments or devices referred to in the other groups of this subclass
G01C 19/72 - Gyrometers using the Sagnac effect, i.e. rotation-induced shifts between counter-rotating electromagnetic beams with counter-rotating light beams in a passive ring, e.g. fibre laser gyrometers
18.
POWER SEMICONDUCTOR DEVICE WITH A DOUBLE ISLAND SURFACE MOUNT PACKAGE
A power semiconductor device including a first and second die, each including a plurality of conductive contact regions and a passivation region including a number of projecting dielectric regions and a number of windows. Adjacent windows are separated by a corresponding projecting dielectric region with each conductive contact region arranged within a corresponding window. A package of the surface mount type houses the first and second dice. The package includes a first bottom insulation multilayer and a second bottom insulation multilayer carrying, respectively, the first and second dice. A covering metal layer is arranged on top of the first and second dice and includes projecting metal regions extending into the windows to couple electrically with corresponding conductive contact regions. The covering metal layer moreover forms a number of cavities, which are interposed between the projecting metal regions so as to overlie corresponding projecting dielectric regions.
A pressure sensor device has: a pressure detection structure provided in a first die of semiconductor material; a package, configured to internally accommodate the pressure detection structure in an impermeable manner, the package having a base structure and a body structure, arranged on the base structure, with an access opening in contact with an external environment and internally defining a housing cavity, in which the first die is arranged covered with a coating material. A piezoelectric transduction structure, of a ultrasonic type, is accommodated in the housing cavity, in order to allow detection of foreign material above the coating material and within the package. In particular, the piezoelectric transduction structure is integrated in the first die, which comprises a first portion, wherein the pressure detection structure is integrated, and a second portion, separate and distinct from the first portion, wherein the piezoelectric transduction structure is integrated.
G01L 9/00 - Measuring steady or quasi-steady pressure of a fluid or a fluent solid material by electric or magnetic pressure-sensitive elements; Transmitting or indicating the displacement of mechanical pressure-sensitive elements, used to measure the steady or quasi-steady pressure of a fluid or fluent solid material, by electric or magnetic means
An integrated circuit includes a plurality of power transistor driver channels for driving external loads. The driver channels can be selectively configured as high-side (HS) or low-side (LS) driver channels. The integrated circuit includes, for each driver channel, a respective on-state test circuit and a respective controller. The on-state test circuits can be selectively configured to test for HS overcurrent conditions, LS overcurrent conditions, HS open load conditions, and LS open load conditions.
G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
H03K 5/24 - Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
A device includes a driver circuit and diagnostic circuitry coupled to the driver circuit. The diagnostic circuitry includes an on-state diagnostic circuit and an off-state diagnostic circuit. The diagnostic circuitry, in operation: generates a configuration signal associated with an operative condition of the driver circuit based on a comparator output of the off-state diagnostic circuit; diagnoses conditions associated with the driver circuit; and controls operation of the on-state diagnostic circuit based on the configuration signal.
G01R 31/52 - Testing for short-circuits, leakage current or ground faults
H03K 5/24 - Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
H03K 17/08 - Modifications for protecting switching circuit against overcurrent or overvoltage
22.
METHOD OF OPERATING HARD DISK DRIVES, CORRESPONDING HARD DISK DRIVE AND PROCESSING DEVICE
In accordance with an embodiment, a hard disk drive includes voice coil motors (VCMs) coupled to respective control units configured to drive retract an operation of the VCMs in the hard disk drive. The retract operation of the VCMs includes a sequence of retract steps. The control units are allotted respective time slots for communication over a communication line with the respective time slots synchronized via the common clock line, and are configured to drive sequences of retract steps of the VCMs in the hard disk drive in a timed relationship.
A MOS transistor of vertical-conduction, trench-gate, type, including a first and a second spacer adjacent to portions of a gate oxide of the trench-gate protruding from a semiconductor substrate, the first and second spacers being specular to one another with respect to an axis of symmetry; enriched P+ regions are formed by implanting dopant species within the body regions using the spacers as implant masks. The formation of symmetrical spacers makes it possible to form source, body and body-enriched regions that are auto-aligned with the gate electrode, overcoming the limitations of MOS transistors of the known type in which such regions are formed by means of photolithographic techniques (with a consequent risk of asymmetry).
Micromechanical device comprising: a semiconductor body; a movable structure configured to oscillate relative to the semiconductor body along an oscillation direction; and an elastic assembly with an elastic constant, coupled to the movable structure and to the semiconductor body and configured to deform along the oscillation direction to allow the oscillation of the movable structure as a function of an acceleration applied to the micromechanical device. The movable structure and the semiconductor body comprise a control structure for the capacitive control of the oscillation of the movable structure: when the control structure is electrically controlled in a first state the micromechanical device is in a first operating mode wherein a total elastic constant of the micromechanical device has a first value, and when it is electrically controlled in a second state the micromechanical device is in a second operating mode wherein the total elastic constant has a second value lower than, or equal to, the first value.
G01P 15/125 - Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces with conversion into electric or magnetic values by capacitive pick-up
B81B 3/00 - Devices comprising flexible or deformable elements, e.g. comprising elastic tongues or membranes
An audio electronic system includes a DC switching converter comprising first and second Zeta converters, each comprising an input stage, an output stage, a first switching stage, and a second switching stage. The input stage of each Zeta converter comprises a respective input inductor having a first terminal electrically coupled to the respective first switching stage. The input inductors of the input stages of the first and second Zeta converters are magnetically coupled in such a way that when current enters the terminal of the input inductor of the first Zeta converter that is coupled to the first switch stage of the first Zeta converter, a voltage induced by the coupled current is positive at the terminal of the input inductor of the second Zeta converter that is coupled to the first switching stage of the second Zeta converter.
H02M 3/155 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
H03F 3/217 - Class D power amplifiers; Switching amplifiers
H04R 3/04 - Circuits for transducers for correcting frequency response
The present disclosure is directed to micro-electromechanical system (MEMS) accelerometers that are configured for a user interface mode and a true wireless stereo (TWS) mode of an audio device. The accelerometers are fabricated with specific electromechanical parameters, such as mass, stiffness, active capacitance, and bonding pressure. As a result of the specific electromechanical parameters, the accelerometers have a resonance frequency, quality factor, sensitivity, and Brownian noise density that are suitable for both the user interface mode and the TWS mode.
G01P 15/125 - Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces with conversion into electric or magnetic values by capacitive pick-up
B81B 7/02 - Microstructural systems containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems (MEMS)
G01P 15/18 - Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration in two or more dimensions
27.
INTEGRATED CIRCUIT WITH OFF-STATE DIAGNOSIS FOR DRIVER CHANNELS
An integrated circuit includes a plurality of power transistor driver channels for driving external loads. The driver channels can be selectively configured as high side or low side driver channels. The integrated circuit includes, for each driver channel, a respective analog test circuit and a respective controller. The integrated circuit includes a single counter connected to each of the controllers for simultaneously controlling off-state diagnosis timing windows for the driver channels.
G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
H03K 5/24 - Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
An integrated circuit includes a sub-system and a reference sub-system. The reference sub-system is substantially identical to the sub-system but is non-operating by default. The integrated circuit includes a test circuit that obtains a parameter value of the sub-system and a reference parameter from the reference sub-system. The integrated circuit detects deterioration of the sub-system based on the parameter value and the reference parameter. The integrated circuit deactivates the sub-system and activates the reference sub-system responsive to detecting deterioration of the sub-system.
G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
G01R 31/00 - Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
G01R 31/3185 - Reconfiguring for testing, e.g. LSSD, partitioning
A manufacturing process forms an HEMT device. For the manufacturing process includes forming, from a wafer of silicon carbide having a surface, an epitaxial layer of silicon carbide on the surface of the wafer A semiconductive heterostructure is formed on the epitaxial layer, and the wafer of silicon carbide is removed.
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
A method includes performing, by a terminal with an access card, a first relay attack check for the access card in accordance with a local value associated with the terminal and a local value associated with the access card; determining, by the terminal, that the access card has passed the first relay attack check, and based thereon, performing, by the terminal with the access card, an authentication check of the access card in accordance with the local value associated with the terminal, the local value associated with the access card, and a local challenge value associated with the terminal; and determining, by the terminal, that the access card has passed the first relay attack check and the authentication check, and based thereon, validating, by the terminal, the access card.
In embodiments, a voltage regulator has an input node to receive an input voltage and an output node. The voltage regulator has a charge pump circuit that receives a boosting control signal to boost the input voltage based on the boosting control signal. The voltage regulator further has a feedback regulation circuit configured to receive the output voltage and to provide a first operation control signal and a second operation control signal as a function of the output voltage; a phase control circuit configured to receive the first operation control signal and to provide the boosting control signal as a function of the first operation control signal; and a filter coupled to the output node, configured to receive the second operation control signal and configured to inject to or sink from the output node a charge that is a function of the second operation control signal.
H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H02M 3/07 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion
32.
SYSTEMS AND METHODS TO TEST AN ASYCHRONOUS FINITE MACHINE
A method to test an asynchronous finite state machine for faults, the method including disabling state transitions out of a state of the asynchronous finite state machine and inputting test data to the AFSM to trigger a transition from the state to an expected state. The method further including enabling transitions out of the state of the asynchronous finite state machine, and determining whether the asynchronous finite state machine has performed a successful transition to the expected state.
A processing system includes a communication system and a processing core configured to generate write requests. A circuit has associated a slave interface circuit configured to manage an address sub-range and selectively forward write requests addressed to a given address. Configuration data specifies whether the given address is protected/unprotected and locked/unlocked. In response to a received write request, address and data are extracted and a determination based on the configuration data is made as to whether the extracted address is protected/unprotected, and locked/unlocked. When the extracted address is unprotected or unlocked, the slave interface forwards the write request. When the extracted address is protected and locked, the slave interface generates an unlock signal in response to a comparison of the extracted address with the extracted data, with the unlock signal being asserted when the extracted data satisfy a predetermined rule with respect to the extracted address.
This disclosure pertains to a microelectromechanical systems (MEMS) device with a tiltable structure, a fixed supporting structure, and an actuation structure with driving arms connected to the tiltable structure by elastic decoupling elements. Described herein, particularly, is a planar stop structure between the driving arms and the tiltable structure, which functions to limit movement in the tiltable plane. This stop structure includes a first projection/abutment surface pair formed by a projection extending from a driving arm and an abutment surface formed by a recess in the tiltable structure. The projection and abutment surface are adjacent and spaced apart in the device's rest condition.
B81B 3/00 - Devices comprising flexible or deformable elements, e.g. comprising elastic tongues or membranes
G02B 26/08 - Optical devices or arrangements for the control of light using movable or deformable optical elements for controlling the direction of light
G03B 21/00 - Projectors or projection-type viewers; Accessories therefor
H04N 9/31 - Projection devices for colour picture display
H10N 30/20 - Piezoelectric or electrostrictive devices with electrical input and mechanical output, e.g. functioning as actuators or vibrators
35.
MICROELECTROMECHANICAL DEVICE WITH A STRUCTURE TILTABLE BY PIEZOELECTRIC ACTUATION HAVING IMPROVED MECHANICAL AND ELECTRICAL CHARACTERISTICS
Disclosed herein is a microelectromechanical device that features a fixed structure defining a cavity, a tiltable structure elastically suspended within the cavity, and a piezoelectrically driven actuation structure that rotates the tiltable structure about a first rotation axis. The actuation structure includes driving arms with piezoelectric material, elastically coupled to the tiltable structure by decoupling elastic elements that are stiff to out-of-plane movements but compliant to torsional movements. The tiltable structure is elastically coupled to the fixed structure at the first rotation axis using elastic suspension elements, while the fixed structure forms a frame surrounding the cavity with supporting elements. A lever mechanism is coupled between a supporting element and a driving arm.
G03B 21/00 - Projectors or projection-type viewers; Accessories therefor
B81B 3/00 - Devices comprising flexible or deformable elements, e.g. comprising elastic tongues or membranes
G02B 26/08 - Optical devices or arrangements for the control of light using movable or deformable optical elements for controlling the direction of light
MEMS actuator including: a substrate; a first and a second semiconductive layer; a frame including transverse regions formed by the second semiconductive layer, elongated parallel to a first direction and offset along a second direction, the frame being movable parallel to the second direction. The MEMS actuator includes, for each transverse region: corresponding front rotor regions, which are fixed to the transverse region and are suspended above the substrate; a first and a second stator region, which are formed by the first semiconductive layer in such a way that, when the frame is in rest position, the transverse region is laterally offset with respect to the first and the second stator regions and a first front rotor region partially faces the first stator region, and in such a way that, during a translation of the frame along the second direction, the first and/or a second front rotor region at least partially face the second stator region, when the transverse region begins to superimpose on the first stator region.
A method is provided for controlling an electronic apparatus on the basis of a value of a lid angle between a first hardware element accommodating a first magnetometer and a second hardware element accommodating a second magnetometer. The method includes acquiring, through the magnetometers, first signals representing an orientation of the hardware elements. A calibration parameter indicative of a condition of calibration of the magnetometers is generated on the basis of the first signals. A reliability value indicative of a condition of reliability of the first signals is generated on the basis of the first signals. A first intermediate value of the lid angle is calculated on the basis of the first signals. A current value of the lid angle is calculated on the basis of the calibration parameter, of the reliability value, and of the first intermediate value, and the electronic apparatus is controlled on the basis of the current value.
G01B 7/30 - Measuring arrangements characterised by the use of electric or magnetic techniques for testing the alignment of axes
G01D 5/16 - Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using electric or magnetic means influencing the magnitude of a current or voltage by varying resistance
G01D 18/00 - Testing or calibrating apparatus or arrangements provided for in groups
G05B 17/02 - Systems involving the use of models or simulators of said systems electric
38.
DEVICE, SYSTEM, METHOD, AND COMPUTER PRODUCT FOR DETECTING AND EVALUATING ENVIRONMENTAL QUANTITIES AND EVENTS WITH MODULAR APPROACH AND VARIABLE COMPLEXITY
A system for detecting and evaluating environmental quantities and events is formed by a detection and evaluation device and a mobile phone, connected through a wireless connection. The device is enclosed in a containment casing housing a support carrying a plurality of inertial sensors and environmental sensors. A processing unit is coupled to the inertial sensors and to the environmental sensors. A wireless connection unit, is coupled to the processing unit and a wired connection port, is coupled to the processing unit. A programming connector is coupled to the processing unit and is configured to couple to an external programming unit to receive programming instructions of the processing unit. A storage structure is coupled to the processing unit and a power-supply unit supplied power in the detection and evaluation device. The mobile phone stores an application, which enables a basicuse mode, an expert use mode, and an advanced use mode.
G05B 19/406 - Numerical control (NC), i.e. automatically operating machines, in particular machine tools, e.g. in a manufacturing environment, so as to execute positioning, movement or co-ordinated operations by means of programme data in numerical form characterised by monitoring or safety
A non-volatile memory receives a data read request from a processing core of a plurality of processing cores. The read request is directed to a data partition of a non-volatile memory. The non-volatile memory determines whether to process the read request using read-while-write collision management. When it is determined to process the read request using read-while-write collision management, an address associated with the read request is stored in an address register of a set of registers associated with the processing core. Write operations directed to the data partition are suspended. A read operation associated with the read request is executed while the write operations are suspended and data responsive to the read operation is stored in one or more data registers of the set of registers. The data stored in the one or more data registers of the set of registers is provided to the processing core.
A processing system includes configuration registers and a non-volatile memory with memory slots storing configuration data bits and error detection bits. A hardware configuration circuit sequentially reads the data bits from the non-volatile memory for storage in respective configuration registers by: receiving bits from a current memory slot; selectively asserting an error signal in response to comparison of received error detection bits with calculated error detection bits; storing the received bits to temporary registers where the error signal deasserted and other otherwise asserting a further error signal where the error signal is asserted. Otherwise, predetermined configuration data is stored to the temporary registers. The content of the temporary registers is then sequentially stored to the configuration registers. A reset signal is generated in response to the further error signal to reset the configuration registers.
A semiconductor device semiconductor chip mounted to a leadframe that includes an electrically conductive pad. An electrically conductive clip is arranged in a bridge-like position between the semiconductor chip and the electrically conductive pad. The electrically conductive clip is soldered to the semiconductor chip and to the electrically conductive pad via soldering material applied at coupling surfaces facing towards the semiconductor chip and the electrically conductive pad. The device further includes a pair of complementary positioning formations formed by a cavity in the electrically conductive clip and a protrusion (such as a stud bump or a stack of stud bumps) formed in the electrically conductive pad. The complementary positioning formations are mutually engaged to retain the electrically conductive clip in the bridge-like position to avoid displacement during soldering.
The present disclosure is directed to a sense amplifier architecture for a memory device having a plurality of memory cells. Groups of non-volatile memory cells store respective codewords formed by stored logic states, logic high or logic low, of the memory cells of the group. The sense amplifier architecture has a plurality of sense amplifier reading branches, each sense amplifier reading branch coupled to a respective memory cell and configured to provide an output signal, which is indicative of a cell current flowing through the same memory cell; a comparison stage, to perform a comparison between the cell currents of memory cells of a group; and a logic stage, to determine, based on comparison results provided by the comparison stage, a read codeword corresponding to the group of memory cells. Information may be stored in different subsets of codewords, the sense amplifier architecture in this case having a subset definition circuit, to allow a preliminary determination of the subset to which a codeword to be read belongs to, based on reference signals.
In accordance with an embodiment, a method of operating a buck-boost power supply includes operating the buck-boost power supply in a buck mode by providing a PWM signal to a first half-bridge circuit, and turning on a charge transfer switch coupled between a first boosted supply node of a second driver circuit coupled to the first half-bridge circuit and a second boosted supply node of a second driver circuit coupled to a second half-bridge circuit when a voltage between the second boosted supply node and an output of the second half-bridge circuit is below a first threshold; and operating the buck-boost power supply in a boost mode by providing a PWM signal to the second half-bridge circuit, and turning on the charge transfer switch when the voltage between the first boosted supply node and an output of the first half-bridge circuit is below a second threshold.
H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
H02M 3/157 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
44.
ENHANCEMENT-MODE HEMT AND MANUFACTURING PROCESS OF THE SAME
An enhancement mode high electron-mobility transistor (HEMT) device includes a semiconductor body having a top surface and including a heterostructure configured to generate a two-dimensional electron gas, 2DEG. The HEMT device includes a gate structure which extends on the top surface of the semiconductor body, is biasable to electrically control the 2DEG and includes a functional layer and a gate contact in direct physical and electrical contact with each other. The gate contact is of conductive material and the functional layer is of two-dimensional semiconductor material and includes a first doped portion with P-type electrical conductivity, which extends on the top surface of the semiconductor body and is interposed between the semiconductor body and the gate contact along a first axis.
A control circuit for an electronic converter is described. The control circuit generates a drive signal for an electronic switch of the electronic converter by setting the drive signal to a first logic level in response to a switch-on signal, thereby closing said electronic switch for a switch-on interval, and to a second logic level in response to a switch-off signal, thereby opening the electronic switch for a switch-off interval. The control circuit comprises a valley detection circuit configured to generate a trigger in a trigger signal in response to detecting a valley in the voltage at the electronic switch during the switch-off interval, and a combinational logic circuit configured to generate the switch-on signal by masking the trigger signal in response to a blanking signal. Accordingly, the control circuit comprises also a blanking circuit configured to generate the blanking signal by determining a blanking time as a function the output power provided by the electronic converter, and asserting the blanking signal when the blanking time elapses since the start of the switch-on interval or the switch-off interval. In particular, the control circuit comprises moreover a blanking time adaption circuit configured to generate a blanking time adaption signal as a function of the input voltage, and adapt the blanking time as a function of the blanking time adaption signal, wherein the blanking time adaption circuit is configured to increase the blanking time when the input voltage increases, and decrease the blanking time when the input voltage decreases.
H02M 3/335 - Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
An integrated circuit (IC) includes: a first functional analog pin or pad; a first analog test bus coupled to the first functional analog pin or pad; first and second analog circuits coupled to the first analog test bus; and a test controller configured to: when the IC is in a functional operating mode, connect an input or output of the first analog circuit to the first analog test bus so that the input or output of the first analog circuit is accessible by the first functional analog pin or pad, and keep disconnected an input or output of the second analog circuit from the first analog test bus, and when the IC is in a test mode, selectively connect the input or output of the first and second analog circuits to the first analog test bus to test the first and second analog circuits using the first analog test bus.
The present disclosure is directed to a wide band gap transistor that includes a semiconductor structure, having at least one wide band gap semiconductor layer of gallium nitride or silicon carbide, an insulating gate structure and a gate electrode, separated from the semiconductor structure by the insulating gate structure. The insulating gate structure contains a mixture of aluminum, hafnium and oxygen.
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 29/205 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds in different semiconductor regions
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
A process for manufacturing a HEMT device includes forming a conductive region on a work body having a semiconductive heterostructure. To obtain the conductive region, a first reaction region having carbon is formed on the heterostructure and a metal stack is formed having a second reaction region in contact with the first reaction region. The work body is annealed, so that the first reaction region reacts with the second reaction region, thus forming an interface portion of the conductive region. The interface portion is of a compound having carbon and is in ohmic contact with the semiconductive hetero structure.
A semiconductor device includes an electrically conductive clip arranged in a bridge-like position between a semiconductor integrated circuit chip and an electrically conductive pad of a leadframe. The electrically conductive clip is soldered to the semiconductor integrated circuit chip and to the electrically conductive pad via soldering material applied at coupling surfaces facing towards the semiconductor integrated circuit chip and the electrically conductive pad. Prior to soldering, the clip is immobilized in the desired bridge-like position via one of welding (such as laser welding) or gluing at dedicated immobilization areas.
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
50.
PHASE-CHANGE MEMORY CELL WITH ASYMMETRIC STRUCTURE, A MEMORY DEVICE INCLUDING THE PHASE-CHANGE MEMORY CELL, AND A METHOD FOR MANUFACTURING THE PHASE-CHANGE MEMORY CELL
A phase-change memory cell includes a heater, a memory region made of a phase-change material located above said heater, and an electrically conductive element positioned adjacent to the memory region and the heater at a first side of the heater. The electrically conductive element extends parallel to a first axis and has, parallel to the first axis, a first dimension at the first side that is greater than a second dimension at a second side opposite to the first side.
H10N 70/00 - Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
H10N 70/20 - Multistable switching devices, e.g. memristors
51.
INTEGRATED CIRCUIT INCLUDING A PHYSICALLY UNCLONABLE FUNCTION DEVICE AND CORRESPONDING METHOD FOR IMPLEMENTING A PHYSICALLY UNCLONABLE FUNCTION
Unclonable function circuitry includes a plurality of pairs of phase-change memory cells in a virgin state, and sensing circuitry coupled to the plurality of pairs of phase-change memory cells in the virgin state. The sensing circuitry identifies a subset of the plurality of pairs of phase-change memory cells in the virgin state based on a reliability mask. Signs of differences of effective resistance values of the identified subset of the plurality of pairs of phase-change memory cells in the virgin state are sensed by the sensing circuitry. The sensing circuitry generates a string of bits based on the sensed signs of differences in the effective resistance values of the identified subset of the plurality of pairs of phase-change memory cells in the virgin state. Processing circuitry coupled to the unclonable function circuitry, in operation, executes one or more operations using the generated string of bits.
In an embodiment, an electronic circuit includes: an input differential pair including first and second transistors; a first pair of transistors in emitter-follower configuration including third and fourth transistors, and an output differential pair including fifth and sixth transistors. The third transistor has a control terminal coupled to the first transistor, and a current path coupled to a first output terminal. The fourth transistor has a control terminal coupled to the second transistor, and a current path coupled to a second output terminal. The fifth transistor has a control terminal coupled to the first transistor, and a first current path terminal coupled to the first output terminal. The sixth transistor has a control terminal coupled to the second transistor, and a first current path terminal coupled to the second output terminal. First and second termination resistors are coupled between the first pair of transistors and the output differential pair.
The present disclosure is directed to self-tests for electrostatic charge variation sensors. The self-tests ensure an electrostatic charge variation sensor is functioning properly. The self-tests may be performed while an electrostatic charge variation sensor is active and without interruption to the application employing the electrostatic charge variation sensor.
Alma Mater Studiorum - Universita' Di Bologna (Italy)
Inventor
Pasotti, Marco
Carissimi, Marcella
Gnudi, Antonio
Franchi Scarselli, Eleonora
Antolini, Alessio
Lico, Andrea
Abstract
A circuit includes a memory array with memory cells arranged in a matrix of rows and columns, where each row includes a word line connected to the memory cells of the row, and each column includes a bit line connected to the memory cells of the column. Computational weights for an in-memory compute operation (IMCO) are stored in the memory cells. A word line control circuit simultaneously actuates word lines in response to input signals providing coefficient data for the IMCO by applying word line signal pulses. A column processing circuit connected to the bit lines processes analog signals developed on the bit lines in response to the simultaneous actuation of the word lines to generate multiply and accumulate output signals for the IMCO. Pulse widths of the signal pulses are modulated to compensate for cell drift. The IMCO further handles positive/negative calculation for the coefficient data and computational weights.
G11C 11/4094 - Bit-line management or control circuits
G11C 11/4074 - Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
G06F 7/544 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices for evaluating functions by calculation
55.
VOLTAGE REGULATOR CIRCUIT FOR A SWITCHING CIRCUIT LOAD
A voltage regulator receives a reference voltage and generates a regulated voltage using a MOSFET having a gate terminal configured to receive a control voltage. A charge pump receives the regulated voltage and generates a charge pump voltage in response to an enable signal and a clock signal generated in response to the enable signal. The voltage regulator further includes a first switched capacitor circuit coupled to the gate terminal and configured to selectively charge a first capacitor with a first current and impose a first voltage drop on the control voltage in response to assertion of the enable signal. The voltage regulator also includes a second switched capacitor circuit coupled to the gate terminal and configured to selectively charge a second capacitor with a second current and impose a second voltage drop on the control voltage in response to one logic state of the clock signal.
H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion
H02M 3/07 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
56.
METHOD TO ESTIMATE PHASE AND AMPLITUDE FOR CONTROL OF A RESONANT MEMS MIRROR
Techniques to be described herein are based upon the combination of a digital lock-in amplifier approach with a numerical method to yield accurate estimations of the amplitude and phase of a sense signal obtained from a movement sensor associated with a resonant MEMS device such as a MEMS mirror. The techniques described herein are efficient from a computational point of view, in a manner which is suitable for applications in which the implementing hardware is to follow size and power consumption constraints.
G02B 26/08 - Optical devices or arrangements for the control of light using movable or deformable optical elements for controlling the direction of light
B81B 3/00 - Devices comprising flexible or deformable elements, e.g. comprising elastic tongues or membranes
57.
SEMICONDUCTOR METAL OXIDE BASED GAS SENSOR ACTIVATED AT ZERO HEATER POWER
A gas sensor is formed by a thin-film semiconductor metal-oxide gas sensing layer, with a thermally conductive and electrically-insulating layer in direct physical contact with a back of the gas sensing layer to carry the gas sensing layer. Sensing circuitry applies a voltage to the gas sensing layer and measures a current flowing through the gas sensing layer. The current flowing through the gas sensing layer is indicative of whether a gas under detection has been detected by the gas sensing layer, and serves to self-heat the gas sensing layer. A support structure extends from a substrate to make direct physical contact with and carry the thermally conductive and electrically insulating layer about a perimeter of a back face thereof, with the support structure shaped to form an air gap between the back of the thermally conductive and electrically insulating layer and a front of the substrate.
G01N 33/00 - Investigating or analysing materials by specific methods not covered by groups
G01N 27/04 - Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating impedance by investigating resistance
58.
Method for hybrid pulse amplitude and width modulation in LED drivers for display panels
Driving a LED array includes determining total charge to be transferred to the LEDs during an image frame, and determining a number of drive pulses of equal width and amplitude that would drive the LEDs with nearly the total charge during display of the image frame. One of the drive pulses is modified so the drive pulses drive the LEDs with the total charge during display. If the width is greater than a minimum width and less than a maximum width, the LEDs are driven with the drive pulses. If the width is less than the minimum width and if an amplitude is greater than a minimum amplitude, the amplitude of the drive pulses is decremented. If the width is less than the minimum width and if the amplitude is equal to the minimum amplitude and if the number of drive pulses is greater than one, the number is decremented.
G09G 3/32 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
G09G 3/34 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix by control of light from an independent source
G09G 3/20 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
G09G 3/3225 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
59.
EXCITATION AND SENSING OF A NETWORK OF LC OSCILLATORS
An electronic system includes a first LC oscillator connected to a first general-purpose input/output (GPIO) circuit and a second LC oscillator connected to a second GPIO circuit. A threshold generator is coupled to an input of the comparator. A control circuit is configured to control a measurement phase comprising a first capture phase and a second capture phase. A microcontroller is coupled to the control circuit and a power management circuit is configured to switch-off the microcontroller following activation of the control circuit by the microcontroller. The control circuit is configured to control the application of an excitation signal to the each oscillator via the respective GPIO circuit, control the GPIO circuit so that oscillations of the oscillator are provided to the comparator, and count, based on an output of the comparator, a number of oscillations in the oscillator exceeding a threshold output by the threshold generator.
G01B 7/30 - Measuring arrangements characterised by the use of electric or magnetic techniques for testing the alignment of axes
H03B 5/08 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
60.
MICROELECTROMECHANICAL GYROSCOPE WITH OUT-OF-PLANE DETECTION MOVEMENT
A microelectromechanical gyroscope is provided with a detection structure having: a substrate with a top surface parallel to a horizontal plane (xy); a mobile mass, suspended above the substrate to perform, as a function of a first angular velocity (Ωx) around a first axis (x) of the horizontal plane (xy), at least a first detection movement of rotation around a second axis (y) of the horizontal plane; and a first and a second stator elements integral with the substrate and arranged underneath the mobile mass to define a capacitive coupling, a capacitance value thereof is indicative of the first angular velocity (Ωx). The detection structure has a single mechanical anchorage structure for anchoring both the mobile mass and the stator elements to the substrate, arranged internally with respect to the mobile mass, which is coupled to this single mechanical anchorage structure by coupling elastic elements yielding to torsion around the second axis; the stator elements are integrally coupled to the single mechanical anchorage structure in an arrangement suspended above the top surface of the substrate.
G01C 19/5712 - Turn-sensitive devices using vibrating masses, e.g. vibratory angular rate sensors based on Coriolis forces using masses driven in reciprocating rotary motion about an axis the devices involving a micromechanical structure
61.
READ CIRCUIT FOR CAPACITIVE SENSORS, CORRESPONDING SENSOR DEVICE AND METHOD
A read circuit for capacitive sensors such as a MEMS microphones includes a sensor node configured to be coupled to a capacitive sensor to apply a bias voltage to the sensor and sense the capacitance value of the sensor wherein the voltage at the sensor node is indicative of the capacitance value of the capacitive sensor. A switch is provided between the sensor node and the intermediate node. A shock detector coupled to the sensor node and the switch asserts a shock signal to make the switch conductive in response to a shock applied to the capacitive sensor, and de-asserts the shock signal to make the switch non-conductive with a delay after the end of the shock applied to the capacitive sensor.
A system for testing is provided. The system includes an electronic circuit and an automatic testing equipment (ATE). The electronic circuit includes a voltage monitor including a resistive divider receiving at its voltage input an input voltage and coupled at its output to an input of a comparator. A reference input of the comparator is coupled to a generator supplying a reference voltage setting one or more thresholds of the comparator. The electronic circuit includes a Built In Self Test Module coupled to the ATE and to the inputs and output of the comparator. The BIST module is being configured upon receiving respective commands from the ATE to test a reaction time of the comparator and an offset of the comparator. The ATE performs a respective test of the ratio of the resistor divider by a first voltage measurement and a test of the reference voltage provided by the generator.
The present disclosure is directed to devices and methods for performing screen state detection. The screen state detection may be used in conjunction with any device with a bendable display. The device and method utilizes an electrostatic charge variation sensor to detect whether the display is in an open state or a closed state.
A method comprises molding laser direct structuring material onto at least one semiconductor die, forming resist material on the laser direct structuring material, producing mutually aligned patterns of electrically-conductive formations in the laser direct structuring material and etched-out portions of the resist material having lateral walls sidewise of said electrically-conductive formations via laser beam energy, and forming electrically-conductive material at said etched-out portions of the resist material, the electrically-conductive material having lateral confinement surfaces at said lateral walls of said etched-out portions of the resist material.
A flexible RAM loader including a shift register that includes a first data section coupled with a serial data input, and a second data section selectively coupled with a first parallel data input. The shift register is configured to load data serially from the serial data input to the first data section and the second data section when the second data section is uncoupled from the first parallel data input, and, when the second data section is coupled with the first parallel data input, configured to load data in parallel from the serial data input into the first data section and from the first parallel data input into the second data section. The flexible RAM loader also including a test register comprising a selection bit to couple the second data section with the first parallel data input.
G11C 29/12 - Built-in arrangements for testing, e.g. built-in self testing [BIST]
G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
H03K 19/173 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
66.
HIGH EFFICIENCY GHOST ILLUMINATION CANCELATION IN EMISSIVE AND NON-EMISSIVE DISPLAY PANELS
Display elements, each having anode and cathode terminals, are arranged into rows and columns. Each row has an anode-line coupled to the anode terminals for its display elements. Each column has a cathode-line coupled to the cathode terminals for its display elements. A switch for each anode-line selectively couples that anode-line to a storage capacitor, and a switch for each cathode-line selectively couples that cathode-line to the storage capacitor. A display driver activates the row driver for a given row and the column driver for a given column. A switch driver closes the switch for the cathode-line for the given column, then opens the switch for that cathode-line. The display driver deactivates the row driver for the given row, after closing the switch for the cathode-line for the given column. The switch driver closes the switch for the anode-line for the given row.
G09G 3/36 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix by control of light from an independent source using liquid crystals
G09G 3/32 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
67.
DIODE WITH CONTACT STRUCTURE INCLUDING AN IMPROVED BARRIER REGION AND RELATED MANUFACTURING PROCESS
The present disclosure is directed to a diode with a semiconductor body of silicon including a cathode region, which has a first conductivity type and is delimited by a front surface; and an anode region, which has a second conductivity type and extends into the cathode region from the front surface. The diode further includes a barrier region of cobalt disilicide, arranged on the anode region; and a metallization region of aluminum or of an aluminum alloy, arranged on the barrier region. The barrier region contacts the anode region.
A method of operating a PMUT electro-acoustical transducer, the method comprising: applying over an excitation interval to the transducer an excitation signal which is configured to emit corresponding ultrasound pulses towards a surrounding space, acquiring at a receiver reflected ultrasound pulses as reflected in said surrounding space, generating a reference echo signal, performing a cross-correlation of said acquired received ultrasound pulses with said reference echo signal, performing a measurement based on the cross-correlation results, in particular a measurement of the time of flight of the ultrasound pulses, wherein said reference echo is obtained by finding an oscillation frequency of the transmitter on the basis of a transmitter ringdown signal, finding an oscillation frequency of the receiver on the basis of a receiver ringdown signal, performing a frequency tuning respectively on the transmitter and the receiver on the basis of said respective oscillation frequencies, then sweeping an input frequency of the transmitter to find a frequency of the maximum displacement in the ringdown signal, performing a frequency tuning of the receiver at said frequency of the maximum displacement in the ringdown signal of the transmitter.
The present disclosure is directed to a method for storing information in a coded manner in non-volatile memory cells. The method includes providing a group of non-volatile memory cells of non volatile memory. The memory cell is of the type in which a stored logic state, which can be logic high or logic low, can be changed through application of a current to the cell and the state in the memory cell is read by reading a current provided by the cell. The group of non-volatile memory cells include a determined number of non-volatile memory cells which is greater than two. The group of non-volatile memory cells store a codeword formed by the values of said stored states of the cells of the group taken according to a given order. Given a set of codewords obtainable by the stored values in the determined number of non-volatile memory cells in a group, the method includes storing the information in at least two subsets of said set of codewords comprising each at least a codeword. Each codeword in a same subset has a same Hamming weight. Each codeword belonging to one subset has a Hamming distance equal or greater than two with respect to each codeword belonging to another subset.
G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
70.
SYSTEM ARCHITECTURE FOR HIGH DENSITY MINI/MICRO LED BACKLIGHT APPLICATION
A non-emissive display includes a backlight controller sending a pulse during each sub-frame of a plurality of frames to row and column drivers that drive backlight zones. The row drivers count each pulse to keep a pulse count total, and reset the pulse count total when it is equal to a first number indicating how many row drivers are present. Each row driver activates its channels and waits for a next pulse if the pulse count total is not equal to the first number and if the pulse count total is equal to a second number indicating in which sub-frame that first driver is to be activated. Each row driver waits for a next pulse if the pulse count total is not equal to the first number and the second number. Each column driver activates its channel in response to receipt of each pulse.
G09G 3/34 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix by control of light from an independent source
G09G 3/36 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix by control of light from an independent source using liquid crystals
71.
ANALOG TO DIGITAL CONVERTER APPARATUS WITH TIME CONTINUOUS INPUT AND CORRESPONDING METHOD
Provided is an analog to digital converter configured to receive a continuous input signal. The analog to digital converter includes an integrating block, comprising at least an integrating stage, which output is coupled to a flash analog to digital converter. The analog to digital converter apparatus includes a feedback path coupled to the output of said flash analog to digital converter. The feedback path includes at least a digital to analog conversion block which output is compared at least to the input signal to obtain an error signal which is brought as input to said integrating block. A control block is configured to perform control comprising at least a digital integration, is coupled between the output of said flash analog to digital converter and said feedback path.
A system-on-chip includes a process-voltage-temperature (PVT) sensor with a filter circuit that initiates a patterned digital signal and propagates the patterned digital signal in a manner responsive to variations in semiconductor material, operating supply voltage and operating temperature of the system-on-chip. A digital comparison circuit compares the initiated patterned digital signal and the propagated patterned digital signal. A warning signal is generated in response to the comparison where there is a detection of discrepancy between the initiated patterned digital signal and the propagated patterned digital signal.
A system to monitor a MOSFET, the system including a switching arrangement configured to switchably isolate a gate terminal of the MOSFET and a source terminal of the MOSFET from a gate-control voltage source and a test circuit configured to detect a change in a gate-to-source voltage of the MOSFET over a test period, the test period occurring while the gate terminal and the source terminal are isolated
The present disclosure is directed to a solid body for a biomedical device, wearable by a patient and configured to acquire one or more physiological parameters of the patient. The solid body includes a first rigid portion, a second rigid portion and a connection portion of flexible type which couples the first and the second rigid portions to each other; and a control circuitry accommodated inside the first and/or the second rigid portions. The connection portion is interposed between the first and the second rigid portions, is integral therewith and is deformable so as to allow a relative movement of the first and the second rigid portions. The first and the second rigid portions are physically couplable to a first and to a second ECG electrode to couple the solid body to the torso of the patient. When the rigid portions are coupled to the ECG electrodes, the control circuitry is electrically coupled to the ECG electrodes and is configured to acquire, through the ECG electrodes, respective electrical signals indicative of said one or more physiological parameters.
An isolated driver device comprises a first semiconductor die and a second semiconductor die galvanically isolated from each other. The second semiconductor die includes a signal modulator circuit configured to modulate a carrier signal to produce a modulated signal encoding information. A galvanically isolated communication channel implemented in the first semiconductor die and the second semiconductor die is configured to transmit the modulated signal from the second semiconductor die to the first semiconductor die. The second semiconductor die includes: a fault detection circuit configured to detect electrical faults in the second semiconductor die; a logic circuit coupled to the fault detection circuit and configured to assert a modulation bypass signal in response to a fault being detected by the fault detection circuit; and modulation masking circuitry configured to force the modulated signal to a steady value over a plurality of periods of the carrier signal in response to the modulation bypass signal being asserted. The first semiconductor die includes a respective logic circuit sensitive to the modulated signal and configured to detect a condition where the modulated signal has a steady value over a plurality of periods of the carrier signal, and to assert a fault detection signal in response to the condition being detected.
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
A DC-DC boost converter includes an inductor coupled between an input voltage and an input node, a diode coupled between the input node and an output node, and an output capacitor coupled between the output node and ground such that an output voltage is formed across the output capacitor. A switch selectively couples the input node to ground in response to a drive signal. Control loop circuitry includes an error amplifier to generate an analog error voltage based upon a comparison of a feedback voltage to a reference voltage, the feedback voltage being indicative of the output voltage, a quantizer to quantize the analog error voltage to produce a digital error signal, and a drive voltage generation circuit to generate the drive signal as having a duty cycle based upon the digital error signal.
H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
A supply node receives supply voltage and an output node provides a regulated output voltage to a load. A switching transistor is coupled between the supply and output nodes. The switching transistor is controlled by a drive signal generated by a control circuit to control switching activity. The control circuit includes circuitry to sense a feedback voltage indicative of the regulated output voltage and a comparator generating a comparison logic signal dependent on a comparison of the feedback voltage to a reference. A logic circuit generates a skip signal in response to the comparison logic signal. A counter generates a termination signal. Signal processing circuitry controls the switching activity by asserting the drive signal as a function of the skip signal and the termination signal.
H02M 3/157 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
78.
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES, CORRESPONDING APPARATUS AND SEMICONDUCTOR DEVICE
A leadframe has a die pad area and an outer layer of a first metal having a first oxidation potential. The leadframe is placed in contact with a solution containing a second metal having a second oxidation potential, the second oxidation potential being more negative than the first oxidation potential. Radiation energy is then applied to the die pad area of the leadframe contacted with the solution to cause a local increase in temperature of the leadframe. As a result of the temperature increase, a layer of said second metal is selectively provided at the die pad area of the leadframe by a galvanic displacement reaction. An oxidation of the outer layer of the leadframe is then performed to provide an enhancing layer which counters device package delamination.
A method of making a MEMS actuator with a monolithic body of semiconductor material includes forming a supporting portion of semiconductor material, orientable with respect to first and second rotation axes, the first rotation axis being transverse with respect to the second rotation axis, and forming a first frame of semiconductor material. The method further includes forming first deformable elements, of semiconductor material, coupled to the first frame, and configured to control a rotation of the supporting portion about the first rotation axis. The method also includes forming a second frame of semiconductor material, and forming second deformable elements, of semiconductor material, coupled to the first frame and to the second frame, and configured to control a rotation of the supporting portion about the second rotation axis. The first and second deformable elements are formed to carry respective first and second piezoelectric actuation elements.
G02B 27/64 - Imaging systems using optical elements for stabilisation of the lateral and angular position of the image
G03B 5/06 - Swinging lens about normal to the optical axis
H02N 2/02 - Electric machines in general using piezoelectric effect, electrostriction or magnetostriction producing linear motion, e.g. actuators; Linear positioners
H02N 2/00 - Electric machines in general using piezoelectric effect, electrostriction or magnetostriction
B81B 3/00 - Devices comprising flexible or deformable elements, e.g. comprising elastic tongues or membranes
STMicroelectronics International N.V. (Switzerland)
Inventor
Desoli, Giuseppe
Cappetta, Carmine
Boesch, Thomas
Singh, Surinder Pal
Suneja, Saumya
Abstract
Embodiments of an electronic device include an integrated circuit, a reconfigurable stream switch formed in the integrated circuit along with a plurality of convolution accelerators and a decompression unit coupled to the reconfigurable stream switch. The decompression unit decompresses encoded kernel data in real time during operation of convolutional neural network.
A DC-DC boost converter includes an inductor coupled between an input voltage and an input node, a first path coupled between the input node and a first output node at which a first output voltage is generated, and a second path coupled between the input node and a second output node at which a second output voltage is generated. The DC-DC boost converter operates in a first operating phase where the first path boosts the first output voltage and where the second path is kept from boosting the second output voltage by the second path being coupled to the first path, and operates in a second operating phase where the second path boosts the second output voltage and where the first path is kept from boosting the first output voltage by the second path not being coupled to the first path.
H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
G02B 26/08 - Optical devices or arrangements for the control of light using movable or deformable optical elements for controlling the direction of light
82.
PWM SIGNAL GENERATOR CIRCUIT AND RELATED INTEGRATED CIRCUIT
A PWM signal generator circuit includes a multiphase clock generator that generates a number n of phase-shifted clock phases having the same clock period and being phase shifted by a time corresponding to a fraction 1/n of the clock period. The PWM signal generator circuit determines for each switch-on duration first and second integer numbers, and for each switch-off duration third and fourth integer numbers. The first integer number is indicative of the integer number of clock periods of the switch-on duration and the second integer number is indicative of the integer number of the additional fractions 1/n of the clock period of the switch-on duration. The third integer number is indicative of the integer number of clock periods of the switch-off duration, and the fourth integer number is indicative of the integer number of the additional fractions 1/n of the clock period of the switch-off duration.
STMicroelectronics International N.V. (Switzerland)
Inventor
Tyagi, Vivek
Rana, Vikas
Auricchio, Chantal
Capecchi, Laura
Abstract
A read signal generator generates read signals to control read operations of a memory array. The read signal generator can be selectively controlled to generate an oscillating signal having a period that corresponds to a feature one of the read signals. The oscillating signal is passed to a frequency divider that divides the oscillating signal and provides the divided oscillating signal to an output pad. The frequency of the oscillating signal can be measured at the output pad. The frequency of the oscillating signal, and the duration of the read signal feature can be calculated from the frequency of the oscillating signal. The read signal feature can then be adjusted if needed.
G11C 7/12 - Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
A method and device for unlatching a door from a frame, using a keyless door latch system, is provided. In one embodiment, a secondary unlocking component receives a signal and derives power from the signal to provide a power source for the keyless door latch system. A microcontroller generates a control signal and an actuator, in response to receiving the control signal, actuates the secondary unlocking component, which allows an energy source, from an exterior of the door, to be transferred to the keyless door latch system for the unlatching of the door.
A photonic integrated circuit chip includes vertical grating couplers defined in a first layer. Second insulating layers overlie the vertical grating coupler and an interconnection structure with metal levels is embedded in the second insulating layers. A cavity extends in depth through the second insulating layers all the way to an intermediate level between the couplers and the metal level closest to the couplers. The cavity has lateral dimensions such that the cavity is capable of receiving a block for holding an array of optical fibers intended to be optically coupled to the couplers.
G02B 6/124 - Geodesic lenses or integrated gratings
G02B 6/34 - Optical coupling means utilising prism or grating
G02B 6/43 - Arrangements comprising a plurality of opto-electronic elements and associated optical interconnections
G02B 6/30 - Optical coupling means for use between fibre and thin-film device
G02B 6/12 - Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
G02B 6/136 - Integrated optical circuits characterised by the manufacturing method by etching
STMicroelectronics International N.V. (Switzerland)
STMicroelectronics S.r.l. (Italy)
Inventor
Rana, Vikas
Pasotti, Marco
De Santis, Fabio
Abstract
A voltage supply circuit and a method for controlling a voltage supply circuit are provided. The voltage supply circuit includes a positive charge pump stage that generates a positive voltage and a negative charge pump stage that generates a negative voltage. The voltage supply circuit also includes a control stage that compares a voltage representative of the negative voltage with a reference voltage and causes a slope of the positive voltage to decrease when the voltage representative of the negative voltage exceeds the reference voltage.
H02M 3/07 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
The present disclosure relates to a device comprising a first transistor and a first circuit comprising first and second terminals, the first circuit being configured to generate a first voltage representing the temperature of the first transistor, a first terminal of the first circuit being coupled to the drain of the first transistor.
H03K 17/0812 - Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the control circuit
A MEMS based device includes a phononic crystal body formed from unit cells and having a defect line extending through the phononic crystal body. Unit cells inside of the defect line lack a same phononic bandgap as the unit cells outside of the defect line. An input MEMS resonator is mechanically coupled to a first end of the defect line, and an output MEMS resonator is mechanically coupled to a second end of the defect line. Each of the unit cells outside of the defect line has an identical geometry. The input MEMS resonator and output MEMS resonator each have a natural frequency within the same phononic bandgap possessed by the unit cells outside of the defect line. There may be more than one defect line, and in such cases, the MEMS device may include more than one input MEMS resonator and/or more than one output MEMS resonator.
G02F 1/035 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on ceramics or electro-optical crystals, e.g. exhibiting Pockels or Kerr effect in an optical waveguide structure
89.
OSCILLATOR CIRCUIT, CORRESPONDING RADAR SENSOR, VEHICLE AND METHOD OF OPERATION
Disclosed herein is a tunable resonant circuit including an inductance directly electrically connected in series between first and second nodes, a variable capacitance directly electrically connected between the first and second nodes, and a set of switched capacitances coupled between the first and second nodes. The set of switched capacitances includes a plurality of capacitance units, each capacitance unit comprising a first capacitance for that capacitance unit directly electrically connected between the first node and a switch and a second capacitance for the capacitance unit directly electrically connected between the switch and the second node. Control circuitry is configured to receive an input control signal and connected to control the switches of the set of switched capacitances. A biasing circuit is directly electrically connected to the tunable resonance circuit at the first and second nodes.
G01S 13/931 - Radar or analogous systems, specially adapted for specific applications for anti-collision purposes of land vehicles
H03B 5/12 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
H03L 7/193 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number the frequency divider/counter comprising a commutable pre-divider, e.g. a two modulus divider
H03L 7/099 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
H03L 7/10 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
90.
DIE ATTACHMENT METHOD FOR SEMICONDUCTOR DEVICES AND CORRESPONDING SEMICONDUCTOR DEVICE
The present disclosure is directed to a method of manufacturing semiconductor devices that includes providing a substrate such as a leadframe having a non-etched adhesion promoter, NEAP layer over the die mounting surface and attaching thereon a semiconductor die having an attachment surface including a first and a second die areas that are wettable by electrically conductive solder material. The NEAP layer is selectively removed, e.g., via laser ablation, from the first substrate area and the second substrate area of the die mounting surface of the substrate. The first substrate area and the second substrate area of the substrate having complementary shapes with respect to the first and second die areas of the semiconductor die. Electrically conductive solder material is dispensed on the first and second substrate areas of the substrate. A semiconductor die is flipped onto the substrate with the first die area and the second die area aligned with the first substrate area and the second substrate area of the substrate having the solder material dispensed thereon. The electrically conductive solder material thus provides electrical coupling of: the first die area and the first substrate area, and the second die area and the second substrate area.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
91.
METHOD OF MANUFACTURING A REDISTRIBUTION LAYER, REDISTRIBUTION LAYER, INTEGRATED CIRCUIT AND METHODS FOR ELECTRICALLY TESTING AND PROTECTING THE INTEGRATED CIRCUIT
To manufacture a redistribution layer for an integrated circuit, a first insulating layer is formed on a conductive interconnection layer of a wafer. A conductive body is then formed in electrical contact with the interconnection layer. The conductive body is then covered with an insulating region having an aperture that exposes a surface of the conductive body. The surface of the conductive body and the insulating region are then covered with an insulating protection layer having a thickness less than 100 nm. This insulating protection layer is configured to provide a protection against oxidation and/or corrosion of the conductive body.
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
C23C 16/50 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating using electric discharges
G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/29 - Encapsulation, e.g. encapsulating layers, coatings characterised by the material
H01L 21/66 - Testing or measuring during manufacture or treatment
92.
SEMICONDUCTOR DIE WITH IMPROVED THERMAL INSULATION BETWEEN A POWER PORTION AND A PERIPHERAL PORTION, METHOD OF MANUFACTURING, AND PACKAGE HOUSING THE DIE
A semiconductor die includes a structural body that has a power region and a peripheral region surrounding the power region. At least one power device is positioned in the power region. Trench-insulation means extend in the structural body starting from the front side towards the back side along a first direction, adapted to hinder conduction of heat from the power region towards the peripheral region along a second direction orthogonal to the first direction. The trench-insulation means have an extension, in the second direction, greater than the thickness of the structural body along the first direction.
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different main groups of groups , or in a single subclass of , , e.g. forming hybrid circuits
An inertial structure is elastically coupled through a first elastic structure to a supporting structure so as to move along a sensing axis as a function of a quantity to be detected. The inertial structure includes first and second inertial masses which are elastically coupled together by a second elastic structure to enable movement of the second inertial mass along the sensing axis. The first elastic structure has a lower elastic constant than the second elastic structure so that, in presence of the quantity to be detected, the inertial structure moves in a sensing direction until the first inertial mass stops against a stop structure and the second elastic mass can move further in the sensing direction. Once the quantity to be detected ends, the second inertial mass moves in a direction opposite to the sensing direction and detaches the first inertial mass from the stop structure.
G01P 15/125 - Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces with conversion into electric or magnetic values by capacitive pick-up
94.
DATA VOLUME SCULPTOR FOR DEEP LEARNING ACCELERATION
STMICROELECTRONICS INTERNATIONAL N.V. (Netherlands)
Inventor
Singh, Surinder Pal
Boesch, Thomas
Desoli, Giuseppe
Abstract
A device include on-board memory, an applications processor, a digital signal processor (DSP) cluster, a configurable accelerator framework (CAF), and a communication bus architecture. The communication bus communicatively couples the applications processor, the DSP cluster, and the CAF to the on-board memory. The CAF includes a reconfigurable stream switch and data volume sculpting circuitry, which has an input and an output coupled to the reconfigurable stream switch. The data volume sculpting circuitry receives a series of frames, each frame formed as a two dimensional (2D) data structure, and determines a first dimension and a second dimension of each frame of the series of frames. Based on the first and second dimensions, the data volume sculpting circuitry determines for each frame a position and a size of a region-of-interest to be extracted from the respective frame, and extracts from each frame, data in the frame that is within the region-of-interest.
Embodiments are directed to electronic fuse devices and systems. One such electronic fuse includes current sensing circuitry that senses a current in a conductor coupled between a power supply and a load, and generates a current sensing signal indicative of the sensed current. I2t circuitry receives the current sensing signal and determines whether the sensed current exceeds an I2t curve of the conductor. The electronic fuse further includes at least one of external MOSFET temperature sensing circuitry that senses a temperature of an external MOSFET coupled to the conductor, low current bypass circuitry that supplies a reduced current to the load in a low power consumption mode during which the external MOSFET is in a non-conductive state, or desaturation sensing circuitry that senses a drain-source voltage of the external MOSFET.
H02H 3/08 - Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition, with or without subsequent reconnection responsive to excess current
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
96.
Digital self-calibration for automatic offset cancellation
A method for calibrating the DC operating point of a PWM receiver circuit is disclosed. The PWM receiving circuit includes an envelop detector having a first resistor string, and includes a bias circuit having a second resistor string and a plurality of switches. The second resistor string is coupled between a supply voltage and a reference voltage and functions as a voltage divider. Each switch, when closed, accesses a second voltage at a node of the second resistor string connected to the closed switch. To perform the calibration process, the plurality of switches is closed one at a time, and the second voltage is compared with a first voltage at a first node of the first resistor string. The switch that, when closed, produces the smallest difference between the first voltage and the second voltage remains closed after the calibration process, and is used for demodulating the PWM signal.
H03B 5/12 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
98.
SIC-BASED ELECTRONIC DEVICE WITH ENHANCED ROBUSTNESS, AND METHOD FOR MANUFACTURING THE ELECTRONIC DEVICE
An electronic device comprising: a semiconductor body of silicon carbide; a first insulating layer on a first surface of the semiconductor body, of a first material with electrical-insulator or dielectric characteristics; a first layer of metal material extending in part on the first surface of the semiconductor body and in part on the first insulating layer; an interface layer on the first layer of metal material and on the first insulating layer, of a second material different from the first material; and a passivation layer of the first material on the interface layer. The first material is silicon oxide, and the second material is silicon nitride.
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
99.
PHASE CHANGE MEMORY DEVICE WITH IMPROVED RETENTION CHARACTERISTICS AND RELATED METHOD
A phase change memory element has a memory region, a first electrode and a second electrode. The memory region is arranged between the first and the second electrodes and has a bulk zone and an active zone. The memory region is made of a germanium, antimony and tellurium based alloy, wherein germanium is in a higher percentage than antimony and tellurium in the bulk zone of the memory region. The active zone is configured to switch between a first stable state associated with a first memory logic level and a second stable state associated with a second memory logic level. The active zone has, in the first stable state, a uniform, amorphous structure and, in the second stable state, a differential polycrystalline structure including a first portion, having a first stoichiometry, and a second portion, having a second stoichiometry different from the first stoichiometry.
G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
H10N 70/00 - Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
H10N 70/20 - Multistable switching devices, e.g. memristors
STMicroelectronics International N.V. (Switzerland)
Inventor
Giacomini, Mauro
Disegni, Fabio Enrico Carlo
Narwal, Rajesh
Saini, Pravesh Kumar
Hareshbhai Niranjani, Mayankkumar
Abstract
An assembly for detecting a structural defect in a semiconductor die is provided. The assembly includes a defect-detection sensor and a microcontroller. The defect-detection sensor includes a plurality of resistive paths of electrical-conductive material in the semiconductor die, each of which has a first end and a second end and extends proximate a perimeter of the semiconductor die. The defect-detection sensor includes a plurality of signal-generation structures, each coupled to a respective resistive path and configured to supply a test signal to the resistive path. The microcontroller is configured to control the signal-generation structures to generate the test signals, acquire the test signals in each resistive paths, test an electrical feature of the resistive paths by performing an analysis of the test signals acquired and detect the presence of the structural defect in the semiconductor die based on a result of the analysis of the test signals acquired.
patents
