STMicroelectronics S.r.l.

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New (last 4 weeks) 31
2024 May (MTD) 22
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IPC Class
H01L 29/66 - Types of semiconductor device 167
H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion 164
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices 159
H01L 23/495 - Lead-frames 134
B81B 3/00 - Devices comprising flexible or deformable elements, e.g. comprising elastic tongues or membranes 129
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Pending 579
Registered / In Force 2,956
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1.

Asynchronous Controller for Processing Unit

      
Application Number 18056012
Status Pending
Filing Date 2022-11-16
First Publication Date 2024-05-16
Owner STMicroelectronics S.r..l. (Italy)
Inventor
  • Castellano, Marco
  • Bruni, Francesco
  • Gandolfi, Luca
  • Leo, Marco

Abstract

A processor includes a synchronous circuit including a plurality of processing stages, wherein each processing stage includes a selection data bus; and an asynchronous circuit coupled to each selection data bus, wherein the asynchronous circuit includes an asynchronous state machine whose states correspond to a process phase or a plurality of circuits, wherein the asynchronous circuit further includes a selectable delay circuit whose delay is determined by a present state of the asynchronous state machine, and wherein the asynchronous circuit is configured for generating a plurality of processing stage clock signals each having a selectable delay provided by the selectable delay circuit.

IPC Classes  ?

2.

SELF-TESTING CIRCUITS FOR DEVICES HAVING MULTIPLE INPUT CHANNELS WITH REDUNDANCY

      
Application Number 17987379
Status Pending
Filing Date 2022-11-15
First Publication Date 2024-05-16
Owner STMicroelectronics S.r.l. (Italy)
Inventor
  • Errico, Nicola
  • Cannone, Alessandro
  • Ferrara, Enrico
  • Piscitelli, Luigi

Abstract

A circuit includes: first analog-to-digital converters (ADCs) configured to be coupled to respective ones of first sensors; a first multiplexer (MUX) coupled to output terminals of the first ADCs; a second MUX configured to be coupled to second sensors which are redundant sensors for the first sensors; a second ADC coupled to an output terminal of the second MUX, the first MUX and the second MUX being controlled by a selection signal; a first checker circuit configured to compare a first data at an output terminal of the first MUX with a second data at an output terminal of the second ADC; and a plurality of switches coupled between respective ones of the input terminals of the second MUX and a reference voltage node.

IPC Classes  ?

  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
  • G01R 31/3167 - Testing of combined analog and digital circuits
  • G01R 31/319 - Tester hardware, i.e. output processing circuits

3.

LIGHT-EMITTER DEVICE WITH INDUCED DEFECTS AND METHOD OF MANUFACTURING THE LIGHT EMITTER DEVICE

      
Application Number 18504034
Status Pending
Filing Date 2023-11-07
First Publication Date 2024-05-16
Owner STMICROELECTRONICS S.r.l. (Italy)
Inventor
  • D'Arrigo, Giuseppe
  • Sciuto, Antonella
  • Mello, Domenico Pierpaolo
  • Barbarino, Pietro Paolo
  • Coffa, Salvatore

Abstract

A light-emitter device comprising: a body of solid-state material; and a P-N junction in the body, including: a cathode region, having N-type conductivity; an anode region, having P-type conductivity, extending in direct contact with the cathode region and defining a light-emitting surface; and a depletion region around an interface between the anode and the cathode regions. The light-emitting surface has at least one indentation that extends towards the depletion region. The depletion region has a peak defectiveness area, housing irregularities in crystal lattice, in correspondence of said at least one indentation. The defectiveness area, which includes point defects, line defects, bulk defects, etc., is generated as a direct consequence of the formation of the indentation by an indenter or nanoindenter system. In the defectiveness area color centers are generated.

IPC Classes  ?

  • H01L 33/02 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the semiconductor bodies
  • H01L 33/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof
  • H01L 33/20 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
  • H01L 33/34 - Materials of the light emitting region containing only elements of group IV of the periodic system

4.

SEMICONDUCTOR PACKAGE OR DEVICE WITH BARRIER LAYER

      
Application Number 18054806
Status Pending
Filing Date 2022-11-11
First Publication Date 2024-05-16
Owner STMICROELECTRONICS S.r.l. (Italy)
Inventor
  • Guarino, Lucrezia
  • Milanesi, Francesca
  • Zafferoni, Claudio

Abstract

The present disclosure is directed to embodiments of a conductive structure on a conductive barrier layer that separates the conductive structure from a conductive layer on which the conductive barrier layer is present. A gap or crevice extends along respective surfaces of the conductive structure and along respective surfaces of one or more insulating layers. The gap or crevice separates the respective surfaces of the one or more insulating layers from the respective surfaces of the conductive structure. The gap or crevice provides clearance in which the conductive structure may expand into when exposed to changes in temperature. For example, when coupling a wire bond to the conductive structure, the conductive structure may increase in temperature and expand into the gap or crevice. However, even in the expanded state, respective surfaces of the conductive structure do not physically contact the respective surfaces of the one or more insulating layers.

IPC Classes  ?

  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices

5.

MANUFACTURING METHOD OF A SEMICONDUCTOR DEVICE WITH EFFICIENT EDGE STRUCTURE

      
Application Number 18509043
Status Pending
Filing Date 2023-11-14
First Publication Date 2024-05-16
Owner STMICROELECTRONICS S.r.l. (Italy)
Inventor
  • Zanetti, Edoardo
  • Rascuna', Simone
  • Saggio, Mario Giuseppe
  • Guarnera, Alfio
  • Fragapane, Leonardo
  • Tringali, Cristina

Abstract

A manufacturing method of an electronic device includes: forming a drift layer of an N type; forming a trench in the drift layer; forming an edge-termination structure alongside the trench by implanting dopant species of a P type; and forming a depression region between the trench and the edge-termination structure by digging the drift layer. The steps of forming the depression region and the trench are carried out at the same time. The step of forming the depression region comprises patterning the drift layer to form a structural connection with the edge-termination structure having a first slope, and the step of forming the trench comprises etching the drift layer to define side walls of the trench, which have a second slope steeper than the first slope.

IPC Classes  ?

  • H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
  • H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 29/872 - Schottky diodes

6.

PROCESSING SYSTEM, RELATED INTEGRATED CIRCUIT, DEVICE AND METHOD

      
Application Number 18503744
Status Pending
Filing Date 2023-11-07
First Publication Date 2024-05-16
Owner
  • STMicroelectronics S.r.l. (Italy)
  • STMicroelectronics Application GMBH (Germany)
Inventor
  • Dondini, Mirko
  • Trecarichi, Calogero Andrea
  • Rennig, Fred

Abstract

An example processing system includes a processing circuit, a volatile memory and a CAN communication controller circuit. The CAN communication controller circuit includes configuration and status registers. A transmission handler circuit and a reception handler circuit transmits and receives data via the CAN core circuit by exchanging data with the volatile memory based on the configuration data stored to the configuration and status registers, and filter elements stored to the volatile memory. Specifically, the processing system further includes a hardware host circuit comprising a non-volatile memory configured to store first configuration data (CD1) and second configuration data (CD2). The CD1 includes configuration data to be transferred to the configuration and status registers of the CAN communication controller circuit and the CD2 includes at least one filter element to be transferred to the volatile memory. A control circuit manages an initialization mode, a reception mode and a transmission mode. During the initialization mode, the hardware host circuit stores the CD1 to the configuration and status registers and the CD2 to the volatile memory.

IPC Classes  ?

  • G06F 13/42 - Bus transfer protocol, e.g. handshake; Synchronisation

7.

METHOD OF COMMUNICATING INFORMATION AND CORRESPONDING DEVICE AND SYSTEM

      
Application Number 18408677
Status Pending
Filing Date 2024-01-10
First Publication Date 2024-05-16
Owner STMicroelectronics S.r.l. (Italy)
Inventor
  • Guerrieri, Lorenzo
  • Poloni, Angelo
  • Lauri, Edoardo

Abstract

A communication circuit supports a first communication protocol and a second communication protocol that is different from the first communication protocol. A number of signals include first signals conveying first information messages and second signals conveying second information messages. The first information messages include a repetitive message having fixed repeated content and the second information messages include a non-repetitive message having variable content. The first signals and the second signals are transmitted via the communication circuit using the first communication protocol for the first signals and the second communication protocol for the second signals.

IPC Classes  ?

  • H04L 69/18 - Multiprotocol handlers, e.g. single devices capable of handling multiple protocols
  • H04L 27/00 - Modulated-carrier systems
  • H04L 27/12 - Modulator circuits; Transmitter circuits
  • H04L 27/26 - Systems using multi-frequency codes

8.

GAN-BASED, LATERAL-CONDUCTION, ELECTRONIC DEVICE WITH IMPROVED METALLIC LAYERS LAYOUT

      
Application Number 18509052
Status Pending
Filing Date 2023-11-14
First Publication Date 2024-05-16
Owner STMICROELECTRONICS S.R.L. (Italy)
Inventor
  • Smerzi, Santo Alessandro
  • Nicotra, Maria Concetta
  • Iucolano, Ferdinando

Abstract

An electronic device, comprising plurality of source metal strips in a first metal level; a plurality of drain metal strips in the first metal level; a source metal bus in a second metal level above the first metal level; a drain metal bus, in the second metal level; a source pad, coupled to the source metal bus; and a drain pad, coupled to the drain metal bus. The source metal bus includes subregions shaped in such a way that, in top-plan view, each of them has a width which decreases moving away from the first conductive pad; the drain metal bus includes subregions shaped in such a way that, in top-plan view, each of them has a width which decreases moving away from the second conductive pad. The first and second subregions are interdigitated.

IPC Classes  ?

  • H01L 23/528 - Layout of the interconnection structure
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body

9.

NON-VOLATILE PHASE-CHANGE MEMORY DEVICE INCLUDING A DISTRIBUTED ROW DECODER WITH N-CHANNEL MOSFET TRANSISTORS AND RELATED ROW DECODING METHOD

      
Application Number 18406097
Status Pending
Filing Date 2024-01-06
First Publication Date 2024-05-09
Owner
  • STMicroelectronics (Grenoble 2) SAS (France)
  • STMicroelectronics S.r.l. (Italy)
Inventor
  • Conte, Antonino
  • Razafindraibe, Alin
  • Tomaiuolo, Francesco
  • Mortier, Thibault

Abstract

In an embodiment, a non-volatile memory device is proposed. The device includes a plurality of local pull-up stages distributed along a group of memory portions in a memory array. Each local pull-up stage includes, for each wordline that extends through the group of memory portions, a corresponding local pull-up transistor of an NMOS type. The local pull-up transistors of each local pull-up are configured to locally decouple the corresponding wordline from a node at a first reference potential in response to a wordline that extends through the group of memory portions being selected, and locally couple the corresponding wordline to the node at the first reference potential in response to all the wordlines that extend through the group of memory portions being deselected to restore locally a deselection voltage on a wordline previously selected.

IPC Classes  ?

  • G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or

10.

OSCILLATOR CIRCUIT, CORRESPONDING RADAR SENSOR, VEHICLE AND METHOD OF OPERATION

      
Application Number 18418298
Status Pending
Filing Date 2024-01-21
First Publication Date 2024-05-09
Owner STMicroelectronics S.r.l. (Italy)
Inventor
  • Parisi, Alessandro
  • Cavarra, Andrea
  • Finocchiaro, Alessandro
  • Papotto, Giuseppe
  • Palmisano, Giuseppe

Abstract

A flash analog-to-digital converter (ADC) receives an input control signal and performs coarse tuning of a frequency of an output signal, produced between first and second nodes having an inductance coupled therebetween. The flash ADC quantizes an operating frequency range for the output signal produced between the first and second nodes as M·Δf, where M is an integer from 0 to N−1, where N is a number of intervals into which a frequency range for the output signal is divided, and where Δf is a resulting frequency step produced by the quantizing. The value of M is generated based upon the input control signal and a word controlling switches of a plurality of switched capacitance circuits associated with the first and second nodes to close ones of those switches associated with the control word to coarsely tune the frequency of the output signal.

IPC Classes  ?

  • G01S 13/58 - Velocity or trajectory determination systems; Sense-of-movement determination systems
  • G01S 7/40 - Means for monitoring or calibrating
  • G01S 13/931 - Radar or analogous systems, specially adapted for specific applications for anti-collision purposes of land vehicles
  • H03B 5/12 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
  • H03L 7/099 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
  • H03L 7/10 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
  • H03L 7/193 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number the frequency divider/counter comprising a commutable pre-divider, e.g. a two modulus divider

11.

MEMS DEVICE HAVING IMPROVED DETECTION PERFORMANCES

      
Application Number 18496653
Status Pending
Filing Date 2023-10-27
First Publication Date 2024-05-09
Owner STMICROELECTRONICS S.r.l. (Italy)
Inventor
  • Riani, Manuel
  • Gattere, Gabriele
  • Rizzini, Francesco

Abstract

The MEMS device is formed by a substrate and a movable structure suspended on the substrate. The movable structure has a first mass, a second mass and a first elastic group mechanically coupled between the first and the second masses. The first elastic group is compliant along a first direction. The first mass is configured to move with respect to the substrate along the first direction. The MEMS device also has a second elastic group mechanically coupled between the substrate and the movable structure and compliant along the first direction; and an anchoring control structure fixed to the substrate, capacitively coupled to the second mass and configured to exert an electrostatic force on the second mass along the first direction. The anchoring control structure controls the MEMS device in a first operating state, wherein the second mass is free to move with respect to the substrate along the first direction, and in a second operating state, wherein the anchoring control structure applies a pull-in force on the second mass which anchors the second mass to the anchoring structure.

IPC Classes  ?

  • G01P 15/125 - Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces with conversion into electric or magnetic values by capacitive pick-up

12.

PIEZOELECTRIC MICROELECTROMECHANICAL RESONATOR DEVICE AND CORRESPONDING MANUFACTURING PROCESS

      
Application Number 18505574
Status Pending
Filing Date 2023-11-09
First Publication Date 2024-05-09
Owner STMICROELECTRONICS S.r.l. (Italy)
Inventor
  • Vercesi, Federico
  • Corso, Lorenzo
  • Allegato, Giorgio
  • Gattere, Gabriele

Abstract

A microelectromechanical resonator device has: a main body, with a first surface and a second surface, opposite to one another along a vertical axis, and made of a first layer and a second layer, arranged on the first layer; a cap, having a respective first surface and a respective second surface, opposite to one another along the vertical axis, and coupled to the main body by bonding elements; and a piezoelectric resonator structure formed by: a mobile element, constituted by a resonator portion of the first layer, suspended in cantilever fashion with respect to an internal cavity provided in the second layer and moreover, on the opposite side, with respect to a housing cavity provided in the cap; a region of piezoelectric material, arranged on the mobile element on the first surface of the main body; and a top electrode, arranged on the region of piezoelectric material, the mobile element constituting a bottom electrode of the piezoelectric resonator structure.

IPC Classes  ?

  • H03H 9/10 - Mounting in enclosures
  • B81B 7/00 - Microstructural systems
  • B81C 1/00 - Manufacture or treatment of devices or systems in or on a substrate
  • H03H 3/02 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
  • H03H 9/17 - Constructional features of resonators consisting of piezoelectric or electrostrictive material having a single resonator

13.

TRIMMING PROCEDURE AND CODE REUSE FOR HIGHLY PRECISE DC-DC CONVERTERS

      
Application Number 17980188
Status Pending
Filing Date 2022-11-03
First Publication Date 2024-05-09
Owner STMicroelectronics S.r.l. (Italy)
Inventor
  • Attanasio, Marco
  • Ramorini, Stefano

Abstract

A converter system includes a reference buffer buffering a reference input to produce a DAC reference, operating from a reference feedback voltage generated by a reference divider. A tail buffer generates a tail voltage from an input voltage generated from the DAC reference by a tail divider. An R-2R type DAC utilizes an R-2R ladder to generate a DAC output from a code. This ladder has a tail resistor coupled to the tail voltage. A feedback buffer buffers the DAC output to produce a converter reference. A DC-DC converter generates a DC output from a DC input, based upon a converter feedback voltage. A feedback divider coupled between the DC output and the converter reference generates the converter feedback voltage. Control circuitry selectively taps the reference divider to produce the reference feedback voltage (performing gain trimming) and selectively taps the tail divider to produce the input voltage (performing offset trimming).

IPC Classes  ?

  • H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion
  • H02M 3/04 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
  • H03M 1/10 - Calibration or testing

14.

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES, CORRESPONDING COMPONENT, SEMICONDUCTOR DEVICE AND METHOD

      
Application Number 18385996
Status Pending
Filing Date 2023-11-01
First Publication Date 2024-05-02
Owner STMicroelectronics S.r.l. (Italy)
Inventor Mazzola, Mauro

Abstract

A leadframe includes a die pad and electrically conductive leads arranged peripherally of the die pad. A semiconductor die is mounted to the die pad. The die is electrically coupled to the electrically conductive leads using an electrical coupling member applied onto the semiconductor die. The electrical coupling member includes a planar body configured to cover the semiconductor die and the electrically conductive leads. The planar body of the electrical coupling member includes strip-like, electrically conductive formations embedded in an electrically insulating material. Each strip-like, electrically conductive formation has a first end configured to contact the semiconductor die and a second end configured to contact the electrically conductive lead.

IPC Classes  ?

  • H01L 23/495 - Lead-frames
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices

15.

SEMICONDUCTOR DEVICE AND CORRESPONDING METHOD

      
Application Number 18386069
Status Pending
Filing Date 2023-11-01
First Publication Date 2024-05-02
Owner STMicroelectronics S.r.l. (Italy)
Inventor
  • Sanna, Aurora
  • Somma, Cristina
  • Halicki, Damian

Abstract

A BGA package includes an array of electrically conductive balls providing electrical contact for a semiconductor die. A power channel is provided to convey power supply current towards the semiconductor die. The power channel is formed by a stack of electrically conductive planes. The electrically conductive planes are stacked in a stepped arrangement wherein a number of stacked planes in each step of the stack increases in a direction from a distal end to a proximal end of the power channel. Adjacent electrically conductive planes in the stack of the power channel are electrically coupled with electrically conductive vias extending therebetween. Current conduction paths towards the die area thus have resistance values that decrease from the distal end to the proximal end of the power channel.

IPC Classes  ?

  • H01L 23/498 - Leads on insulating substrates
  • H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
  • H01L 23/528 - Layout of the interconnection structure

16.

METHOD FOR DETECTING THE PRESENCE OF A LIQUID

      
Application Number 18458765
Status Pending
Filing Date 2023-08-30
First Publication Date 2024-05-02
Owner STMICROELECTRONICS S.r.l. (Italy)
Inventor
  • Rivolta, Stefano Paolo
  • Labombarda, Andrea
  • Guadalupi, Carlo
  • Bardone, Mauro

Abstract

The present disclosure is directed to a method for detecting a liquid on a main surface of a body. The method is performed through a detection device including a processing module, a reference electrode at a reference electric voltage and a first sensing electrode on the main surface and configurated to detect an environmental electric and/or electrostatic charge variation indicative of the presence of the liquid. The method includes the steps of: biasing the first sensing electrode to a bias electric voltage; while the first sensing electrode is at the bias electric voltage, acquiring a first charge variation signal indicative of the electric and/or electrostatic charge variation detected by the first sensing electrode; verifying whether the first charge variation signal is indicative of the presence of the liquid on the main surface, at the first sensing electrode; and, if it is, determining the presence of the liquid on the main surface at the first sensing electrode.

IPC Classes  ?

  • G01F 23/80 - Arrangements for signal processing
  • G01F 23/00 - Indicating or measuring liquid level or level of fluent solid material, e.g. indicating in terms of volume or indicating by means of an alarm

17.

METHOD FOR MANUFACTURING A DEVICE COMPRISING TWO SEMICONDUCTOR DICE AND A DEVICE THEREOF

      
Application Number 18489729
Status Pending
Filing Date 2023-10-18
First Publication Date 2024-05-02
Owner STMICROELECTRONICS S.r.l. (Italy)
Inventor
  • Shaw, Mark Andrew
  • Corso, Lorenzo
  • Garavaglia, Matteo
  • Allegato, Giorgio

Abstract

A device and method for manufacturing a device comprising two semiconductor dice. The device is formed by a first die and a second die. The first die is of semiconductor material and integrates electronic components. The second die has a main surface, forms patterned structures, and is bonded to the first die. Internal electrical coupling structures electrically couple the main surface of the first die to the second die. External connection regions extend on the main surface of the first die. A package packages the first die, the second die and the internal electrical coupling structures and partially surrounds the external connection regions, the external connection regions partially protruding from the package.

IPC Classes  ?

  • B81B 7/00 - Microstructural systems
  • B81C 1/00 - Manufacture or treatment of devices or systems in or on a substrate

18.

METHOD OF PROCESSING ARTICLES AND CORRESPONDING APPARATUS

      
Application Number 18496643
Status Pending
Filing Date 2023-10-27
First Publication Date 2024-05-02
Owner STMICROELECTRONICS S.r.l. (Italy)
Inventor Crema, Paolo

Abstract

Articles such as substrates for semiconductor products comprising metal and resin portions with adhesion promoter material are processed in a plating bath, wherein the adhesion promoter material is exposed to dissolution as a result of prolonged exposure to the plating bath. The articles are processed by dipping them in the processing bath so that they have opposed surfaces exposed to the processing bath. Articles such as substrates for semiconductor products comprising metal and resin portions with adhesion promoter material are processed in a plating bath, wherein the adhesion promoter material is exposed to dissolution as a result of prolonged exposure to the plating bath. The articles are processed by dipping them in the processing bath so that they have opposed surfaces exposed to the processing bath. The movement of the articles through the processing bath B may occur to be halted. In that case a gas flow is provided lapping the opposed surfaces of the articles to shield the opposed surfaces of the articles from exposure to the processing bath.

IPC Classes  ?

  • C25D 21/04 - Removal of gases or vapours
  • C25D 7/12 - Semiconductors
  • C25D 17/00 - Constructional parts, or assemblies thereof, of cells for electrolytic coating

19.

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES, CORRESPONDING SEMICONDUCTOR DEVICE, ASSEMBLY AND SUPPORT SUBSTRATE

      
Application Number 18384524
Status Pending
Filing Date 2023-10-27
First Publication Date 2024-05-02
Owner STMicroelectronics S.r.l. (Italy)
Inventor
  • De Santa, Matteo
  • Mazzola, Mauro

Abstract

A semiconductor die is arranged on a first surface of a leadframe having a first thickness between the first surface and a second surface opposite the first surface and an array of electrically conductive leads. Terminal recesses are provided in the electrically conductive leads in the array at the first surface. At the terminal recesses, the electrically conductive leads have a second thickness less than the first thickness. The semiconductor die is coupled with the electrically conductive leads via wires or ribbons having ends coupled to the electrically conductive leads arranged in the terminal recesses. The leadframe is partially cut starting from the second surface at the terminal recesses with a cutting depth between the first thickness and the second thickness. The partial cut produces exposed surfaces of the electrically conductive leads and the ends of the electrically conductive elongated formations providing wettable flanks for solder material.

IPC Classes  ?

  • H01L 23/495 - Lead-frames
  • H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H05K 1/18 - Printed circuits structurally associated with non-printed electric components
  • H05K 3/34 - Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering

20.

MICROELECTROMECHANICAL GYROSCOPE WITH DETECTION OF ANGULAR VELOCITY ALONG A VERTICAL AXIS

      
Application Number 18490392
Status Pending
Filing Date 2023-10-19
First Publication Date 2024-05-02
Owner STMICROELECTRONICS S.r.l. (Italy)
Inventor
  • Carulli, Paola
  • Falorni, Luca Giuseppe
  • Fedeli, Patrick
  • Guerinoni, Luca

Abstract

A microelectromechanical gyroscope with detection along a vertical axis is provided with a detection structure having a movable structure, suspended above a substrate so as to perform, as a function of an angular velocity around the vertical axis a sense movement along a first horizontal axis. The movable structure has at least one drive mass internally defining a window, elastically coupled to a rotor anchor, at an anchoring region, through elastic anchoring elements; at least one bridge element, rigid and of a conductive material, cantilevered suspended and extending within the window along the first horizontal axis, elastically coupled to the drive mass; movable electrodes, carried integrally by the bridge element with extension along a second horizontal axis. The detection structure also has stator electrodes, arranged in the window and interdigitated with the movable electrodes, at a certain separation distance below the bridge element, which extends longitudinally above the same stator electrodes and the movable electrodes.

IPC Classes  ?

  • G01C 19/5762 - Structural details or topology the devices having a single sensing mass the sensing mass being connected to a driving mass, e.g. driving frames

21.

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES, CORRESPONDING LEADFRAME, MOLD AND SEMICONDUCTOR DEVICE

      
Application Number 18496634
Status Pending
Filing Date 2023-10-27
First Publication Date 2024-05-02
Owner STMICROELECTRONICS S.r.l. (Italy)
Inventor
  • Villa, Riccardo
  • Catalano, Guendalina

Abstract

Laser direct structuring, LDS material is molded onto semiconductor dice arranged on die pads in a leadframe and the semiconductor dice are electrically coupled with electrically conductive leads in the leadframe via electrical connections that comprise electrically conductive formations exposed at the front surface of the LDS material, electrically conductive vias between the semiconductor dice and the front surface of the LDS material, as well as electrically conductive lines over the front surface of the LDS material that couple selected ones of the electrically conductive formations with selected ones of the second electrically conductive vias. The electrically conductive vias and lines are provided applying laser beam energy to the front surface of the laser direct structuring material at spatial positions located as a function of the electrically conductive formations exposed at the front surface of the LDS material acting as fiducials. The electrically conductive formations exposed at the front surface of the LDS material may comprise pillar-like extensions of the leadframe leads, electrically conductive material grown on the leads in cavities in the front surface of the LDS material or electrically conductive leads in a lead frame where the die pads are downset with respect to the leads.

IPC Classes  ?

  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
  • H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
  • H01L 23/495 - Lead-frames

22.

DYNAMIC BIAS FOR BOOTSTRAP RECHARGE IN DISCONTINUOUS MODE DC-DC CONVERTERS

      
Application Number 17979156
Status Pending
Filing Date 2022-11-02
First Publication Date 2024-05-02
Owner STMicroelectronics S.r.l. (Italy)
Inventor
  • Attanasio, Marco
  • Bellotti, Giovanni

Abstract

Disclosed herein is a DC-DC converter including a power section and a bootstrap circuit for driving the gate of the high-side transistor of the power section. The bootstrap circuit includes an adaptive clamp circuit that maintains a proper voltage differential across the bootstrap capacitor within the bootstrap circuit for recharge during off-times regardless of whether the mode of operation of the DC-DC converter continuous conduction mode (CCM), discontinuous conduction mode (DCM), or pulse-skip mode. This voltage differential is established as being between a bootstrap voltage and a voltage at a tap between the high and low side transistors of the power section. The adaptive clamp circuit maintains the bootstrap voltage as following the lesser of the output voltage and the voltage at the tap.

IPC Classes  ?

  • H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
  • H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters

23.

SYSTEM AND METHOD FOR DETERMINING WHETHER AN ELECTRONIC DEVICE IS LOCATED ON A STATIONARY OR STABLE SURFACE

      
Application Number 18048360
Status Pending
Filing Date 2022-10-19
First Publication Date 2024-04-25
Owner STMicroelectronics S.r.l. (Italy)
Inventor
  • Rivolta, Stefano Paolo
  • Rizzardini, Federico

Abstract

A method includes receiving electrostatic sensor data in a processor of an electronic device from an electrostatic sensor mounted behind a touchscreen of the electronic device and using the electrostatic sensor data to determine when the touchscreen is being used. Based on whether or not the touchscreen is being used, an on-table detection (OTD) algorithm is selected from a plurality of available OTD algorithms. In one or more examples, the OTD algorithm may also be selected based on the current device mode of the electronic device, which may be determined from a lid angle, a screen angle, and a keyboard angle of the electronic device. The selected OTD algorithm is run to determine whether or not the electronic device is located on a stationary or stable surface.

IPC Classes  ?

  • G06F 3/0346 - Pointing devices displaced or positioned by the user; Accessories therefor with detection of the device orientation or free movement in a 3D space, e.g. 3D mice, 6-DOF [six degrees of freedom] pointers using gyroscopes, accelerometers or tilt-sensors
  • G06F 3/0354 - Pointing devices displaced or positioned by the user; Accessories therefor with detection of 2D relative movements between the device, or an operating part thereof, and a plane or surface, e.g. 2D mice, trackballs, pens or pucks

24.

METHOD FOR PERFORMING A CORRECTION OF AN IONOSPHERIC ERROR AFFECTING PSEUDO-RANGE MEASUREMENTS IN A GNSS RECEIVER, CORRESPONDING RECEIVER APPARATUS AND COMPUTER PROGRAM PRODUCT

      
Application Number 18481147
Status Pending
Filing Date 2023-10-04
First Publication Date 2024-04-25
Owner STMICROELECTRONICS S.r.l. (Italy)
Inventor
  • Renna, Michele
  • Palella, Nicola Matteo

Abstract

A method corrects an ionospheric error affecting pseudo-range measurements in a GNSS receiver receiving a plurality of satellite signals from a plurality of satellites of the constellation of satellites. The method is performed in a navigation processing procedure performed at a GNSS receiver, receiving pseudo-range measurements previously calculated by the GNSS receiver obtained from a first carrier signal and a second carrier signal in the satellite signals, in particular in GPS bands L1 and L5. The method includes performing a correction procedure of the pseudo-range measurements including applying to the pseudo-range measurements corrections for predictable errors obtaining corrected pseudo-ranges and applying to the corrected pseudo-range measurements a further ionospheric error correction calculation to obtain further ionospheric error correction values.

IPC Classes  ?

  • G01S 19/07 - Cooperating elements; Interaction or communication between different cooperating elements or between cooperating elements and receivers providing data for correcting measured positioning data, e.g. DGPS [differential GPS] or ionosphere corrections
  • G01S 19/04 - Cooperating elements; Interaction or communication between different cooperating elements or between cooperating elements and receivers providing carrier phase data

25.

SYSTEM FOR MONITORING DEFECTS WITHIN AN INTEGRATED SYSTEM PACKAGE

      
Application Number 18489737
Status Pending
Filing Date 2023-10-17
First Publication Date 2024-04-25
Owner STMICROELECTRONICS S.r.l. (Italy)
Inventor
  • Giusti, Domenico
  • Del Sarto, Marco
  • Quaglia, Fabio
  • Duqi, Enri

Abstract

An integrated electronic system is provided with a package formed by a support base and a coating region arranged on the support base and having at least a first system die, including semiconductor material, coupled to the support base and arranged in the coating region. The integrated electronic system also has, within the package, a monitoring system configured to determine the onset of defects within the coating region, through the emission of acoustic detection waves and the acquisition of corresponding received acoustic waves, whose characteristics are affected by, and therefore are indicative of, the aforementioned defects.

IPC Classes  ?

26.

PACKAGED HIGH VOLTAGE MOSFET DEVICE WITH CONNECTION CLIP AND MANUFACTURING PROCESS THEREOF

      
Application Number 18493686
Status Pending
Filing Date 2023-10-23
First Publication Date 2024-04-25
Owner STMICROELECTRONICS S.r.l. (Italy)
Inventor
  • Stella, Cristiano Gianluca
  • Russo, Fabio

Abstract

An HV MOSFET device has a body integrating source conductive regions. Projecting gate structures are disposed above the body, laterally offset with respect to the source conductive regions. Source contact regions, of a first metal, are arranged on the body in electric contact with the source conductive regions, and source connection regions, of a second metal, are arranged above the source contact regions and have a height protruding with respect to the projecting gate structures. A package includes a metal support bonded to a second surface of the body, and a dissipating region, above the first surface of the semiconductor die. The dissipating region includes a conductive plate having a planar face bonded to the source connection regions and spaced from the projecting gate structures. A package mass of dielectric material is disposed between the support and the dissipating region and incorporates the semiconductor die. The dissipating region is a DBC-type insulation multilayer.

IPC Classes  ?

  • H01L 23/495 - Lead-frames
  • H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
  • H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
  • H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement

27.

DC-DC CONVERTER APPARATUS AND CORRESPONDING CONTROL METHOD

      
Application Number 18376277
Status Pending
Filing Date 2023-10-03
First Publication Date 2024-04-18
Owner STMicroelectronics S.r.l. (Italy)
Inventor
  • Bertolini, Alessandro
  • Gasparini, Alessandro
  • Melillo, Paolo
  • Levantino, Salvatore
  • Ghioni, Massimo

Abstract

A boost DC-DC converter includes a switching network, coupled to an inductor, controlled by a PWM driving signal. A control loop receives a voltage output and provides the PWM driving signal. The control loop generates an error signal as a function of a difference between voltage output voltage and a reference, with the PWM driving signal generated based on the error signal. A low pass filter circuit within the control loop receives the PWM driving signal and provides at least one filtered signal. An adder node of the control loop receives the at least one filtered signal from the low pass filter circuit for addition to the at least one filtered signal. The PWM driving signal is generated as a function of a sum of the filtered signal and the error signal.

IPC Classes  ?

  • H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
  • H02M 3/157 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control

28.

VOLTAGE REGULATOR CIRCUIT AND CORRESPONDING DEVICE

      
Application Number 18462997
Status Pending
Filing Date 2023-09-07
First Publication Date 2024-04-18
Owner STMicroelectronics S.r.l. (Italy)
Inventor Rizzo, Alessandro

Abstract

A circuit includes a supply node receiving a supply voltage; an output node providing a regulated voltage; startup circuitry coupled to the supply node; current generator circuitry coupled to the startup circuitry and producing a current; a bandgap node coupled to bandgap circuitry to receive a bandgap voltage; multiplier circuitry coupled to the bandgap node and the current generator circuitry to receive and apply scaling to the current; a first transistor providing a threshold voltage drop across the first and second transistor nodes; a first resistive element interposed between the first transistor and the bandgap node; a second resistive element coupled between ground and the second node of the first transistor; and an operational amplifier receiving a pre-regulated voltage as a function of the bandgap voltage, the threshold voltage across the first transistor, and a voltage drop across the first and second resistive elements.

IPC Classes  ?

  • G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
  • G05F 1/46 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc
  • G05F 3/26 - Current mirrors

29.

USB INTERFACE

      
Application Number 18389940
Status Pending
Filing Date 2023-12-20
First Publication Date 2024-04-18
Owner
  • STMicroelectronics ( Grenoble 2) SAS (France)
  • STMicroelectronics S.r.l. (Italy)
Inventor
  • Camiolo, Jean
  • Ferrazza, Francesco
  • Ballot, Nathalie

Abstract

In an embodiment, a USB interface includes a transformer, a primary winding of the transformer, and a first switch in series between a first and a second node, a secondary winding of the transformer and a component in series between a third and a fourth node, the fourth node configured to be set a first reference potential, a second switch connected between the third node and a first terminal, the first terminal configured to provide an output voltage of the USB interface; wherein the component is configured to avoid a current circulation in the secondary winding when the first switch is closed and a control circuit configured to compare a first voltage of an interconnection node between the secondary winding and the component to a first threshold and compare the first voltage to a second threshold when the first voltage is, in absolute values, above the first threshold.

IPC Classes  ?

  • H02M 3/335 - Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
  • G06F 13/42 - Bus transfer protocol, e.g. handshake; Synchronisation
  • H02M 1/32 - Means for protecting converters other than by automatic disconnection

30.

PROCESS FOR MANUFACTURING A MICRO-ELECTRO-MECHANICAL DEVICE INCLUDING TWO CHAMBERS AT DIFFERENT PRESSURES AND RELATED MICRO-ELECTRO-MECHANICAL DEVICE

      
Application Number 18486044
Status Pending
Filing Date 2023-10-12
First Publication Date 2024-04-18
Owner STMICROELECTRONICS S.r.l. (Italy)
Inventor
  • Ferrari, Paolo
  • Villa, Flavio Francesco

Abstract

Process for manufacturing a MEMS device, including: forming a dielectric region which coats part of a semiconductive substrate of a first semiconductive wafer; forming a region which is permeable to gases and coats the dielectric region; coupling the first semiconductive wafer to a second semiconductive wafer so as to form a first chamber, which houses a first movable mass and has a pressure equal to a first value, and a second chamber, which houses a second movable mass and has a pressure equal to the first value, the permeable region facing the second chamber; selectively removing a portion of the semiconductor substrate and an underlying portion of the dielectric region, so as to expose a part of the permeable region, so as to allow gas exchanges through the permeable region; placing the first and the second semiconductive wafers in an environment with a pressure equal to a second value, so that the pressure in the second chamber becomes equal to the second value; and subsequently forming, on the exposed part of the permeable region, a sealing region impermeable to gases.

IPC Classes  ?

  • B81C 1/00 - Manufacture or treatment of devices or systems in or on a substrate
  • B81B 3/00 - Devices comprising flexible or deformable elements, e.g. comprising elastic tongues or membranes

31.

MICRO ELECTRO MECHANICAL SYSTEM AND MANUFACTURING METHOD THEREOF

      
Application Number 18535923
Status Pending
Filing Date 2023-12-11
First Publication Date 2024-04-18
Owner STMICROELECTRONICS S.r.l. (Italy)
Inventor
  • Longoni, Gianluca
  • Seghizzi, Luca

Abstract

A MEMS device is provided that includes a semiconductor substrate including a main surface extending perpendicular to a first direction and a side surface extending on a plane parallel to the first direction and to a second direction that is perpendicular to the first direction. At least one cantilevered member protrudes from the side surface of the semiconductor substrate along a third direction that is perpendicular to the first and second directions. The at least one cantilevered member includes a body portion that includes a piezoelectric material. The body portion has a length along the third direction, a height along the first direction and a width along the second direction, and the height is greater than the width. The at least one cantilevered member is configured to vibrate by lateral bending along a direction perpendicular to the first direction.

IPC Classes  ?

  • H10N 30/20 - Piezoelectric or electrostrictive devices with electrical input and mechanical output, e.g. functioning as actuators or vibrators
  • B81B 3/00 - Devices comprising flexible or deformable elements, e.g. comprising elastic tongues or membranes
  • H02N 2/18 - Electric machines in general using piezoelectric effect, electrostriction or magnetostriction producing electrical output from mechanical input, e.g. generators
  • H10N 30/00 - Piezoelectric or electrostrictive devices
  • H10N 30/05 - Manufacture of multilayered piezoelectric or electrostrictive devices, or parts thereof, e.g. by stacking piezoelectric bodies and electrodes
  • H10N 30/074 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by depositing piezoelectric or electrostrictive layers, e.g. aerosol or screen printing
  • H10N 30/85 - Piezoelectric or electrostrictive active materials

32.

METHOD OF PRODUCING SEMICONDUCTOR DEVICES AND CORRESPONDING SEMICONDUCTOR DEVICE

      
Application Number 18390544
Status Pending
Filing Date 2023-12-20
First Publication Date 2024-04-11
Owner
  • STMicroelectronics S.r.l. (Italy)
  • STMicroelectronics SDN BHD (Malaysia)
Inventor
  • Albertinetti, Andrea
  • Cagud, Marifi Corregidor

Abstract

A warped semiconductor die is attached onto a substrate such as a leadframe by dispensing a first mass of die attach material onto an area of the substrate followed by dispensing a second mass of die attach material so that the second mass of die attach material provides a raised formation of die attach material. For instance, the second mass may be deposited centrally of the first mass. The semiconductor die is placed onto the first and second mass of die attach material with its concave/convex shape matching the distribution of the die attach material thus effectively countering undesired entrapment of air.

IPC Classes  ?

  • H01L 23/498 - Leads on insulating substrates
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices

33.

METHOD FOR GENERATING COMPUTER-EXECUTABLE CODE FOR IMPLEMENTING AN ARTIFICIAL NEURAL NETWORK

      
Application Number 18470798
Status Pending
Filing Date 2023-09-20
First Publication Date 2024-04-11
Owner
  • STMicroelectronics S.r.l. (Italy)
  • STMicroelectronics (Rousset) SAS (France)
Inventor
  • Folliot, Laurent
  • Lattuada, Marco
  • Demaj, Pierre

Abstract

In an embodiments a method includes obtaining a neural network (INN), the neural network having a plurality of neural layers, each layer being capable of being executed according to different implementation solutions and impacting a required memory allocation for the execution of the neural network and/or an execution time of the neural network, defining a maximum execution time threshold of the neural network and/or a maximum required memory allocation threshold for the execution of the neural network, determining an optimal required memory allocation size for the execution of the neural network from possible implementation solutions for each layer of the neural network, determining an optimal execution time of the neural network from the possible implementation solutions for each layer of the neural network and estimating a performance loss or a performance gain in terms of execution time and required memory allocation for each implementation solution of each layer of the neural network.

IPC Classes  ?

  • G06N 3/10 - Interfaces, programming languages or software development kits, e.g. for simulating neural networks
  • G06F 8/35 - Creation or generation of source code model driven
  • G06F 8/41 - Compilation

34.

INTEGRATED CIRCUIT CHIP INCLUDING A PASSIVATION NITRIDE LAYER IN CONTACT WITH A HIGH VOLTAGE BONDING PAD AND METHOD OF MAKING

      
Application Number 18544747
Status Pending
Filing Date 2023-12-19
First Publication Date 2024-04-11
Owner STMicroelectronics S.r.l. (Italy)
Inventor
  • Mariani, Simone Dario
  • Pizzi, Elisabetta
  • Doria, Daria

Abstract

A back end of line (BEOL) structure for an integrated circuit chip includes a last metal structure providing a bonding pad. A passivation structure over the bonding pad includes a first opening extending exposing an upper surface of the bonding pad. A conformal nitride layer extends over the passivation structure and is placed in contact with the upper surface of the bonding pad. An insulator material layer covers the conformal nitride layer and includes a second opening that extends through both the insulator material layer and the conformal nitride layer. A foot portion of the conformal nitride layer on the upper surface of the bonding pad is self-aligned with the second opening.

IPC Classes  ?

  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings

35.

DC-DC CONVERTER CIRCUIT AND CORRESPONDING METHOD OF OPERATION

      
Application Number 18376328
Status Pending
Filing Date 2023-10-03
First Publication Date 2024-04-11
Owner STMicroelectronics S.r.l. (Italy)
Inventor
  • Bertolini, Alessandro
  • Cattani, Alberto
  • Gasparini, Alessandro

Abstract

In a DC-DC converter, a duty-cycle control signal is generated in response to comparing the switching stage output voltage and a reference voltage signal. A first circuit compares the duty-cycle control signal and a ramp to produce a PWM signal. A second circuit compares the duty-cycle control signal and a skip threshold to produce a skip control signal which halts switching operation of the switching stage. A count is made of number of periods of the skip control signal during a monitoring time window and the number of periods of a clock signal during a period of the skip control signal is counted. When the counted number of skip control signal periods is within a first range and the counted number of clock signal periods is within a second range, a common detection signal is asserted to trigger varying a value of the skip threshold signal.

IPC Classes  ?

  • H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
  • H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion

36.

SIC-BASED ELECTRONIC DEVICE WITH IMPROVED BODY-SOURCE COUPLING, AND MANUFACTURING METHOD

      
Application Number 18471219
Status Pending
Filing Date 2023-09-20
First Publication Date 2024-04-04
Owner STMICROELECTRONICS S.r.l. (Italy)
Inventor
  • Scalia, Laura Letizia
  • Camalleri, Cateno Marco
  • Fragapane, Leonardo

Abstract

Electronic device, comprising: a semiconductor body having a surface; a body region in the semiconductor body, extending along a main direction parallel to the surface of the semiconductor body; and a source region in the body region, extending along the main direction. The electronic device has, at the body and source regions, a first and a second electrical contact region alternating with each other along the main direction, wherein the first electrical contact region exposes the body region, and the second electrical contact region exposes the source region. The electronic device further comprises an electrical connection layer extending with electrical continuity longitudinally to the body and source regions, in electrical connection with the first and the second electrical contact regions.

IPC Classes  ?

  • H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
  • H01L 29/40 - Electrodes
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

37.

CIRCUIT ARRANGEMENT COMPRISING A MOS SENSOR, IN PARTICULAR TMOS SENSOR, AND A CORRESPONDING METHOD FOR OPERATING THE CIRCUIT ARRANGEMENT

      
Application Number 18370052
Status Pending
Filing Date 2023-09-19
First Publication Date 2024-03-28
Owner STMicroelectronics S.r.l. (Italy)
Inventor
  • Ippolito, Calogero Marco
  • Vaiana, Michele

Abstract

A differential pair of FETs forms a sensor circuit coupled to a differential current reading circuit that includes a current to voltage converter and an analog to digital converter. An ESD protection circuit interposed between the sensor circuit and the differential current reading circuit adds spurious currents to a differential sensor current output by the sensor circuit. A circuit before the ESD protection circuit switches the sign of the differential sensor current according to a period of complementary phase clock signals which correspond to a sampling interval of the analog to digital converter. A circuit selects signals depending on the value of the period of the phase clock signals to eliminate the spurious currents.

IPC Classes  ?

  • H03M 1/12 - Analogue/digital converters
  • H03M 3/00 - Conversion of analogue values to or from differential modulation

38.

METHOD FOR SENSING A CURRENT FLOWING IN A TRANSISTOR DRIVING A LOAD, AND CORRESPONDING CIRCUIT ARRANGEMENT FOR SENSING

      
Application Number 18371313
Status Pending
Filing Date 2023-09-21
First Publication Date 2024-03-28
Owner STMicroelectronics S.r.l. (Italy)
Inventor
  • De Vita, Placido
  • Abbisso, Salvatore
  • Torrisi, Giovanni Luca
  • Leone, Antonio Davide

Abstract

A pre-driving stage drives one or more Field Effect Transistors in a power stage driving a load. A method for measuring current flowing in the Field Effect Transistors includes: measuring drain to source voltages of the one or more Field Effect Transistor; and measuring an operating temperature of the one or more Field Effect Transistor. The current flowing in the Field Effect Transistors is measured by: calculating the respective on drain to source resistance at the operating temperature as a function of the measured operating temperature and obtaining the current value as a ratio of the respective measured drain to source voltage over the calculated drain to source resistance at the operating temperature.

IPC Classes  ?

  • G01R 17/16 - Measuring arrangements involving comparison with a reference value, e.g. bridge ac or dc measuring bridges with discharge tubes or semiconductor devices in one or more arms of the bridge, e.g. voltmeter using a difference amplifier
  • G01R 17/04 - Arrangements in which the value to be measured is automatically compared with a reference value in which the reference value is continuously or periodically swept over the range of values to be measured
  • G01R 19/00 - Arrangements for measuring currents or voltages or for indicating presence or sign thereof
  • G01R 19/165 - Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
  • G01R 19/257 - Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques using analogue/digital converters of the type with comparison of different reference values with the value of voltage or current, e.g. using step-by-step method

39.

MEASUREMENT SYSTEM, RELATED INTEGRATED CIRCUIT AND METHOD

      
Application Number 18369583
Status Pending
Filing Date 2023-09-18
First Publication Date 2024-03-28
Owner STMicroelectronics S.r.l. (Italy)
Inventor
  • Nicollini, Germano
  • Vaiana, Michele

Abstract

A measurement system, featuring first and second capacitances, and switching, control, and measurement circuits, charges/discharges the capacitances during normal operation. The switching and control circuits periodically connect a first terminal of the first capacitance to a first voltage and a reference voltage, and a first terminal of the second capacitance to a second voltage and the reference voltage. The second terminal of the first capacitance and the second terminal of the second capacitance are connected to the input terminals of the differential integrator, the charge difference between the capacitances being transferred to the differential integrator. A comparator triggers when the output signal of the differential integrator exceeds the hysteresis threshold of the comparator. Two decoupling capacitances are connected between the input of the comparator and the output of the differential integrator, and two reset phases are used to store various disturbances to these decoupling capacitances, improving precision.

IPC Classes  ?

  • H03F 3/45 - Differential amplifiers
  • H03F 1/26 - Modifications of amplifiers to reduce influence of noise generated by amplifying elements

40.

OPTOELECTRONIC DEVICE

      
Application Number 18527968
Status Pending
Filing Date 2023-12-04
First Publication Date 2024-03-28
Owner
  • STMicroelectronics (Grenoble 2) SAS (France)
  • STMicroelectronics S.r.l. (Italy)
Inventor
  • Steckel, Jonathan
  • Conti, Giovanni
  • L'Episcopo, Gaetano
  • Aleo, Mario Antonio
  • Occhipinti, Carmelo

Abstract

An optoelectronic device includes a backlight panel illuminating a display panel. The backlight panel includes an array of light emitting pixels, each light emitting pixel having at least one subpixel with one or more light emitting diodes positioned on a substrate. The pixel further includes at least one photodetector positioned on the substrate and arranged to detect an amount of reflected light emitted by said subpixel and reflected by the display panel.

IPC Classes  ?

  • G09G 3/34 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix by control of light from an independent source
  • H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different main groups of groups , or in a single subclass of , , e.g. forming hybrid circuits

41.

SENSOR RELIABILITY DETECTION AND POWER MANAGEMENT

      
Application Number 17933739
Status Pending
Filing Date 2022-09-20
First Publication Date 2024-03-21
Owner STMICROELECTRONICS S.R.L. (Italy)
Inventor
  • Rivolta, Stefano Paolo
  • Mura, Roberto

Abstract

The present disclosure is directed to a wearable electronic device, such as a watch, that includes one or more optical sensors. In order to determine accuracy of measurements by the optical sensors, the device detects whether or not the optical sensors are in physical contact with the user's skin. The device detects a level of contact between the user's skin and the optical sensors based on electrostatic charge variation measurements, and generates a contact reliability index (CRI) based on the level of contact. Operation of the optical sensors are adjusted based on the CRI.

IPC Classes  ?

  • A61B 5/1455 - Measuring characteristics of blood in vivo, e.g. gas concentration, pH-value using optical sensors, e.g. spectral photometrical oximeters
  • A61B 5/00 - Measuring for diagnostic purposes ; Identification of persons
  • A61B 5/0205 - Simultaneously evaluating both cardiovascular conditions and different types of body conditions, e.g. heart and respiratory condition
  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer

42.

DUAL-MODE CONTROL CIRCUIT FOR MICROELECTROMECHANICAL SYSTEM GYROSCOPES

      
Application Number 17933743
Status Pending
Filing Date 2022-09-20
First Publication Date 2024-03-21
Owner
  • STMICROELECTRONICS S.r.l. (Italy)
  • POLITECNICO DI MILANO (Italy)
Inventor
  • Valzasina, Carlo
  • Langfelder, Giacomo
  • Bestetti, Marco
  • Bonfanti, Andrea Giovanni

Abstract

The present disclosure is directed to a dual-mode control circuit for a microelectromechanical system (MEMS) gyroscope. A control circuit is coupled to a Lissajous frequency modulated (LFM) gyroscope to control amplitude of oscillation of a mass along two directions. The amplitude of oscillation is controlled by an automatic gain control (AGC) loop which allows the same amplitude of oscillation in both directions. An AGC is implemented with a combination of proportional control (P-type) and integral control (I-type) paths that maintain the correct Lissajous pattern of the oscillation of the mass. The AGC may include a dual-mode stage which is able to switch between a P-type control path and an I-type control path based on the operation of the LFM gyroscope. A fast start-up phase may be controlled by the P-type control path while the I-type path is pre-charged to be ready to use in a steady state condition.

IPC Classes  ?

  • G01C 19/5712 - Turn-sensitive devices using vibrating masses, e.g. vibratory angular rate sensors based on Coriolis forces using masses driven in reciprocating rotary motion about an axis the devices involving a micromechanical structure
  • H03F 3/45 - Differential amplifiers

43.

METHOD OF OPERATING HARD DISK DRIVES, CORRESPONDING CONTROL CIRCUIT, HARD DISK DRIVE AND PROCESSING DEVICE

      
Application Number 18446823
Status Pending
Filing Date 2023-08-09
First Publication Date 2024-03-21
Owner STMicroelectronics S.r.l. (Italy)
Inventor Galbiati, Ezio

Abstract

A back electromotive force (BEMF) of a spindle motor in a hard disk drive is rectified and exploited to drive a voice coil motor (VCM) in the hard disk drive to retract the heads of the hard disk drive to a park position. The VCM is driven in a discontinuous mode comprising an alternation of VCM on-times and VCM off-times. Rectifying the BEMF of the spindle motor is discontinued before the end of the VCM off-times, Toff with the spindle motor brought into a brake condition wherein the spindle motor is short-circuited and the spindle BEMF forces currents through the windings of the spindle motor. The spindle current is thus pre-charged and made ready to cope with a VCM current request at the next VCM on-time.

IPC Classes  ?

  • G11B 21/12 - Raising and lowering; Back-spacing or forward-spacing along track; Returning to starting position
  • G11B 21/10 - Track finding or aligning by moving the head

44.

NETWORK ARCHITECTURE, CORRESPONDING VEHICLE AND METHOD

      
Application Number 18457229
Status Pending
Filing Date 2023-08-28
First Publication Date 2024-03-21
Owner STMicroelectronics S.r.I. (Italy)
Inventor
  • Borgonovo, Giampiero
  • Re Fiorentin, Lorenzo

Abstract

A system, for use in providing media access control (MAC)/router/switch/gateway features in an on-board communication network in a vehicle, includes MAC controllers configured to provide a MAC port layer controlling exchange of information over a data link, virtual machine (VM) bridge blocks configured to provide a MAC frame layer interfacing with System-on-Chip VMs, a software (SW) Ethernet port configured to receive from a host programming/configuration information for the system, a local memory controller configured to facilitate the MAC controllers, the VM bridge blocks and the SW Ethernet port in cooperating with a local memory (LMEM), and queue handlers configured to provide queue management for the MAC controllers, the VM bridge blocks and the SW Ethernet port, during cooperation with the LMEM via the local memory controller.

IPC Classes  ?

  • G06F 9/455 - Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines

45.

METHOD FOR MODIFYING A TEST PROFILE IN AN INTEGRATED CIRCUIT CARD, CORRESPONDING INTEGRATED CIRCUIT CARD, TESTING METHOD AND APPARATUS

      
Application Number 18464811
Status Pending
Filing Date 2023-09-11
First Publication Date 2024-03-21
Owner STMICROELECTRONICS S.r.l. (Italy)
Inventor
  • Chichierchia, Maria
  • Alghiri, Mario

Abstract

An integrated circuit includes a memory and processing circuitry. The memory stores an Elementary File Test (EFT) file including a record storing information to update a target elementary file (TGF) in a file system of the EFT. The stored information includes a file path identifier identifying a position of the TGF in the file system of the EFT file, which is a concatenation of a parent file identifier followed by an identifier of the TGF, a first length indicator of a first type of data, the data of the first type, a second length indicator to indicate a length of a second type of data, and the data of the second type. The processing circuitry, in operation, identifies the TGF based on the file path identifier and updates the content of the TGF to include the first data and one or more instances of the second data.

IPC Classes  ?

  • G06F 8/70 - Software maintenance or management

46.

NON-VOLATILE MEMORY DEVICE AND CORRESPONDING METHOD OF OPERATION

      
Application Number 18464093
Status Pending
Filing Date 2023-09-08
First Publication Date 2024-03-21
Owner
  • STMICROELECTRONICS S.r.l. (Italy)
  • STMICROELECTRONICS (ALPS) SAS (France)
Inventor
  • Conte, Antonino
  • Maccarrone, Agatino Massimo
  • Tomaiuolo, Francesco
  • Jouanneau, Thomas
  • Russo, Vincenzo

Abstract

In a non-volatile memory device, a memory sector is provided. The memory sector includes a plurality of tiles arranged horizontally. Each tile includes a plurality of memory cells arranged in horizontal word lines and vertical bit lines. A pre-decoder is configured to receive a set of encoded address signals to produce pre-decoding signals. A central row decoder is arranged in line with the plurality of tiles, receives the pre-decoding signals and produces level-shifted pull-up and pull-down driving signals for driving the word lines. First buffer circuits are arranged on a first side of each tile. Each of the first buffer circuits is coupled to a respective word line, receives a level-shifted pull-up driving signal and a level-shifted pull-down driving signal, and selectively pulls up or pulls down the respective word line as a function of the values of the received signals.

IPC Classes  ?

  • G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
  • H03K 19/0185 - Coupling arrangements; Interface arrangements using field-effect transistors only
  • H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits

47.

SMDS INTEGRATION ON QFN BY 3D STACKED SOLUTION

      
Application Number 18508007
Status Pending
Filing Date 2023-11-13
First Publication Date 2024-03-21
Owner STMICROELECTRONICS S.r.l. (Italy)
Inventor
  • Somma, Cristina
  • Fontana, Fulvio Vittorio

Abstract

One or more embodiments are directed to quad flat no-lead (QFN) semiconductor packages, devices, and methods in which one or more electrical components are positioned between a die pad of a QFN leadframe and a semiconductor die. In one embodiment, a device includes a die pad, a lead that is spaced apart from the die pad, and at least one electrical component that has a first contact on the die pad and a second contact on the lead. A semiconductor die is positioned on the at least one electrical component and is spaced apart from the die pad by the at least one electrical component. The device further includes at least one conductive wire, or wire bond, that electrically couples the at least one lead to the semiconductor die.

IPC Classes  ?

48.

METHOD AND APPARATUS FOR MANAGING WAVEFORM DATA AND DELAYS IN A WAVEFORM GENERATOR

      
Application Number 17943643
Status Pending
Filing Date 2022-09-13
First Publication Date 2024-03-14
Owner STMicroelectronics S.r.l. (Italy)
Inventor
  • Passi, Stefano
  • Viti, Marco

Abstract

A signal decode circuit is coupled to a buffer for each signal channel. A memory includes a shared area configured to store waveform data sets, each waveform data set including a sequence of coded waveform values specifying waveform step states. The shared area further stores delay data sets, each delay data set including a digital delay value for each signal channel defining a delay profile. A signal pointer addresses the shared area to read one waveform data set from the memory with the sequence of coded waveform values being selectively loaded into one or more of the buffers. A delay pointer addresses the shared area to read one delay data set from the memory with the digital delay values used to control delayed actuation of the signal decode circuits to decode the sequence of coded waveform values from the buffers and generate waveform signals in accordance with the delay profile.

IPC Classes  ?

  • A61B 8/00 - Diagnosis using ultrasonic, sonic or infrasonic waves
  • A61B 8/08 - Detecting organic movements or changes, e.g. tumours, cysts, swellings
  • G01S 7/52 - RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES - Details of systems according to groups , , of systems according to group
  • G01S 15/89 - Sonar systems specially adapted for specific applications for mapping or imaging

49.

AUDIO AMPLIFICATION METHOD AND DEVICE

      
Application Number 18243754
Status Pending
Filing Date 2023-09-08
First Publication Date 2024-03-14
Owner STMicroelectronics S.r.l. (Italy)
Inventor
  • Botti, Edoardo
  • Stilgenbauer, Francesco
  • Malcovati, Piero
  • Bonizzoni, Edoardo
  • De Ferrari, Matteo

Abstract

Signal processing is applied to a digital audio input signal to provide an analog audio output signal using a switching converter circuit driven by a pulse-width-modulated (PWM) signal. The analog audio output signal is sensed to provide an analog feedback signal. The signal processing that is applied includes: converting the digital audio input signal to producing an analog replica; producing an analog error signal indicative of a difference between the analog replica of the digital input signal and the analog feedback signal; converting the analog error signal to produce a digital error signal; digitally filtering the digital error signal to produce a filtered digital error signal; and generating the PWM signal from the filtered digital error signal.

IPC Classes  ?

  • H03F 3/217 - Class D power amplifiers; Switching amplifiers
  • H03F 1/02 - Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
  • H03M 1/82 - Digital/analogue converters with intermediate conversion to time interval
  • H03M 3/00 - Conversion of analogue values to or from differential modulation

50.

CONTROLLER WITH PROTECTION AGAINST CROSS-CONDUCTION FOR AN ELECTRONIC CIRCUIT INCLUDING A PAIR OF SWITCHES AND RELATED CONTROL METHOD

      
Application Number 18451262
Status Pending
Filing Date 2023-08-17
First Publication Date 2024-03-14
Owner STMicroelectronics S.r.I. (Italy)
Inventor
  • Floriani, Ivan
  • Brigo, Elena

Abstract

A controller for an electronic circuit that includes a first and a second switch is provided. The controller includes an event detector stage that receives logic electrical signals and a pulse generator circuit, which is coupled to the event detector stage and generates a dead time signal based on edges of the logic electrical signals detected by the event detector stage. The dead time signal includes pulses delimited by an edge of a first type and by a subsequent edge of a second type. A combinatorial sampling circuit generates a first and a second sampled preliminary signal. An update stage updates the values of the first and the second control signals at each pulse of the dead time signal based on the first and the second sampled preliminary signals, subsequently to the edge of the first type or the second type of the pulse of the dead time signal.

IPC Classes  ?

  • H03K 3/037 - Bistable circuits
  • H03K 5/1534 - Transition or edge detectors
  • H03K 7/08 - Duration or width modulation
  • H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors

51.

CONTROL DEVICE FOR A SWITCHING VOLTAGE REGULATOR HAVING REDUCED AUDIO NOISE AND CONTROL METHOD

      
Application Number 18451256
Status Pending
Filing Date 2023-08-17
First Publication Date 2024-03-14
Owner STMicroelectronics S.r.l. (Italy)
Inventor
  • Floriani, Ivan
  • Castorina, Stefano
  • Altamura, Giulia
  • Moretti, Emanuele

Abstract

A control device for a switching voltage regulator having a switching circuit receives a set of measurement signals including a first measurement signal indicative of an output voltage of the switching voltage regulator. A burst-mode controller is configured to monitor the output voltage with respect to a first threshold and a second threshold higher than the first threshold, and to provide, in response, a burst signal. A driving-signal generation stage is configured to provide at least one switching control signal for the switching circuit based on the burst signal and the set of measurement signals. The driving-signal generation stage has a feedback module configured to provide a control signal based on the burst signal and an error signal indicative of a difference between the first measurement signal and a reference signal.

IPC Classes  ?

  • H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
  • H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion

52.

ELECTRONIC SYSTEM, INTEGRATED CIRCUIT, AND METHOD FOR GENERATING SEQUENTIAL SIGNALS

      
Application Number 18451272
Status Pending
Filing Date 2023-08-17
First Publication Date 2024-03-14
Owner STMicroelectronics S.r.l. (Italy)
Inventor
  • Coppa, Pietro Antonino
  • Lo Giudice, Gianbattista
  • Castaldo, Enrico
  • Conte, Antonino

Abstract

An electronic system is configured to generate a sequential logic signal. The electronic system includes a first ring oscillator including a first plurality of cascaded inverter stages. A combinational logic circuit is configured to generate the sequential logic signal by combining signals at the output terminals of at least two of the inverter stages of the first ring oscillator. The electronic system further includes a second ring oscillator including a second plurality of cascaded inverter stages. A bias current source is configured to supply the inverter stages of the second ring oscillator with a bias current, and a first voltage is generated at the inverter stages of the second ring oscillator. A voltage follower is configured to supply the inverter stages of the first ring oscillator with a second voltage corresponding to the first voltage generated at the inverter stages of the second ring oscillator.

IPC Classes  ?

  • H03K 3/03 - Astable circuits
  • H03K 3/011 - Modifications of generator to compensate for variations in physical values, e.g. voltage, temperature

53.

CALCULATION UNIT FOR MULTIPLICATION AND ACCUMULATION OPERATIONS

      
Application Number 18453158
Status Pending
Filing Date 2023-08-21
First Publication Date 2024-03-14
Owner STMICROELECTRONICS S.r.l. (Italy)
Inventor
  • Gandolfi, Luca
  • Garozzo, Ugo

Abstract

A device includes a multiplier, an accumulator and a floating point adder. The multiplier generates a product of a first factor having a sign bit and exponent bits and a second factor having a sign bit and exponent bits. The multiplier includes a sign multiplier and a subtractor. The sign multiplier generates a product of the sign bit of the first factor and the sign bit of the second factor. The subtractor subtracts the exponent bits of the first factor from the exponent bits of the second factor. The accumulator stores a current accumulation value. The floating-point adder is coupled to the multiplier and to the accumulator, and, in operation, the adder generates an updated accumulation value based a sum of the product and the current accumulation value, and stores the updated accumulation value in the accumulator. The first factor may be a weight of a neural network.

IPC Classes  ?

  • G06F 7/544 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices for evaluating functions by calculation

54.

LID ANGLE DETECTION

      
Application Number 18516453
Status Pending
Filing Date 2023-11-21
First Publication Date 2024-03-14
Owner STMICROELECTRONICS S.r.l. (Italy)
Inventor
  • Rizzardini, Federico
  • Bracco, Lorenzo

Abstract

The present disclosure is directed to a device and method for lid angle detection that is accurate even if the device is activated in an upright position. While the device is in a sleep state, first and second sensor units measure acceleration and angular velocity, and calculate orientations of respective lid components based on the acceleration and angular velocity measurements. Upon the device exiting the sleep state, a processor estimates the lid angle using the calculated orientations, sets the estimated lid angle as an initial lid angle, and updates the initial lid angle using, for example, two accelerometers; two accelerometers and two gyroscopes; two accelerometers and two magnetometers; or two accelerometers, two gyroscopes, and two magnetometers.

IPC Classes  ?

  • G06F 1/16 - Constructional details or arrangements
  • G01B 7/31 - Measuring arrangements characterised by the use of electric or magnetic techniques for testing the alignment of axes for testing the alignment of axes
  • G06F 1/3231 - Monitoring the presence, absence or movement of users
  • G06F 1/3246 - Power saving characterised by the action undertaken by software initiated power-off

55.

SEMICONDUCTOR PACKAGE OR DEVICE WITH SEALING LAYER

      
Application Number 17941886
Status Pending
Filing Date 2022-09-09
First Publication Date 2024-03-14
Owner STMICROELECTRONICS S.r.l. (Italy)
Inventor
  • Milanesi, Francesca
  • Colpani, Paolo

Abstract

The present disclosure is directed to embodiments of a conductive structure on a conductive layer, which may be a conductive damascene layer of a semiconductor device or package. The conductive damascene layer may be within a substrate of the semiconductor device or package. A crevice is present between one or more sidewalls of the conductive structure and one or more sidewalls of one or more insulating layers on the substrate and extends to a surface of the conductive layer. A sealing layer is formed in the crevice that seals the conductive layer from moisture and contaminants external to the semiconductor device or package that may enter the crevice. In other words, the sealing layer stops the moisture and contaminants from reaching the conductive layer such that the conductive layer does not corrode due to exposure to the moisture and contaminants.

IPC Classes  ?

  • H01L 23/498 - Leads on insulating substrates
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device

56.

SENSORIZED EARPHONE DEVICE FOR OUT-OF-EAR MEASUREMENTS

      
Application Number 18243361
Status Pending
Filing Date 2023-09-07
First Publication Date 2024-03-14
Owner STMicroelectronics S.r.l. (Italy)
Inventor
  • Alessi, Enrico Rosario
  • Duqi, Enri
  • Passaniti, Fabio

Abstract

An earphone device has a casing having a measurement portion dedicated to acquisition of at least one measurement quantity with the earphone device arranged outside an ear of a subject. The earphone device is provided with at least one sensor, operatively coupled to the measurement portion within the casing for acquiring signals indicative of the measurement quantity, and a processing module that processes the signals acquired by the sensor so as to provide a processed output signal for monitoring the measurement quantity, as a function of the acquired signals. Electrical-connection elements define electrical paths within the casing in electrical connection with the sensor.

IPC Classes  ?

  • A61B 5/0205 - Simultaneously evaluating both cardiovascular conditions and different types of body conditions, e.g. heart and respiratory condition
  • A61B 5/00 - Measuring for diagnostic purposes ; Identification of persons
  • A61B 5/01 - Measuring temperature of body parts

57.

METHOD OF MANUFACTURING OHMIC CONTACTS OF AN ELECTRONIC DEVICE, WITH THERMAL BUDGET OPTIMIZATION

      
Application Number 18363349
Status Pending
Filing Date 2023-08-01
First Publication Date 2024-03-07
Owner STMICROELECTRONICS S.r.l. (Italy)
Inventor
  • Saggio, Mario Giuseppe
  • Camalleri, Cateno Marco
  • Bellocchi, Gabriele
  • Rascuna', Simone

Abstract

Method of manufacturing an electronic device, comprising forming an ohmic contact at an implanted region of a semiconductor body. Forming the ohmic contact provides for performing a high-temperature thermal process for allowing a reaction between a metal material and the material of the semiconductor body, for forming a silicide of the metal material. The step of forming the ohmic contact is performed prior to a step of forming one or more electrical structures which include materials that may be damaged by the high temperature of the thermal process of forming the silicide.

IPC Classes  ?

  • H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
  • H01L 29/40 - Electrodes
  • H01L 29/66 - Types of semiconductor device

58.

SIC-BASED ELECTRONIC DEVICE WITH IMPROVED GATE DIELECTRIC AND MANUFACTURING METHOD THEREOF, DIODE

      
Application Number 18364180
Status Pending
Filing Date 2023-08-02
First Publication Date 2024-03-07
Owner STMicroelectronics S.r.l. (Italy)
Inventor
  • Fiorenza, Patrick
  • Roccaforte, Fabrizio
  • Zanetti, Edoardo
  • Saggio, Mario Giuseppe

Abstract

Electronic device comprising: a semiconductor body, in particular of Silicon Carbide, SiC, having a first and a second face, opposite to each other along a first direction; and an electrical terminal at the first face, insulated from the semiconductor body by an electrical insulation region. The electrical insulation region is a multilayer comprising: a first insulating layer, of a Silicon Oxide, in contact with the semiconductor body; a second insulating layer on the first insulating layer, of a Hafnium Oxide; and a third insulating layer on the second insulating layer, of an Aluminum Oxide.

IPC Classes  ?

  • H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
  • H01L 29/51 - Insulating materials associated therewith
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/872 - Schottky diodes

59.

MEMS ULTRASONIC TRANSDUCER DEVICE AND MANUFACTURING PROCESS THEREOF

      
Application Number 18455540
Status Pending
Filing Date 2023-08-24
First Publication Date 2024-03-07
Owner STMICROELECTRONICS S.r.l. (Italy)
Inventor Foncellino, Francesco

Abstract

MEMS ultrasonic transducer, MUT, device, comprising a semiconductor body with a first and a second main face, including: a modulation cavity extending into the semiconductor body from the second main face; a membrane body suspended on the modulation cavity and comprising a transduction membrane body and a modulation membrane body; a piezoelectric modulation structure on the modulation membrane body; a transduction cavity extending into the membrane body, the transduction membrane body being suspended on the transduction cavity; and a piezoelectric transduction structure on the transduction membrane body. The modulation membrane body has a first thickness and the transduction membrane body has a second thickness smaller than the first thickness. In use, the modulation membrane vibrates at a first frequency and the transduction membrane vibrates at a second frequency higher than the first frequency, to emit and/or receive acoustic waves at a frequency dependent on the first and the second frequencies.

IPC Classes  ?

  • B06B 1/02 - Processes or apparatus for generating mechanical vibrations of infrasonic, sonic or ultrasonic frequency making use of electrical energy
  • G01S 7/534 - RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES - Details of systems according to groups , , of systems according to group - Details of non-pulse systems

60.

WEARABLE AND PORTABLE SYSTEM AND METHOD FOR MEASURING CARDIAC PARAMETERS FOR DETECTING CARDIOPATHIES

      
Application Number 18456227
Status Pending
Filing Date 2023-08-25
First Publication Date 2024-03-07
Owner STMICROELECTRONICS S.r.l. (Italy)
Inventor
  • Alessi, Enrico Rosario
  • Passaniti, Fabio
  • Di Marco, Oriana Rita Antonia

Abstract

A system for measuring cardiac parameters uses a movements sensor to generate a seismocardiographic signal and a cardiac parameters calculation unit. The cardiac parameters calculation unit provides for generating an envelope signal correlated to the seismocardiographic signal; identifies, in the envelope signal, signal segments having a repetitive pattern; identifies, among the signal segments, pairs of successive peaks such that a first peak of each pair of successive peaks is a systolic peak and a second peak of each pair of successive peaks is a diastolic peak; and calculates a systolic period and a diastolic period for each pair of successive peaks.

IPC Classes  ?

  • A61B 5/11 - Measuring movement of the entire body or parts thereof, e.g. head or hand tremor or mobility of a limb
  • A61B 5/00 - Measuring for diagnostic purposes ; Identification of persons
  • A61B 5/349 - Detecting specific parameters of the electrocardiograph cycle

61.

Time division multiplexing hub

      
Application Number 17898335
Grant Number 11949500
Status In Force
Filing Date 2022-08-29
First Publication Date 2024-02-29
Grant Date 2024-04-02
Owner STMicroelectronics S.r.l. (Italy)
Inventor
  • Quartiroli, Matteo
  • Rizzo Piazza Roncoroni, Alessandra Maria

Abstract

An integrated circuit includes a control circuit, a primary sensor device coupled to the control circuit, and a plurality of groups of secondary sensor devices coupled to the primary sensor device. The primary sensor device receives a master clock signal from the control device and outputs, to each group of secondary sensor devices, a respective secondary clock signal with a frequency lower than the primary clock signal. The primary sensor device generates primary sensor data. The primary sensor device receives secondary sensor data from each group of secondary sensor devices. The primary sensor device combines the primary sensor data and all of the secondary sensor data into a sensor data stream with a time division-multiplexing scheme and outputs the sensor data stream to the control circuit.

IPC Classes  ?

  • H04W 4/02 - Services making use of location information
  • H04J 3/06 - Synchronising arrangements

62.

SIC-BASED ELECTRONIC DEVICE WITH FUSE ELEMENT FOR SHORT-CIRCUITS PROTECTION, AND MANUFACTURING METHOD THEREOF

      
Application Number 18450789
Status Pending
Filing Date 2023-08-16
First Publication Date 2024-02-29
Owner STMICROELECTRONICS S.r.l. (Italy)
Inventor
  • Scalia, Laura Letizia
  • Camalleri, Cateno Marco
  • Zanetti, Edoardo
  • Russo, Alfio

Abstract

SiC-based MOSFET electronic device comprising: a solid body; a gate terminal, extending into the solid body; a conductive path, extending at a first side of the solid body, configured to be electrically couplable to a generator of a biasing voltage; a protection element of a solid-state material, coupled to the gate terminal and to the conductive path, the protection element forming an electronic connection between the gate terminal and the conductive path, and being configured to go from the solid state to a melted or gaseous state, interrupting the electrical connection, in response to a leakage current through the protection element greater than a critical threshold; a buried cavity in the solid body accommodating, at least in part, the protection element.

IPC Classes  ?

  • H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
  • H01L 23/29 - Encapsulation, e.g. encapsulating layers, coatings characterised by the material
  • H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

63.

MULTI-LEVEL PULSER CIRCUIT AND METHOD OF OPERATING A MULTI-LEVEL PULSER CIRCUIT

      
Application Number 18466562
Status Pending
Filing Date 2023-09-13
First Publication Date 2024-02-29
Owner STMICROELECTRONICS S.R.L. (Italy)
Inventor Viti, Marco

Abstract

A multi-level pulser circuit comprises a set of first input pins for receiving respective positive voltage signals at different voltage levels, a set of second input pins for receiving respective negative voltage signals at different voltage levels, and a reference input pin configured to receive a reference voltage signal intermediate the positive voltage signals and the negative voltage signals. The circuit comprises an output pin configured to supply a pulsed output signal. The circuit further comprises control circuitry configured to selectively couple the output pin to one of the first input pins, the second input pins and the reference input pin to generate the pulsed output signal at the output pin. The control circuitry is further configured to selectively couple at least one of the second input pins and the reference input pin to the output pin during falling transitions of the pulsed output signal between two positive voltage levels, and selectively couple at least one of the first input pins and the reference input pin to the output pin during rising transitions of the pulsed output signal between two negative voltage levels.

IPC Classes  ?

  • H03K 3/027 - Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
  • H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits

64.

METHOD FOR MOTION ESTIMATION IN A VEHICLE, CORRESPONDING DEVICE AND COMPUTER PROGRAM PRODUCT

      
Application Number 18496124
Status Pending
Filing Date 2023-10-27
First Publication Date 2024-02-29
Owner
  • STMICROELECTRONICS S.r.l. (Italy)
  • STMICROELECTRONICS, INC. (USA)
  • STMicroelectronics (Grand Ouest) SAS (France)
Inventor
  • Palella, Nicola Matteo
  • Colombo, Leonardo
  • Donadel, Andrea
  • Mura, Roberto
  • Jain, Mahaveer
  • Philippe, Joelle

Abstract

A system includes inertial sensors and a GPS. The system generates a first estimated vehicle velocity based on motion data and positioning data, generates a second estimated vehicle velocity based on the processed motion data and the first estimated vehicle velocity, and generates fused datasets indicative of position, velocity and attitude of a vehicle based on the processed motion data, the positioning data and the second estimated vehicle velocity. The generating the second estimated vehicle velocity includes: filtering the motion data, transforming the filtered motion data in a frequency domain based on the first estimated vehicle velocity, generating spectral power density signals, generating an estimated wheel angular frequency and an estimated wheel size based on the spectral power density signals, and generating the second estimated vehicle velocity as a function of the estimated wheel angular frequency and the estimated wheel size.

IPC Classes  ?

  • B60W 40/101 - Side slip angle of tyre
  • B60W 40/11 - Pitch movement
  • B60W 40/112 - Roll movement
  • B60W 40/114 - Yaw movement
  • G01S 19/47 - Determining position by combining measurements of signals from the satellite radio beacon positioning system with a supplementary measurement the supplementary measurement being an inertial measurement, e.g. tightly coupled inertial

65.

CONTROLLER FOR A BUCK-BOOST SWITCHING CONVERTER WITH OVERCURRENT AND NULL-CURRENT DETECTION AND METHOD FOR CONTROLLING A BUCK-BOOST SWITCHING CONVERTER

      
Application Number 18345525
Status Pending
Filing Date 2023-06-30
First Publication Date 2024-02-29
Owner STMicroelectronics S.r.l. (Italy)
Inventor
  • Castorina, Stefano
  • Brigo, Elena

Abstract

A controller for a buck-boost switching converter, which includes an inductor and a shunt resistor and is coupled to a load which draws a load current, includes a control circuit which performs charge and discharge cycles of the inductor. A first comparator stage generates a first signal which is indicative of a direction of the resistor current during the charge and discharge cycles. A low-pass filtering circuit generates a filtered electrical quantity based on a voltage on the shunt resistor during the charge and discharge cycles. A second comparator stage generates a second signal indicative of a comparison between the filtered electrical quantity and a reference electrical quantity. A detection stage detects the occurrence of an overcurrent in the load based on the second signal.

IPC Classes  ?

  • H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
  • G01R 19/165 - Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
  • H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion

66.

CURRENT SENSING CIRCUIT

      
Application Number 18493494
Status Pending
Filing Date 2023-10-24
First Publication Date 2024-02-22
Owner STMicroelectronics S.r.I (Italy)
Inventor Angelini, Paolo

Abstract

In accordance with an embodiment, a method of measuring a load current flowing through a current measurement resistor coupled between a source node and a load node includes: measuring a first voltage across a replica resistor when a first end of the replica resistor is coupled to the source node and a second end of the replica resistor is coupled to a reference current source; measuring a second voltage across the replica resistor when the second end of the replica resistor is coupled to the source node and the first end of the replica resistor is coupled to the reference current source; measure a third voltage across the current sensing resistor; and calculating a corrected current measurement of the load current based on the measured first voltage, the measured second voltage and the measured third voltage.

IPC Classes  ?

  • G01R 19/25 - Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques
  • G01R 15/14 - Adaptations providing voltage or current isolation, e.g. for high-voltage or high-current networks

67.

TRANSDUCER WITH IMPROVED PIEZOELECTRIC ARRANGEMENT, MEMS DEVICE COMPRISING THE TRANSDUCER, AND METHODS FOR MANUFACTURING THE TRANSDUCER

      
Application Number 18498737
Status Pending
Filing Date 2023-10-31
First Publication Date 2024-02-22
Owner STMICROELECTRONICS S.r.l. (Italy)
Inventor
  • Seghizzi, Luca
  • Vercesi, Federico
  • Pedrini, Claudia

Abstract

A transducer includes a supporting body and a suspended structure mechanically coupled to the supporting body. The suspended structure has a first and a second surface opposite to one another along an axis, and is configured to oscillate in an oscillation direction having at least one component parallel to the axis. A first piezoelectric transducer is disposed on the first surface of the suspended structure, and a second piezoelectric transducer is disposed on the second surface of the suspended structure.

IPC Classes  ?

  • H10N 30/50 - Piezoelectric or electrostrictive devices having a stacked or multilayer structure
  • H10N 30/03 - Assembling devices that include piezoelectric or electrostrictive parts
  • H10N 30/09 - Forming piezoelectric or electrostrictive materials
  • H10N 30/30 - Piezoelectric or electrostrictive devices with mechanical input and electrical output, e.g. functioning as generators or sensors

68.

THRESHOLD VOLTAGE GENERATOR CIRCUIT AND CORRESPONDING RECEIVER DEVICE

      
Application Number 18359465
Status Pending
Filing Date 2023-07-26
First Publication Date 2024-02-15
Owner
  • STMicroelectronics S.r.l. (Italy)
  • ALMA MATER STUDIORUM - UNIVERSITA' DI BOLOGNA (Italy)
Inventor
  • D'Addato, Matteo
  • Elgani, Alessia Maria
  • Perilli, Luca
  • Franchi Scarselli, Eleonora
  • Gnudi, Antonio
  • Canegallo, Roberto Antonio
  • Ricotti, Giulio

Abstract

A circuit includes a clock input node, a first signal input node configured to receive a first modulated signal switching between a first DC voltage and a second DC voltage, a bias circuit, a first output node, a first capacitor, a second capacitor, and switching circuitry coupled to the first capacitor and the second capacitor. Control circuitry is configured to initially set the switching circuitry in a first configuration in response to the first modulated signal having the second DC voltage, thereby charging the first capacitor to the second DC voltage and charging the second capacitor to the first DC voltage, and subsequently set the switching circuitry in a second configuration in response to an edge detected in the clock signal, thereby producing the first threshold voltage at the first output node after charge redistribution taking place between the first and second capacitors.

IPC Classes  ?

  • H03K 3/0233 - Bistable circuits
  • H04L 25/06 - Dc level restoring means; Bias distortion correction
  • H04L 27/06 - Demodulator circuits; Receiver circuits
  • H03L 7/099 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop

69.

MICROELECTROMECHANICAL BUTTON DEVICE AND CORRESPONDING WATERPROOF USER INTERFACE ELEMENT

      
Application Number 18363599
Status Pending
Filing Date 2023-08-01
First Publication Date 2024-02-15
Owner STMICROELECTRONICS S.r.l. (Italy)
Inventor
  • Vercesi, Federico
  • Gattere, Gabriele
  • Allegato, Giorgio
  • Azpeitia Urquia, Mikel
  • Danei, Alessandro

Abstract

A microelectromechanical button device is provided with a detection structure having: a substrate of semiconductor material with a front surface and a rear surface; a buried electrode arranged on the substrate; a mobile electrode, arranged in a structural layer overlying the substrate and elastically suspended above the buried electrode at a separation distance so as to form a detection capacitor; and a cap coupled over the structural layer and having a first main surface facing the structural layer and a second main surface that is designed to be mechanically coupled to a deformable portion of a case of an electronic apparatus of a portable or wearable type. The cap has, on its first main surface, an actuation portion arranged over the mobile electrode and configured to cause, in the presence of a pressure applied on the second main surface, a deflection of the mobile electrode and its approach to the buried electrode, with a consequent capacitive variation of the detection capacitor, which is indicative of an actuation of the microelectromechanical button device.

IPC Classes  ?

  • B81B 7/00 - Microstructural systems
  • B81B 7/02 - Microstructural systems containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems (MEMS)
  • H03K 17/975 - Switches controlled by moving an element forming part of the switch using a capacitive movable element

70.

CONTROL CIRCUIT FOR A SWITCHING STAGE OF AN ELECTRONIC CONVERTER AND CORRESPONDING CONVERTER DEVICE

      
Application Number 18350380
Status Pending
Filing Date 2023-07-11
First Publication Date 2024-02-08
Owner STMicroelectronics S.r.I. (Italy)
Inventor Borghese, Marco

Abstract

A control circuit for a switching stage of an electronic converter includes a PWM signal generator that generates a PWM signal to drive the switching stage of the electronic converter. A loop comparator circuit receives the regulated output voltage of the electronic converter and receives a sum signal from an adder circuit. The loop comparator circuit generates a comparison signal having a first or second logic value in response to the regulated output voltage reaching the sum signal or failing to reach the sum signal. The adder circuit generates the sum signal as a sum of a reference voltage and a programmable offset voltage that is generated by a programmable voltage generator based on a digital word signal. A feedback circuit is coupled to the loop comparator circuit and the PWM signal generator, and provides the digital word signal to the programmable voltage generator.

IPC Classes  ?

  • H03K 3/03 - Astable circuits
  • H02M 3/157 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
  • H03K 7/08 - Duration or width modulation
  • H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion

71.

SYNCHRONIZING DIGITAL DEVICE

      
Application Number 18352581
Status Pending
Filing Date 2023-07-14
First Publication Date 2024-02-08
Owner STMICROELECTRONICS S.r.l. (Italy)
Inventor
  • Quartiroli, Matteo
  • Mecchia, Alessandro
  • Pesenti, Paolo

Abstract

A device includes a local oscillator, an all-digital phase-locked loop, a digital signal generator, sampling circuitry, and an interface. The local oscillator generates a local clock signal. The all-digital phase locked loop generates a sampling control signal. The ADPLL includes a phase-error detector, a digital filter and a sigma-delta modulator. The phase detector generates a phase error signal based on a loop clock signal and a received reference signal. The digital filter generates a signal indicative of a frequency ratio between a frequency of the reference clock signal and the local clock frequency based on the phase error signal. The sigma-delta modulator generates a modulated signal based on the signal indicative of the frequency ratio. The sampling control signal is based on the modulated signal. The sampling circuitry samples digital signals generated by the digital signal generator at a sampling frequency, which is a function of the sampling control signal.

IPC Classes  ?

  • H03L 7/081 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop provided with an additional controlled phase shifter
  • H03L 7/099 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop

72.

MEMS DEVICE WITH AN IMPROVED CAP AND RELATED MANUFACTURING PROCESS

      
Application Number 18359754
Status Pending
Filing Date 2023-07-26
First Publication Date 2024-02-08
Owner STMICROELECTRONICS S.r.l. (Italy)
Inventor
  • Allegato, Giorgio
  • Nicoli, Silvia
  • Alessandri, Anna
  • Garavaglia, Matteo

Abstract

Electronic device including: a MEMS sensor device including a functional structure which transduces a chemical or physical quantity into a corresponding electrical quantity; a cap including a semiconductive substrate; and a bonding dielectric region, which mechanically couples the cap to the MEMS sensor device. The cap further includes a conductive region, which extends between the semiconductive substrate and the MEMS sensor device and includes: a first portion, which is arranged laterally with respect to the semiconductive substrate and is exposed, so as to be electrically coupleable to a terminal at a reference potential by a corresponding wire bonding; and a second portion, which contacts the semiconductive substrate.

IPC Classes  ?

  • B81B 7/00 - Microstructural systems
  • B81C 1/00 - Manufacture or treatment of devices or systems in or on a substrate

73.

ENERGY RECOVERY DRIVER FOR PZT ACTUATORS

      
Application Number 17879066
Status Pending
Filing Date 2022-08-02
First Publication Date 2024-02-08
Owner
  • STMicroelectronics S.r.l. (Italy)
  • Politecnico Di Milano (Italy)
Inventor
  • Zamprogno, Marco
  • Furceri, Raffaele Enrico
  • Gianollo, Matteo
  • Langfelder, Giacomo

Abstract

A differential piezoelectric actuator-system includes an inductor and driver-circuit having switches for transferring energy between first and second actuators and the inductor, and between a voltage-supply node and the inductor. Control circuitry determines whether a next phase in which to operate the driver-circuit is a first charging-phase or a first recovery-phase. The first charging-phase includes operating the switches in: a first sub-phase to transfer energy from the first actuator to the inductor; a second sub-phase to transfer energy from the voltage supply node to the inductor; and a third sub-phase to transfer energy from the inductor to the second actuator. The first recovery-phase includes operating the switches in: a first sub-phase to transfer energy from the first actuator to the inductor; a second sub-phase to transfer energy from the inductor to the second actuator; and a third sub-phase to transfer energy from the inductor to the voltage supply node.

IPC Classes  ?

  • H01L 41/04 - SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR - Details thereof - Details of piezo-electric or electrostrictive elements
  • H02N 2/06 - Drive circuits; Control arrangements
  • H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load

74.

ELECTRONIC DEVICE INCLUDING BAG DETECTION

      
Application Number 18484978
Status Pending
Filing Date 2023-10-11
First Publication Date 2024-02-08
Owner STMICROELECTRONICS S.r.l. (Italy)
Inventor
  • Rivolta, Stefano Paolo
  • Rizzardini, Federico
  • Bracco, Lorenzo
  • Mura, Roberto

Abstract

The present disclosure is directed to a device configured to detect whether the device is in a bag or outside of the bag. The device determines whether the device is in or outside of the bag based on distance measurements generated by at least one proximity sensor and motion measurements generated by at least one motion sensor. By using both distance measurements and motion measurements, the device is able to detect whether the device is in the bag or outside of the bag with high accuracy and robustness.

IPC Classes  ?

  • G01C 19/60 - Electronic or nuclear magnetic resonance gyrometers
  • G01B 7/00 - Measuring arrangements characterised by the use of electric or magnetic techniques
  • H03K 17/945 - Proximity switches

75.

MICROELECTROMECHANICAL SENSOR DEVICE WITH ACTIVE OFFSET COMPENSATION

      
Application Number 18364847
Status Pending
Filing Date 2023-08-03
First Publication Date 2024-02-08
Owner STMICROELECTRONICS S.r.l. (Italy)
Inventor
  • Gattere, Gabriele
  • Darmanin, Jean Marie
  • Rizzini, Francesco

Abstract

A microelectromechanical sensor device having a sensing structure with: a substrate; an inertial mass, suspended above the substrate and elastically coupled to a rotor anchoring structure by elastic coupling elements, to perform at least one inertial movement due to a quantity to be sensed; first sensing electrodes, integrally coupled to the inertial mass to be movable due to the inertial movement; and second sensing electrodes, fixed with respect to the quantity to be sensed, facing and capacitively coupled to the first sensing electrodes to form sensing capacitances having a value that is indicative of the quantity to be sensed. The second sensing electrodes are arranged in a suspended manner above the substrate and a compensation structure is configured to move the second sensing electrodes with respect to the first sensing electrodes and vary a facing distance thereof, in the absence of the quantity to be sensed, in order to compensate for a native offset of the sensing structure.

IPC Classes  ?

  • G01P 15/125 - Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces with conversion into electric or magnetic values by capacitive pick-up

76.

TAGGED MEMORY OPERATED AT LOWER VMIN IN ERROR TOLERANT SYSTEM

      
Application Number 18488581
Status Pending
Filing Date 2023-10-17
First Publication Date 2024-02-08
Owner
  • STMICROELECTRONICS S.r.l. (Italy)
  • STMicroelectronics International N.V. (Switzerland)
Inventor
  • Chawla, Nitin
  • Desoli, Giuseppe
  • Grover, Anuj
  • Boesch, Thomas
  • Singh, Surinder Pal
  • Ayodhyawasi, Manuj

Abstract

A memory array arranged as a plurality of memory cells. The memory cells are configured to operate at a determined voltage. A memory management circuitry coupled to the plurality of memory cells tags a first set of the plurality of memory cells as low-voltage cells and tags a second set of the plurality of memory cells as high-voltage cells. A power source provides a low voltage to the first set of memory cells and provides a high voltage to the second set of memory cells based on the tags.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers
  • G06N 3/08 - Learning methods

77.

ENERGY RECOVERY DRIVER FOR PZT ACTUATORS

      
Application Number 18222180
Status Pending
Filing Date 2023-07-14
First Publication Date 2024-02-08
Owner
  • STMicroelectronics S.r.l. (Italy)
  • Politecnico Di Milano (Italy)
Inventor
  • Zamprogno, Marco
  • Furceri, Raffaele Enrico
  • Gianollo, Matteo
  • Langfelder, Giacomo

Abstract

A differential piezoelectric actuator-system includes an inductor and driver-circuit having switches for transferring energy between first and second actuators and the inductor, and between a voltage-supply node and the inductor. Control circuitry determines whether a next phase in which to operate the driver-circuit is a first charging-phase or a first recovery-phase. The first charging-phase includes operating the switches in: a first sub-phase to transfer energy from the first actuator to the inductor; a second sub-phase to transfer energy from the voltage supply node to the inductor; and a third sub-phase to transfer energy from the inductor to the second actuator. The first recovery-phase includes operating the switches in: a first sub-phase to transfer energy from the first actuator to the inductor; a second sub-phase to transfer energy from the inductor to the voltage supply node; and a third sub-phase to transfer energy from the inductor to the second actuator.

IPC Classes  ?

  • H10N 30/80 - Constructional details
  • H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
  • H02J 7/00 - Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
  • H02N 2/06 - Drive circuits; Control arrangements

78.

PROCESS FOR MANUFACTURING AN OPTICAL MICROELECTROMECHANICAL DEVICE HAVING A TILTABLE STRUCTURE WITH AN ANTIREFLECTIVE SURFACE

      
Application Number 18244479
Status Pending
Filing Date 2023-09-11
First Publication Date 2024-02-08
Owner STMicroelectronics S.r.l. (Italy)
Inventor
  • Seghizzi, Luca
  • Boni, Nicolo'
  • Oggioni, Laura
  • Carminati, Roberto
  • Carminati, Marta

Abstract

A method for manufacturing an optical microelectromechanical device, includes forming, in a first wafer of semiconductor material having a first surface and a second surface, a suspended mirror structure, a fixed structure surrounding the suspended mirror structure, elastic supporting elements extending between the fixed structure and the suspended mirror structure, and an actuation structure coupled to the suspended mirror structure. The method continues with forming, in a second wafer, a chamber delimited by a bottom wall having a through opening, and bonding the second wafer to the first surface of the first wafer and bonding a third wafer to the second surface of the first wafer so that the chamber overlies the actuation structure, and the through opening is aligned to the suspended mirror structure, thus forming a device composite wafer. The device composite wafer is diced to form an optical microelectromechanical device.

IPC Classes  ?

  • B81B 3/00 - Devices comprising flexible or deformable elements, e.g. comprising elastic tongues or membranes
  • B81C 1/00 - Manufacture or treatment of devices or systems in or on a substrate

79.

MICROPRISM AND MICROLENS ARRAY FOR USE IN LIDAR SYSTEM

      
Application Number 17882173
Status Pending
Filing Date 2022-08-05
First Publication Date 2024-02-08
Owner STMicroelectronics S.r.l. (Italy)
Inventor Fincato, Antonio

Abstract

A LIDAR optical unit includes a photonic-integrated-circuit (PIC) affixed to a carrier. The PIC includes an input coupler and an array of output couplers, with a switchable optical network connecting the input coupler to different selected ones of the array of output couplers. A laser source is mounted to the PIC adjacent the input coupler such that laser light generated by the laser source is injected into the input coupler. An optical stack is mounted to the PIC adjacent the array of output couplers to receive laser light extracted from the switchable optical network by the array of output couplers. The optical stack includes an array of microlenses positioned so that a bottom surface thereof is mounted to the PIC, and an array of microprisms is stacked on the array of microlenses so that a bottom surface thereof is mounted to a top surface of the array of microlenses.

IPC Classes  ?

  • G01S 7/481 - Constructional features, e.g. arrangements of optical elements
  • G02B 6/42 - Coupling light guides with opto-electronic elements
  • G02B 6/12 - Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
  • G01S 7/497 - Means for monitoring or calibrating

80.

DEVICE PICK-UP DETECTION

      
Application Number 17882206
Status Pending
Filing Date 2022-08-05
First Publication Date 2024-02-08
Owner STMICROELECTRONICS S.R.L. (Italy)
Inventor
  • Rivolta, Stefano Paolo
  • Mura, Roberto

Abstract

The present disclosure is directed to pick-up state detection for an electronic device, such as a laptop. In a pick-up state, the device is picked or lifted up from a surface, such as a table. A power state of the device is adjusted in response to detecting the pick-up state. For example, the device is in a hibernate state while set on the table, and is switched to a working state in response to detecting the pick-up state.

IPC Classes  ?

  • G06F 3/0346 - Pointing devices displaced or positioned by the user; Accessories therefor with detection of the device orientation or free movement in a 3D space, e.g. 3D mice, 6-DOF [six degrees of freedom] pointers using gyroscopes, accelerometers or tilt-sensors
  • G06F 1/3206 - Monitoring of events, devices or parameters that trigger a change in power modality
  • G01P 15/18 - Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration in two or more dimensions
  • G06F 1/16 - Constructional details or arrangements

81.

DEVICE PICK-UP DETECTION

      
Application Number 18352153
Status Pending
Filing Date 2023-07-13
First Publication Date 2024-02-08
Owner STMICROELECTRONICS S.R.L. (Italy)
Inventor Rivolta, Stefano Paolo

Abstract

The present disclosure is directed to pick-up state detection for an electronic device, such as a laptop. In a pick-up state, the device is picked or lifted up from a surface, such as a table. A power state of the device is adjusted in response to detecting the pick-up state. For example, the device is in a hibernate state while set on the table, and is switched to a working state in response to detecting the pick-up state.

IPC Classes  ?

  • G01P 15/18 - Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration in two or more dimensions
  • G06F 1/3206 - Monitoring of events, devices or parameters that trigger a change in power modality
  • G06F 1/16 - Constructional details or arrangements

82.

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES AND CORRESPONDING SEMICONDUCTOR DEVICE

      
Application Number 18223838
Status Pending
Filing Date 2023-07-19
First Publication Date 2024-02-01
Owner STMicroelectronics S.r.l. (Italy)
Inventor
  • Halicki, Damian
  • Derai, Michele

Abstract

Semiconductor devices of the type currently referred to as a System in a Package (SiP) and having embedded therein a transformer are produced by embedding at least one semiconductor chip in an insulating encapsulation at a first portion thereof. Over a second portion thereof at least partly non-overlapping with the first portion, a stacked structure is formed including multiple layers of electrically insulating material as well as respective patterns of electrically conductive material. The respective patterns of electrically conductive material have: a planar coil geometry for providing electrically conductive coils such as the windings of a transformer and a geometrical distribution providing electrically conductive connections to one or more semiconductor chips.

IPC Classes  ?

  • H01L 23/498 - Leads on insulating substrates
  • H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings

83.

METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES AND CORRESPONDING SEMICONDUCTOR PRODUCTS

      
Application Number 18224805
Status Pending
Filing Date 2023-07-21
First Publication Date 2024-02-01
Owner STMicroelectronics S.r.l. (Italy)
Inventor
  • Cecchetto, Luca
  • Merlini, Alessandra Piera
  • Addesa, Gabriella

Abstract

A semiconductor chip has a top metal layer with a passivation over an outer surface and including a first region and a second region. The passivation is fully removed from the first region and a contact layer for electrical wafer sorting probes is formed over the first region having the passivation fully removed therefrom. The passivation is initially only partly removed from the second region to protect the top met layer. Later, a remaining portion of the passivation is fully removed at the second region. Then, top metal layer at the second region provides a growth region for growing electrically conductive material over the second region.

IPC Classes  ?

  • H01L 21/66 - Testing or measuring during manufacture or treatment
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device

84.

LOW-DROPOUT VOLTAGE REGULATOR CIRCUIT AND CORRESPONDING METHOD OF OPERATION

      
Application Number 18224897
Status Pending
Filing Date 2023-07-21
First Publication Date 2024-02-01
Owner STMicroelectronics S.r.l. (Italy)
Inventor
  • Ferlito, Umberto
  • Vaiana, Michele
  • Bruno, Giuseppe
  • Grasso, Alfio Dario

Abstract

A low-drop out voltage regulator includes a pass element arranged between an input terminal and an output terminal, a feedback network configured to produce a feedback voltage derived from an output voltage, and an error amplifier configured to drive the pass element as a function of a difference between the feedback voltage and a reference voltage. An output transistor coupled in series with the pass element is controlled by a mode selection circuit. In response to assertion of a mode selection signal, the mode selection circuit turns on the output transistor to sink a current with a controlled magnitude from the output node. In response to de-assertion of the mode selection signal, the mode selection circuit sinks a current with a controlled magnitude from a control terminal of the output transistor to turn off the output transistor at a controlled rate.

IPC Classes  ?

  • G05F 1/565 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
  • G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit

85.

METHOD OF OPERATING HARD DISK DRIVES AND CORRESPONDING CONTROL CIRCUIT

      
Application Number 18354797
Status Pending
Filing Date 2023-07-19
First Publication Date 2024-02-01
Owner STMicroelectronics S.r.l. (Italy)
Inventor
  • Galbiati, Ezio
  • Boscolo Berto, Michele
  • Maiocchi, Giuseppe
  • Ricci, Maurizio

Abstract

An embodiment method includes rectifying a back electromotive force of a spindle motor in a hard disk drive and energizing a voice coil motor in the hard disk drive using the rectified back electromotive force of the spindle motor via a voice coil motor power stage to retract a head of the hard disk drive to a park position. The head is retracted by moving the head towards the park position during a first retract phase and retaining the head in the park position during a second retract phase by applying a bias voltage to the voice coil motor power stage during a bias interval of the second retract phase. The method also includes producing a saturation signal indicative of onset of saturation in the voice coil motor power stage and controlling the bias voltage during the second retract phase.

IPC Classes  ?

  • G11B 5/54 - Disposition or mounting of heads relative to record carriers with provision for moving the head into, or out of, its operative position or across tracks
  • H02P 7/025 - Arrangements for regulating or controlling the speed or torque of electric DC motors the DC motors being of the linear type the DC motors being of the moving coil type, e.g. voice coil motors

86.

CONTROL CIRCUIT FOR AN ELECTRONIC CONVERTER, RELATED INTEGRATED CIRCUIT, ELECTRONIC CONVERTER AND METHOD

      
Application Number 18360598
Status Pending
Filing Date 2023-07-27
First Publication Date 2024-02-01
Owner STMICROELECTRONICS S.r.l. (Italy)
Inventor Cacciotto, Fabio

Abstract

A control circuit for a switching stage of an electronic converter is described. The control circuit includes a driver circuit configured to generate one or more drive signals as a function of a Pulse-Width Modulation, PWM, signal and a PWM signal generator circuit configured to generate the PWM signal. A first comparator asserts a comparison signal when a feedback signal having a voltage being indicative of a current flowing through an inductance of the switching stage is greater than a reference signal. In response to a clock signal, a storage element asserts the PWM signal, whereby the clock signal indicates the duration of the switching period of the PWM signal. Conversely, in response to determining that the comparison signal is asserted, the storage element de-asserts the PWM signal. Specifically, the reference signal is generated as a function of the voltage at a capacitance. For this purpose, a further comparator asserts a further comparison signal, when a feedback signal having a voltage being indicative of an output quantity is smaller than the reference voltage. Moreover, a charge and discharge circuit charges the capacitance when the further comparison signal is de-asserted, and discharges the capacitance when the further comparison signal is asserted.

IPC Classes  ?

  • H02M 1/088 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
  • H02M 3/157 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
  • H03K 7/08 - Duration or width modulation
  • H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion

87.

GAS SENSOR DEVICE FOR DETECTING GASES WITH LARGE MOLECULES

      
Application Number 18485072
Status Pending
Filing Date 2023-10-11
First Publication Date 2024-02-01
Owner
  • STMICROELECTRONICS S.r.l. (Italy)
  • STMICROELECTRONICS PTE LTD (Singapore)
Inventor
  • Brahem, Malek
  • Majeri, Hatem
  • Le Neel, Olivier
  • Shankar, Ravi
  • Alessi, Enrico Rosario
  • Biancolillo, Pasquale

Abstract

The present disclosure is directed to a gas sensor device that detects gases with large molecules (e.g., a gas with a molecular weight between 150 g/mol and 450 g/mol), such as siloxanes. The gas sensor device includes a thin film gas sensor and a bulk film gas sensor. The thin film gas sensor and the bulk film gas sensor each include a semiconductor metal oxide (SMO) film, a heater, and a temperature sensor. The SMO film of the thin film gas sensor is an thin film (e.g., between 90 nanometers and 110 nanometers thick), and the SMO film of the bulk film gas sensor is an thick film (e.g., between 5 micrometers and 20 micrometers thick). The gas sensor device detects gases with large molecules based on a variation between resistances of the SMO thin film and the SMO thick film.

IPC Classes  ?

  • G01N 33/00 - Investigating or analysing materials by specific methods not covered by groups
  • G01N 27/12 - Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating impedance by investigating resistance of a solid body in dependence upon reaction with a fluid
  • G01N 27/02 - Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating impedance

88.

MICROELECTROMECHANICAL MEMBRANE TRANSDUCER WITH ACTIVE DAMPER

      
Application Number 18487561
Status Pending
Filing Date 2023-10-16
First Publication Date 2024-02-01
Owner STMICROELECTRONICS S.r.l. (Italy)
Inventor
  • Giusti, Domenico
  • Quaglia, Fabio

Abstract

A microelectromechanical membrane transducer includes: a supporting structure; a cavity formed in the supporting structure; a membrane coupled to the supporting structure so as to cover the cavity on one side; a cantilever damper, which is fixed to the supporting structure around the perimeter of the membrane and extends towards the inside of the membrane at a distance from the membrane; and a damper piezoelectric actuator set on the cantilever damper and configured so as to bend the cantilever damper towards the membrane in response to an electrical actuation signal.

IPC Classes  ?

  • B81B 7/00 - Microstructural systems
  • B81C 1/00 - Manufacture or treatment of devices or systems in or on a substrate
  • F16F 15/00 - Suppression of vibrations in systems; Means or arrangements for avoiding or reducing out-of-balance forces, e.g. due to motion

89.

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES, CORRESPONDING SUBSTRATE AND SEMICONDUCTOR DEVICE

      
Application Number 18224701
Status Pending
Filing Date 2023-07-21
First Publication Date 2024-02-01
Owner STMicroelectronics S.r.l. (Italy)
Inventor Vitello, Dario

Abstract

A semiconductor die mounting substrate, such as a pre-molded leadframe, is provided with die pads, wherein each die pad has opposed first and second surfaces as well as tie bars projecting therefrom. Semiconductor dice are mounted at the first surface of the die pads. A molding encapsulation material surrounds the semiconductor dice mounted at the first surface of the die pads to produce semiconductor devices, with the semiconductor devices being mutually coupled via the tie bars. The tie bars are then cut transverse to their longitudinal direction at an intermediate singulation location to singulate the semiconductor devices into individual semiconductor devices. The tie bars have a hollowed-out portion with a channel-shaped cross-sectional profile at the intermediate singulation location. Easier-to-cut tie bars can be provided without impairing their stiffness in comparison with tie bars having full rectangular/square cross-sectional shapes.

IPC Classes  ?

  • H01L 23/495 - Lead-frames
  • H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
  • H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings

90.

CURRENT SENSING CIRCUIT AND HARD DISK DRIVE INCLUDING SAME

      
Application Number 18343868
Status Pending
Filing Date 2023-06-29
First Publication Date 2024-02-01
Owner STMicroelectronics S.r.l. (Italy)
Inventor Galbiati, Ezio

Abstract

A circuit includes a set of input nodes configured to be coupled to respective ones of the windings of a spindle motor in a hard disk drive to sense the voltages applied to the windings. A set of output nodes is configured to provide output signals indicative of direction of flow of the currents through the windings. Level shifters are coupled to respective input nodes in the set of input nodes and have level-shifted output nodes configured to provide down-shifted replicas of the voltages at the respective input nodes in the set of input nodes. Flip-flops have inputs coupled to respective ones of the level-shifted output nodes of the level shifters and outputs configured to provide the output signals coupled to respective output nodes.

IPC Classes  ?

  • G11B 21/02 - Driving or moving of heads
  • G11B 25/04 - Apparatus characterised by the shape of record carrier employed but not specific to the method of recording or reproducing using flat record carriers, e.g. disc, card
  • G11B 27/36 - Monitoring, i.e. supervising the progress of recording or reproducing

91.

DYNAMIC CURRENT SCALING OF A REGULATOR

      
Application Number 18475678
Status Pending
Filing Date 2023-09-27
First Publication Date 2024-01-25
Owner STMICROELECTRONICS S.r.l. (Italy)
Inventor
  • Marchese, Carmela
  • Bassoli, Rossella

Abstract

A method and apparatus for performing dynamic current scaling of an input current of a voltage regulator are provided. The method and apparatus allow tuning current consumption in various applications, calculating a duration of an activity phase in which various algorithms are executed and activating dynamic current scaling of a regulator if the activity duration is shorter than a programmable threshold. A controller receives a threshold for an activity duration and a window size in which to evaluate the activity duration.

IPC Classes  ?

  • G05F 1/10 - Regulating voltage or current
  • G06F 1/3206 - Monitoring of events, devices or parameters that trigger a change in power modality

92.

DUAL-OPERATING ACCELEROMETER

      
Application Number 18480358
Status Pending
Filing Date 2023-10-03
First Publication Date 2024-01-25
Owner STMICROELECTRONICS S.r.l. (Italy)
Inventor
  • Rizzini, Francesco
  • Manca, Nicolo'
  • Dall'Oglio, Cristian

Abstract

The present disclosure is directed to micro-electromechanical system (MEMS) accelerometers that are configured for a user interface mode and a true wireless stereo (TWS) mode of an audio device. The accelerometers are fabricated with specific electromechanical parameters, such as mass, stiffness, active capacitance, and bonding pressure. As a result of the specific electromechanical parameters, the accelerometers have a resonance frequency, quality factor, sensitivity, and Brownian noise density that are suitable for both the user interface mode and the TWS mode.

IPC Classes  ?

  • G01P 15/125 - Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces with conversion into electric or magnetic values by capacitive pick-up
  • B81B 7/02 - Microstructural systems containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems (MEMS)
  • G01P 15/18 - Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration in two or more dimensions

93.

CONTROL METHOD AND CIRCUIT FOR PHASE SHIFT REGULATION OF INTERLEAVED CONVERTERS AT VARIABLE SWITCHING FREQUENCY

      
Application Number 17872579
Status Pending
Filing Date 2022-07-25
First Publication Date 2024-01-25
Owner STMicroelectronics S.r.l. (Italy)
Inventor
  • Messina, Sebastiano
  • Torrisi, Marco

Abstract

Uncompensated upper and lower reference-currents are generated for first and second branches of a high-frequency half-bridge within an interleaved-totem-pole PFC. A first control-signal for the first branch is generated from comparison between an inductor-current and uncompensated reference-currents for the first branch, a first timing-reference is generated from the first control-signal from a number of active branches, a compensated upper reference-current is generated for the second branch by adding a first compensation-current to the uncompensated upper reference-current for the second branch, a compensated lower reference-current is generated for the second branch by subtracting the first compensation-current from the uncompensated lower reference-current for the second branch, a second control-signal is generated for the second branch from the compensated reference-currents for the second branch, a first timing-difference is generated from a phase-difference between the first and second control-signals, and the first compensation-current is generated from a difference between the first timing-reference and timing-difference.

IPC Classes  ?

  • H02M 1/42 - Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
  • H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion

94.

METHOD FOR AUTO-ALIGNED MANUFACTURING OF A VDMOS TRANSISTOR, AND AUTO-ALIGNED VDMOS TRANSISTOR

      
Application Number 18323317
Status Pending
Filing Date 2023-05-24
First Publication Date 2024-01-25
Owner STMICROELECTRONICS S.r.l. (Italy)
Inventor Enea, Vincenzo

Abstract

A MOS transistor, in particular a vertical channel transistor, includes a semiconductor body housing a body region, a source region, a drain electrode and gate electrodes. The gate electrodes extend in corresponding recesses which are symmetrical with respect to an axis of symmetry of the semiconductor body. The transistor also has spacers which are also symmetrical with respect to the axis of symmetry. A source electrode extends in electrical contact with the source region at a surface portion of the semiconductor body surrounded by the spacers and is in particular adjacent to the spacers. During manufacture the spacers are used to form in an auto-aligning way the source electrode which is symmetrical with respect to the axis of symmetry and equidistant from the gate electrodes.

IPC Classes  ?

  • H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
  • H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 29/66 - Types of semiconductor device
  • H01L 21/3065 - Plasma etching; Reactive-ion etching
  • H01L 21/308 - Chemical or electrical treatment, e.g. electrolytic etching using masks
  • H01L 29/40 - Electrodes

95.

Waveform generator using a waveform coding scheme for both long states and toggle states

      
Application Number 17895671
Grant Number 11881875
Status In Force
Filing Date 2022-08-25
First Publication Date 2024-01-23
Grant Date 2024-01-23
Owner STMicroelectronics S.r.l. (Italy)
Inventor
  • Passi, Stefano
  • Bardelli, Roberto Giorgio

Abstract

A memory includes a sequence of memory locations storing a corresponding sequence of state codes that specifying the shape of a waveform. The sequence of state codes is read from the memory and decoded by a long and toggle decoder circuit. The decoding operation generates a sequence of signal codes. When the state code is a long code, the sequence of signal codes includes same signal codes corresponding to a signal level of the waveform. When the state code is a toggle code, the sequence of signal codes includes a first signal code corresponding to one signal level of the waveform and a second signal code corresponding to another signal level of the waveform. A signal decode circuit then decodes the signal codes in the sequence of signal codes to generate the waveform for output which includes the signal levels corresponding to the decoded signal codes.

IPC Classes  ?

  • H04B 1/04 - Circuits
  • H04B 11/00 - Transmission systems employing ultrasonic, sonic or infrasonic waves

96.

MEMS MIRROR DEVICE WITH PIEZOELECTRIC ACTUATION AND MANUFACTURING PROCESS THEREOF

      
Application Number 18220554
Status Pending
Filing Date 2023-07-11
First Publication Date 2024-01-18
Owner STMicroelectronics S.r.l. (Italy)
Inventor
  • Merli, Massimiliano
  • Carminati, Roberto
  • Boni, Nicolo'
  • Costantini, Sonia
  • Prelini, Carlo Luigi

Abstract

Disclosed herein is a micro-electro-mechanical mirror device having a fixed structure defining an external frame delimiting a cavity, a tiltable structure extending into the cavity, a reflecting surface carried by the tiltable structure and having a main extension in a horizontal plane, and an actuation structure coupled between the tiltable structure and the fixed structure. The actuation structure is formed by a first pair of actuation arms causing rotation of the tiltable structure around a first axis parallel to the horizontal plane. The actuation arms are elastically coupled to the tiltable structure through elastic coupling elements and are each formed by a bearing structure and a piezoelectric structure. The bearing structure of each actuation arm is formed by a soft region of a first material and the elastic coupling elements are formed by a bearing layer of a second material, the second material having greater stiffness than the first material.

IPC Classes  ?

  • G02B 26/08 - Optical devices or arrangements for the control of light using movable or deformable optical elements for controlling the direction of light
  • B81B 3/00 - Devices comprising flexible or deformable elements, e.g. comprising elastic tongues or membranes
  • B81C 1/00 - Manufacture or treatment of devices or systems in or on a substrate

97.

TIME BASED PREDICTIVE MAINTENANCE FOR CAPACITIVE LOADS IN FACTORY AUTOMATION APPLICATIONS

      
Application Number 17866701
Status Pending
Filing Date 2022-07-18
First Publication Date 2024-01-18
Owner STMicroelectronics S.r.l. (Italy)
Inventor
  • Ragonese, Domenico
  • Marano, Vincenzo
  • Di Genova, Giuseppe Antonio
  • Minieri, Marco

Abstract

Disclosed herein is a system including a power transistor having a first conduction terminal coupled to a supply node, a second conduction terminal coupled to an output node, and a control terminal controlled by a drive signal. The system further includes a driver configured to receive an input voltage from an external component and generate the drive signal based thereupon, and a sense circuit. The sense circuit is configured to, when the power transistor is powering a load coupled to the output node: detect whether the power transistor has entered an overload condition, and if so, determine a duration of time that the power transistor is in the overload condition; and assert a diagnostic signal in response to the duration of time being outside of a time window.

IPC Classes  ?

  • G05F 1/573 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for protection with overcurrent detector

98.

HEMT TRANSISTOR INCLUDING AN IMPROVED GATE REGION AND RELATED MANUFACTURING PROCESS

      
Application Number 18477372
Status Pending
Filing Date 2023-09-28
First Publication Date 2024-01-18
Owner STMICROELECTRONICS S.r.l. (Italy)
Inventor
  • Iucolano, Ferdinando
  • Tringali, Cristina

Abstract

An HEMT includes a semiconductor body, which includes a semiconductor heterostructure, and a conductive gate region. The gate region includes: a contact region, which is made of a first metal material and contacts the semiconductor body to form a Schottky junction; a barrier region, which is made of a second metal material and is set on the contact region; and a top region, which extends on the barrier region and is made of a third metal material, which has a resistivity lower than the resistivity of the first metal material. The HEMT moreover comprises a dielectric region, which includes at least one front dielectric subregion, which extends over the contact region, delimiting a front opening that gives out onto the contact region; and wherein the barrier region extends into the front opening and over at least part of the front dielectric subregion.

IPC Classes  ?

  • H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
  • H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/47 - Schottky barrier electrodes
  • H01L 29/66 - Types of semiconductor device

99.

INTEGRATED SENSOR AND METHOD OF TIMING MONITORING IN AN INTEGRATED SENSOR

      
Application Number 18348993
Status Pending
Filing Date 2023-07-07
First Publication Date 2024-01-18
Owner STMICROELECTRONICS S.r.l. (Italy)
Inventor Quartiroli, Matteo

Abstract

The integrated sensor has a clock which provides a clock signal having a clock frequency; a digital detector which detects a power grid signal and generates a reference digital signal indicative of the power grid signal and having a sample rate which is a function of the clock frequency; and a timing monitoring stage which receives the reference digital signal and a nominal signal indicative of a nominal timing of the reference digital signal. The timing monitoring stage also compares the reference digital signal with the nominal signal and, in response, provides an error signal indicative of a timing error between the reference digital signal and the nominal signal.

IPC Classes  ?

  • G01R 29/12 - Measuring electrostatic fields
  • G01R 23/02 - Arrangements for measuring frequency, e.g. pulse repetition rate; Arrangements for measuring period of current or voltage

100.

SWITCHING POWER STAGE CIRCUIT ARRANGEMENT WITH CYCLE-BY-CYCLE PROTECTION AGAINST OVER-CURRENTS AND CORRESPONDING SWITCHING METHOD

      
Application Number 18214751
Status Pending
Filing Date 2023-06-27
First Publication Date 2024-01-11
Owner STMicroelectronics S.r.l. (Italy)
Inventor
  • Botti, Edoardo
  • Gonano, Giovanni
  • Raimondi, Marco

Abstract

A half bridge switching power stage includes high/low side switches driven in response to a cycle-by-cycle protected driving signal derived from a PWM signal. Signals indicative of detected over-currents at said high/low side switches are processed to output the cycle-by-cycle protected driving signal, when the signal indicative of the detected over-current indicates, during a time interval within which the high/low side switch is turned on, that current flowing in the turned on high/low side switch crosses a given threshold, as an inverted PWM signal by turning off the turned on high/low side switch, and otherwise outputting said cycle-by-cycle protected driving signal as a not inverted PWM signal. An anomaly detection circuit receives the signals indicative of the over-current and switches off both the high/low side switches when an anomaly is detected in a pattern of over-current events in the signals indicative of the over-current.

IPC Classes  ?

  • H02M 1/32 - Means for protecting converters other than by automatic disconnection
  • H02M 3/157 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
  • H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion
  • H03F 3/217 - Class D power amplifiers; Switching amplifiers
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