A semiconductor device making it easy to detect disconnection in source wires and achieving a reduction in resistance and an inspection method for the semiconductor device are provided. A semiconductor device according to the present embodiment includes: a lead frame; a semiconductor chip on the lead frame; a source pad provided in the semiconductor chip; a plurality of source wires connected to the source pad; a disconnection detection wire connected to the source pad; source terminals connected to the plurality of source wires; and a disconnection detection terminal connected to the disconnection detection wire. One end of the disconnection detection wire is positioned in vicinity of a corner of the source pad closer to the disconnection detection terminal side.
A bonding region is specified by having a horizontal line partially constituting crosshairs displayed on a monitor of a wire bonding apparatus superimposed on a first line segment of a first marker, and having a vertical line partially constituting the crosshairs superimposed on a first line segment of a second marker.
H01L 23/544 - Marques appliquées sur le dispositif semi-conducteur, p.ex. marques de repérage, schémas de test
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/31 - Capsulations, p.ex. couches de capsulation, revêtements caractérisées par leur disposition
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/16 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types couverts par plusieurs des groupes principaux , ou dans une seule sous-classe de , , p.ex. circuit hybrides
3.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device including an oscillation circuit includes a MISFET having a halo region formed on a semiconductor substrate and a plurality of MISFETs having no halo regions formed on the semiconductor substrate. Gate electrodes of the plurality of MISFETs having no halo regions are electrically connected to each other. The plurality of MISFETs having no halo regions is used in a pair transistor included in the oscillation circuit.
H01L 27/06 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration non répétitive
H01L 21/265 - Bombardement par des radiations ondulatoires ou corpusculaires par des radiations d'énergie élevée produisant une implantation d'ions
H01L 21/266 - Bombardement par des radiations ondulatoires ou corpusculaires par des radiations d'énergie élevée produisant une implantation d'ions en utilisant des masques
H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
4.
COMMON LEAD FRAME, SEMICONDUCTOR DEVICE, METHOD FOR FORMING A COMMON LEAD FRAME, AND CONTROL PROGRAM
A common lead frame can be used for both a first package and a second package and has a planar shape according to specifications of each of a first chip used in the first package and a second chip used in the second package, and a thickness of at least a part of a lead portion through which any one of a first cutting line corresponding to an outer peripheral side of the first package and a second cutting line corresponding to an outer peripheral side of the second package passes is smaller than a thickness of a lead portion through which the first cutting line and the second cutting line do not pass.
H01L 21/48 - Fabrication ou traitement de parties, p.ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes
A trench is formed in a semiconductor substrate. A first silicon oxide film is formed in an inside of the trench. A poly-crystalline silicon film is formed on the first silicon oxide film. A second silicon oxide film is formed from the poly-crystalline silicon film by performing a thermal oxidation treatment to the poly-crystalline silicon film. Thus, an insulating film including the first silicon oxide film and the second silicon oxide film is formed. A first conductive film is formed so as to embed the inside of the trench via the insulating film.
This invention provides a method of managing secret information that ensures that key information in the discard phase can be invalidated and that the system cannot be started. In method of managing secret information in a semiconductor device, the semiconductor device has an OTP (One Time Programmable) module, a security module and a processor. The OTP module further has an OTP memory for storing a secret information and a lifecycle flag for defining an operation phase and a discard phase, a sequencer for reading information stored in the OTP memory and a register for storing the information read by the sequencer. The security module performs a process by the secret information. The processor requests the process to the security module when changing the operation phase to the discard phase and sends a request to the security module to invalidate the secret information.
G06F 21/57 - Certification ou préservation de plates-formes informatiques fiables, p.ex. démarrages ou arrêts sécurisés, suivis de version, contrôles de logiciel système, mises à jour sécurisées ou évaluation de vulnérabilité
G06F 21/79 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du stockage de données dans les supports de stockage à semi-conducteurs, p.ex. les mémoires adressables directement
A height of an upper surface of a control gate electrode is lower than a highest position of a lower surface of a silicide layer on a memory gate electrode adjacent to the control gate electrode via an ONO film. As a result, a structure in contact with the ONO film between the control gate electrode and the memory gate electrode is only the control gate electrode and the memory gate electrode made of polysilicon.
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 27/11521 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec grilles flottantes caractérisées par la région noyau de mémoire
H01L 27/11526 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec grilles flottantes caractérisées par la région de circuit périphérique
H01L 27/11568 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par la région noyau de mémoire
H01L 27/11573 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par la région de circuit périphérique
H01L 29/788 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée à grille flottante
H01L 29/792 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée à isolant de grille à emmagasinage de charges, p.ex. transistor de mémoire MNOS
A semiconductor device includes an insulating substrate and an upper inductor that is formed on the insulating substrate and is a component of a transformer that performs contactless communication between different potentials. Here, the upper inductor is configured to be applied with a first potential. The upper inductor is formed so as to be magnetically coupled to a lower inductor that is configured to be applied with a second potential different from the first potential.
H01L 25/16 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types couverts par plusieurs des groupes principaux , ou dans une seule sous-classe de , , p.ex. circuit hybrides
H01F 27/30 - Fixation ou serrage de bobines, d'enroulements ou de parties de ceux-ci entre eux; Fixation ou montage des bobines ou enroulements sur le noyau, dans l'enveloppe ou sur un autre support
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
A semiconductor device includes a logic circuit, a memory, and a storage device. The storage device has a first special information storage region into which special information is written before a solder reflow process, a second special information storage region into which special information for updating is written after the solder reflow process, and a data storage region. The first special information storage region is constituted by a memory cell having a high reflow resistance and in which data is retained even after the solder reflow process. The second special information storage region and the data storage region are constituted by memory cells having a low reflow resistance and in which data may not be retained during the solder reflow process.
A semiconductor device includes a first clock; a second clock; a first baud rate generator generating the basic clock by using the first clock; a second baud rate generator generating the basic clock by using the second clock; and a control circuit correcting the first baud rate generator. The control circuit includes: a correction operation signal output circuit outputting a correction operation signal on the basis of the second clock of the second baud rate generator; and a correction value setting circuit outputting a correction value setting signal on the basis of the correction operation signal. The second baud rate generator counts a correction period in accordance with the correction operation signal by using the first clock on the basis of the correction value setting signal, and sets a baud rate correction value on the basis of a count result.
A semiconductor device includes a bus control circuit that controls access to a slave shared by a plurality of masters. The bus control circuit includes a plurality of priority determination circuits corresponding to the plurality of masters. The priority determination circuit is configured to, when receiving an urgent access from a corresponding master, change a priority level signal included in an access request from the corresponding master to allocate a high priority level for emergency and allocate a low priority level to a master other than the corresponding master.
G06F 13/372 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus ou au système à bus communs avec commande d'accès décentralisée utilisant une priorité dépendant du temps, p.ex. des compteurs de temps individuellement chargés ou des tranches de temps
A semiconductor device according to one embodiment, includes: a wiring substrate having a core insulating layer; a semiconductor chip mounted on an upper surface of the wiring substrate; a plurality of solder balls formed on a lower surface of the wiring substrate; and a heat sink having a first portion fixed to a back surface of the semiconductor chip via a first adhesive layer, and a second portion located around the first portion and fixed to the wiring substrate via a second adhesive layer. Here, a portion of the plurality of solder balls is arranged at a position overlapping with each of the second portion of the heat sink and the second adhesive layer. Also, a second thickness of the second adhesive layer is greater than two times a first thickness of the first adhesive layer.
H01L 23/367 - Refroidissement facilité par la forme du dispositif
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/498 - Connexions électriques sur des substrats isolants
It is related to improving a performance of a semiconductor device and suppressing yield deterioration. Using a resist pattern as a mask, an ion-implantation is performed from an upper surface of a semiconductor substrate to form an ion-implanted layer in the semiconductor substrate. By subsequently, another ion-implantation is performed. Then, another ion-implanted layer is formed in the semiconductor substrate so as to overlap with the ion-implanted layer. Next, a heat treatment is performed on the semiconductor substrate to diffuse impurities contained in the ion-implanted layers, thereby an p-type floating region is formed.
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 21/225 - Diffusion des impuretés, p.ex. des matériaux de dopage, des matériaux pour électrodes, à l'intérieur ou hors du corps semi-conducteur, ou entre les régions semi-conductrices; Redistribution des impuretés, p.ex. sans introduction ou sans élimination de matériau dopant supplémentaire en utilisant la diffusion dans ou hors d'un solide, à partir d'une ou en phase solide, p.ex. une couche d'oxyde dopée
H01L 21/265 - Bombardement par des radiations ondulatoires ou corpusculaires par des radiations d'énergie élevée produisant une implantation d'ions
H01L 21/266 - Bombardement par des radiations ondulatoires ou corpusculaires par des radiations d'énergie élevée produisant une implantation d'ions en utilisant des masques
H01L 21/28 - Fabrication des électrodes sur les corps semi-conducteurs par emploi de procédés ou d'appareils non couverts par les groupes
14.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A first trench extending in a Y direction is formed in each of a semiconductor substrate located in a cell region and the semiconductor substrate located in an outer peripheral region. A second trench is formed in the semiconductor substrate in the outer peripheral region so as to surround the cell region in a plan view. A p-type body region is formed in the semiconductor substrate in each region. A plurality of p-type floating regions is formed in the semiconductor substrate in the outer peripheral region. A field plate electrode is formed at a lower portion of each of the first trench and the second trench. A gate electrode is formed at an upper portion of the first trench located in the cell region. A floating gate electrode is formed at an upper portion of each of the first trench located in the outer peripheral region and the second trench.
The present disclosure relates technique capable of electrically monitoring a recess amount of a semiconductor substrate. That is, a semiconductor device includes the semiconductor substrate of a first conductivity type having a first main surface and a second main surface, a first area provided on the first main surface, and a second region provided on the first main surface between the first areas. The second area includes an evaluation element. The evaluation element includes: a first semiconductor region of a second conductivity type provided in the first main surface side; a second semiconductor region of the first conductivity type provided on the first main surface side of the first semiconductor region; a first electrode pad in contact with the first semiconductor region; and a second electrode pad in contact with the second semiconductor region.
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 21/66 - Test ou mesure durant la fabrication ou le traitement
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
16.
METHOD OF TESTING SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
An electrical test of a semiconductor device is conducted by electrically connecting a plurality of leads of the semiconductor device with a plurality of electrodes of a test board via a plurality of socket terminals of a socket of a test apparatus, respectively. At least a part of the socket is disposed inside a chamber of the test apparatus, and the test board is disposed outside the chamber. The semiconductor device is to be cooled by a cool air circulating in the chamber. The socket has a cavity portion through which the cool air circulating in the chamber can pass, and a part of each of the plurality of socket terminals is exposed in the cavity portion of the socket. The plurality of socket terminals is to be cooled by the cool air passing through the cavity portion of the socket.
A second memory has n banks accessible in parallel, and stores pixel data. An input DMA controller respectively transfers the pixel data stored in the second memory to n multiply-accumulate units by using n input channels. A sequence controller controls the input DMA controller so as to cause a first input channel to transfer the pixel data in a first pixel space of the input bank to a first multiply-accumulate unit and cause a second input channel to transfer the pixel data in a second pixel space of the same input bank to a second multiply-accumulate unit.
G06F 13/28 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant le transfert par rafale, p.ex. acces direct à la mémoire, vol de cycle
G06T 1/20 - Architectures de processeurs; Configuration de processeurs p.ex. configuration en pipeline
A second memory stores a plurality of input data sets DSi composed of a plurality of pieces of input data. N multiply-accumulate units are capable of performing parallel processings, and each performs a multiply-accumulate operation on any one of the plurality of weight parameter sets and any one of the plurality of input data sets. A second DMA controller transfers the input data set from the second memory to the n multiply-accumulate units. A measurement circuit measures a degree of matching/mismatching of logic levels among the plurality of pieces of input data contained in the input data set within the memory MEM2, the sequence controller controls the number of parallel processings by the n multiply-accumulate units based on a measurement result by the measurement circuit.
G06F 12/0831 - Protocoles de cohérence de mémoire cache à l’aide d’un schéma de bus, p.ex. avec moyen de contrôle ou de surveillance
G06F 13/28 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant le transfert par rafale, p.ex. acces direct à la mémoire, vol de cycle
A semiconductor chip includes a transformer that performs contactless communication between different potentials. The semiconductor chip includes a semiconductor substrate, a semiconductor region formed in an upper surface of the semiconductor substrate, and the transformer formed over the semiconductor substrate. Here, the transformer includes a lower inductor, a lead wiring portion electrically connected to the lower inductor, and an upper inductor 100 magnetically coupled to the lower inductor, and the lead wiring portion has a wiring facing the semiconductor region.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
A disconnection detector circuit that can favorably inspect a connection state of a wire without increase in parasitic capacitance is provided. A semiconductor device includes, in one package, a first integrated circuit including a transformer including a primary coil and a secondary coil, and a second integrated circuit connected to a midpoint and one end of the secondary coil. The second integrated circuit includes a reference line and a detector circuit. The reference line connects the midpoint of the secondary coil and a reference potential. On basis of a potential at a predetermined reference point of the first power supply line, the detector circuit detects whether a connection state between the second integrated circuit and the secondary coil is normal or abnormal.
Before a temperature characteristic of a band gap reference circuit is tested, temperature dependencies of a reference voltage and an absolute temperature proportional voltage for a plurality of samples are measured. When the temperature characteristic is tested, based on a difference ΔVref between the reference voltage of the band gap reference circuit at a predetermined temperature and a median value of the reference voltages of the plurality of samples, a difference ΔVptat between the absolute temperature proportional voltage of the band gap reference circuit at a predetermined temperature and a median value of the absolute temperature proportional voltages of the plurality of samples is calculated.
G01K 13/00 - Thermomètres spécialement adaptés à des fins spécifiques
G01K 7/16 - Mesure de la température basée sur l'utilisation d'éléments électriques ou magnétiques directement sensibles à la chaleur utilisant des éléments résistifs
A battery simulator includes a circuit simulator that simulates an operation of an RC parallel circuit which is an equivalent circuit of a battery to be monitored and an RC parallel circuit optimization device that optimizes the RC parallel circuit based on a monitoring frequency of the battery, wherein the RC parallel circuit optimization device is configured to: delete a capacitance value of the RC parallel circuit when the monitoring frequency is determined to be a low frequency, and delete resistance and capacitance values of the RC parallel circuit when the monitoring frequency is determined to be a high frequency.
G01R 31/374 - Dispositions pour le test, la mesure ou la surveillance de l’état électrique d’accumulateurs ou de batteries, p.ex. de la capacité ou de l’état de charge avec des moyens pour corriger la mesure en fonction de la température ou du vieillissement
G01R 31/3835 - Dispositions pour la surveillance de variables des batteries ou des accumulateurs, p.ex. état de charge ne faisant intervenir que des mesures de tension
H01M 10/42 - Procédés ou dispositions pour assurer le fonctionnement ou l'entretien des éléments secondaires ou des demi-éléments secondaires
A semiconductor chip includes a lower wiring layer, a multilayer wiring layer formed on the lower wiring layer, and an upper wiring layer formed on the multilayer wiring layer. Here, a thickness of a wiring provided in the lower wiring layer is larger than a thickness of each of a plurality of wirings provided in the multilayer wiring layer, and a thickness of a wiring provided in the upper wiring layer is larger than the thickness of each of the plurality of wirings provided in the multilayer wiring layer. A lower inductor which is a component of a transformer is provided in the lower wiring layer, and an upper inductor which is a component of the transformer is provided in the upper wiring layer.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/528 - Configuration de la structure d'interconnexion
According to one embodiment, a semiconductor device includes a semiconductor substrate, wherein, when viewed from a front surface side, the semiconductor substrate includes: an IGBT region including a plurality of IGBTs; a diode region disposed to surround the IGBT region; a diode region including a plurality of diodes; and a peripheral region disposed to surround the diode region, wherein the IGBT includes: a drift layer; a barrier layer; a channel layer; an emitter layer; a pair of trench electrodes 60; a trench insulating film; a field stop layer; and a collector layer, and a diode includes a drift layer; a semiconductor layer; a channel layer; a pair of trench electrodes; a trench insulating film; a field stop layer; and a cathode layer.
H01L 29/739 - Dispositifs du type transistor, c.à d. susceptibles de répondre en continu aux signaux de commande appliqués commandés par effet de champ
If the program stored in the external storage itself is replaced by a legitimate old version of the program by a malicious third party, the semiconductor device (for example, SoC) cannot recognize that it is an old version of the program, and the program can be easily rolled back. An OTP (One Time Programmable ROM) is installed in the chip to manage the latest software version. Specifically, the software version information is checked to see if it is older than the OTP version information by linking the electronic signature updated each time the software is updated with the control table containing the latest software version information stored in the OTP, and comparing the OTP management table with the software version information at system startup.
G06F 8/71 - Gestion de versions ; Gestion de configuration
G06F 21/57 - Certification ou préservation de plates-formes informatiques fiables, p.ex. démarrages ou arrêts sécurisés, suivis de version, contrôles de logiciel système, mises à jour sécurisées ou évaluation de vulnérabilité
A semiconductor device includes a trench formed in an n-type semiconductor substrate, a p-type body region, an n-type source region, a field plate electrode formed at a lower portion of the trench, and a gate electrode formed at an upper portion of the trench. A gate potential is to be supplied to the gate electrode, a source potential is to be supplied to the source region and the body region, and a drain potential is to be supplied to the semiconductor substrate. A potential larger than the source potential and smaller than the drain potential is to be supplied to the field plate electrode.
A semiconductor device includes a semiconductor substrate, a first insulating film formed on an upper surface of the semiconductor substrate in an outer peripheral region so as to surround a cell region in plan view, and a resistive element formed on the first insulating film so as to surround the cell region in plan view. A second insulating film having a thickness thinner than that of the first insulating film is formed on the upper surface of the semiconductor substrate in the outer peripheral region. A dummy pattern is formed from a portion over the second insulating film to a portion over the first insulating film so as to cover a step occurring between the second insulating film and the first insulating film.
Techniques are provided for suppressing the accumulation of holes in floating region and improving the switching time of a semiconductor device such as an Insulated Gate Bipolar. The semiconductor device includes a trench gate and a trench emitter formed in a semiconductor substrate, and a floating region of a first conductivity type formed in the semiconductor substrate sandwiched between the trench gate and the trench emitter. The bottom of the floating region is located below the bottom of the trench gate and the trench emitter, and the floating region has a crystal defect region including crystal defects selectively formed at a position near an upper surface of the semiconductor substrate in the floating region.
H01L 29/739 - Dispositifs du type transistor, c.à d. susceptibles de répondre en continu aux signaux de commande appliqués commandés par effet de champ
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/66 - Types de dispositifs semi-conducteurs
29.
KEY UPDATE MANAGEMENT SYSTEM AND KEY UPDATE MANAGEMENT METHOD
When the external storage itself is replaced by a legitimate old key by a malicious third party, the security IP cannot recognize that it is the old key and can be easily rolled back, that is, the old key is regarded as the legitimate key and operates. An OTP is provided in the SoC, and the version of the key ring is managed in one control table area. Specifically, predetermined information that is updated in synchronization with the key update is written in the management table area of the OTP, and an authentication value is calculated by associating the predetermined information with a key ring including the update key. The calculated authentication value is added and registered when registering the key ring.
H04L 9/14 - Dispositions pour les communications secrètes ou protégées; Protocoles réseaux de sécurité utilisant plusieurs clés ou algorithmes
H04L 9/32 - Dispositions pour les communications secrètes ou protégées; Protocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
30.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A trench is formed in a semiconductor substrate. An insulating film is formed in the trench and on an upper surface of the semiconductor substrate. An ion implantation is performed to the insulating film. An etching treatment is performed to the insulating film, thereby a thickness of the insulating film is reduced. A conductive film is formed in the trench via the insulating film. In plan view, the trench extends in a Y-direction. The above-described ion implantation is performed from a direction inclined by a predetermined angle from an extending direction of a normal line with respect to the upper surface of the semiconductor substrate.
A control gate electrode is formed on a semiconductor substrate via a first gate dielectric film. A second gate dielectric film including a charge storage layer is formed on an upper surface of the semiconductor substrate and on one side surface of the control gate electrode. A memory gate electrode is formed on the second gate dielectric film. A cap film formed of a dielectric material is formed on an upper surface of the control gate electrode, and a silicide film is formed on an upper surface of the memory gate electrode. An upper surface of the cap film and an upper surface of the silicide film are exposed from a sidewall spacer SW and an interlayer dielectric film.
A message handler (61, 62) is described. The message handler is configured, in response to receiving a data package (131, 132) which is formatted according to a given communications protocol, such as CAN or Ethernet, and which comprises package-directing data (22; FIG. 4) and payload data (23; FIG. 4), to generate package (14) having a predetermined data format, for example a layer-2 or layer-3 package, which comprises a header (24; FIG. 4) and payload data (25; FIG. 4). The header comprises an address generated in dependence upon the package-directing data and wherein the payload comprises the data package. The package (14) having a predetermined data format may be an IEEE 1722 frame.
A jitter cancellation circuit includes a clock buffer and a current control unit. The clock buffer inputs a clock outputted from a clock propagation element driven by a power supply voltage. Further, the clock buffer decreases with respect to a power supply voltage according to an increase in an operating current, while giving a delay time increased according to a decrease in the operating current to output the clock. The current control unit is configured to increase/decrease the operating current of the clock buffer in an opposite phase of a fluctuation component of the power supply voltage.
H03K 5/02 - Mise en forme d'impulsions par amplification
H03K 5/133 - Dispositions ayant une sortie unique et transformant les signaux d'entrée en impulsions délivrées à des intervalles de temps désirés utilisant une chaîne de dispositifs actifs de retard
H03K 5/135 - Dispositions ayant une sortie unique et transformant les signaux d'entrée en impulsions délivrées à des intervalles de temps désirés par l'utilisation de signaux de référence de temps, p.ex. des signaux d'horloge
In a case where a crack occurs in a dicing step, the crack can be suppressed from proceeding toward an element region. A first scribe region and a second scribe region that both define an element region are formed in a main surface of a semiconductor wafer. In the first scribe region, an evaluation-deep-trench group including an evaluation-deep-trench-first portion and an evaluation-deep-trench-second portion is formed. The evaluation-deep-trench-first portion is formed in a first region. The evaluation-deep-trench-second portion has a width in an X-axis direction, and is formed in a bar shape extending in a Y-axis direction, in a second region located between the first region and the element region.
H01L 21/784 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs qui consistent chacun en un seul élément de circuit le substrat étant un corps semi-conducteur
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 21/66 - Test ou mesure durant la fabrication ou le traitement
35.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device includes a cell region in which MISFETs are formed, and a peripheral region surrounding the cell region in plan view. In the cell region and the peripheral region, an n-type impurity region is formed in a semiconductor substrate. In the semiconductor substrate, an element isolation portion, a p-type impurity region, and an n-type impurity region are formed in the peripheral region so as to surround the cell region in plan view. A p-type impurity region and an n-type impurity region are formed in the semiconductor substrate in the cell region so as to contact the impurity region. The element isolation portion is located in the impurity region and is spaced apart from a junction interface between the impurity region and the impurity region.
H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
A semiconductor device capable of shortening processing time of a neural network is provided. The memory stores a compressed weight parameter. A plurality of multiply accumulators perform a multiply-accumulation operation to a plurality of pixel data and a plurality of weight parameters. A decompressor restores the compressed weight parameter stored in the memory to a plurality of weight parameters. A memory for weight parameter stores the plurality of weight parameters restored by the decompressor. The DMA controller transfers the plurality of weight parameters from the memory to the memory for weight parameter via the decompressor. A sequence controller writes down the plurality of weight parameters stored in the memory for weight parameter to a weight parameter buffer at write timing.
G06F 13/16 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus de mémoire
G06F 13/28 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant le transfert par rafale, p.ex. acces direct à la mémoire, vol de cycle
G06F 7/544 - Méthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p.ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs non spécifiés pour l'évaluation de fonctions par calcul
When a counter circuit that repeatedly counts a loop variable, an accumulator variable, or the like is configured by a programmable device, a processing delay occurs. The processor comprises an array of programmable logic and at least one dedicated counter circuit for counting variables that are repeatedly modified.
A semiconductor device has an impurity region covering a bottom of a gate trench and a column region. A bottom of the column region is deeper than a bottom of the gate trench. The impurity region is arranged between the gate trench and the column region. This structure can improve the characteristics of the semiconductor device.
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
39.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
The source region, drain region, buried insulating film, gate insulating film, and gate electrode of the semiconductor device are formed in a main surface of a semiconductor substrate. The buried insulating film is buried in a first trench formed between the source and drain regions. The first trench has a first side surface and a first bottom surface. The first side surface faces the source region in a first direction extending from one of the source and drain regions to the other. The first bottom surface is connected to the first side surface and is along the main surface of the semiconductor substrate. A crystal plane of a first surface of the semiconductor substrate, which is the first side surface of the first trench, is (111) plane. A crystal plane of a second surface of the semiconductor substrate, which is the bottom surface of the first trench, is (100) plane.
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 29/04 - Corps semi-conducteurs caractérisés par leur structure cristalline, p.ex. polycristalline, cubique ou à orientation particulière des plans cristallins
H01L 29/66 - Types de dispositifs semi-conducteurs
40.
LOGIC CIRCUIT DESIGN METHOD AND LOGIC CIRCUIT DESIGNING APPARATUS
A method of designing a semiconductor device. It can comprise interpreting a constraint defining a delay value from a timing constraint by inputting data defining a logic circuit and timing constraint data defining a timing constraint relating to the logic circuit, calculating the delay value that can applied to each path in the logic circuit, and verifying the logic circuit by detecting the delay value as a logic verification violation.
G06F 30/367 - Vérification de la conception, p.ex. par simulation, programme de simulation avec emphase de circuit intégré [SPICE], méthodes directes ou de relaxation
41.
SEMICONDUCTOR DEVICE, BATTERY PACK, METHOD OF CONTROLLING SEMICONDUCTOR DEVICE, AND CONTROL PROGRAMS
A semiconductor device, a battery pack, a method of controlling the semiconductor device, and a control program capable of accurately measuring a remaining capacity of a battery is provided. The semiconductor device includes: a current measurement circuit configured to measure a current value of a first current supplied from a battery to the semiconductor device that is a host device and a current value of a second current supplied from the battery to a load; and a computing circuit configured to calculate the remaining capacity of the battery, based on an accumulation value of the first current and an accumulation value of the second current in a period from start of discharging to end of discharging in the battery.
G01R 31/3828 - Dispositions pour la surveillance de variables des batteries ou des accumulateurs, p.ex. état de charge utilisant l’intégration du courant
H02J 7/00 - Circuits pour la charge ou la dépolarisation des batteries ou pour alimenter des charges par des batteries
A semiconductor substrate includes an n-type substrate region, an n-type first semiconductor region and a second semiconductor region disposed at different positions on the n-type substrate region, an n-type buried layer formed on the n-type first semiconductor region and on the second semiconductor region, a p-type third semiconductor region and a p-type fourth semiconductor region formed on the n-type buried layer and spaced apart from each other, and an n-type fifth semiconductor region that reaches an upper surface of the semiconductor substrate from the n-type buried layer. The n-type buried layer, the n-type first semiconductor region, and the n-type substrate region are present under the p-type third semiconductor region and the n-type fifth semiconductor region. A first transistor is formed in an upper portion of the p-type third semiconductor region, and a second transistor is formed in an upper portion of the p-type fourth semiconductor region.
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
43.
CAN COMMUNICATION CONTROLLER AND METHOD OF OPERATING CAN COMMUNICATION CONTROLLER
A CAN communication controller and a method of operating a CAN communication controller are disclosed. The CAN communication controller is for transmitting first and second types of frames wherein the first type of frame is used to transmit event-triggered communication data and the second type of frame is used to transmit best effort traffic data, the CAN communication controller configured, in response to transmitting a frame of the second type having a given identifier, to delay arbitration of a following frame of the second type having the given identifier, and not to delay arbitration of a frame of the first type.
A differential amplifier includes a first differential amplifier circuit as a first stage, a second differential amplifier circuit having a common mode feedback circuit in a second stage, and a feedback differential circuit configured to multiply a differential signal between a differential output of the first differential amplifier circuit and a differential input of the second differential amplifier circuit by a magnitude of a differential output of the common mode feedback circuit.
The semiconductor device includes a control unit having redundant processors, a memory storing target data, a secure memory storing a key used for encryption or decryption processing, an cryptographic unit, a secure processor instructing cryptographic processing to the cryptographic unit in response to a request from the control unit, a first bus coupled to the control unit, the memory, the cryptographic unit, and the secure processor, and a second bus coupled to the secure memory, the cryptographic unit, and the secure processor. The control unit communicates with the memory via a predetermined error detection mechanism, the cryptographic unit includes a plurality of cryptographic processors that independently perform cryptographic processing on target data using a key based on an instruction, and each of the plurality of cryptographic processors includes a data transfer unit that performs data transfer with the memory via the error detection mechanism.
G06F 21/62 - Protection de l’accès à des données via une plate-forme, p.ex. par clés ou règles de contrôle de l’accès
G06F 21/64 - Protection de l’intégrité des données, p.ex. par sommes de contrôle, certificats ou signatures
G06F 21/79 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du stockage de données dans les supports de stockage à semi-conducteurs, p.ex. les mémoires adressables directement
G06F 21/72 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du calcul ou du traitement de l’information dans les circuits de cryptographie
46.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device includes an n-type semiconductor substrate, a trench, and a gate electrode formed in the trench via a gate insulating film. An absolute value of a difference between a thickness of the gate insulating film formed on a corner portion of the trench and a thickness of the gate insulating film formed on the bottom portion of the trench is smaller than an absolute value of a difference between the thickness of the gate insulating film formed on the corner portion of the trench and a thickness of the gate insulating film formed on the sidewall portion of the trench.
H01L 29/739 - Dispositifs du type transistor, c.à d. susceptibles de répondre en continu aux signaux de commande appliqués commandés par effet de champ
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/66 - Types de dispositifs semi-conducteurs
An electric fuse including a fuse body and a fuse pad has a lamination structure of a polysilicon film and a cobalt silicide film. In the fuse body, a first portion having a first thickness and a second portion having a second thickness are formed. The first thickness is smaller than the second thickness. The polysilicon film is formed such that a thickness of the polysilicon film in the first portion becomes smaller than a thickness of the polysilicon film in the second portion.
H01L 23/525 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées avec des interconnexions modifiables
H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
48.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device with improved reliability is provided. The semiconductor device is characterized by its embodiments in that sloped portions are formed on connection parts between a pad and a lead-out wiring portion, respectively. This feature suppresses crack formation in a coating area where a part of the pad is covered with a surface protective film.
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/31 - Capsulations, p.ex. couches de capsulation, revêtements caractérisées par leur disposition
H01L 21/48 - Fabrication ou traitement de parties, p.ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes
H01L 21/56 - Capsulations, p.ex. couches de capsulation, revêtements
H01L 21/78 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels
H01L 21/66 - Test ou mesure durant la fabrication ou le traitement
This invention provides a placement area with an enlarged bump pitch while avoiding the risk of underfill void generation in the bump process.
This invention provides a placement area with an enlarged bump pitch while avoiding the risk of underfill void generation in the bump process.
The number of bumps is not changed, but the bump pitch at the center is arranged in parallel with the drying direction of the flip-chip process in the drying direction, and an arrangement area in which n rows are enlarged by +b(μm) bump pitch is made, and the chip area is finely adjusted.
This invention provides a placement area with an enlarged bump pitch while avoiding the risk of underfill void generation in the bump process.
The number of bumps is not changed, but the bump pitch at the center is arranged in parallel with the drying direction of the flip-chip process in the drying direction, and an arrangement area in which n rows are enlarged by +b(μm) bump pitch is made, and the chip area is finely adjusted.
According to the invention, with respect to the dry air direction after flux cleaning, the power of the dry air does not change for creating a minute bump enlarged area parallel to the air in the central portion.
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 21/56 - Capsulations, p.ex. couches de capsulation, revêtements
A semiconductor device includes a crystal oscillator circuit, a first noise application circuit, and a second noise application circuit. The first noise application circuit is connected to the crystal oscillator circuit and is configured to drive a crystal resonator by selectively applying initial noises of opposite phases to a first external terminal and a second external terminal. The second noise application circuit applies a second noise to the first external terminal by amplifying a signal at the first external terminal and returning the amplified signal to the first external terminal, thereby driving an oscillation amplifier and a crystal resonator of the crystal oscillator circuit and shortening a start-up time of the crystal oscillator circuit.
H03B 5/36 - Production d'oscillation au moyen d'un amplificateur comportant un circuit de réaction entre sa sortie et son entrée l'élément déterminant la fréquence étant un résonateur électromécanique un résonateur piézo-électrique l'élément actif de l'amplificateur comportant un dispositif semi-conducteur
A semiconductor device according to an embodiment includes a level detection unit that validates a level detection signal LD when a value indicated by stream data exceeds a threshold condition value, a ring buffer that cyclically stores internal data generated from the stream data in a storage area that is set within a predetermined address range, a data processing unit that operates with a bus clock and performs data processing using the internal data acquired from the ring buffer, and an address adjustment unit that adjusts a read address indicating a read start position of the ring buffer to a position that becomes a predetermined difference from a write address of the ring buffer at that time in accordance with a start of generation of the bus clock, and generates a bus clock during a period in which the level detection signal LD is valid.
G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p.ex. circuits de commande E/S de données, mémoires tampon de données E/S
G11C 7/22 - Circuits de synchronisation ou d'horloge pour la lecture-écriture [R-W]; Générateurs ou gestion de signaux de commande pour la lecture-écriture [R-W]
52.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device having a semiconductor substrate, a BOX film on the semiconductor substrate, a semiconductor layer on the BOX film, a first trench penetrated through the semiconductor layer and reached to the first insulating film, a first insulating film covering a side surface of the first trench and in contact with an upper surface of the BOX film at a bottom of the first trench, a second trench formed at the bottom of the first trench such that the second trench penetrates through the first insulating film and reached in the BOX film, a second insulating film filled in the first trench and the second trench. A bottom surface of the second trench is located in the BOX film below an interface between the semiconductor layer and the BOX film, and a void is located in the second insulating film at the same height the interface.
H01L 27/12 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant autre qu'un corps semi-conducteur, p.ex. un corps isolant
53.
VISUAL INSPECTION APPARATUS AND VISUAL INSPECTION METHODS
A visual inspection apparatus includes a stage on which a FCBGA type semiconductor package having a lid is placed, a camera located above the stage, a coaxial illumination device located between the camera and the stage, an oblique illumination device located between the camera and the stage, and a control device. The control device is configured to irradiate the FCBGA type semiconductor package with illumination lights by the coaxial illumination device and the oblique illumination device, capture the FCBGA type semiconductor package by the camera to obtain the captured image, integrate a number of pixels of a predetermined pixel value by a binarization process of the captured image to obtain a determination value, and compare the determination value with a predetermined value to determine a non-defective product or a defective product.
A semiconductor device includes a first metal film forming an uppermost layer wiring that has a bonding pad. A concentration of impurities at a crystal grain boundary of the first metal film is higher than a concentration of impurities in crystal grains in the first metal film. The maximum grain size of crystal grains included in the first metal film is less than 5 μm.
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
A semiconductor manufacturer generates a manufacturer encryption key and a manufacturer decryption key corresponding to the manufacturer decryption key, installs the manufacturer decryption key in a semiconductor device, and provides a customer with the manufacturer decryption key, the customer generates a customer encryption key and a customer decryption key corresponding to the customer decryption key, decrypts, by the customer decryption key, a customer key to be installed in the semiconductor device, and supplies the encrypted customer key to the semiconductor manufacturer, the semiconductor manufacturer encrypts the supplied customer key by the manufacturer encryption key without decryption, and supplies the encrypted customer key to the customer, the customer decrypts the customer key by the customer decryption key, and installs the decrypted customer key in the semiconductor device, and in the semiconductor device, the installed customer key is decrypted by the manufacturer decryption key installed by the semiconductor manufacturer.
H04L 9/14 - Dispositions pour les communications secrètes ou protégées; Protocoles réseaux de sécurité utilisant plusieurs clés ou algorithmes
H04L 9/30 - Clé publique, c. à d. l'algorithme de chiffrement étant impossible à inverser par ordinateur et les clés de chiffrement des utilisateurs n'exigeant pas le secret
A cryptographic key installation method of installing a customer key in a semiconductor device, wherein the semiconductor device includes a decryption functional unit that has a secret key installed therein in advance, and when the customer key encrypted by a public key corresponding to the secret key is installed, decrypts the encrypted customer key by the secret key installed in advance to generate a customer key, wherein an encryption device on a user side that uses the semiconductor device encrypts the customer key by the public key, and generates the encrypted customer key, and wherein a key installation device on the user side installs the encrypted customer key in the semiconductor device.
G06F 21/72 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du calcul ou du traitement de l’information dans les circuits de cryptographie
57.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device includes a chip mounting portion and a semiconductor chip provided on the chip mounting portion via a conductive adhesive material. Here, a planar shape of the semiconductor chip is a quadrangular shape. Also, in plan view, a plurality of thin portions is formed at a plurality of corner portions of the semiconductor chip, respectively. Also, the plurality of thin portions respectively formed at the plurality of corner portions of the semiconductor chip is spaced apart from each other. Further, thickness of each of the plurality of thin portions is smaller than a thickness of the semiconductor chip other than the plurality of the thin portions.
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/58 - Dispositions électriques structurelles non prévues ailleurs pour dispositifs semi-conducteurs
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 21/78 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels
H01L 21/306 - Traitement chimique ou électrique, p.ex. gravure électrolytique
58.
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
A source pad electrically coupled with a source of a MOSFET of a semiconductor chip and located at a position below a lead in cross-sectional view is electrically connected with the lead for source via a conductive member bonded to the source pad and a wire bonded to the conductive member.
H01L 23/31 - Capsulations, p.ex. couches de capsulation, revêtements caractérisées par leur disposition
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 21/56 - Capsulations, p.ex. couches de capsulation, revêtements
The semiconductor device has the main surface, the semiconductor substrate having the first impurity region formed on the main surface, the first electrode formed on the main surface having the first impurity region, the insulating film formed on the main surface such that surround the first electrode, the second electrode formed on the insulating film such that spaced apart from the first electrode and annularly surround the first electrode, and the semi-insulating film. The first electrode has the outer peripheral edge portion. The semi-insulating film is continuously formed from on the outer peripheral edge portion to on the second electrode. The outer peripheral edge portion includes the first corner portion. The second electrode has the second corner portion facing the first corner portion. The semi-insulating film on the insulating film is removed between the first corner and the second corner portion.
H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/739 - Dispositifs du type transistor, c.à d. susceptibles de répondre en continu aux signaux de commande appliqués commandés par effet de champ
An improved power MOSFET of a split gate structure including a gate electrode and a field plate electrode in a trench is disclosed. The improved power MOSFET includes a field plate electrode FP formed at a lower portion of a trench TR and a gate electrode GE formed an upper portion of the trench TR. The field plate electrode FP further includes a contact portion FPa which is formed at the upper portion of the trench TR to provide a source potential. The gate electrode GE further includes a connecting portion GEa at the both sides of the contact portion FPa in the trench TR. The connecting portion GEa electrically connects between one portion of the gate electrode GE at a region 2A side and the other portion of the gate electrode GE at a region 2A′ side.
A semiconductor device includes a trench emitter electrode located at a boundary between one end of an active cell region and an inactive cell region, a trench gate electrode located at a boundary between the other end of the active cell region and the inactive cell region, an end trench gate electrode connected to one end of the trench gate electrode, and an end trench emitter electrode connected to one end of the trench emitter electrode. A hole barrier region of a first conductivity type is provided under a body region of a second conductivity type between the end trench gate electrode and the end trench emitter electrode in a plan view. A body region in the active cell region and a body region in the inactive cell region are connected to each other by a body region between the end trench gate electrode and the end trench emitter electrode.
H01L 29/739 - Dispositifs du type transistor, c.à d. susceptibles de répondre en continu aux signaux de commande appliqués commandés par effet de champ
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
H01L 29/66 - Types de dispositifs semi-conducteurs
62.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A dielectric layer has a first opening exposing a surface of a first conductive layer and a second opening exposing a surface of a second conductive layer and having an opening area smaller than an opening area of the first opening. A material of the surface of the second conductive layer exposed from the second opening is different from a material of the surface of the first conductive layer exposed from the first opening, and includes aluminum.
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
63.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
An improved structure and a manufacturing method of a vertical type power MOSFET having a super junction configuration is disclosed. The improved structure and the manufacturing method of the vertical type power MOSFET comprising: a step of preparing a semiconductor substrate SB including an n-type semiconductor layer SL and a p-type epitaxial layer EP on the semiconductor layer SL; a step of forming a trench GT in the p-type epitaxial layer EP by using an etching mask with a predetermined opening width; and a step of introducing an n-type impurity into a bottom portion of the trench GT using the etching mask with the predetermined opening width, whereby forming an n-type column NC at the bottom of trench GT and reaching the semiconductor layer SL.
A method of manufacturing a semiconductor device includes: a grind step of forming a small thickness portion and a large thickness portion surrounding the small thickness portion in plan view by grinding a back surface of a semiconductor wafer; a preparation step of preparing a wafer holding member including a wafer placement surface and a back surface opposite to the wafer placement surface and having a larger thickness than a difference between a thickness of the large thickness portion and a thickness of the small thickness portion; and a placement step of placing the semiconductor wafer on the wafer holding member so that the small thickness portion of the semiconductor wafer and the wafer placement surface of the wafer holding member are in contact with each other on the back surface side of the semiconductor wafer.
H01L 21/683 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitement; Appareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants pour le maintien ou la préhension
H01L 21/66 - Test ou mesure durant la fabrication ou le traitement
H01L 21/304 - Traitement mécanique, p.ex. meulage, polissage, coupe
65.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
Wirings next to each other spaced apart by a first distance are formed in the uppermost layer of a multilayer wiring layer formed on a semiconductor substrate. A protective film covers upper surfaces and side surfaces of the wirings. The protective films formed on the side surfaces of the wirings are spaced apart from each other. The protective film is formed of an inorganic dielectric film. A thickness of the protective film formed on the upper surfaces of the wirings is larger than a thickness of the protective film formed on the side surfaces of the wirings.
H01L 23/31 - Capsulations, p.ex. couches de capsulation, revêtements caractérisées par leur disposition
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 21/56 - Capsulations, p.ex. couches de capsulation, revêtements
66.
SOLID-STATE IMAGE SENSOR, IMAGING DEVICE, AND AD CONVERTER
A solid-state image sensor includes a buffer circuit, and an AD conversion circuit. The buffer circuit is connected to a first pixel and a second pixel of a plurality of pixels. The AD conversion circuit converts a voltage signal from the buffer circuit into a digital signal. The buffer circuit includes a voltage holding circuit connected to the first pixel, a voltage holding circuit connected to the second pixel, and a switch circuit. The switch circuit selectively switches the voltage holding circuit which outputs a voltage signal to the AD conversion circuit between the voltage holding circuits. The buffer circuit carries out an operation of holding a voltage signal of the first pixel in the voltage holding circuit and an operation of holding a voltage signal of the second pixel in the voltage holding circuit in parallel with each other.
A semiconductor device includes an n-type semiconductor substrate, a trench, a gate electrode formed in the trench via the gate insulating film, a p-type base region formed in the semiconductor substrate, and an n-type emitter region formed in the base region. The trench extends in a Y direction, in a plan view. Adjacent ones of a plurality of emitter regions are formed to be spaced apart from each other by a distance, along the Y direction. The distance is wider than ⅕ of a width of each of the emitter regions in the Y direction and narrower than the width.
H01L 29/739 - Dispositifs du type transistor, c.à d. susceptibles de répondre en continu aux signaux de commande appliqués commandés par effet de champ
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/66 - Types de dispositifs semi-conducteurs
68.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
In a memory region, a memory-region first portion in which no raised epitaxial layer is formed, a memory-region second portion in which a first raised epitaxial layer is formed, and a memory-region third portion in which a second raised epitaxial layer is formed are defined. In the memory-region first portion, a first-diffusion-layer first portion of a memory transistor and a second-diffusion-layer first portion of a select transistor are formed. A first-diffusion-layer second portion of the memory transistor is formed in the first raised epitaxial layer. A second-diffusion-layer second portion of the select transistor is formed in the second raised epitaxial layer.
H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p.ex. NON-ET
H10B 43/40 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région de circuit périphérique
69.
METAL FILM AND MANUFACTURING METHOD OF THE METAL FILM, AND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE
A metal film, a manufacturing method of the metal film, semiconductor device, and a manufacturing method of semiconductor device are provided with high crack resistance (higher hardness) during wire bonding. The Metal film has first metal crystal grains, and the second metal crystal grains. Each of the first metal crystal grains has dislocations. Each of the second metal crystal grains has no dislocations. The number of the first metal crystal grains having the dislocations is larger than the number of the second metal crystal grains having no dislocations.
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
A first P-type transistor and a second P-type transistor are connected in series between a power supply terminal and an output terminal. A first N-type transistor and a second N-type transistor are connected between a ground terminal and a power supply terminal. The second N-type transistor and the second P-type transistor are complementarily turned on and off in accordance with an input signal. A gate voltage control circuit changes at least one of the gate voltage of the P-type transistor whose drain is electrically connected to the output terminal and the gate voltage of the N-type transistor by following the output voltage VOUT of the output terminal while keeping the P-type transistor or the N-type transistor on-states.
H03K 17/56 - Commutation ou ouverture de porte électronique, c. à d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs
71.
SEMICONDUCTOR DEVICE INCLUDING A CIRCUIT FOR TRANSMITTING A SIGNAL
Reliability of a semiconductor device is improved. The semiconductor device includes a wiring substrate, a semiconductor chip and a capacitor mounted on the upper surface of the wiring substrate, and a lid formed of a metallic plate covering the semiconductor chip and the wire in substrate. The semiconductor chip is bonded to the lid via a conductive adhesive layer, and the capacitor, which is thicker than the thickness of the semiconductor chip, is disposed in the cut off portion provided in the lid, and is exposed from the lid.
H01L 25/16 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types couverts par plusieurs des groupes principaux , ou dans une seule sous-classe de , , p.ex. circuit hybrides
H01L 23/367 - Refroidissement facilité par la forme du dispositif
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/498 - Connexions électriques sur des substrats isolants
A semiconductor device capable of increasing readout margin in a nonvolatile resistive random access memory is provided. A clamping circuit applies fixed potential to each of a memory element and a reference resistive element. A pre-charge circuit pre-charges first and second nodes to power-source potential. A sense amplifier amplifies the potential difference between the potential of the first node and the potential of the second node generated after a discharge period based on cell current and reference current after pre-charging made by the pre-charge circuit. A third node is coupled to the first and second nodes through a capacitor. An electric-charge supply circuit is connected to the third node, and supplies electric charge to the third node in the discharge period.
G11C 11/16 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments magnétiques utilisant des éléments dans lesquels l'effet d'emmagasinage est basé sur l'effet de spin
G11C 5/08 - Dispositions pour interconnecter électriquement des éléments d'emmagasinage pour interconnecter des éléments magnétiques, p.ex. des noyaux toroïdaux
G11C 7/06 - Amplificateurs de lecture; Circuits associés
73.
SEMICONDUCTOR DEVICE AND POWER SUPPLY CONTROL PROCESSING METHOD FOR CONTROL CIRCUIT OF SEMICONDUCTOR DEVICE
A semiconductor device includes a first regulator electrically connected to a first power supply line, a second regulator electrically connected to a second power supply line, a control circuit configured to control the first and second regulators, and at least two functional circuit modules electrically connectable to the first power supply line and the second power supply line. When all the functional circuit modules are set to a power-on state (active mode), the control circuit controls the first regulator to output a voltage to the first power supply line and the second regulator to output a voltage to the second power supply line, and when some functional circuit modules are set to a power-off state (standby mode), the control circuit controls the first regulator to output a voltage to the first power supply line and the second regulator not to output a voltage to the second power supply line.
H03K 19/00 - Circuits logiques, c. à d. ayant au moins deux entrées agissant sur une sortie; Circuits d'inversion
H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
74.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device includes a wiring layer, a dielectric layer covering the wiring layer, a thin film resistor provided on the dielectric layer, and a plug electrode connecting the thin film resistor to the wiring layer. The plug electrode includes a barrier layer and a buried layer. The buried layer is configured by the filling portion filling a region surrounded by a first incline surface, and an extension portion extending from the filling portion along a second incline surface. The thin film resistor is in contact with the filling portion and the extension portion of the plug electrode. A second incline angle between the second incline surface and a main surface of a semiconductor substrate is smaller than a first incline angle between the first incline surface and the main surface of the semiconductor substrate.
H01L 29/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails des corps semi-conducteurs ou de leurs électrodes
H01C 7/00 - Résistances fixes constituées par une ou plusieurs couches ou revêtements; Résistances fixes constituées de matériau conducteur en poudre ou de matériau semi-conducteur en poudre avec ou sans matériau isolant
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01C 17/12 - Appareils ou procédés spécialement adaptés à la fabrication de résistances adaptés pour déposer en couche le matériau résistif sur un élément de base par des techniques de film mince par pulvérisation
A semiconductor device includes: a first chip mounting portion; a second chip mounting portion; a first semiconductor chip mounted on the first chip mounting portion; second and third semiconductor chips mounted on the second chip mounting portion; and a sealing body for sealing them. Here, the third semiconductor chip includes a first coil and a second coil that are magnetically coupled to each other. Also, the first coil is electrically connected with a first circuit formed in the first semiconductor chip, and the second coil is electrically connected with a second circuit formed in the second semiconductor chip. Also, in cross-sectional view, the second coil is located closer to the second chip mounting portion than the first coil. Further, a power consumption during an operation of the second semiconductor chip is greater than a power consumption during an operation of the first semiconductor chip.
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs sous-groupes différents du même groupe principal des groupes , ou dans une seule sous-classe de ,
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
A clamp element 46 applies a fixed potential to a bit line BL at a time of a readout operation. A reference current source RCS generates a reference current Iref. An offset current source OCS1 is activated at a time of a readout operation for an OTP cell OTPC, and at a time of being activated, generates an offset current Iof1 to be subtracted from a cell current Icel. At the time of the readout operation for the OTP cell OTPC, the sense amplifier SA detects a magnitude relationship between the reference current Iref and a readout current Ird obtained by subtracting the offset current Iof1 from the cell current Icel.
G11C 11/16 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments magnétiques utilisant des éléments dans lesquels l'effet d'emmagasinage est basé sur l'effet de spin
According to one embodiment, an A/D converter includes a successive approximation algorithm setting register that stores a plurality of successive approximation algorithms, an algorithm selection unit that selects a predetermined successive approximation algorithm from the plurality of successive approximation algorithms, a control circuit that generates a comparison value based on the selected predetermined successive approximation algorithm, a DAC that generates a comparison voltage from the comparison value, and a comparator that compares an analog input voltage with the comparison voltage. The control circuit generates a comparison value from a result of the comparison made by the comparator based on the selected predetermined successive approximation algorithm, and converts an analog input voltage into a digital signal from the result of the comparison made by the comparator the number of times equal to the number of bits of the digital signal.
H03M 1/46 - Valeur analogique comparée à des valeurs de référence uniquement séquentiellement, p.ex. du type à approximations successives avec convertisseur numérique/analogique pour fournir des valeurs de référence au convertisseur
78.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device includes a lead, a semiconductor substrate, a back-surface electrode provided between the semiconductor substrate and the lead, and a solder layer configured to connect the back-surface electrode and the lead. The back-surface electrode includes a silicide layer formed on a back surface of the semiconductor substrate, a bonding layer formed on the lead, a barrier layer formed on the bonding layer, and a stress relaxation layer formed between the silicide layer and the barrier layer. The stress relaxation layer is made of a first metal film containing aluminum as a main component or a second metal film containing gold, silver, or copper as a main component.
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/485 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes formées de couches conductrices inséparables du corps semi-conducteur sur lequel elles ont été déposées formées de structures en couches comprenant des couches conductrices et isolantes, p.ex. contacts planaires
An angle error correction device includes an actual rotation angle measurement circuit that converts a rotation angle information of a rotation angle detection target to an angle counter value for each predetermined angle; an actual speed calculator that calculates an actual rotation speed for each predetermined angle from the angle counter value; a curve interpolation circuit that generates a curve interpolation equation from the angle counter value; an ideal speed estimator that calculates an estimated ideal rotation speed for each predetermined angle using the curve interpolation equation; an angle error detector that calculates an angle error for each predetermined angle by integrating an angle ripple ratio determined by the actual rotation speed and the estimated ideal rotation speed; an angle error table in which the angle error calculated by the angle error detector is stored; and a correction circuit that corrects the rotation angle information using the angle error table.
A semiconductor device includes a processor unit, a memory storing a boot program, a reset controller and an address check unit. The reset controller controls a reset for the processor unit based on a reset request and outputs a boot address for the boot program to be executed after reset release to the processor unit. The address check unit performs a tampering check for the boot address output from the reset controller and outputs a boot address error signal based on a tampering check result.
G06F 21/75 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du calcul ou du traitement de l’information par inhibition de l’analyse de circuit ou du fonctionnement, p.ex. pour empêcher l'ingénierie inverse
A method of manufacturing a semiconductor device includes: forming a silicon oxide film covering each of a first main surface and a second main surface of a semiconductor substrate; forming a redistribution wiring on the first main surface side of the semiconductor substrate; and grinding the second main surface of the semiconductor substrate. This grinding step is performed in a state in which a thickness of the silicon oxide film positioned on the second main surface is equal to or larger than 10 nm and equal to or smaller than 30 nm.
In a semiconductor substrate, an n-type source region, an n-type drain region, a first p-type semiconductor region, and a second p-type semiconductor region surrounding the n-type source region and the first p-type semiconductor region are formed. A gate electrode is formed on the semiconductor substrate between the n-type source region and the n-type drain region via a dielectric film GF. In the semiconductor substrate, a recessed portion is formed so as to penetrate through the n-type source region, and the first p-type semiconductor region is formed under the recessed portion.
A technique for enhancing reliability is provided. A semiconductor device includes a main device which operates in a delayed lockstep mode, a sub device which operates in parallel to the main device in a delayed lockstep mode, a delay circuit which delays an output of the main device, a switching circuit which switches the main device to the sub device according to failure information of the main device.
H03K 5/131 - Dispositions ayant une sortie unique et transformant les signaux d'entrée en impulsions délivrées à des intervalles de temps désirés contrôlées numériquement
G06F 11/16 - Détection ou correction d'erreur dans une donnée par redondance dans le matériel
A semiconductor device includes a phase interpolation circuit including an N-bit current digital-analog conversion circuit, a switch circuit, a capacitive element, an inverter, and a control logic circuit. The control logic circuit detects an end of a phase interpolation operation by using an output result of the inverter and outputs a first control signal for turning off the current digital-analog conversion circuit. Also, the control logic circuit detects the end of the phase interpolation operation by using the output result of the inverter and outputs a second control signal for turning off the inverter.
H03L 7/099 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase concernant principalement l'oscillateur commandé de la boucle
H03L 7/197 - Synthèse de fréquence indirecte, c. à d. production d'une fréquence désirée parmi un certain nombre de fréquences prédéterminées en utilisant une boucle verrouillée en fréquence ou en phase en utilisant un diviseur de fréquence ou un compteur dans la boucle une différence de temps étant utilisée pour verrouiller la boucle, le compteur comptant entre des nombres variables dans le temps ou le diviseur de fréquence divisant par un facteur variable dans le temps, p.ex. pour obtenir une division de fréquence
During the scan testing, the peak power that instantaneously occurs in the shift operation is reduced.
During the scan testing, the peak power that instantaneously occurs in the shift operation is reduced.
The semiconductor device of the present invention, the phase of the ATE clock signal (ATE_Clk) is shifted in several variations, by external control, as set in the scan testing scan chain has a clock operating unit for distributing the phase shifted clocks.
A semiconductor device includes a plurality of processors capable of executing a plurality of virtual machines and a cache memory. Each of the plurality of virtual machines executes a different operating system from each other. A hypervisor sets allocation information so as to allocate ways of the cache memory which can be used by the virtual machine. When outputting a memory access request, each of the processors outputs virtual machine identification in association with the information memory access request. When the memory access request is not a cache hit, the cache memory selects a way to be replaced data based on the virtual machine identification information and the allocation information.
G06F 9/455 - Dispositions pour exécuter des programmes spécifiques Émulation; Interprétation; Simulation de logiciel, p.ex. virtualisation ou émulation des moteurs d’exécution d’applications ou de systèmes d’exploitation
G06F 12/0802 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p.ex. mémoires cache
A debug apparatus for performing allocation of target programs in which temperature is uniformized is provided. The debug apparatus receives temperature data measured by temperature sensors from a semiconductor device. The debug apparatus determines, as an analysis result of the temperature data, a CPU where the number of target programs executed is to be decreased and a CPU where the number of target programs executed is to be increased. The debug apparatus changes allocation of the target programs executed by a plurality of CPUs in the semiconductor device based on the analysis result of the temperature data.
A semiconductor device includes a receiving terminal for receiving a signal transmitted through a signal transmission line, a reference plane voltage terminal connected to a refence plane as a refence for the signal on the signal transmission line and a voltage generating circuit configured to generate a refence plane voltage to be supplied to the reference plane voltage terminal based on the signal received by the receiving terminal.
To manufacture a semiconductor device, a first heat treatment for curing a first adhesive material of a conductive paste type is performed, after a semiconductor chip is mounted on a die pad of a lead frame via the first adhesive material. After that, a metal plate is disposed on a pad of the semiconductor chip such that the metal plate faces the pad of the semiconductor chip via a second adhesive material of a conductive paste type, and a second heat treatment is performed for curing each of the first adhesive material and the second adhesive material. A time of the first heat treatment is less than a time of the second heat treatment. After the first adhesive material is cured by the first heat treatment, the first adhesive material is further cured by the second heat treatment.
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/31 - Capsulations, p.ex. couches de capsulation, revêtements caractérisées par leur disposition
H01L 21/56 - Capsulations, p.ex. couches de capsulation, revêtements
H02M 7/00 - Transformation d'une puissance d'entrée en courant alternatif en une puissance de sortie en courant continu; Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant alternatif
Increasing in a contact-resistance between a trench gate lead-out electrode and a gate lead-out contact member is suppressed. It is assumed that a natural oxidation film is formed in the polysilicon film when the trench gate lead-out electrode is formed. In case of the natural oxidation film is formed, a desired etching process is performed so that the natural oxidation film does not protrude beyond the upper surface of the trench gate lead-out electrode.
H01L 21/3213 - Gravure physique ou chimique des couches, p.ex. pour produire une couche avec une configuration donnée à partir d'une couche étendue déposée au préalable
H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
H01L 21/3065 - Gravure par plasma; Gravure au moyen d'ions réactifs
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
A semiconductor device capable of reducing power consumption is provided. A group controller detects a zero weight parameter having a zero value among “n×m” weight parameters to be transferred to a weight parameter buffer. Then, when receiving the zero weight parameter as its input, the group controller exchanges the “n×m” weight parameters to be transferred to the weight parameter buffer so that all multiplication results of the “n” multipliers included in a target multiplier group that is one of the “m” multiplier groups are zero. The group controller controls the target multiplier group to be disabled, and exchanges the “n×m” pixel data to be transferred to the data input buffer, based on the exchange of the “n×m” weight parameters.
A semiconductor device includes a first electrode and a second electrode configuring a MIM capacitor. The first electrode includes a first via plug extending along a first direction. The second electrode includes a second lower wiring extending along the first direction and arranged side by side with the first via plug in a second direction. A length of the first via plug in the first direction is larger than a length of the first via plug in the second direction. A length of the second lower wiring in the first direction is larger than a length of the second lower wiring in the second direction. A length of the first via plug in a third direction is larger than a length of the second lower wiring in the third direction.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
A package construction includes: a die pad, and a suspension lead remaining portion connected to the die pad. Here, an offset portion is provided from a peripheral edge portion of the die pad to the suspension lead remaining portion. Also, the suspension lead remaining portion has: a first end portion connected to the die pad, and a second end portion opposite the first end portion. Further, the second end portion of the suspension lead remaining portion is exposed from the side surface of the sealing body at a position spaced apart from each of the upper surface and the lower surface.
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 23/498 - Connexions électriques sur des substrats isolants
A semiconductor device includes a semiconductor package having a differential signal terminal pair, and a wiring board. The wiring board includes a first and a second signal transmission line and a reference potential plane. The first and the second signal transmission line is formed in a first conductive layer and connected to the differential signal terminal pair. The reference potential plane includes a conductive pattern formed in a different conductive layer from the first conductive layer. The conductive pattern includes a first and a second region overlapped with the first and the second signal transmission line in plan view, respectively. The conductive pattern has a plurality of openings in the first and the second region. An area of a first conductive portion of the reference potential plane in the first region becomes equal to an area of a second conductive portion of the reference potential plane in the second region.
A semiconductor device includes: a die pad having an upper surface facing a semiconductor chip, a metal film formed on the upper surface, and a bonding material formed so as to cover the metal film. Here, the upper surface has: a first region overlapping the semiconductor chip, a second region not overlapping the semiconductor chip, a third region included in the first region and covered with the metal film, and a fourth region included in the first region and adjacent to the third region and also not covered with the metal film. Also, the semiconductor chip is mounted on the die pad such that a center of the semiconductor chip overlaps the third region. Further, an area of the third region is greater than or equal to 11% of an area of the first region, and less than or equal to 55% of the area of the first region.
H01L 23/31 - Capsulations, p.ex. couches de capsulation, revêtements caractérisées par leur disposition
H01L 21/56 - Capsulations, p.ex. couches de capsulation, revêtements
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
A semiconductor device includes a first semiconductor chip, a second semiconductor chip, and a redistribution layer. The first semiconductor chip and the second semiconductor chip are arranged spaced apart from each other in a second direction orthogonal to a first direction. The redistribution layer is disposed across over the first semiconductor chip and the second semiconductor chip. The redistribution layer includes a first inductor and a second inductor. The first inductor and the second inductor are spaced apart and face each other in a third direction orthogonal to the first direction and the second direction. The first inductor and the second inductor are electrically connected to the first semiconductor chip and the second semiconductor chip, respectively. The first inductor and the second inductor are wound across over the first semiconductor chip and the second semiconductor chip in a plane orthogonal to the third direction.
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/31 - Capsulations, p.ex. couches de capsulation, revêtements caractérisées par leur disposition
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 21/48 - Fabrication ou traitement de parties, p.ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes
H01L 21/56 - Capsulations, p.ex. couches de capsulation, revêtements
97.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A second gate electrode is adjacent, in a Y direction, to a first tip of a semiconductor layer in a first active region such that a protruding distance of a second tip of the second gate electrode protruded, in a X direction, from the semiconductor layer in the first active region is greater than or equal to 0. Also, the first tip of the semiconductor layer in the first active region is covered with a second sidewall spacer. Further, a first epitaxial layer and the second gate electrode are electrically connected to each other via a first shared contact plug formed so as to across the first epitaxial layer, the second sidewall spacer and the second gate electrode.
H01L 27/12 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant autre qu'un corps semi-conducteur, p.ex. un corps isolant
H10B 10/00 - Mémoires statiques à accès aléatoire [SRAM]
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
98.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
Semiconductor device has a cell region and a peripheral region, and has a drift layer, a trench, an gate dielectric film on an inner wall of the trench, a gate electrode, and a p-type first semiconductor region below the trench in the cell region on a semiconductor substrate. Further, in the peripheral region on the semiconductor substrate, p-type second semiconductor region is formed in the same layer as the p-type first semiconductor region. a width of the p-type first semiconductor region and a width of the p-type second semiconductor region are different.
H01L 29/16 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
A semiconductor device includes: a first semiconductor chip mounted on a chip mounting portion via a first bonding material; and a second semiconductor chip mounted on the first semiconductor chip. Here, the first semiconductor chip has: a protective film located in an uppermost layer; and a first pad electrode exposed from the protective film at an inside of a first opening portion of the protective film. Also, the second semiconductor chip is mounted on a conductive material, which is arranged on the first pad electrode of the first semiconductor chip, via a second bonding material of an insulative property.
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/31 - Capsulations, p.ex. couches de capsulation, revêtements caractérisées par leur disposition
H01L 25/16 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types couverts par plusieurs des groupes principaux , ou dans une seule sous-classe de , , p.ex. circuit hybrides
Semiconductor device has a regulator circuit having an even number of switching regulators that generate output power from an input power supply and a power management IC that controls the output potential generated by the switching regulator. semiconductor device is characterized in that a group of half of the even number of switching regulators is arranged on a first surface of semiconductor device system board, and a group of switching regulators, which is the remaining half, is arranged on a second surface that is in front-back relation with the first surface. This semiconductor device reduces semiconductor device board-area (pattern-resource).
H01L 25/16 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types couverts par plusieurs des groupes principaux , ou dans une seule sous-classe de , , p.ex. circuit hybrides
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H02M 3/155 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs
