Implementations of semiconductor packages, such as power modules used in automobiles, may include: a first substrate (16, 50) having a first dielectric layer (20, 54) coupled between a first metal layer (22, 56) and a second metal layer (24, 58); a second substrate (18, 60) having a second dielectric layer (30, 60) coupled between a third metal layer (32, 62) and a fourth metal layer (34, 64). A first die (40, 74) may be coupled with a first electrical spacer (42, 78) coupled in a space between and coupled with the first substrate (16, 50) and the second substrate (18, 60) and a second die (44, 76) may be coupled with a second electrical spacer (46, 80) coupled in a space between and coupled with the first substrate (16, 50) and the second substrate (18, 60). The first die (40) and the second die (44) may be positioned in opposite orientations, with the first electrical spacer (42) coupled with the third metal layer (32), the first die (40) coupled with the second metal layer (24), the second electrical spacer (46) coupled with the second metal layer (24) and the second die (44) coupled with the third metal layer (32). Alternatively, the first die (74) and the second die (76) may be in a similar orientation both coupled to the third metal layer (62), both the first electrical spacer (78) and the second electrical spacer (80) being coupled with the second metal layer (58). The extension portion of the second dielectric layer (30, 60) and the extension portion of the first dielectric layer (20, 54) may include substantially similar lengths or the extension portion of the second dielectric layer (30, 60) may extend beyond the extension portion of the first dielectric layer (20, 54) and the lengths of the third and the fourth metal layers (32, 34, 62, 64) may be longer than the lengths of the first and the second metal layers (22, 24, 56, 58). The substrates may be biased relative to a molding apparatus by one or more springs. Flexible interconnection supports/members may be used to provide an interconnect between a first substrate and a second substrate, flexible members may also be used between a die and a substrate. The flexible members may be spacers for the electrical interconnects. They may also integrate a spring biasing function which can be a spiral spring, a sponge-like structure or a clip of various shapes.
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 23/373 - Refroidissement facilité par l'emploi de matériaux particuliers pour le dispositif
H01L 21/56 - Capsulations, p.ex. couches de capsulation, revêtements
2.
HYBRID GATE DIELECTRICS FOR SEMICONDUCTOR POWER DEVICES
In a general aspect, a power semiconductor device can include a silicon carbide (SiC) substrate and a SiC epi-layer disposed on the SiC substrate. The device can also include a well region disposed in the SiC epi-layer and a source region disposed in the well region. The device can further include a gate trench disposed in the SiC epi-layer and adjacent to the source region, the gate trench having a depth that is greater than a depth of the well region and is less than a depth of the SiC epi-layer. The device can also include a hybrid gate dielectric disposed on a sidewall of the gate trench and a bottom surface of the gate trench. The hybrid gate dielectric can include a first high-k dielectric material and a second high-k dielectric material. The device can also include a conductive gate electrode disposed on the hybrid gate dielectric.
H01L 29/24 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des matériaux semi-conducteurs inorganiques non couverts par les groupes , , ou
H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
3.
INTEGRATED WIRE BONDER AND 3D MEASUREMENT SYSTEM WITH DEFECT REJECTION
An apparatus comprises a wire bonder system including a wire bonding device (210), a measuring device (215) and a rejection device (220). The wire bonding device (210) is configured to attach wire bond type electrical interconnect to an electronic assembly. A wire bond is formed between a first semiconductor device and a second electronic device to form at least a portion of the electronic assembly. The measuring device (215) is configured to perform a three dimensional measurement associated with a wire bond, and the rejection device (220) is configured to identify an electronic assembly for rejection according to the three dimensional wire bond measurement.
H01L 21/67 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitement; Appareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants
H01L 21/60 - Fixation des fils de connexion ou d'autres pièces conductrices, devant servir à conduire le courant vers le ou hors du dispositif pendant son fonctionnement
4.
PACKAGED SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING
In one general aspect, a package can include a semiconductor die having a first terminal on a first side of the semiconductor die and a second terminal on a second side of the semiconductor die, a leadframe portion electrically coupled to the second terminal of the semiconductor die, and a molding compound. The first terminal on the first side of the semiconductor die, a first surface of the leadframe portion, and a first surface of the molding compound can define at least a portion of a first surface of the package. A second surface of the molding compound and a second surface of the leadframe portion can define at least a portion of a second surface of the package parallel to the first surface of the package, and the second surface can be on an opposite side of the package from the first surface of the package.
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes
H01L 23/28 - Capsulations, p.ex. couches de capsulation, revêtements
A wireless multichip module has a leadframe structure (10) with potions for receiving flip-chip mounted dies, including an integrated circuit (20) and high and low side mosfets (30, 40) to form a half-bridge circuit encapsulated in molding compound (70). The module is assembled without any bond wires. The module may also carry passive components including an external input capacitor (150) or an internal input capacitor (350).
H01L 21/60 - Fixation des fils de connexion ou d'autres pièces conductrices, devant servir à conduire le courant vers le ou hors du dispositif pendant son fonctionnement
This document discusses, among other things, systems and methods including a boost converter configured to receive an input voltage (e.g., a battery voltage) and to provide a boosted output voltage higher than the input voltage, and a shunt regulator coupled to the output of the boost converter through a resistive element and configured to regulate an output ripple of the boosted output voltage. In an example, using the systems and methods described herein, a battery voltage of less than 5 volts can be boosted and regulated to an output voltage between 16 and 20 volts with an output ripple of less than 500 microvolts.
H02M 1/14 - Dispositions de réduction des ondulations d'une entrée ou d'une sortie en courant continu
H02M 3/155 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs
H02M 3/10 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande
7.
SIC BIPOLAR JUNCTION TRANSISTOR WITH REDUCED CARRIER LIFETIME IN COLLECTOR AND A DEFECT TERMINATION LAYER
A method of manufacturing a silicon carbide (SiC) bipolar junction transistor (BJT) and a SiC BJT (100) are provided. The SiC BJT comprises an emitter region (150), a base region (140) and a collector region (120). The collector region is arranged on a substrate (110) having an off-axis orientation of about 8 degrees or lower. A defect termination layer (DTL, 130) for terminating dislocations originating from the substrate is arranged between the substrate and the collector region. The collector region includes a zone (125) in which the life time of the minority charge carriers is shorter than in the base region. The present invention is advantageous in terms of improved stability of the SiC BJTs.
H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/36 - Corps semi-conducteurs caractérisés par la concentration ou la distribution des impuretés
H01L 29/16 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/32 - Corps semi-conducteurs ayant des surfaces polies ou rugueuses les défectuosités étant à l'intérieur du corps semi-conducteur
H01L 29/04 - Corps semi-conducteurs caractérisés par leur structure cristalline, p.ex. polycristalline, cubique ou à orientation particulière des plans cristallins
H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
This document discusses among other things apparatus and methods for a proof mass including split z-axis portions. An example proof mass can include a center portion configured to anchor the proof-mass to an adjacent layer, a first z-axis portion configure to rotate about a first axis using a first hinge, the first axis parallel to an x-y plane orthogonal to a z-axis, a second z-axis portion configure to rotate about a second axis using a second hinge, the second axis parallel to the x-y plane, wherein the first z-axis portion is configured to rotate independent of the second z-axis portion.
G01P 15/14 - Mesure de l'accélération; Mesure de la décélération; Mesure des chocs, c. à d. d'une variation brusque de l'accélération en utilisant un gyroscope
This document discusses, among other things, an inertial sensor including a single proof-mass formed in an x-y plane of a device layer, the single proof-mass including a single, central anchor configured to suspend the single proof-mass above a via wafer. The inertial sensor further includes first and second electrode stator frames formed in the x-y plane of the device layer on respective first and second sides of the inertial sensor, the first and second electrode stator frames symmetric about the single, central anchor, and each separately including a central platform and an anchor configured to fix the central platform to the via wafer, wherein the anchors for the first and second electrode stator frames are asymmetric along the central platforms with respect to the single, central anchor.
G01C 19/56 - Dispositifs sensibles à la rotation utilisant des masses vibrantes, p.ex. capteurs vibratoires de vitesse angulaire basés sur les forces de Coriolis
G01C 19/5783 - Montages ou boîtiers non spécifiques à l'un des dispositifs couverts par les groupes
G01P 15/02 - Mesure de l'accélération; Mesure de la décélération; Mesure des chocs, c. à d. d'une variation brusque de l'accélération en ayant recours aux forces d'inertie
Various examples include microelectromechanical die for sensing motion that includes symmetrical proof-mass electrodes interdigitated with asymmetrical stator electrodes. Some of these examples include electrodes that are curved around an axis orthogonal to the plane in which the electrodes are disposed. An example provides vertical flexures coupling an inner gimbal to a proof-mass in a manner permitting flexure around a horizontal axis.
G01C 19/56 - Dispositifs sensibles à la rotation utilisant des masses vibrantes, p.ex. capteurs vibratoires de vitesse angulaire basés sur les forces de Coriolis
G01C 19/5719 - Dispositifs sensibles à la rotation utilisant des masses vibrantes, p.ex. capteurs vibratoires de vitesse angulaire basés sur les forces de Coriolis utilisant des masses planaires vibrantes entraînées dans une vibration de translation le long d’un axe
G01C 19/5783 - Montages ou boîtiers non spécifiques à l'un des dispositifs couverts par les groupes
11.
MEMS MULTI-AXIS GYROSCOPE WITH CENTRAL SUSPENSION AND GIMBAL STRUCTURE
Various examples include microelectromechanical die for sensing motion that includes symmetrical proof-mass electrodes interdigitated with asymmetrical stator electrodes. Some of these examples include electrodes that are curved around an axis orthogonal to the plane in which the electrodes are disposed. An example provides vertical flexures coupling an inner gimbal to a proof-mass in a manner permitting flexure around a horizontal axis.
G01C 19/56 - Dispositifs sensibles à la rotation utilisant des masses vibrantes, p.ex. capteurs vibratoires de vitesse angulaire basés sur les forces de Coriolis
G01C 19/5783 - Montages ou boîtiers non spécifiques à l'un des dispositifs couverts par les groupes
New designs for silicon carbide (SiC) bipolar junction transistors (BJTs) and new methods of manufacturing such SiC BJTs are provided. The SiC BJT comprises a collector region (220), a base region (240) and an emitter region (260) arranged as a stack, the emitter region and part of the base region forming a mesa. The intrinsic part of the base region includes a first portion having a first doping concentration and a second portion having a second doping concentration lower than the first doping concentration. Further, the second portion is vertically arranged between the first portion and the emitter region in the stack.
H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/16 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée
A power supply system includes a power supply switch (102) including a first input voltage port, a second input voltage port, and an output voltage port; and a comparator circuit (104) configured to compare a first input voltage (VinA) at the first input voltage port with a second input voltage (VinB) at the second input voltage port, and select a maximum of the first input voltage and the second input voltage. The comparator circuit (104) is further configured to couple the selected maximum voltage to an n-well region of the power supply switch (102) to block reverse current flow from the output voltage port to the first and the second input voltage ports, and further block reverse current flow from the first input voltage port to the second input voltage port. The system can provide true reverse current blocking and hot swap capability.
H02J 1/10 - Fonctionnement de sources à courant continu en parallèle
H02M 3/155 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs
The present disclosure is directed to a modulation scheme for driving a piezo element. In one embodiment, a device may comprise, for example, a piezo element, voltage rails and bridge circuitry. The bridge circuitry may be coupled between the piezo element and the voltage rails. The bridge circuitry may include at least signal sources configured to generate drive signals that cause the piezo element to generate mechanical movement while being coupled to at least one of the voltage rails. In the same or a different embodiment the bridge circuitry may further include comparators, the output of the comparators being usable to determine the resonant frequency of the piezo element. The operating frequency of the bridge circuitry may be configured based on the resonant frequency of the piezo element.
New designs for silicon carbide (Si C) bipolar junction transistors (BJTs) and new methods of manufacturing such Si C BJTs are provided. The Si C BJT comprises a collector region (220), a base region (240) and an emitter region (260). Further, a surface passivation layer is deposited between an emitter contact for contacting the emitter region and a base contact for contacting the base region. The deposited surface passivation layer induces the formation of a depletion region under said surface passivation layer in the extrinsic part of said base region.Further, the Si C BJT comprises a surface gatearranged at the deposited surface passivation layer. The surface gateisconfigured to apply a negative electric potentialto the deposited surface passivation layer with respect to the electric potential in the base region. The present invention is advantageous in that it provides Si C BJTs with improved blocking capabilities.
H01L 29/16 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée
16.
SOFT-START CONTROL TECHNIQUES FOR A SWITCHED-MODE POWER SUPPLY
A power supply system including switched-mode power supply circuitry configured to generate a DC output voltage from a DC input voltage and soft-start feedback circuitry configured to control the switched-mode power supply circuitry to generate a predefined output voltage during a soft-start period of operation. The soft-start feedback circuitry includes a controllable current source configured to generate a reference current and a reference voltage, wherein the reference current is based on a difference between the reference voltage and a feedback voltage proportional to the output voltage, and amplifier circuitry configured to compare the feedback voltage with the reference voltage and generate a control signal to control the operation of the switched-mode power supply during a soft- start period of operation.
A power device includes a semiconductor region which in turn includes a plurality of alternately arranged pillars of first and second conductivity type. Each of the plurality of pillars of second conductivity type further includes a plurality of implant regions of the second conductivity type arranged on top of one another along the depth of pillars of second conductivity type, and a trench portion filled with semiconductor material of the second conductivity type directly above the plurality of implant regions of second conductivity type.
A resonant converter system includes a first stage having inverter circuitry and resonant tank circuitry configured to generate an AC signal from a DC input signal, a transformer configured to transform the AC signal, and a second stage. The second stage features synchronous rectifier (SR) circuitry including a plurality of SR switches each having a body diode and SR control circuitry. SR control circuitry is configured to generate gate control signals to control the conduction state of the SR switches so that the body diode conduction time is minimized and a negative current across the SR switches is reduced or eliminated. The method includes controlling the conduction state of SR switches to conduct as the body diode associated with the switch begins to conduct and controlling the SR switch to turn off as the current through the switch approaches a zero crossing.
H02H 7/122 - Circuits de protection de sécurité spécialement adaptés pour des machines ou appareils électriques de types particuliers ou pour la protection sectionnelle de systèmes de câble ou ligne, et effectuant une commutation automatique dans le cas d'un chan pour redresseurs pour convertisseurs ou redresseurs statiques pour onduleurs, c. à d. convertisseurs de courant continu en courant alternatif
This application discusses, among other things, multiple interface detection circuits configured to connect with a mobile electronic device connector. In an example, a multiple interface detection circuit can include a first comparator to compare a bus voltage of the mobile electronic device connector with a first threshold and to provide a first control signal, a second comparator to compare the bus voltage of the mobile electronic device connector with the first threshold and to provide a second control signal, a third comparator to compare the bus voltage of the mobile electronic device connector with a second threshold and to provide a third control signal, and a switch control configured to switch one or more signals of the connector.
A silicon carbide (SiC) bipolar junction transistor (BJT) and a method of manufacturing such a SiC BJT is provided. The SiC BJT comprises a collector region (220) having a first conductivity type, a base region (240) having a second conductivity type opposite to the first conductivity type, and an emitter region (260) having the first conductivity type arranged as a stack. The intrinsic base region (245), defined by the portion of the base region interfacing the emitter region, comprises a first portion (246) having a first dopant dose. The SiC BJT further comprises two shielding regions (244) having the second conductivity type and a second dopant dose being higher than the first dopant dose. The shielding regions laterally surround the first portion and vertically extend further down in the stack than the first portion. The invention is advantageous in that SiC BJTs with improved blocking capabilities and still sufficiently high current gain are provided.
H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/16 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/04 - Corps semi-conducteurs caractérisés par leur structure cristalline, p.ex. polycristalline, cubique ou à orientation particulière des plans cristallins
21.
SIC BIPOLAR JUNCTION TRANSISTOR WITH OVERGROWN EMITTER
New designs for silicon carbide (SiC) bipolar junction transistors (BJTs) and new methods of manufacturing such SiC BJTs are provided. The SiC BJT comprises a collector region (220), a base region (240) and an emitter region (260) arranged as a stack. The emitter region forms an elevated structure defined by outer sidewalls (265) on top of the stack. The portion of the base region interfacing the emitter region defines the intrinsic base region (245). Further, the intrinsic base region comprises a first portion (246) laterally spaced away from the outer sidewalls of the emitter region by a second portion (247) having a dopant dose higher than that of the first portion. The present invention is advantageous in that SiC BJTs with improved blocking capabilities and still sufficiently high current gain are provided.
H01L 21/04 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives les dispositifs présentant au moins une barrière de potentiel ou une barrière de surface, p.ex. une jonction PN, une région d'appauvrissement, ou une région de concentration de porteurs de charges
H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/24 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des matériaux semi-conducteurs inorganiques non couverts par les groupes , , ou
22.
METHOD OF MANUFACTURING A SIC BIPOLAR JUNCTION TRANSISTOR AND SIC BIPOLAR JUNCTION TRANSISTOR THEREOF
A method of manufacturing a silicon carbide (SiC) bipolar junction transistor (BJT) and a SiC BJT (200) are provided. The SiC BJT comprises an emitter region (236), a base region (234) and a collector region (232). The collector region is arranged on a substrate (210) having an off-axis orientation of about 4 degrees or lower. Further, a defect termination layer (DTL, 220) is arranged between the substrate and the collector region. The thickness and the doping level of the DTL are configured to terminate basal plane dislocations in the DTL and reduce the growth of defects from the DTL to the collector region. The present invention is advantageous in that SiC BJTs with improved stability are provided. Further, a method of evaluating the degradation performance of a SiC BJT is provided.
H01L 21/04 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives les dispositifs présentant au moins une barrière de potentiel ou une barrière de surface, p.ex. une jonction PN, une région d'appauvrissement, ou une région de concentration de porteurs de charges
H01L 29/32 - Corps semi-conducteurs ayant des surfaces polies ou rugueuses les défectuosités étant à l'intérieur du corps semi-conducteur
H01L 29/16 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée
H01L 29/04 - Corps semi-conducteurs caractérisés par leur structure cristalline, p.ex. polycristalline, cubique ou à orientation particulière des plans cristallins
This document discusses, among other things, an mode matching circuit for a inertial sensor including an oscillator circuit configured to selectively couple to a sense axis of an inertial sensor and to provide sense frequency information of the sense axis, a frequency comparator configured to receive the sense frequency information of the sense axis and drive frequency information of the inertial sensor, and to provide frequency difference information to a processor, and a programmable bias source configured to apply a bias voltage to the sense axis to set a sense frequency of the sense axis in response to a command from the processor, and to maintain a desired frequency difference between the sense frequency and a drive frequency of the inertial sensor.
G01P 15/02 - Mesure de l'accélération; Mesure de la décélération; Mesure des chocs, c. à d. d'une variation brusque de l'accélération en ayant recours aux forces d'inertie
G01C 19/56 - Dispositifs sensibles à la rotation utilisant des masses vibrantes, p.ex. capteurs vibratoires de vitesse angulaire basés sur les forces de Coriolis
B81B 7/02 - Systèmes à microstructure comportant des dispositifs électriques ou optiques distincts dont la fonction a une importance particulière, p.ex. systèmes micro-électromécaniques (SMEM, MEMS)
24.
MICROELECTROMECHANICAL PRESSURE SENSOR INCLUDING REFERENCE CAPACITOR
This document discusses, among other things, an apparatus including a silicon die including a vibratory diaphragm, the die having a silicon die top opposite a silicon die bottom, with a top silicon die port extending from the silicon die top through the silicon die to a top of the vibratory diaphragm, and with a bottom silicon die port extending from the silicon die bottom to a bottom of the vibratory diaphragm, wherein the bottom silicon die port has a cross sectional area that is larger than a cross-sectional area of the top silicon die port, a capacitor electrode disposed along a bottom of the silicon die, across the bottom silicon die port, the capacitor electrode including a first signal generation portion that is coextensive with the top silicon die port, and a second signal generation portion surrounding the first portion.
G01L 9/12 - Mesure de la pression permanente, ou quasi permanente d’un fluide ou d’un matériau solide fluent par des éléments électriques ou magnétiques sensibles à la pression; Transmission ou indication par des moyens électriques ou magnétiques du déplacement des éléments mécaniques sensibles à la pression, utilisés pour mesurer la pression permanente ou quasi permanente d’un fluide ou d’un matériau solide fluent en faisant usage des variations de la capacité
G01L 7/08 - Mesure de la pression permanente ou quasi permanente d’un fluide ou d’un matériau solide fluent par des éléments mécaniques ou hydrauliques sensibles à la pression sous forme de jauges, élastiquement déformables du type à diaphragme élastique
B81B 3/00 - Dispositifs comportant des éléments flexibles ou déformables, p.ex. comportant des membranes ou des lamelles élastiques
B81C 1/00 - Fabrication ou traitement de dispositifs ou de systèmes dans ou sur un substrat
25.
THROUGH SILICON VIA WITH REDUCED SHUNT CAPACITANCE
This document refers to apparatus and methods for a device layer of a microelectromechanical system (MEMS) sensor having vias with reduced shunt capacitance. In an example, a device layer can include a substrate having a pair of trenches separated in a horizontal direction by a portion of the substrate, wherein each trench of the pair of trenches includes first and second vertical layers including dielectric, the first and second vertical layers separated by a third vertical layer including polysilicon.
B81C 1/00 - Fabrication ou traitement de dispositifs ou de systèmes dans ou sur un substrat
B81B 7/02 - Systèmes à microstructure comportant des dispositifs électriques ou optiques distincts dont la fonction a une importance particulière, p.ex. systèmes micro-électromécaniques (SMEM, MEMS)
B81B 1/00 - Dispositifs sans éléments mobiles ou flexibles, p.ex. dispositifs capillaires microscopiques
H01G 7/00 - Condensateurs dont la capacité varie par des moyens non mécaniques; Procédés pour leur fabrication
This document refers to multi-die micromechanical system (MEMS) packages. In an example, a multi-die MEMS package can include a controller integrated circuit (IC) configured to couple to a circuit board, a MEMS IC mounted to a first side of the controller IC, a through silicon via extending through the controller IC between the first side and a second side of the controller IC, the second side opposite the first side, and wherein the MEMS IC is coupled to the through silicon via.
This document discusses, among other things, an inertial measurement system including a device layer including a single proof-mass 3 -axis accelerometer, a cap wafer bonded to a first surface of the device layer, and a via wafer bonded to a second surface of the device layer, wherein the cap wafer and the via wafer are configured to encapsulate the single proof-mass 3 -axis accelerometer. The single proof-mass 3 -axis accelerometer can be suspended about a single, central anchor, and can include separate x, y, and z-axis flexure bearings, wherein the x and y-axis flexure bearings are symmetrical about the single, central anchor and the z-axis flexure is not symmetrical about the single, central anchor.
G01P 15/02 - Mesure de l'accélération; Mesure de la décélération; Mesure des chocs, c. à d. d'une variation brusque de l'accélération en ayant recours aux forces d'inertie
G01P 15/097 - Mesure de l'accélération; Mesure de la décélération; Mesure des chocs, c. à d. d'une variation brusque de l'accélération en ayant recours aux forces d'inertie avec conversion en valeurs électriques ou magnétiques au moyen d'éléments vibrants
G01C 19/56 - Dispositifs sensibles à la rotation utilisant des masses vibrantes, p.ex. capteurs vibratoires de vitesse angulaire basés sur les forces de Coriolis
B81B 7/02 - Systèmes à microstructure comportant des dispositifs électriques ou optiques distincts dont la fonction a une importance particulière, p.ex. systèmes micro-électromécaniques (SMEM, MEMS)
B81C 1/00 - Fabrication ou traitement de dispositifs ou de systèmes dans ou sur un substrat
28.
MICROMACHINED MONOLITHIC 3-AXIS GYROSCOPE WITH SINGLE DRIVE
This document discusses, among other things, a cap wafer and a via wafer configured to encapsulate a single proof-mass 3-axis gyroscope formed in an x-y plane of a device layer. The single proof-mass 3-axis gyroscope can include a main proof-mass section suspended about a single, central anchor, the main proof-mass section including a radial portion extending outward towards an edge of the 3-axis gyroscope sensor, a central suspension system configured to suspend the 3-axis gyroscope from the single, central anchor, and a drive electrode including a moving portion and a stationary portion, the moving portion coupled to the radial portion, wherein the drive electrode and the central suspension system are configured to oscillate the 3-axis gyroscope about a z-axis normal to the x-y plane at a drive frequency.
G01C 19/56 - Dispositifs sensibles à la rotation utilisant des masses vibrantes, p.ex. capteurs vibratoires de vitesse angulaire basés sur les forces de Coriolis
B81B 3/00 - Dispositifs comportant des éléments flexibles ou déformables, p.ex. comportant des membranes ou des lamelles élastiques
29.
FLEXURE BEARING TO REDUCE QUADRATURE FOR RESONATING MICROMACHINED DEVICES
An example include microelectromechanical die for sensing motion that includes a fixed portion, an anchor coupled to the fixed portion, a first nonlinear suspension member coupled to anchor on a side of the anchor, a second nonlinear suspension member coupled to the anchor on the same side of the anchor, the second nonlinear suspension member having a shape and location mirroring the first nonlinear suspension member about an anchor bisecting plane and a proof-mass that is planar, the proof mass suspended at least in part by the first nonlinear suspension member and the second nonlinear suspension member such that the proof-mass is rotable about the anchor and is slideable in a plane parallel to the fixed portion.
B81B 3/00 - Dispositifs comportant des éléments flexibles ou déformables, p.ex. comportant des membranes ou des lamelles élastiques
B81C 1/00 - Fabrication ou traitement de dispositifs ou de systèmes dans ou sur un substrat
G01C 19/56 - Dispositifs sensibles à la rotation utilisant des masses vibrantes, p.ex. capteurs vibratoires de vitesse angulaire basés sur les forces de Coriolis
30.
PACKAGING TO REDUCE STRESS ON MICROELECTROMECHANICAL SYSTEMS
One example includes an integrated circuit including at least one electrical interconnects disposed on an elongate are extending away from a main portion of the integrated circuit and a microelectromechanical layer including an oscillating portion, the microelectromechanical layer coupled to the main portion of the integrated circuit.
B81C 3/00 - Assemblage de dispositifs ou de systèmes à partir de composants qui ont reçu un traitement individuel
H01L 21/00 - Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de dispositifs à semi-conducteurs ou de dispositifs à l'état solide, ou bien de leurs parties constitutives
31.
SEALED PACKAGING FOR MICROELECTROMECHANICAL SYSTEMS
One example includes an integrated circuit including at least one electrical interconnects disposed on an elongate are extending away from a main portion of the integrated circuit and a microelectromechanical layer including an oscillating portion, the microelectromechanical layer coupled to the main portion of the integrated circuit, wherein the microelectromechanical layer includes a cap comprising a membrane that extends to the integrated circuit.
B81C 3/00 - Assemblage de dispositifs ou de systèmes à partir de composants qui ont reçu un traitement individuel
B81C 1/00 - Fabrication ou traitement de dispositifs ou de systèmes dans ou sur un substrat
H01L 21/00 - Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de dispositifs à semi-conducteurs ou de dispositifs à l'état solide, ou bien de leurs parties constitutives
The device layer of a 6-degrees-of-freedom (6-DOF) inertial measurement system can include a single proof-mass 6-axis inertial sensor formed in an x-y plane, the inertial sensor including a main proof-mass section suspended about a single, central anchor, the main proof-mass section including a radial portion extending outward towards the edge of the inertial sensor, a central suspension system configured to suspend the 6-axis inertial sensor from the single, central anchor, and a drive electrode including a moving portion and a stationary portion, the moving portion coupled to the radial portion, wherein the drive electrode and the central suspension system are configured to oscillate the 6-axis inertial sensor about a z-axis normal to the x-y plane.
G01C 19/56 - Dispositifs sensibles à la rotation utilisant des masses vibrantes, p.ex. capteurs vibratoires de vitesse angulaire basés sur les forces de Coriolis
B81B 3/00 - Dispositifs comportant des éléments flexibles ou déformables, p.ex. comportant des membranes ou des lamelles élastiques
B81C 1/00 - Fabrication ou traitement de dispositifs ou de systèmes dans ou sur un substrat
33.
CONDUCTIVITY MODULATION IN A SILICON CARBIDE BIPOLAR JUNCTION TRANSISTOR
The present invention relates to a method of manufacturing a silicon carbide (SiC) bipolar junction transistor (BJT) and a SiC BJT. The SiC BJT (100) comprises a collector region (120), a base region (140) and an emitter region (160). The method of the present invention comprises the step of providing an intermediate region (180) of semiconductor material arranged between the base-emitter junction and a contact zone for electrically contacting the base region, the base-emitter junction being formed by the base region (120) and the emitter region (160). The extent of conductivity modulation in the collector region (120) is determined by adjusting at least one parameter of the intermediate region (180) affecting the diffusion current of minority carriers in the intermediate region (180).
H01L 21/04 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives les dispositifs présentant au moins une barrière de potentiel ou une barrière de surface, p.ex. une jonction PN, une région d'appauvrissement, ou une région de concentration de porteurs de charges
H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/16 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée
34.
SEMICONDUCTOR DEVICE AND METHOD OF FORMING A STRUCTURE IN A TARGET SUBSTRATE FOR MANUFACTURING A SEMICONDUCTOR DEVICE
A semiconductor device and a method of forming a structure in a target substrate for manufacturing a semiconductor device is provided. The method comprises the step of providing a masking layer (120) on the target substrate (110) and providing a stair-like profile (122) in the masking layer such that the height of a step of the stair-like profile is smaller than the thickness of the masking layer. Further, the method comprises the step of performing anisotropic etching of the masking layer and the target substrate simultaneously such that a structure having a stair-like profile (124) is formed in the target substrate. The semiconductor device comprises a target substrate including a first region made of a first type of semiconductor material and a second region made of a second type of semiconductor material. The first and second types of semiconductor material are different and the first and second regions are adjacent for forming an active region of the semiconductor device. At the junction between the first and second regions, the semiconductor device comprises a structure having a stair-like profile. The present invention is advantageous in that it provides a semiconductor device with improved characteristics.
H01L 21/04 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives les dispositifs présentant au moins une barrière de potentiel ou une barrière de surface, p.ex. une jonction PN, une région d'appauvrissement, ou une région de concentration de porteurs de charges
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/24 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des matériaux semi-conducteurs inorganiques non couverts par les groupes , , ou
A micromachined inertial sensor (200) with a single proof-mass (201) or measuring 6-degree-of-motions. The single proof-mass (201) includes a frame (202), an x-axis proof mass section (212a, 212b) attached to the frame by a first flexure, and a y-axis proof mass section (218) attached to the frame (202) by a second flexure (228a, 228b). The single proof-mass (201) is formed in a micromachined structural layer and is adapted to measure angular rates about three axes with a single drive motion and linear accelerations about the three axes.
G01C 19/56 - Dispositifs sensibles à la rotation utilisant des masses vibrantes, p.ex. capteurs vibratoires de vitesse angulaire basés sur les forces de Coriolis
G01P 9/04 - en utilisant des dispositifs sensibles à la rotation avec des masses vibrantes, p.ex. diapason
B81B 7/02 - Systèmes à microstructure comportant des dispositifs électriques ou optiques distincts dont la fonction a une importance particulière, p.ex. systèmes micro-électromécaniques (SMEM, MEMS)
B81C 1/00 - Fabrication ou traitement de dispositifs ou de systèmes dans ou sur un substrat
A semiconductor structure comprises an active region comprising trenches extending into a semiconductor region. Each trench includes a shield electrode and a gate electrode. The semiconductor structure also comprises a shield contact region adjacent to the active region. The shield contact region comprises at least one contact trench extending into the semiconductor region. The shield electrode from at least one of the trenches in the active region extends along a length of the contact trench. The semiconductor structure also comprises an interconnect layer extending over the active region and the shield contact region. In the active region the interconnect layer is isolated from the gate electrode in each trench by a dielectric layer and contacts mesa surfaces of the semiconductor region adjacent to the trenches. In the shield contact region the interconnect layer contacts the shield electrode and the mesa surfaces of the semiconductor region adjacent to the contact trench.
Semiconductor devices and methods for making such devices that contain a 3D channel architecture are described. The 3D channel architecture is formed using a dual trench structure containing with a plurality of lower trenches extending in an x and y directional channels and separated by a mesa and an upper trench extending in a y direction and located in an upper portion of the substrate proximate a source region. Thus, smaller pillar trenches are formed within the main line-shaped trench. Such an architecture generates additional channel regions which are aligned substantially perpendicular to the conventional line-shaped channels. The channel regions, both conventional and perpendicular, are electrically connected by their corner and top regions to produce higher current flow in all three dimensions. With such a configuration, higher channel density, a stronger inversion layer, and a more uniform threshold distribution can be obtained for the semiconductor device. Other embodiments are described.
A field effect transistor includes a semiconductor region of a first conductivity type having an upper surface and a lower surface, the lower surface of the semiconductor region extending over and abutting a substrate. A well regions of a second conductivity type is disposed within the semiconductor region. The field effect transistor also includes source regions of the first conductivity type disposed in the well regions and a gate electrode extending over each well region and overlapping a corresponding one of the source regions. Each gate electrode is insulated from the underlying well region by a gate dielectric. At least one LDD region of the first conductivity type is disposed in the semiconductor region between every two adjacent well regions such that the at least one LDD region is in contact with the two adjacent well regions between which it is disposed. A sinker region is disposed in the semiconductor region directly underneath the at least one LDD region such that the at least one LDD region and the sinker region are positioned along a vertical orientation between the upper and lower surfaces of the semiconductor region.
The present invention relates to a silicon carbide (SiC) bipolar junction transistor (BJT), where the surface region between the emitter and base contacts (1, 2) on the transistor is given a negative electric surface potential with respect to the potential in the hulk SiC.
H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/24 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des matériaux semi-conducteurs inorganiques non couverts par les groupes , , ou
40.
LOW SPEED. LOAD INDEPENDENT, SLEW RATE CONTROLLED OUTPUT BUFFER WITH NO DC POWER CONSUMPTION
An output buffer utilizes capacitive feedback to control the output slew rate largely independent of load capacitance. The invention slows the rising and falling slew rates and via a capacitance feedback reduces the effect of load capacitance on slew rate, and uses no DC current. Transistor switches are employed to isolate and reduce noise and interaction among the circuit components and functions.
A method for forming a trench-gate FET includes the following steps. A plurality of trenches is formed extending into a semiconductor region. A gate dielectric is formed extending along opposing sidewalls of each trench and over mesa surfaces of the semiconductor region between adjacent trenches. A gate electrode is formed in each trench isolated from the semiconductor region by the gate dielectric. Well regions of a second conductivity type are formed in the semiconductor region. Source regions of the first conductivity type are formed in upper portions of the well regions. After forming the source regions, a salicide layer is formed over the gate electrode in each trench abutting portions of the gate dielectric. The gate dielectric prevents formation of the salicide layer over the mesa surfaces of the semiconductor region between adjacent trenches.
A circuit that automatically, seamlessly connects the higher (or the lower) of two power supplies to an output is described. The circuit does not incur a one diode drop when the two power supplies are at about the same voltage levels, and the unused power supply draws no stand-by current. Cross coupled transistor and cross coupled inverters are employed.
This document discusses, among other things, a charging emulator configured to be coupled to an electrical interface, the charging emulator including a control circuit configured to receive information about a peripheral device coupled to the electrical interface and a charger circuit configured to provide power to the electrical interface using the received peripheral device information. In an example, the charging emulator can include a component of a host device including a low-power state, and the charger circuit can be configured to provide power to the electrical interface when the host device is in the low-power state.
A semiconductor device (100) has N-well regions (18) holding PMOS devices (110, 112) and P-type regions (14) holding NMOS devices (114, 116). Devices (110) and (114) have high thresholds and devices (112) and (116) have low thresholds. The PMOS devices are junction isolated from the substrate (10) by the N-well (18) and the NMOS devices are isolated from the substrate by the N- type layer (13). Field oxide regions (20) laterally isolate the PMOS from the NMOS devices. The high threshold CMOS devices (110, 114) connect the low threshold CMOS devices to opposite rails Vdd and Vss. A control terminal (121) turns the high threshold devices on to let the low threshold devices switch rapidly. In stand-by mode, the high threshold devices are off and there is very low leakage current.
A semiconductor die package. The semiconductor die package includes a premolded clip structure assembly having a clip structure, a semiconductor die attached to the clip structure, and a first molding material covering at least a portion of the clip structure and the semiconductor die. The semiconductor die package also includes a leadframe structure having a die attach pad, where the leadframe structure is attached to premolded clip structure assembly.
A MOSFET switch (10) is disclosed that is driven on by a circuit that provides a constant gate to source voltage, Vgs, that is independent of the input voltage (A in) he power supply and any logic signals. The constant Vgs is derived from a reference voltage (V bias) and biases the MOSFET switch such that Ron is constant, or Rflatness is minimized. A minimized Rflatness provides a higher fidelity transfer of audio signals compared to prior art switches where Rflatness is greater.
H03K 17/06 - Modifications pour assurer un état complètement conducteur
H03K 17/14 - Modifications pour compenser les variations de valeurs physiques, p.ex. de la température
H03K 17/687 - Commutation ou ouverture de porte électronique, c. à d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs les dispositifs étant des transistors à effet de champ
In one form a lateral MOSFET includes an active gate positioned laterally between a source region and a drain region, the drain region extending from an upper surface of a monocrystalline semiconductor body to a bottom surface of the monocrystalline semiconductor body, and a non-active gate positioned above the drain region. In another form the lateral MOSFET includes a gate positioned laterally between a source region and a drain region, the drain region extending from an upper surface of a monocrystalline semiconductor body to a bottom surface of the monocrystalline semiconductor body, the source region and the drain region being of a first conductivity type, a heavy body region of a second conductivity type in contact with and below the source region, and the drain region comprising a lightly doped drain (LDD) region proximate an edge of the gate and a sinker extending from the upper surface of the monocrystalline body to the bottom surface of the monocrystalline semiconductor body.
A semiconductor die package. The semiconductor die package comprises a semiconductor die and a molded clip structure comprising a clip structure and a first molding material covering at least a portion of the clip structure. The first molding material exposes an outer surface of the clip structure. The clip structure is electrically coupled to the semiconductor die. The semiconductor die package further comprises a leadframe structure comprising a die attach pad and a plurality of leads extending from the die attach pad. The semiconductor die is on the die attach pad of the leadframe structure. A second molding material covers at least a portion of the semiconductor die and the leadframe structure. The semiconductor die package also includes a heat slug and a thermally conductive material coupling the heat slug to the exposed surface of the clip structure.
A semiconductor die package. The semiconductor die package includes a leadframe structure comprising a first lead structure comprising a die attach pad, a second lead structure, and a third lead structure. It also includes a semiconductor die comprising a first surface and a second surface. The semiconductor die is on the die attach pad of the leadframe structure. The first surface is proximate the die attach pad. The semiconductor die package further includes a clip structure comprising a first interconnect structure and a second interconnect structure, the first interconnect structure comprising a planar portion and a protruding portion, the protruding portion including an exterior surface and side surfaces defining the exterior surface. The protruding portion extends from the planar portion of the first interconnect structure. The second surface of the semiconductor die is proximate to the clip structure, and a molding material covers at least the semiconductor die and at least a portion of the side surfaces of the protruding portion.
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes
A buck converter module includes a high side (HS) die having source, drain, and gate bonding pads on a front side of the HS die, a low side (LS) die having a first section thereof with a plurality of through silicon vias (TSVs) extending from a back side to a front side of the LS die, the LS die having source, drain, and gate bonding pads located on a front side of a second section separate from the first section, the drain bonding pad electrically connected to the back side of the LS die in the second section. The HS die and the LS die are bonded together such that the source bonding pad of the HS die is electrically connected to the back side of the LS die, and each of the drain and gate bonding pads are electrically connected to separate TSVs in the LS die.
G05F 1/00 - Systèmes automatiques dans lesquels les écarts d'une grandeur électrique par rapport à une ou plusieurs valeurs prédéterminées sont détectés à la sortie et réintroduits dans un dispositif intérieur au système pour ramener la grandeur détectée à sa va
56.
SEMICONDUCTOR DIE STRUCTURES FOR WAFER-LEVEL CHIPSCALE PACKAGING OF POWER DEVICES, PACKAGES AND SYSTEMS FOR USING THE SAME, AND METHODS OF MAKING THE SAME
Disclosed are semiconductor die structures that enable a die having a vertical power device to be packaged in a wafer-level chip scale package where the current-conducting terminals are present at one surface of the die, and where the device has very low on-state resistance. In an exemplary embodiment, a trench and an aperture are formed in a backside of a die, with the aperture contacting a conductive region at the top surface of the die. A conductive layer and/or a conductive body may be disposed on the trench and aperture to electrically couple the backside current-conducting electrode of the device to the conductive region. Also disclosed are packages and systems using a die with a die structure according to the invention, and methods of making dice with a die structure according to the invention.
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes
57.
FLEXIBLE AND STACKABLE SEMICONDUCTOR DIE PACKAGES, SYSTEMS USING THE SAME, AND METHODS OF MAKING THE SAME
Disclosed are semiconductor die packages, systems, and methods therefor. An exemplary package comprises a patterned conductive layer having a first surface, a second surface, and a first thickness between its first and second surfaces; a semiconductor die disposed over the first surface of the patterned conductive layer and electrically coupled thereto; a plurality of conductive bodies disposed at the second surface of the patterned conductive layer and electrically coupled thereto, each conductive body having a thickness that is greater than the first thickness; and a body of electrically insulating material disposed on the semiconductor die and a portion of the first surface of the patterned conductive layer. A further embodiment further comprises a second semiconductor die disposed over the second surface of the patterned conductive layer and electrically coupled thereto.
H01L 23/12 - Supports, p.ex. substrats isolants non amovibles
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes
Semiconductor packages that contain multiple dies and methods for making such packages are described. The semiconductor packages contain a leadframe with multiple dies and also contain a single premolded clip that connects the dies. The premolded clip connects the solderable pads of the source die and gate die to the source and gate of the leadframe via standoffs. The solderable pads on the dies and on the standoffs provide a substantially planar surface to which the premolded clip is attached. Such a configuration increases the cross-sectional area of the interconnection when compared to wirebonded connections, thereby improving the electrical (RDSon) and the thermal performance of the semiconductor package. Such a configuration also lowers costs relative to similar semiconductor packages that use wirebonded connections. Other embodiments are described.
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes
A field effect transistor device having a strained semiconductor channel region overlying a heterostructure-semiconductor on a metal substrate includes a first semiconductor layer overlying a first metal layer. The first semiconductor layer has a first semiconductor material and a second semiconductor material in a relaxed heterostructure and is heavily doped. A second semiconductor layer overlies the first semiconductor layer and has a first semiconductor material and a second semiconductor material in a relaxed heterostructure. The second semiconductor layer is more lightly doped than the first semiconductor layer. A trench extends into the second semiconductor layer and a channel region has a strained layer of the first semiconductor material adjacent a trench sidewall. The strained channel region provides enhanced carrier mobility and improves performance of the field effect transistor.
Pre-molded component packages that may be as thin as a leadframe for a semiconductor die, systems using the same, and methods of making the same are disclosed. The leads of an exemplary package are exposed at both surfaces at the leadframe. The packages may be stacked upon one another and electrically coupled at the exposed portions of their leads.
A circuit is described that when the power supply to circuits that control a pass transistor is at zero volts, the pass transistor configured as a voltage level translator remains off regardless of the voltages and changes in voltages at the ports connected to the pass transistor. Cross coupled transistors provide a mechanism where the higher of the port voltages is available to power circuitry that maintains the control input of the pass transistor in the off condition. The voltages at the ports may rise and fall relative to each other, but the control input of the pass transistor will keep the pass transistor off.
Disclosed are molded ultra-thin semiconductor die packages, systems that incorporate such packages, and methods of making such packages. An exemplary package comprises a leadframe having an aperture formed between the leadframe's first and second surfaces, and a plurality of leads disposed adjacent to the aperture. The package further comprises a semiconductor disposed in the aperture of the leadframe with its top surface substantially flush with the leadframe's first surface, and at least one gap between at least one side surface of the semiconductor die and at least one lead of the leadframe. A body of electrically insulating material is disposed in the at least one gap. A plurality of conductive members interconnect leads of the leadframe with conductive regions on the die's top surface, with at least one conductive member having a portion disposed over at least a portion of the body of insulating material.
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes
H01L 23/12 - Supports, p.ex. substrats isolants non amovibles
63.
EMBEDDED DIE PACKAGE AND PROCESS FLOW USING A PRE-MOLDED CARRIER
An embedded die package includes a carrier with an electrical device in the cavity of the carrier, a first dielectric layer covering the sides and top of the electrical device except for vias over selected bonding pads of the electrical device, a plurality of metal conductors, each of which is in contact with at least one of the vias, one or more additional dielectric layers lying over the metal conductors and the first dielectric layer, wherein a top layer of the one or more dielectric layers has openings with metalization underneath coupled to at least one of the metal conductors, and solder bumps protruding from each of the openings.
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes
A molded, leadless packaged semiconductor multichip module includes 100 has four mosfets 10, 12, 14, 16 for a full bridge circuit. The mosfets may include two N- channel and two P-channel devices or four mosfets of the same type, but four N-channel are preferred. In module 100 there are two leadframes 30, 40 for assembling the mosfets. In particular, the two N-channel and two P-channel devices are disposed between two leadframes and encapsulated in an electrically insulating molding compound 84. The resulting package has four upper heat sinks 44.1-44.4 that are exposed in the molding compound 84 for transferring heat from the mosfets to the ambient environment. No wire bonds are required. This can significantly reduce the on resistance, RDSON- The top or source-drain lead frame 30 may be soldered to the sources and gates of the bridge mosfets.
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/11 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs ayant des conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 23/34 - Dispositions pour le refroidissement, le chauffage, la ventilation ou la compensation de la température
H01L 23/36 - Emploi de matériaux spécifiés ou mise en forme, en vue de faciliter le refroidissement ou le chauffage, p.ex. dissipateurs de chaleur
An integrated low leakage Schottky diode has a Schottky barrier junction proximate one side of an MOS gate with one end of a drift region on an opposite side of the gate. Below the Schottky metal and the gate oxide is a RESURF structure of an N- layer over a P- layer which also forms the drift region that ends at the diode's cathode in one embodiment of the present invention. The N- and P- layers have an upward concave shape under the gate. The gate electrode and the Schottky metal are connected to the diode's anode. A P- layer lies between the RESURF structure and an NISO region which has an electrical connection to the anode. A P+ layer under the Schottky metal is in contact with the P- layer through a P well.
A three-dimensional semiconductor device structure includes a first semiconductor device and a second semiconductor device bonded together using a patterned conductive layer according to an embodiment of the invention. The first semiconductor device includes a first plurality of terminals on its front side, and the second semiconductor device includes a second plurality of terminals on its front side. The patterned conductive layer includes a plurality of conductive regions. Each of the conductive regions is bonded to a conductor coupled to one of the first plurality of terminals and bonded to another conductor coupled to one of the second plurality of terminals, providing electrical coupling between the first semiconductor device and the second semiconductor device. In a specific embodiment, each terminal of the first semiconductor device is bonded to a corresponding terminal of the second semiconductor device, providing a parallel combination of the first and the second semiconductor devices. In another embodiment, a parallel combination of the first and the second semiconductor devices is provided using one or more terminals on a backside of the first semiconductor device and one or more terminals on a front side of the second semiconductor device.
The present invention includes a pass transistor (2) that limits current drawn from a circui without using a series resistor and while drawing minimal current from an external supply A current mirror (Klout)of the output current (lout) is formed and compared to a reference current (lref). When the output current (lout) increases, the mirror current (Klout ) increases proportionally, and when a threshold (Iref) is crossed, the pass transistor (2) is turned off. The pass transistor (2) is biased from a charge pump (CP) that provides a voltage (Voc), current (ldC) from which a current mirror (lddc) is drawn controls the pass transistor (2).
H02H 9/00 - Circuits de protection de sécurité pour limiter l'excès de courant ou de tension sans déconnexion
H03K 17/082 - Modifications pour protéger le circuit de commutation contre la surintensité ou la surtension par réaction du circuit de sortie vers le circuit de commande
68.
TECHNIQUE FOR COMBINING IN-RUSH CURRENT LIMITING AND SHORT CIRCUIT CURRENT LIMITING
A circuit that protects from high power-on in-rush currents and short circuits. The circuit has a pass transistor and a parallel smaller transistor. A comparator senses when an output voltage crosses a reference and turns off the pass transistor and turns on the parallel smaller transistor. The parallel smaller transistor has a higher "on" resistance so that the short circuit or the in-rush current does not harm the electronics. When the short circuit or in-rush current condition is removed, the comparator senses this condition and returns to the normal operation where the pass transistor is on and the parallel small transistor is off.
H02H 9/00 - Circuits de protection de sécurité pour limiter l'excès de courant ou de tension sans déconnexion
H03K 17/082 - Modifications pour protéger le circuit de commutation contre la surintensité ou la surtension par réaction du circuit de sortie vers le circuit de commande
Semiconductor devices containing a CVD BPSG layer and an undoped CVD oxide cap layer are described. The cap layer can be any silicon oxide material with a thickness between about 50Å and about 350Å. The cap layer may be formed using a low temperature CVD process that is controlled for density by adjusting the amount of silicon precursor in the gas-phase. In some embodiments, the cap layer is deposited on the BPSG layer followed immediately by the BPSG film deposition prior to any annealing of the BPSG layer. The cap layer may prevent dopant out-diffusion and/or out-gassing during storage and high-temperature annealing, and moisture penetration into the BPSG layer, as well as suppress defect nucleation on the as-deposited BPSG surface and defect formation during high temperature annealing, while still allowing flow ability of the BPSG layer. Other embodiments are also described.
H01L 21/31 - Traitement des corps semi-conducteurs en utilisant des procédés ou des appareils non couverts par les groupes pour former des couches isolantes en surface, p.ex. pour masquer ou en utilisant des techniques photolithographiques; Post-traitement de ces couches; Emploi de matériaux spécifiés pour ces couches
H01L 21/20 - Dépôt de matériaux semi-conducteurs sur un substrat, p.ex. croissance épitaxiale
H01L 21/205 - Dépôt de matériaux semi-conducteurs sur un substrat, p.ex. croissance épitaxiale en utilisant la réduction ou la décomposition d'un composé gazeux donnant un condensat solide, c. à d. un dépôt chimique
70.
A METHOD AND SYSTEM THAT DETERMINES THE VALUE OF A RESISTOR IN LINEAR AND NON-LINEAR RESISTOR SETS
The present invention employs identically sized mirror transistors arrange in groups that may be preferentially addressed and activated to determine the value of a resistor. Known current are directed through the resistor, and the voltage developed is measured by comparing against a reference voltage. The current is increased or decreased by the least significant value until the voltage across the resistor matches the reference voltage. A successive approximation or other known technique may be used instead. A reference current is developed that temperature stable and that is trimmed when manufactured to reduce process effects. The reference voltage may be constructed to be independent form a local power source so that the system is relatively independent of process, voltage and temperature, PVT.
Disclosed in this specification is a system-in-a-package substrate that includes an interconnect substrate for permitting finely pitched connections to be made to an integrated circuit. The interconnect substrate includes a central region on its upper surface for receiving the integrated circuit. The interconnect substrate also has interconnections that electrically connect the finely pitched contacts on the upper surface to larger pitched contacts on the lower surface. The larger pitched contacts connect to a conductive trace frame. The resulting assembly is encased in a molding compound along with a plurality of other devices which are configured to interact with one other through the conductive trace.
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes
H01L 21/60 - Fixation des fils de connexion ou d'autres pièces conductrices, devant servir à conduire le courant vers le ou hors du dispositif pendant son fonctionnement
An LDMOS device includes a substrate of a first conductivity type, an epitaxial layer on the substrate, a buried well of a second conductivity type opposite to the first conductivity type in a lower portion of the epitaxial layer, the epitaxial layer being of the first conductivity type below the buried layer. The device further includes a field oxide located between a drain and both a gate on a gate oxide and a source with a saddle shaped vertical doping gradient of the second conductivity type in the epitaxial layer above the buried well such that the dopant concentration in the epitaxial layer above the buried well and below a central portion of the field oxide is lower than the dopant concentration at the edges of the field oxide nearest the drain and nearest the gate.
A semiconductor die package. Embodiments of the semiconductor die package are usable in backlight circuitry. Systems in packages may include a bridge circuit or a part thereof, and a integrated circuit die, such as a driver die, encapsulated by a molding material or other package. The bridge circuit may be stacked on opposing surfaces of a leadframe.
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes
A semiconductor die package. The semiconductor die package includes a leadframe structure, a first semiconductor die comprising a first surface attached to a first side of the leadframe structure, and a second semiconductor die attached to a second side of the leadframe structure. The second semiconductor die comprises an integrated circuit die. A housing material is formed over at least a portion of the leadframe structure, the first semiconductor die, and the second semiconductor die. An exterior surface of the molding material is substantially coplanar with the first surface of the semiconductor die.
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes
Micromodules and methods of making them are disclosed. An exemplary micromodule includes a substrate having a thin film inductor, and a bumped die mounted on the substrate and over the thin film inductor.
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes
H01L 23/50 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes pour des dispositifs à circuit intégré
H01F 10/00 - Pellicules magnétiques minces, p.ex. de structure à un domaine
H01F 27/00 - AIMANTS; INDUCTANCES; TRANSFORMATEURS; EMPLOI DE MATÉRIAUX SPÉCIFIÉS POUR LEURS PROPRIÉTÉS MAGNÉTIQUES - Détails de transformateurs ou d'inductances, en général
An integrated low leakage diode suitable for operation in a power integrated circuit has a structure similar to a lateral power MOSFET, but with the current flowing through the diode in the opposite direction to a conventional power MOSFET. The anode is connected to the gate and the comparable MOSFET source region which has highly doped regions of both conductivity types connected to the channel region to thereby create a lateral bipolar transistor having its base in the channel region. A second lateral bipolar transistor is formed in the cathode region. As a result, substantially all of the diode current flows at the upper surface of the diode thereby minimizing the substrate leakage current. A deep highly doped region in contact with the layers forming the emitter and the base of the vertical parasitic bipolar transistor inhibits the ability of the vertical parasitic transistor to fully turn on.
A field effect transistor (FET) includes a pair of trenches extending into a semiconductor region. Each trench includes a first shield electrode in a lower portion of the trench and a gate electrode in an upper portion of the trench over but insulated from the shield electrode. First and second well regions of a first conductivity type laterally extend in the semiconductor region between the pair of trenches and abut sidewalls of the pair of trenches. The first and second well regions are vertically spaced from one another by a first drift region of a second conductivity type. The gate electrode and the first shield electrode are positioned relative to the first and second well regions such that a channel is formed in each of the first and second well regions when the FET is biased in the on state.
H02M 3/155 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs
H02M 3/04 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques
79.
METHOD FOR FORMING TRENCHES WITH WIDE UPPER PORTION AND NARROW LOWER PORTION
A method for forming a semiconductor structure includes the following steps. A hard mask layer is formed over a semiconductor region. The hard mask layer has inner portions that are thinner than its outer portions, and the inner portions define an exposed surface area of the semiconductor region. A portion of the semiconductor region is removed through the exposed surface area of the semiconductor region. The thinner portions of the hard mask layer are removed to expose surface areas of the semiconductor region underlying the thinner portions. An additional portion of the semiconductor region is removed through all exposed surface areas of the semiconductor region thereby forming a trench having an upper portion that is wider than its lower portion.
A field effect transistor (FET) includes body regions of a first conductivity type over a semiconductor region of a second conductivity type. The body regions form p-n junctions with the semiconductor region. Source regions of the second conductivity type extend over the body regions. The source regions form p-n junctions with the body regions. Gate electrodes extend adjacent to but are insulated from the body regions by a gate dielectric. A carbon-containing region extends in the semiconductor region below the body regions.
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes
81.
STRUCTURE AND METHOD FOR FORMING POWER DEVICES WITH HIGH ASPECT RATIO CONTACT OPENINGS
A field effect transistor (FET) includes body regions of a first conductivity type over a semiconductor region of a second conductivity type. Source regions of the second conductivity type extend over the body regions. Gate electrodes extend adjacent to but are insulated from the body regions by a gate dielectric layer. Contact openings extend into the body regions between adjacent gate electrodes. A seed layer extends along the bottom of each contact opening. The seed layer serves as a nucleation site for promoting growth of conductive fill material. A conductive fill material fills a lower portion of each contact opening. An interconnect layer fills an upper portion of each contact opening and is in direct contact with the conductive fill material. The interconnect layer is also in direct contact with corresponding source regions along upper sidewalls of the contact openings.
A first and a second substrate are bonded together to thereby form a unitary hybrid substrate. Predefined portions of the first substrate are removed to form openings in the first substrate through which surface regions of the second substrate are exposed. A selective epitaxial growth process that is selective with respect to the crystalline orientations of the first and second substrates is carried out to thereby form epitaxial silicon from the exposed surfaces of the second substrate but not from exposed surfaces of the first substrate. The epitaxial silicon formed from the exposed surfaces of the second substrate has the same crystalline orientation as the second substrate.
A field effect transistor includes body regions of a first conductivity type over a semiconductor region of a second conductivity type such that the body regions form p-n junctions with the semiconductor region. Trenches extend through the body region and terminate within the semiconductor region. Source regions of the second conductivity type extend over the body regions adjacent the trenches such that the source regions form p-n junctions with the body regions. A gate dielectric layer lines sidewalls of each trench. A metal liner lines the gate dielectric layer in each trench. A gate electrode comprising metallic material is disposed in each trench.
A trench-gate field effect transistor includes trenches extending into a silicon region of a first conductivity type, and a gate electrodes in each trench. Body regions of second conductivity type extend over the silicon region between adjacent trenches. Each body region forms a first PN junction with the silicon region, and each body region includes a silicon-germanium layer of the second conductivity type laterally extending between adjacent trenches. Source regions of the first conductivity flank the trenches, and each source region forms a second PN junction with one of the body regions. Channel regions extend in the body regions along sidewalls of the trenches between the source regions and a bottom surface of the body regions. The silicon-germanium layers extend into corresponding channel regions to thereby reduce the channel resistance.
Disclosed in this specification is a wireless semiconductor package with multiple dies, at least two of which are attached to a thermally and electrically conductive heat sink. The package provides an efficient means for dissipating heat.
A vertically conducting semiconductor device includes a semiconductor substrate having a topside surface and a backside surface. The semiconductor substrate serves as a terminal of the vertically conducting device for biasing the vertically conducting device during operation. An epitaxial layer extends over the topside surface of the semiconductor substrate but terminates prior to reaching an edge of the semiconductor substrate so as to form a recessed region along a periphery of the semiconductor substrate. An interconnect layer extends into the recessed region but terminates prior to reaching an edge of the semiconductor substrate. The interconnect layer electrically contacts the topside surface of the semiconductor substrate in the recessed region to thereby provide a topside contact to the semiconductor substrate.
A method for obtaining individual dies from a semiconductor structure is disclosed. The semiconductor structure includes a device layer, and the device layer in turn includes active regions separated by predefined spacings. Thick metal is selectively formed on backside of the device layer such that thick metal is formed on backside of active regions but not on backside of the predefined spacings. The semiconductor structure is then cut along the predefined spacings to separate the active regions with thick metal on their backside into individual dies.
B23K 26/14 - Travail par rayon laser, p.ex. soudage, découpage ou perçage en utilisant un écoulement de fluide, p.ex. un jet de gaz, associé au faisceau laser; Buses à cet effet
H01L 21/78 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels
A semiconductor structure includes a monolithically integrated trench FET and Schottky diode. The semiconductor structure further includes a plurality of trenches extending into a semiconductor region. A stack of gate and shield electrodes are disposed in each trench. Body regions extend over the semiconductor region between adjacent trenches, with a source region extending over each body region. A recess having tapered edges extends between every two adjacent trenches from upper corners of the two adjacent trenches through the body region and terminating in the semiconductor region below the body region. An interconnect layer extends into each recess to electrically contact tapered sidewalls of the source regions and the body regions, and to contact the semiconductor region along a bottom of each recess to form a Schottky contact therebetween.
A wire bonding pad over an active area of a semiconductor die has grooves in two orthogonal sections thereof in the top surface of said wire bonding pad.
H01L 21/60 - Fixation des fils de connexion ou d'autres pièces conductrices, devant servir à conduire le courant vers le ou hors du dispositif pendant son fonctionnement
90.
STACKED DUAL-DIE PACKAGES, METHODS OF MAKING, AND SYSTEMS INCORPORATING SAID PACKAGES
A semiconductor die package. It includes a substrate having a first surface and a second surface, a first semiconductor die having its front surface facing the first surface of the substrate, a conductive adhesive disposed between the first semiconductor die and the first surface of the substrate, and a second semiconductor die located on the first semiconductor die. The front surface of second semiconductor die faces away from the first semiconductor die, and the back surface faces toward the first semiconductor die. A plurality of conductive structures electrically couple regions at the front surface of the second semiconductor die to conductive regions at the first surface of the substrate.
A method of forming a semiconductor device on a heavily doped P-type (110) semiconductor layer over a metal substrate includes providing a first support substrate and forming a P-type heavily doped (110) silicon layer overlying the first support substrate. At least a top layer of the first support substrate is removable by a selective etching process with respect to the P-type heavily doped (110) silicon layer. A vertical semiconductor device structure is formed in and over the (110) silicon layer. The vertical device structure includes a top metal layer and is characterized by a current conduction in a ឬ110ᡶ direction. The method includes bonding a second supporting substrate to the top metal layer and removing the first support substrate using a mechanical grinding and a selective etching process to expose a surface of the P-type heavily doped (110) silicon layer and to allow a metal layer to be formed on the surface.
A multichip module buck converter (10) has a high side power mosfet (12), a low side power mosfet (22) and a pre-molded leadframe (40) between the two mosfets for connecting the source of mosfet (12) to the drain of mosfet (22). Clips (14, 16, 18 and 26) carry the source, gate and drain terminals of the mosfet from planes parallel but spaced apart to a common plane.
H02M 3/10 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande
93.
SUPERJUNCTION STRUCTURES FOR POWER DEVICES AND METHODS OF MANUFACTURE
A power device includes an active region and a termination region surrounding the active region. A plurality of pillars of first and second conductivity type are alternately arranged in each of the active and termination regions. The pillars of first conductivity type in the active and termination regions have substantially the same width, and the pillars of second conductivity type in the active region have a smaller width than the pillars of second conductivity type in the termination region so that a charge balance condition in each of the active and termination regions results in a higher breakdown voltage in the termination region than in the active region.
A semiconductor die package. It includes a semiconductor die including a first surface and a second surface opposite the first surface, an optional conductive structure, and a leadframe structure. The leadframe structure comprises a central portion suitable for supporting the semiconductor die, and a plurality of stand-off structures coupled to the central portion of the leadframe structure. The stand-off structures can support the conductive structure, and the conductive structure is attached to the second surface of the semiconductor die.
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
A semiconductor die package is disclosed. The semiconductor die package includes a semiconductor die comprising an input at a first top semiconductor die surface and an output at a second bottom semiconductor die surface. A leadframe having a first leadframe surface and a second leadframe surface opposite the first leadframe surface is in the semiconductor die package and is coupled to the first top semiconductor die surface. A clip having a first clip surface and a second clip surface is coupled to the second bottom semiconductor die surface. A molding material having exterior molding material surfaces covers at least a portion of the leadframe, the clip, and the semiconductor die. The first leadframe surface and the first clip surface are exposed by the molding material, and the first leadframe surface, the first clip surface, and the exterior molding material surfaces of the molding material form exterior surfaces of the semiconductor die package.
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes
A shielded gate field effect transistor includes a trench extending into a semiconductor region. A shield electrode is in a lower portion of the trench, and is insulated from the semiconductor region by a shield dielectric. The shield dielectric comprises first and second dielectric layers, the first dielectric layer extending between the second dielectric layer and the semiconductor region. The second dielectric layer comprises a material which during oxidation process inhibits growth of oxide along surfaces of the semiconductor region covered by the second dielectric layer. An inter-electrode dielectric overlies the shield electrode, and a gate dielectric lines upper trench sidewalls. A gate electrode is in an upper portion of the trench over the inter-electrode dielectric.
An integrated power device module having a leadframe structure with first and second spaced pads and one or more common source-drain leads located between said first and second pads, first and second transistors flip chip attached respectively to said first and second pads, wherein the source of said second transistor is electrically connected to said one or more common source-drain leads, and a first clip attached to the drain of said first transistor and electrically connected to said one or more common source-drain leads. In another embodiment a partially encapsulated power quad flat no-lead package having an exposed top thermal drain clip which is substantially perpendicular to said with a folded stud exposed top thermal drain clip, and an exposed thermal source pad.
H01L 23/42 - Choix ou disposition de matériaux de remplissage ou de pièces auxiliaires dans le conteneur pour faciliter le chauffage ou le refroidissement
98.
DYNAMIC SELECTION OF OSCILLATION SIGNAL FREQUENCY FOR POWER CONVERTER
In one embodiment, a method is provided for providing power to a radio-frequency (RF) component capable of operating under multiple communication standards, wherein each standard has a respective operating frequency. The method includes: receiving a communication standard signal indicative of which of the multiple communication standards the RF component is currently operating under; selecting a frequency for a power converter system in response to the communication standard signal, wherein the selected frequency is higher than a baseband frequency of the current communication standard for the RF component; generating an oscillation signal having the selected frequency; and operating the power converter system with the oscillation signal having the selected frequency to provide power to the RF component, wherein the operation of the power converter system causes minimal interference with the RF component operating under the current communication standard.
H02M 5/00 - Transformation d'une puissance d'entrée en courant alternatif en une puissance de sortie en courant alternatif, p.ex. pour changement de la tension, pour changement de la fréquence, pour changement du nombre de phases
99.
METHODS FOR REDUCING CROSS TALK IN OPTICAL SENSORS
Optical sensors containing reduced amounts of cross talk, as well as methods for making and using such sensors are described. The sensors contain a light absorption coating that is placed on a portion of the external surface of the optical sensor near the detector. This absorption coating reduces the amount of cross talk by reducing the amount of light reflected inside a transparent package of the sensor. As well, the coating can also reduce the amount of ambient and/or stray light that enters the sensor. The coating adds little cost or complexity to the manufacturing process for the sensors, yet reduces the cross talk without substantially increasing the size of the sensor or without increasing any reliability risks. Other embodiments are also described.
G01J 1/20 - Photométrie, p.ex. posemètres photographiques par comparaison avec une lumière de référence ou avec une valeur électrique de référence l'intensité de la valeur mesurée ou de référence étant modifiée jusqu' à égalisation de leurs effets au niveau du détecteur, p.ex. en faisant varier l'angle d'incidence
A field effect transistor is formed as follows. Trenches are formed in a semiconductor region of a first conductivity type. Each trench is partially filled with one or more materials. A dual-pass angled implant is carried out to implant dopants of a second conductivity type into the semiconductor region through an upper surface of the semiconductor region and through upper trench sidewalls not covered by the one or more material. A high temperature process is carried out to drive the implanted dopants deeper into the mesa region thereby forming body regions of the second conductivity type between adjacent trenches. Source regions of the first conductivity type are then formed in each body region.
brevets
