A method for detecting a Direct Memory Access (DMA) memory address violation when testing PCIe devices is disclosed. The method for detecting a DMA memory address violation when testing PCIe devices applies to unintentional and intentional accesses of memory space outside of an area in memory specified by the device driver developed for the device.
G06F 13/28 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant le transfert par rafale, p.ex. acces direct à la mémoire, vol de cycle
G06F 11/22 - Détection ou localisation du matériel d'ordinateur défectueux en effectuant des tests pendant les opérations d'attente ou pendant les temps morts, p.ex. essais de mise en route
G06F 13/42 - Protocole de transfert pour bus, p.ex. liaison; Synchronisation
2.
Method and apparatus for simultaneous protocol and physical layer testing
A method, system, and apparatus for simultaneous physical layer and protocol testing is provided that provides for simultaneous test of many layers of the communication stack at the same time, providing further measurement capability and insight into complex phenomena.
H04L 69/00 - Dispositions, protocoles ou services de réseau indépendants de la charge utile de l'application et non couverts dans un des autres groupes de la présente sous-classe
3.
Method and apparatus for a parallel, metadata-based trace analytics processor
Method and apparatus for a parallel, metadata-based trace analytics processor is disclosed. The trace analytics processor is able to asynchronously parallelize the processing operation and use metadata about each parallel operation intelligently. The result is the ability to get analytics results quickly, efficiently, and in real time.
G06F 9/44 - Dispositions pour exécuter des programmes spécifiques
G06F 11/34 - Enregistrement ou évaluation statistique de l'activité du calculateur, p.ex. des interruptions ou des opérations d'entrée–sortie
G06F 16/907 - Recherche caractérisée par l’utilisation de métadonnées, p.ex. de métadonnées ne provenant pas du contenu ou de métadonnées générées manuellement
In general, the subject matter described in this disclosure can be embodied in methods, systems, and program products for changing the manner in which an input signal is filtered based on a characteristic of an electronic test instrument. The method includes receiving, by the electronic test instrument, user input that modifies a characteristic of a channel of the electronic test instrument, and as a result changing the electronic test instrument from having the first digital filtering configuration to having a second digital filtering configuration, the first digital filtering configuration specifying that all or a majority of digital filtering occurs after the acquisition memory in the channel and the second digital filtering configuration specifying that all or a majority of digital filtering occurs before the acquisition memory in the channel.
G01R 13/02 - Dispositions pour la présentation de variables électriques ou de formes d'ondes pour la présentation sous forme numérique des variables électriques mesurées
5.
Method to test direct memory access (DMA) address capabilities at high address values
A method for detecting a Direct Memory Access (DMA) address capability at high address values when testing PCIe devices is disclosed. The method includes enabling an input/output (I/O) memory management unit (IOMMU); remapping physical addresses to virtual addresses at a high end of an address range; adding a peripheral component interconnect express (PCIe) device; and mapping physical memory addresses to high value memory addresses.
G06F 13/28 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant le transfert par rafale, p.ex. acces direct à la mémoire, vol de cycle
G06F 11/34 - Enregistrement ou évaluation statistique de l'activité du calculateur, p.ex. des interruptions ou des opérations d'entrée–sortie
G06F 11/22 - Détection ou localisation du matériel d'ordinateur défectueux en effectuant des tests pendant les opérations d'attente ou pendant les temps morts, p.ex. essais de mise en route
In general, the subject matter described in this disclosure can be embodied in methods, systems, and program products for characterizing a device under test. An electrical waveform is received from the device under test and sampled to generate an array of data values. User input selects a particular position of the electrical waveform on a display, and identifies a corresponding starting time. A decay of a value at the starting time is identified and the array is analyzed to identify multiple data values that correspond to the decayed value. An ending time is then determined using the multiple data values, and a decay time between the starting time and ending time is determined and presented on a display device.
G01N 27/22 - Recherche ou analyse des matériaux par l'emploi de moyens électriques, électrochimiques ou magnétiques en recherchant l'impédance en recherchant la capacité
H03H 7/01 - Réseaux à deux accès sélecteurs de fréquence
G01R 35/00 - Test ou étalonnage des appareils couverts par les autres groupes de la présente sous-classe
G01R 13/02 - Dispositions pour la présentation de variables électriques ou de formes d'ondes pour la présentation sous forme numérique des variables électriques mesurées
The present disclosure relates to methods and apparatus for testing the true capabilities of devices connected to a computer. Methods consistent with the present disclosure may include generating test commands to send to a data storage device under test while storing information related to the commands sent to the data storage device in a low latency buffer. The low latency buffer may temporarily store command related data while data from a plurality of commands are organized and persistently stored in memory of a persistent data storage device. The low latency buffer may include or be comprised of high speed random access memory and the persistent data storage device may be a solid state drive or hard disk drive. Preferably, the persistent data storage device will store command test sequences that span long periods of time of hours or days.
A method and apparatus for generating a probability density function eye are provided. The method preferably includes the steps of acquiring an input waveform, performing a clock data recovery in accordance with the input waveform to determine one or more expected transition times and defining a plurality of unit intervals of the input waveform in accordance with the one or more expected transition times. One or more values of one or more data points may then be determined in accordance with the input waveform in accordance with the one or more expected transition times, and a category for each unit interval in accordance with its state and its position within the input waveform may also be determined. One or more histograms may then be generated for the determined one or more values for each category of unit intervals.
H04L 7/00 - Dispositions pour synchroniser le récepteur avec l'émetteur
H04B 17/21 - Surveillance; Tests de récepteurs pour la correction des mesures
H04L 7/033 - Commande de vitesse ou de phase au moyen des signaux de code reçus, les signaux ne contenant aucune information de synchronisation particulière en utilisant les transitions du signal reçu pour commander la phase de moyens générateurs du signal de synchronisation, p.ex. en utilisant une boucle verrouillée en phase
10.
Dynamic power supply sensor for multi-power supply applications
In general, the subject matter described in this disclosure can be embodied in a system that implements power supply protection. The system includes first circuitry, second circuitry, a first power supply that is configured to power the first circuitry, and a second power supply that is configured to power the first circuitry and the second circuitry. The system also includes a power supply sensor including an input that is connected to the first power supply, and an output. The system also includes a hysteresis buffer including an input that is connected to the output of the power supply sensor, and an output that is connected to the first circuitry in a configuration that transitions the first circuitry to a protected state as a result of the hysteresis buffer transitioning output states.
H02J 3/18 - Dispositions pour réglage, élimination ou compensation de puissance réactive dans les réseaux
H02J 9/06 - Circuits pour alimentation de puissance de secours ou de réserve, p.ex. pour éclairage de secours dans lesquels le système de distribution est déconnecté de la source normale et connecté à une source de réserve avec commutation automatique
G05F 1/62 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu en utilisant des sources de courant continu en série ou en opposition
G05B 13/02 - Systèmes de commande adaptatifs, c. à d. systèmes se réglant eux-mêmes automatiquement pour obtenir un rendement optimal suivant un critère prédéterminé électriques
A method and apparatus for generating a probability density function eye are provided. The method preferably includes the steps of acquiring an input waveform, performing a clock data recovery in accordance with the input waveform to determine one or more expected transition times and defining a plurality of unit intervals of the input waveform in accordance with the one or more expected transition times. One or more values of one or more data points may then be determined in accordance with the input waveform in accordance with the one or more expected transition times, and a category for each unit interval in accordance with its state and its position within the input waveform may also be determined. One or more histograms may then be generated for the determined one or more values for each category of unit intervals.
H04L 7/033 - Commande de vitesse ou de phase au moyen des signaux de code reçus, les signaux ne contenant aucune information de synchronisation particulière en utilisant les transitions du signal reçu pour commander la phase de moyens générateurs du signal de synchronisation, p.ex. en utilisant une boucle verrouillée en phase
H04B 17/21 - Surveillance; Tests de récepteurs pour la correction des mesures
H04L 7/00 - Dispositions pour synchroniser le récepteur avec l'émetteur
A method and apparatus are provided for calculating s-parameters of a device under test from step waveforms acquired by a time domain network analyzer.
G01R 27/28 - Mesure de l'atténuation, du gain, du déphasage ou des caractéristiques qui en dérivent dans des réseaux électriques quadripoles, c. à d. des réseaux à double entrée; Mesure d'une réponse transitoire
G01R 27/32 - Mesure de l'atténuation, du gain, du déphasage ou des caractéristiques qui en dérivent dans des réseaux électriques quadripoles, c. à d. des réseaux à double entrée; Mesure d'une réponse transitoire dans des circuits comportant des constantes réparties
G06F 19/00 - Équipement ou méthodes de traitement de données ou de calcul numérique, spécialement adaptés à des applications spécifiques (spécialement adaptés à des fonctions spécifiques G06F 17/00;systèmes ou méthodes de traitement de données spécialement adaptés à des fins administratives, commerciales, financières, de gestion, de surveillance ou de prévision G06Q;informatique médicale G16H)
H04L 12/26 - Dispositions de surveillance; Dispositions de test
13.
Noise analysis to reveal jitter and crosstalk's effect on signal integrity
A method and apparatus for generating a probability density function eye are provided. The method preferably includes the steps of acquiring an input waveform, performing a clock data recovery in accordance with the input waveform to determine one or more expected transition times and defining a plurality of unit intervals of the input waveform in accordance with the one or more expected transition times. One or more values of one or more data points may then be determined in accordance with the input waveform in accordance with the one or more expected transition times, and a category for each unit interval in accordance with its state and its position within the input waveform may also be determined. One or more histograms may then be generated for the determined one or more values for each category of unit intervals.
In general, the subject matter described in this disclosure can be embodied in methods, systems, and program products for controlling a protocol analysis device when a code execution breakpoint is encountered. The method includes displaying computer code in a user interface of a software development program. The computer code includes a breakpoint. The computing system receives user input to cause a first hardware device to execute the computer code. The computing system instructs the first hardware device to execute the computer code. The computing system instructs a protocol analysis device that is in communication with the computing system to begin recording data that is transmitted between the first hardware device and a second hardware device. The computing system determines that execution of the computer code has reached the breakpoint and as a result instructs the protocol analysis device to start or stop recording the data.
G06F 9/44 - Dispositions pour exécuter des programmes spécifiques
G06F 11/36 - Prévention d'erreurs en effectuant des tests ou par débogage de logiciel
G06F 3/0484 - Techniques d’interaction fondées sur les interfaces utilisateur graphiques [GUI] pour la commande de fonctions ou d’opérations spécifiques, p.ex. sélection ou transformation d’un objet, d’une image ou d’un élément de texte affiché, détermination d’une valeur de paramètre ou sélection d’une plage de valeurs
15.
Compensating probing tip optimized adapters for use with specific electrical test probes
An adapter as disclosed herein includes at least one transmission path providing an electrical connection between the probing end and the head connection end. The adapter includes a flexible tab-board adapter associated with the probing end of the transmission path, the flexible tab-board adapter for contacting at least one signal testing point. The adapter may further include at least one compensating network positioned substantially near the probing end, the at least one compensating network configured to compensate for parasitics of the adapter.
A method and apparatus is provided for on-the-fly calibration of and correction for time interleave error, including generation of correction data associated with an interleave corrector employed by a system for converting a time-domain input stream, corresponding to samples acquired from an interleaved system of digitizers having impairment due to interleave mismatch, to a time-domain output stream. The method includes determining at least one time-domain acquisition segment; determining at least one frequency-domain acquisition segment; determining at least one frequency-domain block acquisition segment, whereby the frequency-domain block acquisition segment comprises a block of tone values; determining the suitability of the frequency-domain block acquisition segment for use in the generation of adjusted correction data; determining a block dominant tone segment from the frequency-domain block acquisition segment; and determining a block impairment transfer column vector in accordance with the block dominant tone segment and the frequency-domain block acquisition segment.
A compensating resistance adapter spans the distance from a mechanical point of contact of an electrical test probe and at least one signal testing point. The compensating resistance adapter has at least one transmission path extending longitudinally therewith. At least one compensating network is configured with the transmission path and positioned substantially near the probing end thereof. For preferred compensating resistance adapters, the at least one compensating network compensates for inductance caused by the conductive connector adapter. For preferred compensating resistance adapters, the at least one compensating network when used in combination with the electrical test probe is optimized to the signal testing point. Exemplary preferred compensating resistance adapters include a probing blade adapter, a twisted pair adapter, a Y-lead adapter, and a swivel pogo tip pair adapter.
A non-linear digital filtering process is provided whereby slew rate limitation-like phenomena in analog circuitry are compensated. Particularly, a reduction of the signal amplitude with respect to the theoretical size of the signal if linearity had held is avoided. A correct phase is re-established. Customized linear filtering, up-sampling, and down-sampling before and after the non-linear digital processing minimizes the creation of harmonics. The inventive system and method for non-linear processing has few parameters and it is not limited to a polynomial series. A dedicated calibration method is also provided to adapt the value of the parameter for a precise compensation of the right amount of slew rate limitation or other similar compression. Furthermore, a calibration method is shown to adjust existing DSP filtering to accomplish a precise desired filtering even when non-linear corrections may be arbitrarily large.
An apparatus for measuring s-parameters using as few as one pulser and two samplers is described. The apparatus calibrates itself automatically using the internal calibration standards.
G01R 35/00 - Test ou étalonnage des appareils couverts par les autres groupes de la présente sous-classe
G06F 19/00 - Équipement ou méthodes de traitement de données ou de calcul numérique, spécialement adaptés à des applications spécifiques (spécialement adaptés à des fonctions spécifiques G06F 17/00;systèmes ou méthodes de traitement de données spécialement adaptés à des fins administratives, commerciales, financières, de gestion, de surveillance ou de prévision G06Q;informatique médicale G16H)
A field selection graphical user interface (GUI) for use with a protocol analyzer. The GUI allows selecting a source presented by the GUI, selecting a field from a plurality of fields presented by the GUI associated with the selected source, defining one or more preconditions associated with the selected field from a plurality of preconditions presented by the GUI relevant to the selected field, and calculating a field layout in accordance with the selected field and defined one or more preconditions. The GUI further allows selecting a second field from the plurality of fields presented by the GUI associated with the selected source, defining one or more preconditions associated with the selected second field from a plurality of preconditions presented by the GUI relevant to the selected second field, and calculating a field layout in accordance with the selected field and the second field.
A complex acquisition system and method for synchronizing components thereof. The complex acquisition system further including a master acquisition module. The master acquisition module further including an analog to digital acquisition signal generator for generating an analog to digital acquisition signal, a memory acquisition signal generator for generating a memory acquisition signal, a delay calibration signal for generating a delay calibration signal, a step source signal generator for generating a step source signal, and a synchronization module. The complex acquisition system further includes a plurality of slave acquisition modules, each also including a synchronization module. The complex acquisition system additionally includes a distribution system for distributing each of the analog to digital acquisition signal, memory acquisition signal, delay calibration signal and step source signal to each of the synchronization modules in the master and plurality of slave acquisition modules.
A method and an apparatus for performing link equalization testing via a physical layer test and measurement system. The system includes a protocol aware test apparatus for transmitting testing data, a device under test for receiving the transmitted testing data, and an oscilloscope for receiving an output waveform from the device under test. The protocol aware test apparatus selects a first of a plurality of preset values, sends an equalization signal from the protocol aware test apparatus to the device under test, and changes a speed of communication to a predetermined speed and sends a compliance pattern to the device under test after placing the device under test in a loopback mode. A waveform output from the device under test is captured by the oscilloscope, and is analyzed to determine compliance of the device under test with a predetermined link equalization speed in accordance with a predetermined protocol.
A locater tool for positioning a support device for supporting a test probe head or a test probe tip, the locater tool including a template, means for indicating a support device position associated with the template, and means for indicating an achievable probing zone on a surface having connection points when the support device is in the support device position. The locater tool may be a device-attachable locater tool or a pre-positioning locater tool.
G01R 31/01 - Passage successif d'articles similaires aux tests, p.ex. tests "tout ou rien" d'une production de série; Test d'objets en certains points lorsqu'ils passent à travers un poste de test
A complex acquisition system and method for synchronizing components thereof. The complex acquisition system further including a master acquisition module. The master acquisition module further including an analog to digital acquisition signal generator for generating an analog to digital acquisition signal, a memory acquisition signal generator for generating a memory acquisition signal, a delay calibration signal for generating a delay calibration signal, a step source signal generator for generating a step source signal, and a synchronization module. The complex acquisition system further includes a plurality of slave acquisition modules, each also including a synchronization module. The complex acquisition system additionally includes a distribution system for distributing each of the analog to digital acquisition signal, memory acquisition signal, delay calibration signal and step source signal to each of the synchronization modules in the master and plurality of slave acquisition modules.
A method is provided for de-embedding fixtures and/or probes from measurements of devices where probes and fixtures are connected between the ports of a network analysis instrument and a device-under-test.
G01R 31/00 - Dispositions pour tester les propriétés électriques; Dispositions pour la localisation des pannes électriques; Dispositions pour tests électriques caractérisées par ce qui est testé, non prévues ailleurs
G01R 35/00 - Test ou étalonnage des appareils couverts par les autres groupes de la présente sous-classe
G01R 27/28 - Mesure de l'atténuation, du gain, du déphasage ou des caractéristiques qui en dérivent dans des réseaux électriques quadripoles, c. à d. des réseaux à double entrée; Mesure d'une réponse transitoire
27.
Method and apparatus for multiple trigger path triggering
A method and apparatus for determining a trigger in a test and measurement apparatus are provided. The method comprises the steps of loading a first trigger configuration to a first trigger element of the test and measurement apparatus and loading a second trigger configuration to a second trigger element of the test and measurement apparatus so that these trigger elements operate substantially simultaneously, It is then determined whether the input signal generates a trigger in accordance with the one or more trigger configurations.
G06F 19/00 - Équipement ou méthodes de traitement de données ou de calcul numérique, spécialement adaptés à des applications spécifiques (spécialement adaptés à des fonctions spécifiques G06F 17/00;systèmes ou méthodes de traitement de données spécialement adaptés à des fins administratives, commerciales, financières, de gestion, de surveillance ou de prévision G06Q;informatique médicale G16H)
A locater tool for positioning a support device for supporting a test probe head or a test probe tip, the locater tool including a template, means for indicating a support device position associated with the template, and means for indicating an achievable probing zone on a surface having connection points when the support device is in the support device position. The locater tool may be a device-attachable locater tool or a pre-positioning locater tool.
G01R 31/01 - Passage successif d'articles similaires aux tests, p.ex. tests "tout ou rien" d'une production de série; Test d'objets en certains points lorsqu'ils passent à travers un poste de test
29.
Probing blade with conductive connector for use with an electrical test probe
A conductive connector includes a flexible-deflectable extension having a probing end and a head connection end. A conductive transmission path extends between the probing end and the head connection end. A pogo-rotational-action pin is electrically connected to the transmission path at the head connection end of the flexible-deflectable extension.
A system and method for performing a time domain reflectometry measurement. The system includes a coherent interleaved sampling timebase, a sampling strobe generator for generating one or more sampling strobes in accordance with the coherent interleaved sampling timebase, a time domain reflectometry sampling strobe generator for generating one or more time domain reflectometry strobes in accordance with one or more of the generated sampling strobes; and a sampling module for sampling a time domain reflectometry signal in accordance with one or more of the one or more generated sampling strobes and one or more of the one or more generated time domain reflectometry strobes. The system further includes an analog to digital converter for analog to digital converting the samples of the time domain reflectometry signal and a memory for storing the converted samples of the time domain reflectometry signal.
A method and apparatus are provided for the removal of significant broad-band noise from waveforms acquired for time domain network analysis. The method may include the steps of providing the noisy waveform as an input waveform, determining a frequency domain noise shape associated with the input waveform, calculating a wavelet domain noise shape from the frequency domain noise shape, calculating a discrete wavelet transform of the input waveform to form a wavelet domain waveform, and estimating the noise statistics from the wavelet domain waveform. A threshold may be calculated from the estimated noise statistics and the wavelet domain noise shape, and the threshold may be applied to the wavelet domain waveform to form a denoised wavelet domain waveform. Finally, an inverse discrete wavelet transform of the denoised wavelet domain waveform may be calculated to form a denoised waveform.
G01R 29/26 - Mesure du coefficient de bruit; Mesure de rapport signal-bruit
G06F 19/00 - Équipement ou méthodes de traitement de données ou de calcul numérique, spécialement adaptés à des applications spécifiques (spécialement adaptés à des fonctions spécifiques G06F 17/00;systèmes ou méthodes de traitement de données spécialement adaptés à des fins administratives, commerciales, financières, de gestion, de surveillance ou de prévision G06Q;informatique médicale G16H)
G06F 17/18 - Opérations mathématiques complexes pour l'évaluation de données statistiques
32.
Method and apparatus for synchronization of test and measurement apparatuses
A synchronization apparatus and method for synchronizing a plurality of test and measurement apparatuses or signal generators are provided. A trigger selector is provided or for selecting from a plurality of triggers to be provided to the plurality of test and measurement apparatuses. A trigger enabled input is also provided for receiving a trigger enabled signal from each of the plurality of test and measurement apparatuses and a synchronizing block is provided for generating a single synchronized time stamp signal with the selected trigger and the trigger enabled inputs. A plurality of trigger outputs are also provided for providing the time stamp signal to a trigger input of each of the plurality of test and measurement apparatuses.
An apparatus for measuring s-parameters using as few as one pulser and two samplers is described. The apparatus calibrates itself automatically using the internal calibration standards.
G06F 19/00 - Équipement ou méthodes de traitement de données ou de calcul numérique, spécialement adaptés à des applications spécifiques (spécialement adaptés à des fonctions spécifiques G06F 17/00;systèmes ou méthodes de traitement de données spécialement adaptés à des fins administratives, commerciales, financières, de gestion, de surveillance ou de prévision G06Q;informatique médicale G16H)
34.
Time domain reflectometry step to S-parameter conversion
A method and apparatus are provided for calculating s-parameters of a device under test from step waveforms acquired by a time domain network analyzer.
A system for estimating bit error rates (BER) may include using a normalization factor that scales a BER to substantially normalize a Q-scale for a distribution under analysis. A normalization factor may be selected, for example, to provide a best linear fit for both right and left sides of a cumulative distribution function (CDF). In some examples, the normalized Q-scale algorithm may identify means and probabilistic amplitude(s) of Gaussian jitter contributors in the dominant extreme behavior on both sides of the distribution. For such contributors, means may be obtained from intercepts of both sides of the CDF(Qnorm(BER) with the Q(BER)=0 axis, standard deviations (sigmas) may be obtained from reciprocals of slopes of best linear fits, and amplitudes may be obtained directly from the normalization factors. In an illustrative example, a normalized Q-scale algorithm may be used to accurately predict bit error rates for sampled repeating or non-repeating data patterns.
A method and system for measuring the input (loading) impedance of measurement systems using a test fixture. This is done by first measuring the characteristics of an unloaded test fixture to obtain scattering parameters of the test fixture and using a splitting algorithm to calculate the scattering parameters of each transmission line leg of the test fixture. The test fixture is then measured with a measurement system attached. The test fixture effects defined by the scattering parameters are then removed from the measurement to yield the scattering parameters of the measurement system alone (measurement system effects).
G01R 27/32 - Mesure de l'atténuation, du gain, du déphasage ou des caractéristiques qui en dérivent dans des réseaux électriques quadripoles, c. à d. des réseaux à double entrée; Mesure d'une réponse transitoire dans des circuits comportant des constantes réparties
A method is provided for de-embedding measurements from a given network containing mixtures of devices with known and unknown S-parameters given a description of the network and the known S-parameters of the overall system.
G06F 19/00 - Équipement ou méthodes de traitement de données ou de calcul numérique, spécialement adaptés à des applications spécifiques (spécialement adaptés à des fonctions spécifiques G06F 17/00;systèmes ou méthodes de traitement de données spécialement adaptés à des fins administratives, commerciales, financières, de gestion, de surveillance ou de prévision G06Q;informatique médicale G16H)
G01R 27/28 - Mesure de l'atténuation, du gain, du déphasage ou des caractéristiques qui en dérivent dans des réseaux électriques quadripoles, c. à d. des réseaux à double entrée; Mesure d'une réponse transitoire
A method and apparatus for capturing an analog waveform on a serial bus. The method comprises the steps of designating a predetermined digital data sequence, decoding a serial data signal carried on a serial data bus, and comparing the decoded serial data signal to the predetermined digital data sequence. When it is determined that a portion of the decoded serial data matches the predetermined digital data sequence, the portion of the serial data signal corresponding to the matching portion of the decoded serial data signal is marked.
A method and apparatus for generating one or more transfer functions for converting waveforms. The method comprises the steps of determining a system description, representative of a circuit, comprising a plurality of system components, each system component comprising at least one component characteristic, the system description further comprising at least one measurement node and at least one output node, each of the at least one measurement nodes representative of a waveform digitizing location in the circuit. One or more transfer functions are determined for converting a waveform from one or more of the at least one measurement nodes to a waveform at one or more of the at least one output nodes. The generated transfer functions are then stored in a computer readable medium.
G06F 19/00 - Équipement ou méthodes de traitement de données ou de calcul numérique, spécialement adaptés à des applications spécifiques (spécialement adaptés à des fonctions spécifiques G06F 17/00;systèmes ou méthodes de traitement de données spécialement adaptés à des fins administratives, commerciales, financières, de gestion, de surveillance ou de prévision G06Q;informatique médicale G16H)
A method and an apparatus for testing the physical layer of high speed serial communication devices and systems with protocol awareness is disclosed. The apparatus comprises of two major blocks: a General Purpose Platform (GPP) and an Analog Front End (AFE). Physical layer testing is divided into two sets of testing procedures: Receiver and Transmitter testing. This test system can be used in a traditional BERT setting where the test system commands the Device Under Test (DUT) to be placed into either a loop back mode, or into a more advanced mode where the test system is communicating with the DUT on a protocol level and counts the frame error ratio (FER). This FER is protocol dependent and each protocol receiver has its own way of reporting transmission errors to the transmitter. The protocol awareness of this invention is capable of detecting such a level of errors.
A conductive connector includes a flexible-deflectable extension having a probing end and a head connection end. A conductive transmission path extends between the probing end and the head connection end. A pogo-rotational-action pin is electrically connected to the transmission path at the head connection end of the flexible-deflectable extension.
G01R 31/02 - Essai des appareils, des lignes ou des composants électriques pour y déceler la présence de courts-circuits, de discontinuités, de fuites ou de connexions incorrectes de lignes
In exemplary embodiments, a waveform processor system may update pixel state information as a function of current pixel state information (e.g., intensity, color) by comparing a randomized value to a set of predetermined threshold values that correspond to different permitted pixel states. In an illustrative example, each time a display screen is updated, the image may represent multiple (e.g., 2000) triggered sweeps of the waveform. For each triggered sweep, the waveform data is associated with specific pixels on the display screen. To determine how to update each pixel's state (e.g., brightness, color) for the next screen update, each waveform hit on a pixel may initiate a comparison between a randomized value (e.g., pseudorandom number) and the predetermined threshold value for the pixel's current pixel state. In some examples, the pixel state may be increased to the next level if the randomized value exceeds the predetermined threshold value.
A method and apparatus for determining a trigger in a test and measurement apparatus are provided. The method comprises the steps of loading a first trigger configuration to a first trigger element of the test and measurement apparatus and loading a second trigger configuration to a second trigger element of the test and measurement apparatus so that these trigger elements operate substantially simultaneously. It is then determined whether the input signal generates a trigger in accordance with the one or more trigger configurations.
G06F 19/00 - Équipement ou méthodes de traitement de données ou de calcul numérique, spécialement adaptés à des applications spécifiques (spécialement adaptés à des fonctions spécifiques G06F 17/00;systèmes ou méthodes de traitement de données spécialement adaptés à des fins administratives, commerciales, financières, de gestion, de surveillance ou de prévision G06Q;informatique médicale G16H)
A method and apparatus for determining a trigger in a test and measurement apparatus are provided. The method includes the steps of indicating one or more anomalies to be found, loading a first trigger configuration to the test and measurement apparatus and determining for a first predetermined time period whether an input signal generates a trigger related to one or more of the one or more anomalies. A second trigger configuration is loaded to the test and measurement apparatus upon the conclusion of the first predetermined time, and for a second predetermined time it is determined whether the input signal generates a trigger related to one or more of the one or more anomalies.
G06F 19/00 - Équipement ou méthodes de traitement de données ou de calcul numérique, spécialement adaptés à des applications spécifiques (spécialement adaptés à des fonctions spécifiques G06F 17/00;systèmes ou méthodes de traitement de données spécialement adaptés à des fins administratives, commerciales, financières, de gestion, de surveillance ou de prévision G06Q;informatique médicale G16H)
G01R 23/16 - Analyse de spectre; Analyse de Fourier
A method and apparatus for displaying information on a device acquiring data is provided. The method includes the steps of receiving an input data, generating a version of the received input data to be displayed in accordance with one or more display parameters and displaying the generated version of the received input data. A requested change in one or more display parameters is received and the requested change of the one or more display parameters is implemented on the displayed data. Processing continues on the further received input data in accordance with the requested change in the one or more display parameters and the display is ultimately updated with the processed further received input data.
A probe for probing an electrical device under test is provided. The probe comprises a selectively positionable door defining a recessed compartment and a light source positioned within the recessed compartment. When the door is in a first position, the compartment is closed, and when the door is in a second position, the compartment is opened. When opened, the light source is reflected from a reflective surface of the door to illuminate a device being probed. The door may further comprise a magnifying element to allow for magnification of the area being probed by a user.
G01R 31/02 - Essai des appareils, des lignes ou des composants électriques pour y déceler la présence de courts-circuits, de discontinuités, de fuites ou de connexions incorrectes de lignes
47.
Method and apparatus for calibrating equalizers without knowledge of the data pattern being received
A method and apparatus for calibrating an equalizer. The method comprises the steps of defining one or more equalization parameters and calculating a bit error rate of a signal for one or more values of a first of the one or more equalization parameters by counting at least one of running disparity errors and incorrect symbol errors. A value for the first of the one or more equalization parameters which provides the lowest bit error rate is set.
A high-speed arbitrary waveform generator (AWG) that utilizes multiple digital-to-analog converters (D/A converters) and overcomes bandwidth limitations of individual D/A converters to produce high-speed waveforms.
A method of digitizing an analog signal is provided, comprising the steps of separating the analog signal spanning a frequency range into a plurality of frequency bands, and then translating at least one of the signals to a lower frequency band in accordance with a local oscillator and digitizing the at least one translated signal with digitizing elements having a frequency range less than the analog signal frequency range. A fixed relationship of the phase of the local oscillator and a repetitive signal generated in accordance with a writing to a circular buffer of the digitized representation of the at least one of the plurality of frequency bands is then defined. Signals corresponding to the other of the plurality of frequency bands are digitized and written to corresponding circular buffers. Finally, a digital representation of the analog signal is formed from the digitized signals.
G01R 23/00 - Dispositions pour procéder aux mesures de fréquences; Dispositions pour procéder à l'analyse de spectres de fréquences
G06F 17/00 - TRAITEMENT ÉLECTRIQUE DE DONNÉES NUMÉRIQUES Équipement ou méthodes de traitement de données ou de calcul numérique, spécialement adaptés à des fonctions spécifiques
A waveform processing system performs operations that may include identifying a location of a specified bit pattern within a coherently sampled repeating pattern input signal. In some examples, multiple periods of a repeating pattern signal are acquired using coherent sampling techniques such as, for example, coherent interleaved sampling (CIS). In such examples, the sampled waveform may be converted to a binary pattern that can be searched to locate a match to a predetermined or user-specified bit pattern. In one illustrative example, the identified location may be used to display the sampled waveform. In another example, the identified location may be used to measure pattern-dependent jitter of the sampled waveform.
Methods for processing waveforms may include decimating an over-sampled waveform by identifying samples for which the sample's position within a data period indicates that is closest to a selected time within a data period. In some example applications, the selected time may be determined as a preferred time to sample the waveform within a data period. In an illustrative example, a sequence of samples representing an over-sampled waveform may be reduced by identifying a sample in each data period that is closest in time to the selected time. In another illustrative example, a sample within each data period may be identified if it falls within a range that is a function of the selected time within the data period and an integral ratio of a sample period to the data period. The identified samples may be used to reconstruct the original waveform with fewer samples than the over-sampled waveform.
H03M 7/00 - Conversion d'un code, dans lequel l'information est représentée par une séquence donnée ou par un nombre de chiffres, en un code dans lequel la même information est représentée par une séquence ou par un nombre de chiffres différents
A method and apparatus for capturing an analog waveform on a serial bus. The method comprises the steps of designating a predetermined digital data sequence, decoding a serial data signal carried on a serial data bus, and comparing the decoded serial data signal to the predetermined digital data sequence. When it is determined that a portion of the decoded serial data matches the predetermined digital data sequence, the portion of the serial data signal corresponding to the matching portion of the decoded serial data signal is marked.
A device emulator configured to emulate an electronic device to test a computing device. The device emulator includes a plurality of read-write registers that are user configurable to include a set of read registers and a set of write registers, wherein the set of write registers are configured to receive a plurality of requests from the computing device, and wherein the set of read registers are configured to transfer one or more conditional responses of a plurality of conditional responses to the computing device based on the requests; a set of control logic configured to receive the requests from the set of write registers and transfer the conditional responses to the set of read registers; and a circuit device that includes the read-write registers and the set of control logic, wherein the circuit device is configured to operate the control logic to emulate the electronic device.
G06F 9/46 - Dispositions pour la multiprogrammation
G06F 3/00 - Dispositions d'entrée pour le transfert de données destinées à être traitées sous une forme maniable par le calculateur; Dispositions de sortie pour le transfert de données de l'unité de traitement à l'unité de sortie, p.ex. dispositions d'interface
G06F 9/455 - Dispositions pour exécuter des programmes spécifiques Émulation; Interprétation; Simulation de logiciel, p.ex. virtualisation ou émulation des moteurs d’exécution d’applications ou de systèmes d’exploitation
54.
Method of compensating for deterministic jitter due to interleave error
A system and method for compensation of deterministic jitter in measurements made when utilizing a plurality of time interleaved analog-to-digital converters (ADCs). The system includes edge timing measurement error information for each of the plurality of time interleaved ADCs and a processing element for converting a measured edge time of one or more edges of a waveform into a corrected edge time. The processing element determines the corrected edge time by subtracting the edge timing measurement error corresponding to one or more of the time interleaved ADCs.
A waveform processing system may include a compensation circuit to adjust a voltage supplied to an output stage, wherein a supplied voltage is controlled to substantially maintain constant power dissipation in the output stage, and wherein the compensation circuit is configurable independently from the amplification stage. In an illustrative embodiment, a control circuit may be independently configurable with respect to an amplifier that generates a signal for the output stage, and the control circuit may bias a compensation circuit that provides thermal tail compensation for an output stage transistor. In some embodiments, the bias may operate the compensation circuit (i) to maintain a substantially constant power condition in the output stage transistor to substantially reduce thermal tail effects, and (ii) to maintain the output stage transistor in an unsaturated operating condition.
H03F 3/04 - Amplificateurs comportant comme éléments d'amplification uniquement des tubes à décharge ou uniquement des dispositifs à semi-conducteurs comportant uniquement des dispositifs à semi-conducteurs
56.
Common mode regulation for thermal tail compensation
A waveform processing system, and associated methods and apparatus, may include a common mode feedback compensation circuit to adjust a voltage supplied to a differential circuit so as to substantially reduce or eliminate signal distortion associated with thermal tails. In an illustrative example, a feedback circuit may control a supply voltage to maintain a common mode voltage at the collectors of the input transistors of a differential amplifier. For example, the feedback may compensate for component tolerances and/or temperature changes that may cause the cause the input transistors to operate away from a nominal constant power operating point. In some embodiments, the differential circuit and common mode feedback compensation circuit may be configured to substantially reduce thermal tail effects by controlling the supply voltage to maintain a substantially constant power condition for the input transistors.
A method and apparatus for correcting for deterministic jitter in a sequential sampling timebase. The value of a fine analog delay is held at a substantially constant nominal rate during a duration of a counting of a digital clock. A time difference between a trigger at which a fine analog delay starts measuring time and the occurrence of a digital pulse of a stable clock used to count a coarse delay is measured. An input waveform is sampled at a sample time having a nominal delay time. After sampling, a desired compensation time is provided for the sample of the input waveform in accordance with combinations of three independent variables defining a calibration table. The waveform is reconstructed by shifting a delay time of a sampled value of the input waveform from its nominal delay time in accordance with a value defined by the calibration table.
In one implementation, a termination circuit may include a variable resistance circuit that comprises a resistance network in which the resistance of a parallel combination of two complementary transistors of opposite types is substantially independent of the drain-to-source voltages of the transistors when the gate-to-source voltages of the transistors are substantially equal in magnitude and opposite in sign. In various examples, the network may include a resistor in parallel and/or series with the transistors. Some implementations may adjust a resistance of the network in response to a digital-to-analog converter output signal. In another implementation, an integrated circuit may include a termination stage with an integrated resistor in parallel or series with a circuit having a tunable impedance. In an illustrative embodiment, relative channel width of the first and second transistors may be selected to realize substantially complementary characteristics for drain-to-source voltage vs. drain-to-source resistance.
A method and apparatus for generating one or more transfer functions for converting waveforms. The method comprises the steps of determining a system description, representative of a circuit, comprising a plurality of system components, each system component comprising at least one component characteristic, the system description further comprising at least one measurement node and at least one output node, each of the at least one measurement nodes representative of a waveform digitizing location in the circuit. One or more transfer functions are determined for converting a waveform from one or more of the at least one measurement nodes to a waveform at one or more of the at least one output nodes. The generated transfer functions are then stored in a computer readable medium.
G06F 19/00 - Équipement ou méthodes de traitement de données ou de calcul numérique, spécialement adaptés à des applications spécifiques (spécialement adaptés à des fonctions spécifiques G06F 17/00;systèmes ou méthodes de traitement de données spécialement adaptés à des fins administratives, commerciales, financières, de gestion, de surveillance ou de prévision G06Q;informatique médicale G16H)
60.
High speed signal transmission line having reduced thickness regions
Apparatus and associated systems and methods may include one or more features for high speed transmission line structures that may substantially reduce signal degradation due to effects, such as dielectric loss, parasitic capacitance, cross-talk, and/or reflections. For example, one such feature may include a dielectric layer having a reduced thickness within at least a part of a region that extends between two conductors fabricated on a PCB (printed circuit board). In some embodiments, the dielectric layer may include a solder mask layer that is partially or substantially absent in the region between two coplanar conductors. In another embodiment, a substrate layer made of a dielectric material may include a trench in the region between the two conductors. Another such feature, for example, may include a conductor having vias spaced less than a quarter wavelength apart to substantially reduce resonance effects on propagating high frequency signals.
Apparatus and associated systems and methods may relate to a wide bandwidth cable assembly that may include an active amplification stage to receive high frequency signals (e.g., 1 GHz or above) through a transmission line extending distally to a passive, high density signal probe stage. In an illustrative example, the probe stage may receive multiple analog or digital signals from a device under test (DUT). In some embodiments, the probe stage may include probe pins with integrated series resistance to control signal loading, and an equalizer to shape the signal path's frequency response. The amplification stage may provide a virtual ground reference for a termination impedance that may match the transmission line's impedance and may connect in series with a feedback impedance. In one example, a minimally invasive probe head may facilitate measurement of multiple channels of a high speed data bus with minimal signal distortion and/or attenuation.
G01R 23/00 - Dispositions pour procéder aux mesures de fréquences; Dispositions pour procéder à l'analyse de spectres de fréquences
G01R 31/02 - Essai des appareils, des lignes ou des composants électriques pour y déceler la présence de courts-circuits, de discontinuités, de fuites ou de connexions incorrectes de lignes
H04B 15/00 - Suppression ou limitation du bruit ou des interférences
A method and apparatus for testing a data transfer system. The method comprises the steps of storing a first table, the first table noting at least a time of issuance of at least one command and a time of completion of the command and comparing the time of issuance of the command and the time of completion of the command. A timeout condition is registered if the processor determines that a time longer than a predetermined time elapsed between the time of issuance of the command and the time of completion of the command.
G01R 31/28 - Test de circuits électroniques, p.ex. à l'aide d'un traceur de signaux
H03M 13/00 - Codage, décodage ou conversion de code pour détecter ou corriger des erreurs; Hypothèses de base sur la théorie du codage; Limites de codage; Méthodes d'évaluation de la probabilité d'erreur; Modèles de canaux; Simulation ou test des codes
A guide for tip to transmission path contact includes a guide insulator having at least one passageway defined therein. Each passageway has a tip passageway end and a transmission path passageway end. The tip passageway end is suitable for at least partially accommodating the tip of a probing head. The transmission path passageway end is suitable for at least partially accommodating a transmission path of a circuit board component. The tip contacts a transmission path through a passageway when the transmission path is positioned in the transmission path passageway end and the tip is positioned within the tip passageway end.
A method and apparatus for acquiring an analog signal. The method of the invention comprising the steps of acquiring a first portion of the analog signal by a first channel, the first portion of the analog signal spanning a first bandwidth range, and acquiring a second portion of the analog signal by a second channel, the second portion of the analog signal spanning a second bandwidth range adjacent the first bandwidth range. At least one spur in the signal acquired by the first channel corresponding to a portion of the analog signal that should have properly been acquired by the second channel is offset with an opposite spur in the second channel.
A test probe tip constructed substantially from resistive material. The resistive material is made of resistive conducting material substantially enclosed in and dispersed throughout encapsulating material. The test probe tip has a probing end for probing electronic circuitry and a connection end for interfacing with a probing head. The resistive conducting material forms at least one path through the encapsulating material from the probing end to the connection end. The resistive conducting material may be a plurality of longitudinally-extending resistive/conductive members or a plurality of particulate resistive/conductive members.
G01R 31/02 - Essai des appareils, des lignes ou des composants électriques pour y déceler la présence de courts-circuits, de discontinuités, de fuites ou de connexions incorrectes de lignes
Apparatus and associated systems and methods may relate to a data traffic modification system that may receive operating code developed using a graphical user interface (GUI) that permits substantially real-time editing of instructions that have been determined to include errors. In various implementations, a data traffic modification device may selectively modify data traffic upon the occurrence of a predetermined condition. In one illustrative example, operating code may be developed by sequentially editing individual instructions. Upon modifying each instruction, the validity of the operating code with the edited instruction may be checked, and the GUI may display the updated code substantially in real time during an editing session. The GUI may display an indication of the validity status of the set of instructions. In some embodiments, the user may be permitted to continue editing the code within the GUI while the set of instructions contains errors.
A time domain measurement method and apparatus are provided. The method comprises the steps of acquiring a burst signal and determining a plurality of min/max values of the burst signal. The determined min values are connected to generate a lower floor outline. The determined max values are connected to generate an upper roof outline. The burst signal is displayed along with the lower and upper outlines.
G01R 15/00 - MESURE DES VARIABLES ÉLECTRIQUES; MESURE DES VARIABLES MAGNÉTIQUES - Détails des dispositions pour procéder aux mesures des types prévus dans les groupes , ou
G01R 13/00 - Dispositions pour la présentation de variables électriques ou de formes d'ondes
68.
Pause request processing for data traffic modification
Apparatus and associated systems and methods may relate to a data traffic modification system that may include a processing module to handle SATA-compliant data transfers in which a source device or a target device issues requests to pause and subsequently to resume the data transfer. In various implementations, a data traffic modification device may selectively modify data traffic upon the occurrence of a predetermined condition. In one illustrative example, if a target device for the data transfer issues a pause request (e.g., to prevent a buffer overflow), the data traffic modification device may generate a pause acknowledge signal to the target device within a response time specified by the protocol. In another illustrative example, if a source device for the data transfer issues a pause request, the data traffic modification device may generate a pause acknowledge signal to the source device within the response time specified by the protocol.
A substantially planar (in an x-y plane) probing tip includes a probing tip body and two test point connector projections. The first test point connector projection is movably attached to the body to allow motion therebetween. The second test point connector projection is also attached to the body. The motion actuator actuates motion that the motion translator, in turn, converts to move at least one of the test point connector projection connection ends in a third dimension out of the x-y plane. The probing tip has an open position in which the relative distance between the test point connector projections is relatively large. The probing tip also has a closed position in which the relative distance between the test point connector projections is relatively small. In one alternative preferred embodiment, the second test point connector projection body end is also movably attached to the body to allow motion therebetween.
G01R 31/02 - Essai des appareils, des lignes ou des composants électriques pour y déceler la présence de courts-circuits, de discontinuités, de fuites ou de connexions incorrectes de lignes
A system for estimating bit error rates (BER) may include using a normalization factor that scales a BER to substantially normalize a Q-scale for a distribution under analysis. A normalization factor may be selected, for example, to provide a best linear fit for both right and left sides of a cumulative distribution function (CDF). In some examples, the normalized Q-scale algorithm may identify means and probabilistic amplitude(s) of Gaussian jitter contributors in the dominant extreme behavior on both sides of the distribution. For such contributors, means may be obtained from intercepts of both sides of the CDF(Qnorm(BER) with the Q(BER)=0 axis, standard deviations (sigmas) may be obtained from reciprocals of slopes of best linear fits, and amplitudes may be obtained directly from the normalization factors. In an illustrative example, a normalized Q-scale algorithm may be used to accurately predict bit error rates for sampled repeating or non-repeating data patterns.
A conductive connector includes a bendable, shape retainable extension having a head connector at one end and a test point connector at the opposite end. The head connector is for connecting the conductive connector to a probing head. The test point connector is for making electrical contact with testing points. The present invention may be part of a probing system that includes a probing head. The present invention may also include a method for using the conductive connector.
G01R 31/02 - Essai des appareils, des lignes ou des composants électriques pour y déceler la présence de courts-circuits, de discontinuités, de fuites ou de connexions incorrectes de lignes
A method, apparatus and computer program for decoding a data stream. The method comprises the steps of acquiring an analog data signal, determining an initial polarity of the analog data signal, determining a threshold transition level, determining a plurality of transition edges where the analog data signal crosses the threshold transition level, and determining the number of unit intervals between each pair of transition edges. A binary value is assigned to each of the unit intervals, and the binary values are displayed to a user.
An apparatus and method for selecting and recording multi-directional communication packet traffic in a compact manner in realtime while maintaining relative time between the selected packets passing in one direction and the selected packets passing in another direction. The apparatus includes a protocol interface, a block datapath, a record resource, and a trace merge memory. The protocol interface receives X and Y channel packets with interspersed idle times, segments the packets into time-aligned X and Y blocks, and eliminates idle times. The block datapath merges the X and Y blocks, then filters unneeded X and Y channel packets by purging the X and Y blocks from those packets. The record resource compares patterns for identifying the unneeded packets and trigger events. The trace merge memory records the time-aligned filtered merged block stream in a compact form for later analysis.
A method and apparatus for generating a statistic based upon a persistence data is provided. The method comprises the steps of defining a plurality of slices of data comprising a persistence data and generating a histogram of the data within each of the plurality of slices. A parameter is measured for each of the generated histograms, and the measured parameters are plotted corresponding to each of the generated histograms.
G09G 5/22 - Dispositions ou circuits de commande de l'affichage communs à l'affichage utilisant des tubes à rayons cathodiques et à l'affichage utilisant d'autres moyens de visualisation caractérisés par l'affichage de caractères ou de signes individuels en utilisant des signaux de commande d'affichage dérivés de signaux codés représentant les caractères ou les signes avec une mémoire de codes de caractères
G06T 11/20 - Traçage à partir d'éléments de base, p.ex. de lignes ou de cercles
Apparatus and associated systems, methods and computer program products relate to isolating horizontal jitter component(s) from vertical jitter component(s). In preferred embodiments, at least one horizontal component of jitter is distinguished from at least one component of vertical jitter by fitting a curve to a digitally acquired waveform, determining the curve slope and statistical variance about the fitted curve over at least one time period, identifying a functional relationship between the variance and slope, and determining therefrom at least one horizontal component of jitter and at least one vertical component of jitter. Random and deterministic jitter components may be aggregated, in certain embodiments, so as to identify a vertical jitter component that reflects both deterministic and random jitter. In preferred implementations, the isolated vertical jitter component is subtracted from a total jitter measurement so as to better approximate actual signal jitter.
An artifact signal correction system may include a mixing component to generate a waveform corresponding to an artifact such as an error tone, whereupon that waveform may be combined with the input waveform to substantially eliminate the artifact. In preferred embodiments, a method and apparatus for reducing spurious tones in systems of mismatched interleaved digitizers due to interleave error is provided. In various embodiments the method may include reversing the frequency content of an input signal, converting the reversed signal into interleave artifact content, delaying the input signal along a parallel path, and then subtracting the interleave content from the delayed input signal.
A method and apparatus for acquiring a signal employing a coherent timebase are provided. The method comprises the steps of defining a pattern length count of a repetitive pattern in a signal to be acquired, defining a number of samples per unit interval, and providing data strobes synchronous to a coherent timebase. An arbitrary one of the data strobes is designated as a timing for a potential trigger. A number of subsequent data strobes is counted in accordance with the pattern length count times the samples per unit interval and a portion of the signal corresponding to the pattern length count times the samples per unit interval is acquired beginning at a point in the signal defined by the designated arbitrary data strobe. Thereafter one or more additional portions of the signal are acquired corresponding to the pattern length count times the samples per unit interval at a point in the signal defined by when the number of subsequent data strobes reaches the pattern length count times the samples per unit interval.
A method and apparatus for correcting for deterministic jitter in a sequential sampling timebase. The value of a fine analog delay is held at a substantially constant nominal rate during a duration of a counting of a digital clock. A time difference between a trigger at which a fine analog delay starts measuring time and the occurrence of a digital pulse of a stable clock used to count a coarse delay is measured. An input waveform is sampled at a sample time having a nominal delay time. After sampling, a desired compensation time is provided for the sample of the input waveform in accordance with combinations of three independent variables defining a calibration table. The waveform is reconstructed by shifting a delay time of a sampled value of the input waveform from its nominal delay time in accordance with a value defined by the calibration table.
A compensating resistor includes a substrate with a first termination at one end and a second termination at the other end. A frontside resistor is on the frontside of the substrate and extends between the first termination and the second termination. A backside resistor is on the backside of the substrate. One end of the backside resistor is attached to the first termination, but the other end of the backside resistor is free from the second termination. The frontside resistor and the backside resistor are capacitively coupled through the substrate. An alternative embodiment has includes a metal termination pad on the substrate backside to which the free end of the backside resistor connects. The compensating resistor preferably has an attenuation that decreases proportionally to the square root of frequency over the range of frequencies.
G01R 27/04 - Mesure de résistances, de réactances, d'impédances réelles ou complexes, ou autres caractéristiques bipolaires qui en dérivent, p.ex. constante de temps dans des circuits comportant des constantes réparties
G01R 31/02 - Essai des appareils, des lignes ou des composants électriques pour y déceler la présence de courts-circuits, de discontinuités, de fuites ou de connexions incorrectes de lignes
A locking mechanism and method for selectively fixing and allowing movement of a tip portion of a probe relative to a rigid portion of the probe are provided. The mechanism comprises a locking ball joint for selectively locking and allowing relative movement between the tip portion and the rigid portion and a sleeve about the ball joint. The locking ball joint is locked by the placement of the sleeve in a first position, thereby fixing the position of the tip portion relative to the rigid portion, and released by the placement of the sleeve in a second position, thereby allowing movement of the tip portion relative to the rigid portion.
G01R 31/02 - Essai des appareils, des lignes ou des composants électriques pour y déceler la présence de courts-circuits, de discontinuités, de fuites ou de connexions incorrectes de lignes
81.
Use of multiple data comparators in parallel to trigger an oscilloscope on a pattern found in a serial data stream
A method and system are provided for determining a location of a predetermined N bit sequence in a data stream. The method comprises the steps of determining two N bit data words from consecutive bits of the data stream, and providing N, N bit comparators. A first N bits of the two N bit data words is compared with the predetermined N bit data sequence by a first of the N comparators, and a next N bits, starting at a second bit, of the two N bit data words are compared with the predetermined N bit sequence by a second of the N bit comparators. These comparisons are repeated, incrementing the starting bit, until N comparators have been employed and the first through N bits have been employed as the starting bit.
A method and apparatus for displaying an acquired signal on an oscilloscope. The method comprises the steps of acquiring an analog signal, digitizing the analog signal and determining a plurality of samples generated by the digitizing that are to be represented by a same vertical pixel column on a display. Thereafter, a histogram of the values of the determined plurality of samples is generated, and a display characteristic of information displayed in the vertical pixel column is modified based upon the generated values of the histogram.
G09G 5/22 - Dispositions ou circuits de commande de l'affichage communs à l'affichage utilisant des tubes à rayons cathodiques et à l'affichage utilisant d'autres moyens de visualisation caractérisés par l'affichage de caractères ou de signes individuels en utilisant des signaux de commande d'affichage dérivés de signaux codés représentant les caractères ou les signes avec une mémoire de codes de caractères
G06K 9/00 - Méthodes ou dispositions pour la lecture ou la reconnaissance de caractères imprimés ou écrits ou pour la reconnaissance de formes, p.ex. d'empreintes digitales
A method and apparatus for generating a reflection filter. The method comprises the steps of determining an averaged step response of an acquired signal and generating a spectrum response from the averaged step response. A time at which a reflection in the averaged step response begins is determined and information in the averaged step response after the determined time when the reflection begins is replaced with an ideal flat line response to generate a required step response. A spectrum response is generated from the required step response and each frequency point of the spectrum response corresponding to the required step response is divided by each frequency point of the spectrum response corresponding to the averaged step response to generate a spectrum of the reflection filter. The result of the dividing step is processed to generate a reflection filter impulse response.
A method, apparatus and computer program having instructions for storing information in an oscilloscope is provided. The method comprises the steps of storing a screen display in a predetermined format, storing one or more configuration settings associated with the screen display, and storing in memory channel acquisition data associated with the stored screen display. The screen display may also be annotated, the annotation information being stored as well. The stored screen display, one or more associated configuration settings, and stored channel acquisition data, and annotation data, if applicable, may be loaded into the oscilloscope, thereby placing the oscilloscope in the state it was in when the stored data was originally generated.
A method and apparatus for capturing an analog waveform on a serial bus. The method comprises the steps of designating a predetermined digital data sequence, decoding a serial data signal carried on a serial data bus, and comparing the decoded serial data signal to the predetermined digital data sequence. When it is determined that a portion of the decoded serial data matches the predetermined digital data sequence, the portion of the serial data signal corresponding to the matching portion of the decoded serial data signal is marked.
A lossy dielectric device dissipates, absorbs, and/or dampens electric fields. The lossy dielectric device may be used with any transmission path, such as a transmission line or resistor in a probe head. The lossy dielectric device preferably includes a lossy dielectric material contained within a container. The container is positionable and securable substantially adjacent the transmission path to improve the curve of a frequency response. Preferably, the container is insulative, puncture resistant, and thin. In some preferred embodiments, a temporary or permanent connection mechanism is also included.
G01R 31/02 - Essai des appareils, des lignes ou des composants électriques pour y déceler la présence de courts-circuits, de discontinuités, de fuites ou de connexions incorrectes de lignes
A test probe tip constructed substantially from resistive material. The resistive material is made of resistive conducting material substantially enclosed in and dispersed throughout encapsulating material. The test probe has a probing end for probing electronic circuitry and a connection end for interfacing with a probing head. The resistive conducting material forms at least one path through the encapsulating material from the probing end to the connection end. The resistive conducting material may be a plurality of longitudinally extending resistive/conductive members or a plurality of particulate resistive/conductive members.
G01R 31/02 - Essai des appareils, des lignes ou des composants électriques pour y déceler la présence de courts-circuits, de discontinuités, de fuites ou de connexions incorrectes de lignes
88.
Method and system for cascading analyzer trace memories
Cascaded analyzer trace memories are described herein. According to one embodiment, the method comprises receiving a packet stream in a master analyzer and a slave analyzer, wherein the master analyzer includes a first trace memory, and wherein the slave includes a second trace memory. According to one embodiment, the method further comprises determining whether the first trace memory has been filled past a memory address. According to one embodiment, if the first trace memory has not been filled past the memory address, storing one or more packets of the packet stream in the first trace memory. In one embodiment, if the first trace memory has been filled past the memory address, performing the following operations: marking a location in the first trace memory, transmitting a signal to the slave analyzer, and storing one or more packets of the packet stream in the second trace memory.
A method of processing a data signal is provided. The method comprises the steps of acquiring a data signal by an acquisition unit of a test instrument for a predetermined time and storing the data signal in a memory of the test instrument. A clock signal is recovered from the stored data signal, and the stored data signal is sliced into a plurality of data segments of a predetermined length in accordance with the recovered clock signal.
A method and apparatus for displaying substantially noise-free segments of serial data waveforms. The method comprises the steps of dividing an acquired waveform into a plurality of waveform slices and categorizing each of the plurality of waveform slices according to at least a sequence of N bit values prior to a bit value being observed. The waveform slices in each category are then averaged resulting in an average pattern for each category. Each of the averaged patterns is then displayed on a display in an overlayed manner.
A method and apparatus for determining a bit error rate. The method comprises the steps of acquiring a data signal by an acquisition unit of a test instrument for a predetermined period of time, and storing the data signal in a memory of the test instrument. A clock signal is recovered from the stored data signal, and in accordance therewith, the stored data signal is sliced into a plurality of data segments of a predetermined length. Each of said data segments is synchronized to a frame or predetermined pattern to determine a bit error rate thereof.
An apparatus for processing a data signal is provided. The apparatus comprises an acquisition unit of a test instrument for acquiring a data signal for a predetermined time, a memory of the test instrument for storing the data signal, and a clock recovery unit for recovering a clock signal from the stored data signal. A processor slices the stored data signal into a plurality of data segments of a predetermined length in accordance with the recovered clock signal.
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