OPERATING MASTER PROCESSORS IN POWER SAVING MODE
|Date de dépôt||2020-11-16|
|Date de la première publication||2023-02-02|
|Date de publication||2023-02-02|
|Propriétaire||Hewlett-Packard Development Company, L.P. (USA)|
AbrégéTechniques of power management in devices having multi-processor core are described herein. In an example, an ethernet controller of a device comprises a MAC layer module which receives a data packet through a physical network. A multi-processor core coupled to the ethernet controller comprises a first and a second processor. The first and second processor comprise a first driver and a second driver, respectively. The second driver determines that the first processor has entered a power saving mode, receives the data packets directed towards the multi-processor core from the MAC layer module and stores the data packet in a data structure. The econd driver invokes the first driver based on a determination that the data packet is to be handled by the first processor and provides an address of the data structure storing the data packet to the first driver, the data structure being accessible to the first driver.
Classes IPC ?
- G06F 1/3293 - Power saving characterised by the action undertaken by switching to a less power-consuming processor, e.g. sub-CPU
- G06F 9/50 - Allocation of resources, e.g. of the central processing unit [CPU]
- G06F 9/4401 - Bootstrapping