A method includes receiving electrostatic sensor data in a processor of an electronic device from an electrostatic sensor mounted behind a touchscreen of the electronic device and using the electrostatic sensor data to determine when the touchscreen is being used. Based on whether or not the touchscreen is being used, an on-table detection (OTD) algorithm is selected from a plurality of available OTD algorithms. In one or more examples, the OTD algorithm may also be selected based on the current device mode of the electronic device, which may be determined from a lid angle, a screen angle, and a keyboard angle of the electronic device. The selected OTD algorithm is run to determine whether or not the electronic device is located on a stationary or stable surface.
G06F 3/0346 - Pointing devices displaced or positioned by the user; Accessories therefor with detection of the device orientation or free movement in a 3D space, e.g. 3D mice, 6-DOF [six degrees of freedom] pointers using gyroscopes, accelerometers or tilt-sensors
G06F 3/0354 - Pointing devices displaced or positioned by the user; Accessories therefor with detection of 2D relative movements between the device, or an operating part thereof, and a plane or surface, e.g. 2D mice, trackballs, pens or pucks
A device includes a first AND logic gate comprising a first input, a second input, and an output, a second AND logic gate comprising a first input, a second input, and an output, and a first OR logic gate comprising a first input coupled to the output of the first AND logic gate and a second input coupled to the output of the second AND logic gate. A first selection circuit has first and second data inputs, a first control input coupled to the first input of the first AND logic gate and a second control input coupled to the first input of the second AND logic gate. A first D latch includes a data input coupled to an output of the first selection circuit and an activation input coupled to an output of the first OR logic gate and a second D latch includes a data input coupled to the output of the first selection circuit and an activation input coupled to the output of the first OR logic gate.
H03K 19/173 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
The present disclosure concerns overtemperature protection circuit formed inside and on top of a monolithic semiconductor substrate having a surface covered with a gallium nitride layer, comprising:
a first resistor having a first positive temperature coefficient and being arranged in said gallium nitride layer; and
a second resistor having a second temperature coefficient different from the first coefficient.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
The present disclosure concerns a driver of a first e-mode type HEMT power transistor adapted to receiving a maximum voltage of 650 V between its drain and its source, the circuit being formed inside and on top of a monolithic semiconductor substrate having a surface covered with a gallium nitride layer, and comprising at least a second e-mode type transistor adapted to directly transmitting a control voltage to the gate of the first transistor and having an area greater than 5 mm2.
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
The present disclosure concerns a voltage regulation circuit formed inside and on top of a monolithic semiconductor substrate having a surface covered with a gallium nitride layer, comprising: between a first terminal and a second terminal, a first resistor and a first d-mode type HEMT transistor; and between the first terminal and the third terminal, a second d-mode type HEMT transistor; wherein the midpoint between the first resistor and the first transistor is coupled to the gates of the first and second transistors.
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
A sensor package includes a packaging formed by a package bottom, first and second sidewalls extending upwardly from first and second opposite sides of the package bottom, and third and fourth sidewalls extending upwardly from third and fourth opposite sides of the package bottom, the sidewalls and package bottom defining a cavity. An integrated circuit is attached to the package bottom. A plate extends between two of the sidewalls within the cavity and is spaced apart from the package bottom. Sensors are attached to a top surface of the plate on opposite sides of an opening. Wire bondings electrically connect pads on a top face of the sensor to corresponding pads on a top face of the integrated circuit, for example by passing through the opening in the plate or passing past a side end of the plate. A lid extends across and between the sidewalls to close the cavity.
B81B 3/00 - Devices comprising flexible or deformable elements, e.g. comprising elastic tongues or membranes
B81C 1/00 - Manufacture or treatment of devices or systems in or on a substrate
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
7.
SYSTEM FOR MONITORING DEFECTS WITHIN AN INTEGRATED SYSTEM PACKAGE
An integrated electronic system is provided with a package formed by a support base and a coating region arranged on the support base and having at least a first system die, including semiconductor material, coupled to the support base and arranged in the coating region. The integrated electronic system also has, within the package, a monitoring system configured to determine the onset of defects within the coating region, through the emission of acoustic detection waves and the acquisition of corresponding received acoustic waves, whose characteristics are affected by, and therefore are indicative of, the aforementioned defects.
An HV MOSFET device has a body integrating source conductive regions. Projecting gate structures are disposed above the body, laterally offset with respect to the source conductive regions. Source contact regions, of a first metal, are arranged on the body in electric contact with the source conductive regions, and source connection regions, of a second metal, are arranged above the source contact regions and have a height protruding with respect to the projecting gate structures. A package includes a metal support bonded to a second surface of the body, and a dissipating region, above the first surface of the semiconductor die. The dissipating region includes a conductive plate having a planar face bonded to the source connection regions and spaced from the projecting gate structures. A package mass of dielectric material is disposed between the support and the dissipating region and incorporates the semiconductor die. The dissipating region is a DBC-type insulation multilayer.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
9.
ELECTRONIC CIRCUIT COMPRISING A REFERENCE VOLTAGE CIRCUIT AND A START CHECK CIRCUIT
An electronic circuit includes a reference voltage circuit and a circuit for checking the starting operation of the reference voltage circuit. The reference voltage circuit includes a first stack of a first transistor and second transistor receiving first and second control signals, respectively. The start check circuit includes a first elementary test circuit including a second stack of a third transistor and fourth transistor receiving the first and second control signals, respectively. An output of the first elementary test circuit delivers a first binary signal indicative of proper starting operation of the reference voltage circuit.
G05F 1/46 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc
H03K 17/18 - Modifications for indicating state of switch
H03K 17/22 - Modifications for ensuring a predetermined initial state when the supply voltage has been applied
10.
METHOD FOR PERFORMING A CORRECTION OF AN IONOSPHERIC ERROR AFFECTING PSEUDO-RANGE MEASUREMENTS IN A GNSS RECEIVER, CORRESPONDING RECEIVER APPARATUS AND COMPUTER PROGRAM PRODUCT
A method corrects an ionospheric error affecting pseudo-range measurements in a GNSS receiver receiving a plurality of satellite signals from a plurality of satellites of the constellation of satellites. The method is performed in a navigation processing procedure performed at a GNSS receiver, receiving pseudo-range measurements previously calculated by the GNSS receiver obtained from a first carrier signal and a second carrier signal in the satellite signals, in particular in GPS bands L1 and L5. The method includes performing a correction procedure of the pseudo-range measurements including applying to the pseudo-range measurements corrections for predictable errors obtaining corrected pseudo-ranges and applying to the corrected pseudo-range measurements a further ionospheric error correction calculation to obtain further ionospheric error correction values.
G01S 19/07 - Cooperating elements; Interaction or communication between different cooperating elements or between cooperating elements and receivers providing data for correcting measured positioning data, e.g. DGPS [differential GPS] or ionosphere corrections
G01S 19/04 - Cooperating elements; Interaction or communication between different cooperating elements or between cooperating elements and receivers providing carrier phase data
The present disclosure concerns an electronic device formed inside and on top of a monolithic semiconductor substrate having a surface covered with a gallium nitride layer, comprising at least one e-mode type HEMT power transistor adapted to receiving a maximum voltage of 650 V between its drain and its source, and an analog circuit for controlling said power transistor.
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
A device includes a memory and cryptographic processing circuitry coupled to the memory. The memory, in operation, stores one or more lookup tables. The cryptographic processing circuitry, in operation, processes masked data and protects the processing of masked data against side channel attacks. The protecting includes applying masked binary logic operations to masked data using lookup tables of the one or more lookup tables.
STMicroelectronics Design and Application S.R.O. (Czech Republic)
STMicroelectronics (Alps) SAS (France)
Inventor
Vassal, Robin
Andrle, Jiri
Cabaj, Peter
Trouilleau, Cyrille
Abstract
A method is for detecting one or more objects in a detection zone using a time-of-flight sensor. The method includes emitting optical radiation via the emission circuitry of the sensor and subsequently capturing the reflected optical radiation using the reception circuitry. This captured radiation is quantified in terms of photons, and measurement circuitry determines both the amount of these photons and the distance from the sensor to the object(s). An analysis of the photon count, combined with the calculated distance, is used to determine the presence or absence of objects within the detection zone.
A boost DC-DC converter includes a switching network, coupled to an inductor, controlled by a PWM driving signal. A control loop receives a voltage output and provides the PWM driving signal. The control loop generates an error signal as a function of a difference between voltage output voltage and a reference, with the PWM driving signal generated based on the error signal. A low pass filter circuit within the control loop receives the PWM driving signal and provides at least one filtered signal. An adder node of the control loop receives the at least one filtered signal from the low pass filter circuit for addition to the at least one filtered signal. The PWM driving signal is generated as a function of a sum of the filtered signal and the error signal.
H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H02M 3/157 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
A method of manufacturing a chip-sized package includes providing a wafer having a die area formed therein adjacent a front face thereof, with the die area having pads formed thereon. Vias in the wafer are formed to extend between a back face of the wafer and a back side of some of the pads of the die area. Solder pads connected to the vias are formed, and a thermal pad is formed on the back side of the wafer opposite to the die area. Cavities are formed in the back face of the wafer to define pillars extending outwardly from a planar portion of the die area, some of the pillars having the solder pads at a distal end thereof, at least one of the pillars having the thermal pad at a distal end thereof. The wafer is singulated to form a chip-sized package including an integrated circuit die.
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
H01L 23/36 - Selection of materials, or shaping, to facilitate cooling or heating, e.g. heat sinks
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
16.
CAPLESS SEMICONDUCTOR PACKAGE WITH A MICRO-ELECTROMECHANICAL SYSTEM (MEMS)
A semiconductor package that contains an application-specific integrated circuit (ASIC) die and a micro-electromechanical system (MEMS) die. The MEMS die and the ASIC die are coupled to a substrate that includes an opening that extends through the substrate and is in fluid communication with an air cavity positioned between and separating the MEMS die from the substrate. The opening exposes the air cavity to an external environment and, following this, the air cavity exposes a MEMS element of the MEMS die to the external environment. The air cavity separating the MEMS die from the substrate is formed with a method of manufacturing that utilizes a thermally decomposable die attach material.
A circuit includes a supply node receiving a supply voltage; an output node providing a regulated voltage; startup circuitry coupled to the supply node; current generator circuitry coupled to the startup circuitry and producing a current; a bandgap node coupled to bandgap circuitry to receive a bandgap voltage; multiplier circuitry coupled to the bandgap node and the current generator circuitry to receive and apply scaling to the current; a first transistor providing a threshold voltage drop across the first and second transistor nodes; a first resistive element interposed between the first transistor and the bandgap node; a second resistive element coupled between ground and the second node of the first transistor; and an operational amplifier receiving a pre-regulated voltage as a function of the bandgap voltage, the threshold voltage across the first transistor, and a voltage drop across the first and second resistive elements.
G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
G05F 1/46 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc
A MEMS device is provided that includes a semiconductor substrate including a main surface extending perpendicular to a first direction and a side surface extending on a plane parallel to the first direction and to a second direction that is perpendicular to the first direction. At least one cantilevered member protrudes from the side surface of the semiconductor substrate along a third direction that is perpendicular to the first and second directions. The at least one cantilevered member includes a body portion that includes a piezoelectric material. The body portion has a length along the third direction, a height along the first direction and a width along the second direction, and the height is greater than the width. The at least one cantilevered member is configured to vibrate by lateral bending along a direction perpendicular to the first direction.
H10N 30/20 - Piezoelectric or electrostrictive devices with electrical input and mechanical output, e.g. functioning as actuators or vibrators
B81B 3/00 - Devices comprising flexible or deformable elements, e.g. comprising elastic tongues or membranes
H02N 2/18 - Electric machines in general using piezoelectric effect, electrostriction or magnetostriction producing electrical output from mechanical input, e.g. generators
H10N 30/00 - Piezoelectric or electrostrictive devices
H10N 30/05 - Manufacture of multilayered piezoelectric or electrostrictive devices, or parts thereof, e.g. by stacking piezoelectric bodies and electrodes
H10N 30/074 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by depositing piezoelectric or electrostrictive layers, e.g. aerosol or screen printing
H10N 30/85 - Piezoelectric or electrostrictive active materials
In an embodiment, a USB interface includes a transformer, a primary winding of the transformer, and a first switch in series between a first and a second node, a secondary winding of the transformer and a component in series between a third and a fourth node, the fourth node configured to be set a first reference potential, a second switch connected between the third node and a first terminal, the first terminal configured to provide an output voltage of the USB interface; wherein the component is configured to avoid a current circulation in the secondary winding when the first switch is closed and a control circuit configured to compare a first voltage of an interconnection node between the secondary winding and the component to a first threshold and compare the first voltage to a second threshold when the first voltage is, in absolute values, above the first threshold.
H02M 3/335 - Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
G06F 13/42 - Bus transfer protocol, e.g. handshake; Synchronisation
H02M 1/32 - Means for protecting converters other than by automatic disconnection
The present disclosure relates to a capacitor including a first conductive layer over which is formed a stack, comprising from the upper face of the first layer, a first electrode, a first dielectric layer, a second electrode, and a second conductive layer, the stack comprising a stair step within the second conductive layer, the second electrode, and a part of the thickness of the first dielectric layer, the stair step being filled with a second dielectric layer so that the sidewalls of the first electrode are aligned with respect to the sidewalls of the second dielectric layer.
Process for manufacturing a MEMS device, including: forming a dielectric region which coats part of a semiconductive substrate of a first semiconductive wafer; forming a region which is permeable to gases and coats the dielectric region; coupling the first semiconductive wafer to a second semiconductive wafer so as to form a first chamber, which houses a first movable mass and has a pressure equal to a first value, and a second chamber, which houses a second movable mass and has a pressure equal to the first value, the permeable region facing the second chamber; selectively removing a portion of the semiconductor substrate and an underlying portion of the dielectric region, so as to expose a part of the permeable region, so as to allow gas exchanges through the permeable region; placing the first and the second semiconductive wafers in an environment with a pressure equal to a second value, so that the pressure in the second chamber becomes equal to the second value; and subsequently forming, on the exposed part of the permeable region, a sealing region impermeable to gases.
A warped semiconductor die is attached onto a substrate such as a leadframe by dispensing a first mass of die attach material onto an area of the substrate followed by dispensing a second mass of die attach material so that the second mass of die attach material provides a raised formation of die attach material. For instance, the second mass may be deposited centrally of the first mass. The semiconductor die is placed onto the first and second mass of die attach material with its concave/convex shape matching the distribution of the die attach material thus effectively countering undesired entrapment of air.
In an embodiments a method includes obtaining a neural network (INN), the neural network having a plurality of neural layers, each layer being capable of being executed according to different implementation solutions and impacting a required memory allocation for the execution of the neural network and/or an execution time of the neural network, defining a maximum execution time threshold of the neural network and/or a maximum required memory allocation threshold for the execution of the neural network, determining an optimal required memory allocation size for the execution of the neural network from possible implementation solutions for each layer of the neural network, determining an optimal execution time of the neural network from the possible implementation solutions for each layer of the neural network and estimating a performance loss or a performance gain in terms of execution time and required memory allocation for each implementation solution of each layer of the neural network.
A back end of line (BEOL) structure for an integrated circuit chip includes a last metal structure providing a bonding pad. A passivation structure over the bonding pad includes a first opening extending exposing an upper surface of the bonding pad. A conformal nitride layer extends over the passivation structure and is placed in contact with the upper surface of the bonding pad. An insulator material layer covers the conformal nitride layer and includes a second opening that extends through both the insulator material layer and the conformal nitride layer. A foot portion of the conformal nitride layer on the upper surface of the bonding pad is self-aligned with the second opening.
In a DC-DC converter, a duty-cycle control signal is generated in response to comparing the switching stage output voltage and a reference voltage signal. A first circuit compares the duty-cycle control signal and a ramp to produce a PWM signal. A second circuit compares the duty-cycle control signal and a skip threshold to produce a skip control signal which halts switching operation of the switching stage. A count is made of number of periods of the skip control signal during a monitoring time window and the number of periods of a clock signal during a period of the skip control signal is counted. When the counted number of skip control signal periods is within a first range and the counted number of clock signal periods is within a second range, a common detection signal is asserted to trigger varying a value of the skip threshold signal.
H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion
26.
METHOD AND CIRCUIT FOR POWER-UP OF AN ELECTRONIC CIRCUIT
The present disclosure relates to a method comprising: applying, by a control circuit, a first pulsed signal, consisting of sequential first voltage pulses, to the gate of a power transistor supplying a capacitive load of the circuit, the pulses of the first pulsed signal being separated from each other by a first wait time; further to one or more of the pulses of the first signal, making a comparison, by a comparator, of the value of the voltage across the capacitive load with a first voltage threshold value; and, if the first voltage threshold value is exceeded, applying a second pulsed signal, consisting of sequential second voltage pulses, to the gate of the power transistor, the pulses of the second pulsed signal being separated from each other by a second wait time shorter than the first wait time.
G11C 11/4074 - Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
G11C 11/4072 - Circuits for initialization, powering up or down, clearing memory or presetting
G11C 11/4096 - Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
27.
METHOD AND DEVICE FOR MANAGING INFORMATION EXCHANGE BETWEEN NFC CONTROLLER AND AUXILIARY ELEMENTS
A device, including a main element and a set of at least two auxiliary elements, the main element including a master SWP interface, each auxiliary element including a slave SWP interface connected to the master SWP interface of the NFC element through a controllably switchable SWP link and management circuit configured to control the SWP link switching for selectively activating at once only one slave SWP interface on the SWP link.
H04W 4/80 - Services using short range communication, e.g. near-field communication [NFC], radio-frequency identification [RFID] or low energy communication
G06K 7/00 - Methods or arrangements for sensing record carriers
G06K 7/10 - Methods or arrangements for sensing record carriers by corpuscular radiation
H04B 5/00 - Near-field transmission systems, e.g. inductive loop type
An electronic device includes an integrated circuit (IC) with its second face bonded to a first surface of a first support. A conductive clip has a first portion that is elongate and extends across the IC, having its second surface bonded to a first face of the IC by a solder layer. A second portion of the clip extends from the first portion away from the IC toward a second support with the second surface bonded to a first surface of the second support. A first surface of the clip has a pattern formed therein including a depressed floor with fins extending upwardly therefrom. Through-holes extend through the depressed floor to the second surface of the clip. An encapsulating layer covers portions of the first and second supports, IC, and clip while leaving the first surface of the first portion exposed to permit heat to radiate away therefrom.
A method for controlling a MOS transistor compares a first voltage between a drain and a source of the MOS transistor to a second controllable threshold voltage. When the first voltage is smaller than a third voltage, a fourth control voltage is applied to the MOS transistor that is greater than a fifth threshold voltage of the MOS transistor. When the first voltage is greater than the second voltage, the fourth control voltage applied to the MOS transistor is smaller than the fifth voltage. The second voltage is equal to a first constant value between a first time and a second time, and is equal to a second variable value between the second time and a third time. The second value is equal to a sum of the first voltage and a sixth positive voltage. The third time corresponds to a time when the first voltage inverts.
Electronic device, comprising: a semiconductor body having a surface; a body region in the semiconductor body, extending along a main direction parallel to the surface of the semiconductor body; and a source region in the body region, extending along the main direction. The electronic device has, at the body and source regions, a first and a second electrical contact region alternating with each other along the main direction, wherein the first electrical contact region exposes the body region, and the second electrical contact region exposes the source region. The electronic device further comprises an electrical connection layer extending with electrical continuity longitudinally to the body and source regions, in electrical connection with the first and the second electrical contact regions.
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
A differential pair of FETs forms a sensor circuit coupled to a differential current reading circuit that includes a current to voltage converter and an analog to digital converter. An ESD protection circuit interposed between the sensor circuit and the differential current reading circuit adds spurious currents to a differential sensor current output by the sensor circuit. A circuit before the ESD protection circuit switches the sign of the differential sensor current according to a period of complementary phase clock signals which correspond to a sampling interval of the analog to digital converter. A circuit selects signals depending on the value of the period of the phase clock signals to eliminate the spurious currents.
A pre-driving stage drives one or more Field Effect Transistors in a power stage driving a load. A method for measuring current flowing in the Field Effect Transistors includes: measuring drain to source voltages of the one or more Field Effect Transistor; and measuring an operating temperature of the one or more Field Effect Transistor. The current flowing in the Field Effect Transistors is measured by: calculating the respective on drain to source resistance at the operating temperature as a function of the measured operating temperature and obtaining the current value as a ratio of the respective measured drain to source voltage over the calculated drain to source resistance at the operating temperature.
G01R 17/16 - Measuring arrangements involving comparison with a reference value, e.g. bridge ac or dc measuring bridges with discharge tubes or semiconductor devices in one or more arms of the bridge, e.g. voltmeter using a difference amplifier
G01R 17/04 - Arrangements in which the value to be measured is automatically compared with a reference value in which the reference value is continuously or periodically swept over the range of values to be measured
G01R 19/00 - Arrangements for measuring currents or voltages or for indicating presence or sign thereof
G01R 19/165 - Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
G01R 19/257 - Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques using analogue/digital converters of the type with comparison of different reference values with the value of voltage or current, e.g. using step-by-step method
The disclosure includes a method of authenticating a processor that includes an arithmetic and logic unit. At least one decoded operand of at least a portion of a to-be-executed opcode is received on a first terminal of the arithmetic and logic unit. A signed instruction is received on a second terminal of the arithmetic and logic unit. The signed instruction combines a decoded instruction of the to-be-executed opcode and a previous calculation result of the arithmetic and logic unit.
An optoelectronic device includes a backlight panel illuminating a display panel. The backlight panel includes an array of light emitting pixels, each light emitting pixel having at least one subpixel with one or more light emitting diodes positioned on a substrate. The pixel further includes at least one photodetector positioned on the substrate and arranged to detect an amount of reflected light emitted by said subpixel and reflected by the display panel.
G09G 3/34 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix by control of light from an independent source
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different main groups of groups , or in a single subclass of , , e.g. forming hybrid circuits
35.
METHOD FOR MANAGING THE CONSUMPTION OF A MEMORY DEVICE WHEN USING AN ERROR-CORRECTION CODE AND CORRESPONDING SYSTEM
A method for managing the consumption of a memory device includes performing a first reading of data in a first portion of a first memory area of the memory device. During a same memory access, error correction code check bits are read from a second portion of a second memory area of the memory device. The error correction check bits include error correction check bits that are associated with the data in the first portion of the first memory area and other error correction code check bits associated with other data. All of the other error correction code check bits are stored in a register, and the other data in the first portion of the first memory area is read. The error correction code bits associated with the other data are extracted from the register.
A measurement system, featuring first and second capacitances, and switching, control, and measurement circuits, charges/discharges the capacitances during normal operation. The switching and control circuits periodically connect a first terminal of the first capacitance to a first voltage and a reference voltage, and a first terminal of the second capacitance to a second voltage and the reference voltage. The second terminal of the first capacitance and the second terminal of the second capacitance are connected to the input terminals of the differential integrator, the charge difference between the capacitances being transferred to the differential integrator. A comparator triggers when the output signal of the differential integrator exceeds the hysteresis threshold of the comparator. Two decoupling capacitances are connected between the input of the comparator and the output of the differential integrator, and two reset phases are used to store various disturbances to these decoupling capacitances, improving precision.
A back electromotive force (BEMF) of a spindle motor in a hard disk drive is rectified and exploited to drive a voice coil motor (VCM) in the hard disk drive to retract the heads of the hard disk drive to a park position. The VCM is driven in a discontinuous mode comprising an alternation of VCM on-times and VCM off-times. Rectifying the BEMF of the spindle motor is discontinued before the end of the VCM off-times, Toff with the spindle motor brought into a brake condition wherein the spindle motor is short-circuited and the spindle BEMF forces currents through the windings of the spindle motor. The spindle current is thus pre-charged and made ready to cope with a VCM current request at the next VCM on-time.
A system, for use in providing media access control (MAC)/router/switch/gateway features in an on-board communication network in a vehicle, includes MAC controllers configured to provide a MAC port layer controlling exchange of information over a data link, virtual machine (VM) bridge blocks configured to provide a MAC frame layer interfacing with System-on-Chip VMs, a software (SW) Ethernet port configured to receive from a host programming/configuration information for the system, a local memory controller configured to facilitate the MAC controllers, the VM bridge blocks and the SW Ethernet port in cooperating with a local memory (LMEM), and queue handlers configured to provide queue management for the MAC controllers, the VM bridge blocks and the SW Ethernet port, during cooperation with the LMEM via the local memory controller.
An integrated circuit includes a memory and processing circuitry. The memory stores an Elementary File Test (EFT) file including a record storing information to update a target elementary file (TGF) in a file system of the EFT. The stored information includes a file path identifier identifying a position of the TGF in the file system of the EFT file, which is a concatenation of a parent file identifier followed by an identifier of the TGF, a first length indicator of a first type of data, the data of the first type, a second length indicator to indicate a length of a second type of data, and the data of the second type. The processing circuitry, in operation, identifies the TGF based on the file path identifier and updates the content of the TGF to include the first data and one or more instances of the second data.
An artificial neural network includes a unit cell. The unit cell includes a first binary two-dimensional convolution layer configured to receive an input tensor and to generate a first tensor. A first batch normalization layer is configured to receive the first tensor and to generate a second tensor. A concatenation layer is configured to generate a third tensor by concatenating the input tensor and the second tensor. A second binary two-dimensional convolution layer is configured to receive the third tensor and to generate a fourth tensor. A second batch normalization layer is configured to generate an output tensor based on the fourth tensor.
The present disclosure is directed to a wearable electronic device, such as a watch, that includes one or more optical sensors. In order to determine accuracy of measurements by the optical sensors, the device detects whether or not the optical sensors are in physical contact with the user's skin. The device detects a level of contact between the user's skin and the optical sensors based on electrostatic charge variation measurements, and generates a contact reliability index (CRI) based on the level of contact. Operation of the optical sensors are adjusted based on the CRI.
A61B 5/1455 - Measuring characteristics of blood in vivo, e.g. gas concentration, pH-value using optical sensors, e.g. spectral photometrical oximeters
A61B 5/00 - Measuring for diagnostic purposes ; Identification of persons
A61B 5/0205 - Simultaneously evaluating both cardiovascular conditions and different types of body conditions, e.g. heart and respiratory condition
G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
42.
DUAL-MODE CONTROL CIRCUIT FOR MICROELECTROMECHANICAL SYSTEM GYROSCOPES
The present disclosure is directed to a dual-mode control circuit for a microelectromechanical system (MEMS) gyroscope. A control circuit is coupled to a Lissajous frequency modulated (LFM) gyroscope to control amplitude of oscillation of a mass along two directions. The amplitude of oscillation is controlled by an automatic gain control (AGC) loop which allows the same amplitude of oscillation in both directions. An AGC is implemented with a combination of proportional control (P-type) and integral control (I-type) paths that maintain the correct Lissajous pattern of the oscillation of the mass. The AGC may include a dual-mode stage which is able to switch between a P-type control path and an I-type control path based on the operation of the LFM gyroscope. A fast start-up phase may be controlled by the P-type control path while the I-type path is pre-charged to be ready to use in a steady state condition.
G01C 19/5712 - Turn-sensitive devices using vibrating masses, e.g. vibratory angular rate sensors based on Coriolis forces using masses driven in reciprocating rotary motion about an axis the devices involving a micromechanical structure
One or more embodiments are directed to quad flat no-lead (QFN) semiconductor packages, devices, and methods in which one or more electrical components are positioned between a die pad of a QFN leadframe and a semiconductor die. In one embodiment, a device includes a die pad, a lead that is spaced apart from the die pad, and at least one electrical component that has a first contact on the die pad and a second contact on the lead. A semiconductor die is positioned on the at least one electrical component and is spaced apart from the die pad by the at least one electrical component. The device further includes at least one conductive wire, or wire bond, that electrically couples the at least one lead to the semiconductor die.
A method of pairing between a first host device and a first peripheral device includes entering by a user of the first host device a verification value, as well as comparing, by the first peripheral device, between the verification value and a first secret value stored in a memory of the first peripheral device. When the verification corresponds to the first secret value, the method of pairing further includes calculating and storing a first pairing key by the first host device and the first peripheral device to perform the pairing.
One embodiment provides a digital-to-analog converter that includes an output amplifier configured to be powered with a controllable power supply voltage and a ground reference voltage. The output amplifier is configured to generate an analog output signal having a dynamic range centered on a common-mode voltage. The output amplifier includes a common-mode adaptation circuit configured to position a level of the common-mode voltage at a level located in a middle portion of an interval of voltages located between the power supply voltage and the ground reference voltage, according to an effective level of the power supply voltage.
In a non-volatile memory device, a memory sector is provided. The memory sector includes a plurality of tiles arranged horizontally. Each tile includes a plurality of memory cells arranged in horizontal word lines and vertical bit lines. A pre-decoder is configured to receive a set of encoded address signals to produce pre-decoding signals. A central row decoder is arranged in line with the plurality of tiles, receives the pre-decoding signals and produces level-shifted pull-up and pull-down driving signals for driving the word lines. First buffer circuits are arranged on a first side of each tile. Each of the first buffer circuits is coupled to a respective word line, receives a level-shifted pull-up driving signal and a level-shifted pull-down driving signal, and selectively pulls up or pulls down the respective word line as a function of the values of the received signals.
G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
H03K 19/0185 - Coupling arrangements; Interface arrangements using field-effect transistors only
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
47.
WIRELESS COMMUNICATION DEVICE CONFIGURED FOR ULTRA-WIDEBAND COMMUNICATION
A wireless communication device includes a battery, and a platform powered by the battery, with the platform including a processor. The device also includes a voltage regulator powered by the battery, an ultra-wideband communication unit powered by the voltage regulator via the platform when the platform is powered up, and a near-field communication unit powered directly by the battery, and being configured to order the voltage regulator to power the ultra-wideband communication unit when the platform is powered down.
Signal processing is applied to a digital audio input signal to provide an analog audio output signal using a switching converter circuit driven by a pulse-width-modulated (PWM) signal. The analog audio output signal is sensed to provide an analog feedback signal. The signal processing that is applied includes: converting the digital audio input signal to producing an analog replica; producing an analog error signal indicative of a difference between the analog replica of the digital input signal and the analog feedback signal; converting the analog error signal to produce a digital error signal; digitally filtering the digital error signal to produce a filtered digital error signal; and generating the PWM signal from the filtered digital error signal.
A controller for an electronic circuit that includes a first and a second switch is provided. The controller includes an event detector stage that receives logic electrical signals and a pulse generator circuit, which is coupled to the event detector stage and generates a dead time signal based on edges of the logic electrical signals detected by the event detector stage. The dead time signal includes pulses delimited by an edge of a first type and by a subsequent edge of a second type. A combinatorial sampling circuit generates a first and a second sampled preliminary signal. An update stage updates the values of the first and the second control signals at each pulse of the dead time signal based on the first and the second sampled preliminary signals, subsequently to the edge of the first type or the second type of the pulse of the dead time signal.
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
50.
METHOD AND APPARATUS FOR MANAGING WAVEFORM DATA AND DELAYS IN A WAVEFORM GENERATOR
A signal decode circuit is coupled to a buffer for each signal channel. A memory includes a shared area configured to store waveform data sets, each waveform data set including a sequence of coded waveform values specifying waveform step states. The shared area further stores delay data sets, each delay data set including a digital delay value for each signal channel defining a delay profile. A signal pointer addresses the shared area to read one waveform data set from the memory with the sequence of coded waveform values being selectively loaded into one or more of the buffers. A delay pointer addresses the shared area to read one delay data set from the memory with the digital delay values used to control delayed actuation of the signal decode circuits to decode the sequence of coded waveform values from the buffers and generate waveform signals in accordance with the delay profile.
A61B 8/00 - Diagnosis using ultrasonic, sonic or infrasonic waves
A61B 8/08 - Detecting organic movements or changes, e.g. tumours, cysts, swellings
G01S 7/52 - RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES - Details of systems according to groups , , of systems according to group
G01S 15/89 - Sonar systems specially adapted for specific applications for mapping or imaging
51.
SEMICONDUCTOR PACKAGE OR DEVICE WITH SEALING LAYER
The present disclosure is directed to embodiments of a conductive structure on a conductive layer, which may be a conductive damascene layer of a semiconductor device or package. The conductive damascene layer may be within a substrate of the semiconductor device or package. A crevice is present between one or more sidewalls of the conductive structure and one or more sidewalls of one or more insulating layers on the substrate and extends to a surface of the conductive layer. A sealing layer is formed in the crevice that seals the conductive layer from moisture and contaminants external to the semiconductor device or package that may enter the crevice. In other words, the sealing layer stops the moisture and contaminants from reaching the conductive layer such that the conductive layer does not corrode due to exposure to the moisture and contaminants.
The present disclosure is directed to a device and method for lid angle detection that is accurate even if the device is activated in an upright position. While the device is in a sleep state, first and second sensor units measure acceleration and angular velocity, and calculate orientations of respective lid components based on the acceleration and angular velocity measurements. Upon the device exiting the sleep state, a processor estimates the lid angle using the calculated orientations, sets the estimated lid angle as an initial lid angle, and updates the initial lid angle using, for example, two accelerometers; two accelerometers and two gyroscopes; two accelerometers and two magnetometers; or two accelerometers, two gyroscopes, and two magnetometers.
G06F 1/16 - Constructional details or arrangements
G01B 7/31 - Measuring arrangements characterised by the use of electric or magnetic techniques for testing the alignment of axes for testing the alignment of axes
G06F 1/3231 - Monitoring the presence, absence or movement of users
G06F 1/3246 - Power saving characterised by the action undertaken by software initiated power-off
A first near-field communication device detects the presence of a second near-field communication device located within range. In response to that detection, there is an initiation of a near-field communication between the first and second devices. In case of a failure of the initiation of the near-field communication, instead an initiation of a contactless bank transaction between the first and second devices occurs.
A nonvolatile memory device has a “split-voltage” architecture and includes columns of memory words formed on each row by groups of memory cells. All state transistors for memory cells of a memory word are gate controlled by a control element. All control elements of a same row are controlled by a first control signal generated by a first row control circuit in response to a set-reset (SR) latch output signal output for a selected row. In order to write a piece of data in a memory word, the first row control circuit confers onto the first control signal an erasing voltage corresponding to a first logic state of the first control signal and then a programming voltage corresponding to a second logic state of the first control signal without modifying, between erasing and programming the memory word, the state of the latch output signal for the selected row.
An earphone device has a casing having a measurement portion dedicated to acquisition of at least one measurement quantity with the earphone device arranged outside an ear of a subject. The earphone device is provided with at least one sensor, operatively coupled to the measurement portion within the casing for acquiring signals indicative of the measurement quantity, and a processing module that processes the signals acquired by the sensor so as to provide a processed output signal for monitoring the measurement quantity, as a function of the acquired signals. Electrical-connection elements define electrical paths within the casing in electrical connection with the sensor.
An integrated circuit includes an electronic chip having a face covered with a thermal interface material layer. A heat sink includes a mounting area fixed to the chip via the thermal interface material layer. The heat sink includes open notches extending into the mounting area to delimit fins separated from each other by the open notches.
A control circuit for controlling a first transistor includes a diode for suppressing transient voltages. A cathode of the diode is coupled to a first conduction terminal of the first transistor, and an anode of the diode is coupled to a first node. A first resistor is coupled between the first node and a control terminal of the first transistor. A second transistor has a control terminal coupled to the first node, a first conduction terminal configured to receive a first supply voltage, and a second conduction terminal coupled to the control terminal of the first transistor.
H03K 17/0812 - Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the control circuit
58.
CONTROL DEVICE FOR A SWITCHING VOLTAGE REGULATOR HAVING REDUCED AUDIO NOISE AND CONTROL METHOD
A control device for a switching voltage regulator having a switching circuit receives a set of measurement signals including a first measurement signal indicative of an output voltage of the switching voltage regulator. A burst-mode controller is configured to monitor the output voltage with respect to a first threshold and a second threshold higher than the first threshold, and to provide, in response, a burst signal. A driving-signal generation stage is configured to provide at least one switching control signal for the switching circuit based on the burst signal and the set of measurement signals. The driving-signal generation stage has a feedback module configured to provide a control signal based on the burst signal and an error signal indicative of a difference between the first measurement signal and a reference signal.
H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion
59.
ELECTRONIC SYSTEM, INTEGRATED CIRCUIT, AND METHOD FOR GENERATING SEQUENTIAL SIGNALS
An electronic system is configured to generate a sequential logic signal. The electronic system includes a first ring oscillator including a first plurality of cascaded inverter stages. A combinational logic circuit is configured to generate the sequential logic signal by combining signals at the output terminals of at least two of the inverter stages of the first ring oscillator. The electronic system further includes a second ring oscillator including a second plurality of cascaded inverter stages. A bias current source is configured to supply the inverter stages of the second ring oscillator with a bias current, and a first voltage is generated at the inverter stages of the second ring oscillator. A voltage follower is configured to supply the inverter stages of the first ring oscillator with a second voltage corresponding to the first voltage generated at the inverter stages of the second ring oscillator.
A device includes a multiplier, an accumulator and a floating point adder. The multiplier generates a product of a first factor having a sign bit and exponent bits and a second factor having a sign bit and exponent bits. The multiplier includes a sign multiplier and a subtractor. The sign multiplier generates a product of the sign bit of the first factor and the sign bit of the second factor. The subtractor subtracts the exponent bits of the first factor from the exponent bits of the second factor. The accumulator stores a current accumulation value. The floating-point adder is coupled to the multiplier and to the accumulator, and, in operation, the adder generates an updated accumulation value based a sum of the product and the current accumulation value, and stores the updated accumulation value in the accumulator. The first factor may be a weight of a neural network.
G06F 7/544 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices for evaluating functions by calculation
An integrated circuit package includes a support substrate and a cover fastened on a first face of the support substrate. The cover and support substrate define a housing containing an electronic integrated circuit chip having a first face equipped with electrically conductive protruding elements. A first space between the cover and a second face of the electronic integrated circuit chip is filled with a first shape memory material in the austenitic state. A second space between each pair of electrically conductive protruding elements and electrically conductive contact pads of the support substrate is filled with a second shape memory material in the austenitic state.
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 23/051 - Containers; Seals characterised by the shape the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body another lead being formed by a cover plate parallel to the base plate, e.g. sandwich type
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
62.
METHOD OF MANUFACTURING OHMIC CONTACTS OF AN ELECTRONIC DEVICE, WITH THERMAL BUDGET OPTIMIZATION
Method of manufacturing an electronic device, comprising forming an ohmic contact at an implanted region of a semiconductor body. Forming the ohmic contact provides for performing a high-temperature thermal process for allowing a reaction between a metal material and the material of the semiconductor body, for forming a silicide of the metal material. The step of forming the ohmic contact is performed prior to a step of forming one or more electrical structures which include materials that may be damaged by the high temperature of the thermal process of forming the silicide.
H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
Electronic device comprising: a semiconductor body, in particular of Silicon Carbide, SiC, having a first and a second face, opposite to each other along a first direction; and an electrical terminal at the first face, insulated from the semiconductor body by an electrical insulation region. The electrical insulation region is a multilayer comprising: a first insulating layer, of a Silicon Oxide, in contact with the semiconductor body; a second insulating layer on the first insulating layer, of a Hafnium Oxide; and a third insulating layer on the second insulating layer, of an Aluminum Oxide.
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
A memory cell includes a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element. The memory cell is formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor. The gate is formed on the active layer and has a lateral flank covered with a second insulating layer. The variable-resistance element includes a first layer covering a lateral flank of the active layer in a trench formed through the active layer along the lateral flank of the gate and reaching the first insulating layer, and a second layer made of a variable-resistance material.
H10N 70/00 - Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
A method of operating a microcontroller to perform a Fast Fourier Transform, the method including receiving, by the microcontroller, N samples from a signal; and performing, by the microcontroller, a first butterfly operation of the Fast Fourier Transform before all of the N samples have been received from the signal, based on the performing of the first butterfly operation, the microcontroller performs the Fast Fourier Transform at a higher performance to power efficiency than a Fast Fourier Transform operation that begins after all of the N samples are received.
A voltage matching circuit receives a first voltage received by a connector, and outputs a second voltage. The second voltage is equal to the first voltage, if the first voltage is less than a threshold voltage. The second voltage is equal to the first voltage divided by a first factor, if the first voltage is greater than or equal to the threshold voltage.
MEMS ultrasonic transducer, MUT, device, comprising a semiconductor body with a first and a second main face, including: a modulation cavity extending into the semiconductor body from the second main face; a membrane body suspended on the modulation cavity and comprising a transduction membrane body and a modulation membrane body; a piezoelectric modulation structure on the modulation membrane body; a transduction cavity extending into the membrane body, the transduction membrane body being suspended on the transduction cavity; and a piezoelectric transduction structure on the transduction membrane body. The modulation membrane body has a first thickness and the transduction membrane body has a second thickness smaller than the first thickness. In use, the modulation membrane vibrates at a first frequency and the transduction membrane vibrates at a second frequency higher than the first frequency, to emit and/or receive acoustic waves at a frequency dependent on the first and the second frequencies.
B06B 1/02 - Processes or apparatus for generating mechanical vibrations of infrasonic, sonic or ultrasonic frequency making use of electrical energy
G01S 7/534 - RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES - Details of systems according to groups , , of systems according to group - Details of non-pulse systems
68.
WEARABLE AND PORTABLE SYSTEM AND METHOD FOR MEASURING CARDIAC PARAMETERS FOR DETECTING CARDIOPATHIES
A system for measuring cardiac parameters uses a movements sensor to generate a seismocardiographic signal and a cardiac parameters calculation unit. The cardiac parameters calculation unit provides for generating an envelope signal correlated to the seismocardiographic signal; identifies, in the envelope signal, signal segments having a repetitive pattern; identifies, among the signal segments, pairs of successive peaks such that a first peak of each pair of successive peaks is a systolic peak and a second peak of each pair of successive peaks is a diastolic peak; and calculates a systolic period and a diastolic period for each pair of successive peaks.
An integrated circuit includes transistor. That transistor is manufactured using a process including the following steps: forming a first gate region; depositing dielectric layers accumulating on sides of the first gate region to form regions of spacers having a width; etching to remove a part of the deposited dielectric layers accumulated on the sides of the first gate region to reduce the width of the regions of spacers; performing a first implantation of dopants aligned on the regions of spacers to form first lightly doped conduction regions of the transistor; and performing a second implanting of dopants to form first more strongly doped conduction regions of the transistor.
An electronic device includes a doped semiconductor substrate of a first conductivity type. First and second doped wells are provided, separated from each other by trench isolation, within the doped semiconductor substrate. At least one first region and at least one second region are respectively located in the first and second doped wells, with each first and second region having a doping level higher than a doping level of the first and second doped wells. The trench isolation penetrates into the first and second doped wells and extends laterally between the first region and second region. A third region laterally extends between the first and second doped wells at a location under the insulating trench. The third region has a doping level lower than the doping level of the first and second doped wells.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 29/74 - Thyristor-type devices, e.g. having four-zone regenerative action
71.
SIC-BASED ELECTRONIC DEVICE WITH FUSE ELEMENT FOR SHORT-CIRCUITS PROTECTION, AND MANUFACTURING METHOD THEREOF
SiC-based MOSFET electronic device comprising: a solid body; a gate terminal, extending into the solid body; a conductive path, extending at a first side of the solid body, configured to be electrically couplable to a generator of a biasing voltage; a protection element of a solid-state material, coupled to the gate terminal and to the conductive path, the protection element forming an electronic connection between the gate terminal and the conductive path, and being configured to go from the solid state to a melted or gaseous state, interrupting the electrical connection, in response to a leakage current through the protection element greater than a critical threshold; a buried cavity in the solid body accommodating, at least in part, the protection element.
H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
H01L 23/29 - Encapsulation, e.g. encapsulating layers, coatings characterised by the material
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
The present description concerns a package for an electronic device. The package including a plate and a lateral wall, separated by a layer made of a bonding material and at least one region made of a material configured to form in the region an opening between the inside and the outside of the package when the package is heated.
An integrated circuit includes a control circuit, a primary sensor device coupled to the control circuit, and a plurality of groups of secondary sensor devices coupled to the primary sensor device. The primary sensor device receives a master clock signal from the control device and outputs, to each group of secondary sensor devices, a respective secondary clock signal with a frequency lower than the primary clock signal. The primary sensor device generates primary sensor data. The primary sensor device receives secondary sensor data from each group of secondary sensor devices. The primary sensor device combines the primary sensor data and all of the secondary sensor data into a sensor data stream with a time division-multiplexing scheme and outputs the sensor data stream to the control circuit.
A system includes inertial sensors and a GPS. The system generates a first estimated vehicle velocity based on motion data and positioning data, generates a second estimated vehicle velocity based on the processed motion data and the first estimated vehicle velocity, and generates fused datasets indicative of position, velocity and attitude of a vehicle based on the processed motion data, the positioning data and the second estimated vehicle velocity. The generating the second estimated vehicle velocity includes: filtering the motion data, transforming the filtered motion data in a frequency domain based on the first estimated vehicle velocity, generating spectral power density signals, generating an estimated wheel angular frequency and an estimated wheel size based on the spectral power density signals, and generating the second estimated vehicle velocity as a function of the estimated wheel angular frequency and the estimated wheel size.
G01S 19/47 - Determining position by combining measurements of signals from the satellite radio beacon positioning system with a supplementary measurement the supplementary measurement being an inertial measurement, e.g. tightly coupled inertial
An electronic device includes a doped semiconductor substrate of a first conductivity type. A first doped well of a second conductivity type opposite to the first conductivity type extends into the doped semiconductor substrate from a surface thereof. A second doped well of the first conductivity type is located in the first well. A third electrically-insulating well is located in the second well. A fourth doped well of the first conductivity type is located in the third well. First, second, and third doped regions of the first conductivity type are respectively located in the doped semiconductor substrate, the second doped well and the fourth doped well. The first, second, and third doped regions have doping levels greater than a doping level of the doped semiconductor substrate. A fourth doped region the second conductivity type is located in the fourth doped well adjacent the second doped region.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
CONTROLLER FOR A BUCK-BOOST SWITCHING CONVERTER WITH OVERCURRENT AND NULL-CURRENT DETECTION AND METHOD FOR CONTROLLING A BUCK-BOOST SWITCHING CONVERTER
A controller for a buck-boost switching converter, which includes an inductor and a shunt resistor and is coupled to a load which draws a load current, includes a control circuit which performs charge and discharge cycles of the inductor. A first comparator stage generates a first signal which is indicative of a direction of the resistor current during the charge and discharge cycles. A low-pass filtering circuit generates a filtered electrical quantity based on a voltage on the shunt resistor during the charge and discharge cycles. A second comparator stage generates a second signal indicative of a comparison between the filtered electrical quantity and a reference electrical quantity. A detection stage detects the occurrence of an overcurrent in the load based on the second signal.
H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
G01R 19/165 - Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion
77.
METHOD FOR GENERATING AN UPDATE FILE AND CORRESPONDING SERVER DEVICE, UPDATING METHOD AND CORRESPONDING CLIENT DEVICE, UPDATING METHOD AND CORRESPONDING SYSTEM
A server builds an update file to update software. The server compiles source code of an updated version of the software, generating a binary file of the updated version of the software. Memory locations are mapped to sections of the binary file based on mappings of sections of a binary file of a prior version of the software. Bits of sections of a plurality of sections of the binary file of the prior version are logically combined, bit-by-bit, with bits of corresponding sections of the binary file of the updated version. The logically combining includes: applying an exclusive or operation; or applying an exclusive nor operation. The update file is built based on the mapping of the memory locations and on results of the logical combining.
A multi-level pulser circuit comprises a set of first input pins for receiving respective positive voltage signals at different voltage levels, a set of second input pins for receiving respective negative voltage signals at different voltage levels, and a reference input pin configured to receive a reference voltage signal intermediate the positive voltage signals and the negative voltage signals. The circuit comprises an output pin configured to supply a pulsed output signal. The circuit further comprises control circuitry configured to selectively couple the output pin to one of the first input pins, the second input pins and the reference input pin to generate the pulsed output signal at the output pin. The control circuitry is further configured to selectively couple at least one of the second input pins and the reference input pin to the output pin during falling transitions of the pulsed output signal between two positive voltage levels, and selectively couple at least one of the first input pins and the reference input pin to the output pin during rising transitions of the pulsed output signal between two negative voltage levels.
H03K 3/027 - Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
A MOSFET transistor includes, on a semiconductor layer, a stack of a gate insulator and of a gate region on the gate insulator. The gate region has a first gate portion and a second gate portion between the first gate portion and the gate insulator. The first gate portion has a first length in a first lateral direction of the transistor. The second gate portion has a second length in the first lateral direction that is shorter than the first length.
In accordance with an embodiment, a method of measuring a load current flowing through a current measurement resistor coupled between a source node and a load node includes: measuring a first voltage across a replica resistor when a first end of the replica resistor is coupled to the source node and a second end of the replica resistor is coupled to a reference current source; measuring a second voltage across the replica resistor when the second end of the replica resistor is coupled to the source node and the first end of the replica resistor is coupled to the reference current source; measure a third voltage across the current sensing resistor; and calculating a corrected current measurement of the load current based on the measured first voltage, the measured second voltage and the measured third voltage.
In accordance with an embodiment, a power supply circuit includes: a first transistor device comprising a first gate associated with a first transconductance and a second gate associated with a transconductance greater than the first transconductance; and a second transistor device including a third gate associated with a second transconductance and a fourth gate associated with a transconductance greater than the second transconductance. The second transistor device is configured to supply power to at least one load, the first and the third gates are controlled by a closed regulation loop, and the second and the fourth gates are controlled by a sampled reference voltage.
H04N 25/709 - Circuitry for control of the power supply
H04N 25/77 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
H02M 3/155 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
The present disclosure relates to a die comprising metal pillars extending from a surface of the die, the height of each pillar being substantially equal to or greater than 20 μm, the pillars being intended to raise the die when fastening the die by means of a bonding material on a surface of a support. The metal pillars being inserted into the bonding material at which point the bonding material is annealed to be cured and hardened solidifying the bonding material to couple the die to the surface of the support.
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 25/10 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices having separate containers
83.
TRANSDUCER WITH IMPROVED PIEZOELECTRIC ARRANGEMENT, MEMS DEVICE COMPRISING THE TRANSDUCER, AND METHODS FOR MANUFACTURING THE TRANSDUCER
A transducer includes a supporting body and a suspended structure mechanically coupled to the supporting body. The suspended structure has a first and a second surface opposite to one another along an axis, and is configured to oscillate in an oscillation direction having at least one component parallel to the axis. A first piezoelectric transducer is disposed on the first surface of the suspended structure, and a second piezoelectric transducer is disposed on the second surface of the suspended structure.
ALMA MATER STUDIORUM - UNIVERSITA' DI BOLOGNA (Italy)
Inventor
D'Addato, Matteo
Elgani, Alessia Maria
Perilli, Luca
Franchi Scarselli, Eleonora
Gnudi, Antonio
Canegallo, Roberto Antonio
Ricotti, Giulio
Abstract
A circuit includes a clock input node, a first signal input node configured to receive a first modulated signal switching between a first DC voltage and a second DC voltage, a bias circuit, a first output node, a first capacitor, a second capacitor, and switching circuitry coupled to the first capacitor and the second capacitor. Control circuitry is configured to initially set the switching circuitry in a first configuration in response to the first modulated signal having the second DC voltage, thereby charging the first capacitor to the second DC voltage and charging the second capacitor to the first DC voltage, and subsequently set the switching circuitry in a second configuration in response to an edge detected in the clock signal, thereby producing the first threshold voltage at the first output node after charge redistribution taking place between the first and second capacitors.
H03L 7/099 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
85.
MICROELECTROMECHANICAL BUTTON DEVICE AND CORRESPONDING WATERPROOF USER INTERFACE ELEMENT
A microelectromechanical button device is provided with a detection structure having: a substrate of semiconductor material with a front surface and a rear surface; a buried electrode arranged on the substrate; a mobile electrode, arranged in a structural layer overlying the substrate and elastically suspended above the buried electrode at a separation distance so as to form a detection capacitor; and a cap coupled over the structural layer and having a first main surface facing the structural layer and a second main surface that is designed to be mechanically coupled to a deformable portion of a case of an electronic apparatus of a portable or wearable type. The cap has, on its first main surface, an actuation portion arranged over the mobile electrode and configured to cause, in the presence of a pressure applied on the second main surface, a deflection of the mobile electrode and its approach to the buried electrode, with a consequent capacitive variation of the detection capacitor, which is indicative of an actuation of the microelectromechanical button device.
B81B 7/02 - Microstructural systems containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems (MEMS)
H03K 17/975 - Switches controlled by moving an element forming part of the switch using a capacitive movable element
An integrated circuit package includes at least one electronic chip having a first face fastened onto a first face of a carrier substrate by an adhesive interface. The adhesive interface includes a crown formed of a first adhesive material that is fastened on the periphery of the first face of the electronic chip. The crown defining an internal housing. A second adhesive material, different than the first material, is deposited in the internal housing.
A control circuit for a switching stage of an electronic converter includes a PWM signal generator that generates a PWM signal to drive the switching stage of the electronic converter. A loop comparator circuit receives the regulated output voltage of the electronic converter and receives a sum signal from an adder circuit. The loop comparator circuit generates a comparison signal having a first or second logic value in response to the regulated output voltage reaching the sum signal or failing to reach the sum signal. The adder circuit generates the sum signal as a sum of a reference voltage and a programmable offset voltage that is generated by a programmable voltage generator based on a digital word signal. A feedback circuit is coupled to the loop comparator circuit and the PWM signal generator, and provides the digital word signal to the programmable voltage generator.
H02M 3/157 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion
A device includes a local oscillator, an all-digital phase-locked loop, a digital signal generator, sampling circuitry, and an interface. The local oscillator generates a local clock signal. The all-digital phase locked loop generates a sampling control signal. The ADPLL includes a phase-error detector, a digital filter and a sigma-delta modulator. The phase detector generates a phase error signal based on a loop clock signal and a received reference signal. The digital filter generates a signal indicative of a frequency ratio between a frequency of the reference clock signal and the local clock frequency based on the phase error signal. The sigma-delta modulator generates a modulated signal based on the signal indicative of the frequency ratio. The sampling control signal is based on the modulated signal. The sampling circuitry samples digital signals generated by the digital signal generator at a sampling frequency, which is a function of the sampling control signal.
H03L 7/081 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop provided with an additional controlled phase shifter
H03L 7/099 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
89.
MEMS DEVICE WITH AN IMPROVED CAP AND RELATED MANUFACTURING PROCESS
Electronic device including: a MEMS sensor device including a functional structure which transduces a chemical or physical quantity into a corresponding electrical quantity; a cap including a semiconductive substrate; and a bonding dielectric region, which mechanically couples the cap to the MEMS sensor device. The cap further includes a conductive region, which extends between the semiconductive substrate and the MEMS sensor device and includes: a first portion, which is arranged laterally with respect to the semiconductive substrate and is exposed, so as to be electrically coupleable to a terminal at a reference potential by a corresponding wire bonding; and a second portion, which contacts the semiconductive substrate.
The present disclosure is directed to a device configured to detect whether the device is in a bag or outside of the bag. The device determines whether the device is in or outside of the bag based on distance measurements generated by at least one proximity sensor and motion measurements generated by at least one motion sensor. By using both distance measurements and motion measurements, the device is able to detect whether the device is in the bag or outside of the bag with high accuracy and robustness.
An electronic device includes a magnetometer that outputs magnetometer sensor signals and a gyroscope that outputs gyroscope sensor signals. The electronic device includes a magnetometer calibration module that calibrates the magnetometer utilizing the gyroscope sensor signals. The electronic device generates a first magnetometer calibration parameter based on a Kalman filter process. The electronic device generates a second magnetometer calibration parameter based on a least squares estimation process.
A differential piezoelectric actuator-system includes an inductor and driver-circuit having switches for transferring energy between first and second actuators and the inductor, and between a voltage-supply node and the inductor. Control circuitry determines whether a next phase in which to operate the driver-circuit is a first charging-phase or a first recovery-phase. The first charging-phase includes operating the switches in: a first sub-phase to transfer energy from the first actuator to the inductor; a second sub-phase to transfer energy from the voltage supply node to the inductor; and a third sub-phase to transfer energy from the inductor to the second actuator. The first recovery-phase includes operating the switches in: a first sub-phase to transfer energy from the first actuator to the inductor; a second sub-phase to transfer energy from the inductor to the second actuator; and a third sub-phase to transfer energy from the inductor to the voltage supply node.
H01L 41/04 - SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR - Details thereof - Details of piezo-electric or electrostrictive elements
H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
93.
Temporal differential sensing structure for vibrating gyroscope
A microelectromechanical device is provided. A vibrating structure gyroscope included in the device employs a temporal differential sensing method alone or a spatial differential sensing method in combination with the temporal differential sensing method. When used in combination, the temporal sensing method may be applied before the spatial sensing method or applied after the spatial sensing method. The temporal differential sensing samples signals at times t1 and t2 when velocity of a sensing mass within the vibrating structure gyroscope is maximum and has an opposite sign. The temporal sensing method improves Euler and Centrifugal forces cancellation and increases the signal to noise ratio if forces remain equal at times t1 and t2. Applying a high sampling speed can result in times t1 and t2 being sufficiently close to each other and therefore cancel any error terms associated with Euler and Centrifugal forces.
G01C 19/5712 - Turn-sensitive devices using vibrating masses, e.g. vibratory angular rate sensors based on Coriolis forces using masses driven in reciprocating rotary motion about an axis the devices involving a micromechanical structure
94.
TAGGED MEMORY OPERATED AT LOWER VMIN IN ERROR TOLERANT SYSTEM
STMicroelectronics International N.V. (Switzerland)
Inventor
Chawla, Nitin
Desoli, Giuseppe
Grover, Anuj
Boesch, Thomas
Singh, Surinder Pal
Ayodhyawasi, Manuj
Abstract
A memory array arranged as a plurality of memory cells. The memory cells are configured to operate at a determined voltage. A memory management circuitry coupled to the plurality of memory cells tags a first set of the plurality of memory cells as low-voltage cells and tags a second set of the plurality of memory cells as high-voltage cells. A power source provides a low voltage to the first set of memory cells and provides a high voltage to the second set of memory cells based on the tags.
An electronic system includes a control circuit to provide a binary control signal alternating between a first binary state during first phases and a second binary state during second phases; a screen controlled by the control signal, the screen emitting light during each first phase, and to not emit any light during each second phase; a light sensor under the screen or along the edge of the screen, and providing a measurement signal representative of a quantity of light received by the sensor during a measurement phase or a plurality of consecutive measurement phases; and a synchronization device to synchronize each measurement phase with a second phase.
G09G 3/34 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix by control of light from an independent source
A differential piezoelectric actuator-system includes an inductor and driver-circuit having switches for transferring energy between first and second actuators and the inductor, and between a voltage-supply node and the inductor. Control circuitry determines whether a next phase in which to operate the driver-circuit is a first charging-phase or a first recovery-phase. The first charging-phase includes operating the switches in: a first sub-phase to transfer energy from the first actuator to the inductor; a second sub-phase to transfer energy from the voltage supply node to the inductor; and a third sub-phase to transfer energy from the inductor to the second actuator. The first recovery-phase includes operating the switches in: a first sub-phase to transfer energy from the first actuator to the inductor; a second sub-phase to transfer energy from the inductor to the voltage supply node; and a third sub-phase to transfer energy from the inductor to the second actuator.
H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H02J 7/00 - Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
A method for manufacturing an optical microelectromechanical device, includes forming, in a first wafer of semiconductor material having a first surface and a second surface, a suspended mirror structure, a fixed structure surrounding the suspended mirror structure, elastic supporting elements extending between the fixed structure and the suspended mirror structure, and an actuation structure coupled to the suspended mirror structure. The method continues with forming, in a second wafer, a chamber delimited by a bottom wall having a through opening, and bonding the second wafer to the first surface of the first wafer and bonding a third wafer to the second surface of the first wafer so that the chamber overlies the actuation structure, and the through opening is aligned to the suspended mirror structure, thus forming a device composite wafer. The device composite wafer is diced to form an optical microelectromechanical device.
The present disclosure is directed to pick-up state detection for an electronic device, such as a laptop. In a pick-up state, the device is picked or lifted up from a surface, such as a table. A power state of the device is adjusted in response to detecting the pick-up state. For example, the device is in a hibernate state while set on the table, and is switched to a working state in response to detecting the pick-up state.
A microelectromechanical sensor device having a sensing structure with: a substrate; an inertial mass, suspended above the substrate and elastically coupled to a rotor anchoring structure by elastic coupling elements, to perform at least one inertial movement due to a quantity to be sensed; first sensing electrodes, integrally coupled to the inertial mass to be movable due to the inertial movement; and second sensing electrodes, fixed with respect to the quantity to be sensed, facing and capacitively coupled to the first sensing electrodes to form sensing capacitances having a value that is indicative of the quantity to be sensed. The second sensing electrodes are arranged in a suspended manner above the substrate and a compensation structure is configured to move the second sensing electrodes with respect to the first sensing electrodes and vary a facing distance thereof, in the absence of the quantity to be sensed, in order to compensate for a native offset of the sensing structure.
G01P 15/125 - Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces with conversion into electric or magnetic values by capacitive pick-up
100.
METHOD AND APPARATUS FOR ESTIMATING A VALUE IN A TABLE GENERATED BY A PHOTOSITES MATRIX
An embodiment method for estimating a missing or incorrect value in a table of values generated by a photosite matrix comprises a definition of a zone of the table comprising the value to be estimated and other values, referred to as neighboring values, and an estimation of the value to be estimated based on the primary neighboring values and the weight associated with these primary neighboring values, wherein a weight of each neighboring value, referred to as primary neighboring value, of the same colorimetric component as that of the missing or incorrect value to be estimated, is determined according to differences between neighboring values disposed on an axis and neighboring values disposed parallel with this axis and positioned in relation to this axis on the same side as the primary neighboring value for which the weight is determined.
