International Business Machines Corporation

États‑Unis d’Amérique

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Propriétaire / Filiale
[Owner] International Business Machines Corporation 469
IBM United Kingdom Limited 2
Date
2021 42
2020 49
2018 15
2017 2
Avant 2017 350
Classe IPC
G06F 9/30 - Dispositions pour exécuter des instructions machines, p.ex. décodage d'instructions 34
G06F 9/455 - Dispositions pour exécuter des programmes spécifiques Émulation; Interprétation; Simulation de logiciel, p.ex. virtualisation ou émulation des moteurs d’exécution d’applications ou de systèmes d’exploitation 24
G06F 9/46 - Dispositions pour la multiprogrammation 24
H04L 9/32 - Dispositions pour les communications secrètes ou protégées comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système 19
G06F 9/50 - Allocation de ressources, p.ex. de l'unité centrale de traitement [UCT] 17
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Statut
En Instance 120
Enregistré / En vigueur 349
Résultats pour  brevets
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1.

FABRICATION OF SEMICONDUCTOR STRUCTURES

      
Numéro de document 03165991
Statut En instance
Date de dépôt 2021-04-20
Date de disponibilité au public 2021-11-11
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Trivino, Noelia Vico
  • Moselund, Kirsten Emilie
  • Scherrer, Markus

Abrégé

A method for fabricating a semiconductor structure. The method comprises fabricating a photonic crystal structure (113) of a first material, in particular a first semiconductor material and selectively removing the first material within a predefined part of the photonic crystal structure (113). The method further comprises replacing the first material within the predefined part of the photonic crystal structure (113) with one or more second materials by selective epitaxy. The one or more second materials may be in particular semiconductor materials. A device is obtained by such a method.

Classes IPC  ?

  • H01L 33/00 - DISPOSITIFS À SEMI-CONDUCTEURS; DISPOSITIFS ÉLECTRIQUES À L'ÉTAT SOLIDE NON PRÉVUS AILLEURS - Détails

2.

REAL-TIME DETECTION AND CORRECTION OF SHADOWING IN HYPERSPECTRAL RETINAL IMAGES

      
Numéro de document 03167949
Statut En instance
Date de dépôt 2021-04-28
Date de disponibilité au public 2021-11-11
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Maetschke, Stefan
  • Faux, Noel

Abrégé

A method for real-time detection and correction of shadowing in hyperspectral retinal images may include capturing receiving, using a processor, a hyperspectral image of a retina of a patient, detecting, by the processor, a shadow in the hyperspectral image, determining, by the processor that the shadow of the hyperspectral image exceeds a threshold, and in response to determining that the shadow of the hyperspectral image exceeds the threshold, initiating, using the processor, a capture of an additional hyperspectral image of the retina of the patient. Various other methods, systems, and computer-readable media are also disclosed.

Classes IPC  ?

  • A61B 3/12 - Appareils pour l'examen optique des yeux; Appareils pour l'examen clinique des yeux du type à mesure objective, c. à d. instruments pour l'examen des yeux indépendamment des perceptions ou des réactions du patient pour examiner le fond de l'œil, p.ex. ophtalmoscopes
  • G06K 9/62 - Méthodes ou dispositions pour la reconnaissance utilisant des moyens électroniques
  • G06T 7/00 - Analyse d'image

3.

QUANTUM COMPUTING MACHINE LEARNING FOR SECURITY THREATS

      
Numéro de document 03167954
Statut En instance
Date de dépôt 2021-04-15
Date de disponibilité au public 2021-11-11
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s) Ryver, Kelly Nicole

Abrégé

Embodiments are disclosed for a method for a security model. The method includes generating a Bloch sphere based on a system information and event management (SIEM) of a security domain and a structured threat information expression trusted automated exchange of indicator information. The method also includes generating a quantum state probabilities matrix based on the Bloch sphere. Further, the method includes training a security threat model to perform security threat classifications based on the quantum state probabilities matrix. Additionally, the method includes performing a machine learning classification of the security domain based on the quantum state probabilities matrix.

Classes IPC  ?

  • H04L 9/08 - Répartition de clés
  • G06F 21/57 - Certification ou préservation de plates-formes informatiques fiables, p.ex. démarrages ou arrêts sécurisés, suivis de version, contrôles de logiciel système, mises à jour sécurisées ou évaluation de vulnérabilité
  • G06N 20/00 - Apprentissage automatique

4.

FENCING NON-RESPONDING PORTS IN A NETWORK FABRIC

      
Numéro de document 03167963
Statut En instance
Date de dépôt 2021-04-27
Date de disponibilité au public 2021-11-11
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Gavrilov, Constantine
  • Koren, Eli

Abrégé

A computer-implemented method according to one aspect includes determining whether an operating system of a node of a distributed computing environment is functioning correctly by sending a first management query to the node; in response to determining that the operating system of the node is not functioning correctly, determining whether the node has an active communication link by sending a second management query to ports associated with the node; and in response to determining that the node has an active communication link, resetting the active communication link for the node by sending a reset request to the ports associated with the node.

5.

DYNAMICALLY GENERATING FACETS USING GRAPH PARTITIONING

      
Numéro de document 03165987
Statut En instance
Date de dépôt 2021-03-17
Date de disponibilité au public 2021-10-28
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Rivlin, Or
  • Mass, Yosi
  • Roitman, Haggai
  • Konopnicki, David

Abrégé

An example system includes a processor to receive concepts extracted from a result set corresponding to a query and result associations for each extracted concept. The processor is to build a graph based on the extracted concepts, wherein the graph comprises a number of nodes representing the extracted concepts and weighted edges representing similarity between concepts extracted from shared results. The processor is to partition the graph into subgraphs with vertices corresponding to candidate facets for vertices having higher sums of weighted edges. The processor is to rank the candidate facets. The processor is to select higher ranked candidate facets to use as facets. The processor is to output facets with a result set in response to the query.

Classes IPC  ?

6.

THERMAL INTERFACE MATERIAL STRUCTURES FOR DIRECTING HEAT IN A THREE-DIMENSIONAL SPACE

      
Numéro de document 03165971
Statut En instance
Date de dépôt 2021-03-19
Date de disponibilité au public 2021-10-21
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Hoffmeyer, Mark
  • Marroquin, Christopher
  • Campbell, Eric
  • Czaplewski-Campbell, Sarah
  • Mann, Phillip

Abrégé

A thermal interface material (TIM) structure for directing heat in a three-dimensional space including a TIM sheet (100). The TIM sheet (100) includes a lower portion (102) along a lower plane;a first side portion along a first side plane;a first upper portion along an upper plane;a first fold between the lower portion (102) and the first side portion positioning the first side portion substantially perpendicular to the lower portion (102); and a second fold between the first side portion and the first upper portion positioning the first upper portion on substantially perpendicular to the first side portion and substantially parallel to the lower portion (102).

Classes IPC  ?

  • H01L 23/367 - Refroidissement facilité par la forme du dispositif

7.

PIERCED THERMAL INTERFACE CONSTRUCTIONS

      
Numéro de document 03165976
Statut En instance
Date de dépôt 2021-03-19
Date de disponibilité au public 2021-10-21
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s) Hoffmeyer, Mark

Abrégé

Pierced thermal interface constructions including a thermal interface material (TIM) structure comprising: a TIM sheet comprising a plurality of piercings, where each of the plurality of piercings comprises a cavity and displaced material, and where the displaced material from each of the plurality of piercings protrudes away from the TIM sheet.

Classes IPC  ?

  • H05K 7/20 - Modifications en vue de faciliter la réfrigération, l'aération ou le chauffage

8.

DYNAMIC DISCOVERY AND CORRECTION OF DATA QUALITY ISSUES

      
Numéro de document 03165983
Statut En instance
Date de dépôt 2021-04-07
Date de disponibilité au public 2021-10-21
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Shrivastava, Shrey
  • Bhamidipaty, Anuradha
  • Patel, Dhavalkumar

Abrégé

A computing device, method, and system are provided of improving data quality to conserve computational resources. The computing device receives a raw dataset. One or more data quality metric goals corresponding to the received raw dataset are received. A schema of the dataset is determined. An initial set of validation nodes is identified based on the schema of the dataset. The initial set of validation nodes are executed. A next set of validation nodes are iteratively expanded and executed based on the schema of the dataset until a termination criterion is reached. A corrected dataset of the raw dataset is provided based on the iterative execution of the initial and next set of validation nodes.

Classes IPC  ?

  • G06F 17/40 - Acquisition et consignation de données

9.

GENERATING THREE-DIMENSIONAL SPIKES USING LOW-POWER COMPUTING HARDWARE

      
Numéro de document 03165964
Statut En instance
Date de dépôt 2021-03-19
Date de disponibilité au public 2021-10-14
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Asif, Umar
  • Roy, Subhrajit
  • Tang, Jianbin
  • Harrer, Stefan

Abrégé

A method of generating three-dimensional (3D) spikes. The method comprising receiving a signal comprising time-series data and generating a first two- dimensional (2D) grid. Generating the first 2D grid comprises mapping segments of the time-series data to respective positions of the first 2D grid, and generating, for each position, a spike train corresponding to the respective mapped segment. The method further comprises generating a second 2D grid including performing, for each position, a mathematical operation on the spike train of the corresponding position of the first 2D grid. The method further comprises generating a third 2D grid including performing spatial filtering on the positions of the second 2D grid. The method further comprises generating a 3D grid based on a combination of the first 2D grid, the second 2D grid, and the third 2D grid. The 3D grid comprises one or more 3D spikes.

Classes IPC  ?

  • G06N 7/00 - Systèmes de calculateurs basés sur des modèles mathématiques spécifiques

10.

GENERATING PERFORMANCE PREDICTIONS WITH UNCERTAINTY INTERVALS

      
Numéro de document 03170297
Statut En instance
Date de dépôt 2021-02-16
Date de disponibilité au public 2021-10-14
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Arnold, Matthew Richard
  • Elder, Benjamin Tyler
  • Navratil, Jiri
  • Venkataraman, Ganesh

Abrégé

A technique for generating a performance prediction of a machine learning model with uncertainty intervals includes obtaining a first model configured to perform a task and a production dataset?At least one metric predicting a performance of the first model at performing the task on the production dataset is generated using a second model. The second model is a meta-model associated with the first model. At least one value predicting an uncertainty of the at least one metric predicting the performance of the first model at performing the task on the production dataset is generated using a third model. The third model is a meta-meta-model associated with the second model. An indication of the at least one metric predicting the performance of the first model and the at least one value predicting the uncertainty of the at least one metric is provided.

Classes IPC  ?

11.

CONTEXTUAL INTEGRITY PRESERVATION

      
Numéro de document 03170286
Statut En instance
Date de dépôt 2021-03-23
Date de disponibilité au public 2021-10-14
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Gaur, Nitin
  • Ponceleon, Dulce B.
  • Katsis, Ioannis

Abrégé

An example operation includes one or more of receiving, by a data processing node, inference data object from a multi-channel data server over a blockchain, sorting, by the data processing node, longitudinal records contained in the inference data object, linking, by the data processing node, transaction outcomes and inferences data from the inference data object to the sorted longitudinal records, and recording linked data onto a blockchain ledger. The data processing node serves as a validator of data from a robo-advisory using natural language (NL) processing to reduce bias and measure effectiveness of inference from the robo-advisory.

12.

NEURAL NETWORK WEIGHT DISTRIBUTION FROM A GRID OF MEMORY ELEMENTS

      
Numéro de document 03165563
Statut En instance
Date de dépôt 2021-01-28
Date de disponibilité au public 2021-10-14
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Sawada, Jun
  • Modha, Dharmendra
  • Cassidy, Andrew Stephen
  • Arthur, John Vernon
  • Nayak, Tapan
  • Ortega Otero, Carlos
  • Taba, Brian Seisho
  • Akopyan, Filipp
  • Datta, Pallab

Abrégé

Neural inference chips for computing neural activations are provided. In various embodiments, a neural inference chip comprises at least one neural core, a memory array, an instruction buffer, and an instruction memory. The instruction buffer has a position corresponding to each of a plurality of elements of the memory array. The instruction memory provides at least one instruction to the instruction buffer. The instruction buffer advances the at least one instruction between positions in the instruction buffer. The instruction buffer provides the at least one instruction to at least one of the plurality of elements of the memory array from its associated position in the instruction buffer when the memory of the at least one of the plurality of elements contains data associated with the at least one instruction. Each element of the memory array provides a data block from its memory to its horizontal buffer in response to the arrival of an associated instruction from the instruction buffer. The horizontal buffer of each element of the memory array provides a data block to the horizontal buffer of another of the elements of the memory array or to the at least one neural core.

Classes IPC  ?

  • G06N 3/063 - Réalisation physique, c. à d. mise en oeuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurones utilisant des moyens électroniques

13.

MULTI-VALUE PRIMARY KEYS FOR PLURALITY OF UNIQUE IDENTIFIERS OF ENTITIES

      
Numéro de document 03170205
Statut En instance
Date de dépôt 2021-03-05
Date de disponibilité au public 2021-10-07
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Bodziony, Michal
  • Filip, Marcin
  • Luczynski, Marcin
  • Zatorski, Tomasz
  • Laskawiec, Andrzej
  • Piatek, Monika
  • Studzienny, Lukasz

Abrégé

A computer-implemented method for unambiguously identifying entities in a database system may be provided. The method comprises storing data items as records with different attributes in a table of a database, storing naming rules for selected combinations of the attributes of the data items, and prioritizing the naming rules. The method also comprises determining a hash value for each of the selected combinations of the attributes of the data items, and identifying duplicate data items using the determined hash values and the prioritized naming rules.

Classes IPC  ?

  • G06F 17/00 - TRAITEMENT ÉLECTRIQUE DE DONNÉES NUMÉRIQUES Équipement ou méthodes de traitement de données ou de calcul numérique, spécialement adaptés à des fonctions spécifiques

14.

HYBRID READOUT PACKAGE FOR QUANTUM MULTICHIP BONDING

      
Numéro de document 03165562
Statut En instance
Date de dépôt 2021-03-10
Date de disponibilité au public 2021-10-07
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Shao, Dongbing
  • Lewandowski, Eric
  • Bronn, Nicholas
  • Brink, Markus

Abrégé

Systems and techniques that facilitate hybrid readout packaging for quantum multichip bonding are provided. In various embodiments, an interposer can have a first quantum chip and a second quantum chip. In various aspects, a readout resonator (e.g., input/output port) of one or more qubits on the first quantum chip can be routed to an inner portion of the interposer. In various instances, the inner portion can be located between the first quantum chip and the second quantum chip. In various aspects, routing the readout resonator to the inner portion can reduce a number of crossings and/or intersections between input/output lines on the interposer and connection buses between qubits on the interposer.

Classes IPC  ?

  • G06N 10/00 - Calculateurs quantiques, c. à d. systèmes de calculateurs basés sur des phénomènes de mécanique quantique

15.

REDUCING ATTACK SURFACE BY SELECTIVELY COLLOCATING APPLICATIONS ON HOST COMPUTERS

      
Numéro de document 03165559
Statut En instance
Date de dépôt 2021-03-17
Date de disponibilité au public 2021-09-30
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Le, Michael Vu
  • Jamjoom, Hani Talal
  • Molloy, Ian Michael

Abrégé

Reducing attack surface by selectively collocating applications on host computers is provided. System resources utilized by each application running in a plurality of host computers of a data processing environment are measured. Which applications running in the plurality of host computers that utilize similar system resources are determined. Those applications utilizing similar system resources are collocated on respective host computers.

Classes IPC  ?

  • G06F 9/50 - Allocation de ressources, p.ex. de l'unité centrale de traitement [UCT]
  • G06F 21/57 - Certification ou préservation de plates-formes informatiques fiables, p.ex. démarrages ou arrêts sécurisés, suivis de version, contrôles de logiciel système, mises à jour sécurisées ou évaluation de vulnérabilité
  • G06F 9/4401 - Amorçage

16.

OFFLOADING STATISTICS COLLECTION

      
Numéro de document 03167981
Statut En instance
Date de dépôt 2021-02-24
Date de disponibilité au public 2021-09-30
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Butterstein, Dennis
  • Benke, Oliver
  • Bergmann, Tobias
  • Beier, Felix
  • Purcell, Terence

Abrégé

Methods and systems for generating database statistics. Table statistics in a metadata catalog of a source database system are observed, statistics generation costs utilizing a target database system are estimated, and source statistics generation costs utilizing a source database system are estimated. The statistics generation costs are compared and statistics generation queries by the target database system are triggered in response to the statistics generation costs utilizing the target database system having a predefined relationship with the source statistics generation costs utilizing the source database system. The statistics generation queries are performed by the target database system in response to the triggering by the source database system. The generated statistics are sent from the target database system to the source database system, the table statistics in a metadata catalog are updated based on the generated statistics, and the updated table statistics are used to optimize a query plan.

Classes IPC  ?

  • G06F 16/38 - Recherche caractérisée par l’utilisation de métadonnées, p.ex. de métadonnées ne provenant pas du contenu ou de métadonnées générées manuellement

17.

MULTI-TERMINAL PHASE CHANGE MEMORY DEVICE

      
Numéro de document 03168067
Statut En instance
Date de dépôt 2021-02-12
Date de disponibilité au public 2021-09-30
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Philip, Timothy Matthew
  • Clevenger, Lawrence
  • Brew, Kevin

Abrégé

A phase change memory device is provided. The phase change memory device includes a phase change memory material within an electrically insulating wall, a first heater terminal in the electrically insulating wall, and two read terminals in the electrically insulating wall.

Classes IPC  ?

  • G11C 13/00 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage non couverts par les groupes , ou

18.

MECHANICALLY STAMPED UNIQUE FEATURES FOR AUTHENTICITY AND PROVENANCE TRACKING

      
Numéro de document 03165557
Statut En instance
Date de dépôt 2021-02-15
Date de disponibilité au public 2021-09-30
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Lovchik, Robert Dean
  • Weiss, Jonas
  • Temiz, Yuksel
  • Delamarche, Emmanuel

Abrégé

Technology for managing objects. A method is applied to a set of objects, for example, in view of commissioning such objects. The method includes patterning a surface of each object of a set of objects to be managed. The patterning is accomplished by using hard particles to make indentations in a surface of each object of the set of object, with the pattern formed on each object being a unique physical fingerprint that can be used to identify the object when performing various manage method(s) on the objects

Classes IPC  ?

  • G07D 7/20 - Vérification de motifs des papiers
  • B42D 25/30 - Caractéristiques d’identification ou de sécurité, p.ex. pour empêcher la falsification
  • G07D 7/12 - Lumière visible, rayonnement infrarouge ou ultraviolet

19.

OPTICAL SYNAPSES

      
Numéro de document 03165560
Statut En instance
Date de dépôt 2021-02-15
Date de disponibilité au public 2021-09-30
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Abel, Stefan
  • Offrein, Bert Jan
  • La Porta, Antonio
  • Stark, Pascal

Abrégé

An optical synapse comprises a memristive device for non-volatile storage of a synaptic weight dependent on resistance of the device, and an optical modulator for volatile modulation of optical transmission in a waveguide. The memristive device and optical modulator are connected in control circuitry which is operable, in a write mode, to supply a programming signal to the memristive device to program the synaptic weight and, in a read mode, to supply an electrical signal, dependent on the synaptic weight, to the optical modulator whereby the optical transmission is controlled in a volatile manner in dependence on programmed synaptic weight.

Classes IPC  ?

  • G11C 11/54 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments simulateurs de cellules biologiques, p.ex. neurone

20.

OPERATING A SUPERCONDUCTING CHANNEL BY ELECTRON INJECTION

      
Numéro de document 03168081
Statut En instance
Date de dépôt 2021-03-10
Date de disponibilité au public 2021-09-30
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Fuhrer Janett, Andreas
  • Nichele, Fabrizio
  • Ritter, Markus
  • Riel, Heike

Abrégé

The invention is notably directed to a method of operating a superconducting channel. The method relies on a device including: a potentially superconducting material; a gate electrode; and an electrically insulating medium. A channel is defined by the potentially superconducting material. The gate electrode positioned adjacent to the channel, such that an end surface of the gate electrode faces a portion of the channel. The electrically insulating medium is arranged in such a manner that it electrically insulates the gate electrode from the channel. Rendering the channel superconducting by cooling down the device. Next, a voltage difference is applied between the gate electrode and the channel to inject electrons in the channel through the electrically insulating medium and thereby generate a gate current between the gate electrode and the channel. The electrons are injected with an average energy sufficient to modify a critical current IC of the channel.

Classes IPC  ?

  • H01L 39/16 - Dispositifs commutables entre les états normal et supraconducteur

21.

STAGGERED STACKED VERTICAL CRYSTALLINE SEMICONDUCTING CHANNELS

      
Numéro de document 03165149
Statut En instance
Date de dépôt 2021-02-17
Date de disponibilité au public 2021-09-23
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Kang, Tsung-Sheng
  • Li, Tao
  • Rahman, Ardasheir
  • Joseph, Praveen
  • Seshadri, Indira
  • De Silva, Ekmini Anuja

Abrégé

A semiconductor structure (100) includes a first semiconductor channel having a plurality of vertical nanowires (106) and a second semiconducting channel having a plurality of vertical nanowires (106). The first semiconducting channel and the second semiconducting channel are configured to be in a stacked configuration. The plurality of vertical nanowires (106) of the first semiconducting channel are configurated to be in alternating positions relative to the plurality of vertical nanowires (106) of the second semiconducting channel.

Classes IPC  ?

  • H01L 29/786 - Transistors à couche mince
  • H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS
  • H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires

22.

EVENT CORRELATION IN FAULT EVENT MANAGEMENT

      
Numéro de document 03165155
Statut En instance
Date de dépôt 2021-03-09
Date de disponibilité au public 2021-09-23
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Mills, Peter
  • Buggins, Jack Richard
  • Thornhill, Matthew Richard
  • Suckling, Joshua

Abrégé

A method for predicting cost reduction of event correlation in fault event management includes one or more processors receiving a plurality of candidate correlation groups of events in a set of fault events. The method further includes, for each candidate correlation group of events, one or more processors predicting a resource cost reduction in resolving the respective correlation group of events compared to resolving all events in the respective correlation group individually. The method further includes one or more processors analyzing the predicted resource cost reductions for the plurality of candidate correlation groups of events. The method further includes one or more processors selecting a candidate correlation group based on the analysis of predicted resource cost reductions.

Classes IPC  ?

  • G06Q 10/06 - Ressources, gestion de tâches, gestion d'hommes ou de projets, p.ex. organisation, planification, ordonnancement ou affectation de ressources en temps, hommes ou machines; Planification dans l'entreprise; Modèles organisationnels

23.

ALL-SEMICONDUCTOR JOSEPHSON JUNCTION DEVICE FOR QUBIT APPLICATIONS

      
Numéro de document 03165555
Statut En instance
Date de dépôt 2021-02-16
Date de disponibilité au public 2021-09-23
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Holmes, Steven
  • Sadana, Devendra
  • Gluschenkov, Oleg

Abrégé

According to an embodiment of the present invention, a quantum mechanical device includes a monolithic crystalline structure. The monolithic crystalline structure includes a first region doped to provide a first superconducting region, and a second region doped to provide a second superconducting region, the second superconducting region being separated from the first superconducting region by an undoped crystalline region. The first and second superconducting regions and the undoped crystalline region form a Josephson junction.

Classes IPC  ?

  • H01L 39/02 - Dispositifs utilisant la supraconductivité ou l'hyperconductivité; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives - Détails
  • H01L 39/12 - Dispositifs utilisant la supraconductivité ou l'hyperconductivité; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives - Détails caractérisés par le matériau
  • H01L 39/22 - Dispositifs comportant une jonction de matériaux différents, p.ex. dispositifs à effet Josephson
  • H01L 39/24 - Procédés ou appareils spécialement adaptés à la fabrication ou au traitement des dispositifs couverts par  ou de leurs parties constitutives

24.

AUGMENTED SEMICONDUCTOR LASERS WITH SPONTANEOUS EMISSIONS BLOCKAGE

      
Numéro de document 03166664
Statut En instance
Date de dépôt 2021-01-28
Date de disponibilité au public 2021-09-23
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Frougier, Julien
  • Cheng, Kangguo
  • Xie, Ruilong
  • Park, Chanro

Abrégé

A device and a method to produce an augmented-laser (ATLAS) comprising a bi-stable resistive system (BRS) integrated in series with a semiconductor laser. The laser exhibits reduction/inhibition of the Spontaneous Emission (SE) below lasing threshold by leveraging the abrupt resistance switch of the BRS. The laser system comprises a semiconductor laser and a BRS operating as a reversible switch. The BRS operates in a high resistive state in which a semiconductor laser is below a lasing threshold and emitting in a reduced spontaneous emission regime, and a low resistive state in which a semiconductor laser is above or equal to a lasing threshold and emitting in a stimulated emission regime. The BRS operating as a reversible switch is electrically connected in series across two independent chips or on a single wafer. The BRS is formed using insulator-to-metal transition (IMT) materials or is formed using threshold-switching selectors (TSS).

Classes IPC  ?

  • H01S 5/183 - Lasers à émission de surface [lasers SE], p.ex. comportant à la fois des cavités horizontales et verticales comportant uniquement des cavités verticales, p.ex. lasers à émission de surface à cavité verticale [VCSEL]

25.

PHASE CHANGE MATERIAL SWITCH AND METHOD OF FABRICATING SAME

      
Numéro de document 03167071
Statut En instance
Date de dépôt 2021-02-19
Date de disponibilité au public 2021-09-23
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Shen, Tian
  • Xie, Ruilong
  • Brew, Kevin
  • Wu, Heng
  • Zhang, Jingyun

Abrégé

A phase change material switch includes a phase change layer disposed on a metal liner. A gate dielectric layer is disposed on the phase change layer. A metal gate liner is disposed on the gate dielectric layer.

Classes IPC  ?

  • H01L 27/24 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des composants à l'état solide pour le redressement, l'amplification ou la commutation, sans barrière de potentiel ni barrière de surface
  • H01L 45/00 - Dispositifs à l'état solide spécialement adaptés pour le redressement, l'amplification, la production d'oscillations ou la commutation, sans barrière de potentiel ni barrière de surface, p.ex. triodes diélectriques; Dispositifs à effet Ovshinsky; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives

26.

PREDICTIVE PROVISIONING OF REMOTELY-STORED FILES

      
Numéro de document 03167864
Statut En instance
Date de dépôt 2021-03-11
Date de disponibilité au public 2021-09-23
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Seul, Matthias
  • Korchemniy, Alexandr Pavlovich

Abrégé

A computer system with access to remote files stored on a remote system can predict that a portion of a remote file is likely to be necessary. The computer system may download the portion of the remote file to a local file and update metadata of the local file to reflect the downloaded portion.

27.

MAGNETIC FLUX BIAS FOR PULSE SHAPING OF MICROWAVE SIGNALS

      
Numéro de document 03165144
Statut En instance
Date de dépôt 2021-03-04
Date de disponibilité au public 2021-09-23
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s) Abdo, Baleegh

Abrégé

A technique relates to a pulse shaping of microwave signals. In embodiments a nondegenerate mixing device receives signals and a time-varying magnetic flux via input ports. The nondegenerate mixing device uses the signals and the time-varying magnetic flux to generate an output signal on an output port, the output signal having a waveform profile set by the time-varying magnetic flux.

Classes IPC  ?

  • H03C 1/00 - Modulation d'amplitude
  • G06N 10/40 - Réalisations ou architectures physiques de processeurs ou de composants quantiques pour la manipulation de qubits, p.ex. couplage ou commande de qubit
  • H01L 39/22 - Dispositifs comportant une jonction de matériaux différents, p.ex. dispositifs à effet Josephson
  • H03K 17/92 - Commutation ou ouverture de porte électronique, c. à d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs supraconducteurs

28.

HIGH BANDWIDTH MODULE

      
Numéro de document 03165137
Statut En instance
Date de dépôt 2021-02-18
Date de disponibilité au public 2021-09-16
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Arvin, Charles Leon
  • Singh, Bhupender
  • Li, Shidong
  • Muzzy, Chris
  • Wassick, Thomas Anthony

Abrégé

A module includes a substrate having a plurality of contact regions, and a spacer-chip assembly. The spacer-chip assembly in turn includes at least first and second semiconductor dies, each having a plurality of electrical interconnect pillars and a plurality of contact pads, and a spacer wafer. The at least first and second semiconductor dies are secured to the spacer wafer, and the spacer wafer includes at least first and second semiconductor circuit features coupled to a first portion of the contact pads of the at least first and second semiconductor dies. The spacer wafer includes wiring electrically coupling the at least first and second semiconductor dies via a second portion of the contact pads. The spacer wafer has a plurality of holes formed therethrough. The plurality of electrical interconnect pillars extend through the holes and are secured to the contact regions on the substrate.

Classes IPC  ?

  • H01L 21/66 - Test ou mesure durant la fabrication ou le traitement
  • H01L 21/822 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants le substrat étant un semi-conducteur, en utilisant une technologie au silicium

29.

VIRTUAL MACHINE PERFECT FORWARD SECRECY

      
Numéro de document 03165142
Statut En instance
Date de dépôt 2021-03-10
Date de disponibilité au public 2021-09-16
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Green, Matthew
  • Madineni, Narayana Aditya
  • Gray, Michael
  • Mclean, Leigh

Abrégé

Provided is a method, a computer program product, and a system for providing perfect forward secrecy in virtual machines. The method includes receiving a secure memory allocation function from an application, including a connection secret to be stored in memory. The method further includes allocating memory for the connection secret according to the memory size parameter and storing an entry relating to the connection secret in a secure database. The memory information includes a memory location and a memory size of the memory. The method also includes monitoring an operation state relating to the virtual machine. The method further includes receiving, from the application, a secure deallocation function relating to the connection secret and retrieving the memory information from the secure database. The method also includes deleting the connection from the memory and sanitizing the memory location logged by the memory information.

Classes IPC  ?

  • G06F 21/54 - Contrôle des usagers, programmes ou dispositifs de préservation de l’intégrité des plates-formes, p.ex. des processeurs, des micrologiciels ou des systèmes d’exploitation au stade de l’exécution du programme, p.ex. intégrité de la pile, débordement de tampon ou prévention d'effacement involontaire de données par ajout de routines ou d’objets de sécurité aux programmes
  • G06F 21/78 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du stockage de données
  • G06F 9/455 - Dispositions pour exécuter des programmes spécifiques Émulation; Interprétation; Simulation de logiciel, p.ex. virtualisation ou émulation des moteurs d’exécution d’applications ou de systèmes d’exploitation

30.

AUTOMATED SECURED LOGIN FOR ROBOT PROCESS AUTOMATION APPLICATIONS

      
Numéro de document 03166006
Statut En instance
Date de dépôt 2021-03-01
Date de disponibilité au public 2021-09-16
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s) Seitz, Uwe

Abrégé

The present disclosure includes execution of an application process on a first computer system,where the first computer system is arranged within a first security zone. Access credentials for the application process may be stored in a storage device, where the storage device is arranged within a second security zone. The application process may interact with a further application process. The further application process may be executed on a third computer system, where the further application process is controlled by a graphical user interface of the further application process. An application robot may be executed on the first computer system. The application robot may execute the application process. Further, a login into the first computer system from a second computer system may be executed for gaining access to the application process using the access credentials?

Classes IPC  ?

  • H04L 9/32 - Dispositions pour les communications secrètes ou protégées comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système

31.

RESISTIVE RANDOM ACCESS MEMORY INTEGRATED WITH STACKED VERTICAL TRANSISTORS

      
Numéro de document 03166007
Statut En instance
Date de dépôt 2021-02-25
Date de disponibilité au public 2021-09-16
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Balakrishnan, Karthik
  • Hekmatshoartabari, Bahman
  • Reznicek, Alexander
  • Ando, Takashi

Abrégé

A method may include forming two vertical transport field effect transistors stacked one atop the other and separated by a resistive random access memory structure. The two vertical transport field effect transistors may include a source (104, 112), a channel (106, 110), and a drain, wherein a contact layer (152) of the resistive random access memory strucure functions as the drain of the two vertical transport field effect transistors. Forming the two vertical transport field effect transistors may further include forming a first source (104) and a second source (112). The first source (104) is a bottom source and the second source (112) is a top source. The method may include forming a gate conductor layer (138, 140) surrounding the channel (106, 110). The resistive random access memory structures may include faceted epitaxy (144) defined by pointed tips. The pointed tips of the faceted epitaxy (144) may extend vertically toward each other. The faceted epitaxy (144) may be between the two vertical transport field effect transistors.

Classes IPC  ?

  • H01L 27/24 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des composants à l'état solide pour le redressement, l'amplification ou la commutation, sans barrière de potentiel ni barrière de surface
  • H01L 29/49 - Electrodes du type métal-isolant-semi-conducteur
  • H01L 29/66 - Types de dispositifs semi-conducteurs
  • H01L 45/00 - Dispositifs à l'état solide spécialement adaptés pour le redressement, l'amplification, la production d'oscillations ou la commutation, sans barrière de potentiel ni barrière de surface, p.ex. triodes diélectriques; Dispositifs à effet Ovshinsky; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives

32.

SECURE PRIVATE KEY DISTRIBUTION BETWEEN ENDPOINT INSTANCES

      
Numéro de document 03166663
Statut En instance
Date de dépôt 2021-02-10
Date de disponibilité au public 2021-09-16
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Beck, Michael
  • Smolny, Martin
  • Duerr, Thomas
  • Ochs, Georg
  • Mcbrearty, Gerald
  • Soohoo, Stephen

Abrégé

A method, a computer program product, and a system for distributing a private signature key between authorization instances. The method includes registering a plurality of authorization instances in a configuration file and generating host instance key pairs by each of the authorization instances. The method also includes storing the public host keys in the shared database and electing one of the authorization instances to be a signature key leader instance. The method includes generating, by the signature key leader instance, a signature key pair. The signature key pair includes a public signature key and a private signature key. The method also includes storing the public signature key in the shared database and transmitting an encrypted private signature key to a requesting authorization instance of the authorization instances. The method further includes decrypting the encrypted private signature key using the private host key generated by the requesting authorization instance.

Classes IPC  ?

  • H04L 9/32 - Dispositions pour les communications secrètes ou protégées comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système

33.

DIGITAL IMAGE PROCESSING

      
Numéro de document 03165086
Statut En instance
Date de dépôt 2021-01-27
Date de disponibilité au public 2021-09-10
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Staar, Peter
  • Dolfi, Michele
  • Auer, Christoph
  • Georgopoulos, Leonidas
  • Bekas, Konstantinos

Abrégé

A computer-implemented method for processing a digital image. The digital image comprises one or more text cells, wherein each of the one or more text cells comprises a string and a bounding box. The method comprises receiving the digital image in a first format, the first format providing access to the strings and the bounding boxes of the one more text cells. The methods further comprises encoding the strings of the one or more text cells as visual pattern according to a predefined string encoding scheme and providing the digital image in a second format. The second format comprises the visual pattern of the strings of the one or more text cells. A corresponding system and a related computer program product is provided.

Classes IPC  ?

  • G06K 7/10 - Méthodes ou dispositions pour la lecture de supports d'enregistrement par radiation corpusculaire
  • G06T 1/00 - Traitement de données d'image, d'application générale

34.

EFFICIENT GROUND TRUTH ANNOTATION

      
Numéro de document 03165134
Statut En instance
Date de dépôt 2021-01-28
Date de disponibilité au public 2021-09-10
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Staar, Peter
  • Dolfi, Michelle
  • Auer, Christoph
  • Georgopoulos, Leonidas
  • Kaestner, Ralf
  • Velizhev, Alexander
  • Noguer Hidalgo, Dal
  • Kuznetsova, Rita
  • Bekas, Konstantinos

Abrégé

A computer-implemented method for determining a set of target items to be annotated for training a machine learning application. The method comprises providing a training data set with a set of data samples and an auto-encoder with a classifier. The auto-encoder comprises an embedding model that maps the set of data samples to a set of compressed feature vectors. The set of compressed feature vectors define a compressed feature matrix. Further provided are: a definition of a graph associated to the compressed feature matrix, applying a clustering-algorithm to identify node clusters of the graph and applying a centrality algorithm to identify central nodes of the node clusters, retrieving from an annotator node labels for the central nodes, propagating the annotated node labels to other nodes of the graph and performing a training of the embedding model and the classifier with the annotated and the propagated node labels.

Classes IPC  ?

  • G06K 9/00 - Méthodes ou dispositions pour la lecture ou la reconnaissance de caractères imprimés ou écrits ou pour la reconnaissance de formes, p.ex. d'empreintes digitales

35.

AUTONOMOUS DRIVING EVALUATION USING DATA ANALYSIS

      
Numéro de document 03165017
Statut En instance
Date de dépôt 2021-01-29
Date de disponibilité au public 2021-09-02
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Sakamoto, Yoshifumi
  • Aota, Kentaro
  • Cohn, John
  • Groeger, Hardy

Abrégé

A computer implemented method for evaluating autonomous vehicle safety that includes defining criteria for safety of autonomous vehicles in a test space, and dividing the test space into an intended test space (23) and a un-intended test space (24) for the criteria for safety of autonomous vehicles. The intended test space (23) includes characterizations for the autonomous vehicle that can be quantified, and the un-intended test space (24) includes characterizations that are not quantifiable. The method further includes measuring the safety of the autonomous vehicles in the intended test space (23). The applying the un-intended test space (24) is applied to the intended test space (23) as feedback into the intended test space (23); and evaluating the intended test space (23) including the feedback from the un-intended test space (24) using a combined simulation of peripheral vehicles and autonomous vehicles to provide the evaluation of autonomous vehicle safety.

Classes IPC  ?

  • G06Q 10/06 - Ressources, gestion de tâches, gestion d'hommes ou de projets, p.ex. organisation, planification, ordonnancement ou affectation de ressources en temps, hommes ou machines; Planification dans l'entreprise; Modèles organisationnels
  • G08G 1/16 - Systèmes anticollision

36.

SECURE KEY EXCHANGE IN A COMPUTING ENVIRONMENT

      
Numéro de document 03162797
Statut En instance
Date de dépôt 2021-02-16
Date de disponibilité au public 2021-09-02
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Zee, Mooheng
  • Sczepczenski, Richard Mark
  • Flanagan, John
  • Colonna, Christopher

Abrégé

A computer-implemented method includes receiving an authentication response message at an initiator channel on an initiator node from a responder channel on a responder node to establish a secure communication, the receiving at a local key manager (LKM) executing on the initiator node. A state check is performed based on a security association of the initiator node and the responder node. A validation of the authentication response message is performed. An identifier of a selected encryption algorithm is extracted from the authentication response message. The initiator channel requests to communicate with the responder channel based at least in part on a successful state check, a successful validation, and the selected encryption algorithm.

37.

OPTIMAL INTERPRETABLE DECISION TREES USING INTEGER PROGRAMMING TECHNIQUES

      
Numéro de document 03163625
Statut En instance
Date de dépôt 2021-02-15
Date de disponibilité au public 2021-08-26
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Murali, Pavankumar
  • Zhu, Haoran
  • Phan, Dzung Tien
  • Nguyen, Lam Minh

Abrégé

Aspects of the invention include an optimal interpretable decision tree using integer linear programming techniques. A non-limiting example computer-implemented method includes receiving, using a processor, a plurality of data inputs from a process and selecting, using the processor, a data subset from the plurality of data inputs by solving linear programming to obtain a solution. The method builds and optimizes, using the processor, an optimal decision tree based on the data subset and alerts, using the processor, a user when a prediction of the optimal decision tree is greater than a threshold value.

Classes IPC  ?

  • G06F 17/00 - TRAITEMENT ÉLECTRIQUE DE DONNÉES NUMÉRIQUES Équipement ou méthodes de traitement de données ou de calcul numérique, spécialement adaptés à des fonctions spécifiques
  • G06N 5/00 - Systèmes de calculateurs utilisant des modèles basés sur la connaissance

38.

LEARNING WITH MOMENT ESTIMATION USING DIFFERENT TIME CONSTANTS

      
Numéro de document 03165001
Statut En instance
Date de dépôt 2021-02-04
Date de disponibilité au public 2021-08-19
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s) Morimura, Tetsuro

Abrégé

A technique for training a model includes obtaining a training example for a model having model parameters stored on one or more computer readable storage mediums operably coupled to the hardware processor. The training example includes an outcome and features to explain the outcome. A gradient is calculated with respect to the model parameters of the model using the training example. Two estimates of a moment of the gradient with two different time constants are computed for the same type of the moment using the gradient. Using a hardware processor, the model parameters of the model are updated using the two estimates of the moment with the two different time constants to reduce errors while calculating the at least two estimates of the moment of the gradient.

Classes IPC  ?

  • G06N 3/04 - Architecture, p.ex. topologie d'interconnexion

39.

ENCRYPTION FOR MESSAGE QUEUES

      
Numéro de document 03163037
Statut En instance
Date de dépôt 2021-01-10
Date de disponibilité au public 2021-08-12
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s) Giblin, Christopher

Abrégé

A targeted, topic-based encryption in a publish-subscribe message queue. Topic-based encryption driven by encryption policies for both storing and receiving messages uses activity tracking and logging to ensure confidentiality of certain topics associated with stored encrypted messages. Authentication of both publisher and consumer ensure encryption and decryption keys are used in confidence.

40.

ESTIMATION OF CROP TYPE AND/OR SOWING DATE

      
Numéro de document 03163624
Statut En instance
Date de dépôt 2021-01-26
Date de disponibilité au public 2021-08-12
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Tewari, Mukul
  • Singh, Jitendra
  • Dey, Kuntal

Abrégé

Method, apparatus, and computer program product are provided for estimating crop type and/or sowing date. A historical crop growth time series and a plurality of simulated crop growth time series are determined, and the historical time series is matched against each simulated time series to determine an estimated crop type and/or sowing date. For example, one simulated time series may be determined for each crop type/sowing date combination within a set of one or more crop types and one or more sowing dates based on historical crop data. Each time series represents crop growth in an area of interest and comprises element(s) including crop-specific parameter(s), such as leaf area index (LAI). The historical time series may be determined based on remote sensor data. Each simulated time series may be determined using a crop growth simulation model and based on historical crop data, geospatial data, and weather data.

Classes IPC  ?

  • G06Q 50/02 - Agriculture; Pêche; Exploitation minière
  • G06Q 10/04 - Prévision ou optimisation, p.ex. programmation linéaire, "problème du voyageur de commerce" ou "problème d'optimisation des stocks"
  • G06Q 10/06 - Ressources, gestion de tâches, gestion d'hommes ou de projets, p.ex. organisation, planification, ordonnancement ou affectation de ressources en temps, hommes ou machines; Planification dans l'entreprise; Modèles organisationnels

41.

PERFORMING SEARCH BASED ON POSITION INFORMATION

      
Numéro de document 03162787
Statut En instance
Date de dépôt 2021-01-19
Date de disponibilité au public 2021-07-29
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Watanabe, Kenta
  • Ishikawa, Shunsuke
  • Ono, Asako
  • Uetsuki, Hiroaki
  • Tominaga, Yasuyuki
  • Hasegawa, Tohru

Abrégé

Provided are techniques for performing a search based on position information. A search request that provides location information for a region of a screen image is received (900). A selection of a type indicator is received, where the type indicator indicates one of a text item and an image (902). In response to the type indicator indicating the text item (904), one or more of the text item and a date and time are received (906). A search is performed using the location information and the one or more of the text item and the date and time to identify one or more screen image identifiers of one or more corresponding screen images of a plurality of screen images (908). The one or more screen image identifiers are used to retrieve the one or more corresponding screen images (910). The one or more corresponding screen images are displayed as search results (912).

Classes IPC  ?

  • G06F 16/58 - Recherche caractérisée par l’utilisation de métadonnées, p.ex. de métadonnées ne provenant pas du contenu ou de métadonnées générées manuellement

42.

HIERARCHICAL DATA

      
Numéro de document 03163038
Statut En instance
Date de dépôt 2021-01-12
Date de disponibilité au public 2021-07-22
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Coleman, Andrew John
  • Reeve, John Anthony
  • Dolby, Trevor Clifford

Abrégé

A computer-implemented method, system and computer program product for identifying ancestor objects in hierarchical data configured for processing with a query, the query having an associated abstract syntax tree. The abstract syntax tree may be processed so as to generate an augmented abstract syntax tree which includes parent identifiers configured to identify the parent nodes of the query. In this way, a need to pre-parse the data may be alleviated. Instead, the identification of a parent node of a query may be encoded into the abstract syntax tree of the query.

Classes IPC  ?

43.

SUPERCONDUCTING INTERPOSER FOR OPTICAL TRANSDUCTION OF QUANTUM INFORMATION

      
Numéro de document 03143377
Statut En instance
Date de dépôt 2020-06-23
Date de disponibilité au public 2020-12-30
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Bronn, Nicholas Torleiv
  • Bogorin, Daniela Florentina
  • Gumann, Patryk
  • Hart, Sean
  • Olivadese, Salvatore Bernardo
  • Orcutt, Jason

Abrégé

A system for optical transduction of quantum information includes a qubit chip including a plurality of data qubits configured to operate at microwave frequencies, and a transduction chip spaced apart from the qubit chip, the transduction chip including a microwave-to-optical frequency transducer. The system includes an interposer coupled to the qubit chip and the transduction chip, the interposer including a dielectric material including a plurality of superconducting microwave waveguides formed therein. The plurality of superconducting microwave waveguides is configured to transmit quantum information from the plurality of data qubits to the microwave-to-optical frequency transducer on the transduction chip, and the microwave-to-optical frequency transducer is configured to transduce the quantum information from the microwave frequencies to optical frequencies.

Classes IPC  ?

  • G06N 10/40 - Réalisations ou architectures physiques de processeurs ou de composants quantiques pour la manipulation de qubits, p.ex. couplage ou commande de qubit

44.

CRYPTOGRAPHIC KEY ORCHESTRATION BETWEEN TRUSTED CONTAINERS IN A MULTI-NODE CLUSTER

      
Numéro de document 03143383
Statut En instance
Date de dépôt 2020-06-10
Date de disponibilité au public 2020-12-30
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Rodriguez, Eduardo
  • Karnati, Pratheek
  • Bojjireddy, Karunakar

Abrégé

Accessing shared sensitive information in a managed container environment is provided. Each worker node in a plurality of worker nodes has access to shared sensitive application data located in a secure enclave within the plurality of worker nodes using a data encryption key. Each worker node in the plurality of worker nodes protects the data encryption key of each respective worker node using a sealing key that is unique to the secure enclave on a respective worker node.

Classes IPC  ?

  • H04L 9/08 - Répartition de clés
  • H04L 9/32 - Dispositions pour les communications secrètes ou protégées comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système

45.

FABRICATING TRANSMON QUBIT FLIP-CHIP STRUCTURES FOR QUANTUM COMPUTING DEVICES

      
Numéro de document 03143396
Statut En instance
Date de dépôt 2020-06-15
Date de disponibilité au public 2020-12-24
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Chow, Jerry
  • Rosenblatt, Sami

Abrégé

A quantum computing device (300) is formed using a first chip (302) and a second chip (306), the first chip having a first substrate (303), a first set of pads (312 A,B), and a set of Josephson junctions (304) disposed on the first substrate. The second chip has a second substrate (307), a second set of pads (308) disposed on the second substrate opposite the first set of pads, and a second layer (310 A, B) formed on a subset of the second set of pads. The second layer is configured to bond the first chip and the second chip. The subset of the second set of pads corresponds to a subset of the set of Josephson junctions selected to avoid frequency collision between qubits in a set of qubits. A qubit is formed using a Josephson junction from the subset of Josephson junctions and another Josephson junction not in the subset being rendered unusable for forming qubits.

Classes IPC  ?

  • G06N 10/00 - Calculateurs quantiques, c. à d. systèmes de calculateurs basés sur des phénomènes de mécanique quantique
  • H01L 27/18 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des composants présentant un effet de supraconductivité
  • H01L 39/22 - Dispositifs comportant une jonction de matériaux différents, p.ex. dispositifs à effet Josephson
  • H01L 39/24 - Procédés ou appareils spécialement adaptés à la fabrication ou au traitement des dispositifs couverts par  ou de leurs parties constitutives

46.

THERMALIZATION STRUCTURE FOR DEVICES COOLED TO CRYOGENIC TEMPERATURE

      
Numéro de document 03143360
Statut En instance
Date de dépôt 2020-05-13
Date de disponibilité au public 2020-12-24
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Lewandowski, Eric Peter
  • Webb, Bucknell
  • Hertzberg, Jared Barney
  • Sandberg, Martin
  • Jinka, Oblesh

Abrégé

A thermalization structure is formed using a foil and a low temperature device (LTD). The foil includes a first layer of a first material. The LTD includes a surface from which heat is transferred away from the LTD. A coupling is formed between the foil and the surface of the LTD, where the coupling includes a bond formed between the foil and the surface such that forming the bond forms a set of ridges in the foil, a ridge in the set of ridges operating to dissipate the heat.

Classes IPC  ?

  • H01L 23/36 - Emploi de matériaux spécifiés ou mise en forme, en vue de faciliter le refroidissement ou le chauffage, p.ex. dissipateurs de chaleur
  • H01L 39/00 - Dispositifs utilisant la supraconductivité ou l'hyperconductivité; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives

47.

HOMOMORPHIC ENCRYPTION WITH APPLICATIONS TO PRIVATE INFORMATION RETRIEVAL

      
Numéro de document 03143362
Statut En instance
Date de dépôt 2020-06-15
Date de disponibilité au public 2020-12-24
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Gentry, Craig Broadwell
  • Halevi, Shai

Abrégé

A request is received for specific information that can be determined using data in a database on a first computer system. Either at least some of the data is encrypted or the request is encrypted. The first computer system does not have a decryption key to decrypt the encrypted data or request. The first computer system peforms compressible HE operations on the data to determine compressed ciphertext(s) that correspond to the specific information. The operations include using a first uncompressed HE scheme and a second compressed HE scheme. The first HE scheme is used on the data to create other multiple ciphertexts and the second HE scheme is used on the other multiple ciphertexts to pack the other multiple ciphertexts into fewer ciphertexts that are compressed. Both the HE schemes use a same secret key. The first computer system sends a response including compressed ciphertext(s) corresponding to the specific information.

Classes IPC  ?

  • H04L 9/00 - Dispositions pour les communications secrètes ou protégées

48.

SUPERCONDUCTING INTERPOSER FOR THE TRANSMISSION OF QUANTUM INFORMATION FOR QUANTUM ERROR CORRECTION

      
Numéro de document 03143363
Statut En instance
Date de dépôt 2020-05-21
Date de disponibilité au public 2020-12-24
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Bronn, Nicholas
  • Bogorin, Daniela
  • Gumann, Patryk
  • Hart, Sean
  • Olivadese, Salvatore

Abrégé

A system for transmission of quantum information for quantum error correction includes an ancilla qubit chip including a plurality of ancilla qubits, and a data qubit chip spaced apart from the ancilla qubit chip, the data qubit chip including a plurality of data qubits. The system includes an interposer coupled to the ancilla qubit chip and the data qubit chip, the interposer including a dielectric material and a plurality of superconducting structures formed in the dielectric material. The superconducting structures enable transmission of quantum information between the plurality of data qubits on the data qubit chip and the plurality of ancilla qubits on the ancilla qubit chip via virtual photons for quantum error correction.

Classes IPC  ?

  • G06N 10/40 - Réalisations ou architectures physiques de processeurs ou de composants quantiques pour la manipulation de qubits, p.ex. couplage ou commande de qubit
  • G06N 10/70 - Correction, détection ou prévention d’erreur quantique, p.ex. codes de surface ou distillation d’état magique
  • H01L 27/18 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des composants présentant un effet de supraconductivité

49.

CRYOGENIC PACKAGING FOR THERMALIZATION OF LOW TEMPERATURE DEVICES

      
Numéro de document 03143434
Statut En instance
Date de dépôt 2020-06-19
Date de disponibilité au public 2020-12-24
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Jinka, Oblesh
  • Olivadese, Salvatore Bernardo
  • Hart, Sean
  • Bronn, Nicholas Torleiv
  • Chow, Jerry
  • Brink, Markus
  • Gumann, Patryk
  • Bogorin, Daniela Florentina

Abrégé

A thermalization structure is formed using a cover configured with a set of pillars, the cover being a part of a cryogenic enclosure of a low temperature device (LTD). A chip including the LTD is configured with a set of cavities, a cavity in the set of cavities having a cavity profile. A pillar from the set of pillars and corresponding to the cavity has a pillar profile such that the pillar profile causes the pillar to couple with the cavity of the cavity profile within a gap tolerance to thermally couple the chip to the cover for heat dissipation in a cryogenic operation of the chip.

Classes IPC  ?

  • H01L 23/367 - Refroidissement facilité par la forme du dispositif
  • F25D 3/10 - Dispositifs utilisant d'autres agents froids; Dispositifs utilisant des récipients conservant le froid utilisant des gaz liquéfiés, p.ex. de l'air liquide
  • F25D 31/00 - Autres appareils de refroidissement ou de congélation
  • F28D 21/00 - Appareils échangeurs de chaleur non couverts par l'un des groupes
  • H01L 39/04 - Conteneurs; Supports
  • H05K 7/20 - Modifications en vue de faciliter la réfrigération, l'aération ou le chauffage

50.

PARTICLE-BASED, ANISOTROPIC COMPOSITE MATERIALS FOR MAGNETIC CORES

      
Numéro de document 03144801
Statut En instance
Date de dépôt 2020-06-04
Date de disponibilité au public 2020-12-24
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Sridhar, Arvind Raj Mahankali
  • Brunschwiler, Thomas
  • Ye, Suiying
  • Del Carro, Luca
  • Ammann, Jens Oliver

Abrégé

A magnetic core comprises an anisotropic, composite material, which itself includes a matrix material (e.g., a dielectric, non-magnetic material, preferably a paramagnetic material), and magnetically aligned, ferromagnetic particles. The latter may for instance include micrometer- and/or nanometer-length scale particles. Such particles form chains of particles within the matrix material, wherein the chains form percolation paths of magnetic conduction. The paths extend along a first direction, whereby the chains extend, each, substantially along this first direction, while being distinct and distant from each other along a second direction that is perpendicular to the first direction and, possibly, to a third direction that is perpendicular to both the first direction and the second direction. Necking bridges are preferably formed between the particles. Related devices (e.g., inductor, amplifiers, transformers, etc.) and fabrication methods are also disclosed.

Classes IPC  ?

  • H01F 3/08 - Noyaux, culasses ou induits en poudre
  • H01F 1/28 - Aimants ou corps magnétiques, caractérisés par les matériaux magnétiques appropriés; Emploi de matériaux spécifiés pour leurs propriétés magnétiques en matériaux inorganiques caractérisés par leur coercivité en matériaux magnétiques doux métaux ou alliages sous forme de particules, p.ex. de poudre dispersées ou suspendues dans un liant
  • H01F 41/16 - Appareils ou procédés spécialement adaptés à la fabrication ou à l'assemblage des aimants, des inductances ou des transformateurs; Appareils ou procédés spécialement adaptés à la fabrication des matériaux caractérisés par leurs propriétés magnétiques pour appliquer des pellicules magnétiques sur des substrats le matériau magnétique étant appliqué sous forme de particules, p.ex. par sérigraphie

51.

EXECUTING SYSTEM CALLS IN ISOLATED ADDRESS SPACE IN OPERATING SYSTEM KERNEL

      
Numéro de document 03137259
Statut En instance
Date de dépôt 2020-05-15
Date de disponibilité au public 2020-11-26
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Rapoport, Michael
  • Nider, Joel Kelly
  • Bottomley, James

Abrégé

Embodiments of the present systems and methods may provide additional security mechanisms inside an operating system kernel itself by executing system calls in a dedicated address space to reduce the amount of shared resources that are visible to and thus exploitable by a malicious application. For example, in an embodiment, a method implemented in a computer may comprise a processor, memory accessible by the processor, and computer program instructions stored in the memory and executable by the processor, the method may comprise: when a user process makes a system call, switching to kernel mode and using a system call page table for the user process to execute a system call handler, when the system call handler attempts to access unmapped kernel space memory, generating a page fault, and handling the page fault by determining whether the attempted access to unmapped kernel space memory is allowed.

Classes IPC  ?

  • G06F 9/44 - Dispositions pour exécuter des programmes spécifiques
  • G06F 21/53 - Contrôle des usagers, programmes ou dispositifs de préservation de l’intégrité des plates-formes, p.ex. des processeurs, des micrologiciels ou des systèmes d’exploitation au stade de l’exécution du programme, p.ex. intégrité de la pile, débordement de tampon ou prévention d'effacement involontaire de données par exécution dans un environnement restreint, p.ex. "boîte à sable" ou machine virtuelle sécurisée
  • G06F 9/54 - Communication interprogramme
  • G06F 12/14 - Protection contre l'utilisation non autorisée de mémoire

52.

MANAGING DATA AND DATA USAGE IN IOT NETWORK

      
Numéro de document 03137229
Statut En instance
Date de dépôt 2020-05-05
Date de disponibilité au public 2020-11-26
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Rodriguez Bravo, Cesar Augusto
  • Zamora Duran, Edgar Adolfo
  • Trim, Craig
  • Liebinger Portela, Franz Friedrich

Abrégé

In an approach, a processor receives from a network device a request. A processor obtains from a database a device profile for the network device. A processor determines whether the device profile of the network device has a data usage pattern related to data identified by a data identifier. In response to determining the device profile has a related data usage pattern, a processor receives the related data usage pattern from the database. In response to determining the device profile does not have a related data usage pattern, a processor obtains a device type profile from the database. A processor classifies the data usage request based on at least one of the device profile and the device type profile. A processor executes a security action based on the classification of the data usage request. A processor stores the data usage request and executed security action to the database.

Classes IPC  ?

  • H04L 43/065 - liés aux appareils du réseau
  • G06F 21/44 - Authentification de programme ou de dispositif
  • H04W 4/70 - Services pour la communication de machine à machine ou la communication de type machine
  • H04L 67/303 - Profils des terminaux

53.

LIMITED EXECUTION ENVIRONMENT FOR MONOLITHIC KERNEL

      
Numéro de document 03137254
Statut En instance
Date de dépôt 2020-05-15
Date de disponibilité au public 2020-11-26
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Nider, Joel Kelly
  • Rapoport, Michael
  • Bottomley, James

Abrégé

Embodiments of the present systems and methods may provide additional security mechanisms inside an operating system kernel itself by isolating parts of the kernel to protect them from attacks. For example, in an embodiment, a computer-implemented method implemented in a computer comprising a processor, memory accessible by the processor, and computer program instructions stored in the memory and executable by the processor, the method may comprise: creating a namespace in an operating system kernel-space in the memory of the computer, creating an address space for the namespace that maps only kernel objects owned by the namespace, and providing access to kernel objects owned by the namespace only to the least one user process using the combined page table.

Classes IPC  ?

  • G06F 21/53 - Contrôle des usagers, programmes ou dispositifs de préservation de l’intégrité des plates-formes, p.ex. des processeurs, des micrologiciels ou des systèmes d’exploitation au stade de l’exécution du programme, p.ex. intégrité de la pile, débordement de tampon ou prévention d'effacement involontaire de données par exécution dans un environnement restreint, p.ex. "boîte à sable" ou machine virtuelle sécurisée
  • G06F 21/55 - Détection d’intrusion locale ou mise en œuvre de contre-mesures

54.

TRAINING OF ARTIFICIAL NEURAL NETWORKS

      
Numéro de document 03137231
Statut En instance
Date de dépôt 2020-05-12
Date de disponibilité au public 2020-11-19
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Le Gallo-Bourdeau, Manuel
  • Khaddam-Aljameh, Riduan
  • Kull, Lukas
  • Francese, Pier Andrea
  • Toifl, Thomas
  • Sebastian, Abu
  • Eleftheriou, Evangelos Stavros

Abrégé

Methods and apparatus are provided for training an artificial neural network having a succession of neuron layers with interposed synaptic layers each having a respective set of N-bit fixed-point weights {w} for weighting signals propagated between its adjacent neuron layers, via an iterative cycle of signal propagation and weight-update calculation operations. Such a method includes, for each synaptic layer, storing a plurality p of the least-significant bits of each N-bit weight w in digital memory, and storing the next n-bit portion of each weight w in an analog multiply-accumulate unit comprising an array of digital memory elements. Each digital memory element comprises n binary memory cells for storing respective bits of the n-bit portion of a weight, where n = 1 and (p + n + m) = N where m = 0 corresponds to a defined number of most-significant zero bits in weights of the synaptic layer.

Classes IPC  ?

  • G06N 3/063 - Réalisation physique, c. à d. mise en oeuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurones utilisant des moyens électroniques
  • G06N 3/08 - Méthodes d'apprentissage

55.

RELATIONSHIP DISCOVERY

      
Numéro de document 03137226
Statut En instance
Date de dépôt 2020-05-01
Date de disponibilité au public 2020-11-12
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Sadacharam, Saravanan
  • Bhide, Manish Anand
  • Ekambaram, Vijay
  • Ananthapur Bache, Vijay Kumar

Abrégé

Relationship discovery can include receiving at a first mobile device a pair of ultrasonic signals conveyed at different frequencies from a second mobile device. The pair of ultrasonic signals can convey, respectively, a second user's contact information in an encrypted form and a key indicator. A contact number can be selected from a first user's contact list electronically stored on the first mobile device. The contact number can be selected based on the key indicator. A mutual contact can be identified in response to decrypting the second user's contact information using the contact number as a decryption key.

Classes IPC  ?

  • H04B 11/00 - Systèmes de transmission utilisant des ondes ultrasonores, sonores ou infrasonores
  • H04W 8/00 - Gestion de données relatives au réseau
  • H04W 84/18 - Réseaux auto-organisés, p.ex. réseaux ad hoc ou réseaux de détection

56.

THROUGH-SILICON-VIA FABRICATION IN PLANAR QUANTUM DEVICES

      
Numéro de document 03137245
Statut En instance
Date de dépôt 2020-03-20
Date de disponibilité au public 2020-11-05
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Rubin, Joshua
  • Hertzberg, Jared
  • Rosenblatt, Sami
  • Vivekananda, Adiga
  • Brink, Markus
  • Kumar, Arvind

Abrégé

On a first superconducting layer (316) deposited on a first surface of a substrate (312), a first component of a resonator is pattered. On a second superconducting layer (326) deposited on a second surface of the substrate (312), a second component of the resonator is patterned. The first surface and the second surface are disposed relative to each other in a non-co-planar disposition. In the substrate, a recess is created, the recess extending from the first superconducting layer to the second superconducting layer. On an inner surface of the recess, a third superconducting layer (322) is deposited, the third superconducting layer forming a superconducting path between the first superconducting layer and the second superconducting layer. Excess material of the third superconducting layer is removed from the first surface and the second surface, forming a completed through-silicon via TSV (320).

Classes IPC  ?

  • H01L 27/18 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des composants présentant un effet de supraconductivité
  • H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
  • H01L 39/02 - Dispositifs utilisant la supraconductivité ou l'hyperconductivité; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives - Détails
  • H01L 39/24 - Procédés ou appareils spécialement adaptés à la fabrication ou au traitement des dispositifs couverts par  ou de leurs parties constitutives

57.

PERSISTENT FLUX BIASING METHODOLOGY FOR SUPERCONDUCTING LOOPS

      
Numéro de document 03137258
Statut En instance
Date de dépôt 2020-03-27
Date de disponibilité au public 2020-10-29
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Sandberg, Martin
  • Rosenblatt, Sami
  • Topaloglu, Rasit Onur

Abrégé

A tunable qubit device includes a tunable qubit, the tunable qubit including a superconducting quantum interference device (SQUID) loop. The tunable qubit device further includes a superconducting loop inductively coupled to the SQUID loop, and a flux bias line inductively coupled to the superconducting loop. The superconducting loop includes a superconducting material having a critical temperature that is a lower temperature than a critical temperature of any superconducting material of the tunable qubit. In operation, the superconducting loop provides a persistent bias to the tunable qubit.

Classes IPC  ?

  • G06N 10/40 - Réalisations ou architectures physiques de processeurs ou de composants quantiques pour la manipulation de qubits, p.ex. couplage ou commande de qubit
  • B82Y 10/00 - Nanotechnologie pour le traitement, le stockage ou la transmission d’informations, p.ex. calcul quantique ou logique à un électron
  • H01L 27/18 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des composants présentant un effet de supraconductivité
  • H01L 39/12 - Dispositifs utilisant la supraconductivité ou l'hyperconductivité; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives - Détails caractérisés par le matériau
  • H03K 19/195 - Circuits logiques, c. à d. ayant au moins deux entrées agissant sur une sortie; Circuits d'inversion utilisant des éléments spécifiés utilisant des dispositifs supraconducteurs

58.

QUANTUM CODE FOR REDUCED FREQUENCY COLLISIONS IN QUBIT LATTICES

      
Numéro de document 03137264
Statut En instance
Date de dépôt 2020-03-27
Date de disponibilité au public 2020-10-29
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Cross, Andrew
  • Chamberland, Christopher
  • Gambetta, Jay Michael
  • Hertzberg, Jared
  • Yoder, Theodore
  • Zhu, Guanyu

Abrégé

A quantum computer includes a quantum processor that includes a first plurality of qubits arranged in a hexagonal lattice pattern such that each is substantially located at a hexagon apex, and a second plurality of qubits each arranged substantially along a hexagon edge. Each of the first plurality of qubits is coupled to three nearest-neighbor qubits of the second plurality of qubits, and each of the second plurality of qubits is coupled to two nearest-neighbor qubits of the first plurality of qubits. Each of the second plurality of qubits is a control qubit at a control frequency. Each of the first plurality of qubits is a target qubit at one of a first target frequency or a second target frequency. The quantum computer includes an error correction device configured to operate on the hexagonal lattice pattern of the plurality of qubits so as to detect and correct data errors.

Classes IPC  ?

  • G06N 10/20 - Modèles d’informatique quantique, p.ex. circuits quantiques ou ordinateurs quantiques universels
  • G06N 10/70 - Correction, détection ou prévention d’erreur quantique, p.ex. codes de surface ou distillation d’état magique

59.

EXTRACTING DATA FROM A BLOCKCHAIN NETWORK

      
Numéro de document 03137242
Statut En instance
Date de dépôt 2020-03-19
Date de disponibilité au public 2020-10-29
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Oberhofer, Martin
  • Mentzel, Florian
  • Pham The, Hien
  • Thevarajah, Thishanth

Abrégé

The invention relates to a method for a model-driven extraction of event data representing an event occurring on a blockchain network by a computational device with access to the blockchain network. The computational device is configured as an ETL-device for executing an ETL-code to modify a data content of an external data structure external of the blockchain network using the extracted event data. The method comprising detecting the event, determining an event schema, providing and executing a the ETL-code. The ETL- code comprises machine-executable instructions for extracting the event data representing the detected event, transforming the extracted event data using the event schema to comply with a data model defining a logical structure of the external data structure and loading the transformed data to the external data structure to modify the data content of the external data structure.

Classes IPC  ?

  • H04L 9/32 - Dispositions pour les communications secrètes ou protégées comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
  • G06F 16/25 - Systèmes d’intégration ou d’interfaçage impliquant les systèmes de gestion de bases de données

60.

QUBIT FREQUENCY TUNING STRUCTURES AND FABRICATION METHODS FOR FLIP CHIP QUANTUM COMPUTING DEVICES

      
Numéro de document 03137214
Statut En instance
Date de dépôt 2020-04-15
Date de disponibilité au public 2020-10-22
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Shao, Dongbing
  • Brink, Markus
  • Solgun, Firat
  • Hertzberg, Jared Barney

Abrégé

A quantum computing device includes a first chip having a first substrate and one or more qubits disposed on the first substrate. Each of the one or more qubits has an associated resonance frequency. The quantum computing device further includes a second chip having a second substrate and at least one conductive surface disposed on the second substrate opposite the one or more qubits. The at least one conductive surface has at least one dimension configured to adjust the resonance frequency associated with at least one of the one or more qubits to a determined frequency adjustment value.

Classes IPC  ?

  • G06N 10/40 - Réalisations ou architectures physiques de processeurs ou de composants quantiques pour la manipulation de qubits, p.ex. couplage ou commande de qubit
  • B82Y 10/00 - Nanotechnologie pour le traitement, le stockage ou la transmission d’informations, p.ex. calcul quantique ou logique à un électron
  • H01L 39/22 - Dispositifs comportant une jonction de matériaux différents, p.ex. dispositifs à effet Josephson

61.

VERTICAL SUPERINDUCTOR DEVICE

      
Numéro de document 03137255
Statut En instance
Date de dépôt 2020-03-25
Date de disponibilité au public 2020-10-22
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Sandberg, Martin
  • Adiga, Vivekananda
  • Topaloglu, Rasit Onur

Abrégé

A fluxonium qubit includes (400) a superinductor (402). The superinductor includes a substrate (404), and a first vertical stack (406) extending in a vertical direction from a surface (406) of the substrate (404). The first vertical stack includes a first Josephson junction (410) and a second Josephson junction (412) connected in series along the vertical direction. The superinductor includes a second vertical stack (414) extending in a vertical direction from a surface of the substrate. The second vertical stack includes a third Josephson junction (416). The superinductor includes a superconducting connector (420) connecting the first and second vertical stacks in series such that the first, second, and third Josephson junctions are connected in series. The fluxonium qubit further includes a shunted Josephson junction (422) connected to the superinductor with superconducting wires (424, 426) such that the first, second, and third Josephson junctions of the superinductor that are in series are connected in parallel with the shunted Josephson junction.

Classes IPC  ?

  • H01L 27/18 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des composants présentant un effet de supraconductivité
  • B82Y 10/00 - Nanotechnologie pour le traitement, le stockage ou la transmission d’informations, p.ex. calcul quantique ou logique à un électron
  • H01L 39/22 - Dispositifs comportant une jonction de matériaux différents, p.ex. dispositifs à effet Josephson
  • H01L 39/24 - Procédés ou appareils spécialement adaptés à la fabrication ou au traitement des dispositifs couverts par  ou de leurs parties constitutives

62.

DETECTING SENSITIVE DATA EXPOSURE VIA LOGGING

      
Numéro de document 03137249
Statut En instance
Date de dépôt 2020-03-23
Date de disponibilité au public 2020-10-22
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Udupi Raghavendra, Arjun
  • Seul, Matthias
  • Scheideler, Tim
  • Airoldi, Tiziano

Abrégé

A computer-implemented method for dynamically identifying security threats comprising a cyber-attack chain composed of a sequence of partial cyber-attacks represented by attack patterns is provided. The method comprises receiving a sequence of security events, determining, a first cyber-attack pattern by applying a set of predefined rules for detecting an indicator of compromise of a first partial cyber-attack of the cyber-attack chain thereby, identifying a specific cyber-attack chain and determining a type and an attribute in the pattern of the first partial cyber-attack. The method comprises further configuring at least one rule for a downstream partial cyber-attack in the specific cyber-attack chain based on the type and the attribute in the attack pattern of the first partial cyber-attack, and adding the at least one configured rule to the set of predefined rules to be used by the correlation engine for dynamically identifying security threats.

Classes IPC  ?

  • H04L 9/40 - Protocoles réseaux de sécurité
  • G06F 21/55 - Détection d’intrusion locale ou mise en œuvre de contre-mesures

63.

MEASUREMENT SCHEME FOR SUPERCONDUCTING QUBITS USING LOW-FREQUENCY MICROWAVE SIGNALS WITHIN A DILUTION REFRIGERATOR

      
Numéro de document 03170016
Statut En instance
Date de dépôt 2020-03-23
Date de disponibilité au public 2020-10-22
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s) Abdo, Baleegh

Abrégé

Techniques that facilitate a measurement scheme for superconducting qubits using low-frequency microwave signals within a dilution refrigerator are provided. In one example, a cryogenic microwave system for measuring superconducting qubits using microwave signals includes a dilution refrigerator system for a quantum processor. The dilution refrigerator system converts a microwave signal associated with qubit information into a reduced-frequency microwave signal based on a Josephson-mixer circuit located within the dilution refrigerator system. The reduced-frequency microwave signal includes a frequency below a qubit frequency and a readout resonator frequency associated with the quantum processor.

Classes IPC  ?

  • G06N 10/00 - Calculateurs quantiques, c. à d. systèmes de calculateurs basés sur des phénomènes de mécanique quantique

64.

TRANSMON QUBITS WITH TRENCHED CAPACITOR STRUCTURES

      
Numéro de document 03136508
Statut En instance
Date de dépôt 2020-04-06
Date de disponibilité au public 2020-10-15
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Adiga, Vivekananda
  • Sandberg, Martin
  • Chow, Jerry
  • Paik, Hanhee

Abrégé

A qubit includes a substrate, and a first capacitor structure having a lower portion formed on a surface of the substrate and at least one first raised portion extending above the surface of the substrate. The qubit further includes a second capacitor structure having a lower portion formed on the surface of the substrate and at least one second raised portion extending above the surface of the substrate. The first capacitor structure and the second capacitor structure are formed of a superconducting material. The qubit further includes a junction between the first capacitor structure and the second capacitor structure. The junction is disposed at a predetermined distance from the surface of the substrate and has a first end in contact with the first raised portion and a second end in contact with the second raised portion.

Classes IPC  ?

  • H01L 27/18 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des composants présentant un effet de supraconductivité
  • H01L 39/22 - Dispositifs comportant une jonction de matériaux différents, p.ex. dispositifs à effet Josephson
  • H01L 39/24 - Procédés ou appareils spécialement adaptés à la fabrication ou au traitement des dispositifs couverts par  ou de leurs parties constitutives

65.

ADIABATIC PROGRESSION WITH INTERMEDIATE RE-OPTIMIZATION TO SOLVE HARD VARIATIONAL QUANTUM PROBLEMS IN QUANTUM COMPUTING

      
Numéro de document 03135548
Statut En instance
Date de dépôt 2020-04-06
Date de disponibilité au public 2020-10-15
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Greenberg, Don
  • Pistoia, Marco
  • Chen, Richard
  • Nannicini, Giacomo

Abrégé

A hybrid classical-quantum computing device to execute a quantum circuit corresponding to a variational problem, is configured. The configuring further comprises causing the hybrid classical-quantum computing device to execute the quantum circuit by performing an adiabatic progression operation, wherein the adiabatic progression operation comprises increasing the difficulty of the variational problem from a simplified version of the problem to the variational problem.

Classes IPC  ?

  • G06N 5/00 - Systèmes de calculateurs utilisant des modèles basés sur la connaissance

66.

ADAPTIVE ERROR CORRECTION IN QUANTUM COMPUTING

      
Numéro de document 03135529
Statut En instance
Date de dépôt 2020-03-17
Date de disponibilité au public 2020-10-08
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Gunnels, John
  • Wegman, Mark
  • Kaminsky, David

Abrégé

A method for adaptive error correction in quantum computing includes executing a calibration operation on a set of qubits, the calibration operation determining an initial state of a quantum processor. In an embodiment, the method includes estimating, responsive to determining an initial state of the quantum processor, a runtime duration for a quantum circuit design corresponding to a quantum algorithm, the quantum processor configured to execute the quantum circuit design. In an embodiment, the method includes computing an error scenario for the quantum circuit design. In an embodiment, the method includes selecting, using the error scenario and the initial state of the quantum processor, a quantum error correction approach for the quantum circuit design. In an embodiment, the method includes transforming the quantum algorithm into the quantum circuit design, the quantum circuit design including a set of quantum logic gates.

Classes IPC  ?

  • G06N 10/70 - Correction, détection ou prévention d’erreur quantique, p.ex. codes de surface ou distillation d’état magique

67.

GATE VOLTAGE-TUNABLE ELECTRON SYSTEM INTEGRATED WITH SUPERCONDUCTING RESONATOR FOR QUANTUM COMPUTING DEVICE

      
Numéro de document 03135530
Statut En instance
Date de dépôt 2020-03-18
Date de disponibilité au public 2020-10-08
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Hart, Sean
  • Gambetta, Jay Michael
  • Gumann, Patryk

Abrégé

A superconducting coupling device includes a resonator structure. The resonator structure has a first end configured to be coupled to a first device and a second end configured to be coupled to a second device. The device further includes an electron system coupled to the resonator structure, and a gate positioned proximal to a portion of the electron system. The electron system and the gate are configured to interrupt the resonator structure at one or more predetermined locations forming a switch. The gate is configured to receive a gate voltage and vary an inductance of the electron system based upon the gate voltage. The varying of the inductance induces the resonator structure to vary a strength of coupling between the first device and the second device.

Classes IPC  ?

  • G06N 10/40 - Réalisations ou architectures physiques de processeurs ou de composants quantiques pour la manipulation de qubits, p.ex. couplage ou commande de qubit
  • B82Y 10/00 - Nanotechnologie pour le traitement, le stockage ou la transmission d’informations, p.ex. calcul quantique ou logique à un électron
  • H01L 39/00 - Dispositifs utilisant la supraconductivité ou l'hyperconductivité; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives

68.

TUNABLE SUPERCONDUCTING RESONATOR FOR QUANTUM COMPUTING DEVICES

      
Numéro de document 03135532
Statut En instance
Date de dépôt 2020-03-19
Date de disponibilité au public 2020-10-08
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Hart, Sean
  • Gumann, Patryk

Abrégé

A superconducting coupling device includes a resonator structure. The resonator structure has a first end configured to be coupled to a first device and a second end configured to be coupled to a second device. A gate is positioned proximal to a portion of the resonator structure. The gate is configured to receive a gate voltage and vary a kinetic inductance of the portion of the resonator based upon the gate voltage. The varying of the kinetic inductance induces the resonator structure to vary a strength of coupling between the first superconducting device and the second superconducting device.

Classes IPC  ?

  • G06N 10/40 - Réalisations ou architectures physiques de processeurs ou de composants quantiques pour la manipulation de qubits, p.ex. couplage ou commande de qubit
  • B82Y 10/00 - Nanotechnologie pour le traitement, le stockage ou la transmission d’informations, p.ex. calcul quantique ou logique à un électron
  • H01L 39/12 - Dispositifs utilisant la supraconductivité ou l'hyperconductivité; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives - Détails caractérisés par le matériau

69.

QUANTUM FEATURE KERNEL ALIGNMENT

      
Numéro de document 03135537
Statut En instance
Date de dépôt 2020-03-26
Date de disponibilité au public 2020-10-08
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Gambetta, Jay Michael
  • Glick, Jennifer Ranae
  • Temme, Paul Kristan
  • Gujarati, Tanvi Pradeep

Abrégé

The illustrative embodiments provide a method, system, and computer program product for quantum feature kernel alignment using a hybrid classical-quantum computing system. An embodiment of a method for hybrid classical-quantum decision maker training includes receiving a training data set. In an embodiment, the method includes selecting, by a first processor, a sampling of objects from the training set, each object represented by at least one vector.In an embodiment, the method includes applying, by a quantum processor, a set of quantum feature maps to the selected objects, the set of quantum maps corresponding to a set of quantum kernels. In an embodiment, the method includes evaluating, by a quantum processor, a set of parameters for a quantum feature map circuit corresponding to at least one of the set of quantum feature maps.

Classes IPC  ?

  • G06N 3/08 - Méthodes d'apprentissage
  • G06N 20/10 - Apprentissage automatique utilisant des méthodes à noyaux, p.ex. séparateurs à vaste marge [SVM]
  • G06N 5/00 - Systèmes de calculateurs utilisant des modèles basés sur la connaissance

70.

BINDING SECURE KEYS OF SECURE GUESTS TO A HARDWARE SECURITY MODULE

      
Numéro de document 03132747
Statut En instance
Date de dépôt 2020-02-27
Date de disponibilité au public 2020-09-17
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Buendgen, Reinhard
  • Visegrady, Tamas
  • Franzki, Ingo

Abrégé

A method, computer program product, and a system where a secure interface control configures a hardware security module for exclusive use by a secure guest. The secure interface control ("SC") obtains a configuration request (via a hypervisor) to configure the hardware security module (HSM), from a given guest of guests managed by the hypervisor. The SC determines if the HSM is already configured to a specific guest of the one or more guests, but based on determining that the HSM is not configured to the and is a secure guest the SC forecloses establishing a configuration of the HSM by limiting accesses by guests to the HSM exclusively to the given guest. The SC logs the given guest into the HSM by utilizing a secret of the given guest. The SC obtains, from the HSM, a session code and retains the session code.

Classes IPC  ?

  • G06F 21/44 - Authentification de programme ou de dispositif
  • G06F 21/64 - Protection de l’intégrité des données, p.ex. par sommes de contrôle, certificats ou signatures
  • G06F 21/71 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du calcul ou du traitement de l’information
  • G06F 21/86 - Boîtiers fiables ou inviolables

71.

SECURE INTERFACE CONTROL HIGH-LEVEL INSTRUCTION INTERCEPTION FOR INTERRUPTION ENABLEMENT

      
Numéro de document 03132752
Statut En instance
Date de dépôt 2020-02-28
Date de disponibilité au public 2020-09-17
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Borntraeger, Christian
  • Imbrenda, Claudio
  • Busaba, Fadi
  • Bradbury, Jonathan
  • Heller, Lisa

Abrégé

A method is provided by a secure interface control of a computer that provides a partial instruction interpretation for an instruction which enables an interruption. The secure interface control fetches a program status word or a control register value from a secure guest storage. The secure interface control notifies an untrusted entity of guest interruption mask updates. The untrusted entity is executed on and in communication with hardware of the computer through the secure interface control to support operations of a secure entity executing on the untrusted entity. The secure interface control receives, from the untrusted entity, a request to present a highest priority, enabled guest interruption in response to the notifying of the guest interruption mask updates. The secure interface control moves interruption information into a guest prefix page and injecting the interruption in the secure entity when an injection of the interruption is determined to be valid.

Classes IPC  ?

  • G06F 21/12 - Protection des logiciels exécutables
  • G06F 21/51 - Contrôle des usagers, programmes ou dispositifs de préservation de l’intégrité des plates-formes, p.ex. des processeurs, des micrologiciels ou des systèmes d’exploitation au stade du chargement de l’application, p.ex. en acceptant, en rejetant, en démarrant ou en inhibant un logiciel exécutable en fonction de l’intégrité ou de la fiabilité de la source
  • G06F 21/53 - Contrôle des usagers, programmes ou dispositifs de préservation de l’intégrité des plates-formes, p.ex. des processeurs, des micrologiciels ou des systèmes d’exploitation au stade de l’exécution du programme, p.ex. intégrité de la pile, débordement de tampon ou prévention d'effacement involontaire de données par exécution dans un environnement restreint, p.ex. "boîte à sable" ou machine virtuelle sécurisée
  • G06F 21/57 - Certification ou préservation de plates-formes informatiques fiables, p.ex. démarrages ou arrêts sécurisés, suivis de version, contrôles de logiciel système, mises à jour sécurisées ou évaluation de vulnérabilité
  • G06F 21/62 - Protection de l’accès à des données via une plate-forme, p.ex. par clés ou règles de contrôle de l’accès
  • G06F 21/74 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du calcul ou du traitement de l’information opérant en mode dual ou compartimenté, c. à d. avec au moins un mode sécurisé
  • G06F 9/455 - Dispositions pour exécuter des programmes spécifiques Émulation; Interprétation; Simulation de logiciel, p.ex. virtualisation ou émulation des moteurs d’exécution d’applications ou de systèmes d’exploitation

72.

SECURE INTERFACE CONTROL SECURE STORAGE HARDWARE TAGGING

      
Numéro de document 03132757
Statut En instance
Date de dépôt 2020-03-06
Date de disponibilité au public 2020-09-17
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Heller, Lisa
  • Busaba, Fadi
  • Bradbury, Jonathan

Abrégé

A method is provided. A secure interface control in communication with an untrusted entity perform the method. In this regard, the secure interface control implements an initialization instruction to set donated storage as secure. The implementing of the initialization instruction is responsive to an instruction call issued from the untrusted entity.

Classes IPC  ?

  • G06F 12/14 - Protection contre l'utilisation non autorisée de mémoire

73.

SECURE EXECUTION GUEST OWNER CONTROLS FOR SECURE INTERFACE CONTROL

      
Numéro de document 03132759
Statut En instance
Date de dépôt 2020-02-27
Date de disponibilité au public 2020-09-17
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Buendgen, Reinhard
  • Bradbury, Jonathan

Abrégé

A method, computer program product, and a system where a secure interface control determines functionality of a secure guest based on metadata. The secure interface control ("SC") obtains metadata linked to an image of a secure guest to be started by an owner and managed by the hypervisor, where the metadata comprises control(s) that indicate whether a secure guest generated with the image is permitted to obtain a response to a particular request. The SC intercepts, from the secure guest generated with the image, during runtime, a request. The SC determines, based on the control(s), if the secure guest is permitted to obtain a response to the request. If permitted, the SC commences fulfillment of the request, within the computing system. If not permitted, the SC ignores the request.

Classes IPC  ?

  • G06F 21/53 - Contrôle des usagers, programmes ou dispositifs de préservation de l’intégrité des plates-formes, p.ex. des processeurs, des micrologiciels ou des systèmes d’exploitation au stade de l’exécution du programme, p.ex. intégrité de la pile, débordement de tampon ou prévention d'effacement involontaire de données par exécution dans un environnement restreint, p.ex. "boîte à sable" ou machine virtuelle sécurisée
  • G06F 9/455 - Dispositions pour exécuter des programmes spécifiques Émulation; Interprétation; Simulation de logiciel, p.ex. virtualisation ou émulation des moteurs d’exécution d’applications ou de systèmes d’exploitation

74.

INJECT INTERRUPTS AND EXCEPTIONS INTO SECURE VIRTUAL MACHINE

      
Numéro de document 03132760
Statut En instance
Date de dépôt 2020-02-27
Date de disponibilité au public 2020-09-17
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Imbrenda, Claudio
  • Busaba, Fadi
  • Heller, Lisa
  • Bradbury, Jonathan

Abrégé

According to one or more embodiments of the present invention, a computer implemented method includes initiating, by a non-secure entity that is executing on a host server, a secure entity, the non-secure entity prohibited from directly accessing any data of the secure entity. The method further includes injecting, into the secure entity, an interrupt that is generated by the host server. The injecting includes adding, by the non-secure entity, information about the interrupt into a portion of non-secure storage, which is then associated with the secure entity. The injecting further includes injecting, by a secure interface control of the host server, the interrupt into the secure entity.

Classes IPC  ?

  • G06F 9/455 - Dispositions pour exécuter des programmes spécifiques Émulation; Interprétation; Simulation de logiciel, p.ex. virtualisation ou émulation des moteurs d’exécution d’applications ou de systèmes d’exploitation

75.

SECURE STORAGE ISOLATION

      
Numéro de document 03132781
Statut En instance
Date de dépôt 2020-03-02
Date de disponibilité au public 2020-09-17
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Bradbury, Jonathan
  • Heller, Lisa Cranton
  • Bacher, Utz
  • Busaba, Fadi

Abrégé

An computer-implemented method according to examples includes receiving, by a secure interface control of a computing system, a request by a requestor to access a page in a memory of the computing system. The method further includes, responsive to determining that the requestor is a non-secure requestor and responsive to a secure- storage bit being set, prohibiting access to the page without performing an authorization check. The method further includes, responsive to determining that the requestor is a secure requestor, performing the authorization check.

Classes IPC  ?

  • G06F 9/455 - Dispositions pour exécuter des programmes spécifiques Émulation; Interprétation; Simulation de logiciel, p.ex. virtualisation ou émulation des moteurs d’exécution d’applications ou de systèmes d’exploitation
  • G06F 21/78 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du stockage de données

76.

INCREMENTAL DECRYPTION AND INTEGRITY VERIFICATION OF A SECURE OPERATING SYSTEM IMAGE

      
Numéro de document 03132735
Statut En instance
Date de dépôt 2020-02-17
Date de disponibilité au public 2020-09-17
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Buendgen, Reinhard
  • Borntraeger, Christian
  • Bradbury, Jonathan
  • Busaba, Fadi
  • Heller, Lisa
  • Mihajlovski, Viktor

Abrégé

Secure processing within a computing environment is provided by incrementally decrypting a secure operating system image, including receiving, for a page of the secure operating system image, a page address and a tweak value used during encryption of the page. Processing determines that the tweak value has not previously been used during decryption of another page of the secure operating system image, and decrypts memory page content at the page address using an image encryption key and the tweak value to facilitate obtaining a decrypted secure operating system image. Further, integrity of the secure operating system image is verified, and based on verifying integrity of the secure operating system image, execution of the decrypted secure operating system image is started.

Classes IPC  ?

  • G06F 21/57 - Certification ou préservation de plates-formes informatiques fiables, p.ex. démarrages ou arrêts sécurisés, suivis de version, contrôles de logiciel système, mises à jour sécurisées ou évaluation de vulnérabilité
  • G06F 9/455 - Dispositions pour exécuter des programmes spécifiques Émulation; Interprétation; Simulation de logiciel, p.ex. virtualisation ou émulation des moteurs d’exécution d’applications ou de systèmes d’exploitation

77.

DISPATCH OF A SECURE VIRTUAL MACHINE

      
Numéro de document 03132750
Statut En instance
Date de dépôt 2020-02-28
Date de disponibilité au public 2020-09-17
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Busaba, Fadi
  • Heller, Lisa

Abrégé

According to one or more embodiments of the present invention, a computer implemented method includes receiving, by a hypervisor that is executing on a host server, a request to dispatch a virtual machine. The method further includes, based on a determination that the virtual machine is a secure virtual machine, preventing the hypervisor from directly accessing any data of the secure virtual machine by determining, by a secure interface control of the host server, a security mode of the virtual machine. Based on the security mode being a first mode, the secure interface control loads a virtual machine state from a first state descriptor, which is stored in a non-secure portion of memory. Based on the security mode being a second mode, the secure interface control loads the virtual machine state from a second state descriptor, which is stored in a secure portion of the memory.

Classes IPC  ?

  • G06F 21/12 - Protection des logiciels exécutables
  • G06F 21/51 - Contrôle des usagers, programmes ou dispositifs de préservation de l’intégrité des plates-formes, p.ex. des processeurs, des micrologiciels ou des systèmes d’exploitation au stade du chargement de l’application, p.ex. en acceptant, en rejetant, en démarrant ou en inhibant un logiciel exécutable en fonction de l’intégrité ou de la fiabilité de la source
  • G06F 21/53 - Contrôle des usagers, programmes ou dispositifs de préservation de l’intégrité des plates-formes, p.ex. des processeurs, des micrologiciels ou des systèmes d’exploitation au stade de l’exécution du programme, p.ex. intégrité de la pile, débordement de tampon ou prévention d'effacement involontaire de données par exécution dans un environnement restreint, p.ex. "boîte à sable" ou machine virtuelle sécurisée
  • G06F 21/62 - Protection de l’accès à des données via une plate-forme, p.ex. par clés ou règles de contrôle de l’accès
  • G06F 21/74 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du calcul ou du traitement de l’information opérant en mode dual ou compartimenté, c. à d. avec au moins un mode sécurisé
  • G06F 9/455 - Dispositions pour exécuter des programmes spécifiques Émulation; Interprétation; Simulation de logiciel, p.ex. virtualisation ou émulation des moteurs d’exécution d’applications ou de systèmes d’exploitation

78.

COMMUNICATION INTERFACE OF A SECURE INTERFACE CONTROL

      
Numéro de document 03132753
Statut En instance
Date de dépôt 2020-02-26
Date de disponibilité au public 2020-09-17
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Heller, Lisa
  • Busaba, Fadi
  • Bradbury, Jonathan
  • Borntraeger, Christian
  • Bacher, Utz
  • Buendgen, Reinhard

Abrégé

A method is provided. The method is implemented by a communication interface of a secure interface control executing between the secure interface control of a computer and hardware of the computer/ In this regard, the communication interface receives an instruction and determines whether the instruction is a millicoded instruction. Further, the communication interface enters a millimode comprising enabling the secure interface control to engage millicode of the hardware through the communication interface based on the instruction being the millicoded instruction. The millicode, then, executes the instruction

Classes IPC  ?

  • G06F 21/74 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du calcul ou du traitement de l’information opérant en mode dual ou compartimenté, c. à d. avec au moins un mode sécurisé
  • G06F 9/30 - Dispositions pour exécuter des instructions machines, p.ex. décodage d'instructions

79.

STARTING A SECURE GUEST USING AN INITIAL PROGRAM LOAD MECHANISM

      
Numéro de document 03132756
Statut En instance
Date de dépôt 2020-03-06
Date de disponibilité au public 2020-09-17
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Mihajlovski, Viktor
  • Imbrenda, Claudio

Abrégé

A method for starting a secure guest includes receiving, by a hypervisor that is executing on a host server, a request to dispatch a virtual machine (VM) on the host server. The VM is dispatched on the host server by the hypervisor. The VM includes a reboot instruction. The reboot instruction is triggered by the hypervisor to restart the VM in a secure mode.

Classes IPC  ?

  • G06F 9/455 - Dispositions pour exécuter des programmes spécifiques Émulation; Interprétation; Simulation de logiciel, p.ex. virtualisation ou émulation des moteurs d’exécution d’applications ou de systèmes d’exploitation
  • G06F 21/53 - Contrôle des usagers, programmes ou dispositifs de préservation de l’intégrité des plates-formes, p.ex. des processeurs, des micrologiciels ou des systèmes d’exploitation au stade de l’exécution du programme, p.ex. intégrité de la pile, débordement de tampon ou prévention d'effacement involontaire de données par exécution dans un environnement restreint, p.ex. "boîte à sable" ou machine virtuelle sécurisée
  • G06F 21/62 - Protection de l’accès à des données via une plate-forme, p.ex. par clés ou règles de contrôle de l’accès
  • H04L 9/32 - Dispositions pour les communications secrètes ou protégées comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système

80.

SPILLING TEMPORARY RESULTS FOR ACCOMMODATION OF MEMORY BOUNDARIES

      
Numéro de document 03131257
Statut En instance
Date de dépôt 2020-02-27
Date de disponibilité au public 2020-09-03
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Kurup, Girish Gopala
  • Klein, Matthias
  • Sofia, Anthony Thomas
  • Bradbury, Jonathan
  • Mishra, Ashutosh
  • Jacobi, Christian
  • Bhattacharjee, Deepankar

Abrégé

An aspect includes a system architecture that includes a processing unit, an accelerator, a main source buffer, a main target buffer, and a memory block. The main source buffer stores a first part of a source symbol received from an external source. The main target buffer stores an output symbol received from the accelerator. The memory block includes an overflow source buffer that stores the first part of the source symbol received from the main source buffer. The accelerator fetches the first part of the source symbol stored in the overflow source buffer and a second part of the source symbol stored in the main source buffer, and converts the first and second parts of the source symbol together into the output symbol. The second part of the source symbol includes a part of the source symbol not included in the first part of the source symbol.

Classes IPC  ?

  • H03M 7/40 - Conversion en, ou à partir de codes de longueur variable, p.ex. code Shannon-Fano, code Huffman, code Morse

81.

VECTOR STRING SEARCH INSTRUCTION

      
Numéro de document 03141920
Statut En instance
Date de dépôt 2020-02-11
Date de disponibilité au public 2020-08-20
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Lichtenau, Cedric
  • Bradbury, Jonathan
  • Schwarz, Eric Mark
  • Figuli, Razvan Peter
  • Payer, Stefan

Abrégé

An instruction is provided for performing a vector string search. The instruction to be processed is obtained, with the instruction being defined to be a string search instruction to locate occurrence of a substring within a string. The instruction is processed, with the processing including searching the string specified in one operand of the instruction using the substring specified in another operand of the instruction. Based on the searching locating a first full match of the substring within the string, a full match condition indication is returned with position of the first full match in the string, and based on the searching locating only a partial match of the substring at a termination of the string, a partial match condition indication is returned, with the position of the partial match in the string.

Classes IPC  ?

82.

DIRECTED INTERRUPT FOR MULTILEVEL VIRTUALIZATION

      
Numéro de document 03130164
Statut En instance
Date de dépôt 2020-01-10
Date de disponibilité au public 2020-08-20
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Nerz, Bernd
  • Kraemer, Marco
  • Raisch, Christoph
  • Schmidt, Donald
  • Driever, Peter

Abrégé

The invention relates to a method for providing an interrupt signal to a first guest operating system. A bus attachment device receives an interrupt signal from a bus connected module with an interrupt target ID identifying a processor assigned for use by the guest operating system as a target processor for handling the interrupt signal. The bus attachment device checks whether the target processor is scheduled for usage by the guest operating system. If the target processor is not scheduled for usage, the bus attachment device forwards the interrupt signal using broadcasting and updates a forwarding vector entry stored in a memory section assigned to a second guest operating system hosting the first guest operating system. The update is used for indicating to the first operating system that there is a first interrupt signal addressed to the interrupt target ID to be handled.

Classes IPC  ?

  • G06F 9/455 - Dispositions pour exécuter des programmes spécifiques Émulation; Interprétation; Simulation de logiciel, p.ex. virtualisation ou émulation des moteurs d’exécution d’applications ou de systèmes d’exploitation
  • G06F 9/48 - Lancement de programmes; Commutation de programmes, p.ex. par interruption

83.

INCREASING PROCESSING CAPACITY OF PARTITIONS FOR AN ABNORMAL EVENT

      
Numéro de document 03128930
Statut En instance
Date de dépôt 2020-01-28
Date de disponibilité au public 2020-08-13
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s) Sutton, Peter Grimm

Abrégé

A system and related method provides within a data processing system (DPS), a first set of computing resources comprising a set of processor units that comprises a first core in an active state, and a second core that is initially in an inactive state. The processor allocates, for a partition that is hosted on the DPS, the first set of computing resources. The partition is operated using the first core before the second core has been activated. A resource manager determines whether to increase processing capacity based on an abnormal event. The processor then activates the second core from the inactive state to the active state. The partition is then operated using both the first and second (activated). In response to a predefined criterion, the second core is deactivated from the active state to the inactive state.

Classes IPC  ?

  • G06F 9/50 - Allocation de ressources, p.ex. de l'unité centrale de traitement [UCT]
  • G06F 1/3287 - Gestion de l’alimentation, c. à d. passage en mode d’économie d’énergie amorcé par événements Économie d’énergie caractérisée par l'action entreprise par la mise hors tension d’une unité fonctionnelle individuelle dans un ordinateur
  • G06F 9/455 - Dispositions pour exécuter des programmes spécifiques Émulation; Interprétation; Simulation de logiciel, p.ex. virtualisation ou émulation des moteurs d’exécution d’applications ou de systèmes d’exploitation

84.

HANDLING AN INPUT/OUTPUT STORE INSTRUCTION

      
Numéro de document 03127840
Statut En instance
Date de dépôt 2020-01-14
Date de disponibilité au public 2020-08-06
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Raisch, Christoph
  • Kraemer, Marco
  • Lehnert, Frank
  • Klein, Matthias
  • Bradbury, Jonathan
  • Jacobi, Christian
  • Belmar, Brenton
  • Driever, Peter

Abrégé

A data processing system (210) and a method for handling an input/output store instruction (30), comprising a system nest (18) communicatively coupled to at least one input/output bus (22) by an input/output bus controller (20). The data processing system (210) further comprises at least a data processing unit (216) comprising a core (12), a system firmware (10) and an asynchronous core-nest interface (14). The data processing unit (216) is communicatively coupled to the system nest (18) via an aggregation buffer (16). The system nest (18) is configured to asynchronously load from and/or store data to at least one external device (214) which is communicatively coupled to the input/output bus (22). The data processing unit (216) is configured to complete the input/output store instruction (30) before an execution of the input/output store instruction (30) in the system nest (18) is completed. The asynchronous core-nest interface (14) comprises an input/output status array (44) with multiple input/output status buffers (24).

Classes IPC  ?

  • G06F 9/30 - Dispositions pour exécuter des instructions machines, p.ex. décodage d'instructions
  • G06F 13/20 - Traitement de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie

85.

HANDLING AN INPUT/OUTPUT STORE INSTRUCTION

      
Numéro de document 03127852
Statut En instance
Date de dépôt 2020-01-14
Date de disponibilité au public 2020-08-06
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Raisch, Christoph
  • Kraemer, Marco
  • Lehnert, Frank
  • Klein, Matthias
  • Bradbury, Jonathan
  • Jacobi, Christian
  • Belmar, Brenton
  • Driever, Peter

Abrégé

A data processing system (210) and a method for handling an input/output store instruction (30), comprising a system nest (18) communicatively coupled to at least one input/output bus (22) by an input/output bus controller (20). The data processing system (210) further comprises at least a data processing unit (216) comprising a core (12), a system firmware (10) and an asynchronous core-nest interface (14). The data processing unit (216) is communicatively coupled to the system nest (18) via an aggregation buffer (16). The system nest (18) is configured to asynchronously load from and/or store data to an external device (214) which is communicatively coupled to the input/output bus (22). The data processing unit (216) is configured to complete the input/output store instruction (30) before an execution of the input/output store instruction (30) in the system nest (18) is completed.

Classes IPC  ?

  • G06F 9/30 - Dispositions pour exécuter des instructions machines, p.ex. décodage d'instructions
  • G06F 13/00 - Interconnexion ou transfert d'information ou d'autres signaux entre mémoires, dispositifs d'entrée/sortie ou unités de traitement
  • G06F 13/20 - Traitement de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie

86.

COMPRESSION/DECOMPRESSION INSTRUCTION SPECIFYING A HISTORY BUFFER TO BE USED IN THE COMPRESSION/DECOMPRESSION OF DATA

      
Numéro de document 03127864
Statut En instance
Date de dépôt 2020-01-23
Date de disponibilité au public 2020-08-06
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Giamei, Bruce Conrad
  • Sofia, Anthony Thomas
  • Klein, Matthias
  • Weishaupt, Simon
  • Farrell, Mark
  • Slegel, Timothy
  • Mishra, Ashutosh
  • Jacobi, Christian

Abrégé

An instruction to perform a function of a plurality of functions is obtained. The instruction is a single architected instruction of an instruction set architecture that complies to an industry standard for compression. The instruction is executed, and the executing includes performing the function specified by the instruction. The performing includes, based on the function being a compression function or a decompression function, transforming state of input data between an uncompressed form of the input data and a compressed form of the input data to provide a transformed state of data accessing. During performing the function, history relating to the function is accessed. The history is to be used in transforming the state of input data between the uncompressed form and the compressed form.

Classes IPC  ?

  • G06F 9/30 - Dispositions pour exécuter des instructions machines, p.ex. décodage d'instructions

87.

GENERAL-PURPOSE PROCESSOR INSTRUCTION TO PERFORM COMPRESSION/DECOMPRESSION OPERATIONS

      
Numéro de document 03127849
Statut En instance
Date de dépôt 2020-01-23
Date de disponibilité au public 2020-08-06
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Giamei, Bruce Conrad
  • Klein, Matthias
  • Slegel, Timothy
  • Farrell, Mark
  • Sofia, Anthony Thomas
  • Weishaupt, Simon
  • Mishra, Ashutosh

Abrégé

A DEFLATE Conversion Call general-purpose processor instruction. An instruction is obtained by a general- purpose processor of the computing environment. The instruction is a single architected instruction of an instruction set architecture that complies to an industry standard for compression. The instruction is executed, and the executing includes transforming, based on a function to be performedby the instruction being a compression functionor a decompression function, state of input data between an uncompressed form of the input data and a compressed form of the input data to provide a transformed state of data. The transformed state of the data is provided as output to be used in performing a task.

Classes IPC  ?

  • G06F 9/30 - Dispositions pour exécuter des instructions machines, p.ex. décodage d'instructions

88.

RECONCILIATION BETWEEN SIMULATED DATA AND SPEECH RECOGNITION OUTPUT USING SEQUENCE-TO-SEQUENCE MAPPING

      
Numéro de document 03119529
Statut En instance
Date de dépôt 2019-12-06
Date de disponibilité au public 2020-06-18
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Arel, Itamar
  • Looks, Joshua Benjamin
  • Ziaei, Ali
  • Lefkowitz, Michael

Abrégé

A synthetic training data item comprising a first sequence of symbols that represent a synthetic sentence output by a simulator is received. The synthetic training data item is processed using a machine learning model, which outputs a second sequence of symbols that represent the synthetic sentence. The synthetic training data item is modified by replacing the first sequence of symbols with the second sequence of symbols. A statistically significant mismatch exists between the first sequence of symbols and a third sequence of symbols that would be output by an acoustic model that processes a set of acoustic features that represent an utterance of the synthetic sentence, and no statistically significant mismatch exists between the second sequence of symbols and the third sequence of symbols. The modified synthetic training data item may be used to train a second machine learning model that processes data output by the acoustic model.

Classes IPC  ?

  • G10L 13/02 - Procédés d'élaboration de parole synthétique; Synthétiseurs de parole
  • G10L 15/183 - Classement ou recherche de la parole utilisant une modélisation du langage naturel selon les contextes, p.ex. modèles de langage
  • G10L 15/197 - Grammaires probabilistes, p.ex. n-grammes de mots
  • G10L 25/69 - Techniques d'analyses de la parole ou de la voix qui ne se limitent pas à un seul des groupes spécialement adaptées pour un usage particulier pour l’évaluation de signaux de voix synthétiques ou décodés
  • G10L 13/08 - Analyse de texte ou génération de paramètres pour la synthèse de la parole à partir de texte, p.ex. conversion graphème-phonème, génération de prosodie ou détermination de l'intonation ou de l'accent tonique
  • G10L 15/02 - Extraction de caractéristiques pour la reconnaissance de la parole; Sélection d'unités de reconnaissance 
  • G10L 15/06 - Création de gabarits de référence; Entraînement des systèmes de reconnaissance de la parole, p.ex. adaptation aux caractéristiques de la voix du locuteur
  • G10L 15/08 - Classement ou recherche de la parole
  • G10L 15/14 - Classement ou recherche de la parole utilisant des modèles statistiques, p.ex. des modèles de Markov cachés [HMM]
  • G10L 15/24 - Reconnaissance de la parole utilisant des caractéristiques non acoustiques
  • G10L 21/06 - Transformation de la parole en une représentation non audible, p.ex. visualisation de la parole ou traitement de la parole pour les aides tactiles

89.

SORT AND MERGE INSTRUCTION FOR A GENERAL-PURPOSE PROCESSOR

      
Numéro de document 03118173
Statut En instance
Date de dépôt 2019-11-05
Date de disponibilité au public 2020-05-14
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Giamei, Bruce Conrad
  • Recktenwald, Martin
  • Schmidt, Donald William
  • Slegel, Timothy
  • Puranik, Aditya Nitin
  • Farrell, Mark
  • Jacobi, Christian
  • Bradbury, Jonathan
  • Zoellin, Christian Gerhard

Abrégé

A Sort Lists instruction is provided to perform a sort and/or a merge operation. The instruction is an architected machine instruction of an instruction set architecture and is executed by a general-purpose processor of the computing environment. The executing includes sorting a plurality of input lists to obtain one or more sorted output lists, which are output.

Classes IPC  ?

  • G06F 9/30 - Dispositions pour exécuter des instructions machines, p.ex. décodage d'instructions

90.

SAVING AND RESTORING MACHINE STATE BETWEEN MULTIPLE EXECUTIONS OF AN INSTRUCTION

      
Numéro de document 03118174
Statut En instance
Date de dépôt 2019-11-05
Date de disponibilité au public 2020-05-14
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Giamei, Bruce Conrad
  • Recktenwald, Martin
  • Schmidt, Donald William
  • Slegel, Timothy
  • Puranik, Aditya Nitin
  • Farrell, Mark
  • Jacobi, Christian
  • Bradbury, Jonathan
  • Zoellin, Christian Gerhard

Abrégé

Saving and restoring machine state between multiple executions of an instruction. A determination is made that processing of an operation of an instruction executing on a processor has been interrupted prior to completion. Based on determining that the processing of the operation has been interrupted, current metadata of the processor is extracted. The metadata is stored in a location associated with the instruction and used to re-execute the instruction to resume forward processing of the instruction from where it was interrupted.

Classes IPC  ?

  • G06F 9/30 - Dispositions pour exécuter des instructions machines, p.ex. décodage d'instructions
  • G06F 9/38 - Exécution simultanée d'instructions

91.

CONVERSATIONAL AGENT PIPELINE TRAINED ON SYNTHETIC DATA

      
Numéro de document 03114572
Statut En instance
Date de dépôt 2019-09-24
Date de disponibilité au public 2020-04-02
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Arel, Itamar
  • Looks, Joshua Benjamin
  • Ziaei, Ali
  • Lefkowitz, Michael

Abrégé

In one embodiment synthetic training data items are generated, each comprising a) a textual representation of a synthetic sentence and b) one or more transcodes of the synthetic sentence comprising one or more actions and one or more entities associated with the one or more actions. For each synthetic training data item, the textual representation of the synthetic sentence is converted into a sequence of phonemes that represent the synthetic sentence. A first machine learning model is then trained as a transcoder that determines transcodes comprising actions and associated entities from sequences of phonemes, wherein the training is performed using a first training dataset comprising the plurality of synthetic training data items that comprise a) sequences phonemes that represent synthetic sentences and b) transcodes of the synthetic sentences. The transcoder may be used in a conversational agent.

Classes IPC  ?

  • G10L 15/06 - Création de gabarits de référence; Entraînement des systèmes de reconnaissance de la parole, p.ex. adaptation aux caractéristiques de la voix du locuteur
  • G06N 99/00 - Matière non prévue dans les autres groupes de la présente sous-classe
  • G10L 15/193 - Grammaires formelles, p.ex. automates à états finis, grammaires hors contexte ou réseaux de mots
  • G10L 15/02 - Extraction de caractéristiques pour la reconnaissance de la parole; Sélection d'unités de reconnaissance 
  • G10L 15/18 - Classement ou recherche de la parole utilisant une modélisation du langage naturel

92.

STORAGE-AGNOSTIC APPLICATION-CONSISTENT SNAPSHOT AND REPLICATION

      
Numéro de document 03058456
Statut En instance
Date de dépôt 2018-03-30
Date de disponibilité au public 2018-10-04
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s) Govindan, Ranjith

Abrégé

Storage-agnostic application-consistent snapshot and replication is provided. In various embodiments, a snapshot command is issued to a volume snapshot service. The volume snapshot service is thereby directed to place one or more applications in backup mode. A list of LUNs to be snapshotted is retrieved from the volume snapshot service. A snapshot command is issued to one or more storage system underlying the LUNs on the list. Upon completion of the snapshot command to the one or more storage systems, control is returned to the volume snapshot service.

Classes IPC  ?

  • G06F 11/14 - Détection ou correction d'erreur dans les données par redondance dans les opérations, p.ex. en utilisant différentes séquences d'opérations aboutissant au même résultat
  • G06F 11/00 - Détection d'erreurs; Correction d'erreurs; Contrôle de fonctionnement
  • G06F 12/16 - Protection contre la perte de contenus de mémoire

93.

GEOMAGNETIC STORM WARNING

      
Numéro de document 02994716
Statut En instance
Date de dépôt 2018-02-12
Date de disponibilité au public 2018-08-15
Propriétaire
  • INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
  • HYDRO-QUEBEC (Canada)
Inventeur(s)
  • Basu, Chumki
  • Guillon, Sebastien
  • Kamwa, Innocent
  • Padmanaban, Manikandan
  • Cauchon, Luc

Abrégé

A method of receiving a substorm activity data log from one or more remote sensors, where substorm activity is due to solar activity. The method also includes receiving a harmonic distortion data stream from one or more remote observatories monitoring disturbances on a power grid, where the distortion is due to geomagnetically induced currents. The method also includes applying a mathematical model to the harmonic distortion data stream to create a derived harmonic distortion data log, and comparing phase-to-phase similarity of the three phases from the derived harmonic distortion data log. The method also includes predicting future adverse events due to geomagnetically-induced currents on the power grid based at least in part on the comparison and the substorm activity data log, and creating a warning based on the prediction.

Classes IPC  ?

  • G01R 29/16 - Mesure de l'asymétrie des réseaux polyphasés
  • G01W 1/00 - Météorologie
  • H02J 3/26 - Dispositions pour l'élimination ou la réduction des asymétries dans les réseaux polyphasés

94.

SAVING/RESTORING GUARDED STORAGE CONTROLS IN A VIRTUALIZED ENVIRONMENT

      
Numéro de document 03037277
Statut En instance
Date de dépôt 2018-01-12
Date de disponibilité au public 2018-07-26
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Greiner, Dan
  • Slegel, Timothy
  • Jacobi, Christian
  • Saporito, Anthony
  • Shum, Chung-Lung
  • Osisek, Damian

Abrégé

A guarded storage facility sets up a boundary indicating a range of addresses to be guarded or protected. When a program attempts to access an address in a guarded section defined by the boundary, a guarded storage event occurs. Use of this facility facilitates performance of certain tasks within a computing environment, including storage reclamation.

Classes IPC  ?

  • G06F 12/02 - Adressage ou affectation; Réadressage
  • G06F 9/455 - Dispositions pour exécuter des programmes spécifiques Émulation; Interprétation; Simulation de logiciel, p.ex. virtualisation ou émulation des moteurs d’exécution d’applications ou de systèmes d’exploitation

95.

CONDITIONAL BRANCH TO AN INDIRECTLY SPECIFIED LOCATION

      
Numéro de document 03037445
Statut En instance
Date de dépôt 2017-11-09
Date de disponibilité au public 2018-07-26
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Greiner, Dan
  • Saporito, Anthony
  • Shum, Chung-Lung
  • Slegel, Timothy
  • Jacobi, Christian

Abrégé

An instruction to perform a conditional branch to an indirectly specified location is executed. A branch address is obtained from a location in memory, the location in memory designated by the instruction. A determination is made,based on a condition code of another instruction, whether a branch is to occur, and a branch to the branch address is performed, based on determining the branch is to occur.

Classes IPC  ?

  • G06F 9/30 - Dispositions pour exécuter des instructions machines, p.ex. décodage d'instructions

96.

RUN-TIME INSTRUMENTATION OF GUARDED STORAGE EVENT PROCESSING

      
Numéro de document 03037266
Statut En instance
Date de dépôt 2018-01-12
Date de disponibilité au public 2018-07-26
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Greiner, Dan
  • Slegel, Timothy
  • Jacobi, Christian
  • Saporito, Anthony
  • Shum, Chung-Lung

Abrégé

A guarded storage facility sets up a boundary indicating a range of addresses to be guarded or protected. When a program attempts to access an address in a guarded section defined by the boundary, a guarded storage event occurs. Use of this facility facilitates performance of certain tasks within a computing environment, including storage reclamation.

Classes IPC  ?

  • G06F 12/02 - Adressage ou affectation; Réadressage
  • G06F 12/0855 - Accès de mémoire cache en chevauchement, p.ex. pipeline
  • G06F 9/30 - Dispositions pour exécuter des instructions machines, p.ex. décodage d'instructions
  • G06F 9/46 - Dispositions pour la multiprogrammation
  • G06F 11/07 - Réaction à l'apparition d'un défaut, p.ex. tolérance de certains défauts
  • G06F 11/36 - Prévention d'erreurs en effectuant des tests ou par débogage de logiciel
  • G06F 12/14 - Protection contre l'utilisation non autorisée de mémoire

97.

TIME-SLICE-INSTRUMENTATION FACILITY

      
Numéro de document 03037292
Statut En instance
Date de dépôt 2017-12-15
Date de disponibilité au public 2018-07-19
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Giamei, Bruce Conrad
  • Schmidt, Donald William
  • Jacobi, Christian
  • Saporito, Anthony
  • Rosa, Daniel

Abrégé

A facility is provided for collecting time-slice-instrumentation information during processing unit execution. The facility counts, at least in part, occurrence of a specified processing unit event during a time-slice of processing unit execution. The counted events occurring during a first interval of execution and a second interval of execution of the time-slice are retained. The first interval of execution is earlier in the time-slice than the second interval of execution, and the counted events facilitate adjusting performance of the processing unit. In an embodiment, the time-slice is a contiguous period of time of processing unit execution, and the specified processing unit event includes a cache event. The processing unit may interleave processing of multiple different units of work across multiple contiguous time-slices, and during a single time-slice, a single unit of work of the multiple different units of work is processed by the processing unit.

Classes IPC  ?

  • G06F 9/48 - Lancement de programmes; Commutation de programmes, p.ex. par interruption
  • G06F 9/50 - Allocation de ressources, p.ex. de l'unité centrale de traitement [UCT]

98.

TEMPORARILY SUPPRESSING PROCESSING OF A RESTRAINED STORAGE OPERAND REQUEST

      
Numéro de document 03037265
Statut En instance
Date de dépôt 2018-01-09
Date de disponibilité au public 2018-07-19
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Giamei, Bruce Conrad
  • Jacobi, Christian
  • Shum, Chung-Lung
  • Schmidt, Donald William
  • Rosa, Daniel
  • Saporito, Anthony

Abrégé

Processing of a storage operand request identified as restrained is selectively, temporarily suppressed. The processing includes determining whether a storage operand request to a common storage location shared by multiple processing units of a computing environment is restrained, and based on determining that the storage operand request is restrained, then temporarily suppressing requesting access to the common storage location pursuant to the storage operand request. The processing unit performing the processing may proceed with processing of the restrained storage operand request, without performing the suppressing, where the processing can be accomplished using cache private to the processing unit. Otherwise the suppressing may continue until an instruction, or operation of an instruction, associated with the storage operand request is next to complete.

Classes IPC  ?

  • G06F 9/30 - Dispositions pour exécuter des instructions machines, p.ex. décodage d'instructions

99.

FACILITY FOR EXTENDING EXCLUSIVE HOLD OF A CACHE LINE IN PRIVATE CACHE

      
Numéro de document 03037433
Statut En instance
Date de dépôt 2018-01-03
Date de disponibilité au public 2018-07-19
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Giamei, Bruce Conrad
  • Jacobi, Christian
  • Shum, Chung-Lung
  • Schmidt, Donald William
  • Rosa, Daniel
  • Saporito, Anthony

Abrégé

A computing environment facility is provided to extend a hold of a cache line in private (or local) cache exclusively after processing a storage operand request. The facility includes determining whether a storage operand request to a storage location shared by multiple processing units of the computing environment is designated hold. In addition, a determination is made whether a state of the corresponding cache line in private cache used for processing the storage operand request is owned exclusively. Based on determining that the storage operand request is designated hold, and that the state of the corresponding cache line in private cache used for processing the storage operand request is owned exclusively, continuing to hold the corresponding cache line in the private cache exclusively after completing processing of the storage operand request. The continuing to hold may include initiating a counter to facilitate the continuing hold for a desired, set interval.

Classes IPC  ?

  • G06F 12/0815 - Protocoles de cohérence de mémoire cache
  • G06F 12/084 - Systèmes de mémoire cache multi-utilisateurs, multiprocesseurs ou multitraitement avec mémoire cache partagée
  • G06F 9/52 - Synchronisation de programmes; Exclusion mutuelle, p.ex. au moyen de sémaphores

100.

CIPHER MESSAGE WITH AUTHENTICATION INSTRUCTION

      
Numéro de document 03037231
Statut En instance
Date de dépôt 2017-10-02
Date de disponibilité au public 2018-04-19
Propriétaire INTERNATIONAL BUSINESS MACHINES CORPORATION (USA)
Inventeur(s)
  • Greiner, Dan
  • Slegel, Timothy
  • Zoellin, Christian
  • Jacobi, Christian
  • Paprotski, Volodymyr
  • Visegrady, Tamas
  • Buendgen, Reinhard Theodor
  • Bradbury, Jonathan
  • Puranik, Aditya Nitin

Abrégé

An instruction to perform ciphering and authentication is executed. The executing includes ciphering one set of data provided by the instruction to obtain ciphered data and placing the ciphered data in a designated location. It further includes authenticating an additional set of data provided by the instruction, in which the authenticating generates at least a part of a message authentication tag. The at least a part of the message authentication tag is stored in a selected location.

Classes IPC  ?

  • H04L 9/06 - Dispositions pour les communications secrètes ou protégées l'appareil de chiffrement utilisant des registres à décalage ou des mémoires pour le codage par blocs, p.ex. système DES
  • H04L 9/32 - Dispositions pour les communications secrètes ou protégées comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
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