DRIVE CIRCUIT
Registre | Brevet WIPO |
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Numéro d'application | JP2020028853 |
Numéro de publication | 2021/029218 |
Statut | Délivré - en vigueur |
Date de dépôt | 2020-07-28 |
Date de publication | 2021-02-18 |
Propriétaire | OMRON CORPORATION (Japon) |
Inventeur(s) |
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Abrégé
A drive circuit (1) is provided with: a GaN-FET (FET#1) having a source (S) that is connected to an anode of an LD (31) and a drain (D) that is connected to a power source (25) of the LD (31); a gate drive circuit (11) with which an output port (11o) and a negative-side voltage port (11n) are connected, respectively, to a gate (G) and the source (S) of the GaN-FET (FET#1), an input voltage to a positive-side voltage port (11p) being outputted from the output port (11o) during inputting of a signal of a predetermined level; a capacitor (13) that is arranged between the positive-side voltage port (11p) and a negative-side voltage port (11n) of the gate drive circuit (11); a diode (15) that is inserted, in an orientation for shutting off a current that flows from the positive-side voltage port (11p) to a VDD power source for outputting a voltage less than a Vgs breakdown voltage of the GaN-FET (FET#1), into a power source line connecting the positive-side voltage port (11p) of the gate drive circuit (11) and the VDD power source; and a semiconductor switch (FET#2) that is arranged between the source (S) of the GaN-FET (FET#1) and ground.Classes IPC ?
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