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2023
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Invention
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Clock tree routing in a chip stack.
Examples described herein generally relate to clock tree rou... |
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Invention
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Multiple partitions in a data processing array.
An apparatus includes a data processing array ha... |
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Invention
|
Systems and methods to transport memory mapped traffic amongst integrated circuit devices. Embodi... |
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Invention
|
Reconfigurable neural engine with extensible instruction set architecture. An integrated circuit ... |
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Invention
|
Method and apparatus for memory management in a video processing system. An integrated circuit (I... |
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Invention
|
Multi-tenant aware data processing units. Embodiments herein describe creating tag bindings that ... |
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Invention
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Host endpoint adaptive compute composability. Embodiments herein describe a processor system that... |
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Invention
|
Adaptive integrated programmable data processing unit. An integrated circuit device includes mult... |
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Invention
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Distributed configuration of programmable devices. Embodiments herein describe a distributed conf... |
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Invention
|
Dtc nonlinearity correction. Embodiments herein describe correcting nonlinearity in a Digital-to-... |
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2022
|
Invention
|
Dpll timing normalization. Embodiments herein describe normalizing an output of a TDC in a DPLL t... |
|
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Invention
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Low power driver scheme for on-chip and interposer based data transmission.
Signal routing and E... |
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Invention
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Switching between redundant and non-redundant modes of software execution.
Executing critical an... |
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Invention
|
Multiplier block for block floating point and floating point values.
A mode control circuit oper... |
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Invention
|
Noc buffer management for virtual channels.
Embodiments herein describe a NoC where its internal... |
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Invention
|
Pim cancellation architecture.
Embodiments herein describe a PIM correction circuit. In a base s... |
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Invention
|
Satisfying circuit design constraints using a combination of machine learning models.
Multiple c... |
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Invention
|
Decoupling capacitor parameter determination for a power distribution network.
A circuit analysi... |
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Invention
|
Integrated circuit transaction redundancy.
Techniques to provide transaction redundancy in an IC... |
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Invention
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Yield recovery scheme for memory.
A yield recovery scheme for configuration memory of an IC devi... |
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Invention
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Implementing data flows of an application across a memory hierarchy of a data processing array.
... |
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Invention
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Instruction generation and programming model for a data processing array and microcontroller.
In... |
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Invention
|
Chip package with integrated embedded off-die inductors.
A chip package and method for fabricati... |
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Invention
|
Fractional logarithmic number system adder.
An adder for fractional logarithmic number system (F... |
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Invention
|
Host endpoint adaptive compute composability.
Embodiments herein describe a processor system tha... |
|
|
Invention
|
Softmax and log softmax method and system.
Circuits and methods for determining a maximum bias f... |
|
|
Invention
|
Adaptive integrated programmable data processing unit.
An integrated circuit device includes mul... |
|
|
Invention
|
Multi-tenant aware data processing units.
Embodiments herein describe creating tag bindings that... |
|
|
Invention
|
Systems and methods to extract beamforming parameters at a radio unit (ru) of a radio access netw... |
|
|
Invention
|
Chip package with core embedded integrated devices.
A chip package and methods for fabricating t... |
|
|
Invention
|
Buffer circuitry having improved bandwidth and return loss.
An electronic system includes a buff... |
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|
Invention
|
Instruction set architecture for data processing array control.
Controlling a data processing (D... |
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Invention
|
Register integrity check in configurable devices.
Embodiments herein describe integrity check te... |
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|
Invention
|
Latency balancing of paths in multi-processor computing architecture designs for deadlock avoidan... |
|
|
Invention
|
Connectivity layer in 3d devices.
Embodiments herein describe a 3D stack of dies (e.g., an activ... |
|
|
Invention
|
Systems and methods to transport memory mapped traffic amongst integrated circuit devices.
Embod... |
|
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Invention
|
Method for mitigating memory access conflicts in a multi-core graph compiler.
A multi-core archi... |
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Invention
|
Method for mitigating warpage on stacked wafers.
Methods for mitigating warpage on stacked wafer... |
|
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Invention
|
Reconfigurable neural engine with extensible instruction set architecture.
An integrated circuit... |
|
|
Invention
|
Wideband digital step attenuator and buffer circuitry for a receiver system.
Attenuation circuit... |
|
|
Invention
|
Lock and buffer scheduling in multi-core architectures.
Application code is compiled to generate... |
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|
Invention
|
Memory controller with a preprocessor.
A state-of-the-art memory controller and methods for usin... |
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G/S
|
Semiconductor memory; flexible memory block for semiconductor devices |
|
2021
|
Invention
|
Memory self-refresh re-entry state. Examples describe memory refresh operations for memory subsys... |
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|
Invention
|
Block design containers for circuit design. Circuit design development using block design contain... |
|
|
Invention
|
Acceleration-ready program development and deployment for computer systems and hardware accelerat... |
|
|
Invention
|
Integrated circuit package with voltage droop mitigation. A semiconductor device system comprises... |
|
|
Invention
|
Forming and/or configuring stacked dies. Examples described herein generally relate to forming an... |
|
|
Invention
|
Polyphase filter control scheme for fractional resampler systems. Embodiments herein describe a h... |
|
|
Invention
|
Flexible data-driven software control of reconfigurable platforms. Control of a reconfigurable pl... |
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2020
|
Invention
|
Error aware module redundancy for machine learning. Examples herein propose operating redundant M... |
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|
G/S
|
System on module, namely, integrated board-level circuits that integrate a system function in a s... |
|
|
G/S
|
System on module, namely, a board-level circuit that
integrates a system function in a single mo... |
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2019
|
G/S
|
Downloadable computer software platform for the design, programming and operation of integrated c... |
|
|
G/S
|
Downloadable computer software platform for the design,
programming and operation of integrated ... |
|
|
G/S
|
Integrated circuits and semiconductors; computer accelerator
boards; computer accelerator cards;... |
|
|
G/S
|
Integrated circuits; integrated circuits in the nature of
integrated multi-core heterogeneous co... |
|
2018
|
G/S
|
Integrated circuits and semiconductors; computer accelerator boards; computer accelerator cards; ... |
|
|
G/S
|
Integrated circuits; integrated circuits in the nature of integrated multi-core heterogeneous com... |
|
|
G/S
|
Computer accelerator boards; computer accelerator cards; computing memory modules; computer add-i... |
|
2017
|
G/S
|
Computer software for implementing a network protocol stack, not for use in testing website funct... |
|
|
G/S
|
Cards with integrated circuits; Computer network adapters; Computer network interface devices; Et... |
|
|
G/S
|
Computer software and hardware for monitoring and securing network data, enable multiple services... |
|
|
G/S
|
Computer hardware, wide-area computer networks hardware, peer-to-peer computer networks hardware,... |
|
|
G/S
|
Computer software for providing active protection for network servers and network adapters using ... |
|
2015
|
G/S
|
Semiconductors; integrated circuits; programmable logic integrated circuits; field programmable g... |
|
|
G/S
|
Technical consultation in the field of engineering of semiconductors, integrated circuits, progra... |
|
|
G/S
|
Computer software for design, programming, and operation of integrated circuits |
|
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G/S
|
Computer software for design, programming, and operation of integrated circuits. |
|
|
G/S
|
Computer software for design, programming, and operation of
integrated circuits. |
|
2012
|
G/S
|
Computer software systems for packet recordation or storage, time-stamping, time synchronization,... |
|
2011
|
G/S
|
Computer hardware, namely, integrated circuits; integrated circuit, namely, field programmable ga... |
|
|
G/S
|
Computer hardware, namely, integrated circuits; integrated
circuit, namely, field programmable g... |
|
|
G/S
|
Computer software for design, programming, and operation of programmable gate arrays. |
|
|
G/S
|
Integrated circuits, namely, field programmable gate arrays;
computer software for design, progr... |
|
2010
|
G/S
|
Computer software for implementing network communications, computer software used to accelerate n... |
|
|
G/S
|
Computer software; computer software which implements a network protocol stack. |
|
|
G/S
|
Integrated circuits, namely field programmable gate arrays; computer software for design, program... |
|
|
G/S
|
Computer software for design, programming, and operation of programmable gate arrays |
|
|
G/S
|
Integrated circuits, namely, field programmable gate arrays [ ; computer software for design, pro... |
|
|
G/S
|
Integrated circuits, namely field-programmable gate arrays. |
|
|
G/S
|
Integrated circuits, namely field programmable gate arrays;
computer software for design, progra... |
|
|
G/S
|
Integrated circuits; field programmable gate arrays; computer software for the design, programmin... |
|
|
G/S
|
Integrated circuits, namely, field programmable gate arrays |
|
|
G/S
|
Integrated circuits; field programmable gate arrays;
computer software for the design, programmi... |
|
|
G/S
|
Integrated circuits; Integrated circuits in the nature of field programmable gate arrays |
|
2009
|
G/S
|
Data processing equipment and computers; computer hardware and firmware; computer software; compu... |
|
2007
|
G/S
|
Computer hardware, namely, integrated circuits, semiconductors, computer cables, printed circuit ... |
