Sandisk Technologies LLC

United States of America

 
Total IP 5,692
Total IP Rank # 178
IP Activity Score 4/5.0    2,624
IP Activity Rank # 245
Parent Entity SanDisk Corporation

Patents

Trademarks

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Last Patent 2024 - Semiconductor device having edge...
First Patent 1988 - Highly compact eprom and flash e...

Latest Inventions, Goods, Services

2023 Invention Three-dimensional memory device with backside support pillar structures and methods of forming th...
Invention Persistent memory management. Apparatuses, systems, methods, and computer program products are d...
Invention Transistor circuits including fringeless transistors and method of making the same. A lateral ex...
Invention Loop dependent word line ramp start time for program verify of multi-level nand memory. To reduce...
Invention Word line dependent pass voltage ramp rate to improve performance of nand memory. To reduce spike...
Invention Nand memory with different pass voltage ramp rates for binary and multi-state memory. To reduce s...
Invention Non-volatile memory with tier-wise ramp down after program-verify. Memory cells are arranged as N...
Invention Nand string read voltage adjustment. An apparatus includes a control circuit configured to connec...
Invention Adaptive gidl voltage for erasing non-volatile memory. An apparatus is provided that includes a b...
2022 Invention Ppa improvement for voltage mode driver and on-die termination (odt). Systems and methods for im...
Invention High density semiconductor device including integrated controller, logic circuit and memory dies....
Invention Apparatus and methods for bonding pad redistribution layers in integrated circuits. An apparatus...
Invention Semiconductor device having edge seal and method of making thereof without metal hard mask arcing...
Invention Three-dimensional memory device and method of making thereof using selective metal nitride deposi...
Invention Nand fast cyclic redundancy check. The present disclosure relates generally to a method of detec...
Invention End point detection method and apparatus for anisotropic etching using variable etch gas flow. A...
Invention Three-dimensional memory device containing a pillar contact between channel and source and method...
Invention Zq calibration circuit and method for memory interfaces. Systems and methods disclosed herein pr...
Invention Nand string read voltage adjustment. An apparatus includes a control circuit configured to conne...
Invention Sub-block status dependent device operation. A storage device is disclosed herein. The storage d...
Invention Method for dual wavelength overlay measurement with focus at a photoresist top surface and appara...
Invention Dynamic word line boosting during programming of a memory device. The memory device includes a m...
Invention Dual-way sensing scheme for better neighboring word-line interference. A storage device is discl...
Invention Current reference circuit with process, voltage, and wide-range temperature compensation. System...
Invention Precharge scheme during programming of a memory device. The memory device includes at least one ...
Invention Low line-sensitivity and process-portable reference voltage generator circuit. Systems and metho...
Invention Bundle multiple timing parameters for fast slc programming. Technology is disclosed herein for m...
Invention Foggy-fine drain-side select gate re-program for on-pitch semi-circle drain side select gates. A...
Invention Adaptive gidl voltage for erasing non-volatile memory. An apparatus is provided that includes a ...
Invention Three-dimensional memory device including dipole-containing blocking dielectric layer and methods...
Invention Non-volatile memory with shared data transfer latches. An apparatus includes a control circuit t...
Invention Non-volatile memory with tier-wise ramp down after program-verify. Memory cells are arranged as ...
Invention In-place write techniques without erase in a memory device. The memory device has a plurality of...
Invention In-place write techniques without erase in a memory device. The techniques include a memory devi...
Invention Nand memory with different pass voltage ramp rates for binary and multi-state memory. To reduce ...
Invention Nand io bandwidth increase. The disclosure provides circuits and methods for increasing NAND inp...
Invention Word line dependent pass voltage ramp rate to improve performance of nand memory. To reduce spik...
Invention Two-stage high speed level shifter. Improved voltage level shifters are disclosed capable of achi...
Invention Adaptive negative word line voltage. A storage device comprises: a non-volatile memory including...
Invention In-place write techniques without erase in a memory device. The memory device includes a plurali...
Invention Hybrid smart verify for qlc/tlc die. Technology is disclosed herein for smart verify in a memory...
Invention Advanced window program-verify. A memory apparatus and operating method are provided. The appara...
Invention Bonded assembly containing conductive via structures extending through word lines in a staircase ...
Invention Mixed bitline lockout for qlc/tlc die. Technology is disclosed herein for mixed lockout verify. ...
Invention Plane level dedicated starting program voltage to reduce program time for multi-plane concurrent ...
Invention Three-dimensional memory device and method of making thereof using sacrificial material regrowth....