2023
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Invention
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Three-dimensional memory device with backside support pillar structures and methods of forming th... |
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Invention
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Persistent memory management.
Apparatuses, systems, methods, and computer program products are d... |
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Invention
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Transistor circuits including fringeless transistors and method of making the same.
A lateral ex... |
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Invention
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Loop dependent word line ramp start time for program verify of multi-level nand memory. To reduce... |
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Invention
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Word line dependent pass voltage ramp rate to improve performance of nand memory. To reduce spike... |
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Invention
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Nand memory with different pass voltage ramp rates for binary and multi-state memory. To reduce s... |
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Invention
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Non-volatile memory with tier-wise ramp down after program-verify. Memory cells are arranged as N... |
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Invention
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Nand string read voltage adjustment. An apparatus includes a control circuit configured to connec... |
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Invention
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Adaptive gidl voltage for erasing non-volatile memory. An apparatus is provided that includes a b... |
2022
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Invention
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Ppa improvement for voltage mode driver and on-die termination (odt).
Systems and methods for im... |
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Invention
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High density semiconductor device including integrated controller, logic circuit and memory dies.... |
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Invention
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Apparatus and methods for bonding pad redistribution layers in integrated circuits.
An apparatus... |
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Invention
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Semiconductor device having edge seal and method of making thereof without metal hard mask arcing... |
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Invention
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Three-dimensional memory device and method of making thereof using selective metal nitride deposi... |
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Invention
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Nand fast cyclic redundancy check.
The present disclosure relates generally to a method of detec... |
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Invention
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End point detection method and apparatus for anisotropic etching using variable etch gas flow.
A... |
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Invention
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Three-dimensional memory device containing a pillar contact between channel and source and method... |
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Invention
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Zq calibration circuit and method for memory interfaces.
Systems and methods disclosed herein pr... |
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Invention
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Nand string read voltage adjustment.
An apparatus includes a control circuit configured to conne... |
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Invention
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Sub-block status dependent device operation.
A storage device is disclosed herein. The storage d... |
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Invention
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Method for dual wavelength overlay measurement with focus at a photoresist top surface and appara... |
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Invention
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Dynamic word line boosting during programming of a memory device.
The memory device includes a m... |
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Invention
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Dual-way sensing scheme for better neighboring word-line interference.
A storage device is discl... |
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Invention
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Current reference circuit with process, voltage, and wide-range temperature compensation.
System... |
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Invention
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Precharge scheme during programming of a memory device.
The memory device includes at least one ... |
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Invention
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Low line-sensitivity and process-portable reference voltage generator circuit.
Systems and metho... |
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Invention
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Bundle multiple timing parameters for fast slc programming.
Technology is disclosed herein for m... |
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Invention
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Foggy-fine drain-side select gate re-program for on-pitch semi-circle drain side select gates.
A... |
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Invention
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Adaptive gidl voltage for erasing non-volatile memory.
An apparatus is provided that includes a ... |
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Invention
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Three-dimensional memory device including dipole-containing blocking dielectric layer and methods... |
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Invention
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Non-volatile memory with shared data transfer latches.
An apparatus includes a control circuit t... |
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Invention
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Non-volatile memory with tier-wise ramp down after program-verify.
Memory cells are arranged as ... |
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Invention
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In-place write techniques without erase in a memory device.
The memory device has a plurality of... |
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Invention
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In-place write techniques without erase in a memory device.
The techniques include a memory devi... |
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Invention
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Nand memory with different pass voltage ramp rates for binary and multi-state memory.
To reduce ... |
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Invention
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Nand io bandwidth increase.
The disclosure provides circuits and methods for increasing NAND inp... |
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Invention
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Word line dependent pass voltage ramp rate to improve performance of nand memory.
To reduce spik... |
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Invention
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Two-stage high speed level shifter. Improved voltage level shifters are disclosed capable of achi... |
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Invention
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Adaptive negative word line voltage.
A storage device comprises: a non-volatile memory including... |
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Invention
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In-place write techniques without erase in a memory device.
The memory device includes a plurali... |
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Invention
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Hybrid smart verify for qlc/tlc die.
Technology is disclosed herein for smart verify in a memory... |
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Invention
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Advanced window program-verify.
A memory apparatus and operating method are provided. The appara... |
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Invention
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Bonded assembly containing conductive via structures extending through word lines in a staircase ... |
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Invention
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Mixed bitline lockout for qlc/tlc die.
Technology is disclosed herein for mixed lockout verify. ... |
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Invention
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Plane level dedicated starting program voltage to reduce program time for multi-plane concurrent ... |
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Invention
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Three-dimensional memory device and method of making thereof using sacrificial material regrowth.... |