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2024
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Invention
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Three-dimensional memory device including coaxial double contact via structures and methods for f... |
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Invention
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Memory device including an electrically conductive layer with a tapered corner and method of maki... |
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Invention
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Transistor circuits including fringeless transistors and method of making the same.
A first fiel... |
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Invention
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Three-dimensional memory device containing etch stop structures for word line contacts and method... |
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Invention
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Three-dimensional memory device and method of making thereof including non-conformal selective de... |
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Invention
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Cross-point array refresh scheme.
Technology is disclosed herein for refreshing threshold switch... |
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Invention
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Three-dimensional memory device with backside support pillar structures and methods of forming th... |
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Invention
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Open block read icc reduction. Technology is disclosed herein for a storage system that reduces t... |
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2023
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Invention
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Three-dimensional memory device containing multi-level word line contact wells and methods for ma... |
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Invention
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Three-dimensional memory device with integrated contact and support structure and method of makin... |
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Invention
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Three-dimensional memory device containing silicon oxycarbide liners and methods of forming the s... |
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Invention
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Non-volatile memory with loop dependant ramp-up rate. A non-volatile memory system is configured ... |
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Invention
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Apparatus and method for selectively reducing charge pump speed during erase operations. An appar... |
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Invention
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Three-dimensional memory device containing inverted staircase and method of making the same. A de... |
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Invention
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Three-dimensional memory device with backside word line contact via structures and methods of for... |
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Invention
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Transceiver architecture with low kick-back noise and pad cap.
Embodiments of the present techno... |
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Invention
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Three-dimensional memory device containing composite word lines including a respective fluorine-f... |
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Invention
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Open block read icc reduction.
Technology is disclosed herein for a storage system that reduces ... |
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Invention
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Non-volatile memory with slow voltage ramp compensation.
Non-volatile memory cells are programme... |
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Invention
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Method of making high aspect ratio openings using multiple cladding masks and apparatus for imple... |
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Invention
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Semiconductor device containing divot-fill dielectric barrier for metal-to-metal contacts and met... |
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Invention
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Non-volatile memory with adapting erase process.
A memory system performs an erase process for t... |
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Invention
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Integrated memory and control dies.
A memory system comprises a monolithic integration of a NAND... |
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Invention
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Stacked column floorplan for nand.
Technology is disclosed herein for memory device with control... |
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Invention
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Three-dimensional memory device and method of making thereof including expanded support openings ... |
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Invention
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Multi-wafer bonding for nand scaling.
Technology is disclosed herein for a memory device with mu... |
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Invention
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Three-dimensional memory device containing insulated gate located over a top source layer for app... |
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Invention
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Single-level cell pump skip program operation preliminary period timing optimization for non-vola... |
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Invention
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Three-dimensional memory device containing heterojunction source layer and method for manufacturi... |
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Invention
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Three-dimensional memory device containing inverted staircase and method of making the same.
A d... |
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Invention
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High voltage field effect transistors with superjunctions and method of making the same.
A field... |
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Invention
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Bonded three-dimensional memory device having temporary electrical grounding paths in dummy block... |
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Invention
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Three-dimensional memory device with reduced neighboring word line interference and methods of fo... |
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Invention
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One-time programmable memory devices and methods.
An apparatus is provided that includes a memor... |
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Invention
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Apparatus and method for selectively reducing charge pump speed during erase operations.
An appa... |
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Invention
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Programming techniques in a memory device to reduce a hybrid slc ratio.
The memory device includ... |
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Invention
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Hole channel pre-charge to enable large-volume in-place data sanitization of non-volatile memory.... |
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Invention
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Non-volatile memory with faster post-erase defect testing.
As part of the erase operation for a ... |
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Invention
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Enhanced operations of non-volatile memory with shared data transfer latches.
An apparatus inclu... |
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Invention
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Stage based frequency optimization for area reduction of charge pumps.
A stage-based frequency o... |
