Common view time transfer and related apparatuses and methods are disclosed. An apparatus includes a receiver oscillator to provide a local clock signal and one or more processors. The one or more processors are to perform, at least partially based on the local clock signal, event time tagging pre-processing at least partially responsive to satellite signals received from one or more satellites to generate a decimated precision correction state estimate; determine, per satellite signal pseudo range residuals; determine a navigation engine clock state; perform a precision clock state pre-processing operation at least partially responsive to the navigation engine clock state and the decimated precision correction state estimate to generate a precision navigation clock state; and generate a common view real time report at least partially responsive to the per satellite signal pseudo range residuals and the precision navigation clock state.
G01S 19/25 - Acquisition or tracking of signals transmitted by the system involving aiding data received from a cooperating element, e.g. assisted GPS
G01S 19/23 - Testing, monitoring, correcting or calibrating of a receiver element
G01S 19/39 - Determining a navigation solution using signals transmitted by a satellite radio beacon positioning system the satellite radio beacon positioning system transmitting time-stamped messages, e.g. GPS [Global Positioning System], GLONASS [Global Orbiting Navigation Satellite System] or GALILEO
A device for control of network traffic may include a plurality of edge interface circuit and internal interface circuits each coupled to one or more network components. The device may prepend frame identification information to received data frames and remove duplicate data frames when identification information is detected multiple times. The device may store frame identification information in a non-transitory memory device and perform a lookup operation to identify duplicate data frames and eliminate loops in the network.
A device includes a PWM circuit to generate a complementary PWM signal comprised of a positive polarity PWM signal and a negative polarity PWM signal. The positive polarity signal may drive a high-side switch. A trigger multiplexer may take as input the negative polarity PWM signal and may force an output based on a predetermined condition, the predetermined condition including but not limited to the maximum on-time of a low-side switch. The output of the trigger multiplexer may drive a low-side switch. The high-side switch and the low-side switch may drive a load.
H03K 17/693 - Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
A system for network data transactions, the system including an ingress port to receive data frames and timestamp received data frames, a frame analyzer to forward the data frames to a processor, the processor to extract timing information from the data frames and update the data frames based on updated timing calculations and output updated data frames via one or more egress ports. Data frames are timestamped at ingress and egress ports, and egress timestamps are saved in a timestamp memory. The system reduces overall network delays by using dedicated hardware and stored timestamp information.
Teachings of the present disclosure include systems and/or methods for encoding digital data into a handwritten sample. An example method includes: accessing a predetermined vibration pattern stored in a memory corresponding to defined data; and vibrating a stylus based on the predetermined vibration pattern during creation of the handwritten sample to encode the defined data into the handwriting sample.
G06V 30/224 - Character recognition characterised by the type of writing of printed characters having additional code marks or containing code marks
B43K 29/08 - Combinations of writing implements with other articles with measuring, computing or indicating devices
G06F 3/0346 - Pointing devices displaced or positioned by the user; Accessories therefor with detection of the device orientation or free movement in a 3D space, e.g. 3D mice, 6-DOF [six degrees of freedom] pointers using gyroscopes, accelerometers or tilt-sensors
G06F 3/0354 - Pointing devices displaced or positioned by the user; Accessories therefor with detection of 2D relative movements between the device, or an operating part thereof, and a plane or surface, e.g. 2D mice, trackballs, pens or pucks
G06F 3/038 - Control and interface arrangements therefor, e.g. drivers or device-embedded control circuitry
6.
DETERMINING A LOCKED STATUS OF A CLOCK TRACKING CIRCUIT
An example apparatus includes a phase detector, a digital discriminator, and a logic circuit. A status signal of the phase detector is at least partially based on a phase relationship between a reference clock and a feedback clock, the feedback clock generated by a clock tracking circuit to track the reference clock. The digital discriminator may sample the status signal of the phase detector. The logic circuit may determine a locked status of the clock tracking circuit at least partially based on samples of the status signal of the phase detector.
H03L 7/091 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
H03L 7/093 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
H03L 7/095 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using a lock detector
7.
SINGLE AND DUAL EDGE TRIGGERED PHASE ERROR DETECTION
An example apparatus includes a phase detector and a phase error detector. The phase detector may set a status signal to indicate status of phase difference between a reference clock and a feedback clock, the feedback clock generated by a clock tracking circuit to track the reference clock. The phase error detector may set an error signal to be proportional to a phase difference between the reference clock and the feedback clock. At least partially responsive to the status signal, the phase error detector to change from triggered only by edges of the reference clock and feedback clock having a first polarity to triggered by edges of the reference clock and feedback clock having the first polarity and by edges of the reference clock and feedback clock having a second polarity, the second polarity different than the first polarity.
H03L 7/087 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
H03L 7/091 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
An integrated resistor includes a resistor tub, a resistive element, and a dielectric liner. The resistor tub is formed from a conformal metal, and includes a laterally-extending tub base and vertically-extending tub sidewalls extending upwardly from the laterally-extending tub base, wherein the laterally-extending tub base and vertically-extending tub sidewalls define in a resistor tub interior opening. The dielectric liner is formed in the resistor tub interior opening. The resistive element is formed over the dielectric liner in the resistor tub interior opening, and includes a pair of resistor heads connected by a laterally-extending resistor body. The dielectric liner electrically insulates the resistive element from the resistor tub.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
A method of forming a partially silicided element is provided. A silicided structure including a silicide layer on a base structure is formed. A dielectric region is formed over the silicided structure. The dielectric region is etched to form a contact opening exposing a first area of the silicide layer and a tub opening exposing a second area of the silicide layer. A conformal metal is deposited to (a) fill the contact opening to define a contact and (b) form a cup-shaped metal structure in the tub opening. Another etch is performed to remove the cup-shaped metal structure in the tub opening, to remove the underlying silicide layer second area and to expose an underlying area of the base structure, wherein the silicide layer first area remains intact. The base structure with the intact silicide layer first area and removed silicide layer second area defines the partially silicided element.
A switched-capacitor DC-DC converter circuit may convert an input voltage into a desired output voltage level. A comparator may compare a desired voltage level to a divided version of the output voltage. A fully digital control circuit comprising a frequency divider circuit, a counter circuit, a digital control logic circuit and a gain selection circuit may generate a gain value, and a phase generator may convert the gain value into clock phase signals and control settings to control a switch array to select capacitors to produce a desired output voltage.
H02M 3/07 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
H02M 3/157 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
11.
SYMBOL FILTERING AT A PHY-SIDE of PHY-MAC INTERFACE
Disclosed examples include a method. The method includes: conveying symbols from a PHY toward a MAC via a PHY-side of PHY-MAC interface; and filtering one or more symbols at an input of a PHY-side of an interface wrapper of the PHY-side of the PHY-MAC interface. Disclosed examples include an apparatus. The apparatus includes: a PHY-side of PHY-MAC interface; and a logic circuit provided at the PHY-side of PHY-MAC interface, the logic circuit comprising a symbol filter to filter one or more symbols conveyed via the PHY-side of PHY-MAC interface.
A method includes: observing that a digitally controlled oscillator (DCO) frequency is at a boundary of a DCO frequency overlap region; and bypassing at least a portion of the DCO frequency overlap region.
H03L 7/099 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
H03L 7/10 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
13.
SYSTEM FOR TRANSMITTING OBJECT RELATED DATA FROM A BASE UNIT TO A MOBILE UNIT THROUGH A PERSON'S BODY
A system includes a base unit associated with an object, and a mobile unit carriable by a person. The base unit includes a base unit capacitive coupling element providing a base unit-human capacitive coupling between the base unit and the person, and the mobile unit includes a mobile unit capacitive coupling element providing a mobile unit-human capacitive coupling between the mobile unit and the person. The base unit-human capacitive coupling and mobile unit-human capacitive coupling enable a data transmission connection between the base unit and mobile unit that passes through the person's body. Base unit transmitter circuitry of the base unit transmits object related data via the data transmission connection passing through the person's body, mobile unit receiver circuitry of the mobile unit receives the object related data, and an output device of the mobile unit outputs human-perceptible signals based on the received object related data.
G06F 3/0362 - Pointing devices displaced or positioned by the user; Accessories therefor with detection of 1D translations or rotations of an operating part of the device, e.g. scroll wheels, sliders, knobs, rollers or belts
A peripheral device for matrix multiplication including a weight memory, an input memory, a multiplier, an accumulator, an output memory and a sequencer to generate signals to drive the input memory and the output memory and to generate an interrupt signal. The weight memory may be loaded with weights and biases for a matrix multiplication operation, and the multiplier and accumulator may implement the multiply and accumulator operations for a matrix multiplication operation. Data may be swapped between the input memory and output memory to reduce the memory required for matrix multiplication operations.
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
An apparatus and method for determining electrical characteristics has an acquisition circuit and a control circuit. The control circuit causes a first modulation circuit to issue a first set of modulated signals to a first source of alternating current energy, wherein the first set of modulated signals has a first deadtime and wherein a high side switch and a low side switch of the first modulation circuit are turned off. The control circuit further causes the acquisition circuit to acquire a first electrical characteristic of the first source of alternating current energy from the first source of alternating current energy during the first deadtime.
H02P 6/182 - Circuit arrangements for detecting position without separate position detecting elements using back-emf in windings
H02P 6/10 - Arrangements for controlling torque ripple, e.g. providing reduced torque ripple
H02P 27/08 - Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using dc to ac converters or inverters with pulse width modulation
An apparatus includes a power-over-Ethernet (POE) interface to be connected to a powered device (PD) over an Ethernet cable and a control circuit. The control circuit is to measure a voltage provided by the apparatus through the Ethernet cable, determine that the voltage has dropped by at least a given voltage change, based on a determination that the voltage has dropped by at least the given voltage change, determine whether or not a predetermined quantity of Maintain Power Signature (MPS) signals have been missed within a given time frame, and, based on a determination that the predetermined quantity of MPS signals has not been missed within the given time frame, determine that the PD is still connected to the apparatus.
An apparatus may include a physical layer device, a detection circuitry and a power control circuitry. the physical layer device provides one or more functions of a physical layer to interface with a shared physical transmission medium. The detection circuitry detects an indication of power control signaling on the shared physical transmission medium, and detects an indication of Ethernet signaling on the shared physical transmission medium. The indication of power control signaling is different than the indication of Ethernet signaling. The power control circuitry manages a power state of the apparatus at least partially responsive to an output of the detection circuitry.
Motion detection apparatuses are disclosed. The motion detection may be performed using one or more of a sub-window of a predetermined time window, a predetermined threshold value that is settable responsive to changes in one or more environmental factors, or a detection trigger. An apparatus includes a processor and an analog-to-digital converter (ADC) circuitry to sample a reflected predetermined pattern signal to generate reflected predetermined pattern samples. The processor captures collections of the reflected predetermined pattern samples corresponding to a predetermined time window and determines a sum of the collections or sub-collections. The processor determines an average of magnitudes of the determined sum and determines that a moving object is detected responsive to a predetermined threshold value.
A device including an input to receive a clock signal, a ramp start program register, a ramp start active register, a ramp stop program register, a ramp stop active register, a ramp slope program register, a ramp slope active register, an update controller, the update controller to update, based on a programmable condition, respectively, the ramp start active register contents, the ramp stop active register contents and the ramp slope active register contents, and a ramp controller to generate a ramp signal, the ramp signal to begin at the value reflective of the ramp start active register contents, the ramp signal to change value at each cycle of the clock signal based on the value reflective of the ramp slope active register contents, and the ramp signal to stop at the value reflective of the ramp stop active register contents.
One or more examples relate to a method. The method may include: comparing a first value and a second value, the first value representing a duty cycle of a reference clock and the second value representing a duty cycle of an output clock generated by a clock tracking circuit to track the reference clock; setting a duty cycle of a changed clock to reduce duty cycle mismatch between the reference clock and the output clock indicated by the comparing; and providing the changed clock having set duty cycle in lieu of the one of the reference clock or the output clock.
H03L 7/081 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop provided with an additional controlled phase shifter
H03K 5/156 - Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
An inductor-inductor-capacitor (LLC) power converter includes a current input interface to receive a current input indication. The current input indication includes a voltage to represent a current passing through of a primary side of the LLC power converter. The LLC power converter includes voltage input interface to receive a voltage input. The voltage input is to include a representative voltage to be provided from a secondary side of the LLC power converter. The LLC power converter includes a control circuit to generate pulsed-width modulation (PWM) control signals for the LLC power converter. The control circuit is to match an on-time period of a first leg and a second leg of the LLC power converter and based upon the current input indication and the voltage input.
H02M 1/088 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
H02M 3/00 - Conversion of dc power input into dc power output
H02M 3/335 - Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
22.
TRIGGERING AN ERROR DETECTOR ON RISING AND FALLING EDGES OF CLOCK SIGNALS, AND GENERATING AN ERROR SIGNAL THEREFROM
One or more examples relate to triggering a single error detector on rising and falling edges of clock signals, and generating an error signal therefrom. A method may include receiving a first clock signal and a second clock signal. The method may include generating, via a single error detector being triggered at least partially responsive to like respective edges of the first clock signal and the second clock signal, an error signal that represents a phase difference between the first clock signal and the second clock signal.
One or more examples relate to a method. The method includes: receiving up/down error signals indicative of duty cycle mismatch between a reference clock signal and a changed feedback clock signal that represents an output clock signal generated by a clock tracking circuit to track the reference clock signal; setting a duty cycle of a changed feedback clock signal to reduce duty cycle mismatch indicated by the up/down error signals; and providing the changed feedback clock having set duty cycle.
H03K 5/135 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
24.
TIMESTAMP AT A PARALLEL INTERFACE OF A SERDES COUPLING A PHY WITH A PHYSICAL TRANSMISSION MEDIUM
One or more examples relate, generally, to timestamp at a parallel interface of a SerDes for coupling a PHY with a physical transmission medium. In an example, an apparatus includes a SerDes to couple a PHY to a physical transmission medium; a hardware timestamp logic; a bit detector coupled to initiate the hardware timestamp logic at least partially responsive to observing an indicated bit at a parallel interface of the SerDes; and a logic circuit provided at a portion of the PHY, the logic circuit coupled to receive timestamps generated by hardware timestamp logic.
A multi-capacitor module includes a stacked metal-insulator-metal (MIM) structure including a cup-shaped first electrode, a cup-shaped first insulator formed over the cup-shaped first electrode, a cup-shaped second electrode formed over the cup-shaped first insulator, a cup-shaped second insulator formed over the cup-shaped second electrode, a third electrode formed over the cup-shaped second insulator. The stacked MIM structure also includes a first sidewall spacer located between the cup-shaped first electrode and the cup-shaped second electrode, and a second sidewall spacer located between the cup-shaped second electrode and the third electrode. The cup-shaped first electrode, the cup-shaped second electrode, and the cup-shaped first insulator define a first capacitor, and the cup-shaped second electrode, the third electrode, and the cup-shaped second insulator define a second capacitor.
Examples relate to generating sync signals. An example apparatus includes an output, an input and a circuit. The output provides a data-valid signal to a video source operative to provide video data to a video-data-processing pipeline. The input receives a delayed data-valid signal from the video-data-processing pipeline. The circuit to generate a delayed horizontal-sync signal and a delayed vertical-sync signal at least partially responsive to the received delayed data-valid signal.
H04N 21/43 - Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronizing decoder's clock; Client middleware
Vapor cells may include a body including a cavity within the body. A first substrate bonded to a second substrate at an interface within the body, at least one of the first substrate, the second substrate, or an interfacial material between the first and second substrates may define at least one recess or pore in a surface. A smallest dimension of the at least one recess or pore may be about 500 microns or less, as measured in a direction parallel to at least one surface of the first substrate partially defining the cavity.
H03L 7/26 - Automatic control of frequency or phase; Synchronisation using energy levels of molecules, atoms, or subatomic particles as a frequency reference
28.
MULTI-CAPACITOR MODULE INCLUDING A NESTED METAL-INSULATOR-METAL (MIM) STRUCTURE
A multi-capacitor module includes a nested metal-insulator-metal (MIM) structure including a cup-shaped first electrode, a cup-shaped first insulator formed over the cup-shaped first electrode, a cup-shaped second electrode formed over the cup-shaped first insulator, a cup-shaped second insulator formed over the cup-shaped second electrode, and a third electrode formed over the cup-shaped second insulator. The cup-shaped first electrode, the cup-shaped second electrode, and the cup-shaped first insulator define a first capacitor, and the cup-shaped second electrode, the third electrode, and the cup-shaped second insulator define a second capacitor physically nested in the first capacitor.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
29.
High-Level-Synthesis for RISC-V System-on-Chip Generation for Field Programmable Gate Arrays
An article of manufacture includes a medium with instructions that when read and executed by a processor, cause the processor to identify a code stream to be executed by a system-on-a-chip (SoC). The SoC is to include an open standard processor and hardware accelerators implemented in reprogrammable hardware. The processor is to, from the code stream, identify a first portion of the code stream to be executed as software by the open standard processor and a second portion to be executed in the accelerators, compile the first portion into a binary for execution by the open standard processor, and generate a hardware description for the second portion to be implemented by the hardware accelerators. The hardware description and the binary are to exchange data during execution of the code stream.
A metal-insulator-metal (MIM) capacitor includes a bottom electrode, an insulator cup formed on the bottom electrode, a top electrode formed in an opening defined by the insulator cup, a top electrode connection element electrically connected to the top electrode, a vertically-extending bottom electrode contact electrically connected to the bottom electrode, and a bottom electrode connection element electrically connected to the vertically-extending bottom electrode contact. The bottom electrode is formed in a lower metal layer. The insulator cup is formed in a tub opening in a dielectric region and includes a laterally extending insulator cup base formed on the bottom electrode and a vertically-extending insulator cup sidewall extending upwardly from the laterally extending insulator cup base. The top electrode connection element and bottom electrode connection element are formed in an upper metal layer.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
A device for measuring phase noise, including a sampler to sample an input signal, an input filter to receive an input from the sampler, a noise generator to generate a noise signal, a combiner to receive input from, respectively, the input filter and the noise generator, the combiner to output an integrated noise output measurement. The input filter may operate in either the time domain or the frequency domain. The noise generate may generate a noise signal based on the sampler output, or may generate a noise estimate value based on the sampler output.
A fault event monitor and filter having a digital comparator receiving a digital input value, wherein the digital comparator generates a plurality of outputs based on programmable threshold input values, a first counter coupled to a first output of the plurality of outputs of the digital comparator, a second counter coupled to a second output of the plurality of outputs of the digital comparator, and an output controller with a first input coupled to an output of the first counter and with a second input coupled to an output of the second counter, wherein the output controller to generate a fault event signal based at least partially on signals received from the first and second counters.
A system includes a metal tub structure formed in an integrated circuit (IC) structure, a first metal component, and a second metal component. The first metal component is formed from a first metal. The first metal component is formed in an opening defined by the metal tub structure, and includes a first metal first junction element, a first metal second junction element, and a first metal bridge electrically connected to the first metal first junction element and the first metal second junction element. The second metal component is formed from a second metal different than the first metal, and includes a second metal first junction element electrically connected to the first metal first junction element to define a first thermocouple junction, and a second metal second junction element electrically connected to the first metal second junction element to define a second thermocouple junction.
G01K 7/06 - Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat using thermoelectric elements, e.g. thermocouples the object to be measured not forming one of the thermoelectric materials the thermoelectric materials being arranged one within the other with the junction at one end exposed to the object, e.g. sheathed type
G01K 7/02 - Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat using thermoelectric elements, e.g. thermocouples
Examples disclosed herein include a video-data encoder. The video data encoder may encode a 4×4 data block into a bit stream according to a context adaptive variable length coding. The 4×4 data block may be representative of video data. The video-data encoder may, while encoding the 4×4 data block, ignore at least some coefficients of the 4×4 data block. In some examples, the video-data encoder may ignore the at least some coefficients of the 4×4 data block by setting the at least some coefficients of the 4×4 data block to zero prior to encoding the 4×4 data block. Related devices, systems and methods are also disclosed.
H04N 19/13 - Adaptive entropy coding, e.g. adaptive variable length coding [AVLC] or context adaptive binary arithmetic coding [CABAC]
H04N 19/176 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
H04N 19/129 - Scanning of coding units, e.g. zig-zag scan of transform coefficients or flexible macroblock ordering [FMO]
H04N 19/60 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding
Methods of using vapor cells may involve providing a vapor cell including a body defining a cavity within the body. At least a portion of at least one surface of the vapor cell within the cavity may include at least one pore having an average dimension of about 500 microns or less, as measured in a direction parallel to the at least one surface. A vapor pressure of a subject material within the cavity may be controlled utilizing the at least one pore by inducing an exposed surface of a subject material in a liquid state within the at least one pore to have a shape different than a shape the exposed surface of the subject material in a liquid state would have on a flat, nonporous surface.
H03L 7/26 - Automatic control of frequency or phase; Synchronisation using energy levels of molecules, atoms, or subatomic particles as a frequency reference
G04F 5/14 - Apparatus for producing preselected time intervals for use as timing standards using atomic clocks
G05D 16/04 - Control of fluid pressure without auxiliary power
36.
DELTA-SIGMA MODULATION UTILIZING CONTINUOUS-TIME INPUT AND DISCRETE-TIME LOOP FILTER
Delta-sigma modulation utilizing continuous-time input and discrete-time loop filter. An apparatus includes an input circuit, a switched-capacitor, an integrator, a quantizer and a feedback loop. The input circuit receives an analog signal and produce an analog input signal, the input circuit comprising a resistor-capacitor (RC) integrator. The switched-capacitor samples the analog input signal and produce a discrete-time, sampled input signal. The integrator processes the discrete-time, sampled input signal. The quantizer converts an output of the integrator to a digital signal. The feedback loop provides the digital signal to respective inputs of the RC integrator and the integrator.
An device having an oscillator circuit modifiable between a first operating mode and a second operating mode, wherein the first operating mode has a first frequency accuracy and a first power consumption, wherein the second operating mode has a second frequency accuracy and a second power consumption, wherein the second frequency accuracy is more accurate than the first frequency accuracy and the second power consumption is higher than the first power consumption, and a control circuit in communication with the oscillator circuit to modify the operating mode of the oscillator circuit.
H03B 5/24 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising resistance and either capacitance or inductance, e.g. phase-shift oscillator active element in amplifier being semiconductor device
38.
FOREIGN OBJECT DETECTION AND RELATED APPARATUSES, METHODS, AND SYSTEMS
Foreign object detection and related apparatuses, methods, and systems are disclosed. An apparatus includes one or more inductive coils to wirelessly couple with another inductive coil, a series capacitor electrically connected in series with the one or more inductive coils, and a controller to determine a coil current through the one or more inductive coils responsive to a capacitor voltage potential difference across the series capacitor and determine a coil power responsive to the determined coil current and a coil voltage potential difference across the one or more inductive coils.
H02J 50/60 - Circuit arrangements or systems for wireless supply or distribution of electric power responsive to the presence of foreign objects, e.g. detection of living beings
G01R 19/25 - Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques
H02J 50/10 - Circuit arrangements or systems for wireless supply or distribution of electric power using inductive coupling
A hermetically sealed semiconductor die package having a sidewall structure having a first opening and a second opening; a lid attached to the sidewall structure to hermetically seal the first opening; a substrate attached to the sidewall structure to hermetically seal the second opening, wherein the substrate comprises first, second, and third apertures; a first button attached to the substrate to hermetically seal the first aperture; a second button attached to the substrate to hermetically seal the second aperture; and a third button attached to the substrate to hermetically seal the third aperture.
A thin film resistor (TFR) module includes a metal cup structure, a dielectric liner region, a TFR element, and a pair of TFR heads electrically connected to the TFR element. The metal cup structure includes a laterally-extending metal cup base and multiple metal cup sidewalls extending upwardly from the laterally-extending metal cup base. The dielectric liner region is formed in an opening defined by the metal cup structure. The TFR element is formed in an opening defined by the dielectric liner region, wherein the TFR element is insulated from the metal cup structure by the dielectric liner region.
H01C 7/00 - Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material
H01L 27/01 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate comprising only passive thin-film or thick-film elements formed on a common insulating substrate
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01C 17/075 - Apparatus or processes specially adapted for manufacturing resistors adapted for coating resistive material on a base by thin-film techniques
41.
INVERTING CURRENT AMPLIFICATION AND RELATED TOUCH SYSTEMS
One or more examples relate to inverting current amplification and related touch systems. An apparatus includes a first transistor, a second transistor, and a feedback loop. The first transistor and the second transistor provide controlled current at the second transistor that is a copy of current at the first transistor when respective drain-source voltages of the first transistor and the second transistor are substantially equal. The feedback loop sets respective drain-source voltages of the first transistor and the second transistor to be substantially equal, wherein a responsiveness of the feedback loop is proportional to a set transconductance of the feedback loop.
A device with boot code, first mutable code stored in non-volatile memory, a first owner information stored in the non-volatile memory, and an SRAM with an SRAM physically unclonable function (SRAM PUF) region. Boot code may generate a first unique private key based on both the first owner information and a portion of the SRAM PUF region, wherein the first unique private key may not be directly accessible by the first mutable code; generate a first unique private keycode corresponding to the first unique private key; and provide the first mutable code with the first unique private keycode corresponding to the first unique private key. First mutable code may use the first unique private keycode to cause data to be signed with the first unique private key and generate a first unique mutable code private key based on at least a portion of the SRAM PUF region.
G06F 21/72 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in cryptographic circuits
A multi-phase power converter with current matching is provided. The apparatus may include a control circuit to control a first phase of a power converter having a plurality of phases, and a phase matching circuit. The phase matching circuit may remove a DC component from an output ripple voltage of the converter, detect when respective ones of the plurality of phases begins generating its respective phase current and output a phase detector signal, extract a signal proportional to the first phase current and a signal proportional to either the remaining or total phase currents, output first and second voltages respectively proportional to the average of the first phase current and the remaining or total phase current, and output a corrective signal based on the difference between the first and second voltage. The control circuit may control the first phase based on the corrective signal.
H02M 1/14 - Arrangements for reducing ripples from dc input or output
H02M 7/5387 - Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
H02M 7/48 - Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
44.
Metal-Oxide-Metal (MOM) Capacitors for Integrated Circuit Monitoring
An array of metal-oxide-metal (MOM) capacitors formed in an integrated circuit (IC) structure may be used for evaluating misalignments between patterned layers of the IC structure. The array of MOM capacitors may be formed in a selected set of patterned layers, e.g., a via layer formed between a pair of metal interconnect layers. The MOM capacitors may be programmed with different patterned layer alignments (e.g., built in to photomasks or reticles used to form the patterned layers) to define an array of different alignments. When the MOM capacitors are formed on the wafer, the actual patterned layer alignments capacitors may differ from the programmed layer alignments due a process-related misalignment. The MOM capacitors may be subjected to electrical testing to identify this process-related misalignment, which may be used for initiating a correcting action, e.g., adjusting a manufacturing process or discarding misaligned IC structures or devices.
H01L 23/528 - Layout of the interconnection structure
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 21/66 - Testing or measuring during manufacture or treatment
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
45.
BIT ERROR RATE ESTIMATION AND ERROR CORRECTION AND RELATED SYSTEMS, METHODS, DEVICES
Physical layer devices and related methods for determining Bit Error Rates (BERs) and correcting errors in signals received through shared transmission media of wireless local area networks are disclosed. A physical layer device is configured to identify coding violations in received signal, determine a rate of the coding violations in the signal, and estimate a BER of the signal to be equal to the determined rate of the coding violations. A physical layer device is configured to invert a half symbol immediately preceding or immediately following a coding violation based, at least in part, on signal integrities of the half symbol immediately preceding and the half symbol immediately following the coding violation to correct a bit error.
An article of manufacture includes a non-transitory machine-readable medium. The medium includes instructions. The instructions, when read and executed by a processor, cause the processor to identify a first input instruction in a code stream to be executed, determine that the first input instruction includes an atomic operation designation, and selectively block interrupts for a duration of execution of the first input instruction and a second input instruction. The second input instruction is to immediately follow the first input instruction in the code stream.
G06F 9/38 - Concurrent instruction execution, e.g. pipeline, look ahead
G06F 13/366 - Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using a centralised polling arbiter
47.
Ferroelectric random access memory (FRAM) capacitors and methods of construction
Ferroelectric random access memory (FRAM) capacitors and methods of forming FRAM capacitors are provided. An FRAM capacitor may be formed between adjacent metal interconnect layers or between a silicided active layer (e.g., including MOSFET devices) and a first metal interconnect layer. The FRAM capacitor may be formed by a damascene process including forming a tub opening in a dielectric region, forming a cup-shaped bottom electrode, forming a cup-shaped ferroelectric element in an interior opening defined by the cup-shaped bottom electrode, and forming a top electrode in an interior opening defined by the cup-shaped ferroelectric element. The FRAM capacitor may form a component of an FRAM memory cell. For example, an FRAM memory cell may include one FRAM capacitor and one transistor (1T1C configuration) or two FRAM capacitors and two transistor (2T2C configuration).
An apparatus includes a test circuit to receive signals from a piezoelectric horn and a control circuit to determine whether to operate the apparatus in a silent test mode or a normal mode. The apparatus includes a control circuit to, based on a determination to operate in the normal mode, enable a driver circuit to drive the piezoelectric horn so as to output sound when activated by the driver circuit. The test circuit is to, based on a determination to operate in the silent test mode, cause the piezoelectric horn to generate a piezoelectric response, wherein the piezoelectric horn is silent while generating the piezoelectric response during the silent test mode, and cause evaluation of whether or not the piezoelectric horn is working correctly based upon the received signals from the piezoelectric horn.
G10K 9/122 - Devices in which sound is produced by vibrating a diaphragm or analogous element, e.g. fog horns, vehicle hooters or buzzers electrically operated using piezoelectric driving means
H04R 17/10 - Resonant transducers, i.e. adapted to produce maximum output at a predetermined frequency
A system-level design generator tool enables users to configure system-level designs made up of electrical components that satisfy design parameters and have corresponding dependencies, e.g., power, communication, control, security, clock and memory. A block diagram representing each of the functions within the system may utilize a guided parametric search or a design tool to create the solution for each individual block. The inputs into that search and/or design tool may come from the system-level choices, constraints, and cross dependencies tracked by the system generator tool.
A system and method for performing rate adaptation of sub1G packet-oriented client signals for transmission over a Metro Transport Network (MTN) by forming a 64B/66B-encoded client signal from individual client packets of the sub1G packet-oriented client signal and the idle blocks within an inter-packet gap (IPG), inserting thread operations, administration and maintenance (ThOAM) overhead to generate a 64B/66B-encoded client thread signal, performing an idle mapping procedure (IMP) to generate a rate adapted 64B/66B-encoded client thread signal, defining a plurality of pseudo-Ethernet packets in an MTN path, defining a thread channel within the plurality of pseudo-Ethernet packets and mapping the rate adapted 64B/66B-encoded client thread signal into the defined thread channel within the plurality of pseudo-Ethernet packets to generate an MTN path signal for transmission to an intermediate node or a sink mode.
Various examples include a target for an inductive angular-position sensor. The target may rotate about a center axis and may include a number of fins respectively including a respective outer-circumferential edge to overlap a respective first arc at least partially defining a first circle centered at the center axis. A respective first central angle of the respective first arc substantially equal to 360° divided by twice a count of the fins. The number of fins may respectively include a respective inner-circumferential edge, positioned closer to the center axis than the respective outer-circumferential edge is to the center axis. The respective inner-circumferential edge may overlap a respective second arc at least partially defining a second circle centered at the center axis. A respective second central angle of the respective second arc substantially equal to 360° divided by the count of the fins. Related devices, systems and methods are also disclosed.
G01D 5/20 - Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using electric or magnetic means influencing the magnitude of a current or voltage by varying inductance, e.g. by a movable armature
52.
LEARNING A CONNECTIVITY STATE OF AN EXTERNAL NETWORK CONNECTION OF A WI-FI ROUTER
One or more examples relate to detecting external network connectivity at a Wi-Fi router. A disclosed Wi-Fi router may include a Wi-Fi controller and a connectivity circuit. The connectivity circuit may learn a connectivity state of an external network connection of the Wi-Fi router. The connectivity circuit may provide connectivity state information to the Wi-Fi controller. The connectivity state information may include information about the learned connectivity state of the external network connection of the Wi-Fi router.
One or more examples relate, generally, to providing timing signals to gate drivers of a converter. An example apparatus for providing timing signals to gate drivers of a converter includes a circuit that includes a timing input, and a plurality of outputs. The timing input may receive an incoming timing signal. The plurality of outputs may couple to a respective plurality of gate drivers to control an output voltage of a converter. The circuit may provide respective timing signals, at respective ones of the plurality of outputs at least partially responsive to the incoming timing signal, the respective timing signals synchronized such that like edges of the respective timing signals coincide.
H02M 1/088 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
Various examples include a target for inductive angular-position sensing and an inductive angular-position sensor including the same. The target has a target body comprising an inner circular ring around a center axis, and multiple fins formed with and extending radially from portions of the inner circular ring and equally-radially spaced around the center axis. Respective ones of the multiple fins are formed as an arc band-shaped ring. In one or more examples, the respective ones of the multiple fins formed as the arc band-shaped ring provide a current path for an eddy current for the inductive angular-position sensing.
G01B 7/30 - Measuring arrangements characterised by the use of electric or magnetic techniques for testing the alignment of axes
G01D 5/20 - Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using electric or magnetic means influencing the magnitude of a current or voltage by varying inductance, e.g. by a movable armature
55.
Current Sourced, Voltage Clamped, High Speed MOSFET Driver
An apparatus includes an apparatus input to receive a voltage input, an apparatus output to drive an output metal oxide semiconductor field effect transistor (MOSFET) at least partially based upon the voltage input, a current source circuit to provide a current source to the apparatus output when the voltage input rises above a first threshold and before the voltage input rises above a second threshold, a voltage clamp circuit to provide a clamped output voltage to the apparatus output when the voltage input rises above the second threshold, and a current sink circuit to provide a current sink to the apparatus output when the voltage input falls below the second threshold and before the voltage input reaches the first threshold.
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
H03K 17/06 - Modifications for ensuring a fully conducting state
H03K 17/12 - Modifications for increasing the maximum permissible switched current
56.
VEHICLE SECURITY DEVICE WITH PRIMARY ALARM AND DISPLAY ALARM
A system having a theft event sensor; a primary alarm actuator; a display alarm actuator; and a vehicle security device to: receive a theft event signal from the theft event sensor, transmit a primary alarm signal to the primary alarm actuator, and transmit a display alarm signal to the display alarm actuator.
B60R 25/10 - Fittings or systems for preventing or indicating unauthorised use or theft of vehicles actuating a signalling device
B60R 25/104 - Fittings or systems for preventing or indicating unauthorised use or theft of vehicles actuating a signalling device characterised by the type of theft warning signal, e.g. visual or audible signals with special characteristics
An apparatus includes an adjustment circuit configured to receive a pulsed-width modulation (PWM) input, generate an adjusted PWM signal based upon the PWM input, and determine that a first pulse of the PWM input is shorter than a runt signal limit. The adjustment circuit is further configured to, in the adjusted PWM signal, extend the first pulse of the PWM input based on the determination that the PWM input is shorter than the runt signal limit, and output the adjusted PWM signal to an electronic device.
A low dropout (LDO) regulator circuit is provided. The LDO regulator circuit may include a pre-regulator circuit to receive a high voltage input voltage and provide a low voltage supply voltage, and an LDO regulator to receive the low voltage supply voltage and provide a low voltage output voltage. The pre-regulator circuit may include an input stage, an output stage coupled to the input stage, and a first MOSFET coupled to the output stage to provide the low voltage supply voltage. The input stage and first MOSFET may receive the high voltage input voltage. The LDO regulator may include a second MOSFET coupled to the first MOSFET, and may receive the low voltage supply voltage and provide the low voltage output voltage.
G05F 1/563 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices including two stages of regulation, at least one of which is output level responsive, e.g. coarse and fine regulation
G05F 1/56 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
59.
VOLTAGE LEVEL SHIFTING AND CONNECTIONS WITH TOUCH ELECTRODES INCLUDING THE SAME
One or more examples relate to voltage level shifting. An example apparatus may include first and second inputs, an output, and a circuit. The first and second inputs may receive compliments of a signal represented by first voltage levels. The output may provide the signal represented by second voltage levels. The circuit may change voltage levels utilized to represent the signal from first voltage levels to second voltage levels. The circuit may include cross-coupled first high voltage switches, a pair of series coupled switches, and a pair of voltage clamping switches. The cross-coupled first high voltage switches may selectively couple the output to a high voltage node responsive to a high voltage level of the signal. The pair of series coupled switches may comprising respective second high voltage switches, and the pair of series coupled switches may selectively couple the output to a first voltage supply. The pair of voltage clamping switches may increase OFF-resistance of the respective second high voltage switches of the pair of series coupled switches responsive to a low voltage level at the respective input.
A method and apparatus in which a data stream is received that includes constant bit rate (CBR) carrier streams, at least one of which comprises frames, a cumulative phase offset report (CPOR) and a client rate report (CRR). A counter accumulating a PHY-scaled stream clock (IPSCk) is sampled at a nominal sampling period (Tps) to obtain a cumulative PHY-scaled count (CPSC). A PHY-scaled stream phase offset (PSPO) is calculated that indicates phase difference between PHY-scaled stream nominal bit count (LPSD) and an incoming PHY-scaled count delta (IPSD). The data stream is demultiplexed to obtain CBR carrier streams. Respective CBR carrier streams include a previous network node CPOR (CPOR-P) and a previous network node CPO (CPO-P). A CPO is calculated that is a function of CPO-P and PSPO. CPO-P is replaced with the calculated CPO. The CBR carrier streams are multiplexed into intermediate-network-node data streams that are transmitted from the intermediate-network-node.
One or more examples relate, generally to supply voltage based or temperature based fine control of a tunable oscillator of a PLL. An associated method includes: receiving one or more values indicative of temperature or supply voltage of a phase-locked loop (PLL); setting a digital fine-tuning control code to an initialization code, the initialization code at least partially based on the received one or more values indicative of temperature or supply voltage of the PLL, wherein the digital fine-tuning control code for setting a number of tuning-elements within a fine bank of a tunable oscillator; and starting, with the set digital fine-tuning control code, a process to set an initial frequency of the oscillator at or close to a target frequency. The process may be a calibration process performed before initially acquiring lock or re-acquiring lock.
H03L 7/099 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
62.
EMI Reduction in PLCA-Based Networks Through Beacon Temporal Spreading
An apparatus may be communicatively coupled to other nodes in a network. The apparatus may include a control circuit configured to repeatedly issue transmission cycles to the other nodes. A given transmission cycle may include a least one send slot for each of the other nodes to send data. The control circuit may be configured to initiate transmission cycles by issuing beacon signals to the other nodes. The control circuit may be configured to determine when to issue a beacon signal in a given transmission cycle by determining that all of the other nodes have completed all associated send slots in an immediately previous transmission cycle and based upon a determination of the completion of the other nodes' transmission, delaying transmission of the beacon signal for the given transmission cycle.
An apparatus having a substrate having first and second substrate contacts; a chip having a front-side chip contact and first and second back-side chip contacts, the front-side chip contact electrically connected to the first substrate contact; a chiplet having a chiplet contact electrically connected the first back-side chip contact; and a lead electrically connected to the second back-side chip contact and electrically connected to the second substrate contact.
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
A USB control method comprising: counting errors encountered by a USB connection; comparing a number of counted errors to an error count threshold within a set time frame; identifying a port speed configuration for the USB connection; and changing the port speed configuration for the USB connection to a slower port speed configuration than the identified port speed configuration.
An active inductor modulator circuit is provided. The active inductor modulator circuit may include a circuit to receive an input signal and provide an output signal at an output terminal of the circuit based on a clock signal, a modulated active inductor coupled to the circuit to improve a time delay between the input signal and the provided output signal, and a modulation clock circuit to generate a delayed clock signal to enable the modulated active inductor prior to a transition of the output signal from a first logic state to a second logic state.
An apparatus includes two PHY circuits, each including a PHY transmitter circuit and connected to a universal serial bus (USB)-C connector. The apparatus includes a USB circuit to issue a receiver detect signal through one of the PHY transmitters circuit to the USB-C connector, issue another receiver detect signal through the other PHY transmitter circuit to the USB-C connector, determine which receiver detect signal resulted in a termination in a USB-C element, and consequently determine an orientation of a USB plug connected between the apparatus and the USB-C element.
A device with one-time-programmable (OTP) memory, boot code, volatile memory, and non-volatile memory. Boot code may use information in OTP to authenticate code of an implicit owner of the electronic device; receive a first create owner container request; create a first owner container comprising a first signed data image; store the first owner container; and use the first signed data image to authenticate first executable code associated with the first owner. Boot code may transfer ownership from the first owner to a second owner, including authenticating a signed transfer of ownership command using a key stored in the first owner container and creating a second owner container comprising a second signed data image associated with the second owner; storing the second owner container; revoking the first owner container; and using the second signed data image to authenticate second executable code associated with the second owner of the electronic device.
Disclosed are systems, methods, and devices for communicating a source of a 10SPE wake. Such a communication may be performed over a low-pin count hardware interface of a 10SPE physical layer (PHY) module having a split arrangement. A controller side of a 10SPE PHY may perform a local or remote 10SPE wake forward in response to a communicated source of a wake. Also disclosed is a digital interface for operatively coupling a PHY controller to PHY transceiver over a low-pin count connection, where the digital interface includes circuitry for checking the integrity of circuitry of the digital interface. Also disclosed is a PHY transceiver of a 10SPE PHY, where the transceiver includes a circuitry for controlling a starting polarity of frames.
This description relates, generally, to protecting a circuit from an input voltage. Various examples include an apparatus including one or more circuits to draw current from, or provide current to, a pair of connectors for an input circuit. The connectors may be for electrical coupling to first and second terminals of a twisted pair. The one or more circuits may be at least partially responsive to positive and negative biasing signals. The apparatus may additionally include an operational amplifier to generate the positive and negative biasing signals. The operational amplifier may include: a first input terminal at least partially responsive to a reference voltage and a second input terminal at least partially responsive to a common-mode voltage of the input circuit. Related systems and methods are also disclosed.
A metal-insulator-metal (MIM) capacitor includes a bottom electrode cup, an insulator cup, and a top electrode. The bottom electrode cup includes a laterally-extending bottom electrode cup base, and a bottom electrode cup sidewall extending upwardly from the laterally-extending bottom electrode cup base. The insulator cup is formed in an opening defined by the bottom electrode cup, and includes a laterally-extending insulator cup base formed over the laterally-extending bottom electrode cup base, and an insulator cup sidewall extending upwardly from the laterally-extending insulator cup base. A dielectric sidewall spacer is located between the insulator cup sidewall and the bottom electrode cup sidewall. The top electrode is formed in an opening defined by the insulator cup.
A metal-insulator-metal (MIM) capacitor module includes an outer electrode, an insulator, an inner electrode, an outer electrode extension structure, an inner electrode contact element, and an outer electrode contact element. The outer electrode includes a plurality of vertically-extending outer electrode sidewalls. The insulator is formed in an opening defined by the vertically-extending outer electrode sidewalls, and includes a plurality of vertically-extending insulator sidewalls. The inner electrode formed in an interior opening defined by the insulator. The outer electrode extension structure extends laterally from a particular vertically-extending outer electrode sidewall. The inner electrode contact element and outer electrode contact element are formed in a metal layer. The inner electrode contact element is electrically connected to the inner electrode, and the outer electrode contact element is electrically connected to the outer electrode extension structure.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
A low-resistance thick-wire integrated inductor may be formed in an integrated circuit (IC) device. The integrated inductor may include an elongated inductor wire defined by a metal layer stack including an upper metal layer, middle metal layer, and lower metal layer. The lower metal layer may be formed in a top copper interconnect layer, the upper metal layer may be formed in an aluminum bond pad layer, and the middle metal layer may comprise a copper tub region formed between the aluminum upper layer and copper lower layer. The wide copper region defining the middle layer of the metal layer stack may be formed concurrently with copper vias of interconnect structures in the IC device, e.g., by filling respective openings using copper electrochemical plating or other bottom-up fill process. The elongated inductor wire may be shaped in a spiral or other symmetrical or non-symmetrical shape.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
H01F 27/32 - Insulating of coils, windings, or parts thereof
An electronic device may have a plurality of defined life cycle stages and a one-time-programmable (OTP) memory comprising a plurality of life cycle bits, wherein respective bit patterns of the life cycle bits may correspond with respective life cycle stages of the defined life cycle stages. The electronic device may also have a boot code stored in read only memory and executable by a processor to receive a request to transition from a current life cycle stage to a next life cycle stage and, in response to the received request, automatically generate a bit pattern corresponding to the next life cycle stage of the plurality of defined life cycle stages and program the bit pattern corresponding to the next life cycle stage of the plurality of defined life cycle stages in the OTP memory during a time when the OTP memory is not user-accessible.
G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
G06F 3/06 - Digital input from, or digital output to, record carriers
74.
INTEGRATED CIRCUIT BOND PAD WITH MULTI-MATERIAL TOOTHED STRUCTURE
An integrated circuit device may include a multi-material toothed bond pad including (a) an array of vertically-extending teeth formed from a first material, e.g., aluminum, and (b) a fill material, e.g., silver, at least partially filling voids between the array of teeth. The teeth may be formed by depositing and etching aluminum or other suitable material, and the fill material may be deposited over the array of teeth and extending down into the voids between the teeth, and etched to expose top surfaces of the teeth. The array of teeth may collectively define an abrasive structure. The multi-material toothed bond pad may be bonded to another bond pad, e.g., using an ultrasonic or thermosonic bonding process, during which the abrasive teeth may abrade, break, or remove unwanted native oxide layers formed on the respective bond pad surfaces, to thereby create a direct and/or eutectic bonding between the bond pads.
A device having a digital-to-analog converter (DAC) data generator circuit to perform a function upon an event and generate digital DAC data based on the function and the event, and a DAC circuit to generate an analog waveform signal from the digital DAC data.
One or more examples relate to a method, which includes sending, from a provisioner WiFi device to a provisionee WiFi device in an idle mode, a probe request frame including a random data in a custom data field; powering up the provisionee WiFi device in a SoftAp mode at least partially responsive to receiving the probe request frame; sending, from the provisioner WiFi device to the provisionee WiFi device in the SoftAp mode, a further probe request frame including the random data in a custom data field; sending, from the provisionee WiFi device in the SoftAp mode to the provisioner WiFi device, a probe response frame; establishing a secure WiFi connection between the provisioner WiFi device and the provisionee WiFi device utilizing passphrases respectively generated by the provisioner WiFi device and the provisionee WiFi device; and sending provisioning data, from the provisioner WiFi device to the provisionee WiFi device in SoftAp mode, via the secure WiFi connection.
H04L 9/06 - Arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for blockwise coding, e.g. D.E.S. systems
77.
Security of Embedded Devices Through a Device Lifecycle with a Device Identifier
An apparatus includes a database with device profiles, and a device programmer. The device programmer includes instructions. The instructions, when read and executed by a processor, cause the device programmer to identify a device identifier of an electronic device. The device programmer is further caused to, based upon the device identifier, access device data from the database. The device programmer is further caused to, based upon the device data, determine an area of memory of the electronic device that can be written. The device programmer is further caused to, based on the determination of the area of memory of the electronic device that can be written, write data to the area of memory.
A system and method of testing an integrated circuit provide a first clock signal to a first flip-flop with an output to a functional circuit, provide a second clock signal to a second flip-flop with an input from the functional circuit, wherein the second flip-flip has a minimum hold time, provide a test input to the first flip-flop, observe a signal propagation time through the functional circuit, determine the signal propagation time is less than the minimum hold time of the second flip-flop, and increasing a timing separation by adding a unit of delay to the first clock signal or subtracting a unit of delay from the second clock signal.
One or more examples relate to an apparatus to switch data based on a bus identifier and a device identifier. Such an apparatus may include an upstream port for a respective peripheral component interconnect express (PCIe)-compliant communicative connection with a host; a downstream port for a respective PCIe-compliant communicative connection with an endpoint; and a switching logic. The switching logic may store a bus identifier and a device identifier for the endpoint; and switch data at least partially responsive to the bus identifier and the device identifier of the endpoint.
An electronic device includes a transaction host, first and second peripherals, memory, an access control register, and first and second access controllers. The memory stores access control identifier management instructions, a first task related to the first peripheral, and a first bitmask indicating respective access settings for the first and second peripherals for performing the first task. The access control register includes a first access control identifier for the first peripheral and a second access control identifier for the second peripheral. The transaction host executes the access control identifier management instructions to program the first and second access control identifiers based on the first bitmask, and subsequently executes the first task. The first and second access controllers control access to the first and second peripherals, respectively, based on the respective first and second access control identifiers programmed based on the first bitmask.
G06F 21/62 - Protecting access to data via a platform, e.g. using keys or access control rules
G06F 13/10 - Program control for peripheral devices
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
81.
Calibration of Sine-Cosine Coil Mismatches in Inductive Sensors
An apparatus includes a sampling circuit to sample input from a sensor circuit. The input includes a cosine coil waveform and a sine coil waveform. The sampling circuit is to generate a cosine coil sampled data stream and a sine coil sampled data stream. The apparatus includes an adjustment circuit to, based upon a characterization of the sensor circuit, delay the cosine coil sampled data stream or the sine coil sampled data stream.
G01D 18/00 - Testing or calibrating apparatus or arrangements provided for in groups
G01D 5/20 - Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using electric or magnetic means influencing the magnitude of a current or voltage by varying inductance, e.g. by a movable armature
G01B 7/00 - Measuring arrangements characterised by the use of electric or magnetic techniques
82.
REDUCING ERROR IN ESTIMATED ANGULAR POSITION OF A ROTOR OF A MOTOR
Object detection for wireless power transmitters and related systems, methods, and devices are disclosed. A controller for a wireless power transmitter is configured to receive a measurement voltage potential responsive to a tank circuit signal at a tank circuit, provide an alternating current (AC) signal to each of the plurality of transmit coils one at a time, and determine at least one of a resonant frequency and a quality factor (Q-factor) of the tank circuit responsive to each selected transmit coil of the plurality of transmit coils. The controller is also configured to select a transmit coil to use to transmit wireless power to a receive coil of a wireless power receiver responsive to the determined at least one of the resonant frequency and the Q-factor for each transmit coil of the plurality of transmit coils.
H02J 50/60 - Circuit arrangements or systems for wireless supply or distribution of electric power responsive to the presence of foreign objects, e.g. detection of living beings
H02J 50/12 - Circuit arrangements or systems for wireless supply or distribution of electric power using inductive coupling of the resonant type
H02J 50/40 - Circuit arrangements or systems for wireless supply or distribution of electric power using two or more transmitting or receiving devices
G01R 27/26 - Measuring inductance or capacitance; Measuring quality factor, e.g. by using the resonance method; Measuring loss factor; Measuring dielectric constants
An EtherCAT device is disclosed. The EtherCAT device comprises a data input port to receive a signal representing data, the signal representing one of a plurality of possible logical values; and a degradation calculation circuit. The degradation calculation circuit is to read, demodulate, and convert the received signal into a digital domain representation; process the digital domain representation into slices, where the value of the received signal at a respective time is represented in a respective one of the slices; determine differences between the respective slices and reference slices; identify an intended logical value of the received signal responsive to the determined differences; determine a quantification of error at the respective time responsive to the identified logical value and the determined differences; and determine a signal quality index responsive to the determined quantification of error.
An EtherCAT device with a node for use in an EtherCAT network is disclosed. The EtherCAT device includes: a clock circuit; a clock input to receive an input clock signal; a clock output to send an output clock signal; and control logic. The control logic is to determine whether to operate the EtherCAT device in a clock generation mode or a clock propagation mode, wherein in the clock generation mode, the clock circuit is to drive an oscillator to generate the input clock signal; and in the clock propagation mode, the clock circuit is to receive the input clock signal from another node in the EtherCAT network. The control logic is further to control the clock circuit to output the output clock signal for a subsequent node in the EtherCAT network based upon the input clock signal.
A charge pump cell for a charge pump is disclosed that may exhibit improved latch-up immunity. A circuit may be arranged at the charge pump cell to apply a voltage to a bulk contact of a charge transfer transistor of such a charge pump cell at least partially responsive to a relationship between a voltage at a first terminal of the charge transfer transistor and a voltage at a second terminal of the charge transfer transistor. A charge pump including one or more such charge pump cells may include a control loop that is configured to control a pumping signal at least partially responsive to a state of an output voltage of the charge pump.
H02M 3/07 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
87.
PARALLELED TRANSISTOR CELLS OF POWER SEMICONDUCTOR DEVICES
An apparatus is disclosed that includes a common drain, a common source, and a common gate, respectively, of the power semiconductor device, and paralleled transistor cells of the power semiconductor device. In various examples, a configuration of a gate structure of a first respective transistor cell coupled with the common gate is different than a configuration of a gate structure of a second respective transistor cell coupled with the common gate. Alternatively or additionally, in various examples, a configuration of a structure coupled between a first portion of the paralleled transistor cells and the common gate is different than a configuration of a structure coupled between the second portion of the paralleled transistor cells and the common gate.
H03K 3/012 - Modifications of generator to improve response time or to decrease power consumption
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
88.
ELECTRONIC DEVICE INCLUDING ACCESS CONTROL IDENTIFIERS FOR CONTROLLING ACCESS TO PERIPHERALS
An electronic device includes a transaction host, a first peripheral, a second peripheral, a first access controller connected to the first peripheral, a second access controller connected to the second peripheral, and an access control register storing a first access control identifier for the first peripheral and a second access control identifier for the second peripheral. The first access controller to receive an access request for access to the first peripheral by the transaction host, perform an access determination for the first peripheral based at least on the first access control identifier for the first peripheral, and allow or prevent the transaction host access to the first peripheral based on the access determination.
An apparatus and method including a command input to receive a command with a macro identifier from a channel processor, a macro memory storing a plurality of flash control commands, each comprising a duration and a plurality of target control values to control a flash target; and a second finite state machine comprising a plurality of control outputs each corresponding control inputs on the flash target, wherein in response to a received command, the first finite state machine locates in the macro memory a sequence of flash control commands associated with the macro identifier and sequentially outputs the flash control commands to the second finite state machine; and wherein the second finite state machine drives each of the plurality of control outputs based on corresponding values in the first flash control command for the duration specified in the current flash control command.
Some examples may relate to an object-recognition system. The object-recognition system may generate an object identifier when an object having detectable elements in a predetermined spatial pattern is in proximity to a capacitive sensor. The object-recognition system may include a capacitive sensor and a reader to capture channel-capacitance measurements at least partially responsive to the capacitive sensor in proximity of the detectable elements. The object-recognition system may include a recognizer to generate an object identifier at least partially responsive the captured channel-capacitance measurements.
G06F 3/044 - Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
H04L 9/32 - Arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system
G06F 3/041 - Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
91.
METAL-INSULATOR-METAL (MIM) CAPACITOR MODULE INCLUDING A CUP-SHAPED STRUCTURE WITH A ROUNDED CORNER REGION
A metal-insulator-metal (MIM) capacitor includes a bottom electrode cup, an insulator, and a top electrode. The bottom electrode cup includes a laterally-extending bottom electrode cup base and a bottom electrode cup sidewall extending upwardly from the laterally-extending bottom electrode cup base. The insulator includes an insulator cup formed in an opening defined by the bottom electrode cup, and a rounded insulator flange extending laterally outwardly and curving upwardly from the insulator cup, the rounded insulator flange covering an upper surface of the bottom electrode cup sidewall. The top electrode is formed in an opening defined by the insulator cup. The top electrode is insulated from the upper surface of the bottom electrode cup sidewall by the rounded insulator flange.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
92.
METAL-INSULATOR-METAL (MIM) CAPACITOR INCLUDING AN INSULATOR CUP AND LATERALLY-EXTENDING INSULATOR FLANGE
A metal-insulator-metal (MIM) capacitor includes a bottom electrode cup, an insulator, and a top electrode. The bottom electrode cup includes a laterally-extending bottom electrode cup base and a bottom electrode cup sidewall extending upwardly from the laterally-extending bottom electrode cup base. The insulator includes an insulator cup formed in an opening defined by the bottom electrode cup, and an insulator flange extending laterally outwardly from the insulator cup sidewall and extending laterally over an upper surface of the bottom electrode cup sidewall. The top electrode is formed in an opening defined by the insulator cup. The top electrode is insulated from the upper surface of the bottom electrode cup sidewall by the insulator flange.
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
Examples may include an apparatus including a circuit coupled between a supply line, a return line, and a terminal. The circuit may provide an oscillating signal to the terminal. The circuit may include a first switch to couple the supply line with the terminal. The circuit may also include a second switch to couple the return line with the terminal. The circuit may also include a first inductor coupled between the first switch and the terminal. The circuit may also include a second inductor coupled between the second switch and the terminal. The circuit may also include a first diode coupled between the return line and an internal node of the first switch and the first inductor. The circuit may also include a second diode coupled between the supply line and an internal node of the second switch and the second inductor. Related systems and methods are also disclosed.
H02P 27/06 - Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using dc to ac converters or inverters
H02M 7/537 - Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
94.
CIRCUITRY FOR AUTONOMOUSLY MEASURING ANALOG SIGNALS AND RELATED SYSTEMS, METHODS, AND DEVICES
Analog signal measurement and related apparatus, systems, and methods are disclosed. Such an apparatus may include a signal analyzing circuitry to enable responsive to the assertion of the first enable signal, compare the amplified analog input signal to one or more threshold values responsive to the assertion of the second enable signal, and generate an alert signal responsive to a determination that the amplified analog input signal falls outside of the one or more threshold values.
An apparatus may comprise an off-chip data storage device and a semiconductor device package including processing circuitry and an on-chip memory device, the off-chip data storage device including master data and portions of the computer-readable instructions. The processing circuitry may retrieve a master data that includes a digital signature that may be used to verify the master data and a hash table that may include hash information for others of the portions. The processing circuitry may also verify the master instructions responsive to the digital signature, retrieve a portion, calculate a hash value of the retrieved portion, and determine whether the calculated hash value correlates to hash information of the hash table.
An article of manufacture includes a non-transitory machine-readable medium. The medium includes instructions that cause a processor to execute a shift instruction. The shift instruction is to cause a source data in memory to be shifted left or shifted right. The shift instruction is to include a source parameter and a bit size parameter. The processor is to execute the shift instruction through a shift of a first source word of the source data by the bit size parameter to yield a first intermediate word, a shift of a second source word of the source data by the bit size parameter to yield a second intermediate word and a first set of shifted-out bits, and through execution of a logical OR operation on the first intermediate word and the first set of shifted-out bits to yield a first result word.
An article of manufacture includes a non-transitory machine-readable medium. The medium includes instructions. The instructions, when read and executed by a processor, cause the processor to determine that a first input instruction in a code stream to be executed is to perform a read-modify-write operation, determine that the first input instruction is to target a memory location, and, based on a determination that the first input instruction is to perform the read-modify-write operation and the determination that the first input instruction is to target the memory location, convert the first input instruction to a second input instruction to target the memory location with a mask to cause an atomic operation to implement the read-modify-write operation.
A computer system includes a non-transitory computer-readable memory to store (a) a vector table including an exception vector pointing to an exception handler and (b) a vector fail address of a vector fetch bus error handler, and a processor to identify an exception, initiate an exception vector fetch in response to the identified exception to read the exception vector from the vector table, identify a vector fetch bus error associated with the exception vector fetch, access the vector fail address of the vector fetch bus error handler in response to the vector fetch bus error, and execute the vector fetch bus error handler.
One or more examples relate, generally, to an apparatus. The apparatus includes a charged particle source and a charged particle pointer. The charged particle pointer urges charged particles emitted by the charged particle source in a predetermined direction. The charged particle pointer comprises a repeller, and an isolator positioned along a path extending from the repeller in the predetermined direction.
A system includes non-transitory computer readable memory and a processor. The non-transitory computer readable memory stores a current processor interrupt priority level and a current disable interrupt control (DISICTL) interrupt priority level. The processor to update the current processor interrupt priority level based on respective interrupt priority levels associated with respective exceptions, and update the current DISICTL interrupt priority level based on a respective DISICTL instruction, wherein the respective DISICTL instruction specifies a respective user-definable DISICTL interrupt priority level. The processor determines a highest interrupt priority level between the current processor interrupt priority level and the current DISICTL interrupt priority level, and apply the highest interrupt priority level during execution of respective code.