A wire bonding method and a wire bonding device are presented. The wire bonding method bonds a wire to form a bonding wire by using a bonding capillary which leads a wire, detects a defect occurring in a first tail of the wire, bonds the first tail of the wire to a discard lead, separates the first tail of the wire bonded to the discard lead from the wire, and guides a second tail to the separated wire. Wire bonding is performed again by using the wire to which the second tail is guided. A wire bonding device is configured to perform the wire bonding method.
The present invention relates to a semiconductor thin film-forming metal precursor compound represented by chemical formula 1 and a metal-containing thin film formed using same.
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
C23C 16/18 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the deposition of metallic material from metallo-organic compounds
C23C 16/448 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for generating reactive gas streams, e.g. by evaporation or sublimation of precursor materials
C07F 5/00 - Compounds containing elements of Groups 3 or 13 of the Periodic System
The present application relates to a niobium precursor compound, a film-forming precursor composition comprising the niobium precursor compound, and a method for forming a niobium-containing film by using the film-forming precursor composition.
C23C 16/18 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the deposition of metallic material from metallo-organic compounds
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
C07F 9/00 - Compounds containing elements of Groups 5 or 15 of the Periodic System
A method for supplying an object is disclosed. The method for supplying an object may comprise: a step in which a first elevator structure supplies a new magazine, in which the object is accommodated, to one side of the X-axis of a second tray; a step in which a conveyor unit of the second tray moves the new magazine accommodating the object to the other side of the X-axis of the second tray; a step in which a second elevator structure supplies the object to an manufacturing apparatus by holding the new magazine accommodating the object that has been moved to the other side of the X-axis of the second tray by means of the conveyor unit of the second tray.
H01L 21/677 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for conveying, e.g. between different work stations
An automatic pad replacement apparatus is disclosed. The automatic pad replacement apparatus comprises: a first pad carrier having a first loading part in which a pad detachably coupled to the lower end portion of a picker is loaded, and first through-hole parts which allow communication with the first loading part and which are formed through one side thereof in a Z-axis direction; and a gas applying part for suctioning, toward the first loading part, the pad loaded in the first loading part by applying vacuum pressure through the first through-hole parts.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
6.
TABLE MODULE AND APPARATUS FOR AUTOMATICALLY EXCHANGING CONVERSION KIT
Disclosed is a table module. The table module comprises: a conversion kit in which a plurality of vacuum holes are formed in a Z-axis direction; and a table negative pressure transfer plate structure which has the conversion kit disposed on the other surface in the Z-axis direction, and which allows a negative pressure generator and the vacuum holes to communicate with each other. The table negative pressure transfer plate structure can vacuum suction the conversion kit. While the table negative pressure transfer plate structure is vacuum suctioning the conversion kit, the conversion kit is fixed to the table negative pressure transfer plate structure. When the vacuum suctioning of the conversion kit by the table negative pressure transfer plate structure is stopped, the conversion kit can be removed from the table negative pressure transfer plate structure.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 21/677 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for conveying, e.g. between different work stations
7.
FIELD-BIASED NONLINEAR OPTICAL METROLOGY USING CORONA DISCHARGE SOURCE
Various approaches can be used to interrogate a surface such as a surface of a layered semiconductor structure on a semiconductor wafer. Certain approaches employ Second Harmonic Generation while other utilize four wave-mixing or multi-wave mixing. Corona discharge may be applied to the sample to provide additional information. Some approaches involve determining current flow from a sample illuminated with radiation.
G01N 21/95 - Investigating the presence of flaws, defects or contamination characterised by the material or shape of the object to be examined
G01N 21/63 - Systems in which the material investigated is excited whereby it emits light or causes a change in wavelength of the incident light optically excited
H01L 21/66 - Testing or measuring during manufacture or treatment
8.
IMAGE SYNCHRONIZATION DEVICE AND IMAGE INFORMATION GENERATING DEVICE COMPRISING SAME
An image synchronization device according to one embodiment of the present invention comprises: a light-emitting source for emitting light at predetermined intervals; a sampling phase control unit for controlling sampling phases of a first image sensor and a second image sensor on the basis of light-emission timing of the light-emitting source; and a delay control unit for generating delay information on the basis of a result obtained by comparing first image information and second image information that the first image sensor and the second image sensor transmit by sensing and sampling a light-emitting signal of the light-emitting source.
H04N 5/341 - Extracting pixel data from an image sensor by controlling scanning circuits, e.g. by modifying the number of pixels having been sampled or to be sampled
A semiconductor system, according to an embodiment of the present invention, comprises: a first semiconductor device connected to a first transmission line, and for transmitting a first packet to a second transmission line on the basis of first destination information of the first packet received via the first transmission line; a second semiconductor device connected to the first semiconductor device via the second transmission line, and for transmitting a second packet to a third transmission line on the basis of second destination information of the second packet received via the second transmission line; and a third semiconductor device connected to the second semiconductor device via the third transmission line and connected to the first semiconductor device via the first transmission line, and for transmitting a third packet to the first transmission line on the basis of third destination information of the third packet received via the third transmission line.
Disclosed are a transmitter which requires only a low cost and a small area and can eliminate switching noise, and a data transmission method therefor. The transmitter comprises: an encoder for converting two-level input data (1 and 0) into three-level data (+1, 0, and -1); and an output unit for outputting the data converted by the encoder. Here, the encoder adds one bit to the input data so that the number of bits corresponding to logic "1" is adjusted to an even number. Also, "+1" and "-1" corresponding to the logic "1" are alternately arranged, and a particular correlation is established between currents or voltages corresponding to at least two levels among the levels "+1", "0", and "-1" so as to allow a current flowing through a power line or a ground line to be constant regardless of the input data.
G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
According to one embodiment, a semiconductor memory device comprises a first bank and a second bank. Each of the first bank and the second bank comprises a memory cell having a variable resistor element, a reference cell, a sense amplifier having a first input terminal electrically coupled to the memory cell and a second input terminal electrically coupled to the reference cell, and a first transistor electrically coupling the memory cell and the first input terminal of the sense amplifier. A gate of the first transistor of the first bank and a gate of the first transistor of the second bank are independently supplied with a voltage.
G11C 11/15 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements using multiple magnetic layers
According to an embodiment, a resistance change memory includes a semiconductor substrate, a transistor having a control terminal, a first terminal and a second terminal, the transistor provided on the semiconductor substrate, an insulating layer covering the transistor, a first conductive line connected to the first terminal and provided on the insulating layer, a second conductive line provided on the insulating layer, and a resistance change element connected between the second terminal and the second conductive line. The first conductive line has a width greater than a width of the second conductive line in a direction in which the first and second conductive lines are arranged.
G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
G11C 11/15 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements using multiple magnetic layers
H01L 27/105 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
13.
WAFER PROCESSING SYSTEM AND WAFER PROCESSING METHOD USING SAME
A wafer processing system and a wafer processing method are disclosed. A semiconductor manufacturer is provided with a wafer comprising a wafer ID assigned by a wafer manufacturer. Next, the wafer ID is mapped as a wafer unique identification code of the semiconductor manufacturer, and then the wafer ID is identified as the wafer unique identification code without the need to form a separate laser mark.
According to one embodiment, a magnetic memory includes a first metal layer including a first metal, a second metal layer on the first metal layer, the second metal layer including a second metal which is more easily oxidized than the first metal, the second metal layer having a first sidewall portion which contacts the first metal layer, and the second metal layer having a second sidewall portion above the first sidewall portion, the second sidewall portion which steps back from the first sidewall portion, a magnetoresistive element on the second metal layer, a third metal layer on the magnetoresistive element, and a first material which contacts a sidewall portion of the magnetoresistive element and the second sidewall portion of the second metal layer, the first material including an oxide of the second metal.
H01L 27/105 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
According to one embodiment, there is provided a magnetoresistive element, including a first magnetic layer, a nonmagnetic layer on the first magnetic layer, and a second magnetic layer on the nonmagnetic layer, wherein one of the first and second magnetic layers include one of Co and Fe, and a material having a higher standard electrode potential than Co and Fe.
H01L 27/105 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
H01L 29/82 - Types of semiconductor device controllable by variation of the magnetic field applied to the device
A semiconductor memory device is capable of executing a first mode having a first latency and a second mode having a second latency longer than the first latency. The semiconductor memory device includes: a pad unit configured to receive an address and a command from an outside; a first delay circuit configured to delay the address by a time corresponding to the first latency; a second delay circuit including shift registers connected in series and configured to delay the address by a time corresponding to a difference between the first latency and the second latency; and a controller configured to use the first delay circuit and the second delay circuit when executing the second mode.
G11C 11/15 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements using multiple magnetic layers
G11C 7/00 - Arrangements for writing information into, or reading information out from, a digital store
G11C 8/00 - Arrangements for selecting an address in a digital store
17.
MISCORRECTION DETECTION FOR ERROR CORRECTING CODES
Miscorrection detection for error correction codes using bit reliabilities is disclosed, including: receiving a plurality of reliabilities corresponding to respective ones of a plurality of read values; receiving one or more proposed corrections corresponding to one or more of the plurality of read values; and determining a miscorrection metric based at least in part on one or more of the plurality of reliabilities corresponding to the one or more of the plurality of read values.
H03M 13/00 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
A system comprises a component syndrome buffer, and a component decoder configured to obtain, from the component syndrome buffer, a set of one or more component syndromes associated with a turbo product code (TPC) codeword and perform component decoding on the set of one or more component syndromes.
H03M 13/03 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
19.
NEIGHBOR BASED AND DYNAMIC HOT THRESHOLD BASED HOT DATA IDENTIFICATION
An address is received. One or more neighbors associated with the received address is/are determined. One or more neighboring hot metrics is/are determined for the one or more neighbors associated with the received address. A hot metric for the received address is determined based at least in part on the neighboring hot metrics.
According to one embodiment, a memory includes a memory cell array with banks, each bank including rows, a first word lines provided in corresponding to the rows, an address latch circuit which latches a first row address signal, a row decoder which activates one of the first word lines, and a control circuit which is configured to execute a first operation which activates one of the banks based on a bank address signal when a first command is loaded, and a second operation which latches the first row address signal in the address latch circuit, and execute a third operation which activates one of the first word lines by the row decoder based on a second row address signal and the first row address signal latched in the address latch circuit when a second command is loaded after the first command.
G11C 11/15 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements using multiple magnetic layers
According to one embodiment, a resistance change memory includes a memory cell, a sense amplifier and a global bit line. The memory cell is disposed at a location where a local bit line and a word line intersect each other. The memory cell is connected to both the local bit line and the word line. The sense amplifier reads data stored on the memory cell by supplying a read current to the memory cell. The global bit line is connected between the local bit line and the sense amplifier. The global bit line feeds the read current supplied by the sense amplifier to the local bit line. The sense amplifier charges the global bit line, before the local bit line and the global bit line are connected to each other.
G11C 11/15 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements using multiple magnetic layers
G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
22.
GENERATION OF A COMPOSITE READ BASED ON NEIGHBORING DATA
A victim group of one or more cells is read using a first read threshold to obtain a first raw read which includes one or more values. The victim group of cells is read using a second read threshold to obtain a second raw read which includes one or more values. A neighboring read, corresponding to a neighboring group of one or more cells associated with the victim group of cells, is obtained. A composite read is generated, including by selecting from at least the first raw read and the second raw read based at least in part on the neighboring read.
G11C 11/34 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
23.
COBALT (CO) AND PLATINUM (PT)-BASED MULTILAYER THIN FILM HAVING INVERTED STRUCTURE AND METHOD FOR MANUFACTURING SAME
The present invention relates to a cobalt (Co) and platinum (Pt)-based multilayer thin film having a novel structure with perpendicular magnetic anisotropy and to a method for manufacturing same. More particularly, the present invention relates to a perpendicular magnetic anisotropic multilayer thin film having an inverted structure, comprising cobalt thin film layers and platinum thin film layers alternately stacked on a substrate, wherein the thickness of the cobalt thin film layers is greater than that of the platinum thin film layers. The cobalt and platinum-based multilayer thin film having an inverted structure according to the present invention has a novel structure in that the thickness of a magnetic thin film layer is greater than that of a non-magnetic thin film layer, and the size of perpendicular magnetic anisotropic energy is adjusted according to the thickness of the thin film to thus enable the thin film to be applied as a free layer and a fixed layer in a magnetic tunnel junction structure. The thin film of the present invention provides superior thermal stability to thus maintain high perpendicular magnetic anisotropic energy density even after a subsequent heat treatment process, and promotes formation of in-plane magnetic anisotropy to provide the effects of reducing the density of critical current required for magnetization switching, and therefore, the thin film of the present invention can be used effectively in a high performance high density magnetic random access memory.
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