Abstract

An embodiment of the present disclosure relates to a semiconductor apparatus comprising: a first memory cell layer including a first select line extending in a first direction, a second select line extending in a second direction, and a first memory cell connected to the first select line and the second select line; a second memory cell layer provided over the first memory cell layer and including a third select line extending in the first direction, a fourth select line extending in the second direction, and a second memory cell connected to the third select line and to the fourth select line; and a first wiring layer provided between the first memory cell layer and the second memory cell layer and including a first metal wire.

IPC Classes  ?

• H01L 27/105 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
• H01L 21/8239 - Memory structures
• H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof

Abstract

A ferromagnetic resonance (FMR) measurement system is disclosed with a waveguide transmission line (WGTL) connected at both ends to a mounting plate having an opening through which the WGTL is suspended. While the WGTL bottom surface contacts a portion of magnetic film on a whole wafer, a plurality of microwave frequencies is sequentially transmitted through the WGTL. Simultaneously, a magnetic field is applied to the contacted region thereby causing a FMR condition in the magnetic film. After RF output is transmitted through or reflected from the WGTL to a RF detector and converted to a voltage signal, effective anisotropy field, linewidth, damping coefficient, and/or inhomogeneous broadening are determined based on magnetic field intensity, microwave frequency and voltage output. A plurality of measurements is performed by controllably moving the WGTL or wafer and repeating the simultaneous application of microwave frequencies and magnetic field at additional preprogrammed locations on the magnetic film.

IPC Classes  ?

• G01N 24/08 - Investigating or analysing materials by the use of nuclear magnetic resonance, electron paramagnetic resonance or other spin effects by using nuclear magnetic resonance
• G01R 33/30 - Sample handling arrangements, e.g. sample cells, spinning mechanisms
• G01R 31/3185 - Reconfiguring for testing, e.g. LSSD, partitioning
• G01R 31/315 - Contactless testing by inductive methods
• H01L 21/66 - Testing or measuring during manufacture or treatment

Abstract

A phase change material for use in a phase change memory device comprises germanium-antimony-tellurium-indium, wherein the phase change material comprises in total more than 30 at% antimony, preferably 5-16 at% germanium, 30-60 at% antimony, 25-51 at% tellurium, and 2-33% at% indium.

IPC Classes  ?

• H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof

Abstract

A memory cell (100) comprising a transistor, the transistor comprising a substrate (101), a first source/drain region (102), a second source/drain region (112), a gate (104) and a gate insulating layer (103) positioned between the substrate (101) and the gate (104), wherein the gate insulating layer (103) is in a direct contact with the substrate (101) and comprises charge traps (131) distributed over an entire volume of the gate insulating layer (101).

IPC Classes  ?

• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
• H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor

Abstract

Materials, methods, structures and device including the same can provide a semiconductor device such as an LED using an active region corresponding to a non-polar face or surface of III-V semiconductor crystalline material. In some embodiments, an active diode region contains more non-polar III-V material oriented to a non-polar plane than III-V material oriented to a polar plane. In other embodiments, a bottom region contains more non-polar m-plane or a-plane surface area GaN than polar c-plane surface area GaN facing an active region.

IPC Classes  ?

• H01L 31/12 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof structurally associated with, e.g. formed in or on a common substrate with, one or more electric light sources, e.g. electroluminescent light sources, and electrically or optically coupled thereto

Abstract

A package for an optoelectronic device (e.g., a light emitting device such as a LED) includes a sub-mount including a silicon substrate having a thickness in the range of 350 μm - 700 μm. The optoelectronic device is mounted on a die attach pad on the front-side surface of the substrate. Feed-through metallization in one or more via structures having inclined walls such that the cross section of the via structures becomes narrower in a direction into the substrate from both the front-side and back-side surfaces, electrically couples the die attach pad to a contact pad on the back-side surface of the substrate.

IPC Classes  ?

• H01L 23/498 - Leads on insulating substrates
• H01L 33/62 - Arrangements for conducting electric current to or from the semiconductor body, e.g. leadframe, wire-bond or solder balls

Abstract

A submount for a micro-component includes a semiconductor substrate having a cavity defined in a front-side of the substrate in which to mount the micro-component. The submount also includes a thin silicon membrane portion at a bottom of the cavity and thicker frame portions adjacent to sidewalls of the cavity. The substrate includes an electrically conductive feed-through connection extending from a back-side of the substrate at least partially through the thicker silicon frame portion. Electrical contact between the feed- through connection and a conductive layer on a surface of the cavity is made at least partially through a sidewall of the cavity.

IPC Classes  ?

• H01L 23/13 - Mountings, e.g. non-detachable insulating substrates characterised by the shape
• H01L 23/14 - Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
• H01L 23/498 - Leads on insulating substrates

Abstract

A semiconductor device and a method of manufacturing a gate stack for such a semiconductor device. The device includes a gate stack that has a gate insulation layer provided over a channel region of the device, and a metal layer that is insulated from the channel region by the gate insulation layer. The metal layer contains work function modulating impurities which have a concentration profile that varies along a length of the metal layer from the source region to the drain region. The gate stack has a first effective work function in the vicinity of a source region and/or the drain region of the device and a second, different effective work function toward a centre of the channel region.

IPC Classes  ?

• H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
• H01L 29/49 - Metal-insulator semiconductor electrodes
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

Abstract

Therefore, a method of plating wafer via holes in a wafer is provided. A substrate (200) having a first and second side and a plurality of wafer via holes (210) is provided. Each via hole comprises a first and second end extending between the first and second side. A first seed layer (220) is deposited on the first side of the 5 wafer (200). A foil (250) is applied on the first seed layer (220) of the wafer closing the first ends of the plurality of wafer via holes (210). The second side of the wafer (200) is electro-chemically plated and the foil (250) is removed.

IPC Classes  ?

• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements

Abstract

A phase change memory cell, e.g. a line-cell (2), and fabrication thereof, the cell comprising: two electrodes (6, 8); phase change memory material (10) and a dielectric barrier (12). The dielectric barrier (12) is arranged to provide electron tunnelling, e.g. Fowler-Nordheim tunnelling, to the phase change memory material (10). A contact (15) made of phase change memory material may also be provided. The dielectric barrier (12) is substantially uniform e.g. of substantially uniform thickness, e.g. ≥ 5nm.

IPC Classes  ?

• H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof

Abstract

A Fin FET whose fin (12) has an upper portion (30) doped with a first conductivity type and a lower portion (32) doped with a second conductivity type, wherein the junction (34) between the upper portion (30) and the lower portion (32) acts as a diode; and the FinFET further comprises: at least one layer (26, 28) of high-k dielectric material (for example Si3 N4 ) adjacent at least one side of the fin (12) for redistributing a potential drop more evenly over the diode, compared to if the at least one layer of high-k dielectric material were not present, when the upper portion (30) is connected to a first potential and the lower portion (32) is connected to a second potential thereby providing the potential drop across the junction (34). Examples of the k value for the high-k dielectric material are k ≥ 5, k ≥ 7.5, and k ≥ 20.

IPC Classes  ?

• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 21/336 - Field-effect transistors with an insulated gate

Abstract

Methods and structures are provided for formation of devices, e.g., solar cells, on substrates including, e.g., lattice-mismatched materials, by the use of aspect ratio trapping (ART) and epitaxial layer overgrowth (ELO). In general, in a first aspect, embodiments of the invention may include a method of forming a structure. The method includes forming a first opening in a masking layer disposed over a substrate that includes a first semiconductor material. A first layer, which includes a second semiconductor material lattice-mismatched to the first semiconductor material, is formed within the first opening. The first layer has a thickness sufficient to extend above a top surface of the masking layer. A second layer, which includes the second semiconductor material, is formed on the first layer and over at least a portion of the masking layer. A vertical growth rate of the first layer is greater than a lateral growth rate of the first layer and a lateral growth rate of the second layer is greater than a vertical growth rate of the second layer.

IPC Classes  ?

• H01L 21/20 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
• H01L 31/042 - PV modules or arrays of single PV cells

Abstract

An IR sensor comprises a heat sink substrate (10) having portions (12) of relatively high thermal conductivity and portions (14) of relatively low thermal conductivity and a planar thermocouple layer (16) having a hot junction (18) and a cold junction (20), with the hot junction (18) located on a portion (14) of the heat sink substrate with relatively low thermal conductivity. A low thermal conductivity dielectric layer (22) is provided over the thermocouple layer (16), and has a via (24) leading to the hot junction (18). An IR reflector layer (26) covers the low thermal conductivity dielectric layer (22) and the side walls of the via (24). An IR absorber (30; 30') is within the via. This structure forms a planar IR microsensor which uses a structured substrate and a dielectric layer to avoid the need for any specific packaging. This design provides a higher sensitivity by providing a focus on the thermocouple, and also gives better immunity to gas conduction and convection.

IPC Classes  ?

• G01J 5/12 - Radiation pyrometry, e.g. infrared or optical thermometry using electric radiation detectors using thermoelectric elements, e.g. thermocouples

Abstract

A method of improving electrical interconnections between two electrical elements (510,550) is made available by providing a meta-material overlay (700) in conjunction with the electrical interconnection (530) The meta-material overlay is designed to make the electrical signal propagating via the electrical interconnection to act as though the permittivity and permeability of the dielectric medium within which the electrical interconnection is formed are different than the real component permittivity and permeability of the dielectric medium surrounding the electrical interconnection. In some instances the permittivity and permeability resulting from the meta-material cause the signal to propagate as if the permittivity and permeability have negative values. Accordingly the method provides for electrical interconnections possessing enhanced control and stability of impedance, reduced noise, and reduced loss. Alternative embodiments of the meta- material overlay provide, the enhancements for conventional discrete wire bonds whilst also facilitating single integrated designs compatible with tape implementation.

IPC Classes  ?

• H01L 23/66 - High-frequency adaptations
• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates

Abstract

A wafer-level method of fabricating an opto-electronic component package, in which the opto-electronic component is mounted to a semiconductor wafer (175) having first and second surfaces (118, 119) on opposite sides of the wafer. The method includes etching vias (122) in the first surface (118) of the semiconductor wafer. The first surface and surfaces in the vias are metallized, and the metal is structured to define a thermal pad (124) and to define the anode and cathode contact pads (126). A carrier wafer (130) is attached on the side of the semiconductor wafer having the first surface (118), and the semiconductor wafer is thinned from its second surface (119) to expose the metallization in the vias. Metal is provided on the second surface, and the metal is structured to define a die attach pad (HOa) and additional anode and cathode pads (HOb) for the opto-electronic component (108). The opto-electronic component is mounted on the die attach pad and a protective cover is formed over the opto-electronic component.

IPC Classes  ?

• H01L 33/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof

Abstract

A method of forming a dielectric layer (330) on a further layer (114, 320) of a semiconductor device (300) is disclosed. The method comprises depositing a dielectric precursor compound and a further precursor compound over the further layer (114, 320), the dielectric precursor compound comprising a metal ion from the group consisting of Yttrium and the Lanthanide series elements, and the further precursor compound comprising a metal ion from the group consisting of group IV and group V metals; and chemically converting the dielectric precursor compound and the further precursor compound into a dielectric compound and a further compound respectively, the further compound self-assembling during said conversion into a plurality of nanocluster nuclei (335) within the dielectric layer (330) formed from the first dielectric precursor compound. The nanoclusters may be dielectric or metallicinnature. Consequently, a dielectric layer is formed that has excellent charge trapping capabilities. Such a dielectric layer is particularly suitable for use in semiconductor devices such as non-volatile memories.

IPC Classes  ?

• H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
• C23C 14/08 - Oxides
• C23C 16/40 - Oxides
• H01L 21/314 - Inorganic layers
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/51 - Insulating materials associated therewith

Abstract

The present invention is related toa method for producing a contact (4) through the pre-metal dielectric (PMD) layer (6) of an integrated circuit, between the Front End of Line and the Back End of Line, wherein said PMD layer comprises oxygen, said method comprising the steps of : -producing a hole in the PMD, -depositing a conductive barrier layer (3) at the bottom of the hole, -depositing a CuMn alloy on the bottom and side walls of the hole, -filling the remaining portion of the hole with Cu (4), -performing an anneal step, to form a barrier (5) on the side walls of the hole, said barrier comprising an oxide comprising Mn, -performing a CMP step. The invention is equally related to a device which can be produced by the method of the invention.

IPC Classes  ?

• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
• H01L 23/485 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts