Infineon Technologies Austria AG

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IPC Class
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate 7
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions 5
H01L 29/40 - Electrodes 5
H03K 17/06 - Modifications for ensuring a fully conducting state 4
H01L 21/336 - Field-effect transistors with an insulated gate 3
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Found results for  patents

1.

CASCODE DEVICE WITH ONE OR MORE NORMALLY-ON GATES

      
Application Number EP2023069295
Publication Number 2024/013222
Status In Force
Filing Date 2023-07-12
Publication Date 2024-01-18
Owner INFINEON TECHNOLOGIES AUSTRIA AG (Austria)
Inventor Leong, Kennith Kin

Abstract

A switch device comprises: a first power transistor die that includes a normally-on transistor having at most half a maximum rated drain-to-source voltage as the switch device; a second power transistor die that includes a normally-off transistor having at most half the maximum rated drain-to-source voltage as the switch device, wherein a drain of the normally-off transistor is electrically connected to a source of the normally-on transistor to form a cascode device; a voltage blocking device electrically connected between a gate of the normally-on transistor and a source of the normally-off transistor, and configured to block a portion of the voltage across the switch device when the cascode device is off; and an overvoltage protection device configured to turn off the normally-on transistor when the normally-off transistor turns off, such that the cascode device is actively controlled only by a gate of the normally-off transistor. Additional switch devices embodiments are described.

IPC Classes  ?

  • H03K 17/10 - Modifications for increasing the maximum permissible switched voltage
  • H03K 17/0814 - Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the output circuit
  • H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors

2.

CASCODE-BASED SWITCH DEVICE WITH VOLTAGE CLAMP CIRCUIT

      
Application Number EP2023069533
Publication Number 2024/013326
Status In Force
Filing Date 2023-07-13
Publication Date 2024-01-18
Owner INFINEON TECHNOLOGIES AUSTRIA AG (Austria)
Inventor
  • Leong, Kennith Kin
  • Wappis, Herwig

Abstract

A switch device includes: a first power transistor die including a normally-on power transistor; a second power transistor die including a normally-off power transistor having a drain electrically connected to a source of the normally-on power transistor to form a cascode device; and a capacitor electrically connected between a gate of the normally-on power transistor and a source of the normally-off power transistor. Both power transistors have at most half a maximum rated drain-to-source voltage as the switch device. The second power transistor die further includes a voltage clamp circuit having a normally-off clamp transistor with a drain electrically connected to the gate of the normally-on power transistor and a source electrically connected to the source of the normally-off power transistor, and diode(s) between the drain and a gate of the normally-off clamp transistor. Additional switch devices embodiments are described.

IPC Classes  ?

  • H03K 17/10 - Modifications for increasing the maximum permissible switched voltage
  • H03K 17/0814 - Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the output circuit
  • H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors

3.

MICRO-FABRICATED DEVICE FOR CONTROLLING TRAPPED IONS AND METHOD OF MANUFACTURING THE SAME BY MICRO-FABRICATION

      
Application Number EP2022069423
Publication Number 2023/285443
Status In Force
Filing Date 2022-07-12
Publication Date 2023-01-19
Owner
  • INFINEON TECHNOLOGIES AUSTRIA AG (Austria)
  • EIDGENÖSSISCHE TECHNISCHE HOCHSCHULE - ETH ZÜRICH (Switzerland)
  • UNIVERSITÄT INNSBRUCK (Austria)
Inventor
  • Roessler, Clemens
  • Auchter, Silke
  • Stocker, Gerald
  • Sgouridis, Sokratis
  • Decaroli, Chiara
  • Home, Jonathan
  • Valentini, Marco
  • Colombe, Yves
  • Holz, Philip

Abstract

A device (100) for controlling trapped ions (180) includes a first semiconductor substrate (120) comprising a semiconductor and/ or dielectric material. A first micro-fabricated electrode structure (125) is disposed at a main side of the first substrate (120). The device (100) further includes a second substrate (140) comprising a semiconductor and/or dielectric material. A second micro-fabricated electrode structure (145) is disposed at a main side of the second substrate (140) opposite the main side of the first substrate (120). A plurality of spacer members (160) is disposed between the first substrate (120) and the second substrate (140). At least one ion trap is configured to trap ions (180) in a space between the first substrate (120) and the second substrate (140). The first micro-fabricated electrode structure (125) and the second micro-fabricated electrode structure (145) comprise electrodes of the ion trap. A multi-layer metal interconnect (135) is formed on the first substrate (120) and electrically connected to the first micro-fabricated electrode structure (125).

IPC Classes  ?

  • G21K 1/00 - Arrangements for handling particles or ionising radiation, e.g. focusing or moderating
  • G06N 10/00 - Quantum computing, i.e. information processing based on quantum-mechanical phenomena
  • B82Y 10/00 - Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic

4.

SEMICONDUCTOR DIE WITH A VERTICAL POWER TRANSISTOR DEVICE

      
Application Number EP2022062803
Publication Number 2022/243135
Status In Force
Filing Date 2022-05-11
Publication Date 2022-11-24
Owner INFINEON TECHNOLOGIES AUSTRIA AG (Austria)
Inventor
  • Meiser, Andreas Peter
  • Schloesser, Till
  • Henson, Timothy

Abstract

The disclosure relates to a semiconductor die (1), comprising a vertical power transistor device (2), the vertical power transistor device having a source region (3) and a drain region (4) at opposite sides of a semiconductor body (10), and a lateral transistor device (20), the lateral transistor device having a body region (221) with a lateral channel region (221.1), as well as a source and a drain region formed at a frontside of the semiconductor body, wherein a deep trench (305) is arranged laterally between the vertical power transistor device (2) and the lateral transistor device (20), forming a deep trench isolation (306).

IPC Classes  ?

  • H01L 21/8234 - MIS technology
  • H01L 21/765 - Making of isolation regions between components by field-effect
  • H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
  • H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
  • H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
  • H01L 29/40 - Electrodes
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

5.

HOLE DRAINING STRUCTURE FOR SUPPRESSION OF HOLE ACCUMULATION

      
Application Number EP2022062040
Publication Number 2022/233968
Status In Force
Filing Date 2022-05-04
Publication Date 2022-11-10
Owner INFINEON TECHNOLOGIES AUSTRIA AG (Austria)
Inventor
  • Imam, Mohamed
  • Kim, Hyeongnam

Abstract

A semiconductor structure comprising a hole draining structure (402) are provided. A semiconductor structure has a first layer (102) formed over a substrate (101). The first layer has a first concentration of a metal material. The semiconductor structure has a second layer (106) formed over the first layer. The second layer has a second concentration of the metal material less than the first concentration of the metal material. The semiconductor structure has a hole draining structure formed from a superlattice (103) formed between the first layer and the second layer. The hole draining structure has a concentration of the metal material increasing towards the first layer and decreasing towards the second layer.

IPC Classes  ?

  • H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
  • H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds

6.

ELECTRONIC CIRCUIT WITH A TRANSISTOR DEVICE AND A BIASING CIRCUIT

      
Application Number EP2021055642
Publication Number 2021/176079
Status In Force
Filing Date 2021-03-05
Publication Date 2021-09-10
Owner INFINEON TECHNOLOGIES AUSTRIA AG (Austria)
Inventor
  • Weber, Hans
  • Hirler, Franz
  • Kutschak, Matteo-Alessandro
  • Pippan, Manfred
  • Riegler, Andreas

Abstract

An electronic circuit is disclosed. The electronic circuit includes: a half-bridge with a first transistor device (1) and a second transistor device (1a); a first biasing circuit (3) connected in parallel with a load path of the first transistor device (1) and comprising a first electronic switch (31); a second biasing circuit (3a) connected in parallel with a load path of the second transistor device (1a) and comprising a second electronic switch (31a); and a drive circuit arrangement (DRVC). The drive circuit arrangement (DRVC) is configured to receive a first half-bridge input signal (Sin) and a second half-bridge input signal (Sina), drive the first transistor device (1) and the second electronic switch (31a) based on the first half-bridge input signal (Sin), and drive the second transistor device (1a) and the first electronic switch (31) based on the second half-bridge input signal (Sina).

IPC Classes  ?

  • H03K 17/16 - Modifications for eliminating interference voltages or currents
  • H03K 17/74 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of diodes

7.

TRANSISTOR DEVICE AND METHOD OF FABRICATING A TRANSISTOR DEVICE

      
Application Number EP2020053062
Publication Number 2021/155943
Status In Force
Filing Date 2020-02-07
Publication Date 2021-08-12
Owner INFINEON TECHNOLOGIES AUSTRIA AG (Austria)
Inventor
  • Blank, Oliver
  • Braz, Cesar, Augusto
  • Gao, Yan
  • Guillemant, Olivier
  • Hirler, Franz
  • Laforet, David
  • Lagger, Peter
  • Ouvrard, Cedric
  • Pree, Elias
  • Yip, Li, Juin

Abstract

In an embodiment, a transistor device comprises a semiconductor body comprising a plurality of transistor cells comprising a drift region of a first conductivity type, a body region of a second conductivity type forming a first pn junction with the drift region, the second conductivity type opposing the first conductivity type, a source region of the first conductivity type forming a second pn junction with the body region, a columnar field plate trench extending into a major surface of a semiconductor body and comprising a columnar field plate and a gate trench structure extending into the major surface of the semiconductor body and comprising a gate electrode. At least one of the depth and doping level of the body region locally varies within the transistor cell to improve VGSTH homogeneity within the transistor cell.

IPC Classes  ?

  • H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 21/336 - Field-effect transistors with an insulated gate

8.

SUPERJUNCTION TRANSISTOR DEVICE

      
Application Number EP2021051023
Publication Number 2021/148383
Status In Force
Filing Date 2021-01-19
Publication Date 2021-07-29
Owner INFINEON TECHNOLOGIES AUSTRIA AG (Austria)
Inventor
  • Weber, Hans
  • Hirler, Franz
  • Kutschak, Matteo-Alessandro
  • Riegler, Andreas
  • Fischer, Björn

Abstract

A transistor device is disclosed. The transistor device includes: a semiconductor body (100); a drift region (11) in the semiconductor body (100); a plurality of transistor cells (10); and a gate node (G) and a source node (S), wherein each of the plurality of transistor cells (10) includes: a first trench electrode (21) insulated from the semiconductor body (100) by a first dielectric layer (22); a second trench electrode (23) insulated from the semiconductor body (100) by a second dielectric layer (24); a source region (13) and a body region (14) in a first mesa region (111) between the first trench electrode (21) and the second trench electrode (23); and a compensation region (12), wherein the compensation region (12) adjoins the body region (14), the first dielectric (22), the second dielectric (24), and forms a pn-junction with the drift region (11), and wherein from the first trench electrode (21) and the second trench electrode (23) at least the first trench electrode (21) is connected to the gate node (G).

IPC Classes  ?

  • H03K 17/06 - Modifications for ensuring a fully conducting state

9.

SEMICONDUCTOR DEVICES

      
Application Number EP2020080513
Publication Number 2021/084070
Status In Force
Filing Date 2020-10-30
Publication Date 2021-05-06
Owner INFINEON TECHNOLOGIES AUSTRIA AG (Austria)
Inventor
  • Mahmoud, Ahmed
  • Popescu, Dan Horia
  • Rochel, Markus

Abstract

A semiconductor device, comprises a semiconductor body (100) comprising a first surface (101), a second surface (102) opposite to the first surface (101) in a vertical direction (y), an edge termination region (210), and an active region (220) arranged adjacent to the edge termination region (210) in a horizontal direction. The semiconductor device further comprises a plurality of transistor cells (30) at least partly integrated in the active region (220), each transistor cell (30) comprising a source region (31), a body region (32), and a drift region (35) separated from the source region (31) by the body region (32). The semiconductor device further comprises a gate electrode (33) arranged in the active region (220) and dielectrically insulated from the body regions (32) of the plurality of transistor cells (30), a circumferential electrically conducting layer (60) arranged above the first surface (101) and in the edge termination region (210), and a gate pad (46) electrically coupled to the electrically conductive layer (60). The gate pad (46) partially covers the electrically conducting layer (60), the electrically conducting layer (60) extends around and electrically contacts the gate electrode (33), and a contact between the electrically conductive layer (60) and the gate electrode (33) is completely interrupted along the section of the electrically conductive layer (60) that is covered by the gate pad (46).

IPC Classes  ?

  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/40 - Electrodes
  • H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched

10.

INDUCTOR DEVICES AND IMPLEMENTATIONS

      
Application Number EP2020079095
Publication Number 2021/074322
Status In Force
Filing Date 2020-10-15
Publication Date 2021-04-22
Owner INFINEON TECHNOLOGIES AUSTRIA AG (Austria)
Inventor
  • Kasper, Matthias Joachim
  • Leong, Kennith Kin
  • Peluso, Luca

Abstract

According to one configuration, an inductor device includes a first electrically conductive path (131); a second electrically conductive path (132), the first electrically conductive path electrically isolated from the second electrically conductive path; first material (141), the first material operative to space the first electrically conductive path with respect to the second electrically conductive path; and second material (142). The second material has a substantially higher magnetic permeability than the first material. An assembly of the first electrically conductive path, the second electrically conductive path, and the first material resides in a core of the second material.

IPC Classes  ?

  • H01F 17/06 - Fixed inductances of the signal type with magnetic core with core substantially closed in itself, e.g. toroid
  • H01F 38/00 - Adaptations of transformers or inductances for specific applications or functions
  • H01F 27/32 - Insulating of coils, windings, or parts thereof

11.

USE OF AN ELECTRONIC FUSE AS A DAMPING ELEMENT

      
Application Number EP2020072812
Publication Number 2021/028552
Status In Force
Filing Date 2020-08-13
Publication Date 2021-02-18
Owner INFINEON TECHNOLOGIES AUSTRIA AG (Austria)
Inventor Kirchner, Uwe

Abstract

A method for using an electronic fuse (e-fuse) as a damping element and a system including at least one e-fuse are disclosed.

IPC Classes  ?

  • H03K 17/12 - Modifications for increasing the maximum permissible switched current
  • H02H 3/087 - Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition, with or without subsequent reconnection responsive to excess current for dc applications
  • H03K 17/16 - Modifications for eliminating interference voltages or currents
  • H02H 9/00 - Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
  • H03K 17/082 - Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit

12.

SEMICONDUCTOR DEVICE

      
Application Number EP2020061972
Publication Number 2021/001084
Status In Force
Filing Date 2020-04-29
Publication Date 2021-01-07
Owner INFINEON TECHNOLOGIES AUSTRIA AG (Austria)
Inventor
  • Kahrimanovic, Elvir
  • Noebauer, Gerhard
  • Blank, Oliver
  • Ferrara, Alessandro

Abstract

In some embodiments, a semiconductor device comprises a semiconductor die comprising a vertical transistor device having a source electrode, a drain electrode and a gate electrode, the semiconductor die having a first surface and a second surface opposing the first surface. A first metallization structure is located on the first surface and comprises at least one source pad coupled to the source electrode, at least one drain pad coupled to the drain electrode and at least one gate pad coupled to the gate electrode. A second metallization structure is located on the second surface and comprises a conductive structure and an electrically insulating layer and forms an outermost surface of the semiconductor device. The outermost surface of the second metallization structure is electrically insulated from the semiconductor die by the electrically insulating layer.

IPC Classes  ?

  • H01L 23/482 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of lead-in layers inseparably applied to the semiconductor body
  • H01L 23/34 - Arrangements for cooling, heating, ventilating or temperature compensation
  • H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
  • H01L 23/495 - Lead-frames
  • H01L 23/488 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of soldered or bonded constructions
  • H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns

13.

METHOD OF MANUFACTURING SEMICONDUCTOR CHIPS HAVING A SIDE WALL SEALING

      
Application Number EP2020066969
Publication Number 2020/254499
Status In Force
Filing Date 2020-06-18
Publication Date 2020-12-24
Owner INFINEON TECHNOLOGIES AUSTRIA AG (Austria)
Inventor
  • Fachmann, Christian
  • Muri, Ingo

Abstract

A method of manufacturing semiconductor chips having a side wall sealing is described. The method includes forming dicing trenches in a semiconductor wafer. The side walls of the dicing trenches are anodized to generate an anodic oxide layer at the side walls of the dicing trenches. Semiconductor chips are separated from the semiconductor wafer.

IPC Classes  ?

  • H01L 21/24 - Alloying of impurity materials, e.g. doping materials, electrode materials, with a semiconductor body
  • H01L 21/326 - Application of electric currents or fields, e.g. for electroforming
  • H01L 21/784 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, each consisting of a single circuit element the substrate being a semiconductor body

14.

TRANSISTOR ARRANGEMENT

      
Application Number EP2020056018
Publication Number 2020/182658
Status In Force
Filing Date 2020-03-06
Publication Date 2020-09-17
Owner INFINEON TECHNOLOGIES AUSTRIA AG (Austria)
Inventor
  • Weber, Hans
  • Riegler, Andreas
  • Kutschak, Matteo-Alessandro

Abstract

DEPDEPDEPDEPDEP) between the bias node (Q) and a further bias node (R); and a clamping circuit (92) coupled between the bias node (Q) and the source node (S) and configured to clamp a voltage between the bias node (Q) and the further bias node (R) to a clamping voltage level.

IPC Classes  ?

  • H03K 17/06 - Modifications for ensuring a fully conducting state

15.

TRANSISTOR ARRANGEMENT AND ELECTRONIC CIRCUIT WITH A TRANSISTOR ARRANGEMENT

      
Application Number EP2020056196
Publication Number 2020/182721
Status In Force
Filing Date 2020-03-09
Publication Date 2020-09-17
Owner INFINEON TECHNOLOGIES AUSTRIA AG (Austria)
Inventor
  • Weber, Hans
  • Fischer, Björn
  • Hirler, Franz
  • Kutschak, Matteo-Alessandro
  • Riegler, Andreas

Abstract

1111).

IPC Classes  ?

16.

METHOD FOR OPERATING A SUPERJUNCTION TRANSISTOR DEVICE AND SUPERJUNCTION TRANSISTOR DEVICE

      
Application Number EP2020051245
Publication Number 2020/182357
Status In Force
Filing Date 2020-01-20
Publication Date 2020-09-17
Owner INFINEON TECHNOLOGIES AUSTRIA AG (Austria)
Inventor
  • Hirler, Franz
  • Fischer, Björn
  • Kutschak, Matteo-Alessandro
  • Riegler, Andreas
  • Weber, Hans

Abstract

DEPDEPDEPDEPDEP) between a bias region (4) that is coupled to the drift region (11) and the at least one of the compensation region (21) and the body region (22), and wherein the bias region (4) is spaced apart from a body region (22) and a source region (12) of the at least one transistor cell.

IPC Classes  ?

  • H03K 17/06 - Modifications for ensuring a fully conducting state

17.

ACTIVE CLAMP FLYBACK CONVERTER WITH VARIABLE RESONANCE FREQUENCY

      
Application Number EP2019070061
Publication Number 2020/021020
Status In Force
Filing Date 2019-07-25
Publication Date 2020-01-30
Owner INFINEON TECHNOLOGIES AUSTRIA AG (Austria)
Inventor
  • Fontana, Nico
  • Medina-Garcia, Alfredo

Abstract

An active clamp flyback, ACF, converter (600; 610; 700; 710; 720; 900; 1020) comprises a switchable clamp circuit (Lk, S2, Cclamp; Lk,p, S2, Cclamp) arranged on an input side of the ACF converter, and a tank capacitor (Cclamp; Cout) configured to form, in combination with a leakage inductance (Lk; Lk,p, Lk,s) of the ACF converter, a resonator, when the clamp circuit is switched on. The ACF converter further comprises at least one additional capacitor (Cadd), and the resonator is switchable between a first switching state, in which the additional capacitor (Cadd) is connected to the resonator, and a second switching state, in which the additional capacitor (Cadd) is disconnected from the resonator, wherein a capacitance of the resonator is variable dependent on the switching state of the resonator.

IPC Classes  ?

  • H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
  • H02M 3/335 - Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only

18.

POWER SEMICONDUCTOR DEVICE

      
Application Number IB2018051946
Publication Number 2018/172977
Status In Force
Filing Date 2018-03-22
Publication Date 2018-09-27
Owner INFINEON TECHNOLOGIES AUSTRIA AG (Austria)
Inventor
  • Basler, Thomas
  • Bina, Markus
  • Dainese, Matteo
  • Schulze, Hans-Joachim

Abstract

A power semiconductor device (1) comprises a semiconductor body (10) coupled to a first load terminal (11) and a second load terminal (12). The semiconductor body (10) comprises: a first doped region (102) of a second conductivity type electrically connected to the first load terminal (11); an emitter region (1091) of the second conductivity type electrically connected to the second load terminal (12); a drift region (100) of a first conductivity type and arranged between the first doped region (102) and the emitter region (1091). The drift region (100) and the first doped region (102) enable the power semiconductor device (1) to be operated in: a conducting state during which a load current between the load terminals (11, 12) is conducted along a forward direction; in a forward blocking state during which a forward voltage applied between the terminals (11, 12) is blocked; and in a reverse blocking state during which a reverse voltage applied between the terminals (11, 12) is blocked. The semiconductor body (10) further comprises a recombination zone (159) arranged at least within the first doped region (102).

IPC Classes  ?

  • H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
  • H01L 29/861 - Diodes
  • H01L 29/32 - Semiconductor bodies having polished or roughened surface the imperfections being within the semiconductor body
  • H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier

19.

POWER CONVERTER CIRCUIT, POWER SUPPLY SYSTEM AND METHOD

      
Application Number EP2013050763
Publication Number 2013/107782
Status In Force
Filing Date 2013-01-16
Publication Date 2013-07-25
Owner INFINEON TECHNOLOGIES AUSTRIA AG (Austria)
Inventor
  • Deboy, Gerald
  • Tang, Yi

Abstract

Disclosed is a power converter circuit, a power supply system and a method. The power converter circuit (1), comprises • at least one converter series circuit comprising a plurality of converter units (2), the at least one converter series circuit configured to output a series circuit output current (il OUT; i OUT- REC); and • a synchronization circuit (10) configured to generate at least one synchronization signal (S vi), wherein at least one of the plurality of converter units (2) is configured to generate an output current (il) such that at least one of a frequency and a phase of the output current (il) is dependent on the synchronization signal (S vl).

IPC Classes  ?

  • H02J 3/40 - Synchronising a generator for connection to a network or to another generator

20.

LITHIUM BATTERY, METHOD FOR MANUFACTURING A LITHIUM BATTERY, INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT

      
Application Number EP2012004783
Publication Number 2013/075810
Status In Force
Filing Date 2012-11-16
Publication Date 2013-05-30
Owner INFINEON TECHNOLOGIES AUSTRIA AG (Austria)
Inventor
  • Forster, Magdalena
  • Schmut, Katharina
  • Goller, Bernhard
  • Zieger, Günter
  • Sorger, Michael
  • Schweizer, Philemon
  • Sternad, Michael

Abstract

A lithium battery includes a cathode, an anode including a component made of silicon, a separator element disposed between the cathode and the anode, an electrolyte, and a substrate. The anode is disposed over the substrate or the anode is integrally formed with the substrate.

IPC Classes  ?

  • H01M 6/40 - Printed batteries
  • H01M 10/04 - Construction or manufacture in general
  • H01M 10/052 - Li-accumulators
  • H01M 10/0585 - Construction or manufacture of accumulators having only flat construction elements, i.e. flat positive electrodes, flat negative electrodes and flat separators
  • H01M 10/42 - Methods or arrangements for servicing or maintenance of secondary cells or secondary half-cells

21.

METHOD FOR DRIVING A TRANSISTOR AND DRIVE CIRCUIT

      
Application Number DE2011050058
Publication Number 2012/107010
Status In Force
Filing Date 2011-12-20
Publication Date 2012-08-16
Owner
  • INFINEON TECHNOLOGIES AUSTRIA AG (Austria)
  • ZF FRIEDRICHSHAFEN AG (Germany)
Inventor
  • Reiter, Tomas Manuel
  • Kett, Jürgen
  • Doemel, Bernhard

Abstract

A description is given of a method for the pulsed driving of a transistor, which has a drive terminal (G) and a load path (C-E) and the load path of which is connected in series with a load, and a drive circuit for a transistor (1). The method comprises: Driving the transistor with a drive pulse of a first type, which has a first drive level (S21) at least for a first time duration (Tl), before a drive pulse of a second type, which has a second drive level (S22), which is higher in comparison with the first drive level (S21); evaluating a voltage (Vce) across the load path of the transistor (1); terminating the pulsed driving if the voltage (Vce) across the load path exceeds a predefined threshold value.

IPC Classes  ?

  • G01R 31/02 - Testing of electric apparatus, lines, or components for short-circuits, discontinuities, leakage, or incorrect line connection
  • H02H 11/00 - Emergency protective circuit arrangements for preventing the switching-on in case an undesired electric working condition might result
  • H03K 17/082 - Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit

22.

SEMICONDUCTOR DEVICE ARRANGEMENT WITH A FIRST SEMICONDUCTOR DEVICE AND WITH A PLURALITY OF SECOND SEMI CONDUCTOR DEVICES

      
Application Number EP2012050245
Publication Number 2012/093177
Status In Force
Filing Date 2012-01-09
Publication Date 2012-07-12
Owner INFINEON TECHNOLOGIES AUSTRIA AG (Austria)
Inventor
  • Weis, Rolf
  • Hirler, Franz
  • Feldtkeller, Martin
  • Deboy, Gerald
  • Stecher, Matthias
  • Willmeroth, Armin

Abstract

Disclosed is a semiconductor device arrangement including a first semiconductor device having a load path, and a plurality of second transistors, each having a load path between a first and a second load terminal and a control terminal. The second transistors have their load paths connected in series and connected in series to the load path of the first transistor, each of the second transistors has its control terminal connected to the load terminal of one of the other second transistors, and one of the second transistors has its control terminal connected to one of the load terminals of the first semiconductor device.

IPC Classes  ?

  • H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
  • H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 29/40 - Electrodes
  • H01L 27/07 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
  • G05F 1/573 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for protection with overcurrent detector
  • H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
  • H02H 9/02 - Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess current

23.

METHOD FOR TREATING AN OXYGEN-CONTAINING SEMICONDUCTOR WAFER, AND SEMICONDUCTOR COMPONENT

      
Application Number EP2007000475
Publication Number 2007/085387
Status In Force
Filing Date 2007-01-19
Publication Date 2007-08-02
Owner INFINEON TECHNOLOGIES AUSTRIA AG (Austria)
Inventor
  • Schulze, Hans-Joachim
  • Strack, Helmut
  • Mauder, Anton

Abstract

The invention describes a method for treating an oxygen-containing semiconductor wafer which has a first side, a second side which is opposite the first side, a first semiconductor region which adjoins the first side and a second semiconductor region which adjoins the second side, said method having the following method steps: the second side of the wafer is irradiated with high-energy particles, thus producing crystal defects in the second semiconductor region, and a first thermal process in which the wafer is heated to temperatures of between 700°C and 1100°C is carried out. The invention also relates to a component which is produced on the basis of a wafer which has been treated in this manner.

IPC Classes  ?

  • H01L 21/322 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to modify their internal properties, e.g. to produce internal imperfections
  • H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
  • H01L 21/263 - Bombardment with wave or particle radiation with high-energy radiation

24.

METHOD FOR MANUFACTURING A SOLAR CELL, AND SOLAR CELL

      
Application Number EP2006009550
Publication Number 2007/079795
Status In Force
Filing Date 2006-10-02
Publication Date 2007-07-19
Owner INFINEON TECHNOLOGIES AUSTRIA AG (Austria)
Inventor Schulze, Hans-Joachim

Abstract

The invention relates to a method for manufacturing a solar cell which has the following method steps: a monocrystalline semiconductor body is provided which has two opposite sides and basic p doping, protons are implanted into the semiconductor body over a first of the sides such that a number of defect regions arranged at a distance from one another is produced which extend from the one side into the semiconductor body, a curing step is performed in which the semiconductor body is heated at least in the region of the defect regions and its temperature and the duration are chosen such that a number of n doped semiconductor zones arranged at a distance from one another are produced, an n doped emitter is produced which adjoins the n doped semiconductor zones.

IPC Classes  ?

  • H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
  • H01L 31/0288 - Inorganic materials including, apart from doping material or other impurities, only elements of Group IV of the Periodic System characterised by the doping material

25.

SEMICONDUCTOR COMPONENT COMPRISING A P-N JUNCTION, AND METHOD FOR THE PRODUCTION THEREOF

      
Application Number DE2006001848
Publication Number 2007/048387
Status In Force
Filing Date 2006-10-19
Publication Date 2007-05-03
Owner INFINEON TECHNOLOGIES AUSTRIA AG (Austria)
Inventor
  • Mauder, Anton
  • Pfirsch, Frank
  • Schulze, Hans-Joachim
  • Sedlmaier, Stefan
  • Willmeroth, Armin

Abstract

The invention relates to a semiconductor component (1) and a method for producing the same. The semiconductor component (3) comprises a semiconductor member (4) in which a p-n junction is disposed that is provided with a p-conducting region (11) and an n-conducting region (9). The p-conducting region (11) or the n-conducting region (9) of the p-n junction encompasses areas (23) which spatially define the p-n junction within the semiconductor member (4).

IPC Classes  ?

  • H01L 29/861 - Diodes
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 21/336 - Field-effect transistors with an insulated gate
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/165 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form including two or more of the elements provided for in group in different semiconductor regions
  • H01L 29/32 - Semiconductor bodies having polished or roughened surface the imperfections being within the semiconductor body
  • H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes

26.

SEMICONDUCTOR COMPONENT WITH CHARGE COMPENSATION STRUCTURE AND METHOD FOR PRODUCING THE SAME

      
Application Number DE2006001879
Publication Number 2007/048393
Status In Force
Filing Date 2006-10-23
Publication Date 2007-05-03
Owner INFINEON TECHNOLOGIES AUSTRIA AG (Austria)
Inventor
  • Sedlmaier, Stefan
  • Mauder, Anton
  • Pfirsch, Frank
  • Schulze, Hans-Joachim
  • Strack, Helmut
  • Willmeroth, Armin

Abstract

Semiconductor component (1) with charge compensation structure (3) and method for producing the same. For that purpose, the semiconductor component (1) has a semiconductor body (4) with a drift section (5) between two electrodes (6, 7). The drift section (5) comprises drift zones of a first conductivity type forming a current path between the electrodes (6, 7) in the drift section, while charge compensation zones (11) of a complementary conductivity type narrow the current path in the drift section (5). The drift section (5) comprises for that purpose two alternating, epitaxially grown diffusion zone types (9, 10), the first drift zone type (9) having a monocrystalline semiconductor material on a monocrystalline substrate (12), and a second drift zone type (10) having a monocrystalline semiconductor material in a trench structure (13), with walls (14, 15) which have a complementary doping and form the charge compensation zones (11).

IPC Classes  ?

  • H01L 21/336 - Field-effect transistors with an insulated gate
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/267 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups , , , , in different semiconductor regions

27.

SEMICONDUCTOR COMPONENT WITH A DRIFT REGION AND WITH A DRIFT CONTROL REGION

      
Application Number EP2006007450
Publication Number 2007/012490
Status In Force
Filing Date 2006-07-27
Publication Date 2007-02-01
Owner INFINEON TECHNOLOGIES AUSTRIA AG (Austria)
Inventor
  • Pfirsch, Frank
  • Mauder, Anton
  • Schulze, Hans-Joachim
  • Sedlmaier, Stefan
  • Willmeroth, Armin
  • Zundel, Markus
  • Hirler, Franz
  • Mittal, Arunjai

Abstract

The invention relates to a semiconductor component that has a semiconductor body (100) and the following additional features: a drift region (2; 211) of a first mode of conductivity in the semiconductor body (100); a drift control region (3; 241), which is made of a semiconductor material and which is placed, at least in sections, adjacent to the drift region (2) in the semiconductor body, and; an accumulation dielectric (4; 251) that is placed between the drift region (2, 211) and the drift control region (3; 241).

IPC Classes  ?

  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
  • H01L 29/872 - Schottky diodes
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/40 - Electrodes
  • H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration