The present disclosure relates to authenticity and data security for bus-based communication networks in a vehicle. The present disclosure teaches a protocol frame, a sender on data link layer, and a receiver on data link layer providing such authenticity and data security as well as a communication network in a vehicle employing the protocol frame, the sender and the receiver according to the present disclosure.
An optical sensor includes a pixel including a photoactive region configured to convert photons into charge carriers, a first and a second modulation gate configured to be modulated for indirect time of flight measurement, a first and a second storage node arranged on opposite sides of the photoactive region, the first and second storage nodes being configured to pin electrons generated in the photoactive region when the first or the second modulation gate is active, respectively, and a first field plate arranged next to the first storage node and a second field plate arranged next to the second storage node. The first and second field plates are configured to be supplied with a negative bias voltage such that the first and second field plates provide electrical isolation for the first or the second storage node, respectively.
A monitoring system includes: a sensor configured to generate a sensor signal based on a measured property; a controller configured to communicate with the sensor; and a communication channel electrically coupled to the sensor and the controller for carrying electrical communications therebetween. The sensor includes a transmitter configured to transmit an electrical signal on the communication channel to the controller. The controller includes a processing circuit configured to receive the electrical signal, measure an actual signal function response of the electrical signal, correlate the actual signal function response with a reference signal function response to generate a correlation value, compare the correlation value and a correlation threshold to produce a comparison result, and detect a fault based on the comparison result indicating that the correlation value satisfies the correlation threshold.
H04L 67/12 - Protocols specially adapted for proprietary or special-purpose networking environments, e.g. medical networks, sensor networks, networks in vehicles or remote metering networks
G01R 31/52 - Testing for short-circuits, leakage current or ground faults
A method for storing data bits in memory cells, in which the data bits have at least one byte-filling bit, where at least one predefined functionality for a subset of the data bits is coded in the at least one byte-filling bit, and in which the data bits are stored in the memory cells. A method for reading data bits from memory cells, in which the data bits have at least one byte-filling bit, where at least one predefined functionality for a subset of the data bits is coded in the at least one byte-filling bit, and in which the data bits are read from the memory cells based on the coded predefined functionality. Corresponding apparatuses and memories are also disclosed.
A system including circuitry to communicate data across an isolation barrier of a switch driver circuit. For switch driver circuits with galvanic isolation, the circuitry of this disclosure uses the unavoidable common mode voltages caused by the coupling capacitances of the data transfer circuit to evaluate the common mode voltage characteristics, such as the slew rate of a switching event. The switch driver circuit of this disclosure may include a common mode voltage detector to detect and measure features of the unavoidable common mode voltage during a switching event, such as voltage amplitude and slew rate. The common mode voltage detector may couple to a communication interface that provides the common mode voltage information to a controller for the switch driver circuit. In some examples, based on the received information, the controller may adjust the operation of the switching circuit.
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
H02M 1/38 - Means for preventing simultaneous conduction of switches
H02P 27/08 - Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using dc to ac converters or inverters with pulse width modulation
H03K 17/689 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors with galvanic isolation between the control circuit and the output circuit
6.
LINEAR TUNNEL MAGNETORESISTIVE SENSOR INCLUDING AN INTEGRATED BACK-BIAS MAGNET
A sensor module may include a back-bias magnet with a magnetization in a first direction. The sensor module may include a sensor chip including a first set of tunnel magnetoresistive (TMR) sensing elements. The sensor chip may be configured to determine a characteristic of a first magnetic field component using the first set of TMR sensing elements, and to generate a sensor signal based at least in part on the characteristic of the first magnetic field component. A value of the sensor signal may correspond to a linear position of a ferromagnetic object.
G01D 5/16 - Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using electric or magnetic means influencing the magnitude of a current or voltage by varying resistance
A semiconductor die includes: a semiconductor substrate; a first contact pad structure above the semiconductor substrate, the first contact pad structure including a metal contact pad configured for electrical contact and a metal layer adjoining an underside of the metal contact pad and jutting out beyond an edge of the metal contact pad; and a first optical detection marker in a periphery of the first contact pad structure and having a different contrast than the metal contact pad. The first optical detection marker includes a region of the metal layer that is adjacent to the edge of the metal contact pad and unobstructed by the metal contact pad so as to be optically visible in a plan view of the semiconductor die. A method of producing the semiconductor die is also described.
A method of forming a semiconductor package includes producing a package substrate that includes an interior laminate layer, a first metallization layer disposed below the interior laminate layer, and a second metallization layer disposed above the interior laminate layer, providing a first load terminal on a first surface of the first semiconductor die and a second load terminal on a second surface of the first semiconductor die; and a liner of dielectric material on the first semiconductor die; providing a liner of dielectric material on the first semiconductor die; embedding the first semiconductor die within the interior laminate layer such that the first surface of the first semiconductor die faces the second metallization layer, and wherein the liner of dielectric material is disposed on a corner of the first semiconductor die that is between the first and second load terminals of the first semiconductor die.
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
9.
POWER ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME
A power electronic device includes: a carrier having at least two die mounting areas; a power semiconductor die(s) mounted on the carrier at a first mounting area and having a first side facing the carrier and an opposite second side, a second die mounting area being free of any semiconductor die; and a contact clip arranged over the die and second die mounting area. The contact clip is at least partially arranged in a first plane, with a first part over the die being bent downwards such it is arranged in a second plane below the first plane and coupled to the second side of the die. A second part of the contact clip over the second die mounting area is bent upwards such that the second part is arranged in a third plane above the first plane, or is free of any bend and arranged in the first plane.
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
A phase change switching device includes a substrate comprising a main surface, an RF input pad and a plurality of RF output pads disposed over the main surface, and phase change switch connections between the RF input pad and each of the RF output pads, wherein the phase change switch connections each include a phase change material and a heating element thermally coupled to the phase change material, wherein each of the RF output pads are arranged outside of an outer perimeter of the RF input pad, and wherein plurality of RF output pads at least partially surrounds the outer perimeter of the RF input pad.
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
11.
Security aware routing in an in-vehicle communication network
A controller may receive a message provided by a network node included in an in-vehicle communication network. The controller may identify one or more characteristics of the message, the one or more characteristics indicating at least one of a message type of the message, a security property of the message, or a secure zone (SZ) associated with the message. The controller may determine a priority of the message based at least in part on the one or more characteristics. The controller may provide the message to an output buffer based at least in part on the priority of the message, the output buffer being one of a plurality of output buffers.
H04L 67/12 - Protocols specially adapted for proprietary or special-purpose networking environments, e.g. medical networks, sensor networks, networks in vehicles or remote metering networks
A system may include a set of light-emitting diode (LED) circuits, wherein each LED circuit of the set of LED circuits comprises: a first electrode; a set of second electrodes; and a set of pixels, wherein each pixel of the set of pixels corresponds to a combination of the first electrode and a respective second electrode of the set of second electrodes. A plurality of pixels may include the set of pixels corresponding to each LED circuit of the set of LED circuits. The first electrode may be located within a center portion of the respective LED circuit, and each second electrode of the set of second electrodes may be located within an outer portion the respective LED circuit. The system also includes a controller circuit configured to control whether each pixel of the plurality of pixels is activated or deactivated.
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different main groups of groups , or in a single subclass of , , e.g. forming hybrid circuits
G09G 3/32 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
H01L 25/075 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 27/15 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier, specially adapted for light emission
H01L 33/62 - Arrangements for conducting electric current to or from the semiconductor body, e.g. leadframe, wire-bond or solder balls
13.
SEMICONDUCTOR CIRCUIT ARRANGEMENT AND METHOD FOR A SEMICONDUCTOR CIRCUIT ARRANGEMENT
A semiconductor circuit arrangement includes a substrate, at least two first stress-sensitive elements in a first region of the substrate and at least two second stress-sensitive elements in a second region of the substrate. The first stress-sensitive elements each have an electrical characteristic which is dependent on a first component and a second component of a mechanical stress tensor in the first region. The second stress-sensitive elements each have an electrical characteristic which is dependent on a first component and a second component of a mechanical stress tensor in the second region. The semiconductor circuit arrangement includes a measuring circuit configured, based on the respective electrical characteristics of the first stress-sensitive elements and of the second stress-sensitive elements, to determine a stress difference between the first components in the first and second regions and a stress difference between the second components in the first and second regions.
G01L 1/22 - Measuring force or stress, in general by making use of electrokinetic cells, i.e. liquid-containing cells wherein an electrical potential is produced or varied upon the application of stress using resistance strain gauges
G01L 1/18 - Measuring force or stress, in general using properties of piezo-resistive materials, i.e. materials of which the ohmic resistance varies according to changes in magnitude or direction of force applied to the material
14.
MAGNETIC CURRENT SENSOR INTEGRATION INTO HIGH CURRENT CONNECTOR DEVICE WITH MOUNTING FOR TORQUE STABILIZATION
A power connector is provided that is configured to conduct a current. The power connector includes a base structure, an extension structure, and a connector head structure that define a current path for the current. The extension structure is coupled to and extends between the base structure and the connector head structure. The connector head structure includes a bore-hole that vertically extends into the connector head structure toward the base structure. The bore-hole is configured to receive a fastener for coupling the power connector to an electrical interface of a device. The connector head structure has a mechanical engagement feature configured to mechanically engage with a torque stabilization tool during a fastening of the fastener to the connector head structure in order to prevent a torque applied by the fastening of the fastener from being transferred to the extension structure.
G01R 1/04 - Housings; Supporting members; Arrangements of terminals
G01R 15/20 - Adaptations providing voltage or current isolation, e.g. for high-voltage or high-current networks using galvano-magnetic devices, e.g. Hall-effect devices
H01R 4/30 - Clamped connections; Spring connections using a screw or nut clamping member
H01R 13/66 - Structural association with built-in electrical component
15.
SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING THEREOF
The application relates to a power semiconductor device, including: a semiconductor body having a front side coupled to a frontside metallization and a backside coupled to a backside metallization; and an active region with a plurality of transistor cells. The frontside metallization includes a first load terminal structure and a control terminal structure. At least one of the first layer and the second layer is laterally segmented, with a first segment being part of the first load terminal structure and a second segment being part of the control terminal structure.
Disclosed herein is a power semiconductor device including a semiconductor body, a first load terminal, a second load terminal, an active region, an edge termination region, and a thin film layer that includes a bulk material and a laminar filler compound. Furthermore, a method of producing such a power semiconductor device is described herein, the method including: providing a thin film including a mixture of a bulk material component and a laminar filler compound onto a surface of at least parts of the edge termination region and/or over at least parts of the first load terminal; and curing the obtained mixture of the bulk material and laminar filler compound to generate a thin-film layer that includes a bulk material and a laminar filler compound.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
A silicon carbide device includes a silicon carbide substrate, a contact layer located on the silicon carbide substrate and including nickel and silicon, a barrier layer structure including titanium and tungsten, and a metallization layer comprising copper, wherein the contact layer is located between the silicon carbide substrate and at least a part of the barrier layer structure, wherein the barrier layer structure is located between the silicon carbide substrate and the metallization layer, wherein the metallization layer is configured as a contact pad of the silicon carbide device.
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
A system includes a first membrane, a second membrane and a third membrane spaced apart from one another, wherein the second membrane is between the first membrane and the third membrane, and the second membrane comprises a plurality of openings, a sealed low pressure chamber between the first membrane and the third membrane, and a plurality of electrodes in the sealed low pressure chamber
In an embodiment, a method includes: receiving radar digital data; processing the radar digital data with a plurality of sine filters to generate a respective plurality of range-slow-time data, where each sine filter is associated with a respective range zone of a plurality of range zones; generating a first presence score based on a first range-slow-time data of the plurality of range-slow-time data, where the first range-slow-time data is associated with the first range zone; and when the first presence score is higher than a predetermined threshold, generating a plurality of synthetic antennas based on the first range-slow-time data, performing angle estimation based on the plurality of synthetic antennas to generate first probability values for a plurality of angle zones associated with the first range zone, and updating an occupancy grid map based on the first probability values.
A system may comprise a power module including a power switch, a driver circuit configured to control an ON state and an OFF state of the power switch, and a processor configured to control the driver circuit. The processor may be configured to receive a voltage associated with the power switch in the ON state and determine a state of health (SOH) for the power switch based on the voltage and a regression model associated with the power switch.
A power semiconductor device is proposed. The power semiconductor device includes a semiconductor body and a wiring area over a first surface of the semiconductor body. The power semiconductor device further includes a bipolar power semiconductor element including a first load electrode in the wiring area, an active area in the semiconductor body, and a second load electrode at a second surface of the semiconductor body. The power semiconductor device further includes a current sensing element including a pn or pin junction. The power semiconductor device further includes an optical window configured to allow electromagnetic radiation caused by an on-current of the bipolar power semiconductor element to pass to the current sensing element.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
A chip package is provided. The chip package includes an electrically conductive carrier structure, a first power chip on the carrier structure having a control contact pad and a second power chip on the carrier structure having a control contact pad. The first and second power chips are arranged with their respective control contact pad facing a redistribution layer. A logic chip is arranged with a logic contact pad facing a redistribution layer, wherein the redistribution layer connects the logic contact pad with the respective control pads of the power chips.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
A package is disclosed. In one example, the package comprises a carrier, an electronic component mounted on or above the carrier, an electrically insulating and thermally conductive layer on at least part of an upper main surface of the electronic component, and a metal block on the electrically insulating and thermally conductive layer. An encapsulant at least partially encapsulates the electronic component, the carrier, the electrically insulating and thermally conductive layer and the metal block so that an upper main surface of the metal block is exposed beyond the encapsulant.
H01L 23/373 - Cooling facilitated by selection of materials for the device
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
24.
FIELD EFFECT TRANSISTOR COMPRISING EDGE TERMINATION AREA
A field effect transistor (FET) is proposed. The FET includes a transistor cell area in a silicon carbide (SiC) semiconductor body. An edge termination area surrounds the transistor cell area. A source contact is arranged over a first surface of the SiC semiconductor body. A drain contact is arranged on a second surface of the SiC semiconductor body. The FET further includes a drift region of a first conductivity type between the first surface and the second surface. Along a lateral direction, a net doping concentration in the drift region is larger in the transistor cell area than in the edge termination area.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
A chip assembly having a carrier having a cavity and at least one carrier contact, a chip arranged in the cavity and having at least one chip contact, and a wirebond wire, which electrically conductively connects the at least one chip contact to the at least one carrier contact, wherein the wirebond wire is flat-pressed in at least one subregion.
According to various embodiments, a circuit is described including a plurality of scan flip-flops including a sequence of scan flip-flops, wherein at least some scan flip-flops of the sequence are wrapper scan flip-flops, and including, for each scan flip-flop of at least a subset of the scan flip-flops, at the wrapper scan flip-flop's test input a respective test input circuit configured to, when supplied with a mode control signal having a first value, connect the test input to the output of the preceding wrapper scan flip-flop such that the test input of the flip-flop is supplied with the content of the preceding wrapper scan flip-flop and when supplied with the mode control signal having a second value, connect the test input to an output of a part of the circuit such that the test input of the flip-flop is supplied with a value depending on a test result.
A semiconductor package includes: a semiconductor die attached to a leadframe and having a first bond pad at a side of the semiconductor die facing away from the leadframe; a metal clip having a first bonding region attached to the first bond pad of the semiconductor die by a plurality of first wire bonds which extend through a plurality of first openings in the first bonding region of the metal clip, the plurality of first wire bonds forming a joint between the metal clip and the first bond pad of the semiconductor die; and a joint between the plurality of first wire bonds and the metal clip at a side of the metal clip facing away from the semiconductor die. Additional semiconductor package embodiments and related methods of manufacture are also described.
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
28.
OFFSET CORRECTION IN A VOLTAGE CONTROLLED MAGNETORESISTIVE SENSOR
In some implementations, a magnetic sensor may apply an electrical signal across a tunnel barrier layer of a tunnel magnetoresistive (TMR) sensing element. The electrical signal may have a first signal level during a first time period and a second signal level during a second time period. The second signal level may be different from the first signal level. The magnetic sensor may generate an offset-corrected sensor signal based on a sensor signal that results from applying the electrical signal across the tunnel barrier layer of the TMR sensing element.
According to various embodiments, a circuit is described including a plurality of scan flip-flops including a sequence of input wrapper scan flip-flops and including, for each input wrapper scan flip-flop of at least a subset of the input wrapper scan flip-flops, at the input wrapper scan flip-flop's test input a respective test input circuit configured to, when supplied with a mode control signal having a first value, connect the test input to the output of the preceding input wrapper scan flip-flop such that the test input of the flip-flop is supplied with the content of the preceding input wrapper scan flip-flop and when supplied with the mode control signal having a second value, connect the test input to an output of a part of the circuit such that the test input of the flip-flop is supplied with a value depending on a test result.
The disclosure is directed to the use of an externally-supplied control current to control the adjustment of an internal supply voltage generated via voltage regulator circuitry, which may be identified with an integrated circuit (IC) chip. The configuration of the voltage regulator circuitry functions to establish a linear relationship between the control current and the internal voltage supply. This configuration enables setting the control current to a predetermined value, causing the supply voltage to deviate in a predictable and controllable manner, and thus facilitating verification of the IC chip's internal voltage supply test circuitry. Furthermore, because the control current used for this purpose is relatively small (e.g. on the order of microamps), existing on chip test architecture, which may accommodate such low level currents, may be re-used for the selective routing of the control current for such IC testing.
G05F 1/46 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc
G05F 1/565 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
31.
ULTRASONIC TOUCH SENSORS AND CAPACITIVE PRESSURE SENSING MICROELECTROMECHANICAL SYSTEM FUSION
A touch sensor includes a touch structure including a touch interface and an inner interface arranged opposite to the touch interface; a capacitive ultrasonic transmitter arranged inside an enclosed interior volume and configured to transmit an ultrasonic transmit wave towards the touch structure; a capacitive ultrasonic receiver arranged inside the enclosed interior volume and configured to receive at least one ultrasonic reflected wave produced from the ultrasonic transmit wave via internal reflection; a coupling medium that fills an area between the inner interface and the capacitive ultrasonic receiver, wherein an external force applied to the touch interface is configured to impart an internal pressure onto the capacitive ultrasonic receiver through the coupling medium; and a sensor circuit configured to convert the at least one ultrasonic reflected wave into a measurement signal and detect the external force based on the measurement signal.
A transistor device includes: a semiconductor substrate having a doping concentration of a first dopant type; a highly doped source region of a second dopant type formed in a first surface of the semiconductor substrate; a first highly doped drain region of the second dopant type formed in the first surface; a gate structure arranged on the first surface and including a gate electrode formed on the first surface; and a first lightly doped region formed in the first surface and extending from the highly doped source region under the gate electrode. A channel region extends between the first lightly doped region and the highly doped drain region. The channel region has an average doping level of the first dopant type of n×10x that varies by less than 0.5×n×10X between the first lightly doped region and the highly doped drain region along the lateral direction parallel to the first surface.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
A semiconductor device includes a semiconductor die comprising a radio frequency (RF) circuit, a first dielectric layer disposed over a first surface of the semiconductor die, an antenna layer disposed over a surface of the first dielectric layer, and an antenna feeding structure coupling the antenna layer to the RF circuit of the semiconductor die, wherein the semiconductor die comprises a via, and the antenna feeding structure comprises a first portion arranged within the opening of the semiconductor die and extending to the first surface of the semiconductor die, and a second portion arranged through the first dielectric layer.
H01Q 1/22 - Supports; Mounting means by structural association with other equipment or articles
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
An electronic device includes an interface configured to receive telemetry information for one or more power semiconductor devices and a data acquisition and processing unit. The data acquisition and processing unit may be configured to increase a gate voltage above a maximum permitted level for each of the one or more power semiconductor devices having a current slew rate that exceeds a predetermined level as determined by the telemetry information. The data acquisition and processing unit may be configured to increase a gate voltage above a maximum permitted level for each of the one or more power semiconductor devices having a temperature that exceeds a predetermined level as determined by the telemetry information. An electronic system that includes the electronic device is also described.
H04Q 9/00 - Arrangements in telecontrol or telemetry systems for selectively calling a substation from a main station, in which substation desired apparatus is selected for applying a control signal thereto or for obtaining measured values therefrom
35.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE
A semiconductor device includes a transistor. The transistor includes gate trenches formed in a semiconductor substrate, extending in a first horizontal direction and patterning the semiconductor substrate into ridges. The ridges are arranged between two adjacent gate trenches, respectively. The transistor further includes a gate electrode arranged in at least one of the gate trenches, a source region of a first conductivity type, a channel region, and a drift region of the first conductivity type. The source region, channel region and a part of the drift region are arranged in the ridges. The gate electrode is insulated from the channel region and the drift region. The channel region includes a doped portion of a second conductivity type. A doping concentration of the doped portion decreases in a second horizontal direction intersecting the first horizontal direction from a region close to the gate electrode to a central portion of the ridge.
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
An antenna structure for a contactless wearable structure having a plurality of antenna tracks on the substrate, the opposite ends of which are connectable to form an antenna when the substrate is bent, a plurality of capacitor elements on the substrate that are couplable to the antenna for adjusting the resonance frequency of the antenna, and at least one predefined separation region, by means of which it is possible to adjust which of the plurality of capacitor elements are electrically conductively connectable to the antenna when the substrate is bent, in order to form at least one capacitor with a predetermined total capacitance that is electrically conductively coupled to the antenna.
A silicon-controlled rectifier includes a semiconductor body including a first main surface, an active device region, a first, a second, a third and a fourth surface contact area at the first main surface and arranged directly one after another along a first lateral direction, wherein the semiconductor body is electrically contacted at each of the first to fourth surface contact areas, and a first, a second, a third and a fourth SCR region, wherein the first and third SCR regions are of a first conductivity type and directly adjoin the first and third surface contact areas, respectively, and wherein the second and fourth SCR regions are of a second conductivity type and directly adjoin the second and fourth surface contact areas, respectively, wherein the first SCR region is electrically connected to the fourth SCR region, and the second SCR region is electrically connected to the third SCR region.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 29/74 - Thyristor-type devices, e.g. having four-zone regenerative action
38.
MULTIPLE COBALT IRON BORON LAYERS IN A FREE LAYER OF A MAGNETORESISTIVE SENSING ELEMENT
A tunnel magnetoresistive (TMR) sensing element may include a free layer. The free layer of the TMR sensing element may include a first cobalt iron boron (CoFeB) layer, an interlayer over the first CoFeB layer, a second CoFeB layer over the interlayer, and a nickel iron (NiFe) layer over the second CoFeB layer.
According to some embodiments, a method for manufacturing a semiconductor device is provided. One or more first implantation processes are performed to form an implanted region, of a first conductivity type, in a semiconductor body. A trench is formed in the semiconductor body. After forming the trench, a second implantation process is performed to form a current spread region, of a second conductivity type, in the semiconductor body. The second implantation process includes implanting first dopants, through a top surface of the semiconductor body, to form a first portion of the current spread region, and implanting second dopants, through a bottom of the trench, to form a second portion of the current spread region. A gate structure is formed in the trench. A vertical position of the first portion of the current spread region matches a vertical position of the gate structure. The second portion of the current spread region underlies the gate structure.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
A touch sensor includes a touch structure; a signal generator configured to generate an excitation signal; a transmitter configured to receive the excitation signal and transmit an ultrasonic transmit wave towards the touch structure based on the excitation signal; a receiver configured to receive an ultrasonic reflected wave produced by a reflection of the ultrasonic transmit wave at the touch structure, wherein the transmitter and the receiver are coupled by a capacitive path, the receiver is configured to be influenced by the excitation signal whereby the excitation signal induces a capacitive cross-talk on the capacitive path, and the receiver is configured to generate a measurement signal representative of the capacitive cross-talk; and a measurement circuit coupled to the receiver and configured to perform a comparison of the measurement signal with a threshold to determine whether a no-touch event or a touch event has occurred at the touch interface.
A test arrangement for testing an integrated circuit is described wherein the test arrangement comprises a test pattern generator configured to generate a sequence of test patterns, a memory storing an indication for each of a plurality of groups of one or more of the test patterns, whether to use the group of test patterns for testing an integrated circuit and a controller configured to, for each of the test patterns, control the test pattern generator to feed the test pattern to the integrated circuit if the test pattern belongs to a group that should be used for testing the integrated circuit and to skip the test pattern in the testing of the integrated circuit if the test pattern belongs to a group that should not be used for testing the integrated circuit.
A molded package includes: a semiconductor die; a substrate attached to a bottom side of the semiconductor die; an electrically conductive clip attached to a top side of the semiconductor die; and a mold compound encapsulating the semiconductor die. A top side of the electrically conductive clip faces away from the semiconductor die and has an exposed flat surface that overlays the semiconductor die and is not covered by the mold compound. A bottom side of the electrically conductive clip faces the semiconductor die and has a convex curved surface that is attached to the top side of the semiconductor die. Along a vertical cross-section of the electrically conductive clip from the exposed flat surface to the convex curved surface, the electrically conductive clip has a plano-convex shape delimited by the exposed flat surface and the convex curved surface. A method of producing the molded package is also described.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
43.
CHIP PACKAGE, CHIP SYSTEM, METHOD OF FORMING A CHIP PACKAGE, AND METHOD OF FORMING A CHIP SYSTEM
A chip package is provided. The chip package includes a first chip, a second chip, an electrically conductive structure to which the first chip and the second chip are mounted, at least one contact terminal for electrically contacting the first chip and/or the second chip, and encapsulation material at least partially encapsulating the first chip, the second chip, and the electrically conductive structure. The encapsulation material forms a chip package body from which the at least one contact terminal protrudes. At least a portion of the electrically conductive structure forms a portion of an outer surface of the chip package body.
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
44.
SENSOR DEVICES HAVING AN ACOUSTIC COUPLING MEDIUM, AND ASSOCIATED MANUFACTURING METHODS
A sensor device contains at least one sensor chip having at least one MEMS structure arranged at a main surface of the at least one sensor chip, wherein the at least one sensor chip is configured to transmit ultrasonic signals and/or to receive ultrasonic signals. The sensor device further contains an acoustic coupling medium arranged selectively on the at least one MEMS structure, wherein the acoustic coupling medium is configured to decouple an ultrasonic signal to be emitted from the at least one MEMS structure and/or to inject a received ultrasonic signal into the at least one MEMS structure. The acoustic coupling medium only partially covers the main surface of the at least one sensor chip.
A circuit includes a cross-talk compensation component including a power profile reconstruction component for reconstructing the power profile of a digital microphone coupled to a microelectromechanical (MEMS) device, wherein the power profile represents power consumption of the digital microphone over time between at least two operational modes of the digital microphone, and a reconstruction filter for modeling thermal and/or acoustic properties of the digital microphone; and a subtractor having a first input for receiving a signal from the digital microphone, a second input coupled to the cross-talk compensation component, and an output for providing a digital output signal.
B81B 7/02 - Microstructural systems containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems (MEMS)
H04R 3/06 - Circuits for transducers for correcting frequency response of electrostatic transducers
The described techniques address issues associated with hybrid current or magnetic field sensors used to detect both low- and high-frequency magnetic field components. The hybrid sensor implements a DC component rejection path in the high-frequency magnetic field component path. Both digital and analog implementations are provided, each functioning to generate a DC component cancellation signal to at least partially cancel a DC component of a current signal generated via the high-frequency magnetic field component path. The hybrid sensor provides a high-bandwidth, high-accuracy, and low DC offset hybrid current solution that also eliminates the need for DC decoupling capacitors in the high-frequency path. A modification is also described for implementing a Sigma-Delta (ΣΔ) quantization noise reduction path to reduce the quantization noise and to improve accuracy.
G01D 5/14 - Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using electric or magnetic means influencing the magnitude of a current or voltage
A piezoresistive transistor device includes a first transistor cell having a first piezoelectric material body and a first piezoresistive material body arranged in a stacked configuration. A first electrical resistance of the first piezoresistive material body is dependent upon a voltage applied across the first piezoelectric material body by way of a pressure applied by the first piezoelectric material body to the first piezoresistive material body. A second transistor cell includes a second piezoelectric material body and a second piezoresistive material body arranged in a stacked configuration. A second electrical resistance of the second piezoresistive material body is dependent upon a voltage applied across the second piezoelectric material body by way of a pressure applied by the second piezoelectric material body to the second piezoresistive material body. An internal electrical interconnect is configured to electrically connect the first electrical resistance and the second electrical resistance in series or in parallel.
A method of monitoring a thermal impedance of at least a portion of a thermal path between a semiconductor device having at least two output terminals and a heat sink s provided. The method includes causing power dissipation in the semiconductor device by reloading parasitic capacitances of the semiconductor device such that the at least two output terminals are at the same voltage level, measuring a first temperature in response to the power dissipation at a first end of the portion of the thermal path, measuring a second temperature in response to the power dissipation at a second end of the portion of the thermal path, and determining a measure of the thermal impedance based on the first temperature and the second temperature.
An electronic device with a multi-layer contact and a system is disclosed. In an embodiment, a semiconductor device includes a semiconductor substrate having a first electrode terminal located on a first surface and a second surface electrode terminal located on a second surface, the first surface being opposite to the second surface, an electrical contact layer disposed directly on the first electrode terminal, a functional layer directly disposed on the electrical contact layer, an adhesion layer directly disposed on the functional layer, a solder layer directly disposed on the adhesion layer; and a protection layer directly disposed on the solder layer, wherein the semiconductor device is a power semiconductor device configured to provide a vertical current flow.
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 23/482 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of lead-in layers inseparably applied to the semiconductor body
A method of driving a transistor between switching states includes controlling a transition of a gate voltage at a gate terminal of a transistor during each of a plurality of turn-off switching events to turn off the transistor, wherein the transistor is configured to be turned off according to a desaturation time during each of the plurality of turn-off switching events; measuring a transistor parameter indicative of a voltage slew rate of the transistor for a first turn-off switching event during which the transistor is transitioned from an on state to an off state; and regulating a duration of the desaturation time for a next turn-off switching event based on the measured transistor parameter.
H03K 17/16 - Modifications for eliminating interference voltages or currents
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
A semiconductor device includes a semiconductor body having an upper surface, a group of first upper-level metal fingers and second upper-level metal fingers that are arranged alternatingly with one another, wherein each of the first upper-level metal fingers is electrically connected to the semiconductor body by the first lower-level conductive fingers, wherein each of the second upper-level metal fingers is electrically connected to the semiconductor body by the second lower-level conductive fingers, wherein the group of first lower-level conductive fingers and second lower-level conductive fingers defines a connection area over the upper surface, and wherein in the connection area the first upper-level metal fingers are at least partially non-overlapping with the second upper-level metal fingers.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 23/528 - Layout of the interconnection structure
52.
MULTI-BEAM LASER BEAM SCANNER IN A PICTURE GENERATION UNIT
A picture generation system includes a plurality of red-green-blue (RGB) light transmitters configured to synchronously generate respective pixel light beams and transmit the respective pixel light beams along respective transmission paths to be projected into a full field of view (FOV). The full FOV is divided into a plurality of FOV sections that are respectively paired with a different one of the plurality of RGB light transmitters such that each of the plurality of RGB light transmitters transmits light into a respective area defined by its respective FOV section. The picture generation system further includes a scanning system arranged on each of the respective transmission paths of the plurality of RGB light transmitter. The scanning system includes a scanning structure that enables the scanning system to simultaneously steer the respective pixel light beams into the plurality of FOV sections.
G02B 26/12 - Scanning systems using multifaceted mirrors
G02B 26/08 - Optical devices or arrangements for the control of light using movable or deformable optical elements for controlling the direction of light
A frequency linearity measurement circuit configured to measure a frequency linearity of a frequency signal includes: a first measurement circuit configured to generate a first estimate of an integer number of clock cycles of the frequency signal within a respective gate signal period of a gate signal; a second measurement circuit comprising a time-to-digital converter (TDC) configured to generate a second estimate of a fractional number of clock cycle of the frequency signal within the respective gate signal period; a reference measurement circuit configured to generate a third estimate of an expected number of clock cycles within the respective gate signal period; and a closed-loop frequency tracking circuit configured to track a frequency error between an expected frequency and a measured frequency, where the expected frequency and the measured frequency are determined based on the third estimate and on a sum of the first estimate and the second estimate, respectively.
G01S 7/35 - RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES - Details of systems according to groups , , of systems according to group - Details of non-pulse systems
54.
Semiconductor Package and Passive Element with Interposer
A method includes providing an interposer that includes an electrically insulating substrate, upper contact pads disposed on an upper surface, and lower contact pads disposed on a lower surface, providing a semiconductor package that includes a semiconductor die embedded within a package body and a plurality of package terminals exposed from the package body, providing a first passive electrical element that comprises first and second terminals, forming a first electrical connection between the first terminal of the first passive electrical element and a first one of the lower contact pads via the interposer, forming a second electrical connection between the second terminal of the first passive electrical element and a first one of the package terminals, and forming a third electrical connection between a second one of the package terminals and a second one of the lower contact pads via the interposer.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
55.
CHIP ASSEMBLY, METHOD FOR FORMING A CHIP ASSEMBLY, AND METHOD FOR USING A CHIP ARRANGEMENT
A chip arrangement including a chip module which includes a chip, a contact-based interface in accordance with ISO 7816 which is electrically conductively connected to the chip, and an antenna structure which is electrically conductively connected to the chip and provides a contactless interface, and a carrier which comprises a chip module receptacle and a booster antenna structure which, when the chip module is arranged in the chip module receptacle of the carrier, inductively couples to the antenna structure of the chip module, wherein the chip module is arranged releasably in the chip module receptacle.
A frequency linearity measurement circuit configured to measure a frequency linearity of a frequency signal includes: a first measurement circuit having a counter, where the counter is controlled by a gate signal having a gate signal period, where the first measurement circuit is configured to generate a first estimate of an integer number of clock cycles of the frequency signal within a respective gate signal period of the gate signal; a second measurement circuit having a time-to-digital converter (TDC), where the TDC is controlled by the gate signal, and is configured to generate a second estimate of a fractional number of clock cycle of the frequency signal within the respective gate signal period of the gate signal; and a reference measurement circuit configured to generate a third estimate of an expected number of clock cycles within the respective gate signal period of the gate signal.
H03L 7/099 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
G01S 13/34 - Systems for measuring distance only using transmission of continuous waves, whether amplitude-, frequency-, or phase-modulated, or unmodulated using transmission of continuous, frequency-modulated waves while heterodyning the received signal, or a signal derived therefrom, with a locally-generated signal related to the contemporaneously transmitted signal
H03L 7/091 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
57.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE
A semiconductor device includes a transistor including transistor cells. Each transistor cells has a gate electrode arranged in gate trenches formed in a first portion of a silicon carbide substrate and extending in a first horizontal direction, a source region, a channel region, and a current-spreading region. The source region, channel region, and at least part of the current-spreading region are arranged in ridges patterned by the gate trenches. The transistor cells further include a body contact portion of the second conductivity type arranged in a second portion of the silicon carbide substrate and electrically connected to the channel region. The transistor cells further include a shielding region of the second conductivity type. A first portion of the shielding region is arranged below the gate trenches, respectively, and a second portion of the shielding region is arranged adjacent to a sidewall of the gate trenches, respectively.
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
Disclosed is a re-configurable sensor arrangement (100) including a sensor device (110) and a controller device (120), both being configured to communicate with each other, wherein the controller device (120) is configured to transmit a pulse modulated signal (130) to the sensor device (110) via a one-wire voltage interface (140), and wherein the sensor device (110) is configured to receive the pulse modulated signal (130) via the one-wire voltage interface (140) and to re-configure its internal configuration in response to the received pulse modulated signal (130).
A power semiconductor module includes a power semiconductor die arranged on a power substrate, a housing enclosing the power semiconductor die and the power substrate, wherein an interior volume formed by the housing is divided by interior walls into at least a first compartment and a second compartment, wherein the power semiconductor die is arranged within the first compartment, a first encapsulation material encapsulating the power semiconductor die and at least partially filling the first compartment, and a second encapsulation material different from the first encapsulation material, the second encapsulation material encapsulating the first encapsulation material and at least partially filling the second compartment, wherein the first encapsulation material is arranged within the first compartment but not within the second compartment.
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 23/053 - Containers; Seals characterised by the shape the container being a hollow construction and having an insulating base as a mounting for the semiconductor body
H01L 25/11 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group
60.
ENCAPSULATED MEMS DEVICE AND METHOD FOR MANUFACTURING THE MEMS DEVICE
An encapsulated MEMS device and a method for manufacturing the MEMS device are provided. The method comprises providing a cavity structure having an inner volume comprising a plurality of MEMS elements, which are relatively displaceable with respect to each other, and having an opening structure to the inner volume, depositing a Self-Assembled Monolayer (SAM) through the opening structure onto exposed surfaces within the inner volume of the cavity structure, and closing the cavity structure by applying a layer structure on the opening structure for providing a hermetically closed cavity.
A magnetic sensor apparatus includes a magnetic field generating circuit which is configured to generate a magnetic field, a magnetic field sensor circuit which is configured to output a sensor signal in response to the magnetic field, which sensor signal has a signal amplitude dependent on a sensitivity of the magnetic field sensor circuit, an amplifier circuit which is configured to amplify the sensor signal and to output an amplified sensor signal with an amplified signal amplitude, and a control circuit which is configured to use a setting signal to set a supply signal of the magnetic field sensor circuit and/or a gain of the amplifier circuit such that the amplified signal amplitude corresponds to a target amplitude.
An RF switch device includes transistors coupled in series forming an RF conductive current path; a first resistive bias network forming a DC conductive bias path between gate nodes of the plurality of transistors; and a first ESD bias component coupled between the RF conductive current path and the first resistive bias network, wherein the first ESD bias component provides a DC conductive path between the RF conductive current path of the RF switch device and the first resistive bias network during an ESD event.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H02H 9/04 - Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
63.
Fast Lissajous lock control and synchronization of scanning axes of microelectromechanical system
A method of synchronizing a first oscillation about a first axis with a second oscillation about a second axis includes: generating a first position signal that indicates a position of the first oscillation about the first axis; generating a second position signal that indicates a position of the second oscillation about the first axis; determining a phase difference between the first and the second position signals; comparing the phase difference to a threshold value to generate a comparison result; generating a first reference signal having a first frequency and a second reference signal having a second frequency; synchronizing the first oscillation to the first frequency and synchronizing the second oscillation to the second frequency; monitoring the comparison result; and synchronously triggering a start of the first reference signal and the second reference signal responsive to the comparison result indicating that the phase difference is less than the threshold value.
G01S 7/481 - Constructional features, e.g. arrangements of optical elements
G02B 26/08 - Optical devices or arrangements for the control of light using movable or deformable optical elements for controlling the direction of light
H03L 7/099 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
A circuit is configured to generate a first switching signal and a second switching signal. During a first portion of a first switching period, both the first switching signal and the second switching signal indicate to turn-on and turn-off. During a second portion of the first switching period, the first switching signal indicates to turn-on and the second switching signal indicates to turn-off. In response to a determination that a measurement time threshold exceeds the first switching period, the circuit is configured to generate a first adapted switching signal that extends the turn-on portion by a time value in the first switching period and to generate a second adapted switching signal that extends the turn-on time by the time value in a second switching period. The circuit is further configured to control switching circuitry using the first adapted switching signal and the second adapted switching signal to operate a motor.
H02P 23/14 - Estimation or adaptation of motor parameters, e.g. rotor time constant, flux, speed, current or voltage
H02P 27/08 - Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using dc to ac converters or inverters with pulse width modulation
65.
Excess Loop Delay Compensation for a Delta-Sigma Modulator
In accordance with an embodiment, a delta-sigma modulator includes: an analog loop filter comprising an outer portion and an inner portion having an input coupled to the outer portion; a quantizer coupled to an output of the inner portion of the analog loop filter; an outer feedback path coupled between an output of the quantizer and an input to the outer portion of the analog loop filter; and a compensation filter coupled between an output of the quantizer and an input of the inner portion of the analog loop filter. The compensation filter has a transfer function configured to correct for an effect of excess loop delay (ELD) on the delta-sigma modulator.
A semiconductor device includes: a transistor formed in a first semiconductor layer stack; a diode formed in a second semiconductor layer stack, the diode including an anode metal layer; and a carrier. The transistor and the diode are mounted to the carrier. A terminal of the transistor is electrically connected to the carrier, and the anode metal layer is in direct contact with the carrier.
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
Device with ultrasonic transducer and method for manufacturing same. A device is provided, having an ultrasonic transducer, which includes a membrane and a cover element. A coupling medium entirely fills an interspace between the membrane and the cover element, and extends from the interspace into a reservoir space which communicates with the interspace.
A current sensor includes a current rail and a magnetic field sensor. The magnetic field sensor is configured to measure a magnetic field induced by a current flowing through the current rail. A first insulation layer and a second insulation layer are arranged between the current rail and the magnetic field sensor. An interface between the first insulation layer and the second insulation layer is free of a contact with the current rail and/or is free of a contact with the magnetic field sensor. A portion of the current rail extends into the second insulation layer and the portion of the current rail is encapsulated by the second insulation layer.
G01R 15/20 - Adaptations providing voltage or current isolation, e.g. for high-voltage or high-current networks using galvano-magnetic devices, e.g. Hall-effect devices
A sensor system may include a magnet arranged such that a linear position of the magnet corresponds to a position of a trigger element on a substantially linear trajectory, and such that an angular position of the magnet corresponds to a selected position of a selection element, the selected position being one of a plurality of selected positions. The sensor system may include a magnetic sensor to determine the position of the trigger element based on a strength of a first magnetic field component and a strength of a second magnetic field component, and determine the selected position of the selection element based on a strength of a third magnetic field component and the strength of the second magnetic field component. The first magnetic field component, the second magnetic field component, and the third magnetic field component may be perpendicular to each other.
G01D 5/14 - Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using electric or magnetic means influencing the magnitude of a current or voltage
G01D 5/16 - Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using electric or magnetic means influencing the magnitude of a current or voltage by varying resistance
70.
BROADBAND HIGH POWER TRANSMIT/RECEIVE SWITCH SYSTEM
A switch system includes a first hybrid coupler having a first node coupled to a termination terminal, a second node coupled to an antenna terminal, a third node coupled to a quadrature terminal, and a fourth node coupled to an in-phase terminal; and a radio frequency (RF) switch having a first switch coupled between the quadrature terminal and ground, and a second switch coupled between the in-phase terminal and ground, wherein the termination terminal is configured for coupling to a load, wherein the load and the RF switch dissipate RF power due to a transmit mode insertion loss, and wherein a majority of the RF power is reflected into the load by the first hybrid coupler.
A transceiver hybrid includes a multi-layer laminated hybrid comprising a coupler, the coupler including a first metal layer in a first layer of the multi-layer laminated hybrid having a first end coupled to a termination terminal and a second end coupled to a quadrature terminal; and a second metal layer in a second layer of the multi-layer laminated hybrid having a first end coupled to an antenna terminal, and a second end coupled to an in-phase terminal, wherein a width of the first metal layer is greater than a width of the second metal layer, such that a registration error margin is formed between the first metal layer and the second metal layer.
H04B 1/58 - Hybrid arrangements, i.e. arrangements for transition from single-path two-direction transmission to single-direction transmission on each of two paths or vice versa
H04B 1/3888 - Arrangements for carrying or protecting transceivers
72.
CHEMO-RESISTIVE GAS SENSING DEVICE COMPRISING A CATALYTIC GAS FILTER ARRANGEMENT
A sensor chip includes a substrate and one or more chemo-resistive gas sensing elements attached to the substrate. Each gas sensing element provides a signal depending on one or more gases to be sensed. A catalytic gas filter arrangement includes one or more filter sections, each filter section including a cavity covered with at least one membrane. The at least one membrane is supported by a support structure and includes gas permeable pores. A surface defining the pores includes a catalytic material for degrading one or more of the gases. The gas filter arrangement is arranged so at least one of the chemo-resistive gas sensing elements is exposed to a filtered mixture of the gases in the cavity of one of the filter sections. The filtered mixture of gases is obtained by filtering the ambient mixture of the one or more gases with the one of the filter sections.
G01N 33/00 - Investigating or analysing materials by specific methods not covered by groups
G01N 27/16 - Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating impedance by investigating resistance of an electrically-heated body in dependence upon change of temperature caused by burning or catalytic oxidation of surrounding material to be tested, e.g. of gas
73.
Apparatus, Electronic Device and Method for Target Motion Detection
An apparatus includes interface circuitry configured to receive data indicating a measurement signal of a radar sensor. The apparatus further includes processing circuitry configured to determine a rate at which the measurement signal crosses a predefined value based on the data and determine presence of at least one of an interference signal and a target motion in a field of view of the radar sensor based on the rate.
A sensor system may include a first magnet arranged such that a position of the first magnet corresponds to a position of a trigger element on a linear trajectory. The sensor system may include a second magnet arranged such that a position of the second magnet corresponds to a selected position of a selection element. The sensor system may include a magnetic sensor to detect a strength of a first magnetic field component, a strength of a second magnetic field component, and a strength of a third magnetic field component. The magnetic sensor may be further to determine the position of the trigger element based on the strength of the first magnetic field component and the strength of the second magnetic field component, and to determine the selected position of the selection element based on the strength of the third magnetic field component.
An image processing system, includes an image sensor, a bus structure coupled to the image sensor, and a system memory coupled to the image sensor via the bus structure. A direct memory access (DMA) controller is coupled to the bus structure. The DMA controller includes in-line logic hardware configured to retrieve raw pixel data from the image sensor, and internally process the retrieved raw pixel data thereby providing processed pixel data.
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
G06K 7/10 - Methods or arrangements for sensing record carriers by corpuscular radiation
76.
Digital coarse locking in digital phase-locked loops
A digital phase-locked loop (DPLL) circuit includes: a first time-to-digital converter (TDC) and a first digital loop filter (DLF) that are configured to be coupled between a reference clock source and a digitally controlled oscillator (DCO), where the first TDC is configured to, during an acquisition mode, generate a phase error by: receiving a reference clock signal from the reference clock source; receiving a clock signal that is based on an output of the DCO divided by a dividing factor, computing a phase error using the reference clock signal and the clock signal; detecting cycle slipping in the computed phase error; and in response to detecting the cycle slipping, modifying the computed phase error to reduce the impact of cycle slipping on the DPLL circuit; and a first frequency divider circuit configured to generate the clock signal by dividing the output of the DCO by the dividing factor.
H03L 7/093 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
H03L 7/18 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
H03L 7/099 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
77.
POWER CONVERTER CONTROL IN AN ISOLATED POWER DOMAIN
In accordance with an embodiment, an electronic control unit (ECU) includes: a high voltage domain and a low voltage domain galvanically isolated from each other; a bus interface circuit in the low voltage domain; a controller in the high voltage domain, the controller being configured to receive data from and transmit data to the bus interface circuit; a first isolation device that couples the controller and the bus interface circuit; a DC/DC converter in the high voltage domain configured to receive a first battery voltage and configured to generate an output voltage therefrom for supplying the controller; and a second isolation device configured to receive an enable signal from a first circuit node in the low voltage domain and to provide the enable signal to the DC/DC converter in the high voltage domain.
B60L 53/22 - Constructional details or arrangements of charging converters specially adapted for charging electric vehicles
B60L 58/10 - Methods or circuit arrangements for monitoring or controlling batteries or fuel cells, specially adapted for electric vehicles for monitoring or controlling batteries
78.
METHOD FOR MANUFACTURING A CONTACT ON A SILICON CARBIDE SEMICONDUCTOR SUBSTRATE, AND SILICON CARBIDE SEMICONDUCTOR DEVICE
The disclosure relates to a method for manufacturing a contact on a silicon carbide semiconductor substrate and to a silicon carbide semiconductor device comprising a crystalline silicon carbide semiconductor substrate and a contact layer directly in contact with the silicon carbide semiconductor substrate surface and having, at an interface to the semiconductor substrate, a contact phase portion comprising at least a metal, silicon, and carbon. The method comprises the acts of providing a crystalline silicon carbide semiconductor substrate, depositing a metallic contact material layer onto the crystalline silicon carbide semiconductor substrate, and irradiating at least a part of the silicon carbide semiconductor substrate and at least a part of the metallic contact material layer at their interface with at least one thermal annealing laser beam, thereby generating a contact phase portion at the interface, wherein the contact phase portion comprises at least a metal, silicon, and carbon.
H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/04 - Semiconductor bodies characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
The disclosure relates to a method for manufacturing a contact on a SiC substrate, wherein the method includes: providing a crystalline SiC substrate; modifying a crystal structure in a surface area of the SiC substrate such that a carbon-enriched SiC portion is generated in the surface area; forming a contact layer on the SiC substrate by depositing a metallic contact material onto the surface area that includes the carbon-enriched SiC portion; and thermal annealing of at least a part of the carbon-enriched SiC portion of the SiC substrate and at least a part of the contact layer, such that a ternary metallic phase portion including at least the metallic contact material, silicon, and carbon is generated. Furthermore, SiC semiconductor devices are described, which include a crystalline SiC substrate and a contact layer including a ternary metallic phase portion directly in contact with the SiC substrate surface.
H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/04 - Semiconductor bodies characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
80.
METHOD OF SOLDERING A SEMICONDUCTOR CHIP TO A CHIP CARRIER
A method of soldering a semiconductor chip to a chip carrier includes arranging a solder deposit including solder and solder flux between a contact portion of the carrier and a contact portion of a chip pad arranged at a surface of the semiconductor chip. Arranging a dielectric layer at the surface of the semiconductor chip. The dielectric layer includes an opening within which the contact portion of the chip pad is exposed. The dielectric layer further includes arranging a solder flux outgassing trench separate from the opening and intersecting with the solder deposit. The method further includes melting the solder deposit which causes liquid solder to be moved over the solder flux outgassing trench for extraction of flux gas.
In an embodiment, a phase change switch device is provided. The phase change switch includes a phase change material, a set of heaters arranged to heat the phase change material, and a switch arrangement. The switch arrangement includes a plurality of switches, and is configured to selectively provide electrical power to the set of the heaters.
H03K 17/56 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices
82.
SEMICONDUCTOR PACKAGE HAVING A METAL CLIP AND RELATED METHODS OF MANUFACTURING
A semiconductor package includes: a semiconductor die attached to a lead frame and having a first bond pad at a side of the semiconductor die facing away from the lead frame; a metal clip having a first bonding region attached to the first bond pad by a solder joint, the metal clip providing an electrical pathway to the first bond pad; and an additional electrical pathway to the first bond pad. A first end of the additional electrical pathway is attached to the first bond pad. At one or more locations between the first end and a second end of the additional electrical pathway, the additional electrical pathway is attached to a surface of the first bonding region of the metal clip that faces away from the first bond pad. Methods of producing the semiconductor package are also described.
A current sensor system includes a magnetic field sensor including a chip plane, a first set of sensor elements sensitive to a first magnetic field component that is aligned in a first direction that is parallel to the chip plane, and a second set of sensor elements sensitive to a second magnetic field component that is aligned in a second direction that is perpendicular to the chip plane; and three conductor structures arranged in parallel to each other and configured to carry a current parallel or antiparallel to a third direction that is perpendicular to the first direction and to the second direction. The three conductor structures generate three magnetic fields based on the current flowing therethrough, where the three magnetic fields produce a first magnetic field distribution of the first magnetic field component and a second magnetic field distribution of the second magnetic field component.
G01R 15/20 - Adaptations providing voltage or current isolation, e.g. for high-voltage or high-current networks using galvano-magnetic devices, e.g. Hall-effect devices
A power module includes: a first substrate having a patterned first metallization; a second substrate vertically aligned with the first substrate and having a patterned second metallization that faces the patterned first metallization; first vertical power transistor dies having a drain pad attached to a first island of the patterned first metallization and a source pad electrically connected to a first island of the patterned second metallization via first spacers; and second vertical power transistor dies having a source pad electrically connected to the first island of the patterned first metallization via second spacers. A first subset of the second vertical power transistor dies has a drain pad attached to a second island of the patterned second metallization. A second subset of the second vertical power transistor dies has a drain pad attached to a third island of the patterned second metallization. A method of producing the module is described.
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 23/373 - Cooling facilitated by selection of materials for the device
H01L 21/66 - Testing or measuring during manufacture or treatment
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices
85.
ERROR PROCESSING AND CORRECTION OF ADJACENT 2-BIT ERRORS
What is proposed is a solution for processing errors in a sequence of bits, wherein the sequence of bits, in the error-free case, forms a codeword of an error code, wherein the error code is based on an H-matrix or is able to be determined thereby, wherein an error syndrome is determined for the sequence of bits, wherein a link is determined between components of the error syndrome and parts of the H-matrix, and wherein two adjacent bits in the sequence of bits are corrected if the link adopts a predefined value.
H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
H03M 13/00 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
86.
Antenna Package with Via Structure and Method of Formation Thereof
A semiconductor device comprises a semiconductor chip comprising a radio frequency (RF) circuit, a feedline structure coupled to the RF circuit, and an antenna structure comprising a main body stretching along a direction orthogonal to at least one side of a front side and a backside of the semiconductor device, wherein the antenna structure is coupled to the RF circuit through the feedline structure.
A microcontroller includes a plurality of (Intellectual Property) IP blocks each configured to perform one or more functions; a hardware power estimator circuit for estimating power of the microcontroller, the hardware power estimator including a hardware artificial neural network inlcuding a plurality of interconnected nodes arranged in one or more stages, wherein each individual stage comprises: a first input layer including values indicating activities of the microcontroller and/or indicating active cells of the microcontroller; a second input layer including a weighted set of values; an output layer including values calculated for the individual node stage; and at least one intermediate layer situated between the input layer and the output layer, wherein each node of the at least one intermediate layer comprises a multiply and adder (MADD) circuit that is configured to calculate a value for the respective node using values received from the first and second input layers.
In accordance with an embodiment, a method for digital-to-analog conversion includes: mapping a uniformly distributed input code to a non-uniformly distributed input code of a switched capacitor digital-to-analog converter (DAC), the non-uniformly distributed input code including a most significant code (MSC) and a least significant code (LSC); transferring a first charge from a set of DAC capacitors to a charge accumulator based on the MSC; forming a second charge based on the LSC; and transferring the second charge from the set of DAC capacitors to the charge accumulator, where each capacitor of the set of DAC capacitors is used for each value of the non-uniformly distributed input code, each capacitor of the set of DAC capacitors provides a same corresponding nominal charge within each value of the non-uniformly distributed input code, and where the same nominal charge is proportional to a value of the non-uniformly distributed input code.
A molded power semiconductor module includes: one or more power semiconductor dies; a molded body at least partially encapsulating each power semiconductor die and having opposing first and second sides, and lateral sides connecting the first and second sides; and first and second power contacts arranged laterally next to each other at a first one of the lateral sides of the molded body and electrically coupled to the power semiconductor die(s). The power contacts each have opposing first and second sides, each first side having an exposed part exposed from the molded body, each second side having a part that is arranged in a vertical direction below an outline of the respective exposed part of the first side and that is at least partially covered by a protrusion part of the molded body. The vertical direction is perpendicular to the first and second sides of the power contacts.
A power semiconductor device includes at a first side and electrically isolated from first and second load terminals, first control electrodes for controlling a load current in first semiconductor channel structures formed in an active region at the first side, and at a second side and electrically isolated from the first and second load terminals, second control electrodes for controlling the load current in second semiconductor channel structures formed in the active region at the second side. At the second side and in a contiguous area of modified control (AMC) belonging to the active region and having a lateral extension of at least 30% of a thickness of a semiconductor body of the device, either no second control electrodes are provided or the second control electrodes are less effective in removing free charge carriers out of the power semiconductor device than the second control electrodes outside the AMC.
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
91.
Batch Soldering of Different Elements in Power Module
An electronic device includes a substrate including first and second metal regions, a first passive device that includes a metal joining surface and is arranged on the substrate with the metal joining surface of the first passive device facing first metal region, a semiconductor die that includes a metal joining surface and is arranged on the substrate with the metal joining surface of the semiconductor die facing the second metal region, a first soldered joint between the metal joining surface of the first passive device and the first metal region; and a second soldered joint between the metal joining surface of the semiconductor die and the second metal region, wherein a minimum thickness of the first soldered joint is greater than a maximum thickness of the second soldered joint.
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different main groups of groups , or in a single subclass of , , e.g. forming hybrid circuits
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
A method of forming a semiconductor device includes providing a base substrate comprising SiC and a growth surface extending along a plane that is angled relative to a first crystallographic plane of the SiC from the base substrate, forming first and second trenches in the base substrate that extend from the growth surface into the base substrate, epitaxially forming a first SiC layer on the growth surface of the base substrate by a step-controlled epitaxy technique, and epitaxially forming a second SiC layer on the first SiC layer, wherein the first SiC layer is a layer of α-SiC, and wherein the second SiC layer is a layer of β-SiC.
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 29/04 - Semiconductor bodies characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
C30B 25/20 - Epitaxial-layer growth characterised by the substrate the substrate being of the same materials as the epitaxial layer
In some implementations, a device may identify a set of characteristics of a frame. The device may compute a first key index associated with the frame based on the set of characteristics and using a first key index function. The device may determine whether the first key index is associated with any collision entries from a set of collision entries. The device may determine a set of security parameters associated with the frame using a particular key index. The particular key index is either the first key index when the first key index is not associated with any collision entries from the set of collision entries, or is a second key index when the first key index is associated with a collision entry from the set of collision entries.
A semiconductor device includes an electronics carrier, an electrically conductive receptacle attached to a first pad of the electronics carrier, and an electrically conductive press-fit connector including a flange and a base portion extending from the flange to a first end of the press-fit connector, wherein the press-fit connector is in a secured position whereby the base portion is disposed within and securely retained by the receptacle, and wherein the base portion of the press-fit connector is configured to maintain vertical separation between the flange and an upper end of the receptacle in the secured position.
An integrated circuit includes a transistor, a first metallization layer above the transistor and electrically connected to the transistor, and a phase change switch, wherein at least a part of the phase change switch is provided below the first metallization layer, wherein the first metallization layer is provided laterally adjacent to the phase change switch, wherein the phase change switch comprises a heater, and wherein the heater and a part of the transistor are each provided in a lower-level interconnect layer of the integrated circuit.
H10N 70/00 - Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
H10N 70/20 - Multistable switching devices, e.g. memristors
96.
PACKAGE WITH ELECTRICALLY INSULATED CARRIER AND AT LEAST ONE STEP ON ENCAPSULANT
A package is disclosed. In one example, the package includes a first main face for mounting a heat sink and an opposing second main face for being mounted on a mounting base. The package comprises a carrier, an electronic component mounted at the carrier, and an encapsulant encapsulating at least part of the electronic component and at least part of the carrier. Electrically insulating material covers electrically conductive material of the carrier at said first main face. The encapsulant comprises at least one step at the first main face.
A method of fabricating a semiconductor device includes: epitaxially growing a multilayer Group-III nitride structure on a first surface of a substrate; removing portions of the multilayer structure to form a mesa arranged on the first surface; applying insulating material to the first surface of the substrate so that side faces of the mesa are embedded in the insulating material; forming an electrode on a top surface of the mesa; forming a via in the insulating material that extends from the top surface of the insulating material to the first surface of the substrate; inserting conductive material into the via to form a conductive via; applying an electrically conductive redistribution structure to the upper surface and electrically connecting the conductive via to the electrode; and successively removing portions of a second surface of the substrate, to expose the insulating material and form a worked second surface including the insulating material.
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
A semiconductor module includes: a printed circuit board having a first side and an opposite second side; a plurality of power semiconductor packages arranged over and electrically coupled to the first side of the printed circuit board, a first side of the power semiconductor packages facing the first side of the printed circuit board and an opposite second side being configured to be coupled to a heatsink; and at least one bus bar arranged over and electrically coupled to the first side of the printed circuit board. The bus bar is configured to carry a supply current and/or a ground current of at least some of the power semiconductor packages.
H01L 23/40 - Mountings or securing means for detachable cooling or heating arrangements
H05K 7/20 - Modifications to facilitate cooling, ventilating, or heating
H05K 3/32 - Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
H05K 1/18 - Printed circuits structurally associated with non-printed electric components
99.
Apparatus Including a Capacitor and a Coil, and a System Having Such an Apparatus
An apparatus is provided that includes a substrate. In addition, the apparatus includes a first electrically conductive path arranged in a second layer above the substrate and forming a first connection of the apparatus, and a second electrically conductive pad arranged in the second layer and forming a second connection of the apparatus. An electrically conductive element is arranged in a first layer spaced apart from the second layer. The electrically conductive element forms a first capacitor with either the first pad or the second pad. In addition, a first coil is arranged in the first layer, the second layer, or in both layers. A first end of the first coil is connected to the second pad.
Disclosed are a method and apparatus for estimating a rotor position angle of an electric machine, an electric machine control system comprising the apparatus, and a computer-readable storage medium. The method comprises obtaining a back emf of a stator of the electric machine; performing a second-order generalized integrator operation on the back emf, to obtain a signal with a phase lag of 90 degrees with respect to the back emf; dividing the phase-lagging signal by a resonant frequency of the back emf to obtain a stator flux linkage of the stator, then subtracting an inductive magnetic flux of the stator from the stator flux linkage to obtain a rotor flux linkage; and computing a rotor position angle based on the rotor flux linkage.
G01D 5/20 - Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using electric or magnetic means influencing the magnitude of a current or voltage by varying inductance, e.g. by a movable armature
G01B 7/30 - Measuring arrangements characterised by the use of electric or magnetic techniques for testing the alignment of axes
patents
