The present disclosure relates to authenticity and data security for bus-based communication networks in a vehicle. The present disclosure teaches a protocol frame, a sender on data link layer, and a receiver on data link layer providing such authenticity and data security as well as a communication network in a vehicle employing the protocol frame, the sender and the receiver according to the present disclosure.
An optical sensor includes a pixel including a photoactive region configured to convert photons into charge carriers, a first and a second modulation gate configured to be modulated for indirect time of flight measurement, a first and a second storage node arranged on opposite sides of the photoactive region, the first and second storage nodes being configured to pin electrons generated in the photoactive region when the first or the second modulation gate is active, respectively, and a first field plate arranged next to the first storage node and a second field plate arranged next to the second storage node. The first and second field plates are configured to be supplied with a negative bias voltage such that the first and second field plates provide electrical isolation for the first or the second storage node, respectively.
A monitoring system includes: a sensor configured to generate a sensor signal based on a measured property; a controller configured to communicate with the sensor; and a communication channel electrically coupled to the sensor and the controller for carrying electrical communications therebetween. The sensor includes a transmitter configured to transmit an electrical signal on the communication channel to the controller. The controller includes a processing circuit configured to receive the electrical signal, measure an actual signal function response of the electrical signal, correlate the actual signal function response with a reference signal function response to generate a correlation value, compare the correlation value and a correlation threshold to produce a comparison result, and detect a fault based on the comparison result indicating that the correlation value satisfies the correlation threshold.
H04L 67/12 - Protocols specially adapted for proprietary or special-purpose networking environments, e.g. medical networks, sensor networks, networks in vehicles or remote metering networks
G01R 31/52 - Testing for short-circuits, leakage current or ground faults
A semiconductor device includes a semiconductor wafer or a single semiconductor chip or die, and a layer stack. The layer stack comprises a first layer comprising NiSi, and a second layer comprising NiV, wherein the second layer is arranged between the first layer and the semiconductor wafer or single semiconductor chip or die.
Disclosed is a method for producing a semiconductor device, the method including forming a plurality of semiconductor arrangements one above the other, wherein forming each of the plurality of semiconductor arrangements includes forming a semiconductor layer, forming a plurality of trenches in a first surface of the semiconductor layer, and implanting dopant atoms of at least one of a first type and a second type into at least one of a first sidewall and a second sidewall of each of the plurality of trenches. Forming of at least one of the plurality of semiconductor arrangements further includes forming a protective layer covering mesa regions between the plurality of trenches of the respective semiconductor layer, and covering a bottom, the first sidewall and the second sidewall of each of the plurality of trenches that are formed in the respective semiconductor layer.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
A power stage includes: a first transformer; a second transformer; a third transformer; a GaN (gallium nitride) enhancement mode power transistor configured to conduct a load current when driven by a gate current derived from energy transferred by the first transformer; a GaN depletion mode transistor configured to turn off the GaN enhancement mode power transistor absent a threshold voltage applied across a gate and a source of the GaN depletion mode transistor; a voltage clamping device or circuit configured to turn off the GaN depletion mode transistor when reverse biased by a bias current derived from energy transferred by the second transformer; and a GaN enhancement mode transistor configured to turn on the GaN depletion mode transistor when driven by a gate current derived from energy transferred by the third transformer.
H03K 17/16 - Modifications for eliminating interference voltages or currents
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
H02M 7/06 - Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes without control electrode or semiconductor devices without control electrode
7.
DEVICE FOR CONTROLLING TRAPPED IONS WITH INTEGRATED WAVEGUIDE
Joanneum Research Forschungsgesellschaft mbH (Austria)
Universität Innsbruck (Austria)
Inventor
Rössler, Clemens
Lamprecht, Bernhard
Monz, Thomas
Schindler, Philipp
Abstract
A micro-fabricated device for controlling trapped ions includes a first substrate having a main surface. A structured first metal layer is disposed over the main surface of the first substrate. The structured first metal layer includes electrodes of at least one ion trapping zone configured to trap an ion in a space above the structured first metal layer. A dielectric element is fixedly attached to the first substrate. The dielectric element includes at least one short-pulse-laser direct written (SPLDW) waveguide configured to direct laser light towards an ion trapped in the at least one ion trapping zone.
A method for storing data bits in memory cells, in which the data bits have at least one byte-filling bit, where at least one predefined functionality for a subset of the data bits is coded in the at least one byte-filling bit, and in which the data bits are stored in the memory cells. A method for reading data bits from memory cells, in which the data bits have at least one byte-filling bit, where at least one predefined functionality for a subset of the data bits is coded in the at least one byte-filling bit, and in which the data bits are read from the memory cells based on the coded predefined functionality. Corresponding apparatuses and memories are also disclosed.
A system including circuitry to communicate data across an isolation barrier of a switch driver circuit. For switch driver circuits with galvanic isolation, the circuitry of this disclosure uses the unavoidable common mode voltages caused by the coupling capacitances of the data transfer circuit to evaluate the common mode voltage characteristics, such as the slew rate of a switching event. The switch driver circuit of this disclosure may include a common mode voltage detector to detect and measure features of the unavoidable common mode voltage during a switching event, such as voltage amplitude and slew rate. The common mode voltage detector may couple to a communication interface that provides the common mode voltage information to a controller for the switch driver circuit. In some examples, based on the received information, the controller may adjust the operation of the switching circuit.
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
H02M 1/38 - Means for preventing simultaneous conduction of switches
H02P 27/08 - Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using dc to ac converters or inverters with pulse width modulation
H03K 17/689 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors with galvanic isolation between the control circuit and the output circuit
10.
SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING A CAVITY IN A TRENCH
In an embodiment, a semiconductor device is provided that includes a semiconductor substrate having a first major surface, one or more trenches formed in the first major surface and having a base and a side wall extending from the base to the first major surface, an anchoring layer, and a conductive member arranged in the one or more trenches and spaced apart from the side wall of the one or more trenches by a cavity formed in the one or more trenches . The anchoring layer extends from the first major surface of the semiconductor substrate over the cavity and onto an upper surface of the conductive member.
A sensor module may include a back-bias magnet with a magnetization in a first direction. The sensor module may include a sensor chip including a first set of tunnel magnetoresistive (TMR) sensing elements. The sensor chip may be configured to determine a characteristic of a first magnetic field component using the first set of TMR sensing elements, and to generate a sensor signal based at least in part on the characteristic of the first magnetic field component. A value of the sensor signal may correspond to a linear position of a ferromagnetic object.
G01D 5/16 - Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using electric or magnetic means influencing the magnitude of a current or voltage by varying resistance
A semiconductor die includes: a semiconductor substrate; a first contact pad structure above the semiconductor substrate, the first contact pad structure including a metal contact pad configured for electrical contact and a metal layer adjoining an underside of the metal contact pad and jutting out beyond an edge of the metal contact pad; and a first optical detection marker in a periphery of the first contact pad structure and having a different contrast than the metal contact pad. The first optical detection marker includes a region of the metal layer that is adjacent to the edge of the metal contact pad and unobstructed by the metal contact pad so as to be optically visible in a plan view of the semiconductor die. A method of producing the semiconductor die is also described.
A unidirectional power switch includes: a normally-on switch device having a normally-on gate, a source, and a drain; a normally-off switch device having a normally-off gate, a source, and a drain, the drain of the normally-off switch device being electrically connected to the source of the normally-on switch device in a cascode configuration; a first source terminal electrically connected to the source of the normally-off switch device; a second source terminal electrically connected to the source of the normally-on switch device; and a drain terminal electrically connected to the drain of the normally-on switch device. The unidirectional power switch is configurable as either a normally-off unidirectional switch or a normally-on unidirectional switch, depending on a configuration of external gate driver connections to the source terminals. Additional power switch embodiments and related methods of configuring the power switches are described, including a configurable bidirectional power switch.
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
A gate driver comprises an input terminal, an output terminal, and first logic configured to generate an output drive signal at the output terminal corresponding to an input drive signal received at the input terminal. A blanking unit is configured to connect a current sense terminal of the gate driver to a reference supply terminal responsive to a low value of the output drive signal and disconnect the current sense terminal from the reference supply terminal after a predetermined delay period responsive to a high value of the output drive signal.
A method of forming a semiconductor package includes producing a package substrate that includes an interior laminate layer, a first metallization layer disposed below the interior laminate layer, and a second metallization layer disposed above the interior laminate layer, providing a first load terminal on a first surface of the first semiconductor die and a second load terminal on a second surface of the first semiconductor die; and a liner of dielectric material on the first semiconductor die; providing a liner of dielectric material on the first semiconductor die; embedding the first semiconductor die within the interior laminate layer such that the first surface of the first semiconductor die faces the second metallization layer, and wherein the liner of dielectric material is disposed on a corner of the first semiconductor die that is between the first and second load terminals of the first semiconductor die.
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
16.
POWER ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME
A power electronic device includes: a carrier having at least two die mounting areas; a power semiconductor die(s) mounted on the carrier at a first mounting area and having a first side facing the carrier and an opposite second side, a second die mounting area being free of any semiconductor die; and a contact clip arranged over the die and second die mounting area. The contact clip is at least partially arranged in a first plane, with a first part over the die being bent downwards such it is arranged in a second plane below the first plane and coupled to the second side of the die. A second part of the contact clip over the second die mounting area is bent upwards such that the second part is arranged in a third plane above the first plane, or is free of any bend and arranged in the first plane.
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
A phase change switching device includes a substrate comprising a main surface, an RF input pad and a plurality of RF output pads disposed over the main surface, and phase change switch connections between the RF input pad and each of the RF output pads, wherein the phase change switch connections each include a phase change material and a heating element thermally coupled to the phase change material, wherein each of the RF output pads are arranged outside of an outer perimeter of the RF input pad, and wherein plurality of RF output pads at least partially surrounds the outer perimeter of the RF input pad.
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
18.
GATE CHARGE AND LEAKAGE MEASUREMENT TEST SEQUENCE FOR SOLID STATE DEVICES
An apparatus comprises a switch and a capacitor connected to the switch and to a gate driver that drives a gate of a solid state device. The gate driver is operated to perform a test sequence for the solid state device. The test sequence includes turning on a switch and charging a capacitor to a supply voltage during an initial phase. During a first phase, the switch and the solid state device are turned off, the gate driver is disconnected from the supply voltage, and the gate driver drives the gate of the solid state device based at least upon a charge of the capacitor. During a second phase, the gate driver drives the gate of the solid state device to turn on the solid state device. A gate charge at the gate of the solid state device is measured as an operational state of the solid state device.
A controller may receive a message provided by a network node included in an in-vehicle communication network. The controller may identify one or more characteristics of the message, the one or more characteristics indicating at least one of a message type of the message, a security property of the message, or a secure zone (SZ) associated with the message. The controller may determine a priority of the message based at least in part on the one or more characteristics. The controller may provide the message to an output buffer based at least in part on the priority of the message, the output buffer being one of a plurality of output buffers.
H04L 67/12 - Protocols specially adapted for proprietary or special-purpose networking environments, e.g. medical networks, sensor networks, networks in vehicles or remote metering networks
A system may include a set of light-emitting diode (LED) circuits, wherein each LED circuit of the set of LED circuits comprises: a first electrode; a set of second electrodes; and a set of pixels, wherein each pixel of the set of pixels corresponds to a combination of the first electrode and a respective second electrode of the set of second electrodes. A plurality of pixels may include the set of pixels corresponding to each LED circuit of the set of LED circuits. The first electrode may be located within a center portion of the respective LED circuit, and each second electrode of the set of second electrodes may be located within an outer portion the respective LED circuit. The system also includes a controller circuit configured to control whether each pixel of the plurality of pixels is activated or deactivated.
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different main groups of groups , or in a single subclass of , , e.g. forming hybrid circuits
G09G 3/32 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
H01L 25/075 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 27/15 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier, specially adapted for light emission
H01L 33/62 - Arrangements for conducting electric current to or from the semiconductor body, e.g. leadframe, wire-bond or solder balls
21.
SEMICONDUCTOR CIRCUIT ARRANGEMENT AND METHOD FOR A SEMICONDUCTOR CIRCUIT ARRANGEMENT
A semiconductor circuit arrangement includes a substrate, at least two first stress-sensitive elements in a first region of the substrate and at least two second stress-sensitive elements in a second region of the substrate. The first stress-sensitive elements each have an electrical characteristic which is dependent on a first component and a second component of a mechanical stress tensor in the first region. The second stress-sensitive elements each have an electrical characteristic which is dependent on a first component and a second component of a mechanical stress tensor in the second region. The semiconductor circuit arrangement includes a measuring circuit configured, based on the respective electrical characteristics of the first stress-sensitive elements and of the second stress-sensitive elements, to determine a stress difference between the first components in the first and second regions and a stress difference between the second components in the first and second regions.
G01L 1/22 - Measuring force or stress, in general by making use of electrokinetic cells, i.e. liquid-containing cells wherein an electrical potential is produced or varied upon the application of stress using resistance strain gauges
G01L 1/18 - Measuring force or stress, in general using properties of piezo-resistive materials, i.e. materials of which the ohmic resistance varies according to changes in magnitude or direction of force applied to the material
22.
MAGNETIC CURRENT SENSOR INTEGRATION INTO HIGH CURRENT CONNECTOR DEVICE WITH MOUNTING FOR TORQUE STABILIZATION
A power connector is provided that is configured to conduct a current. The power connector includes a base structure, an extension structure, and a connector head structure that define a current path for the current. The extension structure is coupled to and extends between the base structure and the connector head structure. The connector head structure includes a bore-hole that vertically extends into the connector head structure toward the base structure. The bore-hole is configured to receive a fastener for coupling the power connector to an electrical interface of a device. The connector head structure has a mechanical engagement feature configured to mechanically engage with a torque stabilization tool during a fastening of the fastener to the connector head structure in order to prevent a torque applied by the fastening of the fastener from being transferred to the extension structure.
G01R 1/04 - Housings; Supporting members; Arrangements of terminals
G01R 15/20 - Adaptations providing voltage or current isolation, e.g. for high-voltage or high-current networks using galvano-magnetic devices, e.g. Hall-effect devices
H01R 4/30 - Clamped connections; Spring connections using a screw or nut clamping member
H01R 13/66 - Structural association with built-in electrical component
Digital-to-analog converter circuitry comprising a sequence of multiple current drive modules. The sequence may include a first current drive module and a second current drive module of a digital-to-analog converter. The first current drive module is switchable between: i) a first mode of producing a first reference current that is mirrored by a second current drive module coupled to the first current drive module; and ii) a second mode of mirroring a second reference current that is produced by the second current drive module or a third current drive module coupled to the first current drive module.
A layer stack is formed that includes a device layer and an insulator layer. The device layer includes electronic elements. The insulator layer is adjacent to a back surface of the device layer. A spacer disk is adhesive bonded on the layer stack on a side opposite the device layer. The spacer disk and the layer stack form a wafer composite. The wafer composite is divided into a plurality of individual semiconductor chips. Each semiconductor chip includes a portion of the layer stack and a portion of the spacer disk.
H01L 21/784 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, each consisting of a single circuit element the substrate being a semiconductor body
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 23/29 - Encapsulation, e.g. encapsulating layers, coatings characterised by the material
H01L 23/49 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of soldered or bonded constructions wire-like
25.
GATE DRIVER CIRCUIT AND POWER SWITCHING ASSEMBLY WITH GATE DRIVER CIRCUIT
A power switching assembly includes a first driver circuit and a second driver circuit. The first driver circuit is supplied via a first internal supply node and a first reference node and drives a first gate signal. The second driver circuit is supplied via a second internal supply node and a second reference node and drives a second gate signal. The first gate signal and the second gate signal are configured to be in phase with each other. The first reference node and the second reference node are separated. A first buffer capacitor is electrically connected between the first internal supply node and the first reference node. A second buffer capacitor electrically connected between the second internal supply node and the second reference node.
H03K 17/06 - Modifications for ensuring a fully conducting state
H03K 17/082 - Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
26.
SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING THEREOF
The application relates to a power semiconductor device, including: a semiconductor body having a front side coupled to a frontside metallization and a backside coupled to a backside metallization; and an active region with a plurality of transistor cells. The frontside metallization includes a first load terminal structure and a control terminal structure. At least one of the first layer and the second layer is laterally segmented, with a first segment being part of the first load terminal structure and a second segment being part of the control terminal structure.
Disclosed herein is a power semiconductor device including a semiconductor body, a first load terminal, a second load terminal, an active region, an edge termination region, and a thin film layer that includes a bulk material and a laminar filler compound. Furthermore, a method of producing such a power semiconductor device is described herein, the method including: providing a thin film including a mixture of a bulk material component and a laminar filler compound onto a surface of at least parts of the edge termination region and/or over at least parts of the first load terminal; and curing the obtained mixture of the bulk material and laminar filler compound to generate a thin-film layer that includes a bulk material and a laminar filler compound.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
A silicon carbide device includes a silicon carbide substrate, a contact layer located on the silicon carbide substrate and including nickel and silicon, a barrier layer structure including titanium and tungsten, and a metallization layer comprising copper, wherein the contact layer is located between the silicon carbide substrate and at least a part of the barrier layer structure, wherein the barrier layer structure is located between the silicon carbide substrate and the metallization layer, wherein the metallization layer is configured as a contact pad of the silicon carbide device.
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
A system includes a first membrane, a second membrane and a third membrane spaced apart from one another, wherein the second membrane is between the first membrane and the third membrane, and the second membrane comprises a plurality of openings, a sealed low pressure chamber between the first membrane and the third membrane, and a plurality of electrodes in the sealed low pressure chamber
In an embodiment, a method includes: receiving radar digital data; processing the radar digital data with a plurality of sine filters to generate a respective plurality of range-slow-time data, where each sine filter is associated with a respective range zone of a plurality of range zones; generating a first presence score based on a first range-slow-time data of the plurality of range-slow-time data, where the first range-slow-time data is associated with the first range zone; and when the first presence score is higher than a predetermined threshold, generating a plurality of synthetic antennas based on the first range-slow-time data, performing angle estimation based on the plurality of synthetic antennas to generate first probability values for a plurality of angle zones associated with the first range zone, and updating an occupancy grid map based on the first probability values.
A voltage regulator module may comprise a control signal generation module, a power stage, and a routing network. The control signal generation module may be configured to, in a first mode of operation, generate an internal control signal for controlling the power stage. The routing network may be configured to, in the first mode of operation, apply the internal control signal to a control node of the power stage. The routing network may be configured to, in a second mode of operation, electrically connect said control node to an input pin of the voltage regulator module such that the power stage is controllable by an external control signal applied to said input pin. Thus, in the second mode of operation, it becomes possible to control the power stage directly via the external control signal and use this power stage e.g. as a single phase of a multi-phase power converter.
H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
H02M 3/156 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
32.
Semiconductor Device Comprising a Leadframe Adapted for Higher Current Output or Improved Placement of Additional Devices
A semiconductor device comprises a leadframe comprising a die pad and a plurality of leads, a semiconductor die disposed on the die pad, the semiconductor die including a contact pad on a first main face thereof, and one or more bond wires connected with the contact pad, wherein a lead of the plurality of leads is bent back and connected with at least one first bond wire of the one or more bond wires.
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
33.
TRENCH GATE NMOS TRANSISTOR AND TRENCH GATE PMOS TRANSISTOR MONOLITHICALLY INTEGRATED IN SAME SEMICONDUCTOR DIE
A semiconductor die includes: a silicon substrate; a trench gate NMOS transistor formed in a first device region of the silicon substrate; a trench gate PMOS transistor formed in a second device region of the silicon substrate and electrically connected to the trench gate NMOS transistor; and an isolation structure interposed between the first device region and the second device region. Methods of monolithically integrating the trench gate NMOS transistor and the trench gate PMOS transistor in the same semiconductor die are also described.
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
H01L 21/266 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation using masks
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H02M 1/088 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
34.
POWER SEMICONDUCTOR DEVICE, MEASUREMENT SYSTEM AND METHOD FOR DETERMINING A CURRENT OF A POWER SEMICONDUCTOR DEVICE
A power semiconductor device is proposed. The power semiconductor device includes a semiconductor body and a wiring area over a first surface of the semiconductor body. The power semiconductor device further includes a bipolar power semiconductor element including a first load electrode in the wiring area, an active area in the semiconductor body, and a second load electrode at a second surface of the semiconductor body. The power semiconductor device further includes a current sensing element including a pn or pin junction. The power semiconductor device further includes an optical window configured to allow electromagnetic radiation caused by an on-current of the bipolar power semiconductor element to pass to the current sensing element.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
A system may comprise a power module including a power switch, a driver circuit configured to control an ON state and an OFF state of the power switch, and a processor configured to control the driver circuit. The processor may be configured to receive a voltage associated with the power switch in the ON state and determine a state of health (SOH) for the power switch based on the voltage and a regression model associated with the power switch.
This disclosure includes multiple assemblies, sub-assemblies, etc., as well as one or more methods of fabricating same. For example, a first assembly includes a first circuit board. The first circuit board further includes first connector elements disposed on a first edge of the first circuit board and second connector elements disposed on a second edge of the first circuit board. The first edge may be disposed substantially opposite the second edge on the first circuit board. The apparatus may further include first circuitry affixed to the first circuit board. The first edge of the first circuit board aligns with a first axial end of the first circuitry and the second edge of the first circuit board aligns with a second axial end of the first circuitry. The first assembly is used to fabricate a second assembly.
An apparatus includes a calibration circuit operative to produce an error signal indicative of an error associated with a current generator circuit generating a secondary current from a reference current. The secondary current is proportional to the reference current. The calibration circuit derives an adjustment value from the error signal and applies the adjustment value to the current generator circuit. Application of the adjustment value reduces a magnitude of the error signal.
G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
G05F 1/46 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc
An ion movement control apparatus with low pass filter switch , including a digital to analog converter (DAC) connected to a first port and enabled to provide a DAC voltage, an electrode element connected to a second port, the electrode element configured to provide an electrical field for controlling a position of an ion, and a filter switch between the first port and the second port and having a filter leg and a bypass leg in parallel, the filter leg having a filter leg switch and a filter portion between the first port and the second port and selectively coupling the first port through the filter leg to the second port to slow a voltage transient of the DAC voltage to the electrode element, and where the bypass leg has a bypass leg switch that selectively couples the first port directly to the second port.
A semiconductor device includes a semiconductor substrate having a major surface, a trench extending from the major surface into the substrate and having a base and a side wall extending form the base to the major surface, and a field plate arranged in the trench and having a height f. The field plate is electrically insulated from the substrate by a dielectric structure arranged in the trench. The dielectric structure includes a first portion having a first dielectric constant and a second portion having a second dielectric constant higher than the first dielectric constant. The first portion is arranged in a lower portion of the trench. The second portion is arranged in an upper portion of the trench, a thickness x, and overlaps the height of the field plate by a distance v1, where f*0.1≤v1≤f*0.8 or f*0.3≤v1≤f*0.6.
A chip package is provided. The chip package includes an electrically conductive carrier structure, a first power chip on the carrier structure having a control contact pad and a second power chip on the carrier structure having a control contact pad. The first and second power chips are arranged with their respective control contact pad facing a redistribution layer. A logic chip is arranged with a logic contact pad facing a redistribution layer, wherein the redistribution layer connects the logic contact pad with the respective control pads of the power chips.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
A package is disclosed. In one example, the package comprises a carrier, an electronic component mounted on or above the carrier, an electrically insulating and thermally conductive layer on at least part of an upper main surface of the electronic component, and a metal block on the electrically insulating and thermally conductive layer. An encapsulant at least partially encapsulates the electronic component, the carrier, the electrically insulating and thermally conductive layer and the metal block so that an upper main surface of the metal block is exposed beyond the encapsulant.
H01L 23/373 - Cooling facilitated by selection of materials for the device
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
42.
FIELD EFFECT TRANSISTOR COMPRISING EDGE TERMINATION AREA
A field effect transistor (FET) is proposed. The FET includes a transistor cell area in a silicon carbide (SiC) semiconductor body. An edge termination area surrounds the transistor cell area. A source contact is arranged over a first surface of the SiC semiconductor body. A drain contact is arranged on a second surface of the SiC semiconductor body. The FET further includes a drift region of a first conductivity type between the first surface and the second surface. Along a lateral direction, a net doping concentration in the drift region is larger in the transistor cell area than in the edge termination area.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
A chip assembly having a carrier having a cavity and at least one carrier contact, a chip arranged in the cavity and having at least one chip contact, and a wirebond wire, which electrically conductively connects the at least one chip contact to the at least one carrier contact, wherein the wirebond wire is flat-pressed in at least one subregion.
According to various embodiments, a circuit is described including a plurality of scan flip-flops including a sequence of scan flip-flops, wherein at least some scan flip-flops of the sequence are wrapper scan flip-flops, and including, for each scan flip-flop of at least a subset of the scan flip-flops, at the wrapper scan flip-flop's test input a respective test input circuit configured to, when supplied with a mode control signal having a first value, connect the test input to the output of the preceding wrapper scan flip-flop such that the test input of the flip-flop is supplied with the content of the preceding wrapper scan flip-flop and when supplied with the mode control signal having a second value, connect the test input to an output of a part of the circuit such that the test input of the flip-flop is supplied with a value depending on a test result.
A semiconductor package includes: a semiconductor die attached to a leadframe and having a first bond pad at a side of the semiconductor die facing away from the leadframe; a metal clip having a first bonding region attached to the first bond pad of the semiconductor die by a plurality of first wire bonds which extend through a plurality of first openings in the first bonding region of the metal clip, the plurality of first wire bonds forming a joint between the metal clip and the first bond pad of the semiconductor die; and a joint between the plurality of first wire bonds and the metal clip at a side of the metal clip facing away from the semiconductor die. Additional semiconductor package embodiments and related methods of manufacture are also described.
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
46.
OFFSET CORRECTION IN A VOLTAGE CONTROLLED MAGNETORESISTIVE SENSOR
In some implementations, a magnetic sensor may apply an electrical signal across a tunnel barrier layer of a tunnel magnetoresistive (TMR) sensing element. The electrical signal may have a first signal level during a first time period and a second signal level during a second time period. The second signal level may be different from the first signal level. The magnetic sensor may generate an offset-corrected sensor signal based on a sensor signal that results from applying the electrical signal across the tunnel barrier layer of the TMR sensing element.
According to various embodiments, a circuit is described including a plurality of scan flip-flops including a sequence of input wrapper scan flip-flops and including, for each input wrapper scan flip-flop of at least a subset of the input wrapper scan flip-flops, at the input wrapper scan flip-flop's test input a respective test input circuit configured to, when supplied with a mode control signal having a first value, connect the test input to the output of the preceding input wrapper scan flip-flop such that the test input of the flip-flop is supplied with the content of the preceding input wrapper scan flip-flop and when supplied with the mode control signal having a second value, connect the test input to an output of a part of the circuit such that the test input of the flip-flop is supplied with a value depending on a test result.
A circuit board assembly may include a first circuit board including a first slot. The circuit board assembly may include a second circuit board. The first circuit board may be interlocked with the second circuit board via interlocking provided by the second circuit board into the first slot.
A signal adjustor receives a first signal such as feedback associated with generation of an output voltage. The output voltage is regulated based on a selected setpoint reference voltage. The signal adjustor maps a magnitude of the selected setpoint reference voltage to a first set of signal adjustment information amongst multiple sets of signal adjustment information. The signal adjustor then applies the first signal adjustment information to the first signal to produce a second signal.
G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
G05F 1/46 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc
50.
ULTRASONIC TOUCH SENSORS AND CAPACITIVE PRESSURE SENSING MICROELECTROMECHANICAL SYSTEM FUSION
A touch sensor includes a touch structure including a touch interface and an inner interface arranged opposite to the touch interface; a capacitive ultrasonic transmitter arranged inside an enclosed interior volume and configured to transmit an ultrasonic transmit wave towards the touch structure; a capacitive ultrasonic receiver arranged inside the enclosed interior volume and configured to receive at least one ultrasonic reflected wave produced from the ultrasonic transmit wave via internal reflection; a coupling medium that fills an area between the inner interface and the capacitive ultrasonic receiver, wherein an external force applied to the touch interface is configured to impart an internal pressure onto the capacitive ultrasonic receiver through the coupling medium; and a sensor circuit configured to convert the at least one ultrasonic reflected wave into a measurement signal and detect the external force based on the measurement signal.
A transistor device includes: a semiconductor substrate having a doping concentration of a first dopant type; a highly doped source region of a second dopant type formed in a first surface of the semiconductor substrate; a first highly doped drain region of the second dopant type formed in the first surface; a gate structure arranged on the first surface and including a gate electrode formed on the first surface; and a first lightly doped region formed in the first surface and extending from the highly doped source region under the gate electrode. A channel region extends between the first lightly doped region and the highly doped drain region. The channel region has an average doping level of the first dopant type of n×10x that varies by less than 0.5×n×10X between the first lightly doped region and the highly doped drain region along the lateral direction parallel to the first surface.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
A semiconductor device includes a semiconductor die comprising a radio frequency (RF) circuit, a first dielectric layer disposed over a first surface of the semiconductor die, an antenna layer disposed over a surface of the first dielectric layer, and an antenna feeding structure coupling the antenna layer to the RF circuit of the semiconductor die, wherein the semiconductor die comprises a via, and the antenna feeding structure comprises a first portion arranged within the opening of the semiconductor die and extending to the first surface of the semiconductor die, and a second portion arranged through the first dielectric layer.
H01Q 1/22 - Supports; Mounting means by structural association with other equipment or articles
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
An electronic device includes an interface configured to receive telemetry information for one or more power semiconductor devices and a data acquisition and processing unit. The data acquisition and processing unit may be configured to increase a gate voltage above a maximum permitted level for each of the one or more power semiconductor devices having a current slew rate that exceeds a predetermined level as determined by the telemetry information. The data acquisition and processing unit may be configured to increase a gate voltage above a maximum permitted level for each of the one or more power semiconductor devices having a temperature that exceeds a predetermined level as determined by the telemetry information. An electronic system that includes the electronic device is also described.
H04Q 9/00 - Arrangements in telecontrol or telemetry systems for selectively calling a substation from a main station, in which substation desired apparatus is selected for applying a control signal thereto or for obtaining measured values therefrom
The disclosure is directed to the use of an externally-supplied control current to control the adjustment of an internal supply voltage generated via voltage regulator circuitry, which may be identified with an integrated circuit (IC) chip. The configuration of the voltage regulator circuitry functions to establish a linear relationship between the control current and the internal voltage supply. This configuration enables setting the control current to a predetermined value, causing the supply voltage to deviate in a predictable and controllable manner, and thus facilitating verification of the IC chip's internal voltage supply test circuitry. Furthermore, because the control current used for this purpose is relatively small (e.g. on the order of microamps), existing on chip test architecture, which may accommodate such low level currents, may be re-used for the selective routing of the control current for such IC testing.
G05F 1/46 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc
G05F 1/565 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
55.
Method for Fabricating a Power Semiconductor Device
A method for fabricating a SiC power semiconductor device includes: providing a SiC power semiconductor die; depositing a metallization layer over the power semiconductor die, the metallization layer including a first metal; arranging the power semiconductor die over a die carrier such that the metallization layer faces the die carrier, the die carrier being at least partially covered by a plating that includes Ni; and diffusion soldering the power semiconductor die to the die carrier such that a first intermetallic compound is formed between the power semiconductor die and the plating, the first intermetallic compound including Ni3Sn4.
A semiconductor device includes a transistor. The transistor includes gate trenches formed in a semiconductor substrate, extending in a first horizontal direction and patterning the semiconductor substrate into ridges. The ridges are arranged between two adjacent gate trenches, respectively. The transistor further includes a gate electrode arranged in at least one of the gate trenches, a source region of a first conductivity type, a channel region, and a drift region of the first conductivity type. The source region, channel region and a part of the drift region are arranged in the ridges. The gate electrode is insulated from the channel region and the drift region. The channel region includes a doped portion of a second conductivity type. A doping concentration of the doped portion decreases in a second horizontal direction intersecting the first horizontal direction from a region close to the gate electrode to a central portion of the ridge.
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
An antenna structure for a contactless wearable structure having a plurality of antenna tracks on the substrate, the opposite ends of which are connectable to form an antenna when the substrate is bent, a plurality of capacitor elements on the substrate that are couplable to the antenna for adjusting the resonance frequency of the antenna, and at least one predefined separation region, by means of which it is possible to adjust which of the plurality of capacitor elements are electrically conductively connectable to the antenna when the substrate is bent, in order to form at least one capacitor with a predetermined total capacitance that is electrically conductively coupled to the antenna.
A silicon-controlled rectifier includes a semiconductor body including a first main surface, an active device region, a first, a second, a third and a fourth surface contact area at the first main surface and arranged directly one after another along a first lateral direction, wherein the semiconductor body is electrically contacted at each of the first to fourth surface contact areas, and a first, a second, a third and a fourth SCR region, wherein the first and third SCR regions are of a first conductivity type and directly adjoin the first and third surface contact areas, respectively, and wherein the second and fourth SCR regions are of a second conductivity type and directly adjoin the second and fourth surface contact areas, respectively, wherein the first SCR region is electrically connected to the fourth SCR region, and the second SCR region is electrically connected to the third SCR region.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 29/74 - Thyristor-type devices, e.g. having four-zone regenerative action
59.
MULTIPLE COBALT IRON BORON LAYERS IN A FREE LAYER OF A MAGNETORESISTIVE SENSING ELEMENT
A tunnel magnetoresistive (TMR) sensing element may include a free layer. The free layer of the TMR sensing element may include a first cobalt iron boron (CoFeB) layer, an interlayer over the first CoFeB layer, a second CoFeB layer over the interlayer, and a nickel iron (NiFe) layer over the second CoFeB layer.
According to some embodiments, a method for manufacturing a semiconductor device is provided. One or more first implantation processes are performed to form an implanted region, of a first conductivity type, in a semiconductor body. A trench is formed in the semiconductor body. After forming the trench, a second implantation process is performed to form a current spread region, of a second conductivity type, in the semiconductor body. The second implantation process includes implanting first dopants, through a top surface of the semiconductor body, to form a first portion of the current spread region, and implanting second dopants, through a bottom of the trench, to form a second portion of the current spread region. A gate structure is formed in the trench. A vertical position of the first portion of the current spread region matches a vertical position of the gate structure. The second portion of the current spread region underlies the gate structure.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
A driver system includes a first half-bridge that generates a first load current at a first output node, a second half-bridge that generates a second load current at a second output node, a first voltage charging device coupled to the first output node, and a second voltage charging device coupled to the second output node. A method of detecting a short circuit condition in the driver system includes detecting a first charging time at which a first charging voltage of the first voltage charging device is charged to a first threshold voltage; detecting a second charging time at which a second charging voltage of the second voltage charging device is charged to a second threshold voltage; and detecting the short circuit condition on a condition that a time difference between the first charging time and the second charging time is less than a time difference threshold.
H03K 17/081 - Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
H02J 7/00 - Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
H02M 7/5387 - Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
H02P 27/08 - Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using dc to ac converters or inverters with pulse width modulation
62.
Ultrasonic touch sensor using capacitive cross-talk
A touch sensor includes a touch structure; a signal generator configured to generate an excitation signal; a transmitter configured to receive the excitation signal and transmit an ultrasonic transmit wave towards the touch structure based on the excitation signal; a receiver configured to receive an ultrasonic reflected wave produced by a reflection of the ultrasonic transmit wave at the touch structure, wherein the transmitter and the receiver are coupled by a capacitive path, the receiver is configured to be influenced by the excitation signal whereby the excitation signal induces a capacitive cross-talk on the capacitive path, and the receiver is configured to generate a measurement signal representative of the capacitive cross-talk; and a measurement circuit coupled to the receiver and configured to perform a comparison of the measurement signal with a threshold to determine whether a no-touch event or a touch event has occurred at the touch interface.
A chip package is provided. The chip package includes a first chip, a second chip, an electrically conductive structure to which the first chip and the second chip are mounted, at least one contact terminal for electrically contacting the first chip and/or the second chip, and encapsulation material at least partially encapsulating the first chip, the second chip, and the electrically conductive structure. The encapsulation material forms a chip package body from which the at least one contact terminal protrudes. At least a portion of the electrically conductive structure forms a portion of an outer surface of the chip package body.
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
64.
SENSOR DEVICES HAVING AN ACOUSTIC COUPLING MEDIUM, AND ASSOCIATED MANUFACTURING METHODS
A sensor device contains at least one sensor chip having at least one MEMS structure arranged at a main surface of the at least one sensor chip, wherein the at least one sensor chip is configured to transmit ultrasonic signals and/or to receive ultrasonic signals. The sensor device further contains an acoustic coupling medium arranged selectively on the at least one MEMS structure, wherein the acoustic coupling medium is configured to decouple an ultrasonic signal to be emitted from the at least one MEMS structure and/or to inject a received ultrasonic signal into the at least one MEMS structure. The acoustic coupling medium only partially covers the main surface of the at least one sensor chip.
A circuit includes a cross-talk compensation component including a power profile reconstruction component for reconstructing the power profile of a digital microphone coupled to a microelectromechanical (MEMS) device, wherein the power profile represents power consumption of the digital microphone over time between at least two operational modes of the digital microphone, and a reconstruction filter for modeling thermal and/or acoustic properties of the digital microphone; and a subtractor having a first input for receiving a signal from the digital microphone, a second input coupled to the cross-talk compensation component, and an output for providing a digital output signal.
B81B 7/02 - Microstructural systems containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems (MEMS)
H04R 3/06 - Circuits for transducers for correcting frequency response of electrostatic transducers
The described techniques address issues associated with hybrid current or magnetic field sensors used to detect both low- and high-frequency magnetic field components. The hybrid sensor implements a DC component rejection path in the high-frequency magnetic field component path. Both digital and analog implementations are provided, each functioning to generate a DC component cancellation signal to at least partially cancel a DC component of a current signal generated via the high-frequency magnetic field component path. The hybrid sensor provides a high-bandwidth, high-accuracy, and low DC offset hybrid current solution that also eliminates the need for DC decoupling capacitors in the high-frequency path. A modification is also described for implementing a Sigma-Delta (ΣΔ) quantization noise reduction path to reduce the quantization noise and to improve accuracy.
G01D 5/14 - Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using electric or magnetic means influencing the magnitude of a current or voltage
A test arrangement for testing an integrated circuit is described wherein the test arrangement comprises a test pattern generator configured to generate a sequence of test patterns, a memory storing an indication for each of a plurality of groups of one or more of the test patterns, whether to use the group of test patterns for testing an integrated circuit and a controller configured to, for each of the test patterns, control the test pattern generator to feed the test pattern to the integrated circuit if the test pattern belongs to a group that should be used for testing the integrated circuit and to skip the test pattern in the testing of the integrated circuit if the test pattern belongs to a group that should not be used for testing the integrated circuit.
A molded package includes: a semiconductor die; a substrate attached to a bottom side of the semiconductor die; an electrically conductive clip attached to a top side of the semiconductor die; and a mold compound encapsulating the semiconductor die. A top side of the electrically conductive clip faces away from the semiconductor die and has an exposed flat surface that overlays the semiconductor die and is not covered by the mold compound. A bottom side of the electrically conductive clip faces the semiconductor die and has a convex curved surface that is attached to the top side of the semiconductor die. Along a vertical cross-section of the electrically conductive clip from the exposed flat surface to the convex curved surface, the electrically conductive clip has a plano-convex shape delimited by the exposed flat surface and the convex curved surface. A method of producing the molded package is also described.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
In an embodiment, a semiconductor device includes: a main bi-directional switch formed on a semiconductor substrate and including first and second gates, a first source electrically connected to a first voltage terminal, a second source electrically connected to a second voltage terminal, and a common drain; and a substrate control circuit. The substrate control circuit includes: a first diode and a second diode; a discharge circuit including a first transistor and a second transistor connected in a common source configuration to the semiconductor substrate; and a gate potential control circuit including a third diode and a fourth diode. The first diode has a forward voltage Vf1 and the third diode has a forward voltage Vf3, where Vf1≥1.1Vf4 or Vf1≥1.2Vf4 or Vf1≥1.5Vf4 or Vf1≥2Vf4.
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
H03K 17/56 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices
70.
DIODE INCLUDING A TRENCH ELECTRODE SUBDIVIDED INTO AT LEAST FIRST AND SECOND PARTS
A diode is proposed. The diode includes: a semiconductor body having opposing first and second main surfaces; an anode region and a cathode region, the anode region being arranged between the first main surface and the cathode region; an anode pad area electrically connected to the anode region; and trenches extending into semiconductor body from the first main surface. A first group of the trenches includes a first trench electrode. The first trench electrode is subdivided into at least a first part and a second part. A conductance per unit length of the first part along a longitudinal direction of the first trench electrode is by at least a factor of 1000 smaller than a conductance per unit length of the second part along the longitudinal direction of the first trench electrode. The second part is electrically coupled to the anode pad area via the first part.
H01L 27/07 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
71.
PIEZORESISTIVE TRANSISTOR DEVICE AND POWER ELECTRONIC MODULE INCLUDING A PIEZORESISTIVE TRANSISTOR DEVICE
A piezoresistive transistor device includes a first transistor cell having a first piezoelectric material body and a first piezoresistive material body arranged in a stacked configuration. A first electrical resistance of the first piezoresistive material body is dependent upon a voltage applied across the first piezoelectric material body by way of a pressure applied by the first piezoelectric material body to the first piezoresistive material body. A second transistor cell includes a second piezoelectric material body and a second piezoresistive material body arranged in a stacked configuration. A second electrical resistance of the second piezoresistive material body is dependent upon a voltage applied across the second piezoelectric material body by way of a pressure applied by the second piezoelectric material body to the second piezoresistive material body. An internal electrical interconnect is configured to electrically connect the first electrical resistance and the second electrical resistance in series or in parallel.
A method of monitoring a thermal impedance of at least a portion of a thermal path between a semiconductor device having at least two output terminals and a heat sink s provided. The method includes causing power dissipation in the semiconductor device by reloading parasitic capacitances of the semiconductor device such that the at least two output terminals are at the same voltage level, measuring a first temperature in response to the power dissipation at a first end of the portion of the thermal path, measuring a second temperature in response to the power dissipation at a second end of the portion of the thermal path, and determining a measure of the thermal impedance based on the first temperature and the second temperature.
An electronic device with a multi-layer contact and a system is disclosed. In an embodiment, a semiconductor device includes a semiconductor substrate having a first electrode terminal located on a first surface and a second surface electrode terminal located on a second surface, the first surface being opposite to the second surface, an electrical contact layer disposed directly on the first electrode terminal, a functional layer directly disposed on the electrical contact layer, an adhesion layer directly disposed on the functional layer, a solder layer directly disposed on the adhesion layer; and a protection layer directly disposed on the solder layer, wherein the semiconductor device is a power semiconductor device configured to provide a vertical current flow.
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 23/482 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of lead-in layers inseparably applied to the semiconductor body
A method of driving a transistor between switching states includes controlling a transition of a gate voltage at a gate terminal of a transistor during each of a plurality of turn-off switching events to turn off the transistor, wherein the transistor is configured to be turned off according to a desaturation time during each of the plurality of turn-off switching events; measuring a transistor parameter indicative of a voltage slew rate of the transistor for a first turn-off switching event during which the transistor is transitioned from an on state to an off state; and regulating a duration of the desaturation time for a next turn-off switching event based on the measured transistor parameter.
H03K 17/16 - Modifications for eliminating interference voltages or currents
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
A semiconductor device includes a semiconductor body having an upper surface, a group of first upper-level metal fingers and second upper-level metal fingers that are arranged alternatingly with one another, wherein each of the first upper-level metal fingers is electrically connected to the semiconductor body by the first lower-level conductive fingers, wherein each of the second upper-level metal fingers is electrically connected to the semiconductor body by the second lower-level conductive fingers, wherein the group of first lower-level conductive fingers and second lower-level conductive fingers defines a connection area over the upper surface, and wherein in the connection area the first upper-level metal fingers are at least partially non-overlapping with the second upper-level metal fingers.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 23/528 - Layout of the interconnection structure
76.
POWER SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAME
A power semiconductor package includes: a die carrier having first and second opposite sides; and first and second power semiconductor dies each having first and second power electrodes on opposite sides. The second power electrodes face and are electrically coupled to the first side of the carrier. A molded body at least partially encapsulates the dies and has a first and second opposite sides and lateral sides connecting the first and second sides. First and second power contacts and first and second control contacts are arranged laterally next to each other. The first power electrode of the first die is electrically coupled to the first power contact by a first electrical connector. The first power electrode of the second die is electrically coupled to the second power contact by a second electrical connector. A width of each power contact is at least four times the width of each control contact.
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
77.
Real-Time Chirp Signal Frequency Linearity Measurement
A frequency linearity measurement circuit configured to measure a frequency linearity of a frequency signal includes: a first measurement circuit configured to generate a first estimate of an integer number of clock cycles of the frequency signal within a respective gate signal period of a gate signal; a second measurement circuit comprising a time-to-digital converter (TDC) configured to generate a second estimate of a fractional number of clock cycle of the frequency signal within the respective gate signal period; a reference measurement circuit configured to generate a third estimate of an expected number of clock cycles within the respective gate signal period; and a closed-loop frequency tracking circuit configured to track a frequency error between an expected frequency and a measured frequency, where the expected frequency and the measured frequency are determined based on the third estimate and on a sum of the first estimate and the second estimate, respectively.
G01S 7/35 - RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES - Details of systems according to groups , , of systems according to group - Details of non-pulse systems
78.
Semiconductor Package and Passive Element with Interposer
A method includes providing an interposer that includes an electrically insulating substrate, upper contact pads disposed on an upper surface, and lower contact pads disposed on a lower surface, providing a semiconductor package that includes a semiconductor die embedded within a package body and a plurality of package terminals exposed from the package body, providing a first passive electrical element that comprises first and second terminals, forming a first electrical connection between the first terminal of the first passive electrical element and a first one of the lower contact pads via the interposer, forming a second electrical connection between the second terminal of the first passive electrical element and a first one of the package terminals, and forming a third electrical connection between a second one of the package terminals and a second one of the lower contact pads via the interposer.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
79.
CHIP ASSEMBLY, METHOD FOR FORMING A CHIP ASSEMBLY, AND METHOD FOR USING A CHIP ARRANGEMENT
A chip arrangement including a chip module which includes a chip, a contact-based interface in accordance with ISO 7816 which is electrically conductively connected to the chip, and an antenna structure which is electrically conductively connected to the chip and provides a contactless interface, and a carrier which comprises a chip module receptacle and a booster antenna structure which, when the chip module is arranged in the chip module receptacle of the carrier, inductively couples to the antenna structure of the chip module, wherein the chip module is arranged releasably in the chip module receptacle.
A picture generation system includes a plurality of red-green-blue (RGB) light transmitters configured to synchronously generate respective pixel light beams and transmit the respective pixel light beams along respective transmission paths to be projected into a full field of view (FOV). The full FOV is divided into a plurality of FOV sections that are respectively paired with a different one of the plurality of RGB light transmitters such that each of the plurality of RGB light transmitters transmits light into a respective area defined by its respective FOV section. The picture generation system further includes a scanning system arranged on each of the respective transmission paths of the plurality of RGB light transmitter. The scanning system includes a scanning structure that enables the scanning system to simultaneously steer the respective pixel light beams into the plurality of FOV sections.
G02B 26/12 - Scanning systems using multifaceted mirrors
G02B 26/08 - Optical devices or arrangements for the control of light using movable or deformable optical elements for controlling the direction of light
A semiconductor package includes a substrate including a die pad, first and second discrete transistor dies mounted on the die pad, an encapsulant body that encapsulates the first and second discrete transistor dies, and a plurality of leads that are exposed from the encapsulant body, wherein the first and second discrete transistor dies are connected in parallel with one another by electrical interconnections that electrically connect common terminals of the first and second discrete transistor dies to one of the leads, and wherein at least one of the electrical interconnections has a balanced configuration that provides substantially identical electrical impedance as between the common terminals of the first and second discrete transistor dies and the lead to which they are connected.
A frequency linearity measurement circuit configured to measure a frequency linearity of a frequency signal includes: a first measurement circuit having a counter, where the counter is controlled by a gate signal having a gate signal period, where the first measurement circuit is configured to generate a first estimate of an integer number of clock cycles of the frequency signal within a respective gate signal period of the gate signal; a second measurement circuit having a time-to-digital converter (TDC), where the TDC is controlled by the gate signal, and is configured to generate a second estimate of a fractional number of clock cycle of the frequency signal within the respective gate signal period of the gate signal; and a reference measurement circuit configured to generate a third estimate of an expected number of clock cycles within the respective gate signal period of the gate signal.
H03L 7/099 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
G01S 13/34 - Systems for measuring distance only using transmission of continuous waves, whether amplitude-, frequency-, or phase-modulated, or unmodulated using transmission of continuous, frequency-modulated waves while heterodyning the received signal, or a signal derived therefrom, with a locally-generated signal related to the contemporaneously transmitted signal
H03L 7/091 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
83.
VERTICAL JUNCTION FIELD EFFECT TRANSISTOR INCLUDING A PLURALITY OF MESA REGIONS
A vertical junction field effect transistor includes mesa regions and trench structures extending along a first lateral direction in a semiconductor body and arranged alternately along a second lateral direction. The trench structures include a gate contact material electrically connected to a gate region of a first conductivity type in the semiconductor body. A width of the trench structures satisfies one or more of the following conditions: i) the width of at least one trench structure arranged outermost along the second lateral direction is smaller than in a more central part of the trench structures; or ii) the width of at least some trench structures is smaller along an end part in the first lateral direction than in the more central part, an extent of the end part along the first lateral direction being larger than a pitch between neighboring trench structures along the second lateral direction.
H01L 29/808 - Field-effect transistors with field effect produced by a PN or other rectifying junction gate with a PN junction gate
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
An apparatus may include an input pin\ and timing control circuitry coupled to the input pin. The timing control circuitry selectively executes one or more timing control functions based on a set of one or more hardware components coupled to the input pin. The set of one or more hardware components are disposed external to the apparatus. A configuration of the set of one or more hardware components determines which of one or more of the multiple timing control functions are enabled.
H02H 9/02 - Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess current
H02H 3/093 - Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition, with or without subsequent reconnection responsive to excess current with timing means
H03K 17/16 - Modifications for eliminating interference voltages or currents
H03K 17/284 - Modifications for introducing a time delay before switching in field-effect transistor switches
85.
Gate driver circuit with a limiting function to maintain control voltage under a rated limit
A gate driver system includes a transistor configured to be driven between switching states, the transistor including a control terminal controlled by a control voltage that has a maximum rated limit; and a gate driver coupled to the control terminal by a turn-on current path, the gate driver being configured to control the control voltage in order to drive the transistor between the switching states. The turn-on current path includes a resistor and a Zener diode connected in series, with an anode of the Zener diode connected to the control terminal and a cathode of the Zener diode connected to the resistor. The turn-on current path is configured to provide an on-current to increase the control voltage above a switching threshold. While the transistor is turned on, the Zener diode is configured to limit the control voltage to a voltage level limit that is less than the maximum rated limit.
H03K 3/00 - Circuits for generating electric pulses; Monostable, bistable or multistable circuits
H03K 17/00 - Electronic switching or gating, i.e. not by contact-making and -breaking
H03K 17/06 - Modifications for ensuring a fully conducting state
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
H03K 17/693 - Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors
86.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE
A semiconductor device includes a transistor including transistor cells. Each transistor cells has a gate electrode arranged in gate trenches formed in a first portion of a silicon carbide substrate and extending in a first horizontal direction, a source region, a channel region, and a current-spreading region. The source region, channel region, and at least part of the current-spreading region are arranged in ridges patterned by the gate trenches. The transistor cells further include a body contact portion of the second conductivity type arranged in a second portion of the silicon carbide substrate and electrically connected to the channel region. The transistor cells further include a shielding region of the second conductivity type. A first portion of the shielding region is arranged below the gate trenches, respectively, and a second portion of the shielding region is arranged adjacent to a sidewall of the gate trenches, respectively.
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
Disclosed is a re-configurable sensor arrangement (100) including a sensor device (110) and a controller device (120), both being configured to communicate with each other, wherein the controller device (120) is configured to transmit a pulse modulated signal (130) to the sensor device (110) via a one-wire voltage interface (140), and wherein the sensor device (110) is configured to receive the pulse modulated signal (130) via the one-wire voltage interface (140) and to re-configure its internal configuration in response to the received pulse modulated signal (130).
An electronic circuit and a method are disclosed. The electronic circuit includes: a first transistor device having a load path between a first load path node and a second load path node; and a clamping circuit connected to the load path of the first transistor device. The clamping circuit includes: a second transistor device having a load path connected in parallel with the load path of the first transistor device, and a control node; and a drive circuit configured to drive the second transistor device. The drive circuit includes a clamping element and a resistor connected in series between the first and second load path nodes of the first transistor device. The drive circuit is configured to drive the second transistor device dependent on a voltage across the resistor. The first transistor device and the clamping circuit are integrated in a same semiconductor die.
H03K 17/06 - Modifications for ensuring a fully conducting state
H03K 17/081 - Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
H03K 17/10 - Modifications for increasing the maximum permissible switched voltage
89.
Power Semiconductor Module Comprising a First and a Second Compartment and Method for Fabricating the Same
A power semiconductor module includes a power semiconductor die arranged on a power substrate, a housing enclosing the power semiconductor die and the power substrate, wherein an interior volume formed by the housing is divided by interior walls into at least a first compartment and a second compartment, wherein the power semiconductor die is arranged within the first compartment, a first encapsulation material encapsulating the power semiconductor die and at least partially filling the first compartment, and a second encapsulation material different from the first encapsulation material, the second encapsulation material encapsulating the first encapsulation material and at least partially filling the second compartment, wherein the first encapsulation material is arranged within the first compartment but not within the second compartment.
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 23/053 - Containers; Seals characterised by the shape the container being a hollow construction and having an insulating base as a mounting for the semiconductor body
H01L 25/11 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group
90.
ENCAPSULATED MEMS DEVICE AND METHOD FOR MANUFACTURING THE MEMS DEVICE
An encapsulated MEMS device and a method for manufacturing the MEMS device are provided. The method comprises providing a cavity structure having an inner volume comprising a plurality of MEMS elements, which are relatively displaceable with respect to each other, and having an opening structure to the inner volume, depositing a Self-Assembled Monolayer (SAM) through the opening structure onto exposed surfaces within the inner volume of the cavity structure, and closing the cavity structure by applying a layer structure on the opening structure for providing a hermetically closed cavity.
A magnetic sensor apparatus includes a magnetic field generating circuit which is configured to generate a magnetic field, a magnetic field sensor circuit which is configured to output a sensor signal in response to the magnetic field, which sensor signal has a signal amplitude dependent on a sensitivity of the magnetic field sensor circuit, an amplifier circuit which is configured to amplify the sensor signal and to output an amplified sensor signal with an amplified signal amplitude, and a control circuit which is configured to use a setting signal to set a supply signal of the magnetic field sensor circuit and/or a gain of the amplifier circuit such that the amplified signal amplitude corresponds to a target amplitude.
An RF switch device includes transistors coupled in series forming an RF conductive current path; a first resistive bias network forming a DC conductive bias path between gate nodes of the plurality of transistors; and a first ESD bias component coupled between the RF conductive current path and the first resistive bias network, wherein the first ESD bias component provides a DC conductive path between the RF conductive current path of the RF switch device and the first resistive bias network during an ESD event.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H02H 9/04 - Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
93.
Fast Lissajous lock control and synchronization of scanning axes of microelectromechanical system
A method of synchronizing a first oscillation about a first axis with a second oscillation about a second axis includes: generating a first position signal that indicates a position of the first oscillation about the first axis; generating a second position signal that indicates a position of the second oscillation about the first axis; determining a phase difference between the first and the second position signals; comparing the phase difference to a threshold value to generate a comparison result; generating a first reference signal having a first frequency and a second reference signal having a second frequency; synchronizing the first oscillation to the first frequency and synchronizing the second oscillation to the second frequency; monitoring the comparison result; and synchronously triggering a start of the first reference signal and the second reference signal responsive to the comparison result indicating that the phase difference is less than the threshold value.
G01S 7/481 - Constructional features, e.g. arrangements of optical elements
G02B 26/08 - Optical devices or arrangements for the control of light using movable or deformable optical elements for controlling the direction of light
H03L 7/099 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
94.
ISOLATED POWER CONVERTER HAVING A VOLTAGE SUPPLY CIRCUIT
An isolated power converter includes: a transformer having primary winding and first and second auxiliary windings on the primary side; a converter stage configured to convert a DC input for driving the primary winding and having a resonant capacitor electrically connected to the primary winding; a controller configured to control switching of the converter stage; and a voltage supply circuit configured to select a first voltage as a supply voltage for the controller if a voltage proportional to a secondary side voltage of the transformer is at a first level or select a second voltage as the supply voltage if the voltage proportional to the secondary side voltage is at a second level greater than the first level. The first voltage corresponds to a summation of voltages across the first auxiliary winding and the resonant capacitor. The second voltage corresponds to a voltage across the second auxiliary winding.
H02M 3/335 - Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
H02M 3/00 - Conversion of dc power input into dc power output
95.
SILICON-ON-INSULATOR (SOI) DEVICE HAVING VARIABLE THICKNESS DEVICE LAYER AND CORRESPONDING METHOD OF PRODUCTION
A method of producing power semiconductor devices from a silicon-on-insulator (SOI) wafer is described. The SOI wafer includes a silicon device layer, a bulk silicon wafer, and a buried oxide layer separating the silicon device layer from the bulk silicon wafer. The method includes: forming a hard mask on the silicon device layer, wherein the hard mask covers one or more first regions of the silicon device layer and exposes one or more second regions of the silicon device layer; and before forming any field oxide structures and before implanting any device regions, selectively growing epitaxial silicon on the one or more second regions of the silicon device layer exposed by the hard mask such that the thickness of the one or more second regions is increased relative to the one or more first regions. Various devices produced according to the method are also described.
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/80 - Field-effect transistors with field effect produced by a PN or other rectifying junction gate
A semiconductor device includes: a transistor formed in a first semiconductor layer stack; a diode formed in a second semiconductor layer stack, the diode including an anode metal layer; and a carrier. The transistor and the diode are mounted to the carrier. A terminal of the transistor is electrically connected to the carrier, and the anode metal layer is in direct contact with the carrier.
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
Device with ultrasonic transducer and method for manufacturing same. A device is provided, having an ultrasonic transducer, which includes a membrane and a cover element. A coupling medium entirely fills an interspace between the membrane and the cover element, and extends from the interspace into a reservoir space which communicates with the interspace.
A current sensor includes a current rail and a magnetic field sensor. The magnetic field sensor is configured to measure a magnetic field induced by a current flowing through the current rail. A first insulation layer and a second insulation layer are arranged between the current rail and the magnetic field sensor. An interface between the first insulation layer and the second insulation layer is free of a contact with the current rail and/or is free of a contact with the magnetic field sensor. A portion of the current rail extends into the second insulation layer and the portion of the current rail is encapsulated by the second insulation layer.
G01R 15/20 - Adaptations providing voltage or current isolation, e.g. for high-voltage or high-current networks using galvano-magnetic devices, e.g. Hall-effect devices
A circuit is configured to generate a first switching signal and a second switching signal. During a first portion of a first switching period, both the first switching signal and the second switching signal indicate to turn-on and turn-off. During a second portion of the first switching period, the first switching signal indicates to turn-on and the second switching signal indicates to turn-off. In response to a determination that a measurement time threshold exceeds the first switching period, the circuit is configured to generate a first adapted switching signal that extends the turn-on portion by a time value in the first switching period and to generate a second adapted switching signal that extends the turn-on time by the time value in a second switching period. The circuit is further configured to control switching circuitry using the first adapted switching signal and the second adapted switching signal to operate a motor.
H02P 23/14 - Estimation or adaptation of motor parameters, e.g. rotor time constant, flux, speed, current or voltage
H02P 27/08 - Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using dc to ac converters or inverters with pulse width modulation
100.
Excess Loop Delay Compensation for a Delta-Sigma Modulator
In accordance with an embodiment, a delta-sigma modulator includes: an analog loop filter comprising an outer portion and an inner portion having an input coupled to the outer portion; a quantizer coupled to an output of the inner portion of the analog loop filter; an outer feedback path coupled between an output of the quantizer and an input to the outer portion of the analog loop filter; and a compensation filter coupled between an output of the quantizer and an input of the inner portion of the analog loop filter. The compensation filter has a transfer function configured to correct for an effect of excess loop delay (ELD) on the delta-sigma modulator.
