Abstract

Disclosed are a method and a device for signal transmission or reception using aggregated carriers. An operation method of a terminal comprises the steps of: receiving configuration information of multiple cells from a base station; receiving configuration information of a first search space set, which is configured in a first cell among the multiple cells and for scheduling of the first cell, from the base station; and receiving configuration information of a second search space set, which is configured in a second cell among the multiple cells and for scheduling of the first cell, from the base station.

IPC Classes  ?

• H04B 17/373 - Predicting channel quality parameters
• H04W 72/04 - Wireless resource allocation
• H04W 72/12 - Wireless traffic scheduling
• H04J 11/00 - Orthogonal multiplex systems
• H04L 1/00 - Arrangements for detecting or preventing errors in the information received
• H04L 5/00 - Arrangements affording multiple use of the transmission path

Abstract

Disclosed are a method and apparatus for image encoding and image decoding using prediction based on a block type. Whether or not a prediction mode is available for a target block is determined. The determination is performed on the basis of a type of the target block. When it is determined that the prediction mode is unavailable for the target block, signaling associated with the prediction mode is omitted, and determination of another prediction mode is performed. When it is determined that the prediction mode is available for the target block, information indicating whether or not the prediction mode is used for the target block is signaled.

IPC Classes  ?

• H04N 19/159 - Prediction type, e.g. intra-frame, inter-frame or bidirectional frame prediction
• H04N 19/11 - Selection of coding mode or of prediction mode among a plurality of spatial predictive coding modes
• H04N 19/176 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
• H04N 19/593 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding involving spatial prediction techniques
• H04N 19/70 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by syntax aspects related to video coding, e.g. related to compression standards

Abstract

Provided is a method for controlling the access of a terminal in a communication system. An operation method of a terminal comprises the steps of: receiving, from a base station, configuration information for a two-step random access procedure; transmitting, to the base station, RA MSG-A including an RA preamble and an RA payload, on the basis of the configuration information; and receiving, from the base station, RA MSG-B, which is a response to the RA MSG-A. Therefore, communication system performance can be improved.

IPC Classes  ?

• H04W 74/00 - Wireless channel access, e.g. scheduled or random access
• H04W 28/04 - Error control
• H04W 74/02 - Hybrid access techniques
• H04W 84/04 - Large scale networks; Deep hierarchical networks
• H04W 88/08 - Access point devices

Abstract

An image decoding method is disclosed in the present specification. An image decoding method of the present invention comprises: a step of generating a candidate list including motion information derived from a temporal neighboring block and a spatial neighboring block adjacent to a current block; a step of deriving motion information of the current block by using the candidate list; a step of generating a prediction block of the current block by using the derived motion information; and a step of updating the derived motion information in a motion information list, wherein the step of generating the candidate list comprises generating the candidate list including at least one piece of motion information included in the motion information list updated in a block encoded before the current block.

IPC Classes  ?

• H04N 19/513 - Processing of motion vectors
• H04N 19/105 - Selection of the reference unit for prediction within a chosen coding or prediction mode, e.g. adaptive choice of position and number of pixels used for prediction
• H04N 19/119 - Adaptive subdivision aspects e.g. subdivision of a picture into rectangular or non-rectangular coding blocks
• H04N 19/137 - Motion inside a coding unit, e.g. average field, frame or block difference
• H04N 19/176 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
• H04N 19/196 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the adaptation method, adaptation tool or adaptation type used for the adaptive coding being specially adapted for the computation of encoding parameters, e.g. by averaging previously computed encoding parameters
• H04N 19/56 - Motion estimation with initialisation of the vector search, e.g. estimating a good candidate to initiate a search
• H04N 19/593 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding involving spatial prediction techniques

Abstract

An image decoding method is disclosed in the present specification. An image decoding method according to the present invention comprises the steps of: deriving a first candidate list for the current block by using motion information of neighboring blocks of the current block; deriving a second candidate list for the current block by using previously reconstructed motion information; deriving a third candidate list by using the first candidate list and the second candidate list; and deriving a prediction block for the current block by using the third candidate list.

IPC Classes  ?

• H04N 19/51 - Motion estimation or motion compensation
• H04N 19/107 - Selection of coding mode or of prediction mode between spatial and temporal predictive coding, e.g. picture refresh
• H04N 19/109 - Selection of coding mode or of prediction mode among a plurality of temporal predictive coding modes
• H04N 19/11 - Selection of coding mode or of prediction mode among a plurality of spatial predictive coding modes
• H04N 19/117 - Filters, e.g. for pre-processing or post-processing
• H04N 19/119 - Adaptive subdivision aspects e.g. subdivision of a picture into rectangular or non-rectangular coding blocks
• H04N 19/124 - Quantisation
• H04N 19/13 - Adaptive entropy coding, e.g. adaptive variable length coding [AVLC] or context adaptive binary arithmetic coding [CABAC]
• H04N 19/137 - Motion inside a coding unit, e.g. average field, frame or block difference
• H04N 19/60 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding

Abstract

There is provided an image encoding/decoding method and apparatus. The image encoding method of the present invention includes: generating at least one candidate block including warped reference picture (WRP) Flag information in an advanced motion vector prediction (AMVP) mode; constructing a candidate list including the at least one candidate block; and generating a prediction block of a current block based on the candidate list.

IPC Classes  ?

• H04N 19/105 - Selection of the reference unit for prediction within a chosen coding or prediction mode, e.g. adaptive choice of position and number of pixels used for prediction
• H04N 19/137 - Motion inside a coding unit, e.g. average field, frame or block difference
• H04N 19/172 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a picture, frame or field
• H04N 19/593 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding involving spatial prediction techniques

Abstract

There is provided an image encoding/decoding method and apparatus. The image encoding method of the present invention includes: generating at least one candidate block including warped reference picture (WRP) Flag information in an advanced motion vector prediction (AMVP) mode; constructing a candidate list including the at least one candidate block; and generating a prediction block of a current block based on the candidate list.

Abstract

Disclosed are a device and a method for generating a broadcast signal frame corresponding to a time interleaver supporting multiple operation modes. The device for generating a broadcast signal frame, according to one embodiment of the present invention, comprises: a combiner for generating a multiplexed signal by combining a core layer signal and an enhanced layer signal; a power normalizer for lowering the power of the multiplexed signal to a power corresponding to that of the core layer signal; a time interleaver for generating a time-interleaved signal by performing interleaving that applies to both the core layer signal and the enhanced layer signal; and a frame builder for generating a broadcast signal frame including a preamble for signaling time-interleaver information corresponding to the time interleaver, wherein the preamble includes a field indicating starting positions of first complete FEC blocks corresponding to respective physical layer pipes.

IPC Classes  ?

• H04L 1/00 - Arrangements for detecting or preventing errors in the information received

Abstract

According to one embodiment of the present invention, a broadcast signal frame generation device comprises: a combiner combining a core layer signal and an enhanced layer signal so as to generate a multiplexed signal; a power normalizer for lowering power of the multiplexed signal to a power corresponding to the core layer signal; a time interleaver for generating a time-interleaved signal by performing time interleaving applied to both the core layer signal and the enhanced layer signal; and a frame builder for generating a broadcast signal frame including a preamble for signaling start position information and size information of each of physical layer pipes (PLPs), wherein the physical layer pipes comprise a core layer physical layer pipe corresponding to the core layer signal, and an enhanced layer physical layer pipe corresponding to the enhanced layer signal.

IPC Classes  ?

• H04L 5/00 - Arrangements affording multiple use of the transmission path
• H04L 1/00 - Arrangements for detecting or preventing errors in the information received

Abstract

An apparatus and method for time interleaving corresponding to hybrid time interleaving mode are disclosed. An apparatus for time interleaving according to an embodiment of the present invention includes a twisted block interleaver configured to perform intra-subframe interleaving corresponding to time interleaving blocks; and a convolutional delay line configured to perform inter-subframe interleaving using an output of the twisted block interleaver.

IPC Classes  ?

• H03M 13/27 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
• H04H 20/71 - Wireless systems
• H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
• H03M 13/23 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using convolutional codes, e.g. unit memory codes

Abstract

An apparatus and method for generating a broadcast signal frame for signaling a time interleaving mode are disclosed. An apparatus for generating broadcast signal frame according to an embodiment of the present invention includes a time interleaver configured to generate a time-interleaved signal by performing time interleaving on a BICM output signal: and a frame builder configured to generate a broadcast signal frame including a preamble for signaling a time interleaving mode corresponding to the time interleaver for each of physical layer pipes (PLPs).

IPC Classes  ?

• H04H 20/95 - Arrangements characterised by special technical features of the broadcast information, e.g. signal form or information format characterised by a specific format, e.g. MP3 [MPEG-1 Audio Layer 3]

Abstract

An apparatus and method for generating a broadcast signal frame for signaling a time interleaving mode are disclosed. An apparatus for generating broadcast signal frame according to an embodiment of the present invention includes a combiner configured to generate a multiplexed signal by combining a core layer signal and an enhanced layer signal; a power normalizer configured to perform power-normalizing for reducing the power of the multiplexed signal to a power level corresponding to the core layer signal; a time interleaver configured to generate a time-interleaved signal by performing time interleaving after performing the power-normalizing; and a frame builder configured to generate a broadcast signal frame including a preamble for signaling a time interleaving mode corresponding to the time interleaver for each of physical layer pipes (PLPs).

IPC Classes  ?

• H04H 60/02 - Arrangements for generating broadcast information; Arrangements for generating broadcast-related information with a direct linkage to broadcast information or to broadcast space-time; Arrangements for simultaneous generation of broadcast information and broadcast-related information
• H04J 99/00 - Subject matter not provided for in other groups of this subclass
• H03M 13/27 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
• H04L 27/00 - Modulated-carrier systems

Abstract

An apparatus and method for generating a broadcast signal frame using enhanced layer dummy values are disclosed. An apparatus for generating broadcast signal frame according to an embodiment of the present invention includes a combiner configured to generate a multiplexed signal by combining a core layer signal and an enhanced layer signal; a power normalizer configured to reduce the power of the multiplexed signal to a power level corresponding to the core layer signal; a time interleaver configured to generate a time-interleaved signal by performing interleaving that is applied to both the core layer signal and the enhanced layer signal; and a frame builder configured to generate a broadcast signal frame including a preamble for signaling time interleaver information corresponding to the time interleaver, the time interleaver uses one of time interleaver groups, and enhanced layer data corresponding to the one of the time interleaver groups include dummy values.

IPC Classes  ?

• H04H 20/28 - Arrangements for simultaneous broadcast of plural pieces of information

Abstract

An apparatus and method for generating a broadcast signal frame using enhanced layer dummy values are disclosed. An apparatus for generating broadcast signal frame according to an embodiment of the present invention includes a combiner configured to generate a multiplexed signal by combining a core layer signal and an enhanced layer signal; a power normalizer configured to reduce the power of the multiplexed signal to a power level corresponding to the core layer signal; a time interleaver configured to generate a time-interleaved signal by performing interleaving that is applied to both the core layer signal and the enhanced layer signal; and a frame builder configured to generate a broadcast signal frame including a preamble for signaling time interleaver information corresponding to the time interleaver, the time interleaver uses one of time interleaver groups, and enhanced layer data corresponding to the one of the time interleaver groups include dummy values.

IPC Classes  ?

• H04N 21/2383 - Channel coding of digital bit-stream, e.g. modulation
• H04N 21/2389 - Multiplex stream processing, e.g. multiplex stream encrypting
• H04N 19/34 - Scalability techniques involving progressive bit-plane based encoding of the enhancement layer, e.g. fine granular scalability [FGS]

Abstract

An apparatus and method for generating a broadcast signal frame including preamble for signaling injection level information. An apparatus for generating broadcast signal frame according to an embodiment of the present invention includes an injection level controller configured to generate a power reduced enhanced layer signal by reducing a power of an enhanced layer signal; a combiner configured to generate a multiplexed signal by combining a core layer signal and the power reduced enhanced layer signal; a power normalizer configured to reduce the power of the multiplexed signal to a power level corresponding to the core layer signal; a time interleaver configured to generate a time- interleaved signal by performing interleaving that is applied to both the core layer signal and the enhanced layer signal; and a frame builder configured to generate a broadcast signal frame including a preamble for signaling injection level information corresponding to the injection level controller.

IPC Classes  ?

• H04N 19/34 - Scalability techniques involving progressive bit-plane based encoding of the enhancement layer, e.g. fine granular scalability [FGS]
• H04J 3/00 - Time-division multiplex systems
• H04L 1/00 - Arrangements for detecting or preventing errors in the information received
• H04N 7/015 - High-definition television systems

Abstract

An apparatus and method for generating a broadcast signal frame including preamble for signaling injection level information. An apparatus for generating broadcast signal frame according to an embodiment of the present invention includes an injection level controller configured to generate a power reduced enhanced layer signal by reducing a power of an enhanced layer signal; a combiner configured to generate a multiplexed signal by combining a core layer signal and the power reduced enhanced layer signal; a power normalizer configured to reduce the power of the multiplexed signal to a power level corresponding to the core layer signal; a time interleaver configured to generate a time-interleaved signal by performing interleaving that is applied to both the core layer signal and the enhanced layer signal; and a frame builder configured to generate a broadcast signal frame including a preamble for signaling injection level information corresponding to the injection level controller.

IPC Classes  ?

• H04L 1/00 - Arrangements for detecting or preventing errors in the information received

Abstract

Disclosed are a device and a method for generating a broadcast signal frame corresponding to a time interleaver for supporting a plurality of operation modes. The device for generating a broadcast signal frame, according to one embodiment of the present invention, comprises: a combiner for generating a multiplexed signal by combining, at different power levels, a core layer signal and an enhanced layer signal; a power normalizer for lowering power of the multiplexed signal to power corresponding to the core layer signal; a time interleaver for generating a time-interleaved signal by performing interleaving applied to both the core layer signal and the enhanced layer signal; and a frame builder for generating a broadcast signal frame including a preamble for signaling time interleaver information corresponding to the time interleaver, wherein the time interleaver performs the interleaving in one of a plurality of operation modes.

IPC Classes  ?

• H04N 19/34 - Scalability techniques involving progressive bit-plane based encoding of the enhancement layer, e.g. fine granular scalability [FGS]
• H04N 19/46 - Embedding additional information in the video signal during the compression process
• H04N 19/895 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using pre-processing or post-processing specially adapted for video compression involving methods or arrangements for detection of transmission errors at the decoder in combination with error concealment
• H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
• H03M 13/27 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques

Abstract

An apparatus and method for generating a broadcast signal frame corresponding to a time interleaver supporting a plurality of operation modes are disclosed. An apparatus for generating broadcast signal frame according to an embodiment of the present invention includes a combiner configured to generate a multiplexed signal by combining a core layer signal and an enhanced layer signal at different power levels; a power normalizer configured to reduce the power of the multiplexed signal to a power level corresponding to the core layer signal; a time interleaver configured to generate a time-interleaved signal by performing interleaving that is applied to both the core layer signal and the enhanced layer signal; and a frame builder configured to generate a broadcast signal frame including a preamble for signaling time interleaver information corresponding to the time interleaver, the time interleaver uses one of time interleaver groups, and the time interleaver performs the interleaving by using one of a plurality of operation modes..

IPC Classes  ?

• H04N 19/34 - Scalability techniques involving progressive bit-plane based encoding of the enhancement layer, e.g. fine granular scalability [FGS]
• H04N 19/46 - Embedding additional information in the video signal during the compression process
• H04N 19/895 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using pre-processing or post-processing specially adapted for video compression involving methods or arrangements for detection of transmission errors at the decoder in combination with error concealment
• H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
• H03M 13/27 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques

Abstract

An apparatus and a method for generating a broadcast signal frame using layered division multiplexing are disclosed. The broadcast signal frame generation apparatus according to one embodiment of the present invention comprises: a combiner for generating a multiplexed signal by combining a core layer signal and an enhanced layer signal at different power levels; a power normalizer for lowering the power of the multiplexed signal to a power corresponding to the core layer signal; a time-interleaver for generating a time-interleaved signal by performing interleaving which is applied to the core layer signal and the enhanced layer signal together; and a frame builder for generating a broadcast signal frame including size information of physical layer pipes (PLPs) and a preamble for signaling time-interleaver information which is shared with the core layer signal and the enhanced layer signal.

IPC Classes  ?

• H04L 27/26 - Systems using multi-frequency codes
• H04L 1/00 - Arrangements for detecting or preventing errors in the information received

Abstract

An apparatus and method for broadcast signal frame using layered division multiplexing are disclosed. An apparatus for generating broadcast signal frame according to an embodiment of the present invention includes a combiner configured to generate a multiplexed signal by combining a core layer signal and an enhanced layer signal at different power levels; a power normalizer configured to reduce the power of the multiplexed signal to a power level corresponding to the core layer signal; a time interleaver configured to generate a time-interleaved signal by performing interleaving that is applied to both the core layer signal and the enhanced layer signal; and a frame builder configured to generate a broadcast signal frame including a preamble for signaling, size information of Physical Layer Pipes (PLPs) and time interleaver information shared by the core layer signal and the enhanced layer signal.

IPC Classes  ?

• H04N 21/61 - Network physical structure; Signal processing
• H04N 19/34 - Scalability techniques involving progressive bit-plane based encoding of the enhancement layer, e.g. fine granular scalability [FGS]
• H04L 1/00 - Arrangements for detecting or preventing errors in the information received
• H04L 12/18 - Arrangements for providing special services to substations for broadcast or conference
• H04L 27/26 - Systems using multi-frequency codes

Abstract

An apparatus and method for broadcast signal frame using a boundary between Physical Layer Pipes (PLPs) of a core layer are disclosed. An apparatus for generating broadcast signal frame according to an embodiment of the present invention includes a combiner configured to generate a multiplexed signal by combining a core layer signal and an enhanced layer signal at different power levels; a power normalizer configured to reduce the power of the multiplexed signal to a power level corresponding to the core layer signal; a time interleaver configured to generate a time-interleaved signal by performing interleaving that is applied to both the core layer signal and the enhanced layer signal; and a frame builder configured to generate a broadcast signal frame including a preamble for signaling time interleaver information corresponding to the dine interleaver, the time interleaver uses one of time interleaver groups, and a boundary between the time interleaver groups is a boundary between Physical Layer Pipes (PLPs) of a core layer corresponding to the core layer signal.

IPC Classes  ?

• H04L 27/26 - Systems using multi-frequency codes
• H04L 1/00 - Arrangements for detecting or preventing errors in the information received

Abstract

An apparatus and method for broadcast signal frame using a boundary between Physical Layer Pipes (PLPs) of a core layer are disclosed. An apparatus for generating broadcast signal frame according to an embodiment of the present invention includes a combiner configured to generate a multiplexed signal by combining a core layer signal and an enhanced layer signal at different power levels; a power normalizer configured to reduce the power of the multiplexed signal to a power level corresponding to the core layer signal; a time interleaver configured to generate a time-interleaved signal by performing interleaving that is applied to both the core layer signal and the enhanced layer signal; and a frame builder configured to generate a broadcast signal frame including a preamble for signaling time interleaver information corresponding to the time interleaver, the time interleaver uses one of time interleaver groups, and a boundary between the time interleaver groups is a boundary between Physical Layer Pipes (PLPs) of a core layer corresponding to the core layer signal.

IPC Classes  ?

• H04L 1/00 - Arrangements for detecting or preventing errors in the information received
• H04H 20/72 - Wireless systems of terrestrial networks
• H04J 11/00 - Orthogonal multiplex systems
• H04L 27/26 - Systems using multi-frequency codes

Abstract

An apparatus and method for broadcast signal frame using a bootstrap including a symbol for signaling a BICM mode and OFDM parameters of a preamble, together are disclosed. An apparatus for generating broadcast signal frame according to an embodiment of the present invention includes a time interleaver configured to generate a time-interleaved signal by performing interleaving on a BICM output signal; and a frame builder configured to generate a broadcast signal frame including a bootstrap and a preamble using the time- interleaved signal. In this case, the bootstrap includes a symbol for signaling a BICM mode and OFDM parameters of L1 -Basic of the preamble, together.

IPC Classes  ?

• H04L 27/26 - Systems using multi-frequency codes
• H04N 21/2383 - Channel coding of digital bit-stream, e.g. modulation
• H04J 11/00 - Orthogonal multiplex systems
• H04L 1/00 - Arrangements for detecting or preventing errors in the information received

Abstract

An apparatus and method for broadcast signal frame using a bootstrap including a symbol for signaling a BICM mode and OFDM parameters of a preamble, together are disclosed. An apparatus for generating broadcast signal frame according to an embodiment of the present invention includes a time interleaver configured to generate a time-interleaved signal by performing interleaving on a BICM output signal; and a frame builder configured to generate a broadcast signal frame including a bootstrap and a preamble using the time- interleaved signal. In this case, the bootstrap includes a symbol for signaling a BICM mode and OFDM parameters of L1-Basic of the preamble, together.

IPC Classes  ?

• H04N 21/2383 - Channel coding of digital bit-stream, e.g. modulation
• H04N 19/65 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using error resilience
• H04J 11/00 - Orthogonal multiplex systems
• H04L 27/26 - Systems using multi-frequency codes

Abstract

An apparatus and method for broadcast signal frame using layered division multiplexing are disclosed. An apparatus for generating broadcast signal frame according to an embodiment of the present invention includes a combiner configured to generate a multiplexed signal by combining a core layer signal and an enhanced layer signal at different power levels; a power normalizer configured to reduce the power of the multiplexed signal to a power level corresponding to the core layer signal; a time interleaver configured to generate a time-interleaved signal by performing interleaving that is applied to both the core layer signal and the enhanced layer signal; and a frame builder configured to generate a broadcast signal frame including a preamble for signaling, start position information of Physical Layer Pipes (PLPs) and time interleaver information shared by the core layer signal and the enhanced layer signal.

IPC Classes  ?

• H04H 20/30 - Arrangements for simultaneous broadcast of plural pieces of information by a single channel

Abstract

An apparatus and method for broadcast signal frame using a bootstrap and a preamble are disclosed. An apparatus for generating broadcast signal frame according to an embodiment of the present invention includes a time interleaver configured to generate a time-interleaved signal by performing interleaving on a BICM output signal; and a frame builder configured to generate a broadcast signal frame including a bootstrap and a preamble using the time-interleaved signal.

IPC Classes  ?

• H04N 21/643 - Communication protocols
• H04N 21/2383 - Channel coding of digital bit-stream, e.g. modulation
• H04J 11/00 - Orthogonal multiplex systems
• H04L 1/00 - Arrangements for detecting or preventing errors in the information received
• H04L 27/26 - Systems using multi-frequency codes

Abstract

An apparatus and method for broadcast signal frame using a bootstrap and a preamble are disclosed. An apparatus for generating broadcast signal frame according to an embodiment of the present invention includes a time interleaver configured to generate a time-interleaved signal by performing interleaving on a BICM output signal; and a frame builder configured to generate a broadcast signal frame including a bootstrap and a preamble using the time- interleaved signal.

IPC Classes  ?

• H04L 27/26 - Systems using multi-frequency codes
• H04N 21/2383 - Channel coding of digital bit-stream, e.g. modulation
• H04J 11/00 - Orthogonal multiplex systems
• H04L 1/00 - Arrangements for detecting or preventing errors in the information received

Abstract

An apparatus and method for broadcast signal frame using layered division multiplexing are disclosed. An apparatus for generating broadcast signal frame according to an embodiment of the present invention includes a combiner configured to generate a multiplexed signal by combining a core layer signal and an enhanced layer signal at different power levels; a power normalizer configured to reduce the power of the multiplexed signal to a power level corresponding to the core layer signal; a time interleaver configured to generate a time-interleaved signal by performing interleaving that is applied to both the core layer signal and the enhanced layer signal; and a frame builder configured to generate a broadcast signal frame including a preamble for signaling, start position information of Physical Layer Pipes (PLPs) and time interleaver information shared by the core layer signal and the enhanced layer signal.

IPC Classes  ?

• H04N 19/88 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using pre-processing or post-processing specially adapted for video compression involving rearrangement of data among different coding units, e.g. shuffling, interleaving, scrambling or permutation of pixel data or permutation of transform coefficient data among different blocks
• H04N 19/34 - Scalability techniques involving progressive bit-plane based encoding of the enhancement layer, e.g. fine granular scalability [FGS]
• H04J 3/22 - Time-division multiplex systems in which the sources have different rates or codes
• H04L 1/00 - Arrangements for detecting or preventing errors in the information received
• H04L 27/26 - Systems using multi-frequency codes

Abstract

An apparatus and method for broadcast signal frame using layered division multiplexing are disclosed. An apparatus for generating broadcast signal frame according to an embodiment of the present invention includes a combiner configured to generate a multiplexed signal by combining a core layer signal and an enhanced layer signal at different power levels; a power normalizer configured to reduce the power of the multiplexed signal to a power level corresponding to the core layer signal; a time interleaver configured to generate a time-interleaved signal by performing interleaving that is applied to both the core layer signal and the enhanced layer signal; and a frame builder configured to generate a broadcast signal frame including a preamble for signaling, type information of Physical Layer Pipes (PLPs) and time interleaver information shared by the core layer signal and the enhanced layer signal.

IPC Classes  ?

• H04N 21/2383 - Channel coding of digital bit-stream, e.g. modulation
• H04L 1/00 - Arrangements for detecting or preventing errors in the information received
• H04L 27/26 - Systems using multi-frequency codes

Abstract

An apparatus and method for broadcast signal frame using layered division multiplexing are disclosed. An apparatus for generating broadcast signal frame according to an embodiment of the present invention includes a combiner configured to generate a multiplexed signal by combining a core layer signal and an enhanced layer signal at different power levels; a power normalizer configured to reduce the power of the multiplexed signal to a power level corresponding to the core layer signal; a time interleaver configured to generate a time-interleaved signal by performing interleaving that is applied to both the core layer signal and the enhanced layer signal; and a frame builder configured to generate a broadcast signal frame including a preamble for signaling, type information of Physical Layer Pipes (PLPs) and time interleaver information shared by the core layer signal and the enhanced layer signal.

IPC Classes  ?

• H04N 19/34 - Scalability techniques involving progressive bit-plane based encoding of the enhancement layer, e.g. fine granular scalability [FGS]
• H04N 21/434 - Disassembling of a multiplex stream, e.g. demultiplexing audio and video streams or extraction of additional data from a video stream; Remultiplexing of multiplex streams; Extraction or processing of SI; Disassembling of packetised elementary stream
• H04N 19/119 - Adaptive subdivision aspects e.g. subdivision of a picture into rectangular or non-rectangular coding blocks
• H04N 19/187 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being a scalable video layer
• H04N 19/65 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using error resilience
• H04N 19/70 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by syntax aspects related to video coding, e.g. related to compression standards
• H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
• H03M 13/27 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
• H04L 27/26 - Systems using multi-frequency codes

Abstract

A parity interleaving apparatus and method for fixed length signaling information are disclosed. A parity interleaving apparatus according to an embodiment of the present invention includes a processor configured to generate a parity bit string for parity puncturing by segmenting parity bits of an LDPC codeword whose length is 16200 and whose code rate is 3/15, into a plurality of groups, and group-wise interleaving the groups using an order of group-wise interleaving; and memory configured to provide the parity bit string for parity puncturing to a parity puncturing unit.

IPC Classes  ?

• H03M 13/27 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
• H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
• H04L 1/00 - Arrangements for detecting or preventing errors in the information received

Abstract

A zero padding apparatus and method for fixed-length signaling information are disclosed. The zero padding apparatus according to one embodiment of the present invention comprises: a processor which determines the number of groups in which all bits are to be padded with 0 by using a difference between the length of an LDPC information bit string and the length of a BCH-encoded bit string, pads all bits of the groups with 0 by selecting the groups using a shortening pattern order, and generates the LDPC information bit string by padding at least a portion of the groups, which has not been padded with 0, with the BCH-encoded bit string; and a memory for providing the LDPC bit string to an LDPC encoder.

IPC Classes  ?

• H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
• H03M 13/15 - Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
• H03M 13/27 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques

Abstract

A zero padding apparatus and method for variable length signaling information are disclosed. A zero padding apparatus according to an embodiment of the present invention includes a processor configured to generate a LDPC information bit string by deciding a number of groups whose all bits are to be filled with 0 using a difference between a length of the LDPC information bit string and a length of a BCH- encoded bit string, selecting the groups using a shortening pattern order to fill all the bits of the groups with 0, and filling at least a part of remaining groups, which are not filled with 0, with the BCH-encoded bit string; and memory configured to provide the LDPC information bit string to an LDPC encoder.

IPC Classes  ?

• H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
• H03M 13/15 - Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
• H03M 13/27 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques

Abstract

A zero padding apparatus and method for variable length signaling information are disclosed. A zero padding apparatus according to an embodiment of the present invention includes a processor configured to generate a LDPC information bit string by deciding a number of groups whose all bits are to be filled with 0 using a difference between a length of the LDPC information bit string and a length of a BCH- encoded bit string, selecting the groups using a shortening pattern order to fill all the bits of the groups with 0, and filling at least a part of remaining groups, which are not filled with 0, with the BCH-encoded bit string; and memory configured to provide the LDPC information bit string to an LDPC encoder.

IPC Classes  ?

• H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
• H03M 13/15 - Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
• H03M 13/27 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques

Abstract

A parity puncturing apparatus and method for fixed length signaling information are disclosed. A parity puncturing apparatus according to an embodiment of the present invention includes memory configured to provide a parity bit string for parity puncturing for the parity bits of an LDPC codeword whose length is 16200 and whose code rate is 3/15, and a processor configured to puncture a number of bits corresponding to a final puncturing size from the rear side of the parity bit string.

IPC Classes  ?

• H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
• H03M 13/15 - Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
• H03M 13/27 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
• H04L 1/22 - Arrangements for detecting or preventing errors in the information received using redundant apparatus to increase reliability
• H04L 27/34 - Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems

Abstract

A parity interleaving apparatus and method for variable length signaling information are disclosed. A parity interleaving apparatus according to an embodiment of the present invention includes a processor configured to generate a parity bit string for parity puncturing by segmenting parity bits of an LDPC codeword whose length is 16200 and whose code rate is 3/15, into a plurality of groups, and group-wise interleaving the groups using an order of group-wise interleaving; and memory configured to provide the parity bit string for parity puncturing to a parity puncturing unit.

IPC Classes  ?

• H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
• H03M 13/27 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
• H04L 1/22 - Arrangements for detecting or preventing errors in the information received using redundant apparatus to increase reliability

Abstract

A parity puncturing apparatus and method for variable length signaling information are disclosed. A parity puncturing apparatus according to an embodiment of the present invention includes memory configured to provide a parity bit string for parity puncturing for the parity bits of an LDPC codeword whose length is 16200 and whose code rate is 3/15, and a processor configured to puncture a number of bits corresponding to a final puncturing size from the rear side of the parity bit string.

IPC Classes  ?

• H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
• H03M 13/15 - Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
• H03M 13/27 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
• H04L 1/22 - Arrangements for detecting or preventing errors in the information received using redundant apparatus to increase reliability
• H04L 27/34 - Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems

Abstract

A zero padding apparatus and method for fixed length signaling information are disclosed. A zero padding apparatus according to an embodiment of the present invention includes a processor configured to generate a LDPC information bit string by deciding a number of groups whose all bits are to be filled with 0 using a difference between a length of the LDPC information bit string and a length of a BCH- encoded bit string, selecting the groups using a shortening pattern order to fill all the bits of the groups with 0, and filling at least a part of remaining groups, which are not filled with 0, with the BCH-encoded bit string; and memory configured to provide the LDPC information bit string to an LDPC encoder.

IPC Classes  ?

• H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
• H03M 13/15 - Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
• H03M 13/27 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques

Abstract

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64- symbol mapping.

IPC Classes  ?

• H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
• H03M 13/27 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
• H04L 1/24 - Testing correct operation
• H04L 27/36 - Modulator circuits; Transmitter circuits

Abstract

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64- symbol mapping.

IPC Classes  ?

• H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
• H03M 13/27 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
• H04L 1/24 - Testing correct operation
• H04L 27/36 - Modulator circuits; Transmitter circuits

Abstract

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 16- symbol mapping.

IPC Classes  ?

• H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
• H03M 13/27 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
• H04L 1/00 - Arrangements for detecting or preventing errors in the information received
• H04L 27/34 - Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems

Abstract

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256- symbol mapping.

IPC Classes  ?

• H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
• H03M 13/27 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques

Abstract

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check ( ) codeword having a length of 16200 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64- symbol mapping.

IPC Classes  ?

• H04L 27/38 - Demodulator circuits; Receiver circuits
• H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
• H03M 13/27 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
• H04L 1/22 - Arrangements for detecting or preventing errors in the information received using redundant apparatus to increase reliability

Abstract

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 16- symbol mapping.

IPC Classes  ?

• H04L 27/38 - Demodulator circuits; Receiver circuits
• H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
• H03M 13/27 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
• H04L 1/22 - Arrangements for detecting or preventing errors in the information received using redundant apparatus to increase reliability

Abstract

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64- symbol mapping.

IPC Classes  ?

• H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
• H03M 13/27 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques

Abstract

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256- symbol mapping.

IPC Classes  ?

• H04L 27/38 - Demodulator circuits; Receiver circuits
• H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
• H03M 13/27 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
• H04L 1/22 - Arrangements for detecting or preventing errors in the information received using redundant apparatus to increase reliability

Abstract

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation.

IPC Classes  ?

• H03M 13/27 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
• H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits

Abstract

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation.

IPC Classes  ?

• H03M 13/27 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
• H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits

Abstract

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation.

IPC Classes  ?

• H03M 13/27 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
• H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits

Abstract

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation.

IPC Classes  ?

• H04L 27/38 - Demodulator circuits; Receiver circuits
• H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
• H03M 13/27 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques

Abstract

84202222 ABSTRACT A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation. Date Recue/Date Received 2020-04-29

IPC Classes  ?

• H04L 27/38 - Demodulator circuits; Receiver circuits
• H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
• H03M 13/27 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques

Abstract

84202280 ABSTRACT A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation. Date Recue/Date Received 2020-04-21

IPC Classes  ?

• H04L 27/38 - Demodulator circuits; Receiver circuits
• H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
• H03M 13/27 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques

Abstract

An apparatus and method for broadcast signal frame using layered division multiplexing are disclosed. An apparatus for generating broadcast signal frame according to an embodiment of the present invention includes a combiner configured to generate a multiplexed signal by combining a core layer signal and an enhanced layer signal at different power levels; a power normalizer configured to reduce the power of the multiplexed signal to a power level corresponding to the core layer signal; a time interleaver configured to generate a time-interleaved signal by performing interleaving that is applied to both the core layer signal and the enhanced layer signal; and a frame builder configured to generate a broadcast signal frame including a preamble for signaling time interleaver information shared by the core layer signal and the enhanced layer signal, using the time-interleaved signal.

IPC Classes  ?

• H04N 21/2365 - Multiplexing of several video streams
• H04N 21/643 - Communication protocols

Abstract

An apparatus and method for broadcast signal reception are disclosed. A broadcast signal reception apparatus according to an embodiment of the present invention includes a time deinterleaver configured to perform time deinterleaving on a received signal corresponding to a broadcast signal frame, the broadcast signal frame including a preamble for signaling time interleaver information applied commonly for a core layer and an enhanced layer; a core layer BICM decoder configured to restore core layer data corresponding to the broadcast signal frame; an enhanced layer symbol extractor configured to extract enhanced layer symbols by performing cancellation corresponding to the core layer data; and an enhanced layer BICM decoder configured to restore enhanced layer data corresponding to the enhanced layer symbols, wherein the time interleaver information is information about a time interleaver operation.

IPC Classes  ?

• H04N 19/34 - Scalability techniques involving progressive bit-plane based encoding of the enhancement layer, e.g. fine granular scalability [FGS]
• H04N 21/2365 - Multiplexing of several video streams
• H04N 21/2383 - Channel coding of digital bit-stream, e.g. modulation
• H04N 21/643 - Communication protocols
• H04L 1/00 - Arrangements for detecting or preventing errors in the information received

Abstract

An apparatus and method for broadcast signal frame using layered division multiplexing are disclosed. An apparatus for generating broadcast signal frame according to an embodiment of the present invention includes a combiner configured to generate a multiplexed signal by combining a core layer signal and an enhanced layer signal at different power levels; a power normalizer configured to reduce the power of the multiplexed signal to a power level corresponding to the core layer signal; a time interleaver configured to generate a time-interleaved signal by performing interleaving that is applied to both the core layer signal and the enhanced layer signal; and a frame builder configured to generate a broadcast signal frame including a bootstrap and a preamble using the time-interleaved signal.

IPC Classes  ?

• H04H 20/95 - Arrangements characterised by special technical features of the broadcast information, e.g. signal form or information format characterised by a specific format, e.g. MP3 [MPEG-1 Audio Layer 3]
• H03M 13/27 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques

Abstract

An apparatus and method for broadcast signal frame using layered division multiplexing are disclosed. An apparatus for generating broadcast signal frame according to an embodiment of the present invention includes a combiner configured to generate a multiplexed signal by combining a core layer signal and an enhanced layer signal at different power levels; a power normalizer configured to reduce the power of the multiplexed signal to a power level corresponding to the core layer signal; a time interleaver configured to generate a time-interleaved signal by performing interleaving that is applied to both the core layer signal and the enhanced layer signal; and a frame builder configured to generate a broadcast signal frame including a bootstrap and a preamble using the time-interleaved signal.

IPC Classes  ?

• H04N 19/65 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using error resilience
• H04N 19/34 - Scalability techniques involving progressive bit-plane based encoding of the enhancement layer, e.g. fine granular scalability [FGS]
• H04N 19/70 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by syntax aspects related to video coding, e.g. related to compression standards
• H03M 13/27 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques

Abstract

A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword. The second memory is initialized to 0. The processor generates the LDPC codeword by performing accumulation with respect to the second memory using information bits. The accumulation is performed at parity bit addresses that are updated using a sequence corresponding to a parity check matrix (PCM).

IPC Classes  ?

• H04L 1/22 - Arrangements for detecting or preventing errors in the information received using redundant apparatus to increase reliability
• H04W 80/02 - Data link layer protocols
• H04N 19/89 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using pre-processing or post-processing specially adapted for video compression involving methods or arrangements for detection of transmission errors at the decoder
• H04L 1/24 - Testing correct operation

Abstract

A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword. The second memory is initialized to 0. The processor generates the LDPC codeword by performing accumulation with respect to the second memory using information bits. The accumulation is performed at parity bit addresses that are updated using a sequence corresponding to a parity check matrix (PCM).

IPC Classes  ?

• H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
• H04H 20/71 - Wireless systems
• H03M 13/27 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques

Abstract

A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 4/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).

IPC Classes  ?

• H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
• H04N 19/90 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using coding techniques not provided for in groups , e.g. fractals

Abstract

A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 4/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).

IPC Classes  ?

• H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
• H04N 19/90 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using coding techniques not provided for in groups , e.g. fractals

Abstract

A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 5/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).

IPC Classes  ?

• H04L 1/22 - Arrangements for detecting or preventing errors in the information received using redundant apparatus to increase reliability
• H04N 19/89 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using pre-processing or post-processing specially adapted for video compression involving methods or arrangements for detection of transmission errors at the decoder
• H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits

Abstract

81803474 ABSTRACT A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 4/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by perfomiing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM). 1 Date Recue/Date Received 2020-04-09

IPC Classes  ?

• H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
• H04N 19/90 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using coding techniques not provided for in groups , e.g. fractals

Abstract

A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 3/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).

IPC Classes  ?

• H04L 1/22 - Arrangements for detecting or preventing errors in the information received using redundant apparatus to increase reliability
• H04N 19/89 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using pre-processing or post-processing specially adapted for video compression involving methods or arrangements for detection of transmission errors at the decoder
• H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits

Abstract

83989039 ABSTRACT A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 5/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM). Date Recue/Date Received 2020-04-22

IPC Classes  ?

• H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
• H04N 19/44 - Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder

Abstract

A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 2/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).

IPC Classes  ?

• H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits

Abstract

A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 2/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).

IPC Classes  ?

• H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
• H04N 19/90 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using coding techniques not provided for in groups , e.g. fractals

Abstract

A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 3/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).

IPC Classes  ?

• H04L 1/22 - Arrangements for detecting or preventing errors in the information received using redundant apparatus to increase reliability
• H04W 80/02 - Data link layer protocols
• H04N 19/89 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using pre-processing or post-processing specially adapted for video compression involving methods or arrangements for detection of transmission errors at the decoder
• H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
• H04L 1/24 - Testing correct operation

Abstract

A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 2/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).

IPC Classes  ?

• H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
• H04N 19/90 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using coding techniques not provided for in groups , e.g. fractals

Abstract

A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 3/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).

IPC Classes  ?

• H04L 1/22 - Arrangements for detecting or preventing errors in the information received using redundant apparatus to increase reliability
• H04W 80/02 - Data link layer protocols
• H04N 19/89 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using pre-processing or post-processing specially adapted for video compression involving methods or arrangements for detection of transmission errors at the decoder
• H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
• H04L 1/24 - Testing correct operation

Abstract

A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 2/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).

IPC Classes  ?

• H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
• H04N 19/90 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using coding techniques not provided for in groups , e.g. fractals

Abstract

A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 5/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).

IPC Classes  ?

• H04L 1/22 - Arrangements for detecting or preventing errors in the information received using redundant apparatus to increase reliability
• H04W 80/02 - Data link layer protocols
• H04N 19/89 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using pre-processing or post-processing specially adapted for video compression involving methods or arrangements for detection of transmission errors at the decoder
• H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
• H04L 1/24 - Testing correct operation

Abstract

A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 5/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).

IPC Classes  ?

• H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
• H04N 19/90 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using coding techniques not provided for in groups , e.g. fractals

Abstract

A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 4/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).

IPC Classes  ?

• H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
• H04N 19/89 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using pre-processing or post-processing specially adapted for video compression involving methods or arrangements for detection of transmission errors at the decoder

Abstract

A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 3/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).

IPC Classes  ?

• H04L 1/22 - Arrangements for detecting or preventing errors in the information received using redundant apparatus to increase reliability
• H04N 19/89 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using pre-processing or post-processing specially adapted for video compression involving methods or arrangements for detection of transmission errors at the decoder
• H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits

Abstract

An apparatus and a method for transmitting a broadcast signal using a layered division multiplexing are disclosed. An apparatus for transmitting a broadcasting signal according to an embodiment of the present invention comprises: a combiner that generates a multiplexed signal by combining a core layer signal and an enhanced layer signal at different power levels; a power normalizer that lowers power of the multiplexed signal to a power corresponding to the core layer signal; a time interleaver that generates a time-interleaved signal by performing interleaving that is applied to both the core layer signal and the enhanced layer signal; a frame builder that generates a frame of the broadcast signal using the time-interleaved signal; and an OFDM transmitter that generates a pilot signal shared by the core layer corresponding to the core layer signal and the enhanced layer corresponding to the enhanced layer signal.

IPC Classes  ?

• H04L 27/26 - Systems using multi-frequency codes

Abstract

A broadcast signal reception apparatus and method using layered division multiplexing are disclosed. A broadcast signal reception apparatus has an OFDM receiver for generating a received signal, a time deinterleaver for performing time deinterleaving on the received signal corresponding to a broadcast signal frame; a core layer BICM decoder for restoring core layer data corresponding to the broadcast signal frame; an enhanced layer symbol extractor for extracting enhanced layer symbols by performing cancellation corresponding to the core layer data using the output from the core layer BICM decoder; and an enhanced layer BICM decoder for restoring restore enhanced layer data corresponding to the enhanced layer symbols. The OFDM receiver uses a pilot signal that is shared by a core layer corresponding to the core layer data and an enhanced layer corresponding to the enhanced layer data.

IPC Classes  ?

• H04N 21/2383 - Channel coding of digital bit-stream, e.g. modulation
• H04N 19/34 - Scalability techniques involving progressive bit-plane based encoding of the enhancement layer, e.g. fine granular scalability [FGS]
• H04J 11/00 - Orthogonal multiplex systems
• H04N 5/44 - Receiver circuitry

Abstract

A signal multiplexing apparatus and method using layered division multiplexing are disclosed. A signal multiplexing apparatus according to an embodiment of the present invention includes a combiner configured to generate a multiplexed signal by combining a core layer signal and an enhanced layer signal at different power levels; a power normalizer configured to reduce the power of the multiplexed signal to a power level corresponding to the core layer signal; a time interleaver configured to generate a time-interleaved signal by performing interleaving that is applied to both the core layer signal and the enhanced layer signal; and a frame builder configured to generate a broadcast signal frame using the time-interleaved signal and L1 signaling information.

IPC Classes  ?

• H04N 7/08 - Systems for the simultaneous or sequential transmission of more than one television signal, e.g. additional information signals, the signals occupying wholly or partially the same frequency band

Abstract

A signal multiplexing apparatus and method using layered division multiplexing are disclosed. A signal multiplexing apparatus according to an embodiment of the present invention includes a combiner configured to generate a multiplexed signal by combining a core layer signal and an enhanced layer signal at different power levels; a power normalizer configured to reduce the power of the multiplexed signal to a power level corresponding to the core layer signal; a time interleaver configured to generate a time-interleaved signal by performing interleaving that is applied to both the core layer signal and the enhanced layer signal; and a frame builder configured to generate a broadcast signal frame using the time-interleaved signal and Ll signaling information.

IPC Classes  ?

• H04N 19/34 - Scalability techniques involving progressive bit-plane based encoding of the enhancement layer, e.g. fine granular scalability [FGS]
• H04N 19/70 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by syntax aspects related to video coding, e.g. related to compression standards

Abstract

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation.

IPC Classes  ?

• H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
• H03M 13/27 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques

Abstract

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64- symbol mapping.

IPC Classes  ?

• H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
• H03M 13/27 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
• H04L 1/00 - Arrangements for detecting or preventing errors in the information received
• H04L 27/34 - Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems

Abstract

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 10/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256- symbol mapping.

IPC Classes  ?

• H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
• H03M 13/27 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
• H04L 1/00 - Arrangements for detecting or preventing errors in the information received
• H04L 27/34 - Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems

Abstract

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation.

IPC Classes  ?

• H04L 27/38 - Demodulator circuits; Receiver circuits
• H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
• H03M 13/27 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
• H04L 1/22 - Arrangements for detecting or preventing errors in the information received using redundant apparatus to increase reliability

Abstract

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 16- symbol mapping.

IPC Classes  ?

• H03M 13/27 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
• H04H 40/18 - Arrangements characterised by circuits or components specially adapted for receiving
• H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
• H04L 27/38 - Demodulator circuits; Receiver circuits

Abstract

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 10/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.

IPC Classes  ?

• H04L 27/38 - Demodulator circuits; Receiver circuits
• H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
• H03M 13/27 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
• H04L 1/22 - Arrangements for detecting or preventing errors in the information received using redundant apparatus to increase reliability

Abstract

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 16- symbol mapping.

IPC Classes  ?

• H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
• H03M 13/27 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
• H04L 1/00 - Arrangements for detecting or preventing errors in the information received
• H04L 27/34 - Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems

Abstract

A bit interieaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, an'd a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64- symbol mapping.

IPC Classes  ?

• H04L 27/38 - Demodulator circuits; Receiver circuits
• H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
• H03M 13/27 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
• H04L 1/22 - Arrangements for detecting or preventing errors in the information received using redundant apparatus to increase reliability

Abstract

An apparatus and method for multiplexing signals using layered division multiplexing are disclosed. A signal multiplexing apparatus according to an embodiment of the present invention includes a combiner configured to combine a core layer signal and an enhanced layer signal at different power levels to generate a multiplexed signal, a power normalizer configured to reduce power of the multiplexed signal to power corresponding to the core layer signal, and a time interleaver configured to perform interleaving applied to both the core layer signal and the enhanced layer signal.

IPC Classes  ?

• H04L 27/26 - Systems using multi-frequency codes
• H03M 13/27 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
• H04L 1/00 - Arrangements for detecting or preventing errors in the information received

Abstract

An apparatus and method for multiplexing signals using layered division multiplexing are disclosed. A signal multiplexing apparatus according to an embodiment of the present invention includes a combiner configured to combine a core layer signal and an enhanced layer signal at different power levels to generate a multiplexed signal, a power normalizer configured to reduce power of the multiplexed signal to power corresponding to the core layer signal, and a time interleaver configured to perform interleaving applied to both the core layer signal and the enhanced layer signal.

IPC Classes  ?

• H04L 27/26 - Systems using multi-frequency codes
• H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
• H03M 13/27 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
• H04L 1/00 - Arrangements for detecting or preventing errors in the information received

Abstract

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256- symbol mapping.

IPC Classes  ?

• H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
• H03M 13/27 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
• H04L 27/38 - Demodulator circuits; Receiver circuits
• H04L 1/22 - Arrangements for detecting or preventing errors in the information received using redundant apparatus to increase reliability

Abstract

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256- symbol mapping.

IPC Classes  ?

• H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
• H03M 13/27 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques

Abstract

Disclosed are a signal multiplexing device and method using layered division multiplexing. The signal multiplexing method, according to one embodiment of the present invention, comprises: a combiner for combining a core layer signal and an enhanced layer signal in power levels different from each other; and a time interleaver for performing interleaving which is applied to both the core layer signal and the enhanced layer signal.

IPC Classes  ?

• H04L 27/26 - Systems using multi-frequency codes
• H03M 13/27 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
• H04L 1/00 - Arrangements for detecting or preventing errors in the information received

Abstract

An apparatus and method for multiplexing signals using layered division multiplexing are disclosed. A signal multiplexing apparatus according to an embodiment of the present invention includes a combiner configured to combine a core layer signal and an enhanced layer signal at different power levels, and a time interleaver configured to perform interleaving applied to both the core layer signal and the enhanced layer signal.

IPC Classes  ?

• H04L 27/26 - Systems using multi-frequency codes
• H03M 13/27 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
• H04L 5/22 - Arrangements affording multiple use of the transmission path using time-division multiplexing

Abstract

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 5/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64- symbol mapping.

IPC Classes  ?

• H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
• H03M 13/27 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
• H04L 1/24 - Testing correct operation
• H04L 27/36 - Modulator circuits; Transmitter circuits

Abstract

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 5/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64- symbol mapping.

IPC Classes  ?

• H04L 27/38 - Demodulator circuits; Receiver circuits
• H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
• H03M 13/27 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
• H04L 1/24 - Testing correct operation

Abstract

A modulator and a modulation method using a non-uniform 16-symbol signal constellation are disclosed. The modulator includes a memory and a processor. The memory receives a codeword corresponding to a low-density parity check (LDPC) code having a code rate of 2/15. The processor maps the codeword to 16 symbols of the non-uniform 16-symbol signal constellation on a 4-bit basis.

IPC Classes  ?

• H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
• H03M 13/27 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
• H03M 13/31 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining coding for error detection or correction and efficient use of the spectrum
• H04L 1/24 - Testing correct operation
• H04L 27/34 - Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems

Abstract

A modulator and a modulation method using a non-uniform 16-symbol signal constellation are disclosed. The modulator includes a memory and a processor. The memory receives a codeword corresponding to a low-density parity check (LDPC) code having a code rate of 4/15. The processor maps the codeword to 16 symbols of the non-uniform 16-symbol signal constellation on a 4-bit basis.

IPC Classes  ?

• H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
• H03M 13/27 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
• H03M 13/31 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining coding for error detection or correction and efficient use of the spectrum
• H04L 1/24 - Testing correct operation
• H04L 27/34 - Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems

Abstract

A modulator and a modulation method using a non-uniform 16-symbol signal constellation are disclosed. The modulator includes a memory and a processor. The memory receives a codeword corresponding to a low-density parity check (LDPC) code having a code rate of 2/15. The processor maps the codeword to 16 symbols of the non-uniform 16-symbol signal constellation on a 4-bit basis.

IPC Classes  ?

• H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
• H04H 20/00 - Arrangements for broadcast or for distribution combined with broadcast
• H03M 13/27 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
• H03M 13/31 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining coding for error detection or correction and efficient use of the spectrum
• H04L 27/34 - Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems

Abstract

A modulator and a modulation method using a non-uniform 16-symbol signal constellation are disclosed. The modulator includes a memory and a processor. The memory receives a codeword corresponding to a low-density parity check (LDPC) code having a code rate of 4/15. The processor maps the codeword to 16 symbols of the non-uniform 16-symbol signal constellation on a 4-bit basis.

IPC Classes  ?

• H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
• H04H 20/00 - Arrangements for broadcast or for distribution combined with broadcast
• H03M 13/27 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
• H03M 13/31 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining coding for error detection or correction and efficient use of the spectrum
• H04L 27/34 - Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems

Abstract

A modulator and a modulation method using a non-uniform 16-symbol signal constellation are disclosed. The modulator includes a memory and a processor. The memory receives a codeword corresponding to a low-density parity check (LDPC) code having a code rate of 2/15. The processor maps the codeword to 16 symbols of the non-uniform 16-symbol signal constellation on a 4-bit basis.

IPC Classes  ?

• H04L 27/34 - Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems
• H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
• H03M 13/27 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
• H04L 1/24 - Testing correct operation

Abstract

A modulator and a modulation method using a non-uniform 16-symbol signal constellation are disclosed. The modulator includes a memory and a processor. The memory receives a codeword corresponding to a low-density parity check (LDPC) code having a code rate of 4/15. The processor maps the codeword to 16 symbols of the non-uniform 16-symbol signal constellation on a 4-bit basis.

IPC Classes  ?

• H04L 27/34 - Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems
• H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
• H03M 13/27 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
• H04L 1/24 - Testing correct operation