Methods and systems for verifying, via formal verification, a hardware design for a data transformation pipeline comprising one or more data transformation elements that perform a data transformation on one or more inputs, wherein the formal verification is performed under conditions that simplify the data transformations calculations that the formal verification tool has to perform. In one embodiment the hardware design for the data transformation pipeline is verified by formally verifying that the output of an instantiation of the hardware design produces the same output as an instantiation of a hardware design for another data transformation pipeline for a predetermined set of transactions under a constraint that substantially equivalent data transformation elements between the data transformation pipelines produce the same output(s) in response to the same input(s).
Methods and systems for verifying, via formal verification, a hardware design for a data transformation pipeline comprising one or more data transformation elements that perform a data transformation on one or more inputs, wherein the formal verification is performed under conditions that simplify the data transformations calculations that the formal verification tool has to perform. In one embodiment the hardware design for the data transformation pipeline is verified by replacing one or more of the data transformation elements in the hardware design with a function element which is treated as an unevaluated function of its combinational inputs by a formal verification tool such that during formal verification the function element will produce the same output for the same inputs, and formally verifying that for each transaction of a set of transactions an instantiation of the modified hardware design for the data transformation pipeline produces a set of one or more outputs that matches a reference set of one or more outputs for that transaction.
A method of detecting a bug in a counter of a hardware design that includes formally verifying, using a formal verification tool, an inductive assertion from a non-reset state of the hardware design. The inductive assertion establishes a relationship between the counter and a test bench counter at two or more points in time, !f the formal verification tool identifies at least one valid state of the counter in which the inductive assertion is not true, information is output indicating a location of a bug in the counter or the test bench counter.
The operation of a GPU is controlled based on one or more deadlines by which one or more GPU tasks must be completed and estimates of the time required to complete the execution of a first GPU task (which is currently being executed) and the time required to execute one or more other GPU tasks (which are not currently being executed). Based on a comparison between the deadline(s) and the estimates, context switching may or may not be triggered.
The operation of a GPU is controlled based on one or more deadlines by which one or more GPU tasks must be completed and estimates of the time required to complete the execution of a first GPU task (which is currently being executed) and the time required to execute one or more other GPU tasks (which are not currently being executed). Based on a comparison between the deadiine(s) and the estimates, the operating parameters of the GPU may be changed.
A method of identifying a network condition between a pair of network devices, the method comprising: determining a first time period between receiving a first-received packet for an initial media frame and receiving a first-received packet for a subsequent media frame, wherein the packets are received at one of the devices via a network and each received packet comprises a timestamp; determining a second time period between the timestamp of the packet for the initial media frame and the timestamp of the packet for the subsequent media frame; and identifying a network condition in dependence on a difference between the first and second time periods.
A method of identifying a network condition between a pair of network devices, wherein one of the devices comprises a jitter buffer for storing packets received via a network, the method comprising: monitoring a measure of delay in receiving media packets over the network; monitoring a size of the jitter buffer; and identifying a network condition in dependence on a change in the measure of delay and a variation in the size of the jitter buffer.
Methods of notifying a user that an electrical appliance is in a fault state that include predicting that the electrical appliance is to be activated at a particular time; and prior to the particular time, determining from an electrical power circuit associated with the electrical appliance whether the electrical appliance is in a fault state and cannot be activated. If it is determined that the electrical appliance is in a fault state and cannot be activated a determination is made whether the user is proximate the electrical appliance. If it is determined that the user is proximate the electrical appliance then the user is notified that the electrical appliance is in a fault state and cannot be activated.
A digital broadcast receiver for implementing service following using locally saved service following information. The digital broadcast receiver includes an interface configured to receive service following information from a user; a storage module configured to store the received service following information; a digital broadcast receiver module configured to receive a digital broadcast signal; a signal quality detection unit configured to monitor the quality of the received digital broadcast signal; and a processor configured to, in response to the signal quality detection unit detecting the quality of the received digital broadcast signal is below an acceptable level, select an alternate broadcast signal to receive based on the stored service following information.
Systems and methods of geometry processing, for rasterization and ray tracing processes provide for pre-processing of source geometry, such as by tessellating or other procedural modification of source geometry, to produce final geometry on which a rendering will be based. An acceleration structure (or portion thereof) for use during ray tracing is defined based on the final geometry. Only coarse-grained elements of the acceleration structure may be produced or retained, and a fine-grained structure within a particular coarse-grained element may be produced in response to a collection of rays being ready for traversal within the coarse-grained element. Final geometry can be recreated in response to demand from a rasterization engine, and from ray intersection units that require such geometry for intersection testing with primitives. Geometry at different resolutions can be generated to respond to demands from different rendering components.
Methods and apparatus are provided for compressing and decompressing image data by producing two sets of reduced size image data, generating a modulation value for each elementary of the area from the image data, the modulation value encoding information about how to combine the sets of reduced size image data to generate an approximation to the image. In one arrangement, a set of index values is generated corresponding to a set of modulation values for each of the respective elementary areas of a group of elementary areas and these are assigned to each respective group and a second set of index values corresponding to one of the set of first index values for each elementary areas is assigned to each first group of elementary areas. These index values are then stored for use in deriving modulation data more accurately when decompressing the image data. In another arrangement a modulation mode is selected which includes a plurality of modulation values and one of the modulation values is assigned to each elementary area in each block of elementary areas of the image for use in recombining the reduced size image data to generate an approximation to the image. The modulation value is selected with a plurality of bits of index data for each elementary area. In another arrangement, a modulation from a set of possible modulation values is assigned to each elementary area in a group of elementary areas and is represented by a plurality of bits of modulation data. This arrangement is varied by providing modulation values which relate to each alternate elementary area and then either interpolating modulation values vertically or horizontally for each other elementary area or by interpolating either vertically or horizontally image data once sets of reduced sized image data have been recombined with the modulation data.
A wireless media distribution system is provided comprising an access point (6) for broadcasting media and a plurality of stations (2) for reception and playback of media. Each station is configured for receiving and decoding a timestamp in a beacon frame transmitted repeatedly from the access point. This is used to control the output signal of a station physical layer clock (12) which is then used as a clock source for an application layer time synchronisation protocol. This application layer time synchronisation protocol can then be used in the station to control an operating system clock (8) for regulating playback of media.
An RF antenna system is provided for mounting on a window of a vehicle comprising exterior and interior window mountable portions. The first and second portions include an RF coupling section (4) to inductively couple an RF signal received from antenna (20) and a power coupling section (6) for providing external power to an external amplification portion (52) for amplifying received RF signals. The system includes a further electrical connection (16) to a metallic shim (18) which is magnetically fixed to the roof of the vehicle and electrically connected thereto, whereby the roof provides a ground plane for the antenna, by capacitive coupling of the metallic shim to the vehicle roof.
A method and apparatus are provided for compressing a list of primitives in a computer graphics system from a tessellated patch of surface data. Uncompressed domain point indices (2410) are received and stored in an index buffer (2420). The domain point index for the next primitive in the list is compared (2430) with the domain point indices stored in the buffer to determine any matches. The domain point indices of the next primitive are stored in the buffer or, where a match was found, a reference to the position of the matched index. The step of storing the domain point indices in the buffer (2430) includes the storage of a further predicted domain point index which is computed from the domain point indices stored in the buffer. Compressed domain point indices (2490) for the tessellated patch are then output from the buffer. The domain point index value may split into a base identifier as an offset from that base position. The base identifier comprises a row number for point or line primitives or a ring/edge number for triangular primitives.
A method and apparatus are provided for compressing depth buffer data in a three dimensional computer graphics system. The depth buffer data is divided into a plurality of rectangular tiles corresponding to rectangular areas in an associated image. The number of starting point locations in a tile are identified and a difference in depth value determined between each starting point and depth values of each of at least two further locations. Using this information depth values are predicted at a plurality of other locations in the tile and where these predicated values substantially match an actual depth value at location is assigned to a plane associated with respective starting point. Starting point location depth value difference data and plane assignment data for each tile and locations in the tile not assigned to a plane, then stored.
A microprocessor configured to execute programs divided into discrete phases, comprising: a scheduler for scheduling program instructions to be executed on the processor; a plurality of resources for executing programming instructions issued by the scheduler; wherein the scheduler is configured to schedule each phase of the program only after receiving an indication that execution of the preceding phase of the program has been completed. By splitting programs into multiple phases and providing a scheduler that is able to determine whether execution of a phase has been completed, each phase can be separately scheduled and the results of preceding phases can be used to inform the scheduling of subsequent phases.
G06F 9/38 - Concurrent instruction execution, e.g. pipeline, look ahead
G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
G06F 15/80 - Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
G06T 1/20 - Processor architectures; Processor configuration, e.g. pipelining
G06F 9/48 - Program initiating; Program switching, e.g. by interrupt
G06F 9/50 - Allocation of resources, e.g. of the central processing unit [CPU]
A method for converting an interlaced video signal to a non-interlaced video signal, comprising, for each pixel in each missing line of a video field in the interlaced video signal: deriving a correlation data set comprising correlation data for each of a plurality of possible interpolation schemes to be used in reconstructing the pixel; dividing each correlation data set into a plurality of correlation data zones; selecting an interpolation scheme from each correlation data zone; reconstructing the pixel using a blend of the selected interpolation schemes, wherein the blend for each pixel subsequent to a first pixel is determined based on the result of a comparison between the selected interpolation schemes and based on the blend used for a preceding pixel.
A method and apparatus are provided for compressing vertex parameter data in a 3D computer graphic system, where the vertex parameter data is a data block relating to a plurality of vertices used for rendering an image. The data relating to each vertex includes multiple byte data relating to at least one parameter. The parameters include X, Y and Z coordinates and further coordinates for texturing and shading. The multiple byte data is divided into individual bytes and bytes with corresponding byte positions relating to each vertex are grouped together to form a plurality of byte blocks. In one embodiment at least one of the byte blocks is compressed by storing at least one byte in a byte block as a byte origin and storing each of the remaining bytes in the byte block as a difference value from one of the byte origins. In the second embodiment at least one the byte blocks is compressed by identifying the unique bytes in the byte block, storing at least one of the unique bytes as a raw byte origin in a byte delta table, storing in the byte delta table remaining unique bytes as difference values from the preceding byte or from the byte origin, and forming a byte index encoding the bytes in the byte block by reference to the byte delta table. Decompression means are also provided for decompressing vertex parameter data thus compressed. These are able to access randomly the compressed data, rather than having to read a stream of data.
A hardware circuit component for executing multiple sum-of-products operations is manufactured as follows. A set of multiplexed sum-of-products functions of a plurality of operands (a, b, c,... ), any one of which functions can be selected in dependence upon a select value (sel) by multiplex operations, is received. The sum-of-products functions are then rearranged in a particular manner. The rearranged set of sum-of-products functions is merged into a single merged sum-of-products function containing one or more multiplexing operations. From this a layout design can be generated, and a hardware circuit component such as an integrated circuit manufactured from the layout design. The step of re-arranging the multiple sum-of-products functions comprises aligning the elements of the set of sum-of-products functions in such a manner that the amount of multiplexing in the single merged sum-of-products function is less than in the input set of sum-of-products functions. Additionally, negative terms in the sum-of-products functions are selectively negated so that particular products are always positive.
G06F 7/544 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices for evaluating functions by calculation
20.
TESSELLATION OF PATCHES OF SURFACES IN A TILE BASED RENDERING SYSTEM
A method and apparatus are provided for tessellating patches of surfaces in a tile based three dimensional computer graphics rendering system. For each tile in an image a per tile list of primitive indices is derived for tessellated primitives which make up a patch. Hidden surface removal is then performed on the patch and any domain points which remain after hidden surface removal are derived. The primitives are then shaded for display.
A method and apparatus are provided for motion compensated video interpolation. Each field or frame in a sequence of video images is subdivided into a plurality of blocks and a motion vector field is derived using block matching for a current video field using data matched to a previous video field or frame. A first time instance is determined at which an interpolated block is to be displayed and a second time instance is determined at which a corresponding interpolated block is to be created. Video data for each block is interpolated at its second time instance for each block and is then output for display at the first time instance.
A method and apparatus are provided for shading and texturing computer graphic images in a tile based rendering system using dynamically rendered textures. Scene space geometry is derived for a dynamically rendered texture and passed to a tiling unit which derives scene space geometry for a scene which references the textures. Scene space geometry for a scene that references the dynamically rendered texture is also derived and passed to the tiling unit. The tiling unit uses object data derived from the scene space geometry to detect reference to areas of dynamically rendered textures, as yet un-rendered. These are then dynamically rendered.
The present invention relates to improved methods for processing requests and sending data in a bus architecture. The present invention further relates to an improved bus architecture for processing requests and data. There is provided a method for processing read requests in a bus architecture comprising at least one master device connected to at least two slave devices via a bus. The architecture comprises an allocator for allocating incoming requests from the master device to a target slave device and an optimiser for each slave device. Each optimiser is for buffering incoming requests for the respective slave device. The method comprising the steps of: a) the master device sending a read request for a first slave device to the bus; b) the allocator generating a current-state indicator associated with the read request. The current-state indicator has an initial value, The method further comprises c) the allocator generating a priority indicator associated with the read request; d) the allocator sending the read request, the current-state indicator and the priority indicator to the optimiser of the first slave device; e) the optimiser of the first slave device receiving the read request, the current-state indicator and the priority indicator. Finally, if the initial value of the current-state indicator equals the value of the priority indicator, the method comprises processing the read request; or if the initial value of the current-state indicator does not equal the value of priority indicator, the method comprises deferring processing of the read request until a later time.
There is provided a method and apparatus for managing memory in a system for generating 3-dimensional computer images. The image is subdivided into a plurality of rectangular areas. A memory is provided and a page of the memory is allocated for storing object data for objects in the image. Object data for objects in the image are then written to the allocated page of memory. Finally, a bit mask for the allocated page of memory is compiled, the bit mask indicating the rectangular areas having object data stored in the allocated page of memory. A rectangular area of the image can then be rendered by deriving data for display from the object data stored in the memory, for objects in that rectangular area. Once the rectangular area has been rendered, the bit mask for each page of memory which stored, before the step of rendering, object data for that rectangular area, is updated so that the bit mask no longer indicates that rectangular area.
A method and apparatus are provided for receiving an RF service. At least two RF channels (26) are received. Each channel comprises a plurality of time slice services. A selected RF service is decoded from its time sliced portion with a first RF channel in a decoder (24). During periods non-intersecting with that portion of the first RF channel data from a second RF channel is decoded to determine RF services available on the second RF channel. This data is then provided for display.
There is provided a method for texturing and shading a 3D computer graphic image on a plurality of shading engines. First, the image is subdivided into a plurality of tiles and each tile is subdivided into a plurality of micro tiles. An object list is allocated to each tile, the object list containing data defining objects visible in the tile. For one micro tile, it is determined which pixels in the micro tile are intersected by an object A in the object list and it is determined which pixels in the micro tile are intersected by at least one other object in the object list. In parallel with the determination step, pixel intersection data is outputted for an object B for which all intersection determinations for each of the micro tiles in a selected tile have been performed. The pixel intersection data is output to at least one of the plurality of shading engines. Then, those steps are repeated for each micro tile in the selected tile in which there are visible objects. The pixels corresponding to the pixel intersection data for the object B are textured and shaded with the at least one of the plurality of shading engines. Finally, the data derived by the texturing and shading is stored.
A method and apparatus are provided for motion estimation in a sequence of images. One or more motion vectors representing movement of a camera or viewer position or direction are determined between each pair of fields or frames in the sequence of images. A set of candidate motion vectors is then determined for deriving positions of objects in a field or frame from the positions of objects in a previous field or frame. This set of candidate motion vectors is adjusted using the motion vectors representing movement of camera or viewer position and thus a set of motion vectors is derived for a sequence of images using the adjusted set of candidate motion vectors.
A touch sensitive screen system is provided for strolling through a set of data displayed on the screen. A plurality of touch sensitive areas (A, B, C, D, E) are provided. Contact movement with a central area (A) commences scrolling of data displayed on the screen. Movement of the contact into one of a plurality of edge portions (B, C, D, E) causes scrolling of the data to continue.
A method and apparatus are provided for displaying data on a touch sensitive display (2). A detector (4) and CPU (6) detect contact with the touch sensitive display (2) and control the display of data. The system is responsive to a predetermined swiping duration of a finger on the display or to a manual selectable switch to change the display of data between a scrolling of data and a paging of data.
A method and apparatus for rendering a computer generated image using a stencil buffer is described. The method divides an arbitrary closed polygonal contour into first and higher level primitives, where first level primitives correspond to contiguous vertices in the arbitrary closed polygonal contour and higher level primitives correspond to the end vertices of consecutive primitives of the immediately preceding primitive level. The method reduces the level of overdraw when rendering the arbitrary polygonal contour using a stencil buffer compared to other image space methods. A method of producing the primitives in an interleaved order, with second and higher level primitives being produced before the final first level primitives of the contour, is described which improves cache hit rate by reusing more vertices between primitives as they are produced.
There is provided a method to dynamically determine which instructions from a plurality of available instructions to issue in each clock cycle in a multithreaded processor capable of issuing a plurality of instructions in each clock cycle, comprising the steps of: determining a highest priority instruction from the plurality of available instructions; determining the compatibility of the highest priority instruction with each of the remaining available instructions; and issuing the highest priority instruction together with other instructions compatible with the highest priority instruction in the same clock cycle; wherein the highest priority instruction cannot be a speculative instruction. The effect of this is that speculative instructions are only ever issued together with at least one non- speculative instruction.
There is provided a method and apparatus for motion estimation in a sequence of video images. The method comprises a) subdividing each field or frame of a sequence of video images into a plurality of blocks, b) assigning to each block in each video field or frame a respective set of candidate motion vectors, c) determining for each block in a current video field or frame, which of its respective candidate motion vectors produces a best match to a block in a previous video field or frame, d) forming a motion vector field for the current video field or frame using the thus determined best match vectors for each block, and e) forming a further motion vector field by storing a candidate motion vector derived from the best match vector at a block location offset by a distance derived from the candidate motion vector. Finally, steps a) to e) are repeated for a video field or frame following the current video field or frame. The set of candidate motion vectors assigned at step b) to a block in the following video field or frame includes the candidates stored at that block location at step e) during the current video field or frameThe method enables a block or tile based motion estimator to improve its accuracy by introducing true motion vector candidates derived from the physical behaviour of real world objects.
There is provided an apparatus for controlling memory access in a multithreaded processor supporting a plurality of threads, comprising: a processor core; a cache memory storing data accessible by each of the plurality of threads; a main memory storing data accessible by a plurality of threads; an incoherency detection module; and a memory arbiter, wherein the incoherency detection module is connected between the processor core and the memory arbiter, and the memory arbiter is connected between the incoherency detection module and the main memory and wherein there is a separate request queue for each thread for read and write requests sent from the cache memory to the memory arbiter; wherein, in use, the incoherency detection module stores an indication of a memory address for each write request sent from the cache memory to the main memory in a write address memory, and compares the address of each subsequent read request sent from the cache memory with indications in the write address memory and, if the address of the subsequent read request matches an indication, inserts a barrier corresponding to the read request into the request queue of the thread to which the matching indication belongs, and wherein the memory arbiter prevents the read request from accessing the memory bus until the corresponding barrier has been received by the memory arbiter.
A method and apparatus are provided for executing instructions of a multi-threaded processor having multiple hardware threads (32, 34) with differing hardware resources comprising the steps of receiving a plurality of streams of instructions (38, 44) and determining which hardware threads are able to receive instructions for execution (40, 46), determining whether a thread determined to be available for executing an instructions has the hardware resources available required by that instructions (36) and executing the instruction in dependence on the result of the determination (50).
A method and apparatus are provided for rendering a 3 dimensional computer graphics image. The image is subdivided into a plurality of rectangular areas and primitives which may be visible in the image are assigned to respective ones of a plurality of primitive blocks. A determination is made as to which primitive blocks contain primitives which intersect each rectangular area. The rectangular areas are then grouped into a plurality of fixed size groups and control stream data for each of the fixed size groups is derived, this control stream data including data which determines which primitive blocks are required to render the rectangular areas in each respective first fixed size group. The control stream data is then used to render the image for display.
A method and apparatus are provided for rendering a 3 dimensional computer graphics image. The image is divided into plurality of rectangular tiles which are arranged in a multi level structure comprising a plurality of levels of progressively larger groupings of tiles. Image data is divided into a plurality of primitive blocks and these are assigned to groupings of tiles within the multi level structure in dependence on the groupings each one intersects. Control stream data is derived for rendering the image and this comprises references to primitive blocks for each grouping of tiles within each level of the multi level structure, the references corresponding to the primitive blocks assigned to each grouping and control stream data is used to render the primitive data into tiles within the groupings of tiles for display. This is done such that for primitive blocks which intersect a plurality of tiles within a grouping, control stream data is written for the grouping of tiles rather than for each tile within the grouping.
The invention is a method and system for providing trace data in a pipelined data processor. Aspects of the invention include providing a trace pipeline in parallel to the execution pipeline, providing trace information on whether conditional instructions complete or not, providing trace information on the interrupt status of the processor, replacing instructions in the processor with functionally equivalent instructions that also produce trace information and modifying the scheduling of instructions in the processor based on the occupancy of a trace output buffer.
There is provided a method and apparatus for scene change detection for use with bit-rate control of a video compression system. The method and apparatus may be used for scene change detection in intra-coded and/or inter-coded pictures. The method comprises the steps of: compressing each picture in a video signal in turn; determining complexity data from the compressed signal for each picture after partial compression of the picture; determining from the complexity data whether a scene change may have taken place; and adjusting the compression step and allocated compressed bit number for pictures after a scene change detection in dependence on the result of the determination. For an intra-coded picture, the complexity data is a monotonically increasing function of a quantisation parameter and a compressed bit number used in the compression step for the partial compression from which the complexity data is determined. For an inter-coded picture, the complexity data is determined from a combination of a) the change of temporal prediction difference in relation to the average prediction difference of previous inter-coded pictures, b) the intra-coded macroblock number in the current inter-coded picture in relation to the average intra-coded macroblock number in previous inter-coded pictures, and c) the intra- coded macroblock number in the current inter-coded picture in relation to the total encoded macroblock number in the current inter-coded picture.
A method and apparatus are provided for performing overlap transform and deblocking of a decompressed video signal. The video image is sub-divided into a plurality of non-overlaping macroblocks, each of which comprises a plurality of smaller sub- blocks. Each macroblocks comprises two luminance partitions and one chrominance partition. Each partition is buffered and further buffering is provided for sub-blocks of each partition. Overlap transform and deblocking are performed by buffering sub-blocks from current partitions and sub-blocks from partitions from adjacent macroblocks. Overlap transform is performed in the current macroblock for buffered sub-blocks and deblocking is performed for blocks in the adjacent macroblocks.
A method and apparatus are provided for video edge filtering in which a buffer stores pixels required for edge filtering from a plurality of macroblocks. An input tile buffering unit comprising a plurality of dual port tile buffers receives tile portions of each macroblock. These are transposed selectively and provided to a programmable edge filter which performs one dimensional edge filtering on the tile portions. The filtered edges are then selectively transposed in a opposite manner to the first transpose unit and provided to an output buffer as well as provided back to the dual port tile buffers for use in further filtering.
A method and apparatus are provided for reducing parameter and memory usage in a tiled based rendering system. Position data is retrieved from stored static geometry data in a memory and is transformed to screen space. The screen space position data is then used to compile a list of pointers to static geometry data in memory from which the position data was retrieved. This pointer data is then retrieved for each tile and the static geometry data corresponding to the retrieved pointer data is retrieved for each tile. Thus the retrieved geometry data is transformed to screen space and any attribute processing is applied to it prior to hidden surface removal and a transform data is then rendered to a buffer for display.
A method and apparatus are provided for executing instructions from a plurality of instruction threads on a multi-threaded processor. The instruction threads may each include instructions of different complexity. A plurality of pipelines for executing instructions are provided and an instruction scheduler determines on each clock cycle the pipelines upon which instructions will be executed. Some of the pipelines are configured to appear to the instruction threads as single pipelines but in fact comprise two pipeline paths, one for executed instructions of lower complexity and the other. The instruction scheduler determines on which of the two pipeline paths an instruction should execute.
A method and system are provided for prioritising the fetching of instructions for each of a plurality of executing instruction threads in a multi-threaded processor. Instructions come from at least one source of instructions. Each thread has a number of threads buffered for execution in an instruction buffer (34). A first metric for each thread is determined based on the number of instructions currently buffered. A second metric is then determined for each thread, this being an execution based metric. A priority order for the threads is determined from the first and second metrics, and an instruction is fetched from the source for the thread with the highest determined priority which is requesting an instruction.
A method and apparatus are provided for video motion compensation suitable for use in decoding compressed video. An input buffer receives lines of blocks of video data and outputs lines of these to a first block transpose unit (52). This can selectively transpose the lines and columns of an input block of pixels. A vertical line filtering unit (58) is coupled to the block transpose unit for producing an output line of interpolated pixel samples. A first selector with inputs coupled to the output of the vertical line filtering unit and to the output of the input block transpose unit is able to select between an un-interpolated output line of pixels and an interpolated output line of pixel samples. A second selector (62) with inputs coupled to the outputs of the first block transpose unit and to the vertical line filtering unit is able to select between lines of pixels from the first input block transpose unit and from the vertical line filtering unit and provides these to a horizontal line filtering unit (66). The first and second selectors (60), (62) receive control signals related to motion vectors in an incoming stream of data.
A method and apparatus are provided for rendering a three dimensional computer graphics image. The image is sub-divided into a plurality of rectangular areas each associated with a rectangular portion of a display. Graphics image data relating to objects to be rendered is provided and assigned to respective ones of object lists associated with each respective rectangular area. The object lists for each rectangular area are passed to a distribution means coupled to a plurality of graphics processing units. The distribution means determine which graphics processing units are able to receive data for processing and passes the object lists to individual ones of the processing units in dependence on the result of the determination.
A method and apparatus are provided for combining multiple independent tiled based graphic cores. An incoming geometry stream is split into a plurality of streams and sent to respective tile based graphics processing cores. Each one generates a separate tiled geometry lists. These may be combined into a master tiling unit or, alternatively, markers may be inserted into the tiled geometry lists which are used in the rasterisation phase to switch between tiling lists from different geometry processing cores.
The invention provides a method and apparatus for compressing and decompressing electronic image data, and in particular texture data. The compressed data comprises at least two sets of reduced size data, modulation data and modulation and discontinuity flags. The modulation and discontinuity flags determine how the modulation data is used, in combination with the reduced size data sets, in a decompression process. The invention allows for data decompression of textures including large colour discontinuities.
There are provided methods and apparatus for generating a 3-dimensional computer image. The image comprises a number of objects and is divided into separate areas. In a first aspect, control data to link to object data stored in a memory for each object is derived for two objects at a time. This improves processing and memory usage. In a second aspect, two or more separate areas can be processed in parallel by deriving control data for the two separate areas at a time. This improves processing time. To avoid fetching data for both areas, that is actually only applicable to one area, encoding is used in the control data. In a third aspect, object data can be stored on one or across two memory pages, and the control data includes one memory page address in the former case and two memory page addresses in the latter case. This improves memory usage. In a fourth aspect, object data can be stored across two non-contiguous memory pages, by using a look-up table with contiguous portions allocated for each object's object data. This also improves memory usage. In a fifth aspect, when partial rendering is used, and partial depth data is stored and subsequently updated, the depth data can be stored across two memory pages using link portions in the memory pages to either indicate the end of data storage or point to the next memory page. This also improves memory usage.
A method and apparatus are provided to enable tile based rendering systems to operate with predicated geometry whilst only making a single rasterisation pass. To do this, geometry that is to be predicated is substituted in image data with visibility test objects and associated conditional break points. In rasterisation, when a visibility test object is encountered, a visible pixel count register is updated. On completion of rasterisation of a tile, the associated conditional break points are used to test the visible pixel count register to determine if the predicated geometry should be processed and inserted into tile object lists. If it is, then a tile object list corresponding to the predicated geometry is inserted into the tile object list for the current tile and is rasterised before moving onto the next tile.
The invention provides a system and method for compressing an electronic image data set. The image is divided into a plurality of arrays, each of which are separately transformed using a wavelet transformation. The resulting wavelet coefficients are then encoded using an entropy encoding scheme to provide a compressed data set.
A multi threaded processor for executing a plurality of threads in dependence on the availability of resources that each thread requires for it to execute is disclosed. The processor comprises means for determining which thread should execute; means for switching between execution of threads in dependence on the result of the determination, each thread being coupled to a respective register means for storing the state of the thread and for use in executing instructions on the thread; further register means shared by all the threads, wherein executing threads use the further register means to improve execution performance; and means for preventing switching of execution to another thread while the internal register means is in use.
G06F 9/38 - Concurrent instruction execution, e.g. pipeline, look ahead
G06F 9/48 - Program initiating; Program switching, e.g. by interrupt
G06F 15/80 - Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
52.
CLOCK FREQUENCY ADJUSTMENT FOR SEMI-CONDUCTOR DEVICES
A method and apparatus are provided for clocking data processing modules, which require differing average clock frequencies, and for transferring data between the modules. This comprises a means for providing a common clock signal to modules. Clock pulses are deleted from the common clock signal to individual modules in dependence on the clocking frequency required by each module. Clock pulses are applied to modules between which data is to be transferred at times consistent with the data transfer.
There is provided a method and processor for processing a thread. The thread comprises a plurality of sequential instructions, the plurality of sequential instructions comprising some short-latency instructions and some long-latency instructions and at least one hazard instruction, the hazard instruction requiring one or more preceding instructions to be processed before the hazard instruction is processed. The method comprises the steps of: a) before processing each long-latency instruction, incrementing by one, a counter associated with the thread; b) after each long-latency instruction has been processed, decrementing by one, the counter associated with the thread; c) before processing each hazard instruction, checking the value of the counter associated with the thread, and i) if the counter value is zero, processing the hazard instruction, or ii) if the counter value is non-zero, pausing processing of the hazard instruction until a later time. The processor includes means for performing steps a), b) and c) of the method.
There is provided a method and receiver for optimising the processing of a received OFDM signal. The OFDM signal comprises a plurality of symbols in the time direction, each symbol comprising a plurality of sub-carriers in the frequency direction. The method comprises the steps of a) providing a plurality of techniques for channel estimation and equalization of a received OFDM signal, b) receiving one or more symbols of the OFDM signal, c) selecting one of the plurality of techniques to be used on the received one or more symbols or a further one or more symbols of the OFDM signal, d) performing channel estimation and equalization on the received one or more symbols of the OFDM signal, and e) repeating steps b) c) and d).
There is provided a method and apparatus for filtering a received OFDM signal to reduce noise. The OFDM signal comprises a plurality of symbols in the time direction, each symbol comprising a plurality of sub-carriers k in the frequency direction, each a-th sub-carrier of each symbol being transmitted as a pilot sub-carrier with known amplitude and phase, and each symbol having its pilot sub-carriers spaced by b sub-carriers relative to the adjacent symbol. The method comprises producing a filtered version of a selected pilot sub-carrier to be used in subsequent interpolation, by inputting into respective taps of an m-tap filter, m pilot sub-carriers surrounding the selected pilot sub-carrier, the m pilot sub-carriers each satisfying a relationship between n and k, the relationship defining a diagonal line in n-k plane.
A binary rotator which comprises an array of n cascaded 2-input multiplexer banks (104) and receives at an input (102) 2n-bit binary data words can be used not only for rotation but also for selective reversal, without the necessity of the addition of a further multiplexer bank dedicated to the reversal. This is achieved by making groups of multiplexers of at least all but one of the n banks of multiplexers separately controllable by words from control logic (128), rather than feeding the multiplexer banks with single control bits. The control bits are appropriately selected to provide the desired rotation-cum-reversal with just the 2n x n array of multiplexers, and can themselves be generated by appropriate logic gates (124-154).
G06F 7/76 - Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data
G06F 5/01 - Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising
57.
IMPROVEMENTS IN MEMORY MANAGEMENT FOR SYSTEMS FOR GENERATING 3-DIMENSIONAL COMPUTER IMAGES
There is provided a memory management system and method for use with systems for generating 3-dimensional computer generated images. The method comprises the steps of: subdividing the image into a plurality of rectangular areas; providing a memory having, at any one time, a first portion or portions for storing object data for each rectangular area and a second portion or portions for storing depth data derived from the object data; storing the object data in the first portion or portions of the memory; deriving the depth data for each rectangular area, from the object data; storing the depth data for each rectangular area in the second portion or portions of memory; loading further object data into one or more of the first portion or portions of the memory to replace at least part of the existing contents; retrieving the stored depth data; deriving updated depth data for each picture element of each rectangular area from the new object data and the stored data, and storing the updated depth data to replace the previously stored depth data; repeating the previous four steps until there is no further object data to load into the memory; and deriving image data and shading data from the depth data, for display.
Method and apparatus are provided for a synchronising execution of a plurality of threads on a multi-threaded processor. Each thread is provided with a number of synchronisation points corresponding to points where it is advantageous or preferable that execution should be synchronised with another thread. Execution of a thread is paused when it reaches a synchronisation point until at least one other thread with which it is intended to be synchronised reaches a corresponding synchronisation point. Execution is subsequently resumed. Where an executing thread branches over a section of code which included a synchronisation point then execution is paused at the end of the branch until the at least one other thread reaches the synchronisation point of the end of the corresponding branch.
A method and apparatus for managing memory usage for three-dimensional computer graphics systems are provided. A scene which is textured and shaded in the system is divided into a plurality of rectangular areas, each comprising a plurality of picture elements in the scene. For each rectangular area a list of objects which may be visible in the scene is derived. Objects which do not contribute to the final textured and shaded scene are then removed from each list and the rectangular area is then textured and shaded using reduced lists of objects.
A method for selectively storing information received from a broadcast signal is disclosed. The method comprises the steps of; receiving and identifying a broadcast message, the message comprising a plurality of characters; comparing each character of the received message with a start of tag (SOT) identifier stored in a memory; if a character received in the received message is determined to match the SOT identifier stored in the memory then comparing each of the subsequent characters in the received message with an end of tag (EOT) identifier stored in the memory determining if the received message contains both SOT and EOT identifiers; and storing the message in a storage unit in dependence on the result of the determination.
An apparatus (40) for determining motion between a first and second video image comprising means for receiving a first video image comprising a plurality of pixels, means for selecting a block of pixels within the first video image (48), means for receiving a second video image comprising a plurality of pixels, means for selecting at least part of the second video image to produce a search area (47), means for sampling the pixels of the search area in a predetermined pattern and means for comparing the selected block of pixels within the first video image with at least one block of the sampled pixels of the search area to determine the motion of the block of pixels between the images (44) wherein the pattern of sampled pixels varies throughout the search area.
A method and apparatus are provided for selecting between a plurality of instruction sets available to a microprocessor. An instruction fetch address is supplied. At least one predetermined bit of the instruction fetch address is used to select between the instruction sets. Once an instruction set has been selected instructions may be fetched and decoded with a decoding scheme appropriate to the instruction set.
Incoming decoded data (1), for example from an H264 decoder, is fed to an encoder unit (2) that entropy encodes the decoded data using a parallel encoding scheme that includes context based arithmetic encoding. The syntax is chosen so that the context does not depend on the immediately previously encoded symbol. The output of the encoder (2) is fed to a FIFO memory whose output is fed to a complementary decoder (4) whose output produces a delayed copy of the incoming decoded data (1).
A method and apparatus are provided for estimating motion in a sequence of video images. A plurality of fields of a sequence of video images are stored; then for each of a plurality of blocks of pixels in each field a test is performed on a set of candidate motion vectors to determinate which motion vector gives the best benefit in determining the motion between adjacent fields for that block. The testing step includes determining the amount of motion blur present in the image and modifying the testing of candidate motion vectors in dependence on this motion blur.
A method and apparatus are provided for improving the quality of a computer generated image which includes a number of different objects. For each pixel in the image a flag is generated in dependence on the objects rendered at that pixel and on the filtering required by that pixel. This flag is stored in flag store. The flag can subsequently be retrieved and using the selection of a filter to apply to one or more pixels to generate an output pixel. The selected filter is then applied to the pixel and the pixel supplied for display.
A method and apparatus are provided for processing multiple streams of data on a plurality of execution threads. Data is selected from a plurality of data sources (1001 ). An address in the data storage means (1036) is allocated for the data thus selected. The selected data is then loaded into the allocated address. Following this an execution task comprising the selected data source, the data address and an execution address is constructed and the data task is queued with previously constructed tasks. A determination is made as to which processing resources are required for each task and tasks are selected for execution in dependence on this. Tasks selected for execution are distributed across a plurality of processing threads (170). The allocation of data storage in the data storage means includes the steps of selecting data from one of the data sources and supplying a code execution address to a programmable data sequencer (1004). The code from the code execution address is executed to cause data to be written to the data storage means. Furthermore, a tile based computer graphic rendering system may comprise a plurality of mulit-threaded processor cores. Each processor core is allocated to different sectors of the tile.
A method for enhancing an edge transition in a video signal comprising the steps of receiving a video signal including an edge transition, generating a correction signal for the edge transition, applying the correction signal to the video signal to produce a corrected signal and restricting the amplitude of the corrected signal to extend between extended maximum and minimum amplitude limits in dependence on the measured maximum and minimum amplitudes of a predefined pattern of pixels adjacent to the edge transition.
A method and apparatus are provided for converting an interlaced video signal to a progressive scan video signal. For each pixel in each missing line of a video field in a video signal to be converted correlation data is provided for each of a set of possible interpolations between adjacent pixels to be used in the constructing missing pixel. A confidence measure is derived in dependence on the number of maxima and minima in the correlation data. The confidence measure most likely to produce an accurate missing pixel is then determined from the confidence measure and a missing pixel interpolator.
A method and apparatus are provided for converting an interlaced video signal to a progressive scan video signal. For each pixel in each missing line of a video field in a video signal to be converted correlation data is derived for each of a set of possible interpolations between adjacent pixels to be used in reconstructing the missing pixel. A confidence measure is then derived from the correlation data. Adjustment data dependent on the thus derived confidence measure is then selected and used to adjust the correlation data. The thus adjusted correlation data is then used to determine the interpolation scheme most likely to produce an accurate missing pixel and the missing pixel then interpolated.
A method and apparatus are provided for converting an interlaced video signal to a non-interlaced video signal. For each pixel in each missing line of a video field in a video signal, correlation data is derived for each of the set of possible interpolations to be used in reconstructing the pixel in the missing line. A correlation corresponding to the interpolation scheme likely to give the best results for the missing pixel is selected and an interpolation scheme selected in dependence on this. The pixel in the missing line is then interpolated. The correlation data used in the selection of interpolation schemes is derived from data in the same field as the pixel to be reconstructed and from temporally spaced fields.
A method and apparatus are provided for removing regularly occurring visible artefacts in decompressed video images. Firstly a decompressed video signal is received. This is filtered frame by frame to extract data related to the artefacts. The thus extracted data is then processed in a neutral network processor which has been trained to identify the artefacts in order to produce data identifying their locations. The video signal is then corrected to reduce the effect of the thus identified artefacts.
A memory controller maps a processor generated address to a banked DRAM address by applying a randomising function which results in the banks appearing in an irregular and non-cyclic order in the conceptual memory map. Incremental addressing by two or more requestors is thereby more evenly distributed amongst the banks of DRAM to improve average access speed.
A system and method for managing accesses to a memory are provided. A memory management unit (MMU) and a translation lookaside buffer (TLB) are used. The TLB stores addresses of pages which have been recently accessed. The MMU includes a virtual map of an MMU table which stores physical addresses of memory pages linked to logical addresses. A virtual map is stored in a linear address space and the MMU can update the addresses stored in the TLB in response to memory accesses made in the MMU table. The MMU table comprises at least first and second level table entries. The first level table entries store data for map logical addresses to the second level table entries. The second level table entries store data for map logical addresses to physical addresses in memory.
A method and apparatus are provided for controlling instructions provided by a microprocessor output port to other execution units. A microprocessor pipeline of instructions is provided for each execution unit. These are scheduled via the microprocessor unit. For each execution unit, a determination is made as to whether or not the execution unit can receive further instructions. If it cannot, it's associated pipeline is said to be stalled and instructions are deleted from the microprocessor pipeline. Its thread can then be restarted at a later time with the instruction corresponding to the instruction which was unable to execute.
An apparatus for evaluating a mathematical function at an input value comprising, means for selecting a mathematical function, means for inputting a value at which to evaluate the function, means for identifying an interval containing the input value, the interval being described by at least one polynomial function, means for retrieving at least one control point representing the polynomial function from at least one look up table, means for deriving the polynomial function from the control points, means for evaluating the function for the input value and means for providing data representing the evaluated function at an output.
A method and system for adjusting the audio volume of an electronic device such as a digital audio broadcast radio receiver is described. The gain of an amplifier is adjusted according to additional data received with the signal, preferably a radio signal, so that the output volume level of a channel can be automatically adjusted.
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