Embodiments of part coating reactors are provided herein, In some embodiments, a part coating reactor includes a lid assembly, comprising: a body that includes a central region and a peripheral region, wherein the body includes a central opening in the central region, a first annular heater groove disposed radially outward of the central opening, and a second annular heater groove disposed radially outward of the first annular heater groove, wherein the peripheral region includes a plurality of vertical slots that extend from an upper surface of the body, and wherein a lower surface of the body includes an annular alignment groove; and a blocker plate including a substantially flat plate having a plurality of holes disposed therethrough and an annular wall extending above and below the flat plate, wherein an upper surface of the annular wall is disposed in the annular alignment groove of the body.
C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
2.
LIGHT EMITTING DIODE WITH INCREASED LIGHT CONVERSION EFFICIENCY
Embodiments of the present technology include pixel structures. The pixel structures include a light emitting diode structure to generate ultraviolet light. The pixel structures further include a photoluminescent region containing a photoluminescent material. The pixel structures additionally include a first bandpass filter positioned between the light emitting diode structure and the photoluminescent region, where the first bandpass filter is operable to transmit greater than 50% of light having a wavelength less than or about 400 nm. The pixel structures yet additionally include a second bandpass filter positioned on an opposite side of the photoluminescent region as the first bandpass filter, where the second bandpass filter is operable to transmit greater than 50% of light having a wavelength greater than 400 nm.
H01L 27/15 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier, specially adapted for light emission
H01L 25/075 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
3.
UNIFORM EPITAXIAL GROWTH OVER CRYSTALLINE TEMPLATE
A processing system includes one or more processing chambers, and a system controller configured to cause the processing system to perform (a) a pre-clean process on exposed surfaces of a semiconductor structure, the semiconductor structure comprising a first semiconductor region, a second semiconductor region separated from the first semiconductor region by a trench, and a dielectric layer over at least a portion of the first semiconductor region and the second semiconductor region, (b) a first deposition process to form an amorphous silicon-containing layer on the exposed surfaces of the semiconductor structure, (c) a recrystallization anneal process to recrystallize at least a portion of the amorphous silicon-containing layer to form a silicon- containing crystalline layer within the trench, (d) an etch process to remove remaining portions of the amorphous silicon-containing layer, and (e) a second deposition process, to epitaxially form a source/drain region over the silicon- containing crystalline layer within the trench.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
Processing methods are described that include forming a group of LED structures on a substrate layer to form a patterned LED substrate. The methods also include depositing a light absorption material on the pattered LED substrate, where the light absorption material includes at least one photocurable compound and at least one ultraviolet light absorbing material. The methods further include exposing a portion of the light absorption material to patterned light, wherein the patterned light cures the exposed portion of the light absorption material into pixel isolation structures. The methods additionally include depositing an isotropic layer on a top portion and a side portion of the pixel isolation structures, where the LED structures are substantially free of the as-deposited isotropic light reflecting layer.
H01L 27/15 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier, specially adapted for light emission
Measurement systems and methods of optical device metrology as described herein. In an example, a method includes projecting a light beam of a first intensity to a lens coupler disposed on a first surface of an optical device substrate, the lens coupler in-coupling the light beam into the optical device substrate to undergo total internal refraction. The optical device substrate includes a grating having a plurality of grating lines such that light is out-coupled by the grating at a plurality of contact points. A plurality of intensities of the light beam out-coupled by the grating at the plurality of contact points are measured using a receiver and a total optical loss of the optical device substrate and the grating are determined by comparing the plurality of intensities at the contact points and the first intensity of the light beam.
A workpiece mounting system comprising a chuck and a base is disclosed. The emissivity of the base is increased to allow more heat transfer from the chuck to the base. In some embodiments, the emissivity of the base may be controllable so that for ion beams with lower power levels, the emissivity remains low, enabling the chuck to reach the desired temperature quickly. For ion beams with higher power levels, the emissivity may increase to allow more heat transfer to the base, allowing the chuck to maintain the desired temperature. High emissivity coatings may be applied to the top surface of the base. In other embodiments, a set of movable shields may be disposed between the chuck and the base. The position of the shields may be a function of the power level of the incoming ion beam.
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
7.
METHODS FOR FORMING METAL GAPFILL WITH LOW RESISTIVITY
Methods for reducing resistivity of metal gapfill include depositing a conformal layer in an opening of a feature and on a field of a substrate with a first thickness of the conformal layer of approximately 10 microns or less, depositing a non-conformal metal layer directly on the conformal layer at a bottom of the opening and directly on the field using an anisotropic deposition process. A second thickness of the non- conformal metal layer on the field and on the bottom of the feature is approximately 30 microns or greater. And depositing a metal gapfill material in the opening of the feature and on the field where the metal gapfill material completely fills the opening without any voids.
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
C23C 16/02 - Pretreatment of the material to be coated
C23C 16/04 - Coating on selected surface areas, e.g. using masks
C23C 16/06 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the deposition of metallic material
8.
OPTIMIZED SADDLE NOZZLE DESIGN FOR GAS INJECTION SYSTEM
A gas injection nozzle that includes an elongated gas conduit that comprises: a first gas conduit segment configured to be coupled with a gas reservoir; a second gas conduit segment fluidly coupled to the first gas conduit segment and defining a downward curve of the elongated, gas conduit; a third gas conduit segment defining an upward curve of the elongated gas conduit that extends to a sealed end and is disposed in a mirrored relationship with at least a portion of the second gas conduit; and a central gas conduit segment coupled, between the second and third gas conduit, segments, the central gas conduit, segment having a first aperture formed in an upper surface of the central gas conduit and a second aperture, larger than the first aperture, formed in a lower surface of the central gas conduit directly across from the first aperture, wherein the elongated gas conduit has a first diameter along a portion of its length that includes at least the second, third, and central gas conduit segments and wherein the central gas conduit segment includes a substantially horizontal portion that extends on each side of the first and second apertures for a distance that is at least twice the first diameter of the gas conduit.
Methods and apparatus for cleaning tooling parts in a substrate processing tool are provided herein. In some embodiments, a method of cleaning tooling parts in a substrate processing tool includes placing one or more dirty tools on a holder in a bonding chamber of a multi-chamber processing tool; transferring the holder from the bonding chamber to a cleaning chamber of the multi-chamber processing tool; cleaning the one or more dirty tools in the cleaning chamber to produce one or more cleaned tools; inspecting the one or more cleaned tools in an inspection chamber of the multi-chamber processing tool; and transferring the one or more cleaned tools to the bonding chamber
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
H01L 21/52 - Mounting semiconductor bodies in containers
H01L 21/677 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for conveying, e.g. between different work stations
A semiconductor processing method may include providing a fluorine-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region. The substrate may include an exposed region of silicon-and-oxygen-containing material. The substrate may include an exposed region of a liner material. The methods may include providing a hydrogen-containing precursor to the semiconductor processing region. The methods may include contacting the substrate with the fluorine-containing precursor and the hydrogen-containing precursor. The methods may include selectively removing at least a portion of the exposed silicon-and-oxygen-containing material.
Embodiments disclosed herein include a semiconductor processing tool. In an embodiment, the semiconductor processing tool comprises a chamber, a pedestal in the chamber, and a first gas feed system on a first side of the pedestal. In an embodiment, the first gas feed system comprises a first exhaust line with a first valve to open and close the first exhaust line, and a first source gas feed line with a second valve to open and close the first source gas feed line. In an embodiment, the semiconductor processing tool further comprises a second gas feed system on a second side of the pedestal. In an embodiment, the second gas feed system comprises a second exhaust line with a third valve to open and close the second exhaust line, and a second source gas feed line with a fourth valve to open and close the second source gas feed line.
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating
C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
C23C 16/509 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating using electric discharges using radio frequency discharges using internal electrodes
C23C 16/04 - Coating on selected surface areas, e.g. using masks
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
12.
GENERATION AND UTILIZATION OF VIRTUAL FEATURES FOR PROCESS MODELING
A method includes receiving profile data of a plurality of features of a substrate. The method further includes generating a typical profile based on the profile data of the plurality of features. The method further includes generating a first array of features. Each of the first array of features is based on the typical profile. The method further includes providing the first array of features to a process model. The method further includes obtaining first output from the process model based on the first array of features. The method further includes causing performance of a corrective action in view of the first output from the process model.
G05B 19/418 - Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control (DNC), flexible manufacturing systems (FMS), integrated manufacturing systems (IMS), computer integrated manufacturing (CIM)
G05B 13/04 - Adaptive control systems, i.e. systems automatically adjusting themselves to have a performance which is optimum according to some preassigned criterion electric involving the use of models or simulators
C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
A61M 5/24 - Ampoule syringes, i.e. syringes with needle for use in combination with replaceable ampoules or cartridges, e.g. automatic
A61J 1/14 - Containers specially adapted for medical or pharmaceutical purposes - Details; Accessories therefor
Embodiments disclosed herein include an impedance matching network. In an embodiment, the impedance matching network comprises an input, and a first matrix tuning element on a first branch from the input, where the first matrix tuning element comprises a variable capacitance. In an embodiment, the impedance matching network further comprises a transformer on a second branch from the input, where the transformer has at least a first tap, where a second matrix tuning element is on the first tap, and where the second matrix tuning element comprises a variable capacitance. In an embodiment, the impedance matching network further comprises a third matrix tuning element after the transformer on the second branch, where the third matrix tuning element comprises a variable capacitance. In an embodiment, the impedance matching network further comprises an output after the third matrix tuning element on the second branch.
A reflector plate assembly for processing a substrate includes a reflector plate having a first surface, wherein the first surface is a bare polished surface, a reflector disk embedded within the reflector plate from the first surface, a coating layer on the reflector disk, and a pyrometer disposed through an opening of the reflector disk.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
16.
METHODS AND APPARATUS FOR TOROIDAL PLASMA GENERATION
Methods and apparatus for forming plasma in a process chamber use an annular exciter formed of a first conductive material with a first end electrically connected to an RF power source that provides RF current and a second end connected to a ground and an annular applicator, physically separated from the annular exciter, formed of a second conductive material with at least one angular split with an angle forming an upper overlap portion and a lower overlap portion separated by a high K dielectric material which is configured to provide capacitance in conjunction with an inductance of the annular applicator to form a resonant circuit that is configured to resonate when the annular exciter flows RF current that inductively excites the annular applicator to a resonant frequency which forms azimuthal plasma from the annular applicator.
A method and apparatus for forming tungsten features in semiconductor devices is provided. The method includes exposing a top opening of a feature formed in a substrate to a physical vapor deposition (PVD) process to deposit a tungsten liner layer within the feature. The PVD process is performed in a first processing region of a first processing chamber and the tungsten liner layer forms an overhang portion, which partially obstructs the top opening of the feature. The substrate is transferred from the first processing region of the first processing chamber to a second processing region of a second processing chamber without breaking vacuum. The overhang portion is exposed to nitrogen-containing radicals in the second processing region to inhibit subsequent growth of tungsten along the overhang portion. The feature is exposed to a tungsten-containing precursor gas to form a tungsten fill layer over the tungsten liner layer within the feature.
C23C 16/04 - Coating on selected surface areas, e.g. using masks
C23C 16/08 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the deposition of metallic material from metal halides
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
C23C 28/00 - Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of main groups , or by combinations of methods provided for in subclasses and
A method and apparatus for performing post-exposure bake operations is described herein. After exposure of photoresist on a substrate, the substrate is heated during a baking process to facilitate protection of the resist. The baking process is performed in a vacuum environment at sub-atmospheric pressures. After baking at reduced pressure, the substrate is cooled. The cooling process is performed at sub- atmospheric pressures. Further development of the resist is performed at ambient pressures.
H01L 21/027 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
20.
SCANNING IMPEDANCE MEASUREMENT IN A RADIO FREQUENCY PLASMA POCESSING CHAMBER
Embodiments include a method of processing a substrate in a plasma processing system, comprising delivering an RF signal, by an RF generator, through an RF match to an electrode assembly while the RF match is set to a first matching point, and delivering a voltage waveform, by a waveform generator, to the electrode assembly while the RF signal is delivered to the electrode assembly. The method includes receiving, by the RF match, a synchronization signal from a RF generator or the waveform generator, measuring, by an output sensor of the RF match, different sets of impedance related data of the plasma processing system over different time periods and after different delays, calculating, by the RF match, a combined impedance parameter based on the different_sets of impedance related data, and adjusting a matching parameter within the RF match based on the combined impedance parameter to achieve a second matching point.
A method of forming a semiconductor memory device includes simultaneously filling a top portion of a first high aspect ratio (HAR) structure and a top portion a second HAR structure with a silicon-containing sacrificial layer by a cycle of a deposition process and an etch process, wherein the first HAR structure has a critical dimension (CD) of between 150 nm and 250 nm, and the second HAR structure has a CD of between 250 nm and 400 nm.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H01L 21/3205 - Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layers; After-treatment of these layers
H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
22.
SYMMETRIC ANTENNA ARRAYS FOR HIGH DENSITY PLASMA ENHANCED PROCESS CHAMBER
The present disclosure is directed to an antenna array. The antenna array includes a plurality of dielectric windows coupled to a support structure comprising a plurality of gas ports, a primary frame comprising a primary conduit connected to a power source and a plurality of secondary frames supported by the primary frame. The secondary frame includes a secondary conduit connected to the primary conduit. A plurality of inductive couplers are disposed over the plurality of dielectric windows and supported by the secondary frames. The plurality of inductive couplers include a plurality of antenna connectors and a plurality of plurality of antennas. The plurality of antenna connectors connect the plurality of antennas to the secondary conduit.
A method includes identifying an image of a substrate processing equipment part that forms a plurality of holes. The method further includes determining, by a processing device based on the image, a corresponding neighboring angular distance of each of the plurality of holes and a corresponding area of each of the plurality of holes. The method further includes identifying, by the processing device, a first subset of the plurality of holes that are at least partially clogged based on at least one of the corresponding neighboring angular distance or the corresponding area of each of the plurality of holes. A corrective action associated with the substrate processing equipment part is to be performed based on the first subset of the plurality of holes that are at least partially clogged.
Methods leverage premixed gas mixtures to perform a metrology process on a substrate using an inline secondary ion mass spectrometry (SIMS) process. The premixed gas mixture of two or more gases is injected into a plasma chamber that is configured to produce sputtering ions for the inline SIMS process. The two or more gases produce non-metallic ion species which are compatible with downstream substrate fabrication processes and allow further fabrication to be performed on the substrate after the inline SIMS process has completed. The sputtering ions are ejected from the plasma chamber into a magnetic field. The intensity of the magnetic field is altered to select a single species of ions. The single species of ions are directed towards a surface of the substrate and secondary ions sputtered from the surface of the substrate by the selected species of ions are detected and analyzed.
Exemplary semiconductor processing methods may include providing one or more deposition precursors to a processing region of a semiconductor processing chamber. The methods may include contacting a substrate housed in the processing region with the one or more deposition precursors. The methods may include forming a silicon-containing material on the substrate. The methods may include providing a fluorine-containing precursor to the processing region of the semiconductor processing chamber. The methods may include contacting the silicon-containing material on the substrate with the fluorine-containing precursor to form a fluorine-treated silicon-containing material. The methods may include contacting the fluorine-treated silicon-containing material with plasma effluents of argon or diatomic nitrogen.
A system and method for creating a beam current profile that eliminates variations that are not position dependent is disclosed. The system includes two Faraday sensors; one which is moved across the ion beam and a second that remains at or near a certain location. The reference Faraday sensor is used to measure temporal variations in the beam current, while the movable Faraday sensor measures both the position dependent variations and the temporal variations. By combining these measurements, the actual position dependent variations of the scanned ion beam can be determined. This resultant beam current profile can then be used to control the scan speed of the electrostatic or magnetic scanner.
H01J 37/317 - Electron-beam or ion-beam tubes for localised treatment of objects for changing properties of the objects or for applying thin layers thereon, e.g. ion implantation
Embodiments of the disclosure include an apparatus and method of forming an improved memory device. In some embodiments, the apparatus generally includes, for example, a plurality of alternating layers formed over a surface of a substrate including a plurality of word line layers with gate regions and a plurality of inter-word line dielectric layers; a channel; and an ONO layer stack disposed between the gate regions and the channel. The embodiments of the present disclosure may include at least one of: word line layers with gate regions that have sidewalls that have a reverse dome shape, sacrificial layers disposed between the word line layers and the inter-word line dielectric layers, or top and bottom dielectric layers deposited on top and bottom portions of the word line layers. Embodiments of the disclosure described herein may allow for the electric field of the gate regions of a memory device to be modified.
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/50 - EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
Methods for DRAM device with a buried word line are described. The method includes forming a metal nitride layer comprising lanthanum nitride (LaN) and a molybdenum conductor layer in a feature on a substrate. The method includes depositing the molybdenum conductor layer by atomic layer deposition (ALD) on the metal nitride layer.
Methods for forming a semiconductor structure and semiconductor structures are described. Some embodiments of the method comprise patterning a substrate to form a first opening and a second opening, the substrate comprising an n transistor and a p transistor, the first opening over the n transistor and the second opening over the p transistor. The substrate is pre-cleaned. A molybdenum film is selectively deposited on the p transistor.
C23C 16/04 - Coating on selected surface areas, e.g. using masks
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
30.
GAS DISTRIBUTION APPARATUSES FOR IMPROVING MIXING UNIFORMITY
Gas distribution apparatuses described herein include a mixing plate adjacent a back plate of a showerhead. The mixing plate has a back surface and a front surface defining a thickness of the mixing plate. The mixing plate has a mixing channel comprising a top portion and a bottom portion defining a mixing channel length and at least two gas inlets in fluid communication with the top portion of the mixing channel. The gas distribution apparatus also includes a mixer disposed within the thickness of the mixing plate in the top portion of the mixing channel. The mixer has a top plate and a mixer stem extending from the top plate and a plurality of blades positioned along the mixer stem length. Also provided are processing chambers including the gas distribution apparatuses described herein.
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
A method for forming alignment marks leverages pad density and critical dimensions (CDs). In some embodiments, the method includes forming first and second alignment marks on a first substrate and a second substrate where the alignment marks have a width within 5% of the associated CD of copper pads on the respective substrates and forming a first and second dummy patterns around the first and second alignment marks. The first and second dummy patterns have dummy pattern densities within 5% of the respective copper pad density of the first and second substrates and CDs within 5% of the respective copper pad CDs. In some embodiments, alignment marks with physical dielectric material protrusions and recesses on opposite substrate surfaces may further enhance bonding.
H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
Target assemblies for PVD chambers are provided herein. In some embodiments, a target assembly for a PVD chamber includes: a backing plate; and a target coupled to the backing plate and having a substrate facing surface opposite the backing plate, wherein a peripheral portion of the target includes an angled surface extending radially outward and toward the backing plate, wherein an annular portion of the angled surface has a surface roughness greater than a surface roughness of a remainder of the substrate facing surface of the target.
The present disclosure generally relates to methods and system used to collect waste fluids. A system controller is disclosed to control the operation of at least a portion of the system. The controller has a CPU. The fabrication facility includes a first processing system having fluid dispensed therein for processing a material on a part. A first drain is configured to collect the processing fluid as waste fluid after processing the part. The fabrication facility also includes a waste collection system fluidly coupled to the system drain. The waste collection system has two or more valves configured to couple the system drain and two or more facility drains. Each facility drain is uniquely coupled to one of the two or more valves. The CPU is configured to operate the valves between an open and a closed state in response to the fluid entering the system drain.
B24B 55/12 - Devices for exhausting mist of oil or coolant; Devices for collecting or recovering materials resulting from grinding or polishing, e.g. of precious metals, precious stones, diamonds or the like
B24B 55/03 - Equipment for cooling the grinding surfaces, e.g. devices for feeding coolant designed as a complete equipment for feeding or clarifying coolant
B24B 37/005 - Control means for lapping machines or devices
In some embodiments, a showerhead assembly includes a heated showerhead having a heater plate and a gas distribution plate coupled together; an ion filter spaced from the heated showerhead; a spacer ring in contact between the heated showerhead and the ion filter; a remote plasma region between the heated showerhead and the ion filter; an upper isolator spaced from the spacer ring and supported on the ion filter; a sealing ring fastened to the heated showerhead sealing against the upper isolator and pushing the upper isolator against the ion filter; a gap between a bottom of the gas distribution plate and a top of the ion filter, the gap being in fluid communication with the remote plasma region; a first passage extending through the heater plate; and a second passage in communication with the first passage and extending through the gas distribution plate, the second passage extending to the gap.
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
C23C 16/50 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating using electric discharges
The present disclosure is directed towards polishing modules for performing chemical mechanical polishing of a substrate. The substrate may be a semiconductor substrate. The polishing modules described have a plurality of pads, such as polishing pads, disposed within a single polishing station. The pads are configured to remain stationary during processing, such as during polishing or buff operations. Either an x-y gantry assembly or a head actuation assembly is coupled to a system body of a polishing module and is configured to move a carrier head over the pads. Between process operations the polishing pads may be indexed to expose a new polishing pad to the carrier head.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
36.
RETAINER FOR CHEMICAL MECHANICAL POLISHING CARRIER HEAD
A retaining ring for a carrier head of a chemical mechanical polishing system includes an annular outer portion having an annular outer surface and a plurality of flanges projecting radially inward from the annular outer portion. Adjacent flanges are separated by a gap and inner ends of the plurality of flanges provide an inner surface to contact a substrate held in the carrier head. The plurality of flanges are canted relative to radial direction.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
37.
SYSTEM AND METHOD FOR CONTROLLING FORELINE PRESSURE
A system and method for controlling pressure in a foreline of a processing system are disclosed herein that reduce variation in foreline pressure. In one example, a processing system is provided that includes a first process chamber, a first pump, a foreline, and a first foreline pressure control system. The first pump has an inlet and an outlet. The inlet of the first pump coupled to an exhaust port of the first process chamber. The foreline is coupled to the outlet of the first pump. The first foreline pressure control system is fluidly coupled to the foreline downstream of the first pump. The first foreline pressure control system is operable to control a pressure in the foreline independent from operation of the first pump.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating
C23C 16/52 - Controlling or regulating the coating process
38.
EQUIPMENT PARAMETER MANAGEMENT AT A MANUFACTURING SYSTEM USING MACHINE LEARNING
A method includes receiving first data associated with an equipment parameter. The first data is indicative of an equipment setting of a process tool of a plurality of process tools at a first manufacturing system. The method further includes providing the first data as input to a trained machine learning model. The trained machine learning model is trained using historical data pertaining to equipment parameters of the plurality of process tools at the first manufacturing system. The method further includes obtaining, as output of the trained machine learning model, a predicted value of a metric corresponding to the equipment parameter. The method further includes comparing the predicted value of the metric with the first data, and performing a corrective action based on the comparing.
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
Embodiment of the present disclosure generally relate to optical device structures and methods for forming a metal containing interconnection structure in a high aspect ratio gap on a substrate for an optical device. In one embodiment, the method includes providing a substrate having a gap in a material layer disposed on a substrate, depositing a gap fill material in an opening of the gap, etching the gap fill material to remove portions of the gap fill material deposited in the gap, and cyclically depositing more of the gap fill material in the opening of the gap to completely fill the gap.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
41.
PAD SURFACE CLEANING DEVICE AROUND PAD CONDITIONER TO ENABLE INSITU PAD CONDITIONING
The present disclosure relates to a pad surface cleaning system to be used with a conditioning module to condition a polishing surface of a polishing pad The pad surface cleaning system may be used to spray the polishing surface with a high- pressure fluid spray to loosen debris from the polishing surface. The pad surface cleaning system may also be used to remove the loosened debris. Further, the pad surface cleaning system may isolate a conditioning disk from a polishing fluid to protect the conditioning disk from reacting with the polishing fluid.
A method and system for including a microwave anneal combined with a nanosecond laser pulse are provided. The method may include applying continuous electromagnetic energy from a first electromagnetic energy source to a substrate, wherein the substrate has a major surface. The method may further include exposing the substrate to laser pulses from a second electromagnetic energy source while applying the continuous electromagnetic energy, wherein exposing the substrate to each pulse of the laser pulses occurs in phase with the continuous electromagnetic energy.
H01L 21/268 - Bombardment with wave or particle radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
43.
SUBSTRATE PLACEMENT OPTIMIZATION USING SUBSTRATE MEASUREMENTS
A computer readable medium includes instructions that, when executed by a processing device, cause the processing device to perform operations. Operations include processing a first substrate in a process chamber while the first substrate is supported by a substrate support at a first placement location. The first substrate includes a first surface profile after processing. Operations further include generating a first surface profile map of the first surface profile using a substrate measurement system. Operations further include determining a plurality of etch rates corresponding to a plurality of locations on the first substrate. Operations further include processing data associated with the plurality of etch rates using a model that is to output one or more estimated surface profiles associated with one or more estimated placement locations. Operations further include determining a recommended placement for substrates on the substrate support based on the one or more estimated placement locations.
H01L 21/68 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for positioning, orientation or alignment
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 21/677 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for conveying, e.g. between different work stations
Embodiments of radio frequency (RF) power connection rods are provided herein. In some embodiments, an RF power connection rod includes a first connection rod having a first connection end, a first socket end opposite the first connection end, and a first hollow portion extending from the first connection end to the first socket end; a second connection rod having a second connection end, a second socket end opposite the second connection end, and a second hollow portion extending from the second connection end to the second socket end, wherein the second connection end is adjustably coupled to the first connection end along an axial direction of the second connection rod, and wherein a gas flow path extends from one or more gas inlets of the first connection rod, through the first hollow portion to the second hollow portion, to one or more gas outlets disposed through the second connection rod; a first plug coupled to the first socket end; and a second plug coupled to the second socket end.
The present disclosure is directed to a stage for supporting a substrate. The stage includes a rotating base having a top surface with a rotating base flatness of 1 nm or less, a motor, a screw disposed on the rotating base, a nut threadably connected to the screw, one or more stabilization arms, and a substrate support disposed on the nut. The rotating base flatness of the top surface of the rotating base is a difference between a maximum point and a minimum point on the top surface of the rotating base. The screw has a bottom surface with a screw flatness of 1 nm or less. The flatness of the screw is the difference between a maximum point and a minimum point on the bottom surface of the screw. The motor rotates the rotating base and the screw.
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
46.
IN-CHAMBER METROLOGY OF SUBSTRATES FOR PROCESS CHARACTERIZATION AND IMPROVEMENT
A method includes receiving, by a processing device, first data generated by a first sensor of a substrate processing system. The first data is generated responsive to the first sensor receiving electromagnetic radiation from a substrate held by a robot arm of a transfer chamber in the substrate processing system. The method further includes processing the first data to obtain second data. The second data includes a first indication of performance of the substrate processing system. The method further includes causing, in view of the second data, performance of a corrective actions associated with the substrate processing system.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 21/677 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for conveying, e.g. between different work stations
H01L 21/68 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for positioning, orientation or alignment
A robot apparatus with variable end effector pitch is provided suitable for accommodating varying pitches, e.g., between two adjacent processing chambers or between two adjacent load lock chambers. The robot apparatus may operate in dual substrate handling mode, single substrate handling mode, or a combination thereof. The robot apparatus may also be an off-axis robot. A variety of robot apparatuses according to various embodiments, electronic device processing systems including such robot apparatuses, and methods of use thereof are described.
B25J 9/04 - Programme-controlled manipulators characterised by movement of the arms, e.g. cartesian co-ordinate type by rotating at least one arm, excluding the head movement itself, e.g. cylindrical co-ordinate type or polar co-ordinate type
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
H01L 21/677 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for conveying, e.g. between different work stations
48.
ION IMPLANTATION FOR INCREASED ADHESION WITH RESIST MATERIAL
Exemplary methods of semiconductor processing may include forming a layer of silicon-containing material on a semiconductor substrate. The methods may include performing a post-formation treatment on the layer of silicon-containing material to yield a treated layer of silicon-containing material. The methods may include contacting the treated layer of silicon-containing material with an adhesion agent. The methods may include forming a layer of a resist material on the treated layer of silicon-containing material.
H01L 21/027 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or
H01L 21/033 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or comprising inorganic layers
G03F 7/09 - Photosensitive materials - characterised by structural details, e.g. supports, auxiliary layers
G03F 7/11 - Photosensitive materials - characterised by structural details, e.g. supports, auxiliary layers having cover layers or intermediate layers, e.g. subbing layers
49.
ADHESION IMPROVEMENT BETWEEN LOW-K MATERIALS AND CAP LAYERS
Exemplary semiconductor processing methods may include providing one or more deposition precursors to a processing region of a semiconductor processing chamber. A semiconductor substrate may be positioned within the processing region. The methods may include forming a layer of low dielectric constant material on the semiconductor substrate. The methods may include purging the processing region of the one or more deposition precursors. A plasma power may be maintained at less than or about 750 W while purging the processing region. The methods may include forming an interface layer on the layer of low dielectric constant material. The methods may include forming a cap layer on the interface layer.
Embodiments include semiconductor processing methods to form low-κ films on semiconductor substrates are described. The processing methods may include flowing one or more deposition precursors to a semiconductor processing system. The one or more deposition precursors may include a silicon-containing precursor that may be a cyclic compound. The methods may include generating a deposition plasma from the one or more deposition precursors. The methods may include depositing a silicon-and-carbon-containing material on the substrate from plasma effluents of the deposition plasma. The silicon-and-carbon-containing material as-deposited may be characterized by a dielectric constant less than or about 3.0.
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
Embodiments include semiconductor processing methods to form low-κ films on semiconductor substrates are described. The processing methods may include flowing one or more deposition precursors to a semiconductor processing system, wherein the one or more deposition precursors include a silicon-containing precursor. The silicon-containing precursor may include a carbon chain. The methods may include generating a deposition plasma from the one or more deposition precursors. The methods may include depositing a silicon-and-carbon-containing material on the substrate from plasma effluents of the deposition plasma. The silicon-and-carbon-containing material as-deposited may be characterized by a dielectric constant less than or about 3.0.
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
A method for defect classification is described. The method includes storing a plurality of defect classes in terms of a plurality of classification rules in a multi-dimensional feature space, wherein the plurality of classification rules, for each defect class of the plurality of defect classes, defines in the multi-dimensional feature space a boundary of a region associated with the defect class; receiving one or more electron beam image data associated with a plurality of defects detected in one or more display devices on a large area substrate under inspection; applying, by a processor, an automatic classifier to the electron beam image data, the automatic classifier based on the plurality of classification rules; and identifying the plurality of defects each classified with at least a first level of confidence based on at least one confidence threshold.
Embodiments described herein relate to process systems for cleaning semiconductor process chamber components. The process systems include a process chamber having process chamber components. The process chamber components include a substrate support disposed within a chamber volume of the process chamber. A gas distribution assembly faces the substrate support. A gas baffle is fluidly coupled to the gas distribution assembly. A sensor system is coupled to the process chamber and is configured to monitor at least one characteristic of the volume of the process chamber. A dynamic gas assist is fluidly coupled to the gas baffle and is communicatively coupled to the sensor.
C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
C23C 16/50 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating using electric discharges
C23C 16/52 - Controlling or regulating the coating process
Methods and apparatus for selectively depositing a molybdenum layer on a substrate which includes contacting a substrate surface initially comprising a first portion comprising amorphous silicon, and a second portion comprising silicon and germanium with a molybdenum precursor to selectively form a molybdenum layer on the second portion of the substrate surface.
C23C 16/04 - Coating on selected surface areas, e.g. using masks
C23C 16/08 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the deposition of metallic material from metal halides
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
In one embodiment, a liquid metal pump is disclosed. The liquid metal pump includes a metal-side platen including a liquid metal cavity, an air-side platen including an air cavity, a diaphragm, a liquid metal inlet port, a metal outlet port, a plurality of heating coils, and a shuttle. The diaphragm is disposed between the metal-side platen and the air-side platen at an interface of the metal-side platen and the air-side platen. The diaphragm separates the liquid metal cavity from the air cavity. The shuttle is attached to the diaphragm and configured to actuate the diaphragm between an open and a closed position.
A polishing system (100), a fluid reuse system (500) and a method of polishing a substrate. The polishing system comprises a catch basin (200), a vacuum device (400), and a polishing fluid recycling module (501) for recycling polishing fluid. The catch basin is sized to surround and to abut a polishing pad (104) secured to a platen (102). A radially inward facing surface of the catch basin is further defined by an arc radius which is equal to an arc radius of the platen that the catch basin is sized to surround, the radially inward facing surface of the catch basin configured to allow for a polishing fluid to flow radially outward from the polishing pad into the trough. The systems and method collects and reuses polishing fluid used during a Chemical Mechanical Polishing (CMP) process for manufacturing electronic devices.
B24B 57/00 - Devices for feeding, applying, grading or recovering grinding, polishing or lapping agents
B24B 57/02 - Devices for feeding, applying, grading or recovering grinding, polishing or lapping agents for feeding of fluid, sprayed, pulverised, or liquefied grinding, polishing or lapping agents
B24B 37/04 - Lapping machines or devices; Accessories designed for working plane surfaces
B24B 1/00 - Processes of grinding or polishing; Use of auxiliary equipment in connection with such processes
Embodiments of the present disclosure provide a multiple disk pad conditioner and methods of using the multiple disk pad conditioner during a chemical mechanical polishing (CMP) process. The multiple disk pad conditioner has a plurality of conditioning heads having conditioning disks affixed thereto. The multiple disk pad conditioner can include a conditioning arm, and a plurality of conditioning heads attached to the conditioning arm. Each of the plurality of conditioning heads has a conditioning disk affixed thereto, in some embodiments, each of the conditioning heads include a rotational axis, wherein each of the rotational axes is disposed a distance apart in a first direction that extends along the length of the conditioning arm.
Embodiments described herein relate to an outcoupler of a waveguide combiner includes a plurality of optical device structures and an overburden layer. The optical structures are disposed in or on an optical device substrate. The plurality of optical device structures have a structure refractive index less than or equal to 2.0. The overburden layer is disposed over a top surface and sidewalls of each optical device structure of the plurality of optical device structures. The overburden layer has an overburden refractive index greater than or equal to 2.0. A refractive index contrast between the overburden refractive index and the structure refractive index is about 0.3 to about 0.5. An overburden thickness variation is less than or equal to 20 nm. The overburden thickness variation is a difference between a maximum point and a minimum point of an uppermost surface of the overburden layer.
Methods of manufacturing and processing semiconductor devices (i.e., electronic devices) are described. Embodiments of the disclosure advantageously provide electronic devices which comprise a dipole region and meet reduced thickness and lower thermal budget requirements. The electronic devices described herein comprise a source region, a drain region, and a channel separating the source region and the drain region, an interfacial layer on a top surface of the channel, a high-ĸ dielectric layer on the interfacial layer, a dipole layer on the high-ĸ dielectric layer, and optionally, a capping layer on the dipole layer. In some embodiments, the methods comprise annealing the substrate to drive atoms from the dipole layer into one or more of the interfacial layer or the high-ĸ dielectric layer.
Embodiments of the disclosure provide conformally deposited molybdenum films having reduced resistivity and methods of forming the same. The methods include forming a nucleation layer directly on a dielectric layer on a substrate surface by exposing the substrate surface to a molybdenum-containing precursor and a nucleation reactant, and conformally depositing a molybdenum film on the nucleation layer. Another aspect of the disclosure pertains to a method that is part of a gap fill process, comprising forming a nucleation layer directly on a dielectric region within one or more high aspect ratio gap features, including vertical gap features and/or horizontal gap features, and conformally depositing a molybdenum film on the nucleation layer to fill the feature.
C23C 16/08 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the deposition of metallic material from metal halides
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
C23C 16/04 - Coating on selected surface areas, e.g. using masks
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
61.
PULSED VOLTAGE COMPENSATION FOR PLASMA PROCESSING APPLICATIONS
Embodiments provided herein generally include apparatus, e.g., plasma processing systems, and methods for the plasma processing of a substrate in a processing chamber. Some embodiments are directed to a method for waveform generation, which generally includes delivering a first waveform with an associated setpoint from an energy source; detecting at least one characteristic of the first waveform; estimating a voltage decay during a portion of a pulse during the first waveform; calculating a compensation factor; and adjusting the at least one characteristic using the compensation factor to adjust a voltage decay.
Exemplary semiconductor processing systems may include a gas source coupled with a number of processing chambers. The gas source may include a controller. Each chamber may include an exhaust assembly having a foreline and a pump. The systems may include at least one abatement system coupled with each pump. The systems may include a plurality of exhaust lines that extend between each pump and the abatement system. The systems may include a dilution gas source coupled with each exhaust line. The systems may include a mass flow controller coupled between the dilution gas source and each exhaust line. The systems may include a temperature sensor coupled with each exhaust line between the pump and the abatement system. The temperature sensor may be communicatively coupled with the controller of the gas source, which may control flow of a gas to a chamber based on a measurement from the temperature sensor.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
Embodiments of the present disclosure herein include an apparatus and method for processing a substrate. More specifically, embodiments of this disclosure provide substrate flipping device that includes a gripping actuator, and a substrate securing assembly. The substrate securing assembly comprises an upper structure coupled to the gripping actuator, a lower structure coupled to the gripping actuator, and a plurality of sets of gripping pads attached to the upper structure and the lower structure, wherein each set of gripping pads is configured to secure substrates of different sizes.
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
64.
PIECEWISE FUNCTIONAL FITTING OF SUBSTRATE PROFILES FOR PROCESS LEARNING
A method includes receiving, by a processing device, data indicative of a plurality of measurements of a profile of a substrate. The method further includes separating the data into a plurality of sets of data, a first set of the plurality of sets associated with a first region of the profile, and a second set of the plurality of sets associated with a second region of the profile. The method further includes fitting data of the first set to a first function to generate a first fit function. The first function is selected from a library of functions. The method further includes fitting data of the second set to a second function to generate a second fit function. The method further includes generating a piecewise functional fit of the profile of the substrate. The piecewise functional fit includes the first fit function and the second fit function.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
A three-dimensional (3D) NAND memory structure may include material layers arranged in a vertical stack including alternating horizontal insulating layers and wordline layers. The material layers may be etched to form a landing pad. A vertical wordline may extend through one or more of the horizontal wordline layers beneath the landing pad. The vertical wordline may be conductively connected to a top horizontal wordline, and the vertical wordline may be insulated from any of the horizontal wordlines that the vertical wordline extends through beneath the top horizontal wordline. A liner may also be formed over a top horizontal wordline at the landing pad.
H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 41/50 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
H10B 43/50 - EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
66.
DRY ETCH FOR NITRIDE EXHUME PROCESSES IN 3D NAND FABRICATION
A three-dimensional (3D) NAND memory structure may include alternating layers of materials arranged in a vertical stack on a silicon substrate, such as alternating oxide and nitride layers. The alternating nitride layers may later be removed, and the recesses may be filled with a conductive material to form word lines for the memory array. To avoid pinching off these recesses with silicon byproducts from a traditional wet etch, a dry etch may be instead be used to remove the nitrite layers. To protect the silicon substrate, a first insulating layer may be deposited at the bottom of the slit to cover the exposed silicon substrate before performing the dry etch. After applying a second insulating layer to cover the alternating oxide/nitride layers, a directional etch may punch through both insulating layers to again expose the silicon substrate before applying a solid material fill in the slit.
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
Exemplary substrate support assemblies may include an electrostatic chuck body. The body may include a support plate defining a substrate support surface. The body may include a base plate coupled with the support plate. A bottom surface of the base plate may define an annular recess. The body may include a cooling plate coupled with the base plate. The assemblies may include a support stem coupled with the body. The assemblies may include a heater embedded within the body. The assemblies may include one or more electrodes embedded within the body. The assemblies may include an annular plate disposed within the annular recess. The annular plate may have a thermal conductivity of less than about 20 W/mK. The assemblies may include a vacuum sealing element disposed between the annular plate and the cooling plate. The assemblies may include a thermal gasket disposed radially inward of the vacuum sealing element.
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H02N 13/00 - Clutches or holding devices using electrostatic attraction, e.g. using Johnson-Rahbek effect
A substrate handling system includes a fixed deposition ring; a moving deposition ring disposed above the fixed deposition ring and configured for vertical movement; and a plurality of circumferentially spaced, electrically conductive grounding plates vertically disposed between the fixed deposition ring and the moving deposition ring, each grounding plate extending from a radially inner end to a radially outer end, each grounding plate configured for vertical movement relative to the fixed deposition ring, and each grounding plate having an electrical contact at the radially inner end.
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
A method of forming a structure on a substrate includes forming a tungsten nucleation layer within at least one opening within a multi-tier portion of a substrate. The method includes exposing the nucleation layer a nitrogen-containing gas to inhibit growth of the nucleation layer at narrow portions within the at least one opening. The method includes exposing the at least one opening to the tungsten-containing precursor gas to form a fill layer over the nucleation layer within the at least one opening. The method includes exposing the at least one opening of the substrate to the nitrogen-containing gas or a nitrogen-containing plasma to inhibit growth of portions of the fill layer along the at least one opening.
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
C23C 16/02 - Pretreatment of the material to be coated
C23C 16/04 - Coating on selected surface areas, e.g. using masks
C23C 16/06 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the deposition of metallic material
A chemical mechanical polishing apparatus has a heating system, a purge gas source, a purge liquid source, and a controller. The heating system includes a source of heated gas, an arm extending over a platen, and a manifold in the arm with an a plurality of openings positioned over the platen and separated from a polishing pad for delivering the heated gas onto the polishing pad. The controller is configured to cause the heated gas to flow from the source of heated gas through the manifold and the plurality of openings to heat the polishing pad during a polishing operation, and to cause the apparatus to perform a purging operation which alternates between flowing purge gas from the purge gas source and flowing purge liquid from the purge liquid source through the manifold and the plurality of openings.
B24B 49/14 - Measuring or gauging equipment for controlling the feed movement of the grinding tool or work; Arrangements of indicating or measuring equipment, e.g. for indicating the start of the grinding operation taking regard of the temperature during grinding
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
Exemplary semiconductor processing systems may a lid plate. A gas splitter may be seated on the lid plate. The gas splitter may include a top surface and a plurality of side surfaces. The gas splitter may defines a gas inlet, one or more gas outlets, and one or more gas lumens. The one or more gas lumens may extend between and fluidly couple the gas inlet with each of the one or more gas outlets. A primary gas weldment may extend to and fluidly couples to the gas inlet. A gas panel may include a first fluid source and a second fluid source that are each fluidly coupled with the primary gas weldment. One or more secondary gas weldments may extend between and fluidly couple each of the one or more gas outlets with a respective one of the plurality of processing chambers.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
Exemplary semiconductor processing systems may include a lid plate and a gas splitter. The gas splitter may be seated on the lid plate. The gas splitter may include a top surface and a plurality of side surfaces. The gas splitter may define a gas inlet, a gas outlet, a gas lumen that extends between and fluidly couples the gas inlet with the gas outlet, and a first divert lumen that is fluidly coupled with the gas lumen and that directs gases away from a processing chamber through a divert outlet. The semiconductor processing system may include a first divert weldment. The first divert weldment may extend from and fluidly couple to the divert outlet. The first divert weldment may include a first divert weldment outlet and a second divert weldment outlet.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
Embodiments of methods and associated apparatus for filling features in a silicon-containing dielectric layer of a substrate are provided herein. In some embodiments, a method of filling features in a silicon-containing dielectric layer of a substrate includes: depositing a discontinuous liner layer in the feature via a physical vapor deposition (PVD) process in a first process chamber; performing a hydrogen plasma process in a second process chamber to form silicon-hydrogen bonds on surfaces of the feature not covered by the discontinuous liner layer; and depositing a bulk tungsten layer on the discontinuous liner layer and over the silicon-hydrogen bonds to fill the feature with tungsten in a third process chamber.
An imaging system for capturing spatial images of biological tissue samples may include an imaging chamber configured to hold a biological tissue sample placed in the imaging system; a light source configured to illuminate the biological tissue sample to activate one or more fluorophores in the biological tissue sample; a Time Delay and Integration (TDI) imager comprising a plurality of partitions, where the plurality of partitions may be configured to capture images at a plurality of different depths in the biological tissue sample simultaneously during a scan by the TDI imager; and a controller configured to cause the TDI imager to scan the biological tissue sample.
Processing chambers, substrate supports, centering wafers and methods of center calibrating wafer hand-off are described. A centering wafer comprises a disc-shaped body having a top surface and a bottom surface defining a thickness, a center, an outer edge having an outer peripheral face, a first arc-shaped slit and a second arc-shaped slit. Embodiments of the disclosure advantageously provide the ability to use the centering wafer to monitor and control backside pressure and thereby determine the center of a substrate support prior to processing the centering wafer. The centering wafer may be centered at a plurality of different angles by rotating the centering wafer.
H01L 21/68 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for positioning, orientation or alignment
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
Embodiments described herein relate to sub-pixel circuits, displays including sub- pixel circuits, and a method of forming sub-pixel circuits that may be utilized in a display such as an organic light-emitting diode (OLED) display. Some configurations of the displays described herein, include the sub-pixel circuits and at least one sensor opening adjacent to the overhang structure and an adjacent sub- pixel circuit. The at least one sensor opening includes a sensor disposed thereunder. Other configurations displays described herein, include sub-pixel circuits including OLED sub-pixels and a transparent sub-pixel such that a sensor is disposed thereunder. The configurations described herein utilize sensors that are integrated to increase the transmittance of the display while eliminating the need for bezels and reducing dead zones in the display.
Exemplary substrate processing systems may include a lid plate. The systems may include a gas feed line having an RPS outlet and a bypass outlet. The systems may include a remote plasma unit supported atop the lid plate. The remote plasma unit may include an inlet and an outlet. The inlet may be coupled with the RPS outlet. The systems may include a center manifold having an RPS inlet coupled with the outlet and a bypass inlet coupled with the bypass outlet. The center manifold may include a plurality of outlet ports. The systems may include a plurality of side manifolds that are fluidly coupled with the outlet ports. Each of the side manifolds may define a gas lumen. The systems may include a plurality of output manifolds seated on the lid plate. Each output manifold may be fluidly coupled with the gas lumen of one of the side manifolds.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
Methods of selectively depositing a carbon-containing layer are described. Exemplary processing methods may include treating a substrate comprising a carbon-containing surface and a silicon-containing surface with one or more of ozone or hydrogen peroxide to passivate the silicon-containing surface. In one or more embodiments, a carbon-containing layer is then selectively deposited on the carbon-containing surface and not on the silicon-containing surface by flowing a first precursor over the substrate to form a first portion of an initial carbon-containing film on the carbon-containing surface and not on the silicon-containing surface. The methods may include removing a first precursor effluent from the substrate. A second precursor may then be flowed over the substrate to react with the first portion of the initial carbon-containing layer. The methods may include removing a second precursor effluent from the substrate.
H01L 21/033 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or comprising inorganic layers
H01L 21/32 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers using masks
79.
HIGH-THROUGHPUT SPATIAL IMAGING SYSTEM FOR BIOLOGICAL SAMPLES
An imaging system for capturing spatial images of biological tissue samples may include an imaging chamber configured to hold a biological tissue sample placed in the imaging system; a light source configured to illuminate the biological tissue sample to activate a plurality of fluorophores in the biological tissue sample; and a plurality of Time Delay and Integration (TDI) imagers configured to simultaneously scan the biological tissue sample, where the plurality of TDI imagers may be configured to separately receive light from different ones of the plurality of fluorophores.
A processing apparatus (100) for processing a flexible substrate (10) is described. The processing apparatus (100) includes a vacuum processing chamber (110) including at least one deposition source (111) for depositing a layer of material on the flexible substrate (10). Further, the processing apparatus (100) includes a post- processing chamber (120) comprising a post-processing roller (130) and a gas supply (140). The post processing roller (130) has a substrate facing surface (131) comprising a plurality of gas outlets (132). The gas supply (140) is connected to the post processing roller (130) to provide a gas through the plurality of gas outlets (132) into an interspace between the flexible substrate and the substrate facing surface (131).
C23C 16/06 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the deposition of metallic material
C23C 16/54 - Apparatus specially adapted for continuous coating
81.
EVAPORATION SOURCE, MATERIAL DEPOSITION APPARATUS, AND METHOD OF DEPOSITING MATERIAL ON A SUBSTRATE
An apparatus for rotating a substrate within a deposition chamber is described. The substrate is rotated using a substrate support assembly with a shaft and a susceptor coupled to a top of the shaft. The susceptor and the shaft are coupled together using a cogged feature. The cogged feature includes a plurality of teeth or projections on a coupling portion of the shaft which interlock with an indent disposed on the bottom of the susceptor. A lift pin assembly is further coupled to the shaft and configured to raise and lower a substrate from the susceptor.
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
Embodiments described herein relate to a susceptor kit. The susceptor kit includes a susceptor support plate including a plurality of susceptor lift pin holes and a plurality of susceptor support holes, a plurality of susceptor supports recessed within the plurality of susceptor support holes and coupled to the susceptor support plate, and a lift pin assembly. The plurality of susceptor supports receive a plurality of susceptor support pins. The support body supports the support pin link in a spaced apart relation to the susceptor support plate. The lift pin assembly is received in the plurality of susceptor lift pin holes. The lift pin assembly includes a lift pin cap and a susceptor lift pin comprising a susceptor stop plate. The susceptor support plate stop is receivable within the susceptor lift pin holes.
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
Embodiments described herein relate semiconductor manufacturing and processing. More particularly, a processing systems for auto correcting misalignments of substrates in process chambers is provided. The processing system includes a process chamber having a substrate support disposed within a chamber volume of the process chamber. The substrate support includes a pocket for receiving a substrate, and a plurality of flow conduits extending between a top surface of the pocket and a bottom surface of the substrate support. An imaging device is coupled to the process chamber and configured to monitor a position of a substrate when loaded in the pocket of the substrate support.
H01L 21/68 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for positioning, orientation or alignment
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
C23C 16/52 - Controlling or regulating the coating process
85.
FLUORINE BASED CLEANING FOR PLASMA DOPING APPLICATIONS
A method of cleaning a plasma chamber is disclosed. Periodically, a cleaning process is performed. The cleaning process comprises introducing a mixture of fluoride molecules and argon into the plasma chamber and creating a plasma. The fluoride molecules are ionized and interact with the deposited material on the chamber walls. This causes the fluorine ions to bond to the deposited material, which typically results in a gas that can be exhausted from the plasma chamber. When the deposited material has been removed, the amount of free fluorine within the plasma chamber increases. This increase in fluorine may be used to determine when the plasma chamber is cleaned.
Methods and apparatus for processing a substrate is provided herein. For example, the method comprises prior to processing a substrate, obtaining a first measurement at a first point along a surface of the substrate, in a process chamber processing the substrate in a presence of an electric field, subsequent to processing the substrate, obtaining a second measurement at the first point along the surface of the substrate, and determining whether substrate warpage occurred based upon analysis of the first measurement and the second measurement.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
G01B 11/24 - Measuring arrangements characterised by the use of optical techniques for measuring contours or curvatures
Methods for selective deposition are described herein. The methods include depositing an oxide on a first portion of a substrate surface selected from the group consisting of a metal surface, a metal nitride surface and a metal silicide surface. The methods further comprise selectively depositing a molybdenum film on a second portion of the substrate surface that does not have the oxide deposited thereon.
C23C 16/06 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the deposition of metallic material
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
C23C 16/515 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating using electric discharges using pulsed discharges
C23C 14/04 - Coating on selected surface areas, e.g. using masks
Methods of depositing a conformal carbon-containing film on an EUV photoresist to reduce line edge roughness (LER) are described. Exemplary processing methods may include flowing a first precursor over a patterned EUV surface to form a first portion of an initial carbon-containing film on the structure. The methods may include removing a first precursor effluent from the patterned EUV photoresist. A second precursor may then be flowed over the patterned EUV photoresist to react with the first portion of the initial carbon-containing film. The methods may include removing a second precursor effluent from the patterned EUV photoresist. The methods may include etching the substrate to remove a portion of the carbon-containing film and expose a top surface of the patterned surface and expose the substrate between the patterned surfaces.
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/033 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or comprising inorganic layers
G03F 7/11 - Photosensitive materials - characterised by structural details, e.g. supports, auxiliary layers having cover layers or intermediate layers, e.g. subbing layers
89.
GENERATING INDICATIONS OF LEARNING OF MODELS FOR SEMICONDUCTOR PROCESSING
A method includes receiving a first value associated with a first input parameter of a model. The method further includes receiving a first plurality of values associated with a second input parameter of the model. The method further includes providing to the model the first value and the first plurality of values. The method further includes receiving a first plurality of outputs from the model. The method further includes preparing the first plurality of outputs for presentation via a presentation element of a graphical user interface. The presentation element includes two axes. The first axis is associated with a first property of a first feature associated with the output from the model. The second axis is associated with a second property of the first feature.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
90.
METHODS AND MECHANISMS FOR ADJUSTING CHUCKING VOLTAGE DURING SUBSTRATE MANUFACTURING
An electronic device manufacturing system including a substrate-holder configured to secure a substrate during processing and a controller, operatively coupled to the substrate-holder. The controller is configured to apply, to an electrode of the substrate-holder, a first voltage. The controller is further configured to determine a first impedance value between the substrate-holder and the substrate. The controller is further configured to determine a delta value between the first impedance value and a predetermined second impedance value, and determine whether the delta value satisfies a threshold criterion. Responsive to the delta value failing to satisfy the threshold criterion, the controller is further configured to apply a second voltage to the substrate, wherein the second voltage is greater than the first voltage.
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
Semiconductor devices (e.g., GAA device structures) and processing methods and cluster tools for forming GAA device structures are described. The cluster tools for forming GAA device structures comprise a first etch chamber, a second etch chamber, and a third etch chamber. Each of the first etch chamber and the second etch chamber independently comprises a single-wafer chamber or an immersion chamber. One or more of the first etch chamber or the second etch chamber may be a wet etch chamber. In some embodiments, at least one of the first etch chamber, the second etch chamber, and the third etch chamber is a dry etch chamber. The cluster tool described herein advantageously reduces the number of cleaning processes, the total time between cleaning and processing operations, variations in time between processing and variation in sidewall loss compared to conventional cluster tools.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
Methods and systems for generating a predictive HER2 score using machine learning models are disclosed. An example method generally includes identifying a plurality of nuclei and membrane segments in regions of interest in an input image using a first machine learning model. For the plurality of nuclei and membrane segments identified in the input image, a plurality of features are extracted and classified into one of a plurality of feature categories. Using a second machine learning model, a predictive HER2 score indicating the likelihood of whether a stained tissue sample captured in the input image is HER2 positive or HER2 negative is generated based on the classification assigned to the plurality of extracted features associated with the plurality o segments.
G16B 20/00 - ICT specially adapted for functional genomics or proteomics, e.g. genotype-phenotype associations
G16H 30/00 - ICT specially adapted for the handling or processing of medical images
G16H 50/20 - ICT specially adapted for medical diagnosis, medical simulation or medical data mining; ICT specially adapted for detecting, monitoring or modelling epidemics or pandemics for computer-aided diagnosis, e.g. based on medical expert systems
G06V 20/69 - Microscopic objects, e.g. biological cells or cellular parts
G06V 10/25 - Determination of region of interest [ROI] or a volume of interest [VOI]
G06V 10/764 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using classification, e.g. of video objects
G06V 10/82 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using neural networks
G06V 10/56 - Extraction of image or video features relating to colour
93.
TIME DELAY INTEGRATION ACQUISITION FOR SPATIAL GENOMICS IMAGING
An imaging system for capturing spatial-omic images of biological tissue samples may include an imaging chamber configured to secure a biological tissue sample placed in the imaging system; a Time Delay and Integration (TDI) imager comprising at least one scan line; a light source configured to illuminate an area on the biological tissue sample that is being captured by the TDI imager; and a controller configured to cause the TDI imager to scan the biological tissue sample using one or more TDI scans of the biological tissue sample.
A method and apparatus for heating a transparent component within a semiconductor processing chamber is described. The transparent component is heated using a transparent heater coupled to the transparent component. The transparent heater includes a support base, an electrode layer, and a capping layer. The electrode layer is a heating element. The transparent heater has an optical transparency of greater than about 80% at a wavelength which is emitted by one or more radiation sources within the processing chamber. The transparent heater is a flexible transparent heater or is formed of a plurality of sub-heaters.
C30B 25/10 - Heating of the reaction chamber or the substrate
C30B 25/08 - Reaction chambers; Selection of materials therefor
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
95.
ACTIVELY CONTROLLED PRE-HEAT RING FOR PROCESS TEMPERATURE CONTROL
An apparatus for heating a gas is described. The apparatus is a pre-heat ring and heater assembly positioned in a deposition chamber, such as an epitaxial deposition chamber. The pre-heat ring has a first portion configured to be heated using one or more heaters. The one or more heaters are disposed through a sidewall of the process volume beneath the pre-heat ring and are configured to heat the pre- heat ring so that gas flowed over the pre-heat ring is also heated before being flowed over a substrate. The one or more heaters may include two heaters disposed at distal ends of the first portion of the pre-heat ring. One or more temperature sensors are also configured to measure a temperature of the pre-heat ring.
A method includes performing an etch process, including supplying a first process gas and a second process gas onto a surface of a substrate on a substrate support within a processing volume of a processing chamber for a first time duration, wherein the first process gas comprises fluorine-containing gas, and the second process gas comprises nitrogen-containing gas, and performing an anneal process to sublimate by-products formed on the surface of the substrate during the etch process, and supplying the first process gas without supplying the second process gas into the processing volume of the processing chamber for a second time duration.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
97.
SUBSTRATE MODIFICATION FOR SUPERLATTICE CRITICAL THICKNESS IMPROVEMENT
A method and apparatus for forming strain relaxed buffers that may be used in semiconductor devices incorporating superlattice structures are provided. The method includes epitaxially depositing a first silicon germanium layer over the substrate. The first silicon germanium layer has a first surface that contacts a frontside surface of the substrate and a second surface opposite the first surface. The first silicon germanium layer has a first thickness and a germanium concentration gradient that increases from the first surface to the second surface. The method further includes epitaxially depositing a silicon germanium capping layer on the first silicon germanium layer. The silicon germanium capping layer has a second thickness and a substantially uniform germanium concentration that is equal to, substantially equal to, or greater than a maximum germanium concentration of the germanium concentration gradient.
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H10B 12/00 - Dynamic random access memory [DRAM] devices
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
Embodiments disclosed herein include sensor devices. In an embodiment, a sensor device comprises a substrate, a first sensor of a first type on the substrate, where a catalytic layer is provided as at least part of the first sensor, a second sensor of the first type on the substrate and adjacent to the first sensor, and a lid over the substrate, where an opening through the lid is provided over the first sensor and the second sensor.
G01K 7/02 - Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat using thermoelectric elements, e.g. thermocouples
G01K 7/16 - Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat using resistive elements
G01K 11/26 - Measuring temperature based on physical or chemical changes not covered by group , , , or using measurement of acoustic effects of resonant frequencies
G01N 9/00 - Investigating density or specific gravity of materials; Analysing materials by determining density or specific gravity
G01D 21/02 - Measuring two or more variables by means not covered by a single other subclass
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
A sealing member includes a monolithic body including a first portion adjoining a second portion. The first portion forms part of a circle. The second portion includes first and second lobes. Each lobe adjoins the first portion with a concave surface. In one example, each lobe includes a rounded tip, and a convex surface extends from one rounded tip to the other rounded tip.
A method includes depositing a flowable film on a substrate by providing a first input flow, the first input flow including plasma effluents of a first precursor, removing a portion of the flowable film from a sidewall of a feature defined within the substrate to obtain a remaining portion of the flowable film by providing a second input flow, the second input flow including plasma effluents of a second precursor, reducing hydrogen content of the remaining portion of the flowable film to obtain a densified film by providing a third input flow, the third input flow including plasma effluents of a third precursor, and treating the densified film in accordance with a film treatment process.
C23C 16/505 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating using electric discharges using radio frequency discharges