Provided is a novel semiconductor device. The present invention comprises a flip-flop circuit and a memory circuit. The memory circuit comprises a first transistor, a second transistor, a first capacitance element, and a second capacitance element, and further comprises a substrate, a first insulator, and a second insulator. The first insulator is provided on the substrate, and the second insulator is provided on the first insulator. The first insulator comprises a first opening and a second opening, which are provided extending perpendicular to a surface of the substrate, and the second insulator comprises a third opening and a fourth opening, which are provided extending perpendicular to a surface of the substrate. The flip-flop circuit is provided on the substrate. At least a portion of the first capacitance element and the second capacitance element is respectively provided in the first opening and the second opening, and at least a portion of the first transistor and the second transistor is respectively provided in the third opening and the fourth opening.
H10B 12/00 - Dynamic random access memory [DRAM] devices
G11C 14/00 - Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
H01L 27/04 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
One aspect of the present invention provides a secondary battery that can be used in a wide temperature range and that is not easily affected by ambient temperatures. Also provided is a highly safe secondary battery. In the present invention, a secondary battery is produced using three types or two types of conduction aids and without using an organic resin binder. Selected as a carbon material functioning as the conduction aid is graphene oxide, graphene oxide that has been subjected to a reduction treatment, or carbon nanotubes.
Provided is a novel semiconductor device. This semiconductor device has a flip-flop group that includes n flip-flops, and a plurality of storage units. The flip-flop group has a function for saving n bits of data. One of the plurality of storage units has a function for saving the n bits of data. Another one of the plurality of storage units has a function for saving p bits of data. When the data saved in the flip-flop group is n bits long, the n bits of data saved in the flip-flop group are written to the one of the storage units in a first operation. When the data saved in the flip-flop group is p bits long, the p bits of data are written to the other one of the storage units in a second operation. n is any integer equal to or greater than 2, and p is any integer equal to or greater than 1 and less than n.
G11C 14/00 - Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
G11C 5/02 - Disposition of storage elements, e.g. in the form of a matrix array
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 41/70 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
H10B 53/30 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
H10B 99/00 - Subject matter not provided for in other groups of this subclass
G06F 9/48 - Program initiating; Program switching, e.g. by interrupt
H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
H01L 27/04 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 21/336 - Field-effect transistors with an insulated gate
H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
Provided is a semiconductor device having a narrow occupation area. This semiconductor device comprises a first transistor, a second transistor, a first insulating layer, and a second insulating layer. The first transistor comprises a metal oxide layer and a first conductive layer. The first insulating layer is provided on the first conductive layer. The second insulating layer is provided on the first insulating layer. The first insulating layer and the second insulating layer have an opening that reaches the first conductive layer. The metal oxide layer is in contact with a top surface of the first conductive layer, a side surface of the first insulating layer, and a top surface and a side surface of the second insulating layer. The first insulating layer contains oxygen. The second insulating layer contains nitrogen. The metal oxide layer has a region that is in contact with the second insulating layer and any one of the gate, the source, and the drain of the second transistor.
G02F 1/1368 - Active matrix addressed cells in which the switching element is a three-electrode device
G09F 9/30 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
H01L 21/336 - Field-effect transistors with an insulated gate
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H10K 59/123 - Connection of the pixel electrodes to the thin film transistors [TFT]
H10K 59/124 - Insulating layers formed between TFT elements and OLED elements
5.
SEMICONDUCTOR DEVICE, MEMORY DEVICE, AND ELECTRONIC APPARATUS
Provided is a semiconductor device having a high storage density. This semiconductor device has a first layer and a second layer above the first layer. The first layer has first to fourth conductors, first to fifth insulators, and a first semiconductor, and the second layer has fifth to seventh conductors, sixth and seventh insulators, and a second semiconductor. The first insulator, the second conductor, the second insulator, and the third conductor are formed in said order on the first conductor and are each provided with a first opening of which the bottom surface is the first semiconductor. In addition, the first semiconductor, the fourth insulator, and the fourth conductor are formed in said order in the first opening. In addition, the third insulator is positioned on the side surfaces of the third conductor and on the upper surface of the second insulator. The fifth conductor is positioned on the upper surface of the fourth conductor and the upper surface of the fifth insulator. The sixth insulator and the sixth conductor are formed in said order on the fifth conductor and are each provided with a second opening of which the bottom surface is the fifth conductor. In addition, the second semiconductor, the seventh insulator, and the seventh conductor are formed in said order in the second opening.
H10B 12/00 - Dynamic random access memory [DRAM] devices
H01L 21/336 - Field-effect transistors with an insulated gate
H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
H10B 41/70 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
Provided is a storage device which can be miniaturized and made highly integrated. This storage device has a configuration having a capacitive element formed directly below a vertical transistor, wherein one electrode of the capacitive element is shared with either a source electrode or a drain electrode of the vertical transistor. Therefore, it is possible to provide a storage device in which the overlapping area of the vertical transistor and the capacitive element is large, and which has a high degree of integration. In addition, since the area ratio of the capacitive element to the cell area can be increased, the capacitive element can be formed with a low profile, and a thin-type memory cell array can be formed.
Provided is a secondary battery which increases conductivity of a positive electrode and achieves a high capacity. This secondary battery comprises a positive electrode having a positive-electrode active substance, a first conductive material, and a second conductive material having a shape different from that of the first conductive material. The positive-electrode active substance has lithium cobaltate containing magnesium in a surface layer portion thereof. The weight of the second conductive material is smaller than or equal to the weight of the first conductive material. The second conductive material forms an aggregate and has a portion that sticks to the positive-electrode active substance.
H01M 4/131 - Electrodes based on mixed oxides or hydroxides, or on mixtures of oxides or hydroxides, e.g. LiCoOx
H01M 4/36 - Selection of substances as active materials, active masses, active liquids
H01M 4/525 - Selection of substances as active materials, active masses, active liquids of inorganic oxides or hydroxides of nickel, cobalt or iron of mixed oxides or hydroxides containing iron, cobalt or nickel for inserting or intercalating light metals, e.g. LiNiO2, LiCoO2 or LiCoOxFy
H01M 4/62 - Selection of inactive substances as ingredients for active masses, e.g. binders, fillers
This storage device has: a first insulator on a substrate; an oxide semiconductor which covers at least a portion of the first insulator; first and second conductors on the oxide semiconductor; a second insulator on the first conductor; a third insulator on the second conductor; a third conductor on the second insulator; a fourth conductor on the third insulator; a fourth insulator which is disposed on the third conductor and the fourth conductor and has a first opening overlapping gaps between the first conductor, the second insulator, and the third conductor, and the second conductor, the third insulator, and the fourth conductor; a fifth insulator disposed inside the first opening; a fifth conductor disposed on the fifth insulator; a sixth conductor which is disposed inside a second opening formed in the fourth insulator and is in contact with the upper surface of the third conductor; and a seventh conductor which is disposed inside a third opening formed in the fourth insulator, the third insulator, and the fourth conductor and is in contact with the upper surface of the second conductor, wherein the height of the first insulator is greater than the width thereof, and the upper surface of the first insulator is in contact with the fifth insulator.
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 41/70 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
H01L 27/04 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 21/336 - Field-effect transistors with an insulated gate
H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
The present invention provides a semiconductor device which comprises a transistor of a very small size. This semiconductor device comprises first and second transistors; the first transistor comprises first to third conductive layers, a first semiconductor layer and a first insulating layer; the second conductive layer is arranged on the first conductive layer; the first semiconductor layer is in contact with the upper surface of the first conductive layer and the second conductive layer; the first insulating layer is in contact with the upper surface of the first semiconductor layer; the third conductive layer is arranged on the first semiconductor layer and the first insulating layer; the second transistor comprises fourth to sixth conductive layers, a second semiconductor layer and the first conductive layer; the fifth conductive layer is arranged on the fourth conductive layer; the second semiconductor layer is in contact with the upper surface of the fourth conductive layer and the fifth conductive layer; the first insulating layer is in contact with the upper surface of the second semiconductor layer; the sixth conductive layer is arranged on the second semiconductor layer and the first insulating layer; a second insulating layer is arranged between the first and second conductive layers and between the fourth and fifth conductive layers; and the thickness of the second insulating layer between the first and second conductive layers is different from the thickness of the second insulating layer between the fourth and fifth conductive layers.
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 41/70 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
H10B 99/00 - Subject matter not provided for in other groups of this subclass
H10K 50/10 - OLEDs or polymer light-emitting diodes [PLED]
The present invention provides a semiconductor device which achieves both low power consumption and high performance. This semiconductor device comprises a first conductive layer, a second conductive layer, a first semiconductor layer, a second insulating layer that is arranged on the first semiconductor layer, a third conductive layer that is arranged on the second insulating layer, and a first insulating layer that is sandwiched between the first conductive layer and the second conductive layer; the first insulating layer has a first opening which reaches the first conductive layer; the second conductive layer has a second opening; the first opening and the second opening overlap with each other when viewed in plan; the first semiconductor layer is in contact with the upper surface of the first conductive layer and the lateral surface of the first insulating layer in the first opening; the first semiconductor layer is in contact with the lateral surface of the second conductive layer in the second opening; the first semiconductor layer has a region which overlaps with the third conductive layer, with the second insulating layer being interposed therebetween; and the lateral surface of the first insulating layer in the first opening has a region where the angle between the lateral surface of the first insulating layer and the upper surface of the first conductive layer is not less than 10 degrees but less than 55 degrees.
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H05B 45/60 - Circuit arrangements for operating LEDs comprising organic material, e.g. for operating organic light-emitting diodes [OLED] or polymer light-emitting diodes [PLED]
H10K 50/10 - OLEDs or polymer light-emitting diodes [PLED]
Provided is a storage device which can be micro-fabricated or highly integrated. This storage device has a plurality of memory cells, a first insulator, and a second insulator disposed on the first insulator. Each of the memory cells has a capacitance element and a transistor disposed on the capacitance element. At least a part of the capacitance element is disposed in a first opening provided in the first insulator. At least a part of the transistor is disposed in a second opening provided on the second insulator. The first opening has a region overlapping with the second opening. The diameter of the first opening is larger than the diameter of the second opening. In the adjacent memory cells, the interval at which capacitance elements are arranged coincides with the interval at which transistors are arranged.
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
Provided is a semiconductor device configured to allow miniaturization or an advanced degree of integration. This semiconductor device has a first transistor, a connection part, a first insulator, a second insulator, and first wiring. The connection part has a first electrode and a second electrode. The first transistor has second and third electrodes, a first semiconductor, a gate insulator, and a first gate electrode. The first insulator has a first opening that reaches the first wiring. The first electrode is in contact with a side surface in the first opening and an upper surface of the first wiring. The second electrode is in contact with the first electrode in the first opening. The second insulator has a second opening that reaches the second electrode. The third electrode is provided on the second insulator. The first semiconductor is in contact with the third electrode, a side surface in the second opening in the second insulator, and an upper surface of the second electrode. The gate insulator is in contact with the first semiconductor in the second opening. The first gate electrode faces the first semiconductor via the gate insulator.
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 41/70 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
H01L 21/336 - Field-effect transistors with an insulated gate
H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
Provided is a storage device that enables high integration. The storage device comprises a first transistor and a second transistor on the first transistor. The first transistor has a first oxide semiconductor that is on a substrate, a first conductor and second conductor that are on the first oxide semiconductor and separate from each other, a first insulator that is disposed on the first conductor and the second conductor and that has an opening which overlaps with a region between the first conductor and the second conductor, a second insulator that is disposed in the opening of the first insulator and on the first oxide semiconductor, and a third conductor that is disposed on the second insulator in the opening. The second transistor has a third insulator that is disposed on the first insulator and the third conductor and that has an opening, a fourth conductor that is disposed on the third insulator and that has an opening overlapping with the opening of the third insulator, a second oxide semiconductor that is disposed in the openings of the third insulator and the fourth conductor, a fourth insulator that is disposed on the second oxide semiconductor in the opening, and a fifth conductor that is disposed on the fourth insulator in the opening. Part of the second oxide semiconductor passes through the third insulator and is electrically connected with the third conductor.
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
The present invention provides a semiconductor device which enables the achievement of miniaturization or high integration. According to the present invention, a second layer, a mask and a first resist mask are sequentially formed on a first layer; the first resist mask is provided with a first opening part; the size of the first opening part in a plan view is reduced; the mask is provided with a second opening part in a position where the second opening part overlaps with the first opening part; the first resist mask is removed; a second resist mask is formed on the mask, which has been provided with the second opening part; the second resist mask is provided with a third opening part; the size of the third opening part in a plan view is reduced; the mask is provided with a fourth opening part in a position where the fourth opening part overlaps with the third opening part but does not overlap with the second opening part; the second resist mask is removed; the second layer is provided with fifth opening parts in positions where the fifth opening parts respectively overlap with the second opening part and the fourth opening part; the mask is removed; and an oxide semiconductor, which is in contact with the lateral surface of the second layer and the upper surface of the first layer, is formed within the fifth opening parts.
H10B 53/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
H01L 27/04 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
Provided is a highly safe high-capacity secondary battery. This battery comprises a positive electrode having a positive electrode active material and a conductive material. The positive electrode active material has cobalt, oxygen, magnesium, and nickel, has a median diameter of 1-12 μm inclusive, and in depth-direction EDX-ray analysis of a region having a surface other than the (00l) surface of the positive electrode active material, has a portion where the distribution of magnesium overlaps with the distribution of nickel. The conductive material is stuck to a portion of the surface other than the (00l) surface of the positive electrode active material.
H01M 4/525 - Selection of substances as active materials, active masses, active liquids of inorganic oxides or hydroxides of nickel, cobalt or iron of mixed oxides or hydroxides containing iron, cobalt or nickel for inserting or intercalating light metals, e.g. LiNiO2, LiCoO2 or LiCoOxFy
The present invention provides a semiconductor device with stable operation. This semiconductor device has a first transistor, a second transistor, a third transistor, and a first capacitance element. One among the source and drain of the third transistor is electrically connected to one among the source and drain of the second transistor. The other among the source and drain of the third transistor is electrically connected to a gate of the first transistor and a first terminal of the first capacitance element. One among the source and drain of the first transistor is electrically connected to a gate of the second transistor and a second terminal of the first capacitance element. The semiconductor device can be provided to a drive circuit having a function for transmitting, to a display device, signals for causing an image to be displayed.
H03K 17/06 - Modifications for ensuring a fully conducting state
G02F 1/1368 - Active matrix addressed cells in which the switching element is a three-electrode device
G09F 9/30 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
G09G 3/20 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
H05B 33/14 - Light sources with substantially two-dimensional radiating surfaces characterised by the chemical or physical composition or the arrangement of the electroluminescent material
The present invention provides a transistor which enables the achievement of miniaturization. The present invention also provides a transistor which has good electrical characteristics. This semiconductor device comprises first to third conductive layers, first to third semiconductor layers, and first and second insulating layers. The second semiconductor layer is arranged on the first conductive layer; the first insulating layer is arranged on the second semiconductor layer; the second conductive layer is arranged on the first insulating layer; and the third semiconductor layer is arranged on the second conductive layer. The first insulating layer has an opening which reaches the second semiconductor layer. The first semiconductor layer has a portion that is in contact with the third semiconductor layer, a portion that is in contact with the lateral surface of the first insulating layer within the opening, and a portion that is in contact with the second semiconductor layer. The second insulating layer covers the first semiconductor layer. The third conductive layer overlaps with the first semiconductor layer, with the second insulating layer being interposed therebetween. The first to third semiconductor layers contain silicon. The second and third semiconductor layers contain a same impurity element. The first insulating layer contains hydrogen, nitrogen and silicon.
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H10K 50/10 - OLEDs or polymer light-emitting diodes [PLED]
Provided is a display device having a high display quality. This display device has pixels, a scanning line driving circuit, and a power supply circuit. The pixels each have first and second transistors, and the second transistor has a semiconductor layer provided in a first opening formed in an interlayer insulating layer on a substrate. A first conductive layer that functions as a gate electrode of the first transistor has a region that extends in a first direction, and is electrically connected to the scanning line driving circuit. A second conductive layer that functions as a source electrode or a drain electrode of the second transistor is provided on the interlayer insulating layer and has a second opening overlapping with the first opening. The second conductive layer has a region that extends in a second direction perpendicular to the first direction, and is electrically connected to the power supply circuit. The first conductive layer and the second conductive layer have regions that overlap with each other having therebetween an insulating layer that is provided in a layer between the first conductive layer, and the second conductive layer and the semiconductor layer, and that functions as a gate insulating layer for the first and second transistors.
G09F 9/30 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
G02F 1/1368 - Active matrix addressed cells in which the switching element is a three-electrode device
G09G 3/20 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
G09G 3/3225 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
G09G 3/36 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix by control of light from an independent source using liquid crystals
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 41/70 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
H10K 50/10 - OLEDs or polymer light-emitting diodes [PLED]
H10K 59/123 - Connection of the pixel electrodes to the thin film transistors [TFT]
H10K 59/124 - Insulating layers formed between TFT elements and OLED elements
Provided is a high-definition and highly reliable organic semiconductor device. Provided is a light-emitting device that is one among a plurality of light-emitting devices formed on an insulating layer, wherein: when a film having a similar composition to a light-emitting layer that includes a first substance and a light-emitting substance has been irradiated in an air atmosphere with a daylight color LED at an illuminance of 300 lux for 60 minutes, the concentration of an oxygen adduct in the first substance is at least 15 ppm; and the interval between first electrodes of adjacent light-emitting devices is 2-5 µm, inclusive.
Provided is a semiconductor device having a novel configuration. This semiconductor device has: a first element layer on which a readout circuit is provided; a second element layer on which an amplification circuit is provided; and a third element layer on which a memory cell is provided. The second element layer is provided so as to be layered on the first element layer. The third element layer is provided so as to be layered on the second element layer. The memory cell and the amplification circuit are electrically connected via a first bit line. The amplification circuit and the readout circuit are electrically connected via a second bit line. The amplification circuit has the function of transmitting a signal corresponding to the electric potential of the first bit line to the second bit line. The amplification circuit has a first transistor in which a first semiconductor layer having a channel forming region has an oxide semiconductor. The memory cell has: a second transistor in which a second semiconductor layer having a channel forming region has an oxide semiconductor; and a capacitive element. The first semiconductor layer is provided in a direction horizontal to the surface of a substrate to which the first element layer is provided. The second semiconductor layer is provided in a direction perpendicular to the surface of the substrate to which the first element layer is provided.
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
Provided is a semiconductor device that occupies a small area. The semiconductor device includes a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a first conductive layer, a second conductive layer, and a first insulation layer. The first insulation layer is provided on the first conductive layer. The second conductive layer is provided on the first insulation layer. The first insulation layer and the second conductive layer include an opening that reaches the first conductive layer. The first semiconductor layer contacts an upper surface of the first conductive layer, a side surface of the first insulation layer, and an upper surface and a side surface of the second conductive layer. The second semiconductor layer is provided on the first semiconductor layer. The third semiconductor layer is provided on the second semiconductor layer. The first semiconductor layer includes a first material. The second semiconductor layer includes a second material. The third semiconductor layer includes a third material. A band gap of the first material is greater than a band gap of the second material. A band gap of the third material is greater than the band gap of the second material.
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
The present invention provides a novel energy storage system. The energy storage system includes a secondary battery, a current measurement circuit, a voltage measurement circuit, and a control circuit, wherein the secondary battery has a negative electrode, the negative electrode contains graphite and silicon, the current measurement circuit and the voltage measurement circuit are each electrically connected to the control circuit, the control circuit has a function that starts charging of the secondary battery, the control circuit has a function that uses a current value detected by the current measurement circuit and a voltage value detected by the voltage measurement circuit to perform a first operation for calculating the voltage derivative of the quantity of electricity in the charging current of the secondary battery and a second operation for detecting an extreme value of the voltage derivative, and the control circuit has a function that stops charging when a predetermined time has elapsed since the detection of the extreme value in the second operation.
H02J 7/10 - Regulation of the charging current or voltage using discharge tubes or semiconductor devices using semiconductor devices only
H01M 10/48 - Accumulators combined with arrangements for measuring, testing or indicating the condition of cells, e.g. the level or density of the electrolyte
23.
STORAGE DEVICE AND STORAGE DEVICE PRODUCTION METHOD
Provided is a storage device which can be micro-fabricated or highly integrated. This storage device has a memory cell on a first transistor including silicon in a semiconductor layer. The memory cell has a capacitance element and a second transistor on the capacitance element. The capacitance element has a first conductor, a first insulator, and a second conductor, laminated in the stated order. The second conductor serves as one of a source and a drain of the second transistor. A third conductor serves as the other of the source and the drain of the second transistor, and is located on a second insulator. The second insulator and the third conductor are each provided with an opening which reaches the second conductor. An oxide semiconductor, a third insulator, and a fourth conductor are laminated in the stated order so as to overlap with the opening. The fourth conductor is electrically connected to a source or a drain of the first transistor.
H10B 12/00 - Dynamic random access memory [DRAM] devices
H01L 21/205 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth using reduction or decomposition of a gaseous compound yielding a solid condensate, i.e. chemical deposition
H01L 21/316 - Inorganic layers composed of oxides or glassy oxides or oxide-based glass
The present invention provides a highly integrated and reliable semiconductor device. A back gate of a second transistor is electrically connected to a control signal line that provides a control signal for controlling the threshold voltage of the second transistor. One of the source or the drain of the second transistor is electrically connected to a readout word line that provides a readout word signal. The other of the source or the drain of the second transistor is electrically connected to a readout bit line that reads out a potential corresponding to data. In a memory cell that is selected in a data readout period, a low level is provided as the readout word signal and a high level is provided as the control signal. In a memory cell that is unselected in a data readout period, a high level is provided as the readout word signal and a low level is provided as the control signal.
G11C 11/405 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with three charge-transfer gates, e.g. MOS transistors, per cell
G11C 11/4091 - Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
Provided is a storage device which allows for miniaturization and high integration. The present invention comprises: a first insulator on a substrate; an oxide semiconductor covering the first insulator; a first conductor and a second conductor on the oxide semiconductor; a second insulator on the first conductor; a third insulator on the second conductor; a third conductor on the second insulator; a fourth conductor on the third insulator; a fourth insulator which is disposed on the third conductor and the fourth conductor and which has a first opening overlapping the region between the first conductor, second insulator and third conductor and the second conductor, third insulator and fourth conductor; a fifth insulator disposed inside the first opening and disposed on the oxide semiconductor; a fifth conductor disposed on the fifth insulator inside the first opening; a sixth conductor which is disposed inside a second opening formed in the fourth insulator, and which is in contact with the top surface of the third conductor; and a seventh conductor which is disposed inside a third opening formed in the fourth insulator, the third insulator and the fourth conductor, and which is in contact with the top surface of the second conductor. The height of the first insulator is greater than the width of the first insulator.
H10B 12/00 - Dynamic random access memory [DRAM] devices
H01L 21/336 - Field-effect transistors with an insulated gate
H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
H01L 27/04 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
H10B 41/70 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
Provided is a storage device which can be micro-fabricated or highly integrated. The storage device includes a memory cell, a first insulator, and a second insulator. The memory cell includes a capacitor element and a transistor on the capacitor element. The capacitor element includes a second conductor, a third insulator on the second conductor, and a third conductor on the third insulator. A portion of the second conductor, a portion of the third insulator, and a portion of the third conductor are disposed in an opening part provided to the first insulator. The transistor includes the third conductor, a fourth conductor on the second insulator, an oxide semiconductor, a fourth insulator on the oxide semiconductor, and a fifth conductor on the fourth insulator. A portion of the oxide semiconductor is disposed in an opening part provided to the second insulator and the fourth conductor. The oxide semiconductor has a region in contact with the upper surface of the third conductor, a region in contact with a side surface of the fourth conductor, and a region in contact with a portion of the upper surface of the fourth conductor. The oxide semiconductor has a lamination structure.
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 41/70 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
H01L 27/04 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 21/336 - Field-effect transistors with an insulated gate
H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
Provided is a novel semiconductor device. A vertical channel transistor is provided overlapping a capacitive element. A ferroelectric body is used as a dielectric layer of the capacitive element. It is preferable that the ferroelectric body contains hafnium, zirconium, or at least one element that is selected from among group 13 to 15 elements. Using an oxide semiconductor for a semiconductor layer of the vertical channel transistor makes it possible to raise the dielectric breakdown voltage between the source and drain and to reduce the channel length.
H10B 53/30 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
H01L 27/04 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H10B 53/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
Provided is a storage device which can be micro-fabricated or highly integrated. This storage device comprises a memory cell and a first insulator. The memory cell comprises a capacitive element and a transistor disposed on the capacitive element. The capacitive element comprises a first conductor, a second insulator disposed on the first conductor, and a second conductor disposed on the second insulator. The first insulator is disposed on the second conductor. The transistor comprises the second conductor, a third conductor disposed on the first insulator, an oxide semiconductor, a third insulator disposed on the oxide semiconductor, and a fourth conductor disposed on the third insulator. An opening part reaching the second conductor is formed in the first insulator and the third conductor. A portion of the oxide semiconductor is disposed in the opening part. The oxide semiconductor comprises a region in contact with an upper surface of the second conductor, a region in contact with a side surface of the third conductor, and a region in contact with a portion of the upper surface of the third conductor. An angle formed by the side surface of the first insulator at the opening part and the upper surface of the first conductor is 45 degrees to less than 90 degrees.
H10B 12/00 - Dynamic random access memory [DRAM] devices
H01L 21/205 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth using reduction or decomposition of a gaseous compound yielding a solid condensate, i.e. chemical deposition
H01L 21/316 - Inorganic layers composed of oxides or glassy oxides or oxide-based glass
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
Provided is a semiconductor having a small occupied area. This semiconductor device has a first conductive layer, a second conductive layer on the first conductive layer, a first insulating layer on the second conductive layer, a semiconductor layer and a third conductive layer on the first insulating layer, a second insulating layer on the semiconductor layer and the third conductive layer, and a fourth conductive layer on the second insulating layer. At least a portion of the second conductive layer is in contact with the upper surface of the first conductive layer; the semiconductor layer is in contact with the upper surface of the first conductive layer, the side surface of the second conductive layer, the third conductive layer, and the side surface of the first insulating layer; and the fourth conductive layer overlaps the semiconductor layer with the second insulating layer interposed therebetween.
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
The present invention provides a semiconductor device which achieves both low power consumption and high performance. This semiconductor device comprises first and second transistors, and a first insulating layer. The first transistor comprises first to third conductive layers, a first semiconductor layer, and a second insulating layer. The first insulating layer is held between the first conductive layer and the second conductive layer. The first insulating layer and the second conductive layer each have an opening that reaches the first conductive layer. The first semiconductor layer is in contact with the upper surface of the first conductive layer, the lateral surface of the first insulating layer and the lateral surface of the second conductive layer within the openings. The first semiconductor layer has a region which overlaps with the third conductive layer, with the second insulating layer being interposed therebetween. The second transistor comprises a second semiconductor layer, second and third insulating layers, and a fourth conductive layer. The ends of the second semiconductor layer coincide or generally coincide with the ends of the third insulating layer. The second semiconductor layer has a region which overlaps with the fourth conductive layer, with the second insulating layer and the third insulating layer being interposed therebetween.
G09F 9/30 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
H01L 21/336 - Field-effect transistors with an insulated gate
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
The present invention provides a novel computation processing device. The present invention comprises a first current generation unit, a second current generation unit, a third current generation unit, and a multiply-accumulate computation unit. The first current generation unit has a function for outputting a first current amount that corresponds to first data, and a second current amount that corresponds to second data. The second current generation unit has a function for outputting a third current amount that corresponds to third data. The third current generation unit has a function for outputting a fourth current amount that corresponds to fourth data. The multiply-accumulate computation unit has a function for outputting a current amount that corresponds to a sum obtained by adding together the product of the first and third current amounts and the product of the second and fourth current amounts. The first data and/or the second data is zero.
Provided is a low-cost touch panel. This touch panel comprises a transistor, a detection element, an interlayer insulation layer, a connection electrode, and conductive particles, and the detection element has a pair of electrodes. The interlayer insulation layer has an opening that reaches a source electrode, a drain electrode, or a gate electrode of the transistor. The connection electrode is provided so as to have a region located within the opening. One of the pair of electrodes of the detection element is provided so as to have a region overlapping the connection electrode, and the connection electrode and the one of the pair of electrodes of the detection element are electrically connected via the conductive particles. The conductive particles are provided between the connection electrode and the one of the pair of electrodes of the detection element so as to have a region located within the opening. Therefore, the connection electrode and the one of the pair of electrodes of the detection element are electrically connected via the conductive particles.
G09F 9/00 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
G09F 9/30 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
H05B 33/10 - Apparatus or processes specially adapted to the manufacture of electroluminescent light sources
H05B 33/12 - Light sources with substantially two-dimensional radiating surfaces
H10K 50/10 - OLEDs or polymer light-emitting diodes [PLED]
H05B 33/22 - Light sources with substantially two-dimensional radiating surfaces characterised by the chemical or physical composition or the arrangement of auxiliary dielectric or reflective layers
H10K 59/00 - Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group
33.
SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE
The present invention provides a semiconductor device which comprises a transistor of a very small size. This comprises a first and a second transistor. The first transistor has first to third electrically conductive layers, an insulation layer, and first and second semiconductor layers. The second electrically conductive layer on the first electrically conductive layer has an opening overlapping the first electrically conductive layer. The first semiconductor layer is in contact with the top surface of the first electrically conductive layer as well as the top surface and side surface of the second electrically conductive layer. The second semiconductor layer is in contact with the top surface of the first semiconductor layer. The insulation layer is in contact with the top surface of the second semiconductor layer. The third electrically conductive layer overlaps with the first and second semiconductor layers inside the opening. The second transistor has the insulation layer, a third semiconductor layer, and fourth to sixth electrically conductive layers. The fourth and fifth electrically conductive layers are in contact with different top surfaces of the third semiconductor layer. The insulation layer is in contact with the top surface of the third semiconductor layer between the fourth and fifth electrically conductive layers. The sixth electrically conductive layer is in contact with the top surface of the insulation layer. The first and second semiconductor layers have respectively different materials, and the second and third semiconductor layers have the same materials.
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
G09F 9/00 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
G09F 9/30 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
H01L 21/336 - Field-effect transistors with an insulated gate
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
With respect to a secondary battery, since a separator is expensive and requires cumbersome handling, a reduction in the production cost or simplification of the production process has been awaited. One embodiment of the present invention provides a secondary battery which has a novel configuration. By arranging a polymer-containing layer, which has a carboxy group, between a positive electrode active material layer and a negative electrode active material layer in a secondary battery, a short circuit between a positive electrode and a negative electrode is prevented. In addition, the polymer-containing layer has ion permeability that enables permeation of lithium ions, and prevents a short circuit due to dendrite. The polymer-containing layer does not have pores, but has ion permeability.
The present invention provides a novel signal output circuit. The present invention provides a shift register which has a signal output circuit that comprises a vertical channel transistor. The present invention enables the achievement of a signal output circuit which occupies a small area by using one of the gate-source parasitic capacitance and the gate-drain parasitic capacitance of the vertical channel transistor, the one having a higher capacitance, for a bootstrap capacitor. The present invention is capable of shortening the channel length by using an oxide semiconductor for a semiconductor layer of the vertical channel transistor, thereby enhancing the withstand voltage between the source and the drain. The present invention also enables a stable operation in a high temperature environment.
G09F 9/00 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
G09F 9/30 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
G09G 3/20 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
G09G 3/3225 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
G11C 19/28 - Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
H01L 21/336 - Field-effect transistors with an insulated gate
H01L 21/82 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H03K 19/094 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
Provided is a display device having a touch sensor and a driver for driving the touch sensor that are built in. This display device has a touch panel function, and an electrode of the touch sensor is electrically connected to a first drive circuit monolithically formed on a substrate on which a pixel circuit is formed. A transistor having a metallic oxide in a semiconductor layer can be used in the first drive circuit. The transistor of the first drive circuit has a structure that can be easily downsized and can be operated at high speed. Consequently, an area occupied by the circuit can be reduced, thereby contributing to the reduction of a bezel width.
G09F 9/00 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
G09F 9/30 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
G06F 3/041 - Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
G06F 3/044 - Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
Provided is a semiconductor device having a novel configuration. This semiconductor device comprises an arithmetic logic unit, bus wiring, and a storage device. The storage device comprises a first element layer having a plurality of readout circuits, and a second element layer having a plurality of cell arrays. Each of the readout circuits has a sense amplifier. Each of the cell arrays has a memory cell. The second element layer is stacked on top of the first element layer. The memory cell and the sense amplifier are electrically connected through a bit line. The storage device is electrically connected to the arithmetic logic unit through the bus wiring. Data retained in one of the plurality of cell arrays is output onto the bus wiring through one of the plurality of readout circuits. The data that is output onto the bus wiring is output with a bit width that is a multiple of eight bits.
Provided is a semiconductor device that demonstrates fast access speed. This semiconductor device has a first storage layer, a second storage layer, and a circuit layer. The first storage layer has a plurality of first storage circuits, the second storage layer has a second storage circuit, and the circuit layer has a selector. The selector has a plurality of input terminals and an output terminal. The first storage layer is positioned below the circuit layer, and the second storage layer is positioned above the circuit layer. The plurality of first storage circuits are electrically connected to the plurality of input terminals, and the second storage circuit is electrically connected to the output terminal. The selector has a function of enabling conduction between one selected from the plurality of input terminals, and the output terminal of the selector. The semiconductor device has a function for writing data read out from the second storage circuit to the first storage circuit via the selector.
H10B 12/00 - Dynamic random access memory [DRAM] devices
G11C 5/04 - Supports for storage elements; Mounting or fixing of storage elements on such supports
G11C 11/405 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with three charge-transfer gates, e.g. MOS transistors, per cell
H01L 21/336 - Field-effect transistors with an insulated gate
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
H10B 41/70 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
H10B 99/00 - Subject matter not provided for in other groups of this subclass
H10N 70/00 - Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
H10N 99/00 - Subject matter not provided for in other groups of this subclass
The present invention provides a semiconductor device which is capable of achieving miniaturization or high integration. A semiconductor device according to the present invention comprises: a first conductor and a second conductor, which are arranged to be separate from each other on an oxide; a third conductor which is in contact with a part of the upper surface of the first conductor; a fourth conductor which is in contact with a part of the upper surface of the second conductor; a first insulator which is arranged on the third conductor and the fourth conductor, and has an opening between the third conductor and the fourth conductor; a second insulator which is arranged within the opening of the first insulator, and is in contact with another part of the upper surface of the first conductor, another part of the upper surface of the second conductor, a lateral surface of the third conductor, and a lateral surface of the fourth conductor; a third insulator which is in contact with the upper surface of the oxide, the first conductor, the second conductor, and a lateral surface of the second insulator; and a fifth conductor which is arranged on the third insulator. With respect to this semiconductor device, the distance between the first conductor and the second conductor is shorter than the distance between the third conductor and the fourth conductor; the second insulator comprises a first layer and a second layer that is arranged on the first layer; the first layer comprises a nitride insulator; and the second layer comprises an oxide insulator.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 27/00 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 41/70 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
The present invention provides a secondary battery capable of operating below the freezing point. Provided is a secondary battery that comprises an electrolyte and a positive electrode active material, wherein the electrolyte includes a first ionic liquid, a second ionic liquid, and a lithium salt, the amount of the second ionic liquid added is 5-25 percent by weight and preferably 10-20 percent by weight relative to the total weight of the first ionic liquid, the second ionic liquid and the lithium salt, and the positive electrode active material has a layered rock salt-type crystalline structure. The second ionic liquid preferably has 1,3-diallyl imidazolium cations.
H01M 4/505 - Selection of substances as active materials, active masses, active liquids of inorganic oxides or hydroxides of manganese of mixed oxides or hydroxides containing manganese for inserting or intercalating light metals, e.g. LiMn2O4 or LiMn2OxFy
H01M 4/525 - Selection of substances as active materials, active masses, active liquids of inorganic oxides or hydroxides of nickel, cobalt or iron of mixed oxides or hydroxides containing iron, cobalt or nickel for inserting or intercalating light metals, e.g. LiNiO2, LiCoO2 or LiCoOxFy
H01M 10/0567 - Liquid materials characterised by the additives
H01M 10/0569 - Liquid materials characterised by the solvents
The present invention provides: a positive electrode active material for which a decrease in discharge capacity during charge and discharge cycles is suppressed; and a battery which uses said positive electrode active material. Alternatively, the present invention provides a battery having high safety. This battery comprises a positive electrode. The positive electrode has a positive electrode current collector and a positive electrode active material layer. The positive electrode current collector has a metal foil, such as a stainless foil, and a covering layer for at least partially covering the surface of the metal foil. The covering layer contains aluminum. The positive electrode active material included in the positive electrode active material layer contains a lithium cobalt oxide containing nickel and magnesium. The detected amount of nickel in a surface layer part of the positive electrode active material is greater than the detected amount of nickel in the inside of the positive electrode active material. The detected amount of magnesium in the surface layer part of the positive electrode active material is greater than the detected amount of magnesium in the inside of the positive electrode active material. The surface layer part of the positive electrode active material has a region where the distribution of nickel and the distribution of magnesium overlap each other.
H01M 4/13 - Electrodes for accumulators with non-aqueous electrolyte, e.g. for lithium-accumulators; Processes of manufacture thereof
H01M 4/36 - Selection of substances as active materials, active masses, active liquids
H01M 4/525 - Selection of substances as active materials, active masses, active liquids of inorganic oxides or hydroxides of nickel, cobalt or iron of mixed oxides or hydroxides containing iron, cobalt or nickel for inserting or intercalating light metals, e.g. LiNiO2, LiCoO2 or LiCoOxFy
The present invention provides a document viewing device for contributing to smooth execution of tasks. The document viewing device comprises an input unit, a registration unit, a display control unit, and a display unit. The input unit has a feature of receiving a document specified by a user. The registration unit has a feature of registering a comment in an assigned comment section, which is a part of the document. The display control unit has a feature of causing the display unit to display a comment such that the user can identify whether a person who has registered the comment is the user or another user different from the user.
G06F 40/169 - Annotation, e.g. comment data or footnotes
G06F 3/0481 - Interaction techniques based on graphical user interfaces [GUI] based on specific properties of the displayed interaction object or a metaphor-based environment, e.g. interaction with desktop elements like windows or icons, or assisted by a cursor's changing behaviour or appearance
Provided is an electronic apparatus with reduced stray light. The electronic apparatus includes a display panel and an optical device. The optical device has a function of partially reducing the brightness of light which is emitted by the display panel. For the optical device, a half mirror, a dimmer filter, or the like, can be used, the transmittance of which continuously decreases outwards from the inside thereof. By using such electronic apparatus, stray light, which tends to occur around a lens, can be reduced, and the visibility of an image displayed on the display panel can therefore be improved.
Provided is a display device that drives at high speed. This display device has pixels, a scanning line driving circuit, and a power supply circuit. The pixels each have first and second transistors, and the second transistor is provided with a semiconductor layer inside an opening formed in an interlayer insulating layer on a substrate. A first conductive layer that functions as a gate electrode of the first transistor has a region that extends in a first direction, and is electrically connected to the scanning line driving circuit. A second conductive layer that functions as a source electrode or a drain electrode of the second transistor is provided below the opening. The second conductive layer has a region that extends in a second direction perpendicular to the first direction, and is electrically connected to the power supply circuit. The first conductive layer and the second conductive layer have respective regions that overlap each other with the interlayer insulating layer interposed therebetween.
G09F 9/30 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
G02F 1/1368 - Active matrix addressed cells in which the switching element is a three-electrode device
The present invention provides a semiconductor device that achieves both low power consumption and high performance. Provided is a semiconductor device having first and second transistors. The first transistor has a first conductive layer, a first insulation layer on the first conductive layer, a second conductive layer on the first insulation layer, a second insulation layer on the second conductive layer, a third insulation layer on the second insulation layer, a third conductive layer on the third insulation layer, and a first semiconductor layer. The second conductive layer has a first opening that reaches the first insulation layer in a region overlapping with the first conductive layer. The first insulation layer to third insulation layer and the third conductive layer have a second opening that reaches the first conductive layer in a region overlapping with the first opening. The first semiconductor layer is in contact with an upper surface of the first conductive layer, a side surface of the first insulation layer, a side surface of the second insulation layer, a side surface of the third insulation layer, and an upper surface and a side surface of the third conductive layer. The second transistor has a fourth conductive layer, a first insulation layer to a third insulation layer on the fourth conductive layer, and a second semiconductor layer on the third insulation layer.
Provided is a transistor of minute size. Said transistor has a first conductive layer, a second conductive layer, a third conductive layer, a first insulating layer, a second insulating layer, and a semiconductor layer. The first insulating layer is provided on the first conductive layer and has an opening reaching the first conductive layer and a recessed portion surrounding the opening in plan view. The second conductive layer is provided so as to cover the inner wall of the recessed portion and has a region facing the semiconductor layer via the first insulating layer. The semiconductor layer is provided so as to have a region overlapping the opening and makes contact with a top surface of the first conductive layer, a side surface of the first insulating layer, a side surface of the second conductive layer, and a top surface of the second conductive layer. The second insulating layer is provided so as to make contact with a top surface of the semiconductor layer. The third conductive layer is provided on the second insulating layer so as to cover the inner wall of the opening, and has a region facing the semiconductor layer via the second insulating layer.
Provided is a semiconductor device with a novel configuration. This semiconductor device has: a first computing device that has registers, and a second computing device that has memory circuits, layer selecting circuits, and a computing circuit. The first computing device and the second computing device are provided to an element layer that is formed by stacking a plurality of second element layers on a first element layer. The registers each have a flip-flop and a data holding circuit. The flip-flops and the computing circuit are provided to the first element layer. The data holding circuits are provided to each layer of the plurality of second element layers on the first element layer provided with the flip-flops. The memory circuits and the layer selecting circuits are provided to each layer of the plurality of second layers on the first element layer provided with the computing circuit.
G11C 5/04 - Supports for storage elements; Mounting or fixing of storage elements on such supports
G11C 14/00 - Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
48.
METHOD FOR PRODUCING POSITIVE ELECTRODE ACTIVE MATERIAL, AND POSITIVE ELECTRODE ACTIVE MATERIAL
Provided is a positive electrode active material which achieves both high capacity and safety. This method for producing a positive electrode active material involves: forming a mixed solution in which a cobalt compound and a nickel compound are dissolved; reacting the mixed solution with an alkaline aqueous solution to obtain a suspension in which a cobalt-nickel hydroxide is precipitated; performing a first suction filtration using water; and performing a second suction filtration using an organic solvent after the first suction filtration, wherein in the cobalt-nickel hydroxide, an atomic number ratio of nickel to the sum of an atomic number ratio of cobalt and the atomic number ratio of nickel is 0 to 0.01 (exclusive of 0).
H01M 4/525 - Selection of substances as active materials, active masses, active liquids of inorganic oxides or hydroxides of nickel, cobalt or iron of mixed oxides or hydroxides containing iron, cobalt or nickel for inserting or intercalating light metals, e.g. LiNiO2, LiCoO2 or LiCoOxFy
One embodiment of the present invention provides a positive electrode active material having little deterioration. The positive electrode active material is produced by: obtaining a nickel compound that contains nickel, cobalt and manganese through a coprecipitation process; subsequently, mixing a lithium compound, an aluminum compound (or a magnesium compound), and the nickel compound, heating the mixture at a first heating temperature, and pulverizing or crushing the mixture; subsequently, further mixing a lithium compound, heating the mixture at a second temperature which is higher than the first temperature, and pulverizing or crushing the mixture; and subsequently, subjecting the mixture to a third heating treatment.
H01M 4/525 - Selection of substances as active materials, active masses, active liquids of inorganic oxides or hydroxides of nickel, cobalt or iron of mixed oxides or hydroxides containing iron, cobalt or nickel for inserting or intercalating light metals, e.g. LiNiO2, LiCoO2 or LiCoOxFy
H01M 4/505 - Selection of substances as active materials, active masses, active liquids of inorganic oxides or hydroxides of manganese of mixed oxides or hydroxides containing manganese for inserting or intercalating light metals, e.g. LiMn2O4 or LiMn2OxFy
The present invention provides a charging method according to the state of a positive electrode when charging starts. The present invention also improves battery charging characteristics. The method for charging a battery having a positive electrode active substance expressed by LixMO2 for a positive electrode determines the necessity of a first charging from the value of x at a time point when starting to charge the battery, where M is one or more selected from Co, Ni, Mn, and Al. When it is determined that the first charging is necessary, a second charging and a third charging are sequentially performed after the first charging is performed. When it is determined that the first charging is unnecessary, the second charging and the third charging are sequentially performed. The first charging is performed with a current value of 1C to 5C, inclusive, and a charging time of 10 seconds to 30 seconds, inclusive. The second charging is a constant current charging, and the third charging is a constant voltage charging.
Provided is a novel energy storage system. This system comprises a secondary battery and a differential stage. The differential stage is provided with a register; the differential stage functions to convert a first voltage of the secondary battery into first voltage data by analog-to-digital conversion; the differential stage functions to measure time required for the first voltage to change by a first voltage value; the register functions to hold second voltage data that is higher than the first voltage data by a data value that is equivalent to the first voltage value; and the differential stage functions to halt power supply to the register during an interval until the first voltage changes by the first voltage value.
H01M 4/36 - Selection of substances as active materials, active masses, active liquids
H01M 4/525 - Selection of substances as active materials, active masses, active liquids of inorganic oxides or hydroxides of nickel, cobalt or iron of mixed oxides or hydroxides containing iron, cobalt or nickel for inserting or intercalating light metals, e.g. LiNiO2, LiCoO2 or LiCoOxFy
H01M 10/48 - Accumulators combined with arrangements for measuring, testing or indicating the condition of cells, e.g. the level or density of the electrolyte
H02J 7/02 - Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries for charging batteries from ac mains by converters
52.
SECONDARY BATTERY AND METHOD FOR PRODUCING POSITIVE ELECTRODE ACTIVE MATERIAL
The present invention provides a novel positive electrode active material. The present invention also provides a highly safe secondary battery. This lithium ion secondary battery has a positive electrode, wherein the positive electrode has a positive electrode active material, the positive electrode active material having nickel, cobalt, manganese, oxygen, and additive elements. The additive elements are at least one or two or more selected from fluorine, aluminum, magnesium, titanium, and calcium. The positive electrode active material comprises a layer having a large amount of additive elements, and an interior, wherein the layer having a large amount of additive elements has at least one selected from among additive elements the amount of which is larger than in the interior.
H01M 4/525 - Selection of substances as active materials, active masses, active liquids of inorganic oxides or hydroxides of nickel, cobalt or iron of mixed oxides or hydroxides containing iron, cobalt or nickel for inserting or intercalating light metals, e.g. LiNiO2, LiCoO2 or LiCoOxFy
H01M 4/36 - Selection of substances as active materials, active masses, active liquids
H01M 4/505 - Selection of substances as active materials, active masses, active liquids of inorganic oxides or hydroxides of manganese of mixed oxides or hydroxides containing manganese for inserting or intercalating light metals, e.g. LiMn2O4 or LiMn2OxFy
Provided is a charging management system which is for a secondary battery and has a new configuration. The present invention comprises: a secondary battery having a first battery cell and a second battery cell that are connected in series; a current measurement circuit having a function of measuring, at the time of charging the secondary battery, current flowing in the first battery cell and the second battery cell; a voltage measurement circuit having a function of measuring, at the time of charging the secondary battery, respective voltages in the first battery cell and the second battery cell; and a control circuit having a function of performing control for matching charging rates of the first battery cell and the second battery cell. The control circuit has a function of calculating data sets indicative of the respective battery characteristics for the first battery cell and the second battery cell, in accordance with data of the measured current and data of the measured voltages. The control for matching the charging rates of the first battery cell and the second battery cell is performed by controlling the charging rates through matching maximal values of the data sets indicative of the battery characteristics.
H02J 7/02 - Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries for charging batteries from ac mains by converters
G01R 31/382 - Arrangements for monitoring battery or accumulator variables, e.g. SoC
G01R 31/385 - Arrangements for measuring battery or accumulator variables
H01M 10/48 - Accumulators combined with arrangements for measuring, testing or indicating the condition of cells, e.g. the level or density of the electrolyte
Provided is a secondary battery which achieves both high safety and reduction in charging/discharging time. A secondary battery according to the present invention is of a winding type. In the secondary battery, a positive electrode current collector of a positive electrode has a first tab and a second tab, and a negative electrode current collector of a negative electrode has a third tab and a fourth tab. The first tab is located at a portion closer to the center of the winding as compared with the second tab, and the third tab is located at a portion closer to the center of the winding as compared with the fourth tab. The first tab and the second tab are joined at a first joining part, and the third tab and the fourth tab are joined at a second joining part. A positive electrode active material has a first region, and a second region located on the surface side of the positive electrode active material. The first region contains lithium, cobalt, and oxygen. The second region contains lithium, cobalt, magnesium, and oxygen.
H01M 10/0587 - Construction or manufacture of accumulators having only wound construction elements, i.e. wound positive electrodes, wound negative electrodes and wound separators
H01G 11/26 - Electrodes characterised by their structure, e.g. multi-layered, porosity or surface features
H01G 11/70 - Current collectors characterised by their structure
H01G 11/74 - Terminals, e.g. extensions of current collectors
H01M 4/13 - Electrodes for accumulators with non-aqueous electrolyte, e.g. for lithium-accumulators; Processes of manufacture thereof
H01M 4/131 - Electrodes based on mixed oxides or hydroxides, or on mixtures of oxides or hydroxides, e.g. LiCoOx
H01M 4/525 - Selection of substances as active materials, active masses, active liquids of inorganic oxides or hydroxides of nickel, cobalt or iron of mixed oxides or hydroxides containing iron, cobalt or nickel for inserting or intercalating light metals, e.g. LiNiO2, LiCoO2 or LiCoOxFy
Provided is a positive electrode active material with a suppressed decrease in discharge capacity in a charge-discharge cycle. Alternatively, provided is a highly safe secondary battery. The secondary battery comprises a positive electrode having the positive electrode active material, a negative electrode, and an electrolyte. The positive electrode active material is produced by mixing a first composite oxide containing lithium and cobalt, a magnesium source, and a fluoride to form a mixture, heating the mixture at a temperature of 650-1130℃ to form a second composite oxide, and then cooling the second composite oxide at a cooling rate higher than 250℃/h.
H01M 4/525 - Selection of substances as active materials, active masses, active liquids of inorganic oxides or hydroxides of nickel, cobalt or iron of mixed oxides or hydroxides containing iron, cobalt or nickel for inserting or intercalating light metals, e.g. LiNiO2, LiCoO2 or LiCoOxFy
Provided is a positive electrode active material that is prevented from the decrease in a discharge capacity in a charge-discharge cycle. This positive electrode active material comprises cobalt, nickel and oxygen, in which the content of nickel relative to the total amount of cobalt and nickel, i.e., Ni/(Co+Ni), is more than 0.175 and equal to or less than 0.215, and the positive electrode active material has diffraction peaks at least two of 2θ = 18.526±0.1°, 2θ = 37.391±0.1°, 2θ = 37.628±0.1°, 2θ = 39.015±0.1°, 2θ = 44.947±0.1°, 2θ = 49.029±0.1° and 2θ = 58.857±0.1° when the positive electrode active material is analyzed by powder X-ray diffraction using CuKα1 line in the state charged to 4.5 V (vs.Li/Li+).
H01M 4/525 - Selection of substances as active materials, active masses, active liquids of inorganic oxides or hydroxides of nickel, cobalt or iron of mixed oxides or hydroxides containing iron, cobalt or nickel for inserting or intercalating light metals, e.g. LiNiO2, LiCoO2 or LiCoOxFy
Provided are a novel material search method and a novel material search system. From among a plurality of peaks that occur in an XRD profile of an input sample, P peaks are acquired in order of greatest peak intensity. A record that includes R peak positions in order of greatest peak intensity is generated for each set of physical properties data of a plurality of known materials registered in a material database. From among a plurality of records, a record that includes peaks that match or substantially match all of the P peak positions of the sample is searched, and when a corresponding record is found, a determination is made as to whether the sample matches a known material that is registered in the material database. At least a portion of information pertaining to the known material is also outputted. Preferably, R is greater than P, and R is no more than 6 times P.
One embodiment of the present invention provides a novel positive electrode active material. Also provided is a secondary battery that is highly safe. A positive electrode active material is produced by: obtaining a nickel compound (also referred to as a precursor) that contains nickel, cobalt and manganese through a coprecipitation process; mixing a lithium compound and the nickel compound, heating the mixture at a first temperature, and pulverizing or crushing the mixture; heating the pulverized or crushed mixture at a second temperature which is higher than the first temperature, and mixing magnesium thereinto; and subjecting the resulting mixture to a third heating treatment.
H01M 4/525 - Selection of substances as active materials, active masses, active liquids of inorganic oxides or hydroxides of nickel, cobalt or iron of mixed oxides or hydroxides containing iron, cobalt or nickel for inserting or intercalating light metals, e.g. LiNiO2, LiCoO2 or LiCoOxFy
H01M 4/36 - Selection of substances as active materials, active masses, active liquids
H01M 4/505 - Selection of substances as active materials, active masses, active liquids of inorganic oxides or hydroxides of manganese of mixed oxides or hydroxides containing manganese for inserting or intercalating light metals, e.g. LiMn2O4 or LiMn2OxFy
59.
SECONDARY BATTERY, POSITIVE ELECTRODE ACTIVE MATERIAL, AND METHOD FOR PRODUCING POSITIVE ELECTRODE ACTIVE MATERIAL
Provided is a positive electrode active material which achieves both high capacity and safety. This secondary battery has a positive electrode. The positive electrode includes a positive electrode active material. The positive electrode active material contains a lithium cobalt oxide containing magnesium, nickel, and aluminum. When the positive electrode is analyzed by powder X-ray diffraction using a CuKα1 ray source at a depth of charge of 0.8 or greater, diffraction peaks are present at 2θ=19.30±0.20° and 2θ=45.55±0.10° in the positive electrode active material. The positive electrode active material has a first region including a surface parallel to the (001) plane and a second region including a surface parallel to a plane intersecting the (001) plane. The concentration of nickel in the first region is higher than the concentration of nickel in the second region.
H01M 4/525 - Selection of substances as active materials, active masses, active liquids of inorganic oxides or hydroxides of nickel, cobalt or iron of mixed oxides or hydroxides containing iron, cobalt or nickel for inserting or intercalating light metals, e.g. LiNiO2, LiCoO2 or LiCoOxFy
Provided is a semiconductor device having favorable electrical characteristics. This semiconductor device has: a first layered body; a semiconductor layer having a channel-forming region under the first layered body; and a second layered body under the semiconductor layer. The first layered body and the second layered body each have at least a first insulator and a second insulator. At such a time, the first insulator of the first layered body and the first insulator of the second layered body have regions that overlap each other with the channel-forming region therebetween, and the second insulator of the first layered body and the second insulator of the second layered body have regions that overlap each other with the first insulator of the first layered body, the channel-forming region, and the first insulator of the second layered body therebetween. Furthermore, the first insulator included in the first layered body and the first insulator included in the second layered body share a function, and the second insulator included in the first layered body and the second insulator included in the second layered body share a function.
H10B 12/00 - Dynamic random access memory [DRAM] devices
H01L 21/3205 - Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layers; After-treatment of these layers
H01L 21/336 - Field-effect transistors with an insulated gate
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 27/04 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
H10B 41/70 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
H10B 53/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
H10B 53/30 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
Provided is a semiconductor device having a novel configuration. This semiconductor device comprises a first element layer, and a plurality of second element layers on each of which a temperature detection circuit, a voltage generation circuit, and a memory cell are provided. The plurality of second element layers are stacked on the first element layer. The memory cell has a transistor in which a semiconductor layer having a channel forming region contains an oxide semiconductor. The transistor has a back gate. The voltage generation circuit provided on each layer has a feature of generating a back gate voltage to be supplied to the back gate of the transistor of the memory cell provided on the same layer. The temperature detection circuit has a feature of controlling the back gate voltage according to a detected temperature. Among the second element layers, the back gate voltage to be supplied to the transistor of a second element layer provided on an upper layer is larger than the back gate voltage to be supplied to the transistor of a second element layer provided on a lower layer.
G06F 12/00 - Accessing, addressing or allocating within memory systems or architectures
G11C 5/02 - Disposition of storage elements, e.g. in the form of a matrix array
G11C 5/04 - Supports for storage elements; Mounting or fixing of storage elements on such supports
G11C 7/04 - Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
Provided is a semiconductor device having a small circuit scale and reduced power consumption. The semiconductor device comprises: a first computation unit that performs digital computation; and a second computation unit that performs analog computation. In the computation of a convolutional neural network, the computation of a convolutional layer is executed by the first computation unit, and the computation of a fully connected layer is executed by the second computation unit. Since the convolutional layer often uses the same filter value repeatedly, the first computation unit is configured to have one input of the same filter value and a plurality of inputs of data to be subjected to convolution processing, and simultaneously execute a plurality of product-sum computations. In addition, since the fully connected layer requires a weighting factor of the product of the number of input data and the number of output data, the second computation unit is configured to store a weighting coefficient of each computation cell in the computation cells arranged in a matrix, and transmit input data in each row direction to output output data from each column direction.
Provided is a novel semiconductor device. In the present invention, a first circuit is electrically connected to a second circuit via a first wire, the first circuit is electrically connected to a fourth circuit via each of a third wire and a fourth wire, the second circuit is electrically connected to a third circuit via a fifth wire, the first circuit has a function for achieving a conductive state or non-conductive state between the first wire, a second wire, the third wire, and the fourth wire, the third circuit has a function for holding potential corresponding to first data, the second circuit has a function for applying the potential corresponding to the first data from the first wire to the fifth wire, a function for holding potential corresponding to second data, and a function for amplifying a change in potential of the fifth wire and outputting the change to the first wire, and the fourth circuit has a function for outputting the potential corresponding to the first data or the potential corresponding to the second data depending on a potential difference between the third wire and the fourth wire.
G11C 7/12 - Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
The present invention provides a lithium ion secondary battery having excellent discharge characteristics even in a low-temperature environment. The lithium ion secondary battery comprises a positive electrode, a negative electrode, and an electrolyte. The positive electrode has a lithium cobalt oxide having a median diameter (D50) of 1-12 µm inclusive. The lithium cobalt oxide has magnesium on the surface layer. The negative electrode has graphite particles, silicon particles, and a polymer having a carboxy group. The electrolyte has a mixed solvent of a fluorinated cyclic carbonate and a fluorinated chain carbonate.
H01M 4/133 - Electrodes based on carbonaceous material, e.g. graphite-intercalation compounds or CFx
H01M 4/134 - Electrodes based on metals, Si or alloys
H01M 4/36 - Selection of substances as active materials, active masses, active liquids
H01M 4/38 - Selection of substances as active materials, active masses, active liquids of elements or alloys
H01M 4/525 - Selection of substances as active materials, active masses, active liquids of inorganic oxides or hydroxides of nickel, cobalt or iron of mixed oxides or hydroxides containing iron, cobalt or nickel for inserting or intercalating light metals, e.g. LiNiO2, LiCoO2 or LiCoOxFy
H01M 4/587 - Carbonaceous material, e.g. graphite-intercalation compounds or CFx for inserting or intercalating light metals
H01M 4/62 - Selection of inactive substances as ingredients for active masses, e.g. binders, fillers
H01M 10/0569 - Liquid materials characterised by the solvents
Provided is a lithium-ion secondary battery excelling in a cycle characteristic and in safety. Provided is a lithium-ion secondary battery having a positive electrode, a negative electrode, and an electrolyte, wherein the positive electrode has a lithium cobalt oxide with a median diameter (D50) of greater than 12 μm, the lithium cobalt oxide has magnesium in a surface layer portion thereof, and the negative electrode has graphite particles, silicon particles, and a polymer having a carboxy group.
H01M 4/36 - Selection of substances as active materials, active masses, active liquids
H01M 4/38 - Selection of substances as active materials, active masses, active liquids of elements or alloys
H01M 4/525 - Selection of substances as active materials, active masses, active liquids of inorganic oxides or hydroxides of nickel, cobalt or iron of mixed oxides or hydroxides containing iron, cobalt or nickel for inserting or intercalating light metals, e.g. LiNiO2, LiCoO2 or LiCoOxFy
H01M 4/587 - Carbonaceous material, e.g. graphite-intercalation compounds or CFx for inserting or intercalating light metals
H01M 4/62 - Selection of inactive substances as ingredients for active masses, e.g. binders, fillers
The present invention provides: a positive electrode active material for which a decrease in discharge capacity during charge and discharge cycles is reduced; and a secondary battery which uses this positive electrode active material. Alternatively, provided is a secondary battery having high safety. In this lithium ion secondary battery with a positive electrode: the positive electrode has a collector and a positive electrode active material layer; one surface of the collector has a first recessed portion, a second recessed portion, and a first portion located between the first recessed portion and the second recessed portion; the positive electrode active material layer is provided in the first recessed portion and the second recessed portion; and in a cross sectional view of the positive electrode, when the one surface of the collector faces upward, then with respect to the lowermost portion of the first recessed portion, the height of the uppermost portion of the positive electrode active material layer is substantially level with the height of the uppermost portion of the first portion.
H01M 4/131 - Electrodes based on mixed oxides or hydroxides, or on mixtures of oxides or hydroxides, e.g. LiCoOx
H01M 4/525 - Selection of substances as active materials, active masses, active liquids of inorganic oxides or hydroxides of nickel, cobalt or iron of mixed oxides or hydroxides containing iron, cobalt or nickel for inserting or intercalating light metals, e.g. LiNiO2, LiCoO2 or LiCoOxFy
H01M 4/62 - Selection of inactive substances as ingredients for active masses, e.g. binders, fillers
H01M 4/70 - Carriers or collectors characterised by shape or form
Provided are: a positive electrode active material by which a decrease in discharge capacity during charge and discharge cycles is suppressed; and a secondary battery using the same. Also provided is a secondary battery having high safety. The secondary battery includes: a positive electrode having a positive electrode active material; a negative electrode; and an electrolyte. The positive electrode active material is formed through a first step for mixing a composite oxide containing lithium, cobalt, and oxygen, a magnesium source and a nickel source to form a mixture, and a second step for heating the mixture, wherein the nickel source is a nickel fluoride, and in the second step, magnesium, nickel, and fluorine are segregated on a surface of the composite oxide.
H01M 4/525 - Selection of substances as active materials, active masses, active liquids of inorganic oxides or hydroxides of nickel, cobalt or iron of mixed oxides or hydroxides containing iron, cobalt or nickel for inserting or intercalating light metals, e.g. LiNiO2, LiCoO2 or LiCoOxFy
This semiconductor device (200) includes: an oxide (230) on a substrate; a first conductor (242a1) and a second conductor (242b1) that are on the oxide and are separated from each other; a third conductor (242a2) that is in contact with one portion of the upper surface of the first conductor; a fourth conductor (242b2) that is in contact with one portion of the upper surface of the second conductor; first insulators (271a, 271b) that are disposed on the third conductor and the fourth conductor, respectively, and have an opening overlapping a region between the third conductor and the fourth conductor; a second insulator (255) that is disposed inside the opening of the first insulators, and is in contact with the other portion of the upper surface of the first conductor, the other portion of the upper surface of the second conductor, a side surface of the third conductor, and a side surface of the fourth conductor; a third insulator (250) that is disposed inside the opening of the first insulators, and is in contact with the upper surface of the oxide, a side surface of the first conductor, a side surface of the second conductor, and a side surface of the second insulator; and a fifth conductor that, in the inside of the opening of the first insulators, is disposed on the third insulator, and that has a region overlapping the oxide with the third insulator therebetween. The distance (L2) between the first conductor and the second conductor is less than the distance (L1) between the third conductor and the fourth conductor.
H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
H01L 21/3205 - Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layers; After-treatment of these layers
H01L 21/336 - Field-effect transistors with an insulated gate
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 27/04 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
Provided are a positive electrode active material and a secondary battery using same, wherein a decrease in discharge capacity during charge/discharge cycles is suppressed. Alternatively, provided is a highly safe secondary battery. The secondary battery has a positive electrode active material which has a lithium cobalt oxide containing nickel and magnesium, wherein the amount of nickel and magnesium detected in the surface layer of the positive electrode active material is greater than the amount of nickel and magnesium detected inside the positive electrode active material, and the distribution of nickel and the distribution of magnesium overlap in the surface layer of the positive electrode active material. It is preferable that the positive electrode active material further contains fluorine, and the amount of fluorine detected in the surface layer of the positive electrode active material is greater than the amount of fluorine detected inside the positive electrode active material.
H01M 4/525 - Selection of substances as active materials, active masses, active liquids of inorganic oxides or hydroxides of nickel, cobalt or iron of mixed oxides or hydroxides containing iron, cobalt or nickel for inserting or intercalating light metals, e.g. LiNiO2, LiCoO2 or LiCoOxFy
Provided is an electronic apparatus with which it is possible to view an image with little distortion. This electronic apparatus has a display device and an optical instrument. The optical instrument has a position adjustment mechanism, and can adjust diopter. The display device is caused to display a corrected image obtained by subjecting an original image to barrel distortion in order to correct the distortion aberration of a lens. The correction amount (image size and distortion rate) of the corrected image is changed according to the position of the lens that is moved by the position adjustment mechanism. Consequently, it is possible to always correct an image to the optimum state even if the position of the lens is moved in order to adjust diopter, and thus improve the quality of the image to be viewed.
The present invention provides a semiconductor device that achieves both low power consumption and high performance. Provided is a semiconductor device comprising a first semiconductor layer, a second semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a first insulation layer, and a second insulation layer. The first insulation layer is provided on the first conductive layer. The second conductive layer is provided on the first insulation layer. The first insulation layer and the second conductive layer have an opening that reaches the first conductive layer. The first semiconductor layer makes contact with an upper surface of the first conductive layer, a side surface of the first insulation layer, and an upper surface and a side surface of the second conductive layer. The second semiconductor layer is provided on the first semiconductor layer. The second insulation layer is provided on the second semiconductor layer. The third conductive layer is provided on the second insulation layer. The conductivity of the first semiconductor layer is higher than the conductivity of the second semiconductor layer.
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H05B 45/60 - Circuit arrangements for operating LEDs comprising organic material, e.g. for operating organic light-emitting diodes [OLED] or polymer light-emitting diodes [PLED]
H10K 50/10 - OLEDs or polymer light-emitting diodes [PLED]
Provided is a semiconductor with a small occupied area. This semiconductor device has a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a first insulating layer, a second insulating layer, and a third insulating layer, wherein the first insulating layer is positioned on the first conductive layer, the second conductive layer is positioned on the first conductive layer with the first insulating layer interposed therebetween, the second insulating layer covers the upper surface and the lateral surface of the second conductive layer, the third conductive layer is positioned on the second insulating layer, the semiconductor layer is in contact with the upper surface of the first conductive layer, the lateral surface of the second insulating layer, and the third conductive layer, the third insulating layer is positioned on the semiconductor layer, and the fourth conductive layer is positioned on the semiconductor layer with the third insulating layer interposed therebetween.
G02F 1/1368 - Active matrix addressed cells in which the switching element is a three-electrode device
G09F 9/30 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H05B 45/60 - Circuit arrangements for operating LEDs comprising organic material, e.g. for operating organic light-emitting diodes [OLED] or polymer light-emitting diodes [PLED]
H10K 50/10 - OLEDs or polymer light-emitting diodes [PLED]
Provide is a battery pack which is reduced in cost. This battery pack comprises a plurality of battery cells, a heat dissipation mechanism, and a switching mechanism, wherein the switching mechanism operates the heat dissipation mechanism according to the temperature of the plurality of battery cells, and switches between a state where the battery cells and the heat dissipation mechanism are close to each other and a state where the battery cells and the heat dissipation mechanism are spaced apart from each other. The heat dissipation mechanism may preferably include a heat sink using natural cooling. The heat dissipation mechanism may further preferably include a heat transfer plate.
Provided is an electric power storage module that has a plurality of batteries connected in series and that is capable of performing control to operate a heater in accordance with a battery having the lowest battery temperature. The electric power storage module comprises: a first battery and a second battery connected in series; a heater; and a control circuit. The heater is provided near the first battery and the second battery and is electrically connected to an IC included in the control circuit. The control circuit is provided with: a first voltage sensor for detecting a voltage of the first battery; a second voltage sensor for detecting a voltage of the second battery; and an electric current sensor for detecting electric currents flowing through the first battery and the second battery. In charging of the first battery and the second battery, the heater is turned on by means of a signal from the IC when a voltage difference between a first dQ/dV peak voltage, which is calculated from the detected values by the first voltage sensor and the electric current sensor, and a second dQ/dV peak voltage, which is calculated from the detected values by the second voltage sensor and the electric current sensor, is 5 mV or more.
H01M 10/633 - Control systems - characterised by algorithms, flow charts, software details or the like
H01M 10/48 - Accumulators combined with arrangements for measuring, testing or indicating the condition of cells, e.g. the level or density of the electrolyte
H01M 10/651 - Means for temperature control structurally associated with the cells characterised by parameters specified by a numeric value or mathematical formula, e.g. ratios, sizes or concentrations
A semiconductor device having a high storage density is applied in the present invention. This semiconductor device has a first layer and a first insulating material. The first layer has a first oxide semiconductor, first to ninth conductors, and second to fifth insulating materials. The first layer is positioned on the first insulating material, and the first oxide semiconductor is positioned above the first insulating material. The first and sixth conductors are positioned on the top and lateral surfaces of the first oxide semiconductor and on the top surface of the first insulating material, respectively. Further, the second and fourth conductors are positioned on the top surface of the first oxide semiconductor. The second insulating material and the third conductor are positioned between the first conductor and the second conductor, the third insulating material and the fifth conductor are positioned between the second conductor and the fourth conductor, and the fourth insulating material and the seventh conductor are positioned between the fourth conductor and the sixth conductor. The fifth insulating material and the eighth conductor are positioned on the first conductor, in the stated order, in a region that does not overlap the first oxide. Further, the ninth conductor is positioned on the second conductor.
H10B 12/00 - Dynamic random access memory [DRAM] devices
G11C 11/405 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with three charge-transfer gates, e.g. MOS transistors, per cell
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H10B 41/70 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
H10B 99/00 - Subject matter not provided for in other groups of this subclass
Provided is a semiconductor device having a novel configuration. The present invention has: a base die having a first power supply circuit that generates a first voltage; a first die having a second power supply circuit that generates a second voltage due to having the first voltage supplied thereto; and a second die having a functional circuit that operates due to having the second voltage supplied thereto. The first die and the second die have a first through electrode and a second through electrode. The first die is provided on the base die. The second die is provided in contact with the top layer or the bottom layer of the first die. The base die and the first die are electrically connected via the first through electrode. The first die and the second die are electrically connected via the second through electrode.
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
G11C 5/04 - Supports for storage elements; Mounting or fixing of storage elements on such supports
H01L 21/336 - Field-effect transistors with an insulated gate
H01L 23/36 - Selection of materials, or shaping, to facilitate cooling or heating, e.g. heat sinks
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 99/00 - Subject matter not provided for in other groups of this subclass
Provided is a semiconductor device that has a high storage density and is highly reliable. The semiconductor device comprises first to third layers that are laminated. The first layer includes a delay signal generation circuit and a row circuit. The second layer includes a first delay addition circuit and a first memory cell, and the third layer includes a second delay addition circuit and a second memory cell. The delay signal generation circuit has a function for generating first and second delay signals representing first and second delay times, and supplying said delay signals to the first and second delay addition circuits, respectively. The row circuit has a function for generating a row selection signal for selecting the first or second memory cell to be subjected to a reading operation, and supplying said row selection signal to the first or second delay addition circuit. The first delay addition circuit has a function for supplying the row selection signal to the first memory cell after the first delay time has elapsed. The second delay addition circuit has a function for supplying the row selection signal to the second memory cell after the second delay time has elapsed. The first delay time is longer than the second delay time.
G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
G06F 12/00 - Accessing, addressing or allocating within memory systems or architectures
G06F 12/06 - Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication
G11C 5/04 - Supports for storage elements; Mounting or fixing of storage elements on such supports
G11C 7/12 - Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
G11C 7/22 - Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
H01L 21/336 - Field-effect transistors with an insulated gate
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 41/70 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
78.
SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE
Provided is a semiconductor device having a small occupancy area. The semiconductor device comprises a first conductive layer, a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, and a second conductive layer stacked in this order, and further comprises a semiconductor layer, a third conductive layer, and a fifth insulating layer. The semiconductor layer is in contact with the upper surface of the first conductive layer, a side surface of the first insulating layer, a side surface of the second insulating layer, a side surface of the third insulating layer, a side surface of the fourth insulating layer, and the second conductive layer. The fifth insulating layer is positioned on the semiconductor layer. The third conductive layer is positioned on the fifth insulating layer and overlaps the semiconductor layer with the fifth insulating layer therebetween. The first insulating layer includes a region containing more hydrogen compared to each of the second insulating layer and the fourth insulating layer. The third insulating layer contains oxygen.
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 21/336 - Field-effect transistors with an insulated gate
H10K 50/10 - OLEDs or polymer light-emitting diodes [PLED]
H05B 33/14 - Light sources with substantially two-dimensional radiating surfaces characterised by the chemical or physical composition or the arrangement of the electroluminescent material
79.
SECONDARY BATTERY, METHOD FOR PRODUCING SAME, AND VEHICLE
An aspect of the present invention provides a secondary battery that is highly safe and reliable. This secondary battery comprises a positive electrode, a negative electrode, and an electrolyte. The positive electrode has a positive electrode active material layer that includes nickel, cobalt, and manganese. The positive electrode active material layer comprises secondary particles, the secondary particles including a plurality of primary particles. Among the plurality of primary particles, a layer that includes calcium is present between two adjacent primary particles, the layer that includes calcium having a thickness of 1–10 nm. The density of the layer that includes calcium is not less than 2.0 g/cm3, but less than 3.3 g/cm3.
H01M 4/525 - Selection of substances as active materials, active masses, active liquids of inorganic oxides or hydroxides of nickel, cobalt or iron of mixed oxides or hydroxides containing iron, cobalt or nickel for inserting or intercalating light metals, e.g. LiNiO2, LiCoO2 or LiCoOxFy
H01M 4/36 - Selection of substances as active materials, active masses, active liquids
H01M 4/505 - Selection of substances as active materials, active masses, active liquids of inorganic oxides or hydroxides of manganese of mixed oxides or hydroxides containing manganese for inserting or intercalating light metals, e.g. LiMn2O4 or LiMn2OxFy
80.
POSITIVE ELECTRODE ACTIVE MATERIAL, LITHIUM-ION BATTERY, ELECTRONIC DEVICE, AND VEHICLE
The present invention provides a lithium-ion battery having exceptional charge characteristics and discharge characteristics even in low-temperature environments. A lithium-ion battery having a positive electrode active material including cobalt, oxygen, magnesium, aluminum, and nickel, the positive electrode active material having a median diameter of 1-12 µm inclusive and containing magnesium and aluminum in a surface-layer section, and the surface layer section having a region in which the magnesium is distributed toward the surface of the positive electrode active material to a greater extent than the aluminum, said region extending to 50 nm from the surface of the positive electrode active material.
H01M 4/525 - Selection of substances as active materials, active masses, active liquids of inorganic oxides or hydroxides of nickel, cobalt or iron of mixed oxides or hydroxides containing iron, cobalt or nickel for inserting or intercalating light metals, e.g. LiNiO2, LiCoO2 or LiCoOxFy
Provided is a semiconductor device that can be miniaturized or highly integrated. The semiconductor device comprises: a first conductor; a second conductor that is above the first conductor; a third conductor that contacts an upper surface of the second conductor; a fourth conductor that is above the third conductor; a fifth conductor that is above the second conductor and the fourth conductor; first and second oxides; and fourth and fifth insulators. The fourth insulator and the first oxide are disposed inside a first opening provided in the fourth conductor and the like. The first oxide has a region that is opposite from the fourth conductor with the fourth insulator therebetween, a region that contacts an upper surface of the third conductor, and a region that contacts a lower surface of the fifth conductor. The fifth insulator and the second oxide are disposed inside a second opening that is provided in the second conductor and the like. The second oxide has a region that is opposite from the second conductor with the fifth insulator therebetween, a region that contacts an upper surface of the first conductor, and a region that contacts the lower surface of the fifth conductor.
H10B 43/23 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
H10B 99/00 - Subject matter not provided for in other groups of this subclass
Provided is a semiconductor device having a small circuit size and reduced power consumption. This semiconductor device includes first to fifth circuits. Each of the first to fourth circuits has first and second cells, a sixth circuit, first and second current generation circuits, a first input terminal, and a second output terminal. The first to fourth circuits are electrically connected in a ring, and the first circuit is electrically connected to the fifth circuit. In each of the first to fourth circuits, the first cell is electrically connected to the second cell via first wiring, the first current generation circuit, and third wiring, and also electrically connected to the first input terminal and the sixth circuit via second wiring. Further, the second cell is electrically connected to a first output terminal via the second current generation circuit. It is to be noted that the first current generation circuit functions as a current mirror circuit, and the second current generation circuit functions as a function system calculation circuit. The first cell performs a product operation, and the second cell holds the operation result.
G06G 7/60 - Analogue computers for specific processes, systems, or devices, e.g. simulators for living beings, e.g. their nervous systems
G11C 5/02 - Disposition of storage elements, e.g. in the form of a matrix array
G11C 5/04 - Supports for storage elements; Mounting or fixing of storage elements on such supports
G11C 11/54 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using elements simulating biological cells, e.g. neuron
Provided is a semiconductor device capable of miniaturization or high integration. This semiconductor device includes: an oxide on a substrate; a first conductor and a second conductor that are on the oxide and are separated from each other; a third conductor contacting an upper surface of the first conductor; a fourth conductor contacting an upper surface of the second conductor; a first insulator that is on the third conductor and the fourth conductor and has an opening; a second insulator that is disposed inside the opening of the first insulator, and contacts the upper surface of the first conductor, the upper surface of the second conductor, a side surface of the third conductor, and a side surface of the fourth conductor; a third insulator on the second insulator; and a fifth conductor on the third insulator, wherein the opening of the first insulator has a region overlapping with a region between the third conductor and the fourth conductor, the third insulator contacts an upper surface of the oxide in a region between the first conductor and the second conductor, and the distance between the first conductor and the second conductor is less than the distance between the third conductor and the fourth conductor in a cross-sectional view in a channel length direction of a transistor.
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
H01L 29/41 - Electrodes characterised by their shape, relative sizes or dispositions
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 41/70 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
H10B 99/00 - Subject matter not provided for in other groups of this subclass
Provided is a semiconductor device that has a novel structure. The present invention has: a base die that has a clock signal generation circuit and a first synchronization circuit provided thereto; and a plurality of dies that are layered on the base die. The base die and the plurality of dies are electrically connected via a through electrode that is provided in the plurality of dies. Each of the plurality of dies has a second synchronization circuit. The clock signal generation circuit generates a plurality of clock signals of different frequencies. The second synchronization circuit of each of the plurality of dies operates by input of one of the clock signals of the different frequencies. The clock signals of the different frequencies are supplied to the second synchronization circuits of the plurality of dies via the through electrode.
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
G06F 1/06 - Clock generators producing several clock signals
G06F 12/00 - Accessing, addressing or allocating within memory systems or architectures
G11C 5/04 - Supports for storage elements; Mounting or fixing of storage elements on such supports
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 41/70 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
85.
LIGHT-EMITTING DEVICE AND LIGHT-EMITTING APPARATUS PRODUCTION METHOD
Provided is a light-emitting device with which it is possible to obtain a light-emitting apparatus having a low manufacturing cost while exhibiting a high definition level and high reliability. Provided is a light-emitting device comprising: a first electrode; a second electrode; and a first layer and a second layer that are located between the first and second electrodes. The first layer is located on a side closer to the first electrode as compared to the second layer. The first electrode and the first layer are independent layers in each of a plurality of the light-emitting devices. The second electrode and the second layer are continuous layers shared by the plurality of light-emitting devices. The first layer has a first electron transport layer and a light-emitting layer containing light-emitting substance. The second layer has a second electron transport layer. The first electron transport layer is located between the light-emitting layer and the second electron transport layer. The first electron transport layer contains a first compound having electron transportability and having a glass transition temperature of 110°C or higher. The second electron transport layer contains a second compound having electron transportability.
Provided is a new display apparatus that is excellent in terms of convenience, usefulness, and reliability. A display apparatus having first through fourth light-emitting devices, wherein the first light-emitting device comprises a first layer which includes a luminescent material and is interposed between a first electrode and a second electrode, and a second layer interposed between the first layer and the first electrode. The second device comprises a third layer which includes a luminescent material and is interposed between a third electrode and a fourth electrode, and a fourth layer interposed between the third layer and the third electrode, the third electrode comprising a first gap between the third electrode and the first electrode, and the fourth layer being continuous with the second layer over the first gap. The third light-emitting device comprises a fifth layer which includes a luminescent material and is interposed between a fifth electrode and a sixth electrode, and a sixth layer interposed between the fifth layer and the fifth electrode, the fifth electrode comprises a second gap between the fifth electrode and the third electrode, and the sixth layer comprises a third gap which overlaps with the second gap between the sixth layer and the fourth layer.
H10K 59/122 - Pixel-defining structures or layers, e.g. banks
G09F 9/30 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
G09F 9/302 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements characterised by the form or geometrical disposition of the individual elements
H10K 50/852 - Arrangements for extracting light from the devices comprising a resonant cavity structure, e.g. Bragg reflector pair
The present invention provides: a positive electrode active material which is suppressed in a decrease of the discharge capacity during charge and discharge cycles; and a secondary battery which uses this positive electrode active material. The present invention provides a secondary battery that comprises a positive electrode active material which contains lithium cobaltate and wherein: the total mass of magnesium oxide and tricobalt tetraoxide as estimated by performing a Rietveld analysis on a pattern that is obtained by powder X-ray diffractometry of the positive electrode active material is 3% or less relative to the mass of the lithium cobaltate; and a powder of the positive electrode active material has a volume resistivity of 1.0E + 8 Ω∙cm to 1.0E + 10 Ω∙cm at a pressure of 64 MPa.
H01M 4/525 - Selection of substances as active materials, active masses, active liquids of inorganic oxides or hydroxides of nickel, cobalt or iron of mixed oxides or hydroxides containing iron, cobalt or nickel for inserting or intercalating light metals, e.g. LiNiO2, LiCoO2 or LiCoOxFy
The present invention provides a lithium ion battery and an electronic device, each of which has high safety or high reliability. The present invention provides a lithium ion battery which has a positive electrode that comprises a positive electrode active material which contains lithium cobaltate that contains magnesium; the lithium cobaltate has an average crushing strength of 700 MPa or more; the positive electrode active material has an O3-type crystal structure in a discharged state; and if the positive electrode in a charged state is analyzed by means of powder X-ray diffractometry, the positive electrode active material has a crystal structure belonging to the space group R-3m, wherein the coordinates of cobalt are shown by (0, 0, 0.5) and the coordinates of oxygen are shown by (0, 0, x) (wherein 0.20 ≤ x ≤ 0.25).
H01M 4/525 - Selection of substances as active materials, active masses, active liquids of inorganic oxides or hydroxides of nickel, cobalt or iron of mixed oxides or hydroxides containing iron, cobalt or nickel for inserting or intercalating light metals, e.g. LiNiO2, LiCoO2 or LiCoOxFy
Provided is a novel display device with excellent convenience, useability, and reliability. This display device has a first light-emitting device, a first layer, a first reflection film, a second light-emitting device, a second layer, and a second reflection film, wherein the first light-emitting device comprises a third layer, a first electrode, and a first unit, and the first unit is sandwiched between the first electrode and the third layer. The first unit includes a first light-emitting material and the first light-emitting material is provided with a light-emitting spectrum having a peak at a first wavelength. The third layer is light-transmissive and includes a second electrode, and the first layer is interposed between the third layer and the first reflection film. The first layer is light-transmissive and has an ordinary light refractive index that is lower than that of the third layer in the first wavelength. Additionally, the second light-emitting device comprises a fourth layer, a third electrode, and a second unit, and the second unit is sandwiched between the third electrode and the fourth electrode. The fourth layer has a gap between itself and the third layer. The second layer is sandwiched between the fourth layer and the second reflection film.
The present invention provides a semiconductor device which comprises a transistor of a very small size. The present invention provides a semiconductor device wherein: a second conductive layer has a region that is in contact with the upper surface of a first conductive layer; the second conductive layer has a first opening that overlaps with the first conductive layer; a third conductive layer is provided on the second conductive layer; the third conductive layer has a second opening that overlaps with the first opening; a first insulating layer is in contact with the lateral wall of the first opening of the second conductive layer; a semiconductor layer is in contact with the upper surface of the first conductive layer, the lateral surface of the first insulating layer and the upper surface of the third conductive layer; a second insulating layer is provided on the semiconductor layer; a fourth conductive layer is provided on the second insulating layer; the first insulating layer has a region that is sandwiched between the lateral wall of the first opening and the semiconductor layer; and the semiconductor layer has a region that is sandwiched between the lateral wall of the first opening and the fourth conductive layer.
G02F 1/1368 - Active matrix addressed cells in which the switching element is a three-electrode device
G09F 9/00 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
G09F 9/30 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
H01L 21/336 - Field-effect transistors with an insulated gate
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
Provided is a semiconductor device (10) having a transistor of a very small size. This semiconductor device has a first transistor (100) and a second transistor (200). The first transistor has a first conductive layer (112a), a first insulation layer (110) on the first conductive layer, a second insulation layer (120) on the first insulation layer, a second conductive layer (112b) on the second insulation layer, a first semiconductor layer (108), a third insulation layer (106), and a third conductive layer (104). The first insulation layer, the second insulation layer, and the second conductive layer have an opening (143) that reaches the first conductive layer. The first semiconductor layer touches the upper surface and side surfaces of the second conductive layer, the side surfaces of the first insulation layer, the second insulation layer, and the upper surface of the first conductive layer. The third insulation layer is provided on the first semiconductor layer. The third conductive layer is provided on the third insulation layer. The second transistor has: a second semiconductor layer (208) on the second insulation layer; the third insulation layer, which is on the second semiconductor layer; and a fourth conductive layer (204) having a region that overlaps the second semiconductor layer, with the third insulation layer therebetween.
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
G09F 9/00 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
G09F 9/30 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
H01L 21/336 - Field-effect transistors with an insulated gate
Provided are: a positive electrode active material which has excellent charge and discharge rate characteristics; and a secondary battery using the same. Provided is a positive electrode active material in which: the crystallite size calculated from an XRD pattern is 150 nm or more; the ratio of the number of nickel atoms to the sum of the number of transition metal atoms is larger in the inside than in a first surface layer part and in a second surface layer part; the ratio of the number of atoms of at least one element selected from cobalt and manganese to the sum of the number of transition metal atoms is larger in the second surface layer part than in the inside; and the concentration of at least one additive element is higher in the first surface layer part than in the inside and in the second surface layer part.
H01M 4/525 - Selection of substances as active materials, active masses, active liquids of inorganic oxides or hydroxides of nickel, cobalt or iron of mixed oxides or hydroxides containing iron, cobalt or nickel for inserting or intercalating light metals, e.g. LiNiO2, LiCoO2 or LiCoOxFy
H01G 11/24 - Electrodes characterised by the structural features of powders or particles used therefor
H01M 4/505 - Selection of substances as active materials, active masses, active liquids of inorganic oxides or hydroxides of manganese of mixed oxides or hydroxides containing manganese for inserting or intercalating light metals, e.g. LiMn2O4 or LiMn2OxFy
The present invention provides a semiconductor device having a transistor of a very small size. In the semiconductor device, a second conductive layer is provided above the first conductive layer, the second conductive layer has a first opening that overlaps with the first conductive layer, a third conductive layer is provided above the second conductive layer, the third conductive layer has a second opening that overlaps with the first opening, a first insulating layer is in contact with the sidewall of the first opening of the second conductive layer, a semiconductor layer is in contact with the top surface of the first conductive layer, the side surface of the first insulating layer, and the top surface of the third conductive layer, a second insulating layer is provided above the semiconductor layer, a fourth conductive layer is provided above the second insulating layer, the first insulating layer has a region sandwiched between the sidewall of the first opening of the second conductive layer and the semiconductor layer, and the semiconductor layer has a region sandwiched between the sidewall of the first opening of the second conductive layer and the fourth conductive layer.
G09F 9/00 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
G09F 9/30 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
H05B 33/10 - Apparatus or processes specially adapted to the manufacture of electroluminescent light sources
H05B 33/14 - Light sources with substantially two-dimensional radiating surfaces characterised by the chemical or physical composition or the arrangement of the electroluminescent material
H10K 50/10 - OLEDs or polymer light-emitting diodes [PLED]
Provided is a semiconductor device that can be miniaturized or highly integrated. This semiconductor device has a first conductor, a first oxide and a second oxide which are electrically connected to the first conductor and have an opening, a second conductor electrically connected to the first oxide, a third conductor disposed inside the opening in the first oxide, a fourth conductor electrically connected to the third conductor, a fifth conductor electrically connected to the second oxide, a sixth conductor disposed inside the opening in the second oxide, a seventh conductor electrically connected to the sixth conductor, and an eighth conductor electrically connected to the second conductor and the seventh conductor. The fourth conductor is provided in the same layer as the seventh conductor, and the direction in which the fourth conductor extends is the same as the direction in which the fifth conductor extends.
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
95.
SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE
The present invention provides a semiconductor device which has a high degree of integration. The semiconductor device has first and second transistors which are electrically connected to each other and a first insulating layer. The first transistor has a first semiconductor layer, a second insulating layer, and first to third conductive layers. The second transistor has a second semiconductor layer, a third insulating layer, and fourth to sixth conductive layers. The first insulating layer is disposed on the first conductive layer, and has an opening that reaches the first conductive layer. The second conductive layer is disposed on the first insulating layer. The first semiconductor layer is in contact with the upper surface of the first conductive layer, the inner wall of the opening, and the second conductive layer. The third conductive layer is disposed on the second insulating layer so as to overlap with the inner wall of the opening. The third insulating layer is disposed on the fourth conductive layer. The fifth and sixth conductive layers are disposed on the fourth conductive layer with the third insulating layer therebetween. The second semiconductor layer is in contact with the upper surfaces of the fifth and sixth conductive layers, lateral surfaces of the same mutually facing each other, and the upper surface of the third insulating layer interposed between the fifth conductive layer and the sixth conductive layer.
G09F 9/00 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
G09F 9/30 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
H05B 44/00 - Circuit arrangements for operating electroluminescent light sources
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
Provided is a high-definition display device. This display device has a transistor, wherein a semiconductor layer of the transistor is provided inside an opening formed in an interlayer insulation layer on a substrate. A floating-state conductive layer is provided below the opening. A source electrode and a drain electrode are provided on the interlayer insulation layer at positions facing each other with the opening therebetween in a plan view. A gate insulation layer and a gate electrode are provided on the semiconductor layer. A region along a side surface of the opening within the semiconductor layer can be made to serve as a channel forming region.
G09F 9/30 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
Provided is a small-size display device with a narrow frame. This display device in which drive circuits and a pixel circuit are stacked, has a laminate of first to third layers, wherein the drive circuit is provided in the first layer and the second layer, and the pixel circuit is provided in the third layer. The first layer has a transistor having silicon in a semiconductor layer, and the second layer and the third layer each have a transistor having a metal oxide in a semiconductor layer. Further, the channel length of the transistor in the second layer is shorter than that of the transistor in the third layer, and the structure is suited to high-speed operations of the circuits.
G09F 9/30 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
H05B 44/00 - Circuit arrangements for operating electroluminescent light sources
H10K 59/123 - Connection of the pixel electrodes to the thin film transistors [TFT]
H10K 59/124 - Insulating layers formed between TFT elements and OLED elements
H10K 59/127 - Active-matrix OLED [AMOLED] displays comprising two substrates, e.g. display comprising OLED array and TFT driving circuitry on different substrates
H10K 59/131 - Interconnections, e.g. wiring lines or terminals
Provided is a semiconductor device that has a small circuit scale and in which power consumption is reduced. The semiconductor device has first to fourth cells, first and second circuits, and first to fourth current generation circuits. The first cell is electrically connected to the third cell via first wiring and the first current generation circuit, and is electrically connected to the first circuit via second wiring. The second cell is electrically connected to the fourth cell via third wiring and the second current generation circuit, and is electrically connected to the second circuit via fourth wiring. The third cell is electrically connected to the second cell via the third current generation circuit and the fourth wiring. The fourth cell is electrically connected to the first cell via the fourth current generation circuit and the second wiring. In addition, the first and second current generation circuits function as a current mirror circuit, and the third and fourth current generation circuits function as a calculation circuit for a function system. Calculation of a product is performed by the first and second cells, and the calculation result is held by the third and fourth cells.
G06G 7/60 - Analogue computers for specific processes, systems, or devices, e.g. simulators for living beings, e.g. their nervous systems
G11C 5/02 - Disposition of storage elements, e.g. in the form of a matrix array
G11C 5/04 - Supports for storage elements; Mounting or fixing of storage elements on such supports
G11C 11/54 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using elements simulating biological cells, e.g. neuron
Provided is a semiconductor device having a novel configuration. The semiconductor device includes: a first element layer including a control unit; and a second element layer provided as stacked on the first element layer. The second element layer includes: a storage unit that functions as a set-associative cache memory having n (where n is equal to or greater than 2) ways; and an input/output unit that has the function of inputting and outputting data stored in the storage unit. The second element layer is provided as n stacked element layers. The n element layers each include a first transistor. In the first transistor, a semiconductor layer having a channel formation region includes silicon. The n element layers each include a storage unit and an input/output unit that are provided as separated from each other. The storage unit provided to any one of the n element layers outputs data corresponding to any one of the n ways to the control unit through the input/output unit provided to any one of the n element layers.
Through the present invention, the driving voltage of a light-emitting device is reduced, and light emission efficiency is enhanced. Provided is a light-emitting device having a first electrode, a second electrode, a light-emitting layer, and a first layer, the light-emitting layer being positioned between the first electrode and the second electrode, the first layer being positioned between the first electrode and the light-emitting layer, the light-emitting layer having a light-emitting substance, the first layer having a first organic compound, the HOMO level of the first organic compound being -5.40 eV or lower, and the first organic compound being represented by general formula (G1). (In general formula (G1): Q is O or S; either A or B is a group represented by general formula (g1), and the other of A or B and R1 through R31 each independently represent any of H, D, an alkyl group, a cyclic saturated hydrocarbon group, an alkoxy group, an amino group, a halogen, a haloalkyl group, and an aromatic hydrocarbon group; and R9 and R10 may bond with each other to form a spiro ring system.)
C07D 307/77 - Heterocyclic compounds containing five-membered rings having one oxygen atom as the only ring hetero atom ortho- or peri-condensed with carbocyclic rings or ring systems
H10K 30/60 - Organic devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation in which radiation controls flow of current through the devices, e.g. photoresistors
H10K 65/00 - Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element and at least one organic radiation-sensitive element, e.g. organic opto-couplers
H10K 85/60 - Organic compounds having low molecular weight
H10K 101/30 - Highest occupied molecular orbital [HOMO], lowest unoccupied molecular orbital [LUMO] or Fermi energy values
H10K 101/40 - Interrelation of parameters between multiple constituent active layers or sublayers, e.g. HOMO values in adjacent layers
patents
