An integrated circuit includes a semiconductor substrate and a plurality of dielectric layers over the semiconductor substrate, including a top dielectric layer. A metal plate or metal coil is located over the top dielectric layer; a metal ring is located over the top dielectric layer and substantially surrounds the metal plate or metal coil. A protective overcoat overlies the metal ring and overlies the metal plate or metal coil. A trench opening is formed through the protective overcoat, with the trench opening exposing the top dielectric layer between the metal plate/coil and the metal ring, the trench opening substantially surrounding the metal plate or metal coil.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/58 - Structural electrical arrangements for semiconductor devices not otherwise provided for
2.
MONOLITHIC INTEGRATION OF HIGH AND LOW-SIDE GAN FETS WITH SCREENING BACK GATING EFFECT
An electronic device includes an one of aluminum gallium nitride, aluminum nitride, indium aluminum nitride, or indium aluminum gallium nitride back barrier layer over a buffer structure, a gallium nitride layer over the back barrier layer, a hetero-epitaxy structure over the gallium nitride layer, first and second transistors over the hetero-epitaxy structure, and a hole injector having a doped gallium nitride structure over the hetero-epitaxy structure and a conductive structure partially over the doped gallium nitride structure to inject holes to form a hole layer proximate an interface of the back barrier layer and the buffer structure to mitigate vertical electric field back gating effects for the first transistor.
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
3.
INTEGRATED BATTERY CHARGE REGULATION CIRCUIT BASED ON POWER FET CONDUCTIVITY MODULATION
A system includes a switching converter and a circuit coupled to the switching converter. The circuit includes monitoring circuitry and a switch coupled to the switching converter. The circuit also includes a transconductance stage having a first transconductance input, a second transconductance input, and a transconductance output, the first transconductance input coupled to the monitoring circuitry and the transconductance output coupled to the switch. Additionally, the circuit includes a resistor having a first resistor terminal and a second resistor terminal, the first resistor terminal coupled to the transconductance output and to the switch; and a capacitor having a first capacitor terminal and a second capacitor terminal, the first capacitor terminal coupled to the second resistor terminal.
H02J 7/00 - Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
H02H 3/06 - Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition, with or without subsequent reconnection - Details with automatic reconnection
4.
VOLTAGE CONVERTER WITH AVERAGE INPUT CURRENT CONTROL AND INPUT-TO-OUTPUT ISOLATION
A circuit includes a control circuit having a first control circuit input, a second control circuit input, a first control circuit output, and a second control circuit output, and a first transistor having a first current terminal, a second current terminal, and a control terminal, the control terminal coupled to the first control circuit output, the first current terminal coupled to the first control circuit input and to a second transistor, and the second current terminal adapted to be coupled to the second transistor, a logic circuit having a first logic input, a second logic input, and a logic output, the first logic input coupled to the second control circuit output and a switch having a first switch terminal, a second switch terminal, and a switch control terminal, the switch control terminal coupled to the logic output and the first switch terminal coupled to the second current terminal.
H02M 3/155 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
In an example, a system includes an oscillator circuit on a chip. The oscillator circuit includes a charging current generator including a current mirror, an amplifier, and an on-chip resistor, where the on-chip resistor is coupled to a pin on the chip. The oscillator circuit also includes oscillator circuitry coupled to the charging current generator, where the oscillator circuitry includes a comparator, a phase generator, a first capacitor coupled to a first resistor, and a second capacitor coupled to a second resistor. The system also includes an external resistor coupled to the pin, where the external resistor is external to the chip. The system includes an external capacitor coupled to the pin, where the external capacitor is external to the chip.
H03B 5/20 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising resistance and either capacitance or inductance, e.g. phase-shift oscillator
An apparatus includes: a first conductor layer patterned into parallel strips having a first end and an opposite second end formed on a device side surface of a multilayer package substrate, the multilayer package substrate including conductor layers spaced from one another by dielectric material and coupled to one another by conductive vertical connection layers extending through the dielectric material; a second conductor layer in the multilayer package substrate spaced from the first conductor layer, the second conductor layer patterned into parallel strips having a first end and a second end, the second conductor layer coupled to the first conductor layer by vertical connectors formed of the conductive vertical connection layers at the first end and the second end, and a semiconductor die mounted to the device side surface of the multilayer package substrate that is spaced from and coupled to the second conductor.
Sequences to synchronize devices and related methods are disclosed herein including an access address generator to cryptographically generate a first bit sequence, an access address selector to read a first portion of the first bit sequence and read a second portion of the first bit sequence, the second portion different than the first portion, an access address analyzer to identify a first access address from a first section of the first portion based on a first criteria, the first criteria a function of a first autocorrelation function and identify a second access address from a second section of the second portion based on a second criteria, the second criteria a function of a second autocorrelation function.
H04L 9/06 - Arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for blockwise coding, e.g. D.E.S. systems
H04W 4/80 - Services using short range communication, e.g. near-field communication [NFC], radio-frequency identification [RFID] or low energy communication
Disclosed embodiments include a decision feedback equalizer (DFE) comprising an N-bit parallel input adapted to be coupled to a communication channel and configured to receive consecutive communication symbols, a first DFE path including a first path input configured to receive communication symbols, and a first adder having a first adder input coupled to the first path input. There is a first DFE filter having outputs responsive to the first DFE filter inputs, the outputs coupled to the second adder input. The DFE includes a first path having a first slicer and a first multiplexer, a first path multiplexer output, and a second DFE path including a second path input configured to receive a second communication symbol, a second adder, a second DFE filter, a second slicer, and a second multiplexer.
A package substrate includes a first metal layer, a second metal layer, isolation material containing the first and second metal layers, an isolation circuit, a first plurality of contact pads, and a second plurality of contact pads. The isolation circuit includes a first circuit element in the first metal layer and a second circuit element in the second metal layer and electrically isolated from the first circuit element by the isolation material. The first plurality of contact pads is adapted to be coupled to a first integrated circuit on the package substrate and includes a first contact pad coupled to the first circuit element. The second plurality of contact pads is adapted to be coupled to a second integrated circuit on the package substrate and includes a second contact pad coupled to the second circuit element.
An electronic device includes a first dielectric layer above a semiconductor layer, lower-bandgap dielectric layer above the first dielectric layer, the lower-bandgap dielectric layer having a bandgap energy less than a bandgap energy of the first dielectric layer, a first capacitor plate above the lower-bandgap dielectric layer in a first plane of first and second directions, a second dielectric layer above the first capacitor plate, a second capacitor plate above the second dielectric layer in a second plane of the first and second directions, the first and second capacitor plates spaced apart from one another along a third direction, and a conductive third capacitor plate above the second dielectric layer in the second plane, the third capacitor plate spaced apart from the second capacitor plate in the second plane.
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different main groups of groups , or in a single subclass of , , e.g. forming hybrid circuits
11.
SAMPLE ADAPTIVE OFFSET PARAMETER ESTIMATION FOR IMAGE AND VIDEO CODING
A method and apparatus for decoding video. The method includes determining a sample adaptive offset edge type of at least a portion of the image, determining a boundary edge type of the at least a portion of the image, modifying the sample adaptive offset edge type of the at least a portion of the image according to the determined edge type of the at least a portion of the image, selecting a sample adaptive offset type according to at least one of the determined sample adaptive offset edge type or the modified sample adaptive offset edge type, and filtering at least a portion of the image utilizing the selected filter type.
H04N 19/167 - Position within a video image, e.g. region of interest [ROI]
H04N 19/117 - Filters, e.g. for pre-processing or post-processing
H04N 19/14 - Coding unit complexity, e.g. amount of activity or edge presence estimation
H04N 19/174 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a slice, e.g. a line of blocks or a group of blocks
H04N 19/176 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
H04N 19/61 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding in combination with predictive coding
H04N 19/82 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals - Details of filtering operations specially adapted for video compression, e.g. for pixel interpolation involving filtering within a prediction loop
H04N 19/86 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using pre-processing or post-processing specially adapted for video compression involving reduction of coding artifacts, e.g. of blockiness
12.
AT-SPEED TEST OF FUNCTIONAL MEMORY INTERFACE LOGIC IN DEVICES
Methods to test functional memory interface logic of a core under test utilize a built-in-self-test (BIST) controller to generate test sequences, and a clock-gating circuit to selectively supply the test sequences to a memory input or memory output on the core under test. After an initial data initialization of the core under test at BIST mode, an at-speed functional mode is utilized to capture a desired memory output.
An electronic device includes a substrate having first and second conductive traces, a semiconductor die having a transistor with a first terminal and a second terminal, and first and second metal clips. The first metal clip has a first end portion coupled to the first terminal of the transistor, and a second end portion coupled to the first conductive trace of the substrate. The second metal clip has a first end portion coupled to the second terminal of the transistor and a second end portion coupled to the second conductive trace of the substrate, and a middle portion of the second metal clip is spaced apart from and at least partially overlying a portion of the first metal clip.
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different main groups of groups , or in a single subclass of , , e.g. forming hybrid circuits
A method of fabricating an integrated circuit includes etching trenches in a first surface of a semiconductor layer. A trench dielectric layer is formed over the first surface and over bottoms and sidewalls of the trenches and a doped polysilicon layer is formed over the trench dielectric layer and within the trenches. The doped polysilicon layer is patterned to form a polysilicon bridge that connects to the polysilicon within the filled trenches and a blanket implant of a first dopant is directed to the polysilicon bridge and to the first surface. The blanket implant forms a contact region extending from the first surface into the semiconductor layer.
H01L 21/225 - Diffusion of impurity materials, e.g. doping materials, electrode materials, into, or out of, a semiconductor body, or between semiconductor regions; Redistribution of impurity materials, e.g. without introduction or removal of further dopant using diffusion into, or out of, a solid from or into a solid phase, e.g. a doped oxide layer
An ultrasound system includes a transmit-receive switch. The transmit-receive switch includes a combined transmit-receive and return-to-zero (RTZ) path. The combined transmit-receive and RTZ path includes a transistor with a first current terminal, a second current terminal, and a control terminal. The second current terminal of the transistor is coupled to a ground node via a first switch and is coupled to a receive node via a second switch. The ultrasound system also includes a receiver front-end circuit coupled to the receive node.
A passive circuit component includes an edge having a low line edge roughness (LER). A method for manufacturing the passive circuit component includes a self-aligned double patterning (SADP) etch process using a tri-layer process flow. The tri-layer process flow includes use of an underlayer, hard mask, and photoresist. The passive circuit component made by this method achieves improved mismatch between like components due to the low LER.
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
A multi-phase buck-boost converter includes a first half-bridge circuit, a second half-bridge circuit, a third half-bridge circuit, and a control circuit. The first half-bridge circuit is coupled to a first inductor terminal. The second half-bridge circuit is coupled to a second inductor terminal. The third half-bridge circuit is coupled to a third inductor terminal, a system voltage terminal, and a battery terminal. The control circuit is coupled to the first half-bridge circuit, the second half-bridge circuit, and the third half-bridge circuit. The control circuit is configured to transition the first half-bridge circuit, the second half-bridge circuit, and the third half-bridge circuit from operation in a buck mode to operation in a buck-boost mode based on an off-time of the first half-bridge being less than a particular time.
H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
An example method includes forming and patterning an etch assist layer on a first dielectric layer such that the etch assist layer is not over a first bond pad; forming and patterning a first photoresist layer on a second patterned conductive layer on the first dielectric, wherein the first photoresist layer is not over the first bond pad and etching the second dielectric layer to a depth of 5 to 15% of a thickness of the first dielectric layer and the second dielectric layer; etching the first dielectric layer and second dielectric layer using a second photoresist layer to a depth of 20 to 25%; and exposing the first bond pad by etching the first dielectric layer using a patterned third photoresist layer, such that an area of the dielectric layer exposed by the third opening adjacent to the bond pad is between 3-5 μm thick.
H01F 41/04 - Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils or magnets for manufacturing coils
A voltage regulator control circuit includes a transistor input controller. The transistor input controller forces a slew control signal on its slew control output to a state responsive to a change in a load condition and forces an ON signal to a state on its first transistor control output. A first transistor has a first control input and first and second current terminals. A second transistor couples to the first transistor. A driver has a slew control input, a driver input, and a driver output. The driver input couples to the first transistor control output. The driver output couples to the first control input. Responsive to a first logic state of the slew control signal and a first state of the ON signal, the driver provides a higher current to the first control input, and responsive to a second state of the slew control signal and a first state of the ON signal, the driver provides a lower current to the first control input.
H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
Techniques for signaling of sample adaptive offset (SAO) information that may reduce the coding rate for signaling such information in the compressed bit stream are provided. More specifically, techniques are provided that allow SAO information common to two or more of the color components to be signaled using one or more syntax elements (flags or indicators) representative of the common information. These techniques reduce the need to signal SAO information separately for each color component.
H04N 19/86 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using pre-processing or post-processing specially adapted for video compression involving reduction of coding artifacts, e.g. of blockiness
H04N 19/117 - Filters, e.g. for pre-processing or post-processing
H04N 19/186 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being a colour or a chrominance component
H04N 19/463 - Embedding additional information in the video signal during the compression process by compressing encoding parameters before transmission
H04N 19/70 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by syntax aspects related to video coding, e.g. related to compression standards
H04N 19/80 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals - Details of filtering operations specially adapted for video compression, e.g. for pixel interpolation
H04N 19/82 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals - Details of filtering operations specially adapted for video compression, e.g. for pixel interpolation involving filtering within a prediction loop
H04N 19/91 - Entropy coding, e.g. variable length coding [VLC] or arithmetic coding
A microelectronic device including an isolation device. The isolation device includes a lower isolation element, an upper isolation element, and an inorganic dielectric plateau between the lower isolation element and the upper isolation element. The inorganic dielectric plateau contains an upper etch stop layer and a lower etch stop layer between the upper isolation element and the lower isolation element. The upper etch stop layer provides an end point signal during the plateau etch process which provides feedback on the amount of inorganic dielectric plateau which has been etched. The lower etch stop layer provides a traditional etch stop function to provide for a complete plateau etch and protection of an underlying metal bond pad. The inorganic dielectric plateau also contains alternating layers of high stress and low stress silicon dioxide, which provide a means of reinforcement of the inorganic dielectric plateau.
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns
22.
MICROELECTRONIC DEVICE PACKAGE INCLUDING ANTENNA AND SEMICONDUCTOR DEVICE
A described example includes an antenna formed in a first conductor layer on a device side surface of a multilayer package substrate, the multilayer package substrate including conductor layers spaced from one another by dielectric material and coupled to one another by conductive vertical connection layers, the multilayer package substrate having a board side surface opposite the device side surface; and a semiconductor die mounted to the device side surface of the multilayer package substrate spaced from and coupled to the antenna.
In one example, a calibration method includes receiving, from a sensor proximate a first conductor, a sensor signal representing a measurement of a magnetic field produced based on a first current flowing in the first conductor and a second current flowing in a second conductor, the first current including first and second current components having different frequencies, and the second current including third and fourth current components, the third current component phase shifted from, and having the same frequency as, the first current component and the fourth current component having a different frequency from the third current component, determining reference values of the first and second currents, and based on the sensor signal and the reference values of the first and second currents, determining for the sensor, a plurality of coupling coefficients representing magnetic field coupling between the first and second conductors.
In some examples, an apparatus comprises a first coil, a second coil, a control circuit, and a processing circuit. The second coil is magnetically coupled to the first coil. The control circuit has a signal output coupled to the first coil, and a control output, and the control circuit configured to: responsive to a state of the control input, select a field strength level from a set of discrete field strength levels; and provide a first signal representing the selected field strength level at the signal output. Also, the processing circuit has processing inputs and a processing output, the processing inputs coupled to the second coil, the processing output coupled to the control input, and the processing circuit configured to, responsive to a second signal across the processing inputs, set a state of the processing output representing a polarity of a magnetic field sensed by the second coil.
A microelectronic device includes a galvanic isolation component. The galvanic isolation component includes a lower winding and an upper isolation element over the lower winding. The galvanic isolation component further includes a field suppression structure located interior to the lower winding. The field suppression structure includes a conductive field deflector that is separated from the lower winding by a lateral distance that is half a thickness of the lower winding to twice the thickness of the lower winding. A top surface of the conductive field deflector is substantially coplanar with a bottom surface of the lower winding. The conductive field deflector is electrically connected to a semiconductor material in a substrate. The lower winding is separated from a substrate by a first dielectric layer. The upper isolation element is separated from the lower winding by a second dielectric layer.
The present disclosure generally relates to shallow trench isolation (STI) processing with local oxidation of silicon (LOCOS), and an integrated circuit formed thereby. In an example, an integrated circuit includes a semiconductor layer, a LOCOS layer, an STI structure, and a passive circuit component. The semiconductor layer is over a substrate. The LOCOS layer is over the semiconductor layer. The STI structure extends into the semiconductor layer. The passive circuit component is over and touches the LOCOS layer.
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
In some examples, a semiconductor package comprises an electrically conductive surface and a bond wire coupled to the electrically conductive surface. The bond wire includes a first stitch bond coupled to the electrically conductive surface, and a second stitch bond contiguous with the first stitch bond and coupled to the electrically conductive surface. The second stitch bond is partially, but not completely, overlapping with the first stitch bond.
A method for performing code block segmentation for wireless transmission using concatenated forward error correction encoding includes receiving a transport block of data for transmission having a transport block size, along with one or more parameters that define a target code rate. A number N of inner code blocks needed to transmit the transport block is determined. A number M—outer code blocks may be calculated based on the number of inner code blocks and on encoding parameters for the outer code blocks. The transport block may then be segmented and encoded according to the calculated encoding parameters.
H04L 1/00 - Arrangements for detecting or preventing errors in the information received
H03M 13/00 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
H03M 13/09 - Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
H03M 13/15 - Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
H03M 13/25 - Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
H03M 13/27 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
H03M 13/29 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
A circuit includes a half-bridge circuit is configured to provide a switching voltage responsive to respective high-side and low-side drive signals. High-side slew control circuitry is configured to provide a high-side slew-compensated control signal responsive to a high-side enable signal and a slew current signal representative of a slew rate at a switching output. A high-side driver is configured to provide the high-side drive signal responsive to the high-side slew-compensated control signal. Low-side slew control circuitry is configured to provide a low-side slew-compensated drive signal responsive to a low-side enable signal and the slew current signal. A low-side driver is configured to provide the low-side drive signal responsive to the low-side slew-compensated control signal. A capacitor is coupled between the high-side and low-side slew control circuitry and is configured to convert the slew rate to the slew current signal.
H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion
H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H03K 17/16 - Modifications for eliminating interference voltages or currents
30.
DETERMINISTIC JITTER COMPENSATION SCHEME FOR DTC TIMING PATH
In an example, a system includes an N divider coupled to an output of a low dropout regulator. The system also includes a load balancing circuit coupled to the N divider and configured to sink a load balancing current at the output of the low dropout regulator during one or more phases of the N divider. The system includes a switch coupled to the load balancing circuit and configured to connect the load balancing circuit to the output of the low dropout regulator during the one or more phases of the N divider.
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
31.
OSCILLATOR CALIBRATED TO A MICROELECTROMECHANICAL SYSTEM (MEMS) RESONATOR-BASED OSCILATOR
A clock circuit includes a voltage-controlled oscillator (VCO) having a control input and a first clock output. The clock circuit includes a frequency-locked loop (FLL) having an FLL input and a control output, the control output coupled to the control input. A microelectromechanical system (MEMS) resonator-based oscillator has a second clock output. A multiplexer has a first multiplexer input, a second multiplexer input, a selection input, and a multiplexer output. The first multiplexer input is coupled to the first clock output. The second multiplexer input is coupled to the second clock output. The multiplexer output is coupled to the FLL input.
H03L 7/099 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
H03B 5/32 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator
H03L 7/085 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
H03M 1/46 - Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
In examples, a semiconductor die comprises a semiconductor substrate having a surface, the surface having first and second surface portions, and a radiator layer on the surface. The radiator layer comprises a metal member having a first metal member portion above the first surface portion and a second metal member portion above the second surface portion, a first distance between the first metal member portion and the first surface portion, and a second distance between the second metal member portion and the second surface portion, the first distance less than the second distance. The radiator layer includes first and second electrodes. The radiator layer includes a piezoelectric layer extending along a length of the radiator layer and on each of the first and second electrodes, the piezoelectric layer between the first and second metal members and the semiconductor substrate.
A controller includes: a pulse-width modulation (PWM) circuit; a control loop; and a reference voltage controller. The control loop has: a feedback input adapted to be coupled to an output voltage of a power stage; a control loop output coupled to a PWM control input; and an operational amplifier with a first feedback input, a first reference input, and an amplifier output, the first feedback input connected to the feedback input, and the amplifier output coupled to the PWM control input. The reference voltage controller has a reference voltage output coupled to the first reference input, the reference voltage controller configured to adjust a reference voltage provided to the reference voltage output responsive to a dynamic error estimate based on error in the operational amplifier.
H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion
Examples of low capacitance bidirectional and unidirectional electrostatic discharge (ESD) protection devices for high voltage (e.g., 15 kV, 30 kV) applications are provided. Such devices include a circuit of a diode and a Zener diode coupled via their anodes to form an NPN structure and another, low capacitance diode coupled in series with the NPN structure. Such circuit may be configured on each of two dies, and the circuits coupled via wire bonds. Additional wire bonds may be used to respectively couple two pins of the device to the two circuits, or the pins may be coupled to the circuits via respective conductive die attaches. In a multichip module (MCM) topology, the NPN diode structure may be coupled to two low capacitance diodes on one die, and that circuit may be coupled to a third low capacitance diode disposed on another die. Some arrangements employ an insulator in conjunction with a single die. Some arrangements enable FlipChip fabrication technology.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
35.
Systems and Methods for Online Gain Calibration of Digital-to-Time Converters
A system includes a first digital-to-time converter (DTC) adapted to receive a first DTC code and a first clock signal. The first DTC provides an output clock signal. The system includes a calibration DTC adapted to receive a calibration DTC code and a second clock signal. The calibration DTC provides a calibration output signal. The system includes a latch comparator which provides outputs indicative of which of the output clock signal and the calibration output signal is received first. The system includes an average computation module which provides an average value of the outputs of the latch comparator. The system includes a digital controller adapted to receive the average value. The digital controller provides the DTC code and the calibration DTC code.
A microelectronic device including a galvanic isolator with filler metal within an upper isolation element. The galvanic isolator includes a lower isolation element, an upper isolation element, and an inorganic dielectric plateau between the lower isolation element and the upper isolation element. The upper isolation element contains tines of filler metal which are electrically tied to each other and are electrically tied to the upper isolation element. The ends of the tines are rounded to minimize electric fields. The filler metal increases the overall metal density on the metal layer of the upper isolation element to meet the typical metal density requirements of modern microelectronic fabrication processing.
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
A microelectronic device includes a buried trench capacitor below an electronic component of the microelectronic device. In one embodiment, the buried trench capacitor may be formed between a silicon oxide capped p-type buried trench capacitor polysilicon region and a buried trench capacitor deep n-type region separated by buried trench capacitor liner dielectric. In a second embodiment, the buried trench capacitor may be formed by a buried trench capacitor polysilicon region and a p-type silicon epitaxial region separated by a buried trench capacitor liner dielectric. One terminal of the deep trench capacitor is made through the substrate via a deep trench substrate contact. The second terminal of the deep trench capacitor is made via a well contact that connects to the capacitor through a deep well region in one embodiment and through a polysilicon layer in a second embodiment.
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
A circuit (300) includes a plurality of first stage integrators (106 (1,1) - 106(2,1)). Each of the plurality of first stage integrators (106 (1, 1 ) - 106(2, 1 )) includes a first input (324 ), a. second input (326), a third input (322) and an output (328). The first input (324) of each of the plurality of first stage integrators is coupled to a. different one of circuit inputs (304), the second input (326) is coupled to a first reference input, the third input (322) is coupled to a second reference input and the output (328) of each of the plurality of first stage integrators is coupled to the first input (324) of such first stage integrator. The circuit (300) includes a second stage integrator ( 108(1)) which includes a first input (386) coupled to each of the first inputs of the plurality' of first stage integrators, a second input. (388) coupled to the first reference input, and an output (392) coupled to the first input (386) of the second stage integrator (108(1)).
In examples, a semiconductor die (106) comprises a semiconductor substrate (506) having a surface (550), the surface having first and second surface portions (564, 567), and a radiator layer (206) on the surface. The radiator layer comprises a metal member (560) having a first metal member portion (563) above the first surface portion and a second metal member portion (566) above the second surface portion, a first distance between the first metal member portion and the first surface portion, and a second distance between the second metal member portion and the second surface portion, the first distance less than the second distance. The radiator layer includes first and second electrodes (555, 573). The radiator layer includes a piezoelectric layer (554) extending along a length of the radiator layer and on each of the first and second electrodes, the piezoelectric layer between the first and second metal member portions and the semiconductor substrate.
B06B 1/06 - Processes or apparatus for generating mechanical vibrations of infrasonic, sonic or ultrasonic frequency making use of electrical energy operating with piezoelectric effect or with electrostriction
40.
CURRENT LIMITER CIRCUIT WITH ADJUSTABLE RESPONSE TIME
A current limiter (104) includes a gain adjustment circuit (208) designed to change the response time (e.g., operation mode) of the current limiter. The current limiter may be designed to operate at different selectable speed modes (e.g., slow mode, fast mode) that affect how quickly the current limiter responds to an overcurrent stimulus. The speed modes may be selected by choosing between different current mirror arrangements in the gain adjustment circuit. Regardless of which mode of operation is selected for the current limiter, a speedup circuit (210) may also be implemented, which includes a switch (M5) to initiate a nonlinear speedup of the response time after a certain overcurrent stimulus is received.
In one example, an apparatus comprises first (702), second (704) and third (706) memory devices, an error detection circuit (902), and an error correction circuit (904). The error detection circuit is configured to detect a mismatch among data stored at the first, second, and third memory devices, and responsive to detecting the mismatch, provide a correction signal (910) representing a majority state of the data. The error correction circuit is configured to write the majority state of the data into at least one of the first, second, or third memory devices responsive to the correction signal.
G06F 11/14 - Error detection or correction of the data by redundancy in operation, e.g. by using different operation sequences leading to the same result
H03K 3/3565 - Bistables with hysteresis, e.g. Schmitt trigger
42.
BOOST CONVERTER WITH WIDE AVERAGE CURRENT LIMITING RANGE
H02M 3/155 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion
A microelectronic device (100) including an isolation device (101). The isolation device (101) includes a lower isolation element (119), an upper isolation element (148), and an inorganic dielectric plateau (152) between the lower isolation element (119) and the upper isolation element (148). The inorganic dielectric plateau (152) contains an upper etch stop layer (136) and a lower etch stop layer (129) between the upper isolation element (148) and the lower isolation element (119). The upper etch stop layer (136) provides an end point signal during the plateau etch process (161) which provides feedback on the amount of inorganic dielectric plateau (152) etched. The lower etch stop layer (129) provides an etch stop function, ensuring a complete plateau etch (161) and protecting an underlying metal bond pad (122). The inorganic dielectric plateau (152) contains alternating layers of high stress silicon dioxide (141) and low stress silicon dioxide (132) which, provide a means of reinforcement of the inorganic dielectric plateau (152)
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
44.
Methods and apparatus to reduce retimer latency and jitter
An example system includes: interleaving circuitry including a data input, a plurality of data outputs, and a plurality of clock inputs, the data input coupled to the received data input and each of the plurality of clock inputs coupled to one of the plurality of receiver clock outputs; and handoff circuitry coupled to the interleaving circuitry, the handoff circuitry including: comparison circuitry coupled to the clock generation circuitry and configured to compare the plurality of receiver clocks to the transmission clock; clock configuration circuitry coupled to the comparison circuitry and configured to select one of the plurality of receiver clocks based on the comparison circuitry; and a plurality of flip-flops coupled to the clock configuration circuitry and configured to convert the plurality of data outputs from the plurality of receiver clocks to the transmission clock to generate a plurality of transmission data streams based on the one of the plurality of receiver clocks selected by the clock configuration circuitry.
A layer of additive material is formed in a circular printing area on a substrate using additive sources distributed across a printing zone. The additive sources form predetermined discrete amounts of the additive material. The substrate and the additive sources are rotated with respect to each other around a center of rotation, so that a pattern of the additive material is formed in a circular printing area on the substrate. Each additive source receives actuation waveforms at an actuation frequency that is proportional to a distance of the additive source from the center of rotation. The actuation waveforms include formation signals, with a maximum of one formation signal in each cycle of the actuation frequency. The formation signals result in the additive sources forming the predetermined discrete amounts of the additive material on the substrate.
B29C 64/165 - Processes of additive manufacturing using a combination of solid and fluid materials, e.g. a powder selectively bound by a liquid binder, catalyst, inhibitor or energy absorber
B22F 10/00 - Additive manufacturing of workpieces or articles from metallic powder
B22F 10/14 - Formation of a green body by jetting of binder onto a bed of metal powder
B33Y 30/00 - ADDITIVE MANUFACTURING, i.e. MANUFACTURING OF THREE-DIMENSIONAL [3D] OBJECTS BY ADDITIVE DEPOSITION, ADDITIVE AGGLOMERATION OR ADDITIVE LAYERING, e.g. BY 3D PRINTING, STEREOLITHOGRAPHY OR SELECTIVE LASER SINTERING - Details thereof or accessories therefor
B33Y 70/00 - Materials specially adapted for additive manufacturing
B33Y 80/00 - Products made by additive manufacturing
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/288 - Deposition of conductive or insulating materials for electrodes from a liquid, e.g. electrolytic deposition
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
An integrated circuit includes first and second trenches in a semiconductor substrate and a semiconductor mesa between the first and second trenches. A source region having a first conductivity type and a body region having an opposite second conductivity type are located within the semiconductor mesa. A trench shield is located within the first trench, and a gate electrode is over the trench shield between first and second sidewalls of the first trench. A gate dielectric is on a sidewall of the first trench between the gate electrode and the body region, and a pre-metal dielectric (PMD) layer is over the gate electrode. A gate contact through the PMD layer touches the gate electrode between the first and second sidewalls, and a trench shield contact through the PMD layer touches the trench shield between the first and second sidewalls.
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
47.
STABILIZING DIELECTRIC STRESS IN A GALVANIC ISOLATION DEVICE
A microelectronic device including an isolation device with a stabilized dielectric. The isolation device includes a lower isolation element, an upper isolation element, and an inorganic dielectric plateau between the lower isolation element and the upper isolation element. The dielectric sidewall of the inorganic dielectric plateau is stabilized in a nitrogen containing plasma which forms a SiOxNy surface on the dielectric sidewall of the inorganic dielectric plateau. The SiOxNy surface on the dielectric sidewall of the inorganic dielectric plateau reduces ingress of moisture into the dielectric stack of the inorganic dielectric plateau.
H01L 27/01 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate comprising only passive thin-film or thick-film elements formed on a common insulating substrate
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
A processor with instruction storage configured to store processor instructions, data storage configured to store processor data representing an array, the array including plural data elements, a controller, and an instruction pipeline. The instruction pipeline includes: a load stage circuit configured to load an array element from the data storage, a compare stage circuit configured to compare the array element to a reference value, a store stage circuit configured to store a set of results that includes a result of the comparison of the array element to the reference value, and a loop hit detect stage circuit configured to determine whether any of the set of results is associated with a hit on the reference value.
An example apparatus includes: a first level shifting circuit including a supply output; a first deserializer stage including a supply input, a first input, a first output, and a second output, the supply input coupled to the supply output; a second level shifting circuit including a second input and a third output, the second input coupled to the first output; and a second deserializer stage including a third input, a fourth output and a fifth output, the third input coupled to the third output.
A microelectronic device includes a lower isolation element and an upper isolation element, separated by an isolation dielectric layer stack. The microelectronic device includes a lower field reduction layer over the lower isolation element, under the isolation dielectric layer stack. The lower field reduction layer includes a first dielectric layer adjacent to the isolation dielectric layer stack, and a second dielectric layer over the first dielectric layer. A dielectric constant of the first dielectric layer is greater than a dielectric constant of the second dielectric layer. The dielectric constant of the second dielectric layer is greater than a dielectric constant of the isolation dielectric layer stack adjacent to the lower field reduction layer. Methods of forming example microelectronic device having lower field reduction layers are disclosed.
H01L 27/01 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate comprising only passive thin-film or thick-film elements formed on a common insulating substrate
Described examples include an apparatus includes a dichroic wedge and a spatial light modulator optically coupled to the dichroic wedge. The apparatus also includes a display optically coupled to the spatial light modulator. The display includes a waveguide having a first side and a second side and a first diffractive optical element on the first side of the waveguide. The display also includes a second diffractive optical element on the first side of the waveguide and a third diffractive optical element on the second side of the waveguide.
A balun includes a first winding which has a first terminal coupled to an input, and a second terminal coupled to a reference potential terminal. The balun includes a second winding magnetically coupled to the first winding. The second winding has a first terminal coupled to a first differential output, a second terminal coupled to a second differential output, and a tap coupled to the reference potential terminal. The balun includes a first capacitor which has a first terminal coupled to the first winding and a second terminal coupled to the second winding. The balun includes a third winding which has a first terminal coupled to the reference potential terminal and a floating second terminal. The balun includes a second capacitor which has a first terminal coupled to the third winding and a second terminal coupled to the second winding.
An analog-to-digital converter (ADC) includes a switched capacitor circuit, a comparator, and a control circuit. The switched capacitor circuit has a switch control input and an output, and includes switches coupled to the switch control input and coupled to capacitors. The comparator has an input coupled to the output of the switched capacitor circuit and has an output. The control circuit has a switch control output coupled to the switch control input, has an input coupled to the output of the comparator, and provides switch control signals at the switch control output. Responsive to the switch control signals, the switched capacitor circuit provides an output signal to the comparator that is based on a sample of an analog input signal acquired in a sample acquisition cycle and based on a digital sample value output by the ADC prior to the sample acquisition cycle.
H03M 1/46 - Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
H03M 1/06 - Continuously compensating for, or preventing, undesired influence of physical parameters
H03M 1/18 - Automatic control for modifying the range of signals the converter can handle, e.g. gain ranging
A microelectronic device includes a galvanic isolation device on a silicon substrate and a semiconductor device on a semiconductor substrate. The galvanic isolation device includes a lower isolation element over the silicon substrate and an upper isolation element above the lower isolation element, separated by a dielectric plateau that comprises inorganic dielectric material extending from the lower isolation element to the upper isolation element. The galvanic isolation device includes lower bond pads connected to the lower isolation element adjacent to the dielectric plateau, and upper bond pads over the dielectric plateau, connected to the upper isolation element. The semiconductor device includes an active component, and device bond pads coupled to the active component. The microelectronic device includes first electrical connections to the lower bond pads and second electrical connections to the upper bond pads. The first electrical connections or the second electrical connections are connected to the device bond pads.
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
H01F 27/32 - Insulating of coils, windings, or parts thereof
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 27/01 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate comprising only passive thin-film or thick-film elements formed on a common insulating substrate
55.
BOOST CONVERTER WITH WIDE AVERAGE CURRENT LIMITING RANGE
A boost converter that provides a wide average current limiting range includes a switch coupled to an inductor output and a power input, a diode coupled to the inductor output and an output terminal load and configured to conduct current in only one direction away from the inductor output and toward the output terminal, a clamp circuit coupled to the diode and the switch, and a minimum time off module coupled to the diode and the switch. The clamp circuit is configured to clamp an inductor output current to a reference current while the converter is operating in a continuous conduction mode (CCM) of operation. The minimum time off module is configured to cause the inductor output current to be zero for at least a time Toff while the converter is operating in a pulse frequency modulation (PFM) mode of operation.
H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion
In some examples, a semiconductor package includes a semiconductor die; a conductive member coupled to the semiconductor die; and a multi-layer package substrate. The multi-layer package substrate includes a first horizontal metal layer to provide a ground connection; a second horizontal metal layer above the first horizontal metal layer; vertical members coupling to the first and second horizontal metal layers; and a mold compound covering the first and second horizontal metal layers and the vertical members. The first horizontal metal layer, the second horizontal metal layer, and the vertical members together form a structure including a conductive strip coupled to the conductive member, a transition member coupled to the conductive strip, a waveguide coupled to the transition member, and a horn antenna coupled to the waveguide.
A current limiter includes a gain adjustment circuit designed to change the response time (e.g., operation mode) of the current limiter. The current limiter may be designed to operate at different selectable speed modes (e.g., slow mode, fast mode) that affect how quickly the current limiter responds to an overcurrent stimulus. The speed modes may be selected by choosing between different current mirror arrangements in the gain adjustment circuit. Regardless of which mode of operation is selected for the current limiter, a speedup circuit may also be implemented, which includes a switch to initiate a nonlinear speedup of the response time after a certain overcurrent stimulus is received.
H02H 9/02 - Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess current
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
A semiconductor package includes a multilayer package substrate including a top layer including a top dielectric layer and a top metal layer providing a top portion of pins on top filled vias, and a bottom layer including a bottom dielectric layer and a bottom metal layer on bottom filled vias that provide externally accessible bottom side contact pads. The top dielectric layer together with the bottom dielectric layer providing electrical isolation between the pins. And integrated circuit (IC) die that comprises a substrate having a semiconductor surface including circuitry, with nodes connected to bond pads with bonding features on the bond pads. An electrically conductive material interconnect provides a connection between the top side contact pads and the bonding features. At least a first pin includes at least one bump stress reduction structure that includes a local physical dimension change of at least 10% in at least one dimension.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
A microelectronic device includes a galvanic isolation component having a lower isolation element over a substrate with lower bond pads connected to the lower isolation element, a dielectric plateau over the lower isolation element that does not extend to the lower bond pads, and an upper isolation element and upper bond pads over the dielectric plateau. The upper bond pads are laterally separated from the lower bond pads by an isolation distance. The microelectronic device includes high voltage wire bonds on the upper bond pads that extend upward, within 10 degrees of vertical, for a vertical distance greater than the isolation distance. The microelectronic device further includes low voltage wire bonds on the lower bond pads that have a loop height directly over a perimeter of the substrate that is less than 5 times a wire diameter of the low voltage wire bonds.
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different main groups of groups , or in a single subclass of , , e.g. forming hybrid circuits
A method and a video processor for preventing start code confusion. The method includes aligning bytes of a slice header relating to slice data when the slice header is not byte aligned or inserting differential data at the end of the slice header before the slice data when the slice header is byte aligned, performing emulation prevention byte insertion on the slice header, and combine the slice header and the slice data after performing emulation prevention byte insertion.
H04N 19/70 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by syntax aspects related to video coding, e.g. related to compression standards
In examples, an electronic device includes an antenna and a transmitter line. The transmitter line includes a double-tuned transformer having first and second windings, the first winding having first and second ends, the second winding having third and fourth ends, and the third end coupled to the antenna. The transmitter line includes a first capacitor coupled between the first and second ends. The transmitter line also includes a second capacitor coupled between the third and fourth ends, and a switch coupled between the first end and a reference terminal.
A device configured to communicate via a Wi-Fi channel obtains a contention-free access period on the Wi-Fi channel. The device sends a first probe packet to a receiving Wi-Fi device during the contention-free access period, with at least one parameter of a Wi-Fi transmitter of the Wi-Fi transceiver set to a first setting, and waits for a first reply period. The device sends a second probe packet to the receiving Wi-Fi device during the contention-free access period, with the at least one parameter of the Wi-Fi transmitter set to a second setting, where the second setting is based on a result of the first reply period, and waits for a second reply period. The device sets the at least one parameter of the Wi-Fi transmitter to a data packet setting, where the data packet setting is based at least on a result of the second reply period.
A network communications receiver and a method of operating the same in symbol timing recovery and equalization adaptation. A data converter (308) samples a received analog signal (AIN) at an initialization frequency (/init) higher than the symbol frequency of the received signal, and converts the samples to a digital sample stream. A decision feedback equalizer (320) including a digital filter (325) with one or more tap weights is adapted, and an error measurement (MSE) obtained from the output of the decision feedback equalizer. In response to the error measurement crossing an error threshold value (ALSEnir seq), a timing loop including timing error detection (350) is initiated to adjust the phase of the sampling clock (SCLK) applied to the data converter.
A multi-phase buck-boost converter (101) includes a first half-bridge circuit (107), a second half¬ bridge circuit (115), a third half-bridge circuit (111), and a control circuit (130). The first half-bridge circuit (107) is coupled to a first inductor terminal (123). The second half-bridge circuit (115) is coupled to a second inductor terminal (127). The third half-bridge circuit (111) is coupled to a third inductor terminal (125), a system voltage terminal (104), and a battery terminal (106). The control circuit (130) is coupled to the first half-bridge circuit (107), the second half-bridge circuit (115), and the third half-bridge circuit (111). The control circuit (130) is configured to transition the first half¬ bridge circuit (107), the second half-bridge circuit (115), and the third half-bridge circuit (111) from operation in a buck mode to operation in a buck-boost mode based on an off-time of the first half¬ bridge circuit (107) being less than a particular time.
H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
An example method includes fonning and patterning an etch assist layer on a first dielectric layer such that the etch assist layer is not over a first bond pad (504); forming and patterning a first photoresist layer on a second patterned conductive layer on the first dielectric, where the first photoresist layer is not over the first bond pad (506) and etching the second dielectric layer to a depth of 5 to 15% of a thickness of the first dielectric layer and the second dielectric layer (514); etching the first dielectric layer and second dielectric layer using a second photoresist layer to a depth of 20 to 25%; and exposing the first bond pad by etching the first dielectric layer using a patterned third photoresist layer, such that an area of the dielectric layer exposed by the third opening adjacent to the bond pad is between 3-5pm thick.
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
In some examples, a semiconductor package (100) includes a semiconductor die (98); a conductive member (102) coupled to the semiconductor die; and a multi-layer package substrate. The multi-layer package substrate includes a first horizontal metal layer (104) to provide a ground connection; a second horizontal metal layer (105) above the first horizontal metal layer; vertical members (108B,108D, 110B, 110D, 112B, 112D) coupling to the first and second horizontal metal layers; and a mold compound covering the first and second horizontal metal layers and the vertical members. The first horizontal metal layer, the second horizontal metal layer, and the vertical members together form a structure including a conductive strip (106) coupled to the conductive member, a transition member (108) coupled to the conductive strip, a waveguide (110) coupled to the transition member, and a horn antenna (112) coupled to the waveguide.
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different main groups of groups , or in a single subclass of , , e.g. forming hybrid circuits
H01Q 1/22 - Supports; Mounting means by structural association with other equipment or articles
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
67.
REVERSE RECOVERY PROTECTION IN A SWITCHING VOLTAGE CONVERTER
A voltage regulator control circuit includes a transistor input controller (404). The transistor input controller (404) forces a slew control signal on its slew control output to a state responsive to a change in a load condition and forces an ON signal to a state on its first transistor control output. A first transistor (HS) has a first control input and first and second current terminals. A second transistor (LS) couples to the first transistor. A driver (406) has a slew control input, a driver input, and a driver output. The driver input couples to the first transistor control output. The driver output couples to the first control input. Responsive to a first state of the slew control signal and a first state of the ON signal, the driver (406) provides a higher current to the first control input, and responsive to a second state of the slew control signal and a first state of the ON signal, the driver (406) provides a lower current to the first control input.
H02M 3/155 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
H02M 1/32 - Means for protecting converters other than by automatic disconnection
A processor (100) with instruction storage (114) configured to store processor instructions, data storage (120) configured to store processor data representing an array, the array including plural data elements, a controller (102), and an instruction pipeline (104). The instruction pipeline includes: a load stage circuit (126) configured to load an array element from the data storage, a compare stage circuit (128) configured to compare the array element to a reference value, a store stage circuit (130) configured to store a set of results that includes a result of the comparison of the array element to the reference value, and a loop hit detect stage circuit (132) configured to determine whether any of the set of results is associated with a hit on the reference value.
A microelectronic device (100) includes a buried trench capacitor (170) below an electronic component (174) of the microelectronic device (100). In one embodiment, the buried trench capacitor (170) may be formed between a silicon oxide capped p-type buried trench capacitor polysilicon region (126) and a buried trench capacitor deep n-type region (108) separated by buried trench capacitor liner dielectric (124). In a second embodiment, the buried trench capacitor (170) may be formed by a buried trench capacitor polysilicon region (126) and a p-type silicon epitaxial region (106) separated by a buried trench capacitor liner dielectric (124). One terminal of the deep trench capacitor (170) is made through the substrate (102) via a deep trench substrate contact (134). The second terminal of the deep trench capacitor (170) is made via a well contact that connects to the capacitor (170) through a deep well region in one embodiment and through a polysilicon layer in a second embodiment.
H01L 29/94 - Metal-insulator-semiconductors, e.g. MOS
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
70.
Hold time improved low area flip-flop architecture
In an example, a scan flip-flop includes a first transistor and a second transistor coupled to a data input. The scan flip-flop includes a third transistor coupled to a clock input and a fourth transistor coupled to an inverse clock input. The scan flip-flop includes a fifth transistor coupled to a scan enable input and the first transistor, and includes a sixth transistor coupled to an inverse scan enable input and the second transistor. The scan flip-flop includes an input multiplexer that includes a seventh transistor and eighth transistor coupled to the scan data input, a ninth transistor coupled to the scan enable input, and a tenth transistor coupled to the inverse scan enable input. The input multiplexer includes a first diode-connected transistor coupled between a first voltage rail and the seventh transistor, and includes a second diode-connected transistor coupled between a second voltage rail and the eighth transistor.
An electronic device includes a leadframe including a die pad and contacts, where a die attached is to the die pad. Wire bonds are attached from the die to the contacts and a mold compound overlies the leadframe and encapsulates the die and the wire bonds. The mold compound has angled side surfaces that extend from a top of the mold compound to a bonding surface of the contacts. The contacts extend from the angled side surfaces in a range of approximately 100 to 300 um.
A circuit includes a plurality of first stage integrators. Each of the plurality of first stage integrators includes a first input, a second input, a third input and an output. The first input of each of the plurality of first stage integrators is coupled to a different one of circuit inputs, the second input is coupled to a first reference input, the third input is coupled to a second reference input and the output of each of the plurality of first stage integrators is coupled to the first input of such first stage integrator. The circuit includes a second stage integrator which includes a first input coupled to each of the first inputs of the plurality of first stage integrators, a second input coupled to the first reference input, and an output coupled to the first input of the second stage integrator.
A Group III-V semiconductor device and a method of fabricating the same including an in-situ surface passivation layer. A two-stage cleaning process may be effectuated for cleaning a reactor chamber prior to growing one or more epitaxial layers and forming subsequent surface passivation layers, wherein a first cleaning process may involve a remotely generated plasma containing fluorine-based reactive species for removing SiXNY residual material accumulated in the reactor chamber and/or over any components disposed therein.
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
C23C 16/30 - Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating
C30B 25/08 - Reaction chambers; Selection of materials therefor
An integrated circuit including a comparator having an enable signal input and an output and timing circuitry. The timing circuitry includes a first transistor having a control terminal, a second transistor having a control terminal, a first inverter having an input coupled to the control terminal of the second transistor and having an output coupled to the enable signal input, and a second inverter having an input coupled to the output of the comparator and having an output coupled to the control terminal of the first transistor.
Barrier layers for anisotropic magneto-resistive (AMR) sensors integrated with semiconductor circuits and methods of making the same are described. The AMR sensors includes a NiFe alloy layer disposed over a dielectric layer. The NiFe alloy layer is in contact with a conductive via coupled to the semiconductor circuits in a substrate underneath the AMR sensor. A barrier layer is formed on the dielectric layer to prevent Ni or Fe atoms from diffusing through the dielectric layer toward the semiconductor circuits. Further, a sacrificial layer is used to facilitate forming a planarized surface with ends of the conductive vias exposed without compromising the barrier layer.
G01D 5/16 - Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using electric or magnetic means influencing the magnitude of a current or voltage by varying resistance
G01D 5/18 - Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using electric or magnetic means influencing the magnitude of a current or voltage by varying effective impedance of discharge tubes or semiconductor devices
In one example, a neural network processor comprises a memory interface, an instruction buffer, a weights buffer, an input data register, a weights register, an output data register, a computing engine, and a controller. The controller is configured to: receive a first instruction from the instruction buffer; responsive to the first instruction, fetch input data elements from the memory interface to the input data register, and fetch weight elements from the weights buffer to the weights register. The controller is also configured to: receive a second instruction from the instruction buffer; and responsive to the second instruction: fetch the input data elements and the weight elements from, respectively, the input data register and the weights register to the computing engine; and perform, using the computing engine, computation operations between the input data elements and the weight elements to generate output data elements.
In one example, a neural network processor comprises an input data register, a weights register, a computing engine configurable to perform multiplication and accumulation (MAC) operations between input data elements of a range of input precisions and weight elements of a range of weight precisions, and a controller. The controller is configured to: receive a first indication of the particular input precision and a second indication of the particular weight precision, and configure the computing engine based on the first and second indications. The controller is also configured to, responsive to an instruction: fetch input data elements and weight elements to the computing engine; and perform, using the computing engine configured based on the first and second indications, MAC operations between the input data elements at the particular input precision and the weight elements at the particular weight precision to generate intermediate output data elements.
G06F 7/544 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices for evaluating functions by calculation
In one example, a neural network processor comprises a memory interface (534), an instruction buffer (520), a weights buffer (526), an input data register (528a), a weights register (528b), an output data register (528a), a computing engine (524), and a controller (522). The controller is configured to: receive a first instruction from the instruction buffer; responsive to the first instruction, fetch input data elements from the memory interface to the input data register, and fetch weight elements from the weights buffer to the weights register. The controller is also configured to: receive a second instruction from the instruction buffer; and responsive to the second instruction: fetch the input data elements and the weight elements from, respectively, the input data register and the weights register to the computing engine; and perform, using the computing engine, computation operations between the input data elements and the weight elements to generate output data elements.
A circuit includes a processing circuit. The processing circuit is configured to model a battery using a battery model. The battery model includes: a voltage terminal, an RC stage having a first resistor and a first capacitor in parallel, a second resistor, a second capacitor and a ground terminal. The second resistor is coupled between the voltage terminal and the RC stage. The RC stage is coupled between the second resistor and the second capacitor. The second capacitor is coupled between the RC stage and the ground terminal. The processing circuit is also configured to determine a first resistance of the first resistor based on a first ratio of the first resistance to a total battery resistance, determine a second resistance of the second resistor based on a second ratio of the second resistance to the total battery resistance, and determine the total battery resistance.
In one example, a neural network processor comprises a computing engine and a post-processing engine, the post-processing engine configurable to perform different post-processing operations for a range of output precisions and a range of weight precisions. The neural network processor further comprises a controller configured to: receive a first indication of a particular output precision, a second indication of the particular weight precision, and post-processing parameters; and configure the post-processing engine based on the first and second indications and the first and second post-processing parameters. The controller is further configured to, responsive to a first instruction, perform, using the computing engine, multiplication and accumulation operations between input data elements and weight elements to generate intermediate data elements. The controller is further configured to, responsive to a second instruction, perform, using the configured post-processing engine, post-processing operations on the intermediate data elements to generate output data elements.
Systems and articles of manufacture provide an efficient safety mechanism for signal processing hardware. An example system includes a hardware accelerators, including a first hardware accelerator, and a second hardware accelerator coupled to the first hardware accelerator. Each of the first and second hardware accelerators includes a protected memory and an unprotected memory, and at least one of the hardware accelerators has an outlier filter. The system also includes a memory coupled to the hardware accelerators; and interface protectors, including a first interface protector coupled between the first hardware accelerator and the memory; a second interface protector coupled between the first hardware accelerator, the memory, and the second hardware accelerator; and a third interface protector coupled between the second hardware accelerator and the memory.
G06V 10/98 - Detection or correction of errors, e.g. by rescanning the pattern or by human intervention; Evaluation of the quality of the acquired patterns
G06F 11/07 - Responding to the occurrence of a fault, e.g. fault tolerance
G06V 10/36 - Applying a local operator, i.e. means to operate on image points situated in the vicinity of a given point; Non-linear local filtering operations, e.g. median filtering
A semiconductor device includes a source region. A drain region has a first conductivity type and a second dopant concentration spaced apart from the source region. A first drift region is located between the source region and the drain region and has the first conductivity type and a first dopant concentration that is lower than the second dopant concentration of the drain region. An oxide structure includes a first portion on or over the first drift region and a tapered portion between the first portion and the drain region. A substrate surface extension is between the tapered portion and the drain region. A buffer region has the first conductivity type between the first drift region and the drain region and under the tapered portion of the oxide structure. The buffer region has a third dopant concentration between the second dopant concentration and the first dopant concentration.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
A digital signal processor having a CPU with a program counter register and, optionally, an event context stack pointer register for saving and restoring the event handler context when higher priority event preempts a lower priority event handler. The CPU is configured to use a minimized set of addressing modes that includes using the event context stack pointer register and program counter register to compute an address for storing data in memory. The CPU may also eliminate post-decrement, pre-increment and post-decrement addressing and rely only on post-increment addressing.
Techniques of fabricating shallow trench isolation structures that reduce or minimize the number of trench cones during the formation of shallow trenches. The disclosed techniques introduce separate etch steps for etching shallow trenches with small feature dimensions and for etching shallow trenches with large feature dimensions. As an example, the disclosed techniques involve etching a first shallow trench in a first region of a substrate with a first etching parameter, and etching a second shallow trench in a second region of a substrate with a second etching parameter different from the first etching parameter. Among other things, the etching parameter may include an etching selectivity ratio of silicon to an etch retardant that contributes to cone formations. Because of the separate etch steps, the disclosed techniques allow the sidewall slopes between the first and second shallow trenches to be within a few degrees of deviation.
A monitoring circuit for a photovoltaic module includes a measurement conditioning circuit, a microcontroller circuit, and a transmitter circuit. The measurement conditioning circuit includes a voltage sense terminal, a voltage reference terminal, and a digital measurement data output. The microcontroller circuit includes a digital measurement data input coupled with the digital measurement data output, a modulation clock input, a measurement data stream output, and a transmit select output. The transmitter circuit includes a measurement data stream input coupled with the measurement data stream output, a modulation clock output coupled with the modulation clock input, a transmit select input coupled with the transmit select output, and positive and negative output communication terminals.
H04Q 9/00 - Arrangements in telecontrol or telemetry systems for selectively calling a substation from a main station, in which substation desired apparatus is selected for applying a control signal thereto or for obtaining measured values therefrom
G01K 1/024 - Means for indicating or recording specially adapted for thermometers for remote indication
G01K 7/00 - Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat
H02S 50/00 - Monitoring or testing of PV systems, e.g. load balancing or fault identification
86.
CABAC Decoder with Decoupled Arithmetic Decoding and Inverse Binarization
An encoded bitstream of entropy encoded video data is received by a video decoder. The encoded bitstream represents syntax elements of a sequence of coding blocks. The sequence of coding blocks is recovered by processing a bin sequences associated with each coding block in a processing pipeline, wherein a defined amount of time is allocated to process each coding block in the processing pipeline. The encoded bitstream is arithmetically decoded to produce each bin sequence. The arithmetic decoder is time-wise decoupled from the processing pipeline by storing a plurality of the bin sequences in a buffer memory.
H04N 19/436 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals - characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation using parallelised computational arrangements
H04N 19/44 - Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
H04N 19/61 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding in combination with predictive coding
H04N 19/70 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by syntax aspects related to video coding, e.g. related to compression standards
H04N 19/91 - Entropy coding, e.g. variable length coding [VLC] or arithmetic coding
A method for pairing a key fob with a control unit is provided. The key fob executes an ID authenticated key agreement protocol with a pairing device based on a key fob identification to authenticate one another and to generate a first encryption key. The pairing device encrypts a control unit identification using the first encryption key. The key fob receives the encrypted control unit identification transmitted from the pairing device. The key fob then executes an ID authenticated key agreement protocol with the control unit based on the control unit identification to authenticate one another and to generate a second encryption key. The key fob then receives an operational key transmitted from the control unit that is encrypted with the second encryption key.
H04L 9/14 - Arrangements for secret or secure communications; Network security protocols using a plurality of keys or algorithms
H04L 9/32 - Arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system
Systems and methods are provided in which two types of trace modes may be used at different times to trace events that occur during execution of an instruction program by a processor core. One such system includes execution trace circuitry that, when triggered, traces a sequence of events that occur during execution of the instruction program, and generates trace information indicative of the sequence of events. In response to a first trigger signal, the execution trace circuitry traces a first set of events in the sequence of events using a first trace mode, in which cycle information for the first set of events is not provided; and in response to a second trigger signal, the execution trace circuitry traces a second set of events in the sequence of events using a second trace mode, in which cycle information for the second set of events is provided.
High-speed data communication devices, e.g., repeaters, interfacing between a host and a peripheral operate such that high-speed components except for a host-side squelch detector are set or maintained in a deactivated state during an idle period of a micro frame. In an example, a start of a micro frame is detected on a data bus during a first time period. In a second time period after the first time period, the high-speed communication device determines whether at least one data packet is contained in the micro frame. When it is determined during the second time period that no data packet is contained in the micro frame, active components, except a squelch detector, are controlled to be inactive during a third time period after the second time period.
A caching system including a first sub-cache, and a second sub-cache, coupled in parallel with the first cache, for storing cache data evicted from the first sub-cache and write-memory commands that are not cached in the first sub-cache, and wherein the second sub-cache includes: color tag bits configured to store an indication that a corresponding cache line of the second sub-cache storing write miss data is associated with a color tag, and an eviction controller configured to evict cache lines of the second sub-cache storing write-miss data based on the color tag associated with the cache line.
G06F 12/128 - Replacement control using replacement algorithms adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel
G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
G06F 12/0802 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
G06F 12/0804 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
G06F 12/0806 - Multiuser, multiprocessor or multiprocessing cache systems
G06F 12/0811 - Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
G06F 12/0817 - Cache consistency protocols using directory methods
G06F 12/0853 - Cache with multiport tag or data arrays
G06F 12/0855 - Overlapped cache accessing, e.g. pipeline
G06F 12/0864 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing
G06F 12/0884 - Parallel mode, e.g. in parallel with main memory or CPU
G06F 12/0888 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using selective caching, e.g. bypass
G06F 12/0891 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
G06F 12/0895 - Caches characterised by their organisation or structure of parts of caches, e.g. directory or tag array
G06F 12/0897 - Caches characterised by their organisation or structure with two or more cache hierarchy levels
G06F 12/121 - Replacement control using replacement algorithms
G06F 12/126 - Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning
G06F 12/127 - Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning using additional replacement algorithms
G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
G06F 15/80 - Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
G11C 7/22 - Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
G11C 29/42 - Response verification devices using error correcting codes [ECC] or parity check
G11C 29/44 - Indication or identification of errors, e.g. for repair
91.
MATHEMATICAL CALCULATIONS WITH NUMERICAL INDICATORS
One example includes a method for assigning numerical indicators that each define a respective numerical format in a mathematical calculation. The method includes receiving a mathematical expression as an input. The mathematical expression includes at least one expression term. The method also includes assigning a first numerical indicator to each of the expression term(s) and performing at least one mathematical calculation provided by the mathematical expression to obtain a mathematical solution comprising at least one solution term. The method also includes assigning a second numerical indicator to each of the solution term(s) based on the first numerical indicator of each of the at least one expression term and based on rules defined in an indicator priority rule-set. The method further includes displaying each of the at least one solution term of the mathematical solution in a format corresponding to the respectively assigned second numerical indicator on a graphical display.
Examples of bandgap circuits and elements thereof enable generation of an accurate and stable bandgap reference voltage that is not affected by low current gain. An example circuit includes first and second input transistors, each having an emitter to receive a tail current; first and second core transistors, a collector of each coupled to ground; a first lower leg coupled between a first upper leg and the emitter of the first core transistor at a first current input coupled to the base of the first input transistor; a second lower leg coupled between a second upper leg and the emitter of the second core transistor at a second current input coupled to the base of the second input transistor; and a base resistor coupled between the base and collector of the first core transistor. The input transistor pair has a current density ratio that is the same as that of the core transistor pair.
An electronic device includes a semiconductor die attached to a die attach pad, a package structure having opposite first and second sides, opposite third and fourth sides spaced apart from one another along a first direction, and opposite fifth and sixth sides spaced apart from one another along an orthogonal second direction, conductive leads positioned along opposite third and fourth sides of the package structure, tie bars extending from the die attach pad and having respective ends exposed along the respective fifth and sixth sides of the package structure, and the fifth and sixth sides of the package structure each have individual indents that extend to a respective one of the third and fourth sides of the package structure.
An electronic device includes a multilevel package substrate, a semiconductor die, and a package structure, the multilevel package substrate having a first level, a second level, and a filter circuit in the first and second levels. The filter circuit includes a filter input terminal, a first capacitor, a first inductor, a second capacitor, a second inductor, a filter output terminal, and a reference terminal. The semiconductor die is attached to the multilevel package substrate and has a conductive structure coupled to one of the terminals of the filter circuit, and the package structure encloses the semiconductor die and a portion of the multilevel package substrate.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
A network communications receiver and a method of operating the same in symbol timing recovery and equalization adaptation. A data converter samples a received analog signal at an initialization frequency higher than the symbol frequency of the received signal, and converts the samples to a digital sample stream. A decision feedback equalizer including a digital filter with one or more tap weights is adapted, and an error measurement obtained from the output of the decision feedback equalizer. In response to the error measurement crossing an error threshold value, a timing loop including timing error detection is initiated to adjust the phase of the sampling clock applied to the data converter.
A transformer includes a substrate and a first metal layer having a first inductor having a first center tap. A second metal layer includes a second inductor having a second center tap, and the second metal layer includes a bond pad. A third metal layer includes a first conductor electrically connecting the bond pad to the first center tap, and the third metal layer includes a second conductor electrically connecting the bond pad and the first center tap. The third metal layer is situated between the substrate and the first metal layer, and the first metal layer is situated between the third metal layer and the second metal layer.
H01F 27/30 - Fastening or clamping coils, windings, or parts thereof together; Fastening or mounting coils or windings on core, casing, or other support
H01F 27/32 - Insulating of coils, windings, or parts thereof
In one example, an apparatus comprises first, second and third memory devices, an error detection circuit, and an error correction circuit. The error detection circuit is configured to detect a mismatch among data stored at the first, second, and third memory devices, and responsive to detecting the mismatch, provide a correction signal representing a majority state of the data. The error correction circuit is configured to write the majority state of the data into at least one of the first, second, or third memory devices responsive to the correction signal.
In one example, a neural network processor (502) comprises an input data register (528a), a weights register (528b), a computing engine (524) configurable to perform multiplication and accumulation (MAC) operations between input data elements of a range of input precisions and weight elements of a range of weight precisions, and a controller (522). The controller is configured to: receive a first indication of the particular input precision and a second indication of the particular weight precision, and configure the computing engine based on the first and second indications. The controller is also configured to, responsive to an instruction: fetch input data elements and weight elements to the computing engine; and perform, using the computing engine configured based on the first and second indications, MAC operations between the input data elements at the particular input precision and the weight elements at the particular weight precision to generate intermediate output data elements.
In one example, a neural network processor comprises a computing engine (1300) and a post-processing engine (1302), the post-processing engine configurable to perform different post-processing operations for a range of output precisions and a range of weight precisions. The neural network processor further comprises a controller configured to; receive a first indication of a particular output precision (1312), a second indication of the particular weight precision (1312), and post-processing parameters (1314); and configure the post-processing engine based on the first and second indications and the first and second post-processing parameters. The controller is further configured to, responsive to a first instruction, perform, using the computing engine, multiplication and accumulation operations between input data elements and weight elements to generate intermediate data elements. The controller is further configured to, responsive to a second instruction, perform, using the configured post-processing engine, post-processing operations on the intermediate data elements to generate output data elements.
A circuit includes a processing circuit (400). The processing circuit (400) is configured to model a battery using a battery model. The battery model includes: a voltage terminal, an RC stage having a first resistor and a first capacitor in parallel, a second resistor, a second capacitor and a ground terminal. The second resistor is coupled between the voltage terminal and the RC stage. The RC stage is coupled between the second resistor and the second capacitor. The second capacitor is coupled between the RC stage and the ground terminal. The processing circuit is also configured to determine a first resistance of the first resistor based on a first ratio of the first resistance to a total battery resistance, determine a second resistance of the second resistor based on a second ratio of the second resistance to the total battery resistance, and determine the total battery resistance.
G01R 31/367 - Software therefor, e.g. for battery testing using modelling or look-up tables
G01R 31/396 - Acquisition or processing of data for testing or for monitoring individual cells or groups of cells within a battery
G01R 31/382 - Arrangements for monitoring battery or accumulator variables, e.g. SoC
G01R 31/385 - Arrangements for measuring battery or accumulator variables
G01R 27/26 - Measuring inductance or capacitance; Measuring quality factor, e.g. by using the resonance method; Measuring loss factor; Measuring dielectric constants
