A circuit (300) includes a plurality of first stage integrators (106 (1,1) - 106(2,1)). Each of the plurality of first stage integrators (106 (1, 1 ) - 106(2, 1 )) includes a first input (324 ), a. second input (326), a third input (322) and an output (328). The first input (324) of each of the plurality of first stage integrators is coupled to a. different one of circuit inputs (304), the second input (326) is coupled to a first reference input, the third input (322) is coupled to a second reference input and the output (328) of each of the plurality of first stage integrators is coupled to the first input (324) of such first stage integrator. The circuit (300) includes a second stage integrator ( 108(1)) which includes a first input (386) coupled to each of the first inputs of the plurality' of first stage integrators, a second input. (388) coupled to the first reference input, and an output (392) coupled to the first input (386) of the second stage integrator (108(1)).
In examples, a semiconductor die (106) comprises a semiconductor substrate (506) having a surface (550), the surface having first and second surface portions (564, 567), and a radiator layer (206) on the surface. The radiator layer comprises a metal member (560) having a first metal member portion (563) above the first surface portion and a second metal member portion (566) above the second surface portion, a first distance between the first metal member portion and the first surface portion, and a second distance between the second metal member portion and the second surface portion, the first distance less than the second distance. The radiator layer includes first and second electrodes (555, 573). The radiator layer includes a piezoelectric layer (554) extending along a length of the radiator layer and on each of the first and second electrodes, the piezoelectric layer between the first and second metal member portions and the semiconductor substrate.
B06B 1/06 - Processes or apparatus for generating mechanical vibrations of infrasonic, sonic or ultrasonic frequency making use of electrical energy operating with piezoelectric effect or with electrostriction
3.
CURRENT LIMITER CIRCUIT WITH ADJUSTABLE RESPONSE TIME
A current limiter (104) includes a gain adjustment circuit (208) designed to change the response time (e.g., operation mode) of the current limiter. The current limiter may be designed to operate at different selectable speed modes (e.g., slow mode, fast mode) that affect how quickly the current limiter responds to an overcurrent stimulus. The speed modes may be selected by choosing between different current mirror arrangements in the gain adjustment circuit. Regardless of which mode of operation is selected for the current limiter, a speedup circuit (210) may also be implemented, which includes a switch (M5) to initiate a nonlinear speedup of the response time after a certain overcurrent stimulus is received.
In one example, an apparatus comprises first (702), second (704) and third (706) memory devices, an error detection circuit (902), and an error correction circuit (904). The error detection circuit is configured to detect a mismatch among data stored at the first, second, and third memory devices, and responsive to detecting the mismatch, provide a correction signal (910) representing a majority state of the data. The error correction circuit is configured to write the majority state of the data into at least one of the first, second, or third memory devices responsive to the correction signal.
G06F 11/14 - Error detection or correction of the data by redundancy in operation, e.g. by using different operation sequences leading to the same result
H03K 3/3565 - Bistables with hysteresis, e.g. Schmitt trigger
5.
BOOST CONVERTER WITH WIDE AVERAGE CURRENT LIMITING RANGE
H02M 3/155 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion
A microelectronic device (100) including an isolation device (101). The isolation device (101) includes a lower isolation element (119), an upper isolation element (148), and an inorganic dielectric plateau (152) between the lower isolation element (119) and the upper isolation element (148). The inorganic dielectric plateau (152) contains an upper etch stop layer (136) and a lower etch stop layer (129) between the upper isolation element (148) and the lower isolation element (119). The upper etch stop layer (136) provides an end point signal during the plateau etch process (161) which provides feedback on the amount of inorganic dielectric plateau (152) etched. The lower etch stop layer (129) provides an etch stop function, ensuring a complete plateau etch (161) and protecting an underlying metal bond pad (122). The inorganic dielectric plateau (152) contains alternating layers of high stress silicon dioxide (141) and low stress silicon dioxide (132) which, provide a means of reinforcement of the inorganic dielectric plateau (152)
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
A processor (100) with instruction storage (114) configured to store processor instructions, data storage (120) configured to store processor data representing an array, the array including plural data elements, a controller (102), and an instruction pipeline (104). The instruction pipeline includes: a load stage circuit (126) configured to load an array element from the data storage, a compare stage circuit (128) configured to compare the array element to a reference value, a store stage circuit (130) configured to store a set of results that includes a result of the comparison of the array element to the reference value, and a loop hit detect stage circuit (132) configured to determine whether any of the set of results is associated with a hit on the reference value.
A microelectronic device (100) includes a buried trench capacitor (170) below an electronic component (174) of the microelectronic device (100). In one embodiment, the buried trench capacitor (170) may be formed between a silicon oxide capped p-type buried trench capacitor polysilicon region (126) and a buried trench capacitor deep n-type region (108) separated by buried trench capacitor liner dielectric (124). In a second embodiment, the buried trench capacitor (170) may be formed by a buried trench capacitor polysilicon region (126) and a p-type silicon epitaxial region (106) separated by a buried trench capacitor liner dielectric (124). One terminal of the deep trench capacitor (170) is made through the substrate (102) via a deep trench substrate contact (134). The second terminal of the deep trench capacitor (170) is made via a well contact that connects to the capacitor (170) through a deep well region in one embodiment and through a polysilicon layer in a second embodiment.
H01L 29/94 - Metal-insulator-semiconductors, e.g. MOS
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
9.
JOINT TIMING RECOVERY AND DECISION FEEDBACK EQUALIZER ADAPTATION IN WIRELINE NETWORK RECEIVERS
A network communications receiver and a method of operating the same in symbol timing recovery and equalization adaptation. A data converter (308) samples a received analog signal (AIN) at an initialization frequency (/init) higher than the symbol frequency of the received signal, and converts the samples to a digital sample stream. A decision feedback equalizer (320) including a digital filter (325) with one or more tap weights is adapted, and an error measurement (MSE) obtained from the output of the decision feedback equalizer. In response to the error measurement crossing an error threshold value (ALSEnir seq), a timing loop including timing error detection (350) is initiated to adjust the phase of the sampling clock (SCLK) applied to the data converter.
A multi-phase buck-boost converter (101) includes a first half-bridge circuit (107), a second half¬ bridge circuit (115), a third half-bridge circuit (111), and a control circuit (130). The first half-bridge circuit (107) is coupled to a first inductor terminal (123). The second half-bridge circuit (115) is coupled to a second inductor terminal (127). The third half-bridge circuit (111) is coupled to a third inductor terminal (125), a system voltage terminal (104), and a battery terminal (106). The control circuit (130) is coupled to the first half-bridge circuit (107), the second half-bridge circuit (115), and the third half-bridge circuit (111). The control circuit (130) is configured to transition the first half¬ bridge circuit (107), the second half-bridge circuit (115), and the third half-bridge circuit (111) from operation in a buck mode to operation in a buck-boost mode based on an off-time of the first half¬ bridge circuit (107) being less than a particular time.
H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
An example method includes fonning and patterning an etch assist layer on a first dielectric layer such that the etch assist layer is not over a first bond pad (504); forming and patterning a first photoresist layer on a second patterned conductive layer on the first dielectric, where the first photoresist layer is not over the first bond pad (506) and etching the second dielectric layer to a depth of 5 to 15% of a thickness of the first dielectric layer and the second dielectric layer (514); etching the first dielectric layer and second dielectric layer using a second photoresist layer to a depth of 20 to 25%; and exposing the first bond pad by etching the first dielectric layer using a patterned third photoresist layer, such that an area of the dielectric layer exposed by the third opening adjacent to the bond pad is between 3-5pm thick.
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
In some examples, a semiconductor package (100) includes a semiconductor die (98); a conductive member (102) coupled to the semiconductor die; and a multi-layer package substrate. The multi-layer package substrate includes a first horizontal metal layer (104) to provide a ground connection; a second horizontal metal layer (105) above the first horizontal metal layer; vertical members (108B,108D, 110B, 110D, 112B, 112D) coupling to the first and second horizontal metal layers; and a mold compound covering the first and second horizontal metal layers and the vertical members. The first horizontal metal layer, the second horizontal metal layer, and the vertical members together form a structure including a conductive strip (106) coupled to the conductive member, a transition member (108) coupled to the conductive strip, a waveguide (110) coupled to the transition member, and a horn antenna (112) coupled to the waveguide.
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different main groups of groups , or in a single subclass of , , e.g. forming hybrid circuits
H01Q 1/22 - Supports; Mounting means by structural association with other equipment or articles
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
13.
REVERSE RECOVERY PROTECTION IN A SWITCHING VOLTAGE CONVERTER
A voltage regulator control circuit includes a transistor input controller (404). The transistor input controller (404) forces a slew control signal on its slew control output to a state responsive to a change in a load condition and forces an ON signal to a state on its first transistor control output. A first transistor (HS) has a first control input and first and second current terminals. A second transistor (LS) couples to the first transistor. A driver (406) has a slew control input, a driver input, and a driver output. The driver input couples to the first transistor control output. The driver output couples to the first control input. Responsive to a first state of the slew control signal and a first state of the ON signal, the driver (406) provides a higher current to the first control input, and responsive to a second state of the slew control signal and a first state of the ON signal, the driver (406) provides a lower current to the first control input.
H02M 3/155 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
H02M 1/32 - Means for protecting converters other than by automatic disconnection
In one example, a neural network processor comprises a memory interface (534), an instruction buffer (520), a weights buffer (526), an input data register (528a), a weights register (528b), an output data register (528a), a computing engine (524), and a controller (522). The controller is configured to: receive a first instruction from the instruction buffer; responsive to the first instruction, fetch input data elements from the memory interface to the input data register, and fetch weight elements from the weights buffer to the weights register. The controller is also configured to: receive a second instruction from the instruction buffer; and responsive to the second instruction: fetch the input data elements and the weight elements from, respectively, the input data register and the weights register to the computing engine; and perform, using the computing engine, computation operations between the input data elements and the weight elements to generate output data elements.
In one example, a neural network processor (502) comprises an input data register (528a), a weights register (528b), a computing engine (524) configurable to perform multiplication and accumulation (MAC) operations between input data elements of a range of input precisions and weight elements of a range of weight precisions, and a controller (522). The controller is configured to: receive a first indication of the particular input precision and a second indication of the particular weight precision, and configure the computing engine based on the first and second indications. The controller is also configured to, responsive to an instruction: fetch input data elements and weight elements to the computing engine; and perform, using the computing engine configured based on the first and second indications, MAC operations between the input data elements at the particular input precision and the weight elements at the particular weight precision to generate intermediate output data elements.
In one example, a neural network processor comprises a computing engine (1300) and a post-processing engine (1302), the post-processing engine configurable to perform different post-processing operations for a range of output precisions and a range of weight precisions. The neural network processor further comprises a controller configured to; receive a first indication of a particular output precision (1312), a second indication of the particular weight precision (1312), and post-processing parameters (1314); and configure the post-processing engine based on the first and second indications and the first and second post-processing parameters. The controller is further configured to, responsive to a first instruction, perform, using the computing engine, multiplication and accumulation operations between input data elements and weight elements to generate intermediate data elements. The controller is further configured to, responsive to a second instruction, perform, using the configured post-processing engine, post-processing operations on the intermediate data elements to generate output data elements.
A circuit includes a processing circuit (400). The processing circuit (400) is configured to model a battery using a battery model. The battery model includes: a voltage terminal, an RC stage having a first resistor and a first capacitor in parallel, a second resistor, a second capacitor and a ground terminal. The second resistor is coupled between the voltage terminal and the RC stage. The RC stage is coupled between the second resistor and the second capacitor. The second capacitor is coupled between the RC stage and the ground terminal. The processing circuit is also configured to determine a first resistance of the first resistor based on a first ratio of the first resistance to a total battery resistance, determine a second resistance of the second resistor based on a second ratio of the second resistance to the total battery resistance, and determine the total battery resistance.
G01R 31/367 - Software therefor, e.g. for battery testing using modelling or look-up tables
G01R 31/396 - Acquisition or processing of data for testing or for monitoring individual cells or groups of cells within a battery
G01R 31/382 - Arrangements for monitoring battery or accumulator variables, e.g. SoC
G01R 31/385 - Arrangements for measuring battery or accumulator variables
G01R 27/26 - Measuring inductance or capacitance; Measuring quality factor, e.g. by using the resonance method; Measuring loss factor; Measuring dielectric constants
18.
MULTIPLE PRIMARY NODES FOR WIRELESS BATTERY MANAGEMENT SYSTEM ROBUSTNESS
A system (500) includes a first plurality of secondary devices (550), each secondary device (550) of the first plurality of secondary devices including a first wireless transmitter and a battery monitor integrated circuit (IC). The battery monitor IC is configured to obtain battery data from at least one battery cell, and the first wireless transmitter is configured to wirelessly transmit the battery data. A first primary device (502) has a second wireless transmitter wirelessly coupled to the first wireless transmitters of the first plurality of secondary devices via a first wireless network. A second primary device (506) has a second wireless transmitter. The second primary device (506) is configured to detect a fault with the first primary device and, in response detection of the fault, to establish a second wireless network with the first plurality of secondary devices.
H04Q 9/00 - Arrangements in telecontrol or telemetry systems for selectively calling a substation from a main station, in which substation desired apparatus is selected for applying a control signal thereto or for obtaining measured values therefrom
G08C 25/00 - Arrangements for preventing or correcting errors; Monitoring arrangements
H01M 10/42 - Methods or arrangements for servicing or maintenance of secondary cells or secondary half-cells
Described embodiments include a circuit (500) for filtering electromagnetic interference (EMI) that includes an electrically conductive housing (108) enclosing the circuit, a first power terminal (102) providing a first signal (IN+), and a second power terminal (104) providing a second signal (IN-), the first and second signals forming a differential power input. A filter circuit (250) provides a common mode noise cancelling signal (to 256) at an output responsive to first and second inputs (from 252 and 254). An inductive choke (120) has first and second coils that are magnetically coupled. The first coil (122) is coupled between the first power terminal and a first converter input. The second coil (124) is coupled between the second power terminal and a second converter input. A third capacitor (256) is coupled between the filter output and the second power terminal. A fourth capacitor (118) is coupled between the first power terminal and the second power terminal, and an inductor (460) is coupled between the housing and a ground terminal.
A digital-to-time converter circuit (200) includes a scrambling and noise shaping circuit (211), a digital-to-analog converter (DAC) (208), and a buffer circuit (218). The scrambling and noise shaping circuit (211) includes an input and an output. The input is coupled to a delay input terminal (114B). The scrambling and noise shaping circuit (211) is configured to generate a residue value signal that scrambles and noise shapes a mismatch error. The DAC (208) includes an input and an output. The input of the DAC (208) is coupled to the output of the scrambling and noise shaping circuit (211). The DAC (208) is configured to generate a residue timing signal based on the residue value signal that scrambles and noise shapes the mismatch error. The buffer circuit (218) includes an input and an output. The input of the buffer circuit (218) is coupled to the output of the DAC (208). The output of the buffer circuit (218) is coupled to a signal output terminal (114C).
H03M 1/82 - Digital/analogue converters with intermediate conversion to time interval
H03M 3/00 - Conversion of analogue values to or from differential modulation
H03M 7/16 - Conversion to or from unit-distance codes, e.g. Gray code, reflected binary code
H03M 1/80 - Simultaneous conversion using weighted impedances
H03M 1/08 - Continuously compensating for, or preventing, undesired influence of physical parameters of noise
G04F 10/00 - Apparatus for measuring unknown time intervals by electric means
H03L 7/08 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop
Methods of separating semiconductor dies are described. The method can separate individual semiconductor dies (115) from a semiconductor wafer (110) without using a blade. The methods include a plasma etch process (155) utilizing metal structures (145) formed on a back side of the wafer (110) as masks to remove a portion of the semiconductor wafer (110) from the back side. The portion removed by the plasma etch process (155) corresponds to the scribe lines (120) between the semiconductor dies (115). The plasma etch process (155) terminates at a dielectric layer (125) formed on a front side of the wafer (110). The dielectric layer (125) may be severed to complete the separation process. Moreover, an ultrasonic water jet process may be utilized to remove burrs of the dielectric layer (125) that has been severed.
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
22.
SWITCHING FREQUENCY CONTROL FOR INTEGRATED RESONANT HALF-BRIDGE ISOLATED DC/DC WITH BURST MODE OPERATION
A system includes a control circuit (408) having a voltage input and a control circuit output. The control circuit (408) produces a control voltage at the control circuit output having a magnitude inversely related to a magnitude of an input voltage at the input voltage input. A VCO (430) has a VCO control input and a VCO clock output. The VCO control input is coupled to the control circuit output. The VCO (430) produces a VCO clock on the VCO clock output having a frequency that is a function of the control voltage. A protection circuit (440) has a first clock input, a second clock input, and a protection circuit output. The second clock input is coupled to the VCO clock output. The protection circuit (440) generates a protection circuit output signal at the protection circuit output based on a difference in frequency between a clock signal at the first clock input and the VCO clock.
H02M 3/335 - Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
A microelectromechanical system (MEMS) switch (100) that is implemented with a coplanar waveguide (104). The MEMS switch (100) includes an input terminal (124) and an output terminal (128). The MEMS switch (100) includes a beam (132) extending between the input terminal (124) and the output terminal (128). The beam (132) includes a first edge (136) and a second edge (140) coupled to a gate (190) of the MEMS switch (100). The beam (132) includes a third edge (144) proximate the input terminal (124), the first edge (136) includes a first set of finger contacts (184) proximate a first corner of the beam (132) and a second set of finger contacts (186) proximate a second comer of the beam (132). The beam (132) includes a fourth edge (148) proximate the output terminal (128), the fourth edge (148) opposing the third edge (144). The MEMS switch (100) has a first anchor (164) coupled to the input terminal (124). The first anchor (164) includes a first segment (176) extending from a region proximate the input terminal (124) to a region overlying the first set of fingers contacts (184).
In an example, a method includes broadcasting advertising packets from a broadcaster BLUETOOTH device (1102), where the advertising packets include one or more connection parameters (1112) for one or more links (1110) in a link cluster (1106). The method also includes receiving, at the broadcaster BLUETOOTH device (1102), a link cluster coordination request from a scanner BLUETOOTH device (1104), where the link cluster coordination request includes one or more connection parameters (1112) for a link (1110) in the link cluster (1106).
H04W 4/80 - Services using short range communication, e.g. near-field communication [NFC], radio-frequency identification [RFID] or low energy communication
25.
METHODS AND APPARATUS TO REDUCE INTER-STAGE GAIN ERRORS IN ANALOG-TO-DIGITAL CONVERTERS
An example analog-to-digital converter (ADC) (100) comprising: sample and hold circuitry (120) coupled to an analog input (VIN); a first sub- ADC (130) coupled to the sample and hold circuitry (120); a multiplying digital-to-analog converter (M-DAC) (140) coupled to the first sub-ADC (130); summation circuitry (160) coupled to the sample and hold circuitry (120) and the M-DAC (140); an amplifier (170) coupled to the summation circuitry (160); a second sub- ADC (180) coupled to the amplifier (170); and reference generation circuitry (150) coupled to the first sub-ADC (130), the M-DAC (140), and the second sub-ADC (180), the reference generation circuitry (150) including: reference voltage circuitry coupled to the M-DAC (140); a first resistor coupled to the reference voltage circuitry; a second resistor coupled to the first resistor; and a capacitor coupled in parallel to the second resistor by a switch.
H03M 1/08 - Continuously compensating for, or preventing, undesired influence of physical parameters of noise
H03K 19/0944 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET
26.
SYNCHRONOUS ALIGNMENT OF MULTIPLE HIGH-SPEED DIVIDERS
A timing alignment circuit (108) includes detection circuitry (138, 142) to receive first and second output signals, and output an error sign signal indicating whether the second output signal leads or lags the first output signal and a divide ratio slip signal. The timing alignment circuit (108) also includes control and aligning circuitry (162, 164). The control circuitry (162) receives a first local sync status signal and outputs a first control signal to a first component (102). The aligning circuitry (164) receives the error sign signal and the divide ratio slip signal from the detection circuitry (138, 142) and also receives a second local sync status signal indicating when the first and second output signals are synchronized. The aligning circuitry (164) outputs a second control signal to a second component (104).
H03L 7/18 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
H03L 7/093 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
H03L 7/097 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using a comparator for comparing the voltages obtained from two frequency to voltage converters
A controller circuit (1012) is configured to receive a measurement signal (1040, 1050, 1072) representing a power converter state and receive a control signal (1062) representing a power converter resonant period. Based on the power converter state and the power converter resonant period, the controller circuit (1012) determines for a switching cycle: a charging interval, a first dead time interval, a discharging interval, and a second dead time interval. The first dead time interval is after the charging interval. The discharging interval is after the first dead time interval. The second dead time interval is after the discharging interval. The controller circuit (1012) provides a first drive signal (1030) and a second drive signal (1032) based on the charging interval, the first dead time interval, the discharging interval, and the second dead time interval.
H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion
H02M 1/42 - Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
H02M 3/00 - Conversion of dc power input into dc power output
H02M 7/219 - Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only in a bridge configuration
28.
MULTI-BIT VOLTAGE-TO-DELAY CONVERSION IN DATA CONVERTER CIRCUITRY
An analog-to-digital converter circuit (100) incorporating a multi-bit input buffer (110) having a differential input and configured to generate, at a plurality of differential outputs, a plurality of residues (VP/M9,...) of a differential input sample (VIN) relative to a corresponding plurality of zero-crossing references. Chopping stages chop the residues, for example with a pseudo-random binary sequence. The circuit further includes zero-crossing comparators (120), each with differential inputs coupled to receive one of the chopped residues. The zero-crossing comparators (120) are in an ordered sequence of zone thresholds within the input range of the circuit. Folding logic circuitry (130) has inputs coupled to outputs of the comparators, and outputs a delay domain signal (FOLDP, FOLDM) indicating a magnitude of the one of the residues relative to a nearest zone threshold. Digital stage circuitry (160) generates a digital output word representing the received input sample responsive to the comparator outputs and the delay domain signal.
A pulse generator circuit (210) includes a charge pump (114) having a charge pump output. A voltage divider (R1/R2) is coupled to the charge pump output. The voltage divider (R1/R2) has a voltage divider output. An error amplifier (116) has a first error amplifier input and a second error amplifier input. The first error amplifier input is coupled to the voltage divider output. A dependent current source circuit (220) has a first input coupled to the charge pump output, a second input coupled to the voltage divider output, and a third input coupled to the second error amplifier input. The dependent current source circuit (220) is configured to cause a current to flow from the charge pump output that is proportional to a difference between a first voltage at the voltage divider output and a second voltage at the second error amplifier input.
H03L 7/089 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
H03L 7/099 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
G11C 7/22 - Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
In an example, a wireless battery management system (200) includes one or more sets of battery cells (208). The wireless battery management system (200) includes a primary node (102) configured to broadcast a downlink packet in a first superframe. The wireless battery management system (200) also includes a first secondary node (206) coupled to a first set of battery cells (208). The first secondary node (206) is configured to receive the downlink packet and transmit a first uplink packet to the primary node (102) during the first superframe. The wireless battery management system (200) includes a second secondary node (210) coupled to a second set of battery cells (212). The second secondary node (210) is configured to receive the first uplink packet from the first secondary node (206) in the first superframe. The second secondary node (210) is also configured to transmit a second uplink packet to the primary node (102) during a second superframe.
B60L 58/12 - Methods or circuit arrangements for monitoring or controlling batteries or fuel cells, specially adapted for electric vehicles for monitoring or controlling batteries responding to state of charge [SoC]
B60L 58/18 - Methods or circuit arrangements for monitoring or controlling batteries or fuel cells, specially adapted for electric vehicles for monitoring or controlling batteries of two or more battery modules
H04W 4/48 - Services specially adapted for particular environments, situations or purposes for vehicles, e.g. vehicle-to-pedestrians [V2P] for in-vehicle communication
In an example, a method includes connecting a first BLUETOOTH device (1102) to a second BLUETOOTH device (1104) via one or more links (1110) within a link cluster (1106). The method also includes receiving a request at the first BLUETOOTH device (1102) from the second BLUETOOTH device (1104) to change one or more link connection parameters (1112) of a link (1110) within the link cluster (1106). The method includes, responsive to receiving the request, changing the link connection parameter (1112) of the link (1110) within the link cluster (1106).
H04W 4/80 - Services using short range communication, e.g. near-field communication [NFC], radio-frequency identification [RFID] or low energy communication
H04W 52/36 - Transmission power control [TPC] using constraints in the total amount of available transmission power with a discrete range or set of values, e.g. step size, ramping or offsets
A bidirectional phase shifter (200) includes a differential quadrature hybrid coupler (206), a switch network (207), and a differential reflection type phase shifter (RTFS) (204). The differential quadrature hybrid coupler (206) includes a first phase input/output (I/O) port, an inverse first phase I/O port, a second phase EO port, and an inverse second phase I/O port. The switch network (207) is coupled to the first phase EO port, the inverse first phase I/O port, the second phase I/O port, and the inverse second phase EO port. The differential RTFS (204) including a differential I/O port coupled to the switch network (207).
refref) connected between a positive voltage rail (VDD) and the second positive power terminal. A fuse (120) is connected between the positive voltage rail and the first positive power terminal.
G11C 17/16 - Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
G11C 17/18 - Auxiliary circuits, e.g. for writing into memory
34.
VARIABLE DELAY FIR FILTER FOR REFLECTION EQUALIZATION
In an example, a circuit (200) includes a first signal path (212) including a first filter (202A) having a first number of taps and having an input and an output. The circuit (200) also includes a combiner (208) having first and second inputs, the first input coupled to the output of the first filter (202A). The circuit (200) includes a second signal path (214A) coupled to the input of the first filter (202A) and to the second input of the combiner (208). The second signal path (214A) includes a gain component (206A), a delay component (204A) coupled to the gain component (206A), and a second filter (202B) having a second number of taps and coupled to the delay component (204A).
A microelectronic device (100) includes a GaN FET (102) on a substrate (104) such as silicon and a buffer layer (106) of p-type GaN semiconductor material. The GaN FET (102) includes a gate electrode extension (146) including p-type GaN semiconductor material (120) in electrical contact with the gate electrode p-type GaN stack (124). The gate electrode extension (146) including p-type GaN semiconductor material (120) in electrical contact with the gate electrode p-type GaN stack (124) may improve the GaN FET (102) characteristics such as off state leakage, subthreshold voltage and post stress Vt shift.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 21/337 - Field-effect transistors with a PN junction gate
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
In some examples, an apparatus includes a circuit configured to receive communication on a first bus (602). The circuit is also configured to provide the communication on a second bus for a first period of time (604). The circuit is also configured to monitor a duration of the providing of the communication on the second bus (606). The circuit is also configured to, responsive to the duration exceeding a threshold amount, stop providing the communication on the second bus for a second period of time (608).
In a described example, an apparatus (100) includes: a semiconductor device (102) mounted to a device side surface (115) of a package substrate (104), the package substrate having a board side surface (105) opposite the device side surface; an antenna module (108) mounted to the package substrate and coupled to the semiconductor device; and mold compound (103) covering the semiconductor device and a portion of the package substrate.
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different main groups of groups , or in a single subclass of , , e.g. forming hybrid circuits
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01Q 1/22 - Supports; Mounting means by structural association with other equipment or articles
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
In some examples, a circuit (104) includes a phase frequency detector (PFD) (206) having a first input, a second input, and an output. The circuit also includes a control circuit (208) having an input and an output, the control circuit input coupled to the output of the PFD. The circuit also includes a modulation circuit (210) having an input and an output, the modulation circuit input coupled to the output of the control circuit. The circuit also includes an oscillator (212) having an oscillator input and an oscillator output, the oscillator input coupled to the output of the modulation circuit and the output of the oscillator coupled to the second input of the PFD.
H03L 7/093 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
H03L 7/18 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
_sense_sense) representative of a current in a load (106) adapted to be driven in response to the first and second pulse width modulation signals, and circuitry (114) coupled to the input for adjusting the dead time periods in response to the signal representative of a current.
A system (100) for handling requests that includes a set of memory banks (109) coupled to a memory controller (103) which comprises a set of read queues (105 and 107), including a read queue currently designated as the priority read queue (105 or 107). The memory controller (103) loads read requests from an associated processor (101) into the set of read queues (105 and 107). To process the read requests, the memory controller (103) is configured to schedule the read requests of the priority read queue (105 or 107) based on an availability of the associated memory bank (109), and if not in the priority read queue (105 or 107), also based on whether the read requests conflict with a recently scheduled read request from the priority read queue (105 or 107). Upon an execution of a read request from the priority read queue (105 or 107), the memory controller (103) designates a different one of the set of read queues (105 and 107) as the priority read queue (105 or 107), if the read request was at a front of the priority read queue (105 or 107).
In examples, a device (100) comprises control logic (129) configured to detect an idle cycle, an operand generator (140) configured to provide a synthetic operand responsive to the detection of the idle cycle, and a computational circuit (120). The computational circuit is configured to, during the idle cycle, perform a first computation on the synthetic operand. The computational circuit is configured to, during an active cycle, perform a second computation on an architectural operand.
Described herein are systems and methods for executing multiple instruction set architectures (IS As) on a singular processing unit. In an implementation, a processor (100) that includes a first decoder (109), a second decoder (111), instruction fetch circuitry (101), and instruction dispatch circuitry (107) is configured to execute two separate instruction set architectures. In an implementation, the instruction fetch circuitry (101) is configured to fetch instructions from an associated memory. In an implementation the instruction dispatch circuitry (107) is coupled to the instruction fetch circuitry (101), the first decoder (109), and the second decoder (111) and is configured to route instructions associated with a first ISA to the first decoder (109), and route instructions associated with a second ISA to the second decoder (111).
In examples, a semiconductor package (300) comprises a semiconductor substrate (1039) including a device side having circuitry formed therein. The package also includes a conductive layer (1000) positioned above the semiconductor substrate; a patch antenna (112) coupled to the conductive layer and to the device side of the semiconductor substrate; and a mold compound (304) covering the patch antenna. The mold compound has a relative permittivity ranging from 3.4 to 3.5 and a loss tangent ranging from 0.0025 to 0.013.
H01Q 19/06 - Combinations of primary active antenna elements and units with secondary devices, e.g. with quasi-optical devices, for giving the antenna a desired directional characteristic using refracting or diffracting devices, e.g. lens
H01Q 1/22 - Supports; Mounting means by structural association with other equipment or articles
Examples of circuitry and systems and methods provide a multi-way configurable amplifier (200) to support various applications. The multi-way configurable amplifier (200) may include a reconfigurable filter (204) that comprises first and second inputs (216, 218) adapted to receive an input signal; a fully differential amplifier (FDA) (232); and first and second reconfigurable resistance-capacitance (RC) networks (234, 236). The FDA (232) has an inverting input, a non-inverting input, an inverting output, and a non-inverting output. The inverting input is coupled to the first input (216), and the non-inverting input is coupled to the second input (218). The first reconfigurable RC network (234) is coupled to the non-inverting output, and the second reconfigurable RC network (236) is selectively couplable to the inverting output. The reconfigurable filter (204) is configurable to enable operation in any of multiple modes including a single-ended mode of operation and a differential mode of operation.
In an example, a method includes obtaining, in a probing Wi-Fi device (100) a transmit opportunity (TXOP) on a Wi-Fi channel. The method also includes transmitting a probe packet from the probing Wi-Fi device (100) to a receiving Wi-Fi device (116) during the TXOP with a first antenna (114.1). The method includes receiving first feedback responsive to transmitting the probe packet with the first antenna (114.1). The method also includes transmitting the probe packet from the probing Wi- Fi (100) device to the receiving Wi-Fi device (116) during the TXOP with a second antenna (114.2). The method includes receiving second feedback responsive to transmitting the probe packet with the second antenna (114.2). The method also includes setting, by the probing Wi-Fi device (100), a transmission parameters set and a selected antenna based at least in part on the first feedback or the second feedback.
H04B 7/06 - Diversity systems; Multi-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station
46.
ADAPTING SPLIT-TRANSISTOR SWITCHING POWER SUPPLY BASED ON CONDITION
Techniques for controlling a switching converter. In an example, the converter includes a switching element and a logic circuit. The switching element includes a plurality of parallel- coupled transistors (S1a-b). The logic circuit (203) is configured to initially provide one or more gate drive signals to one or more of the parallel-coupled transistors (S1a-b), respectively, but not to all of the transistors (S1a-b). After a delay period, the logic circuit (203) is further configured to provide a respective gate drive signal to all or an otherwise larger number of the transistors (S1a-b). The initially-provided one or more gate signals is/are based on one or more conditions associated with the converter, such as RdsOn associated with the switching element and/or temperature. In this manner, a switching transistor that is adaptively-sized based on the condition(s) is initially switched to damp ringing, and a larger switching transistor (e g., all transistors in parallel) is subsequently switched for low conduction loss.
H03K 17/16 - Modifications for eliminating interference voltages or currents
H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion
H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H03K 17/12 - Modifications for increasing the maximum permissible switched current
An automatic charge/ discharge circuit is presented that allows a current mirror circuit (275) with a high capacitance to quickly and automatically charge or discharge the capacitance in order to allow for a fast start-up power supply (300). The charge/ discharge circuit (370) automatically stops charging or discharging as the voltage on the capacitance approached a desired steady state.
In one example, an integrated circuit (200) comprises: a substrate (206); a semiconductor die (104); metal interconnects (130, 132, 134, 136), the semiconductor die being mounted to the substrate via the metal interconnects; an inductor (202) mounted to the substrate; and a magnetic material (208) encapsulating the semiconductor die, the inductor, and the metal interconnects, the magnetic material including: coated metal particles (510, 512, 514, 520, 522, 524, 526, 528, 530, and 532), which are coated with a first insulation material; and a second insulation material (533), in which the coated metal particles are suspended.
H01F 1/28 - Magnets or magnetic bodies characterised by the magnetic materials therefor; Selection of materials for their magnetic properties of inorganic materials characterised by their coercivity of soft-magnetic materials metals or alloys in the form of particles, e.g. powder dispersed or suspended in a bonding agent
H01F 1/33 - Magnets or magnetic bodies characterised by the magnetic materials therefor; Selection of materials for their magnetic properties of inorganic materials characterised by their coercivity of soft-magnetic materials metallic particles having oxide skin
H01F 41/02 - Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils or magnets
In one example, an integrated circuit (200) comprises: a substrate (206); a semiconductor die (104); metal interconnects (130, 132, 134) coupled between the semiconductor die and the substrate; an insulation layer (240_l, 240_2, 240_3, 240_4) coupled between the semiconductor die and the substrate, the insulation layer surrounding the metal interconnects; an inductor (202) coupled to the substrate; and a magnetic material (208) encapsulating the semiconductor die, the inductor, the metal interconnects and the insulation layer, the magnetic material having a different material from the insulation layer.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
A short detection circuit (100) includes a first transistor (102), a switched load circuit (110), a second transistor (104), a switched capacitor circuit (120), and a comparator (130). The first transistor (102) is configured to conduct a load current. The switched load circuit (110) is coupled to the first transistor (102). The switched load circuit (110) is configured to switchably draw a test current. The second transistor (104) is coupled to the first transistor (102). The second transistor (104) is configured to conduct a sense current. The sense current includes first and second portions that are respectively representative of the load current and the test current. The switched capacitor circuit (120) is coupled to the second transistor(104). The switched capacitor circuit (120) is configured to generate a short detection voltage representative of the second portion. The comparator (130) has a first comparator input coupled to the switched capacitor circuit (120). The comparator (130) is configured to compare the short detection voltage to a short threshold voltage.
H02H 3/087 - Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition, with or without subsequent reconnection responsive to excess current for dc applications
A semiconductor device (200) is described herein. The semiconductor device comprises a silicon substrate layer (204). The semiconductor device comprises a first semiconductor layer comprising a gallium nitride layer (206), the first semiconductor layer disposed over the silicon substrate layer. The semiconductor device comprises a second semiconductor layer disposed on the first semiconductor layer, the second semiconductor layer comprising an aluminum gallium nitride layer (208). The semiconductor device comprises a first drain contact (214) extending through the second semiconductor layer and extending into the first semiconductor layer.
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
H01L 21/336 - Field-effect transistors with an insulated gate
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
A method (900) is provided. In some examples, the method includes receiving a first user input at processing circuitry (910). The method also includes determining, by the processing circuitry based on a signal from a radar sensor, movement of a user in a room after receiving the first user input (920). In addition, the method includes determining, by the processing circuitry, a first estimated location of a first wall in the room based on a first portion of the movement of the user (940). The method further includes determining, by the processing circuitry, a second estimated location of a second wall in the room based on a second portion of the movement of the user (950).
G01S 13/34 - Systems for measuring distance only using transmission of continuous waves, whether amplitude-, frequency-, or phase-modulated, or unmodulated using transmission of continuous, frequency-modulated waves while heterodyning the received signal, or a signal derived therefrom, with a locally-generated signal related to the contemporaneously transmitted signal
G01S 13/42 - Simultaneous measurement of distance and other coordinates
G01S 13/536 - Discriminating between fixed and moving objects or between objects moving at different speeds using transmission of continuous unmodulated waves, amplitude-, frequency-, or phase-modulated waves
G01S 13/58 - Velocity or trajectory determination systems; Sense-of-movement determination systems
G01S 13/72 - Radar-tracking systems; Analogous systems for two-dimensional tracking, e.g. combination of angle and range tracking, track-while-scan radar
G01S 13/89 - Radar or analogous systems, specially adapted for specific applications for mapping or imaging
In an example, a circuit (100) includes an emulated current generator (114) configured to provide an emulated current signal responsive to a charge current and a discharge current. The emulated current signal can be representative of an emulated current through an output inductor (El). A comparator (116) is configured to provide a comparator signal responsive to the emulated current signal and sensed current signal representative of a measure of current through the output inductor (El). An inductor code counter (134) is configured to adjust an inductor code count value responsive to the comparator signal. A slope of the emulated current signal can be adjusted responsive to the inductor code count value.
H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion
H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
54.
FLOATING HIGH-VOLTAGE LEVEL TRANSLATOR WITH ADAPTIVE BYPASS CIRCUIT
Techniques are described herein to enhance capability of floating level translators (100). For example, increased headroom is accomplished by adaptively bypassing the protection elements (309, 310) of the voltage level translator (100). In an example, a floating level translator (100) can translate an input signal from a low-voltage domain to a high-voltage domain. A bypass circuit (414) is coupled across the protection elements (309, 310). The bypass circuit (414) selectively engages during low-voltage operation (e.g., thereby providing a lower loss path relative to loss caused by the high-voltage protection elements (309, 310) and thus increasing the headroom swing), and disengages responsive to the high-voltage reference rail of the high-voltage domain exceeding a threshold or otherwise being high enough (e.g., greater than the potential of the low- voltage domain power rail). The bypass circuit (414) can be implemented in a relatively low- complexity manner (e.g., back-to-back high-voltage FETs) without additional signals to control low-voltage capability.
A method includes sending, by a first node to a second node during a first connection event (410), a request (430) to change a current operation frequency, wherein the request (430) is encoded in a first operation frequency (420). The method also includes sending, by the first node to the second node during the first connection event (410), a first packet (452) encoded in a second operation frequency (450), where second operation frequency (450) is different from the first operation frequency (420).
In some examples, a vehicular battery management system (BMS) comprises a set of battery cells and a secondary network node coupled to the set of battery cells. The secondary network node is configured to wirelessly receive, in a first slot (808) of a super frame (800), a unicast downlink packet (820) from a primary network node, the unicast downlink packet addressed to the secondary network node. The secondary network node is also configured to wirelessly transmit, in a second slot (809) of the super frame and responsive to the unicast downlink packet, an uplink packet (832) to the primary network node.
H04W 72/30 - Resource management for broadcast services
H04W 4/48 - Services specially adapted for particular environments, situations or purposes for vehicles, e.g. vehicle-to-pedestrians [V2P] for in-vehicle communication
B60L 58/18 - Methods or circuit arrangements for monitoring or controlling batteries or fuel cells, specially adapted for electric vehicles for monitoring or controlling batteries of two or more battery modules
Aspects of the disclosure provide for an apparatus. In an example, the apparatus (20) includes a clock switching circuit (22) coupled to oscillators (273) and one or more circuit units (230, 240, 250, 260). The clock switching circuit is configured to receive, from the oscillators, a set of frequency signals (282, 283, 284), provide an uplink primary clock signal (281) and an enable signal (285, 286) to the one or more circuit units, the enable signal determined synchronously with the uplink primary clock signal, receive, from the one or more circuit units or a clock management circuit, a clock frequency request, provide the uplink primary clock signal based on a first signal of the set of frequency signals, and according to the clock frequency request, determine whether to continue to provide the uplink primary clock signal based on the first signal or to provide the uplink primary clock signal based on a second signal of the set of frequency signals.
The description generally relates to a capacitor (124) on an integrated circuit (IC) die. In an example, a package (100) includes first (102) and second (104) IC dice. The first IC die (102) includes a first circuit (126), a capacitor (124), and a polyimide layer. The first circuit (126) is on a substrate (120). The capacitor (124) includes a bottom plate (124a) over the substrate (120) and a top plate (124b) over the bottom plate (124a). The polyimide layer is at least partially over the top plate (124b). A distance from a top surface of the top plate (124b) to a bottom surface of the polyimide layer is at least 30 % of a distance from a top surface of the bottom plate (124a) to a bottom surface of the top plate (124b). A signal path, including the capacitor (124), is electrically coupled between the first circuit (126) and a second circuit (136) in the second IC die (104), which does not include a galvanic isolation capacitor in the signal path.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
59.
METHODS, APPARATUS, AND ARTICLES OF MANUFACTURE TO IMPROVE PERFORMANCE OF NETWORKS OPERATING IN MULTIPLE FREQUENCY BANDS
An example apparatus (200) includes interface circuitry (212), memory (218) configured to store machine-readable instructions (220), and processing circuitry (202) configured to at least one of instantiate or execute the machine-readable instructions (220). The example processing circuitry (202) is configured to at least one of instantiate or execute the machine-readable instructions (220) to determine a connectivity metric for a first device synchronized with a second device and cause, via the interface circuitry (212), transmission of the connectivity metric to a third device with which the first device is not synchronized Additionally, the example processing circuitry (202) is configured to at least one of instantiate or execute the machine-readable instructions (220) to, based on a first communication from the third device, cause transmission of a second communication to the first device to cause the first device to synchronize with the third device.
An electronic device (100) includes a molded package structure (108) and a conductive lead (110, 120) partially exposed outside the package structure (108), the package structure having lateral sides (101, 102, 103, 104) extending at an angle (01, 92) that is greater than 15 degrees and 25 degrees or less to facilitate mold cavity filling during package molding and mitigate mold voids in the electronic device (100). A method of fabricating an electronic device includes attaching a die (150) to a lead frame, electrically coupling a conductive terminal of the die (150) to a conductive lead and performing a molding process using a mold having cavity sidewalls with a draft angle greater than 15 degrees and 25 degrees or less to form a package structure (108) that encloses the die (150) and partially encloses the conductive lead (110, 120).
A device (100) with a substrate (104), the substrate including opposite first (124) and second (126) surfaces, the first surface including metal pads (128), a dielectric layer between the first and second surfaces, and an opening (134) extending through the dielectric layer and connecting between the first and second surfaces, the opening including first and second ridge structures, each of the first and second ridge structure extending with a uniform cross-section along the opening.
A microelectronic device (100) includes a resistive differential alignment monitor (RD AM) (101), including a first variable-width resistor (102) and a second variable-width resistor (103), which are members of a conductor level (104). Each of the resistors (102) and (103) include a wide portion (105) and (109) and a narrow portion (107) and (111). The RD AM (101) further includes a vertical connector (113a), (113b), (115), (116a), (116b), and (118) to each of the wide portion (105) and the narrow portion (107) of the first variable- width resistor (102), and to the wide portion (109) and the narrow portion (111) of the second variable-width resistor (103). The vertical connectors (113a), (113b), (115), (116a), (116b), and (118) are members of a vertical connector level (119). Test terminals (124a), (124b), (124c), and (124d) are coupled to the vertical connectors (113a), (113b), (115), (116a), (116b), and (118). The vertical connectors (113a), (113b), and (115) to the first variable-width resistor (102) and the vertical connectors (116a), (116b), and (118) to the second variable-width resistor (103) are separated by equal distances and are oriented anti-parallel to each other. The RD AM (101) may be used to estimate a misalignment distance between the members of the vertical connector level (119) and the members of the conductor level (104).
One example includes a method for fabricating a substrate-integrated waveguide (SIW) (100). The method includes forming a first metal layer (102) on a carrier surface. The first metal layer (102) can extend along an axis (110). The method also includes forming a first metal sidewall (104) extending from a first edge of the first metal layer (102) along the axis (110) and forming a second metal sidewall (106) extending from a second edge of the first metal layer (102) opposite the first edge along the axis (110) to form a trough extending along the axis (110). The method also includes providing a dielectric material (114) over the first metal layer (102) and over the first and second metal sidewalls (104 and 106). The method further includes forming a second metal layer (108) over the dielectric material (114) and over the first and second metal sidewalls (104 and 106). The second metal layer (108) can extend along the axis (110) to enclose the SIW (100) in all radial directions along the axis (110).
A controller area network including one or more first network nodes biased from a first power supply voltage, and a second network node biased from a second, lower, power supply voltage. The second network node includes a transmitter (310a) driving a differential voltage onto bus lines (CANH, CANL) to communicate a dominant bus state at a second dominant state common mode voltage, a receiver (400) coupled to the bus lines, sense circuitry (440) to sense a common mode voltage at the bus lines, and control circuitry (450) to control a recessive state common mode voltage in response to the sensed dominant state common mode voltage.
In some examples, an apparatus includes: a ramp generation circuit (1002) having a ramp control input (1003b) and a ramp output (1003e), the ramp control input coupled to a power factor correction (PFC) output terminal; a comparator (630) having a comparator output and first and second comparator inputs, the first comparator input coupled to the ramp output, the second comparator input coupled to a PFC switch current sensing terminal; and a pulse width modulation (PWM) generation circuit (634) having a PWM control input and a PWM output, the PWM control input coupled to the comparator output, and the PWM output coupled to a PFC switch control terminal.
H02M 1/42 - Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
66.
BIASING ISOLATION REGION IN SEMICONDUCTOR SUBSTRATE
The present disclosure generally relates to biasing an isolation region in a semiconductor substrate. In an example, an integrated circuit includes a semiconductor substrate (112), a first rectifying device (212), and a second rectifying device (214). The semiconductor substrate (112) has a first region (128, 242), a second region (126, 244), and a third region (144, ISO) each being an opposite conductivity type from the semiconductor substrate (112). The first region (128, 242) and the second region (126, 244) are respective current terminals of a transistor. The first rectifying device (212) has a first positive terminal (222) and a first negative terminal (224). The first positive terminal (222) is coupled to the first region (128, 242), and the first negative terminal (224) is coupled to the third region (144, ISO) The second rectifying device (214) has a second positive terminal (226) and a second negative terminal (228). The second positive terminal (226) is coupled to a ground terminal, and the second negative terminal (228) is coupled to the third region (144, ISO).
An IC is coupled to a power stage having a first half bridge having first and second transistors and a second half bridge having third and fourth transistors. A controller (110) has a first control output to provide first-fourth control signals to the first-fourth transistors. The controller (110) asserts the first-fourth control signals to implement a state sequence. The state sequence includes a first state in which the first and fourth transistors are ON, a second state in which the first and third transistors are ON, a third state in which the second and fourth transistors are ON, and a fourth state in which the second and third transistors are ON. During each switching cycle, the controller (110) implements the first and fourth states with one of the second or third states implemented between the first and fourth states, with every n switching cycles alternating implementation of the second or third states.
H02M 3/335 - Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion
An ADC (100) includes a comparator (102) to provide a comparator output responsive to an input voltage of the ADC and a DAC output voltage; a SAR circuit (108) including a SAR that stores an n-bit digital code that is initialized at a beginning of a conversion phase of the ADC, where the SAR circuit is to update the digital code responsive to the comparator output, where an ADC output is responsive to the digital code at an end of the conversion phase; and a DAC (106) to provide the DAC output voltage responsive to the digital code and a reference voltage. The DAC includes an m-bit CDAC (204) and an (n-m)-bit RD AC (202) to provide an intermediate voltage responsive to the n-m least-significant bits of the digital code and the reference voltage. The CDAC provides the DAC output voltage responsive to the m most-significant bits of the digital code, the intermediate voltage, and reference voltage.
H03M 1/46 - Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
H03M 1/06 - Continuously compensating for, or preventing, undesired influence of physical parameters
A method (1100) of forming an integrated circuit includes first forming (1108) a resistor body and a transistor gate from a semiconductor layer over a substrate. Second, sidewall spacers are formed (1112) adjacent the resistor body and the transistor gate. Third, a silicide blocking structure is formed (1116) over at least a portion of the resistor body. And fourth, the resistor body and the transistor gate are concurrently millisecond annealed (1118).
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H10N 97/00 - Electric solid-state thin-film or thick-film devices, not otherwise provided for
In a described example, an apparatus includes: a multilayer package substrate (704) including a die mount area (721) on a die side surface and comprising power pads and ground pads on an opposing board side surface, the multilayer package substrate including post connect locations (710, 712) on the die side surface for receiving power post connects (710) and for receiving ground post connects (712) for a flip chip mounted semiconductor device, the power post connect locations and the ground post connect locations positioned in the die mount area, the power post connect locations and the ground post connect locations intermixed in the die mount area; and a semiconductor device having post connects extending from bond pads on a device side surface of the semiconductor device mounted to the die side surface of the multilayer package substrate by solder joints between the post connects and the post connect locations.
H01L 23/50 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements for integrated circuit devices
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
71.
ROUTABLE MULTILEVEL PACKAGE WITH MULTIPLE INTEGRATED ANTENNAS
Described examples include an apparatus (200) having a first antenna (207-1) and a second antenna (207-2) formed in a first layer on a first surface of a multilayer package substrate (204), the multilayer package substrate having layers including patterned conductive portions and dielectric portions, the multilayer package substrate having a second surface opposite the first surface. The apparatus also has an isolation wall (217) formed in the multilayer package substrate formed in at least a second and a third layer in the multilayer package substrate and a semiconductor die (202) mounted to the first surface of the multilayer package substrate spaced from and coupled to the first antenna and the second antenna.
An example device (105) includes: switch circuitry (106A) configured to: connect, in a first state (202) based on a control signal (118), a first switch input to a first switch output and a second switch input to a second switch output; and connect, in a second state (204) based on the control signal (118), the first switch input to the second switch output and the second switch input to the first switch output; an operational amplifier (110) configured to: generate, in response to the control signal (118), a first voltage (VI, 112) based on a gain and the connections in the first state (202); and generate, in response to the control signal (118), a second voltage (V2, 112) based on the gain and the connections in the second state (204); and an Analog to Digital Converter (ADC) (116) configured to convert the first voltage (VI, 112) and second voltage (V2, 112) into a digital value (504) based on a multiplication of the input voltage and the gain.
H03F 3/393 - Dc amplifiers with modulator at input and demodulator at output; Modulators or demodulators specially adapted for use in such amplifiers with semiconductor devices only with field-effect devices
One example includes a power supply system. The system includes a power switch configured to activate via a control voltage responsive to a first state of an activation signal to conduct current from a power rail (202) to a switching terminal (204). The system further includes a power switch deactivation driver configured to control an amplitude of the control voltage responsive to a second state of the activation signal based on a voltage difference between the power rail (202) and the switching terminal (204) to provide for a variable rate of deactivation of the power switch.
A bridgeless power factor correction (PFC) control circuit includes a non-linear current sensor (218). The non-linear current sensor (218) includes a non-linear shunt (222, 224), a comparator (228), and a reference voltage circuit (230). The non-linear shunt includes a capacitor connection terminal and a ground terminal. The comparator (228) includes a first input, a reference voltage input, and a zero- crossing detector output. The first is input coupled to the capacitor connection terminal. The reference voltage circuit (230) is coupled to the reference voltage input.
H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion
H02M 1/42 - Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
G01R 19/175 - Indicating the instants of passage of current or voltage through a given value, e.g. passage through zero
A described example (475) includes: a reconstituted semiconductor device (451) flip chip mounted on a device side surface (449) of a package substrate (453), the package substrate having terminals (457) for connecting the package substrate to a circuit board, the reconstituted semiconductor device further including: a semiconductor die (402) mounted in a dielectric layer (405) and having bond pads spaced from one another by at least a first pitch distance that is less than 100 microns; a redistribution layer (415) formed over the bond pads having conductors in passivation layers; solder bumps on the redistribution layer coupled to the bond pads of the semiconductor die, the solder bumps spaced from one another by at least a second pitch distance that is greater than the first pitch distance; and solder joints formed between the package substrate and the solder bumps, the solder joints coupling the package substrate to the semiconductor die in the reconstituted semiconductor device.
H01L 21/60 - Attaching leads or other conductive members, to be used for carrying current to or from the device in operation
H01L 25/03 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
Described embodiments include a circuit with a first amplifier (104) having first and second amplifier inputs and a first amplifier output. The first amplifier input (102) is coupled to a reference voltage terminal. The second amplifier input (106) is coupled to a voltage feedback terminal. A second amplifier (364) has third and fourth amplifier inputs and second and third amplifier outputs. The third amplifier input is coupled to the first amplifier output (112). A first switch (360) has first and second switch terminals. The second switch terminal is coupled to the fourth amplifier input. A third amplifier (370) has fifth and sixth amplifier inputs and a fourth amplifier output. The fifth amplifier input is coupled to the second amplifier output (372). The sixth amplifier input is coupled to the third amplifier output (374). A second switch (362) has a third switch terminal coupled to the fourth amplifier output, and a fourth switch terminal coupled to the first amplifier output (112).
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion
H02M 3/156 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
One example includes a passive radar receiver system (110) including an RE receiver front-end (114) to receive a wireless source signal (106) and a reflected signal (108). An antenna switch (120) of the front-end (114) switches a first antenna (116) to a receiver chain (122) during a first time to generate first radar signal data based on a combined wireless signal comprising the wireless source signal (106) and the reflected signal (108), and switches a second antenna (118) to the receiver chain (122) during a second time to generate second radar signal data based on the combined wireless signal. A signal processor (124) generates source signal data associated with the wireless source signal (106) based on the first and second radar signal data and generates reflected signal data associated with the reflected signal (108) based on the first and second radar signal data, and generates target radar data associated with a target (102) based on the source and reflected radar signal data.
G01S 7/35 - RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES - Details of systems according to groups , , of systems according to group - Details of non-pulse systems
G01S 13/00 - Systems using the reflection or reradiation of radio waves, e.g. radar systems; Analogous systems using reflection or reradiation of waves whose nature or wavelength is irrelevant or unspecified
78.
ELECTRONIC DEVICE WITH IMPROVED BOARD LEVEL RELIABILITY
An electronic device (100) includes a semiconductor die (120), a package structure (108) enclosing the semiconductor die (120), and a conductive lead (110) having first and second surfaces (131, 132). The first surface (131) has a bilayer (111, 112) exposed along a bottom side (105) of the package structure (108), and the second surface (132) is exposed along another side (101) of the package structure (108). The bilayer (111, 112) includes first and second plated layers (111, 112), the first plated layer (111) on and contacting the first surface (131) of the conductive lead (110) and the second plated layer (112) on and contacting the first plated layer (111) and exposed along the bottom side (105) of the package structure (108), where the first plated layer (111) includes cobalt, and the second plated layer (112) includes tin.
A converter includes a power stage to provide a current through a primary winding of a transformer in response to a PWM signal and to induce a current in a secondary winding of the transformer to generate an output voltage. The power stage has a switching terminal. The converter also includes a controller (260), a clamp circuit (320), and an impedance device (330). The controller (260) includes a first transistor ( Qi) coupled with a second transistor (Q3) to initiate an operational voltage during a startup mode and to provide a control voltage based on an amplitude of a switching voltage at the switching terminal during a switching mode. The clamp circuit (320) couples between the control input of the first transistor (Q) and a reference terminal and clamps a voltage at the first control input responsive to the switching voltage exceeding a clamp voltage. The impedance device (330) couples between the switching terminal and the clamp circuit (320).
H02M 1/36 - Means for starting or stopping converters
H02M 3/335 - Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
A method (600) includes receiving, by a microcontroller, a live firmware update (LFU) command from an external host (602); and downloading, by the microcontroller, an image of a new version of firmware responsive to the LFU command (604). During a first time period, the method includes initializing only variables contained in the new version that are not contained in an old version of firmware (606). During a second time period, the method includes updating one or more of an interrupt vector table, a function pointer, and/or a stack pointer responsive to the new version (608). The second time period begins responsive to completing initialization of the variables.
An integrated circuit (IC) fabrication flow including a multilevel metallization scheme where one or more metal layer members (880-1 to 880-7) of a scribelane structure (893) are formed according to one or more design constraints. A total thickness of the metal layer members (880-1 to 880-7) of the scribelane structure (893) along a dicing path may be limited to a threshold value to optimize dicing separation yields in a dicing operation.
Examples of contactor controllers, systems and methods time-modulate levels of high-side (HS) and low-side (LS) clamp voltages in a contactor controller (200) to switch a path (232, 234) through which current flows during quick-turn-off (QTO) of the contactor controller (200). One of the clamp voltages is at a high level and the other is at a low level. The output voltage of the contactor controller (200) is held at the low level. The path switching may be a function of one or more parameters. In a configuration, the level of a supply voltage of the contactor controller (200) is monitored and used to control the path switching. In a configuration, temperatures of HS and LS transistors (202, 204) of the contactor controller (200) are monitored and used to control the path switching. Control of the path switching may be performed to dissipate power in a larger area to increase thermal performance of the contactor controller. Both clamps may remain active throughout the QTO process, providing redundancy and safety.
H03K 17/042 - Modifications for accelerating switching by feedback from the output circuit to the control circuit
H03K 17/14 - Modifications for compensating variations of physical values, e.g. of temperature
H03K 17/16 - Modifications for eliminating interference voltages or currents
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
H01H 47/22 - Circuit arrangements not adapted to a particular application of the relay and designed to obtain desired operating characteristics or to provide energising current for supplying energising current for relay coil
83.
PULSE FREQUENCY MODULATOR FOR SWITCHED MODE POWER SUPPLY
In some examples, an apparatus comprises: an amplifier (404) having an amplifier output and first and second amplifier inputs, the first amplifier input coupled to a reference voltage terminal (421), and the second amplifier input coupled to a power input terminal (425); a ramp generation circuit (which is part of a switching frequency modulation circuit 408) having a reset input and a ramp output; a comparator (406) having a comparator output and first and second comparator inputs, the first comparator input coupled to the amplifier output, and the second comparator input coupled to the ramp output; and a switching signal generation circuit (412) having a circuit input and a circuit output, the circuit input coupled to the comparator output, and the circuit output coupled to a power control terminal (429).
H02M 3/156 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion
84.
ULTRA-LOW LEAKAGE DIODES USED FOR LOW INPUT BIAS CURRENT
In an example, a device (200) includes a semiconductor substrate (216) having a top surface (205). The device (200) also includes a P-doped well (210) formed in the semiconductor substrate (216) and extending downwardly from the top surface (205). The device (200) includes a cathode (208) of a diode formed by an N-doped region in the P-doped well (210). The device (200) also includes an anode (206) of the diode formed by a P-doped region, the P-doped region spaced away from the N-doped region in the P-doped well (210). The device (200) includes a deep N-type buried layer (DNBL) (214) formed in the semiconductor substrate (216), the P-doped well (210) formed between the top surface (205) and the DNBL (214). The device (200) also includes an N-doped well (220A) extending from the top surface (205) to the DNBL (214).
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
A semiconductor device (100) includes a ROM (102), a differential sense amplifier (120) and a multiplexer logic circuit (110). The ROM (102) has memory cells (104) in rows along word lines (108) and columns along bit lines (106), and a reference column having reference transistors (119) along a reference bit line (117). The multiplexer logic circuit (110) couples a selected bit line (106) to a first differential amplifier input (122) and couples the reference bit line (117) to the second differential amplifier input (124) and controls a reference current of the reference bit line (117) to be between a first bit line current of a programmed memory cell (104) and a second bit line current of an unprogrammed memory cell (104).
G11C 7/14 - Dummy cell management; Sense reference voltage generators
G11C 17/12 - Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM using field-effect devices
G11C 17/14 - Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
G11C 17/16 - Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
G11C 17/18 - Auxiliary circuits, e.g. for writing into memory
In some examples, a circuit (106) includes sensing circuitry (108), a synchronization circuit (110), and a controller (112). The sensing circuitry is configured to provide a comparison result based on a comparison between a reference voltage and a feedback voltage. The synchronization circuit is configured to synchronize the comparison result into a clock domain to form a synchronous comparison result. The controller is configured to receive the synchronous comparison result, determine a predicted gate control signal based on the synchronous comparison result, determine a gate control signal based on the synchronous comparison result, provide the predicted gate control signal to the sensing circuitry as the feedback voltage, and provide the gate control signal for controlling a power converter.
H02M 3/157 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion
The description generally relates to a bird's beak profile of a field oxide region. In an example, a semiconductor device structure includes a semiconductor substrate (202), a dielectric oxide layer (204), and a field oxide region (206). The semiconductor substrate (202) has a top surface. The dielectric oxide layer (204) is over the top surface of the semiconductor substrate (202). The field oxide region (206) is over the semiconductor substrate (202). The field oxide region (206) is connected to the dielectric oxide layer (204) through a bird's beak region. A lower surface of the bird's beak region interfaces with the semiconductor substrate (202). In a cross-section along a direction from the field oxide region (206) to the dielectric oxide layer (204), the lower surface of the bird's beak region does not have a slope with a magnitude that exceeds 0.57735, where rise of the slope is in a direction normal to the top surface of the semiconductor substrate (202).
An example system includes: a device (105) coupled to a data line (120), the device (105) configured to: send a first command on the data line (120), the first command including a first address; after sending the first command, read a first value on the data line (120), the first value including data from a first target device (110) and a second target device (115); responsive to reading the first value, send a second command including the first address and data representing the first value on the data line (120); send a third command on the data line (120), the third command including the first address; after sending the third command, read a second value on the data line (120), the second value including data from the first target device (110) and the second target device (115); responsive to reading the second value, send a fourth command on the data line (120), the fourth command including the first address.
A physical layer transceiver (106) and a network node including the transceiver. The transceiver (106) includes a media independent interface (200), a converter circuit block (210) comprising circuitry (214) configured to convert digital signals to analog signals for transmission over a network communications medium and convert analog signals received over the medium to digital signals, and one or more processing blocks (202A; 202B; 202C) configured to process digital data communicated between the media independent interface and the converter circuit block according to a network protocol. Management and control circuitry (220) including power management circuitry and reset circuitry are provided. The transceiver (106) further includes at least one single event effect (SEE) monitor (240), such as an ambience monitor (242), a configuration register monitor (244), a state machine monitor (246), or a phase locked loop (PEL) lock monitor (250), configured to detect and respond to an SEE event in the transceiver (106).
A system (100) includes a plurality of digital-to-analog converter (DAC) channels (Cl-CN). Each DAC channel includes a current control circuit (150-1) which receives a start limit signal or an end limit signal. The current control circuit (150-1) reduces an output current limit of the channel responsive to the start limit signal and increases the output current limit responsive to the end limit signal. Each channel includes a current sensor circuit (120-1) adapted to measure the output current of the channel and provide a channel over-current alert signal if the output current rises above a high current limit. The system (100) includes a controller (140) which asserts the start limit signal if the number of channels exceeding the high current limit is greater than a maximum allowable number and asserts the end limit signal if the number of channels exceeding the high current limit is less than the maximum allowable number minus a hysteresis value.
In an example, a system (100) includes an amplifier having an output stage configured to provide an output voltage (108), where the output stage includes a p-channel transistor (102) and an n-channel transistor (110). The system (100) includes a sense transistor (116) having a gate coupled to a gate of the p-channel transistor (102), where the sense transistor (116) is configured to sense a current (162) of the p-channel transistor (102) and produce a sense current (166). The system (100) includes a current mirror configured to provide the sense current (166) to a gate of a control transistor (140), the control transistor (140) having a source coupled to the gate of the p-channel transistor (102). The control transistor (140) is configured to adjust a gate current provided to the p-channel transistor (102) based on comparing the sense current (166) to a reference current (178).
In an example, a system (100) includes a first power stage (102) including a first power field effect transistor (FET) (104) and a first sense transistor (106) coupled to the first power FET (104). The system (100) also includes a second power stage (162) including a second power FET (172) and a second sense transistor (174) coupled to the second power FET (172), where the second power stage (162) is smaller than the first power stage (102). The system (100) includes a first switch (160) coupled to a gate (108) and a drain (112) of the first power FET (104) and a second switch (130) coupled to the first power stage (102) and the second power stage (162). The system (100) also includes a sense amplifier (132) coupled to the second switch (130), where the first power stage (102), the second power stage (162), and the sense amplifier (132) are coupled to a load terminal (140).
An example device (100) includes: converter circuitry (104 A) having an output configured to couple to a first memory circuit (106 A) from a plurality of memory circuits (106A, 106B, 106C), the converter circuitry (104 A) configured to: receive a first instruction formatted with a uniform protocol; and convert the first instruction from the uniform protocol to a protocol specific to the first memory circuit (106A); logic circuitry (108) having an input configured to couple to the first memory circuit (106 A), the logic circuitry (108) configured to: receive a first result of the first instruction from the first memory circuit (106 A); and responsive to a second instruction, combine the first result with other results from ones of the plurality of memory circuits (106B, 106C) into an output.
A digital-to-analog converter (DAC) (100) for converting a digital input word to an analog output signal includes a string DAC (104), a first interpolator (130) and a second interpolator (150). The string DAC (104) outputs a first voltage and a second voltage in response to M most significant bits of the digital input word. The first interpolator (130) interpolates between the first and second voltages in response to middle Q least significant bits of the digital input word and provides a first interpolated voltage. The second interpolator (150) interpolates between the first interpolated voltage and the second voltage in response to lower P least significant bits of the digital input word.
H03M 1/68 - Digital/analogue converters with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits
Semiconductor devices with high area efficiency are described. Such a semiconductor device (200) can be positioned within an isolation structure (245), and include diodes coupled to the isolation structure (245). In this manner, the semiconductor devices utilize an area, which may be otherwise left as an inactive space (or dead space) to achieve a smaller footprint. Further, the semiconductor devices may include multiple fingers of doped regions (270, 275) arranged horizontally, vertically, or a combination of both. The fingers of doped regions form diodes connected in parallel using metal lines that are parallelized to facilitate flowing large amounts of current. The parallelized metal lines with reduced lengths ameliorate issues associated with parasitic resistance of the metal lines during ESD or surge events.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
A method includes programming (410) first and second values and a first compare enable command into respective first operand, second operand, and first compare enable command registers in a hardware comparator circuit. The method includes determining (440, 450) that a first match exists corresponding to the first and second values, programming a third value into the first operand register and a fourth value into the second operand register, and programming a second compare enable command into a second compare enable command register in the hardware comparator circuit. In response to a determination that a second match exists corresponding to the third and fourth values, the method includes asserting a success interrupt signal, programming (472) a fifth value into the first operand register and a sixth value into the second operand register and programming a second compare enable command into a second compare enable command register in the hardware comparator circuit.
G06F 21/75 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation, e.g. to counteract reverse engineering
A control circuit (410) includes a timeout circuit (414) configured to receive a first control signal. The timeout circuit (414) asserts a timeout output signal on a timeout circuit output responsive to an expiration of a time period following assertion of the first control signal. A counter circuit (416) has an input coupled to the timeout circuit output and has a counter circuit output. Responsive to assertion of the first control signal, the counter circuit (416) selectively increments an output count value on the counter circuit output responsive to the timeout output signal having a first logic state or decrements the output count value on the counter circuit output responsive to the timeout output signal having a second logic state. A comparator circuit (420) has a control input coupled to the counter circuit output. The comparator circuit (420) adjusts a magnitude of a reference signal responsive to the output count value from the counter circuit (416).
H02M 3/156 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
98.
MULTILEVEL PACKAGE SUBSTRATE WITH STAIR SHAPED SUBSTRATE TRACES
An electronic device (100) includes a multilevel package substrate (101) with first and second levels (El, L2), the second level (L2) including a first trace layer with a first conductive trace feature (106), a conductive first via (108) that contacts the first conductive trace feature (106), and a first dielectric layer (104), and the first level (El) including a second trace layer with a stair shaped second conductive trace feature (110), the second conductive trace feature (110) having a first portion (111) with a first thickness (113), and a second portion (112), having a second thickness (114) greater than the first thickness (113).
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/12 - Mountings, e.g. non-detachable insulating substrates
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
A test system (200) has first (210), second (220) and third (230) circuits having the same design and configured to receive a same input signal. A majority voter circuit (240) has a first voter input (214) coupled to a first circuit output, a second voter input (224) coupled to a second circuit output, a third voter input (234) coupled to a third circuit output, and a voter output (244). The output signal is equal to a signal present at least two of the voter inputs. A discrepancy detector circuit (260) has first, second and third discrepancy inputs coupled to the first, second and third circuit outputs, respectively. A discrepancy output (262) provides a first logic signal responsive to the first, second and third circuit outputs having equal values and provides a second logic signal responsive to the first, second and third circuit outputs having unequal values.
G06F 11/18 - Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits, e.g. by quadding or by majority decision circuits
100.
VOLTAGE CONVERTER WITH AVERAGE INPUT CURRENT CONTROL AND INPUT-TO-OUTPUT ISOLATION
A voltage converter (100) having a voltage input and a voltage output, the voltage converter (100) including a first and second transistors (Ml, ISO FET) and an average current control circuit (130). The first transistor (Ml) has a first control input, a first current terminal, and a second current terminal. The first current terminal is adapted to be coupled to a switch node. The second transistor (ISO FET) has a second control input, a third current terminal, and a fourth current terminal. The third current terminal is adapted to be coupled to an inductor (El). The average current control circuit (130) is coupled to the third current terminal and the fourth current terminal. The average current control circuit (130) is configured to determine an average current level of current flowing through the second transistor (ISO FET) and to control a voltage on the first control input of the first terminal based on the determined average current level.
H02M 3/156 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
patents
