Texas Instruments Incorporated

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H01L 23/495 - Lead-frames 586
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1.

METHODS FOR ENERGY-EFFICIENT UNICAST AND MULTICAST TRANSMISSION IN A WIRELESS COMMUNICATION SYSTEM

      
Application Number 17527109
Status Pending
Filing Date 2021-11-15
First Publication Date 2022-08-11
Owner Texas Instruments Incorporated (USA)
Inventor
  • Ekpenyong, Anthony Edet
  • Bendlin, Ralf Matthias
  • Onggosanusi, Eko Nugroho
  • Chen, Runhua

Abstract

A method for time multiplexing subframes on a serving cell to a user equipment, wherein one set of subframes operate with the legacy LTE transmission format and one set of subframes operate with an evolved transmission format comprising reduced density CRS transmission without a PDCCH control region.

IPC Classes  ?

  • H04L 5/00 - Arrangements affording multiple use of the transmission path

2.

AGING COMPENSATION OF A FERROELECTRIC PIEZOELECTRIC SHOCK SENSOR

      
Application Number 17732475
Status Pending
Filing Date 2022-04-28
First Publication Date 2022-08-11
Owner TEXAS INSTRUMENTS INCORPORATED (USA)
Inventor
  • Summerfelt, Scott Robert
  • Cook, Benjamin Stassen

Abstract

A method includes measuring a temperature of a semiconductor die, in which the semiconductor die includes a piezoelectric device, a pyroelectric device, and a memory. The method further includes receiving a first signal from the pyroelectric device, and based on the first signal, determining a parameter to be combined with a second signal from the piezoelectric device. The method further includes storing the parameter and the measured temperature into the memory.

IPC Classes  ?

  • G01P 21/00 - Testing or calibrating of apparatus or devices covered by the other groups of this subclass
  • G01P 15/09 - Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces with conversion into electric or magnetic values by piezo-electric pick-up

3.

DUAL GATE DIELECTRIC LAYERS GROWN WITH AN INHIBITOR LAYER

      
Application Number 17730944
Status Pending
Filing Date 2022-04-27
First Publication Date 2022-08-11
Owner Texas Instruments Incorporated (USA)
Inventor
  • Arendt, Mark Francis
  • Gilmore, Damien Thomas

Abstract

A semiconductor device including a first dielectric layer and a second dielectric layer is formed by forming an inhibitor layer over a semiconductor material. The inhibitor layer includes at least silicon and nitrogen. The semiconductor material is heated in an oxygen-containing ambient which oxidizes the inhibitor layer and forms the first dielectric layer which includes the oxidized inhibitor layer, and oxidizes the semiconductor material to form the second dielectric layer. The second dielectric layer is thicker than, the first dielectric layer. The first dielectric layer and the second dielectric layer each include at least 90 weight percent silicon dioxide and less than 1 weight percent nitrogen. The first dielectric layer and the second dielectric layer may be used to form gate dielectric layers for a first MOS transistor and a second MOS transistor that operates at a higher voltage than the first MOS transistor.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 29/51 - Insulating materials associated therewith
  • H01L 21/8234 - MIS technology

4.

OUTPUT TERMINAL FAULT DETECTION CIRCUIT

      
Application Number 17168528
Status Pending
Filing Date 2021-02-05
First Publication Date 2022-08-11
Owner Texas Instruments Incorporated (USA)
Inventor
  • Demirci, Kemal Safak
  • Chellamuthu, Shanmuganand
  • Li, Qunying

Abstract

A circuit includes a gain stage, first and second amplifiers, and a comparison circuit. The gain stage has an input and an output. The first amplifier has an input and an output. The input of the first amplifier is coupled to the input of the gain stage. The second amplifier has an input and an output. The input of the second amplifier is coupled to the output of the gain stage. The comparison circuit is coupled to the outputs of the first and second amplifiers. The comparison circuit is configured to compare signals on the outputs of the first and second amplifiers and to generate a fault flag signal responsive to the output signal from the first amplifier being different than the output signal from the second amplifier.

IPC Classes  ?

  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
  • H03F 3/45 - Differential amplifiers
  • H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
  • H03K 5/24 - Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude

5.

DFE IMPLEMENTATION FOR WIRELINE APPLICATIONS

      
Application Number 17733843
Status Pending
Filing Date 2022-04-29
First Publication Date 2022-08-11
Owner Texas Instruments Incorporated (USA)
Inventor
  • Ganesan, Raghu
  • Rajai, Kalpesh

Abstract

Disclosed embodiments include a decision feedback equalizer (DFE) comprising an N-bit parallel input adapted to be coupled to a communication channel and configured to receive consecutive communication symbols, a first DFE path including a first path input configured to receive communication symbols, and a first adder having a first adder input coupled to the first path input. There is a first DFE filter having outputs responsive to the first DFE filter inputs, the outputs coupled to the second adder input. The DFE includes a first path having a first slicer and a first multiplexer, a first path multiplexer output, and a second DFE path including a second path input configured to receive a second communication symbol, a second adder, a second DFE filter, a second slicer, and a second multiplexer.

IPC Classes  ?

  • H04L 25/03 - Shaping networks in transmitter or receiver, e.g. adaptive shaping networks

6.

HEXAGONAL BORON NITRIDE STRUCTURES

      
Application Number 17729121
Status Pending
Filing Date 2022-04-26
First Publication Date 2022-08-11
Owner TEXAS INSTRUMENTS INCORPORATED (USA)
Inventor
  • Colombo, Luigi
  • Dadvand, Nazila
  • Cook, Benjamin Stassen
  • Venugopal, Archana

Abstract

A microstructure comprises a plurality of interconnected units wherein the units are formed of hexagonal boron nitride (h-BN) tubes. The graphene tubes may be formed by photo-initiating the polymerization of a monomer in a pattern of interconnected units to form a polymer microlattice, removing unpolymerized monomer, coating the polymer microlattice with a metal, removing the polymer microlattice to leave a metal microlattice, depositing an h-BN precursor on the metal microlattice, converting the h-BN precursor to h-BN, and removing the metal microlattice.

IPC Classes  ?

  • C01B 21/064 - Binary compounds of nitrogen with metals, with silicon, or with boron with boron
  • C23C 16/34 - Nitrides
  • C23C 18/32 - Coating with one of iron, cobalt or nickel; Coating with mixtures of phosphorus or boron with one of these metals
  • C23C 18/16 - Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, i.e. electroless plating
  • C23C 18/36 - Coating with one of iron, cobalt or nickel; Coating with mixtures of phosphorus or boron with one of these metals using reducing agents using hypophosphites
  • C23C 18/28 - Sensitising or activating
  • C23C 18/30 - Activating
  • C23C 18/20 - Pretreatment of the material to be coated of organic surfaces, e.g. resins

7.

MONITORING CIRCUIT FOR PHOTOVOLTAIC MODULE

      
Application Number 17733619
Status Pending
Filing Date 2022-04-29
First Publication Date 2022-08-11
Owner Texas Instruments Incorporated (USA)
Inventor
  • Pauletti, Timothy Patrick
  • Chen, Suheng

Abstract

A monitoring circuit for a photovoltaic module includes a measurement conditioning circuit, a microcontroller circuit, and a transmitter circuit. The measurement conditioning circuit includes a voltage sense terminal, a voltage reference terminal, and a digital measurement data output. The microcontroller circuit includes a digital measurement data input coupled with the digital measurement data output, a modulation clock input, a measurement data stream output, and a transmit select output. The transmitter circuit includes a measurement data stream input coupled with the measurement data stream output, a modulation clock output coupled with the modulation clock input, a transmit select input coupled with the transmit select output, and positive and negative output communication terminals.

IPC Classes  ?

  • H04Q 9/00 - Arrangements in telecontrol or telemetry systems for selectively calling a substation from a main station, in which substation desired apparatus is selected for applying a control signal thereto or for obtaining measured values therefrom
  • H02S 50/00 - Monitoring or testing of PV systems, e.g. load balancing or fault identification
  • G01K 1/024 - Means for indicating or recording specially adapted for thermometers for remote indication
  • G01K 7/00 - Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat

8.

PACKAGE SUBSTRATE WITH CTE MATCHING BARRIER RING AROUND MICROVIAS

      
Application Number 17679082
Status Pending
Filing Date 2022-02-24
First Publication Date 2022-08-11
Owner Texas Instruments Incorporated (USA)
Inventor
  • Williamson, Jaimal Mallory
  • Li, Guangxu

Abstract

A multi-layer package substrate includes a first build-up layer including a first dielectric layer and at least a second build-up layer including a second dielectric layer on the first build-up layer. The second build-up layer includes a top metal layer with a surface configured for attaching at least one integrated circuit (IC) die. The first build-up layer includes a bottom metal layer and a first microvia extending through the first dielectric layer, and the second build-up layer includes at least a second microvia extending through the second dielectric layer that is coupled to the first microvia. A barrier ring that has a coefficient of thermal expansion (CTE) matching material relative to a CTE of a metal of the second microvia positioned along only a portion of a height of at least the second microvia including at least around a top portion of the second microvia.

IPC Classes  ?

  • H01L 23/00 - SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR - Details of semiconductor or other solid state devices
  • H01L 23/498 - Leads on insulating substrates
  • H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups

9.

OUTPUT TERMINAL FAULT DETECTION CIRCUIT

      
Application Number US2022015467
Publication Number 2022/170178
Status In Force
Filing Date 2022-02-07
Publication Date 2022-08-11
Owner TEXAS INSTRUMENTS INCORPORATED (USA)
Inventor
  • Demirci, Kemal, Safak
  • Chellamuthu, Shanmuganand
  • Li, Qunying

Abstract

A circuit includes a gain stage (112), first and second amplifiers (121, 122), and a comparison circuit (128). The gain stage (112) has an input and an output. The first amplifier (121) has an input and an output. The input of the first amplifier (121) is coupled to the input of the gain stage (112). The second amplifier (122) has an input and an output. The input of the second amplifier (122) is coupled to the output of the gain stage (112). The comparison circuit (128) is coupled to the outputs of the first and second amplifiers (121, 122). The comparison circuit (128) is configured to compare signals on the outputs of the first and second amplifiers (121, 122) and to generate a fault flag signal (129) responsive to the output signal from the first amplifier (121) being different than the output signal from the second amplifier (122).

IPC Classes  ?

  • G01R 31/54 - Testing for continuity
  • H03F 1/20 - Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of distributed coupling in discharge-tube amplifiers
  • H03F 3/195 - High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits
  • H03F 15/00 - Amplifiers using galvano-magnetic effects not involving mechanical movement, e.g. using Hall effect

10.

HIGH VOLTAGE ISOLATION BARRIER WITH ELECTRIC OVERSTRESS INTEGRITY

      
Application Number 17730872
Status Pending
Filing Date 2022-04-27
First Publication Date 2022-08-11
Owner Texas Instruments Incorporated (USA)
Inventor West, Jeffrey A.

Abstract

An electronic device comprises a multilevel metallization structure over a semiconductor layer and including a first region, a second region, a pre-metal level on the semiconductor layer, and N metallization structure levels over the pre-metal level, N being greater than 3. The electronic device also comprises an isolation component in the first region, the isolation component including a first terminal and a second terminal in different respective metallization structure levels, as well as a conductive shield between the first region and the second region in the multilevel metallization structure, the conductive shield including interconnected metal lines and trench vias in the respective metallization structure levels that at least partially encircle the first region.

IPC Classes  ?

  • H01L 23/60 - Protection against electrostatic charges or discharges, e.g. Faraday shields
  • H01L 23/528 - Layout of the interconnection structure
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices

11.

CACHE SIZE CHANGE

      
Application Number 17727912
Status Pending
Filing Date 2022-04-25
First Publication Date 2022-08-11
Owner TEXAS INSTRUMENTS INCORPORATED (USA)
Inventor
  • Chachad, Abhijeet Ashok
  • Bhoria, Naveen
  • Thompson, David Matthew
  • Muralidharan, Neelima

Abstract

A method includes determining, by a level one (L1) controller, to change a size of a L1 main cache; servicing, by the L1 controller, pending read requests and pending write requests from a central processing unit (CPU) core; stalling, by the L1 controller, new read requests and new write requests from the CPU core; writing back and invalidating, by the L1 controller, the L1 main cache. The method also includes receiving, by a level two (L2) controller, an indication that the L1 main cache has been invalidated and, in response, flushing a pipeline of the L2 controller; in response to the pipeline being flushed, stalling, by the L2 controller, requests received from any master; reinitializing, by the L2 controller, a shadow L1 main cache. Reinitializing includes clearing previous contents of the shadow L1 main cache and changing the size of the shadow L1 main cache.

IPC Classes  ?

  • G06F 12/0811 - Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
  • G06F 12/0815 - Cache consistency protocols
  • G06F 12/128 - Replacement control using replacement algorithms adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel
  • G06F 12/0817 - Cache consistency protocols using directory methods
  • G06F 12/084 - Multiuser, multiprocessor or multiprocessing cache systems with a shared cache
  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
  • G06F 11/30 - Monitoring
  • G06F 12/0808 - Multiuser, multiprocessor or multiprocessing cache systems with cache invalidating means
  • G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline, look ahead
  • G06F 9/46 - Multiprogramming arrangements
  • G06F 9/54 - Interprogram communication
  • G06F 12/0895 - Caches characterised by their organisation or structure of parts of caches, e.g. directory or tag array
  • G06F 12/0831 - Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means

12.

FREQUENCY-DIVISION MULTIPLEXING

      
Application Number 17554922
Status Pending
Filing Date 2021-12-17
First Publication Date 2022-08-11
Owner Texas Instruments Incorporated (USA)
Inventor
  • Motos, Tomas
  • Almholt, Thomas

Abstract

A method is provided. In some examples, the method includes generating, by processing circuitry, a spread of chips representing an input bit. In addition, the method includes converting, by the processing circuitry, the spread of chips to a plurality of symbols comprising a pair of symbols. The method also includes mapping, by the processing circuitry, the pair of symbols to a single carrier signal and generating, by the processing circuitry, a radio-frequency (RF) signal based on the single carrier signal. The method further includes transmitting, by the processing circuitry via an antenna, the RF signal.

IPC Classes  ?

  • H04B 1/69 - Spread spectrum techniques
  • H04L 27/10 - Frequency-modulated carrier systems, i.e. using frequency-shift keying

13.

Automatic sleep circuit

      
Application Number 17390276
Grant Number 11409350
Status In Force
Filing Date 2021-07-30
First Publication Date 2022-08-09
Grant Date 2022-08-09
Owner Texas Instruments Incorporated (USA)
Inventor
  • Krishnamurthy, Ganapathi Shankar
  • Guduri, Venkatesh

Abstract

An integrated circuit including an autosleep circuit and a voltage regulator. The autosleep circuit includes a latch, a voltage detection circuit outputting a signal to a set input of the latch responsive to a voltage at its input exceeding a threshold voltage, and a delay timer outputting a signal to a reset input of the latch responsive to inactivity at one or more input terminals. A voltage regulator is configured to generate a voltage for biasing a subsystem such as digital logic, and is also the input voltage to the voltage detection circuit. The voltage regulator includes a plurality of transistors in parallel, one gated by the output of the latch and each of the others gated by one of the one or more input terminals. The voltage regulator includes an output leg that generates the output voltage responsive to one of the parallel transistors being turned on.

IPC Classes  ?

  • G06F 1/32 - Means for saving power
  • G06F 9/44 - Arrangements for executing specific programs
  • G06F 1/3206 - Monitoring of events, devices or parameters that trigger a change in power modality
  • G06F 9/4401 - Bootstrapping
  • G06F 1/3287 - Power saving characterised by the action undertaken by switching off individual functional units in the computer system

14.

CIRCUIT DESIGN VALIDATION TOOL FOR RADIATION-HARDENED DESIGN

      
Application Number 17586516
Status Pending
Filing Date 2022-01-27
First Publication Date 2022-08-04
Owner TEXAS INSTRUMENTS INCORPORATED (USA)
Inventor
  • Gewax, Lawrence James
  • Duryea, Timothy Paul

Abstract

One example includes a method for validating a circuit design. The method includes providing a set of coded rules. Each of the coded rules can define conditions for circuit cells to qualify the circuit design as being radiation-hardened. The method also includes accessing a circuit design netlist associated with the circuit design from a circuit design database. The method also includes evaluating each of the circuit cells in the circuit design netlist with respect to each of the coded rules. The method further includes providing a circuit evaluation report comprising an indication of failure of a set of the circuit cells with respect to one or more of the coded rules in response to the evaluation.

IPC Classes  ?

  • G06F 30/33 - Design verification, e.g. functional simulation or model checking
  • G06F 30/327 - Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist

15.

Technique for GaN Epitaxy on Insulating Substrates

      
Application Number 17588589
Status Pending
Filing Date 2022-01-31
First Publication Date 2022-08-04
Owner TEXAS INSTRUMENTS INCORPORATED (USA)
Inventor
  • Dellas, Jr., Nicholas S.
  • Summerfelt, Scott Robert

Abstract

A method includes depositing a first epitaxial layer of an aluminum gallium nitride (AlGaN) material onto a preliminary substrate and polishing the first layer's surface. Ions are implanted beneath the surface, which is bonded to a seed insulating substrate. Annealing is performed, resulting in second epitaxial layer on preliminary substrate and third epitaxial layer on seed insulating substrate. Third layer's surface is polished to obtain a seed wafer. In some implementations, a fourth epitaxial layer of a second AlGaN material is deposited onto surface of third layer. Fourth layer's surface is polished, and ions are implanted beneath the surface, which is bonded to a product insulating substrate. Annealing is performed, resulting in fifth epitaxial layer on seed insulating substrate and sixth epitaxial layer on product insulating substrate. The sixth layer can be used to obtain an AlGaN product, and the fifth layer can be reused to fabricate additional AlGaN products.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting
  • H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering

16.

QUICK CLEARING OF REGISTERS

      
Application Number 17722477
Status Pending
Filing Date 2022-04-18
First Publication Date 2022-08-04
Owner TEXAS INSTRUMENTS INCORPORATED (USA)
Inventor
  • Anderson, Timothy David
  • Bui, Duc Quang
  • Narnur, Soujanya

Abstract

A method of clearing of registers and logic designs with AND and OR logics to propagate the zero values provided to write enable signal buses upon the execution of clear instruction of more than one registers, allowing more than one architecturally visible registers to be cleared with one signal instruction regardless of the values of data buses.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers
  • G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
  • G06F 15/80 - Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors

17.

SEMICONDUCTOR DEVICE PACKAGE WITH REDUCED STRESS

      
Application Number 17723439
Status Pending
Filing Date 2022-04-18
First Publication Date 2022-08-04
Owner Texas Instruments Incorporated (USA)
Inventor
  • Ostrowicki, Gregory Thomas
  • Nangia, Amit Sureshkumar

Abstract

A described example includes: a semiconductor device die with an active surface; the semiconductor device die mounted on a package substrate with substrate leads and the semiconductor device die electrically coupled to the substrate leads; at least a first rigid low expansion material (RLEM) covering a portion of the semiconductor device die; and the first RLEM, the semiconductor device die, and a portion of the substrate leads covered with mold compound and forming a packaged semiconductor device die.

IPC Classes  ?

  • H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
  • H01L 23/498 - Leads on insulating substrates
  • H01L 23/00 - SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR - Details of semiconductor or other solid state devices
  • H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings

18.

METHODS AND SYSTEMS FOR CHROMA RESIDUAL DATA PREDICTION

      
Application Number 17726463
Status Pending
Filing Date 2022-04-21
First Publication Date 2022-08-04
Owner Texas Instruments Incorporated (USA)
Inventor
  • Gupte, Ajit Deepak
  • Srinivasan, Ranga Ramanujam

Abstract

Several methods and systems for chroma residual data prediction for encoding blocks corresponding to video data are disclosed. In an embodiment, at least one coefficient correlating reconstructed luma residual samples and corresponding reconstructed chroma residual samples is computed for one or more encoded blocks of video data. Predicted chroma residual samples are generated for encoding a block of video data based on corresponding reconstructed luma residual samples and the at least one coefficient.

IPC Classes  ?

  • H04N 19/186 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being a colour or a chrominance component
  • H04N 19/176 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
  • H04N 19/147 - Data rate or code amount at the encoder output according to rate distortion criteria
  • H04N 19/107 - Selection of coding mode or of prediction mode between spatial and temporal predictive coding, e.g. picture refresh

19.

MULTI-FUNCTION BOND PAD

      
Application Number 17162189
Status Pending
Filing Date 2021-01-29
First Publication Date 2022-08-04
Owner Texas Instruments Incorporated (USA)
Inventor
  • Banerjee, Suvadip
  • Tellkamp, John Paul

Abstract

An electronic device includes one or more multinode pads having two or more conductive segments spaced from one another on a semiconductor die. A conductive stud bump is selectively formed on portions of the first and second conductive segments to program circuitry of the semiconductor die or to couple a supply circuit to a load circuit. The multinode pad can be coupled to a programming circuit in the semiconductor die to allow programming a programmable circuit of the semiconductor die during packaging. The multinode pad has respective conductive segments coupled to the supply circuit and the load circuit to allow current consumption or other measurements during wafer probe testing in which the first and second conductive segments are separately probed prior to stud bump formation.

IPC Classes  ?

  • H01L 23/00 - SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR - Details of semiconductor or other solid state devices
  • H01L 23/488 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of soldered or bonded constructions
  • H01L 23/528 - Layout of the interconnection structure
  • H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups

20.

LOW COST METHOD-B HIGH VOLTAGE ISOLATION SCREEN TEST

      
Application Number 17512382
Status Pending
Filing Date 2021-10-27
First Publication Date 2022-08-04
Owner TEXAS INSTRUMENTS INCORPORATED (USA)
Inventor Bonifield, Thomas Dyer

Abstract

A method includes applying an AC test voltage signal to a terminal of an electronic device, the AC test voltage signal having a test frequency of 100 Hz or more, sensing a current signal of the electronic device during application of the AC test voltage signal, and identifying the electronic device as passing an isolation test in response to the current signal being less than a current threshold. After identifying the electronic device as passing the isolation test, the method includes applying a second AC test voltage signal to the terminal of the electronic device, the second AC test voltage signal having a second test frequency of 100 Hz or more, measuring a partial discharge of the electronic device during application of the second AC test voltage signal, and identifying the electronic device as passing a partial discharge test in response to the partial discharge being less than a threshold.

IPC Classes  ?

  • G01R 31/52 - Testing for short-circuits, leakage current or ground faults
  • G01R 31/14 - Circuits therefor

21.

CONDUCTIVE PATTERNING USING A PERMANENT RESIST

      
Application Number 17512959
Status Pending
Filing Date 2021-10-28
First Publication Date 2022-08-04
Owner TEXAS INSTRUMENTS INCORPORATED (USA)
Inventor
  • Inoue, Hidetoshi
  • Kawano, Kenji
  • Sato, Yuki
  • Ando, Takafumi
  • Lueders, Michael
  • Herzer, Stefan
  • Morroni, Jeffrey

Abstract

A permanent resist, such as TMMF, is used when patterning conductive material on a substrate, enabling lines that have a higher line-to-space ratio (L/S) or a higher aspect ratio (T/L) or both. Pattern density can thus be increased, allowing for improved performance (e.g., greater efficiency, in the case of transformer coil patterning) and greater heat dissipation. As examples, the permanent-resist-based patterning fabrication methods can be used to create transformer coils within an integrated circuit (IC) module, or a routable lead frame for one or more IC dies.

IPC Classes  ?

  • G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
  • H01L 21/027 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or

22.

LOAD REGULATION

      
Application Number 17565550
Status Pending
Filing Date 2021-12-30
First Publication Date 2022-08-04
Owner TEXAS INSTRUMENTS INCORPORATED (USA)
Inventor
  • Jing, Weibing
  • Yang, Qi
  • Li, Dan
  • Wu, Guoyang

Abstract

A device includes an operational amplifier having a first input, a second input and an output, the operational amplifier configured to generate a first signal at the output. The device includes a reference resistor divider having a first and second resistor, a first terminal of the first resistor coupled to the second input of the operational amplifier. A second terminal of the first resistor is coupled to a first terminal of the second resistor and a second terminal of the second resistor coupled to an electrically neutral terminal. The device includes a voltage to current (V2I) converter having an input and an output, the input coupled to the output of the operational amplifier, and the V2I converter configured to generate a second signal at the output of the V2I converter. The device includes a switch coupled to the output of the V2I converter and to the reference resistor divider.

IPC Classes  ?

  • H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion
  • H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load

23.

SYSTEM AND METHOD FOR THE COMPRESSION OF ECHOLOCATION DATA

      
Application Number US2022012874
Publication Number 2022/164686
Status In Force
Filing Date 2022-01-19
Publication Date 2022-08-04
Owner TEXAS INSTRUMENTS INCORPORATED (USA)
Inventor
  • Subburaj, Karthik
  • Rao, Sandeep

Abstract

A method for compressing echolocation data is provided. The method includes dividing the echolocation data into a plurality of partitions (600), and selecting a first partition for processing (602). The method also includes combining echolocation data from the first partition with echolocation data within a second partition (604), and combining echolocation data from the first partition with echolocation data within a third partition (606). The method further includes storing the combined echolocation data for all of the plurality of partitions except for the first partition in a memory (608).

IPC Classes  ?

  • G01S 13/28 - Systems for measuring distance only using transmission of interrupted, pulse modulated waves wherein the transmitted pulses use a frequency- or phase-modulated carrier wave with time compression of received pulses
  • G01S 7/292 - Extracting wanted echo-signals

24.

LOOKUP-TABLE-BASED ANALOG-TO-DIGITAL CONVERTER

      
Application Number US2022013802
Publication Number 2022/164841
Status In Force
Filing Date 2022-01-26
Publication Date 2022-08-04
Owner TEXAS INSTRUMENTS INCORPORATED (USA)
Inventor
  • Pentakota, Visvesvaraya, Appala
  • Rajagopal, Narasimhan
  • Shetty, Chirag, Chandrahas
  • K, Prasanth
  • Shrivastava, Neeraj
  • Miglani, Eeshan
  • Venkataraman, Jagannathan

Abstract

An analog-to-digital converter system (10) includes a digital-to-analog converter (32) for generating calibration voltages based on digital input codes, and an analog-to-digital converter (18), connected to the digital-to-analog converter (32), for receiving the calibration voltages from the digital-to-analog converter (32), for receiving sampled voltages, for generating digital output codes based on the calibration voltages, and for generating digital output codes based on the sampled voltages. The analog-to-digital converter system (10) may have a lookup table (20), connected to the analog-to-digital converter (18), for storing the first digital output codes in association with the digital input codes. A method of calibrating an analog-to-digital converter system (10) is also described.

IPC Classes  ?

  • H03M 1/46 - Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter

25.

CIRCUIT DESIGN VALIDATION TOOL FOR RADIATION-HARDENED DESIGN

      
Application Number US2022014479
Publication Number 2022/165294
Status In Force
Filing Date 2022-01-31
Publication Date 2022-08-04
Owner TEXAS INSTRUMENTS INCORPORATED (USA)
Inventor
  • Gewax, Lawrence, James
  • Duryea, Timothy, Paul

Abstract

One example includes a method for validating a circuit design. The method includes providing a set of coded rules (106). Each of the coded rules (106) can define conditions for circuit cells to qualify the circuit design as being radiation-hardened. The method also includes accessing a circuit design netlist (112) associated with the circuit design from a circuit design database (108). The method also includes evaluating each of the circuit cells in the circuit design netlist (112) with respect to each of the coded rules (106). The method further includes providing a circuit evaluation report comprising an indication of failure of a set of the circuit cells with respect to one or more of the coded rules (106) in response to the evaluation.

IPC Classes  ?

  • G06F 30/33 - Design verification, e.g. functional simulation or model checking
  • G06F 117/02 - Fault tolerance, e.g. for transient fault suppression
  • G06F 119/02 - Reliability analysis or reliability optimisation; Failure analysis, e.g. worst case scenario performance, failure mode and effects analysis [FMEA]
  • H05K 10/00 - Arrangements for improving the operating reliability of electronic equipment, e.g. by providing a similar stand-by unit

26.

LOOKUP TABLE FOR NON-LINEAR SYSTEMS

      
Application Number 17588493
Status Pending
Filing Date 2022-01-31
First Publication Date 2022-08-04
Owner Texas Instruments Incorporated (USA)
Inventor
  • Pentakota, Visvesvaraya Appala
  • Naru, Srinivas Kumar Reddy
  • Shetty, Chirag
  • Miglani, Eeshan
  • Shrivastava, Neeraj
  • Rajagopal, Narasimhan
  • Dusad, Shagun

Abstract

In described examples, a circuit includes a multiplexer. The multiplexer receives an input voltage and a calibration signal. An analog-to-digital converter (ADC) is coupled to the multiplexer and generates an output code in response to the calibration signal. A storage circuit is coupled to the ADC and stores the input code representative of the calibration signal at an address corresponding to the output code. The stored input code includes an index value and a coarse value.

IPC Classes  ?

27.

STRESS ISOLATION USING THREE-DIMENSIONAL TRENCHES

      
Application Number 17388301
Status Pending
Filing Date 2021-07-29
First Publication Date 2022-08-04
Owner Texas Instruments Incorporated (USA)
Inventor
  • Yen, Ting-Ta
  • Segovia-Fernandez, Jeronimo
  • Jackson, Ricky Alan
  • Cook, Benjamin

Abstract

A semiconductor system includes a substrate. The substrate has a front side and a back side. A device is formed on the front side of the substrate. A vertical spring is etched in the substrate about the device. A trench is etched in the front side of the substrate about the device. A wall of the trench forms a side of the vertical spring.

IPC Classes  ?

28.

CALIBRATION SCHEME FOR FILLING LOOKUP TABLE IN AN ADC

      
Application Number 17467561
Status Pending
Filing Date 2021-09-07
First Publication Date 2022-08-04
Owner TEXAS INSTRUMENTS INCORPORATED (USA)
Inventor
  • Rajagopal, Narasimhan
  • Miglani, Eeshan
  • Shetty, Chirag Chandrahas
  • Shrivastava, Neeraj
  • Dusad, Shagun
  • Naru, Srinivas Kumar Reddy
  • Gopinath, Nithin
  • Babu, Charls
  • Srivastava, Shivam
  • Nagarajan, Viswanathan
  • Venkataraman, Jagannathan
  • Moondra, Harshit
  • K, Prasanth
  • Pentakota, Visvesvaraya Appala

Abstract

In described examples, a circuit includes a calibration engine. The calibration engine generates multiple input codes. A digital to analog converter (DAC) is coupled to the calibration engine, and generates a first calibration signal in response to a first input code of the multiple input codes. An analog to digital converter (ADC) is coupled to the DAC, and generates multiple raw codes responsive to the first calibration signal. A storage circuit is coupled to the ADC and stores a first output code corresponding to the first input code. The first output code is obtained using the multiple raw codes generated by the ADC.

IPC Classes  ?

29.

RATE CONTROL IN VIDEO CODING

      
Application Number 17545146
Status Pending
Filing Date 2021-12-08
First Publication Date 2022-08-04
Owner Texas Instruments Incorporated (USA)
Inventor
  • Nagori, Soyeb
  • Kudana, Arun Shankar
  • Mathew, Manu

Abstract

A method of rate control in coding of a video sequence to generate a compressed bit stream is provided that includes computing a sequence base quantization step size for a sequence of pictures in the video sequence, computing a picture base quantization step size for a picture in the sequence of pictures based on the sequence base quantization step size, a type of the picture, and a level of the picture in a rate control hierarchy, and coding the picture using the picture base quantization step size to generate a portion of the compressed bit stream.

IPC Classes  ?

  • H04N 19/196 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the adaptation method, adaptation tool or adaptation type used for the adaptive coding being specially adapted for the computation of encoding parameters, e.g. by averaging previously computed encoding parameters
  • H04N 19/142 - Detection of scene cut or scene change
  • H04N 19/177 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being a group of pictures [GOP]
  • H04N 19/152 - Data rate or code amount at the encoder output by measuring the fullness of the transmission buffer
  • H04N 19/126 - Quantisation - Details of normalisation or weighting functions, e.g. normalisation matrices or variable uniform quantisers

30.

RESONANT DC-DC CONVERTER WITH AVERAGE HALF CYCLE CONTROL

      
Application Number 17563200
Status Pending
Filing Date 2021-12-28
First Publication Date 2022-08-04
Owner Texas Instruments Incorporated (USA)
Inventor
  • Stracquadaini, Rosario
  • Giombanco, Salvatore

Abstract

Resonant DC-DC converter control circuitry includes a feedback input, a differential integrator, a resonant voltage input, a first comparator, and a second comparator. The differential integrator includes a first input, a second input, a first output, and a second output. The first input is coupled to the feedback input. The second input is coupled to a ground terminal. The first comparator includes a first input coupled to the resonant voltage input, and a second input coupled to the first output of the differential integrator. The second comparator includes a first input coupled to the resonant voltage input, and a second input coupled to the second output of the differential integrator.

IPC Classes  ?

  • H02M 3/335 - Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
  • H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion

31.

SEMICONDUCTOR PACKAGE SUBSTRATE WITH A SMOOTH GROOVE ABOUT A PERIMETER OF A SEMICONDUCTOR DIE

      
Application Number 17719235
Status Pending
Filing Date 2022-04-12
First Publication Date 2022-08-04
Owner TEXAS INSTRUMENTS INCORPORATED (USA)
Inventor
  • Wang, Chienhao
  • Lee, Bob
  • Chien, Yuhharng

Abstract

A semiconductor package includes a metallic pad and leads spaced from the metallic pad by a gap, the metallic pad including a roughened surface. The semiconductor package further includes a semiconductor die including bond pads, and an adhesive between the roughened surface of the metallic pad and the semiconductor die, therein bonding the semiconductor die to the metallic pad, wherein the adhesive includes a resin. The metallic pad further includes a groove surrounding the semiconductor die on the roughened surface, the groove having a surface roughness less than a surface roughness of the roughened surface of the metallic pad.

IPC Classes  ?

  • H01L 23/00 - SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR - Details of semiconductor or other solid state devices
  • H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
  • H01L 23/495 - Lead-frames
  • H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
  • H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
  • H01L 21/68 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for positioning, orientation or alignment
  • G06T 7/00 - Image analysis
  • G06T 7/70 - Determining position or orientation of objects or cameras

32.

Cache Preload Operations Using Streaming Engine

      
Application Number 17720657
Status Pending
Filing Date 2022-04-14
First Publication Date 2022-08-04
Owner TEXAS INSTRUMENTS INCORPORATED (USA)
Inventor
  • Zbiciak, Joseph Raymond Michael
  • Anderson, Timothy David
  • Tran, Jonathan (son) Hung
  • Chirca, Kai
  • Wu, Daniel
  • Chachad, Abhijeet Ashok
  • Thompson, David M.

Abstract

A stream of data is accessed from a memory system using a stream of addresses generated in a first mode of operating a streaming engine in response to executing a first stream instruction. A block cache preload operation is performed on a cache in the memory using a block of addresses generated in a second mode of operating the streaming engine in response to executing a second stream instruction.

IPC Classes  ?

  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
  • G06F 9/345 - Addressing or accessing the instruction operand or the result of multiple operands or results
  • G06F 12/0875 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline, look ahead
  • G06F 9/32 - Address formation of the next instruction, e.g. by incrementing the instruction counter
  • G06F 12/0897 - Caches characterised by their organisation or structure with two or more cache hierarchy levels
  • G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
  • G06F 11/00 - Error detection; Error correction; Monitoring
  • G06F 12/0862 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
  • G06F 12/1036 - Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] for multiple virtual address spaces, e.g. segmentation

33.

PREFETCH KILL AND REVIVAL IN AN INSTRUCTION CACHE

      
Application Number 17727921
Status Pending
Filing Date 2022-04-25
First Publication Date 2022-08-04
Owner TEXAS INSTRUMENTS INCORPORATED (USA)
Inventor
  • Heremagalur Ramaprasad, Bipin Prasad
  • Thompson, David Matthew
  • Chachad, Abhijeet Ashok
  • Ong, Hung

Abstract

A system comprises a processor including a CPU core, first and second memory caches, and a memory controller subsystem. The memory controller subsystem speculatively determines a hit or miss condition of a virtual address in the first memory cache and speculatively translates the virtual address to a physical address. Associated with the hit or miss condition and the physical address, the memory controller subsystem configures a status to a valid state. Responsive to receipt of a first indication from the CPU core that no program instructions associated with the virtual address are needed, the memory controller subsystem reconfigures the status to an invalid state and, responsive to receipt of a second indication from the CPU core that a program instruction associated with the virtual address is needed, the memory controller subsystem reconfigures the status back to a valid state.

IPC Classes  ?

  • G06F 12/1045 - Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
  • G06F 15/78 - Architectures of general purpose stored program computers comprising a single central processing unit

34.

COMBINED CAPACITIVE AND PIEZOELECTRIC SENSING IN A HUMAN MACHINE INTERFACE

      
Application Number US2022012875
Publication Number 2022/164687
Status In Force
Filing Date 2022-01-19
Publication Date 2022-08-04
Owner TEXAS INSTRUMENTS INCORPORATED (USA)
Inventor
  • Braathen, Jan, Morten
  • Lehman, Dennis, Patrick
  • Oljaca, Miroslav
  • Robertson, Maxwell, G.
  • Newman, Merril

Abstract

A human machine interface (HMI) system and method of operating. The system includes capacitive measurement circuitry (140) coupled to one or more capacitive touch elements (112), and piezoelectric measurement circuit (150) coupled to one or more piezoelectric touch elements (114). The capacitive measurement circuitry (140) amplifies a signal corresponding to a capacitance at the one or more capacitor input terminals by a gain level for communication to processing circuitry. Gain control circuitry, for example in a central processing unit (120), is configured to increase the gain level of the gain stage of the capacitive measurement circuitry responsive to the piezoelectric measurement circuitry receiving a user input from at least one of the piezoelectric touch elements (112).

IPC Classes  ?

  • G06F 3/041 - Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means

35.

LOW COST METHOD-B HIGH VOLTAGE ISOLATION SCREEN TEST

      
Application Number US2022013478
Publication Number 2022/164740
Status In Force
Filing Date 2022-01-24
Publication Date 2022-08-04
Owner TEXAS INSTRUMENTS INCORPORATED (USA)
Inventor Bonifield, Thomas Dyer

Abstract

A method (100) includes applying (110) an AC test voltage signal (VT) to a terminal of an electronic device, the AC test voltage signal (VT) having a test frequency (Fl) of 300 Hz to 100 kHz, sensing (112) a current signal (IT) of the electronic device during application of the AC test voltage signal (VT), and identifying (115) the electronic device (200) as passing an isolation test in response to the current signal (IT) being less than a current threshold (ITH). After identifying (115) the electronic device as passing the isolation test, the method (100) includes applying (116) a second AC test voltage signal (VT) to the terminal of the electronic device, the second AC test voltage signal (VT) having a second test frequency (F2) of 300 Hz to 100 kHz, measuring (118) a discharge of the electronic device during application of the second AC test voltage signal (VT), and identifying (121) the electronic device (200) as passing a discharge test in response to the discharge being less than a discharge threshold (DTH).

IPC Classes  ?

  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
  • G01R 31/12 - Testing dielectric strength or breakdown voltage
  • G01R 31/14 - Circuits therefor

36.

MULTI-FUNCTION BOND PAD

      
Application Number US2022014478
Publication Number 2022/165293
Status In Force
Filing Date 2022-01-31
Publication Date 2022-08-04
Owner TEXAS INSTRUMENTS INCORPORATED (USA)
Inventor
  • Banerjee, Suvadip
  • Tellkamp, John, Paul

Abstract

An electronic device includes one or more multinode pads (120, 130) having two or more conductive segments (121, 122) spaced from one another on a semiconductor die (111). A conductive stud bump (128) is selectively formed on portions of the first and second conductive segments (121, 122) to program circuitry of the semiconductor die (111) or to couple a supply circuit (125) to a load circuit (136). The multinode pad (120, 130) can be coupled to a programming circuit in the semiconductor die (111) to allow programming a programmable circuit of the semiconductor die (111) during packaging. The multinode pad (120, 130) has respective conductive segments (121, 122) coupled to the supply circuit (125) and the load circuit (136) to allow current consumption or other measurements during wafer probe testing in which the first and second conductive segments (121, 122) are separately probed prior to stud bump formation.

IPC Classes  ?

  • H01L 21/76 - Making of isolation regions between components
  • H01L 21/363 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth using physical deposition, e.g. vacuum deposition, sputtering
  • H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier

37.

LOOKUP TABLE FOR NON-LINEAR SYSTEMS

      
Application Number US2022014532
Publication Number 2022/165318
Status In Force
Filing Date 2022-01-31
Publication Date 2022-08-04
Owner TEXAS INSTRUMENTS INCORPORATED (USA)
Inventor
  • Pentakota, Visvesvaraya Appala
  • Naru, Srinivas Kumar Reddy
  • Shetty, Cirag
  • Miglani, Eeshan
  • Shrivastava, Neeraj
  • Rajagopal, Narasimhan
  • Dusad, Shagun

Abstract

In described examples, a circuit (100) includes a multiplexer- (112). The multiplexer (112) receives an input voltage (110) and a calibration signal. An analog-to-digital converter (ADC) (106) is coupled to the multiplexer (112) and generates an output code in response to the calibration signal. A storage circuit (108) is coupled to the ADC (106) and stores the input code representative of the calibration signal at an address corresponding to the output code. The stored input code includes an index value and a coarse value.

IPC Classes  ?

38.

Cascode bias for comparator

      
Application Number 17406583
Grant Number 11405030
Status In Force
Filing Date 2021-08-19
First Publication Date 2022-08-02
Grant Date 2022-08-02
Owner Texas Instruments Incorporated (USA)
Inventor
  • Mustafi, Manish
  • Kundu, Amal Kumar

Abstract

A comparator having: a first transistor coupled to a first input terminal; a first current source coupled to the first transistor; a second transistor coupled to a second input terminal and coupled to the first current source; a third transistor coupled in series with the first transistor; a fourth transistor coupled in series with the second transistor; a fifth transistor coupled in series with the first transistor; a sixth transistor coupled in series with the second transistor; a seventh transistor coupled to the first input terminal and coupled as a source follower to the fifth transistor; and an eighth transistor coupled to the second input terminal and coupled as a source follower to the sixth transistor. The comparator also including a differential amplifier coupled to the first output terminal and coupled to the second output terminal.

IPC Classes  ?

  • H03K 5/24 - Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
  • H03F 3/45 - Differential amplifiers

39.

PIPELINE SETTING SELECTION FOR GRAPH-BASED APPLICATIONS

      
Application Number 17582992
Status Pending
Filing Date 2022-01-24
First Publication Date 2022-07-28
Owner TEXAS INSTRUMENTS INCORPORATED (USA)
Inventor
  • Weaver, Lucas
  • Villarreal, Jr., Jesse Gregory

Abstract

An example system includes a pipeline depth determination circuit and a buffer depth determination circuit. The pipeline depth determination circuit is configured to analyze input-output connections between a plurality of processing nodes specified to perform a processing task, and determine a pipeline depth of the processing task based on the input-output connections. The buffer depth determination circuit is configured to analyze the input-output connections between the plurality of processing nodes, and assign, based on the input-output connections, a depth value to each of a plurality of buffer memories configured to store output of a first of the processing nodes for input to a second of the processing nodes.

IPC Classes  ?

  • G06F 13/40 - Bus structure
  • G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus

40.

SEMICONDUCTOR PACKAGE WITH ISOLATED HEAT SPREADER

      
Application Number 17719246
Status Pending
Filing Date 2022-04-12
First Publication Date 2022-07-28
Owner TEXAS INSTRUMENTS INCORPORATED (USA)
Inventor
  • Poddar, Anindya
  • Kim, Woochan
  • Arora, Vivek Kishorechand

Abstract

A semiconductor package includes a metallic pad and leads, a semiconductor die attached to the metallic pad, the semiconductor die including an active side with bond pads opposite the metallic pad, a wire bond extending from a respective bond pad of the semiconductor die to a respective lead of the leads, a heat spreader over the active side of the semiconductor die with a gap separating the active side of the semiconductor die from the heat spreader, an electrically insulating material within the gap and in contact with the active side of the semiconductor die and the heat spreader; and mold compound covering the semiconductor die and the wire bond, and partially covering the metallic pad and the heat spreader, with the metallic pad exposed on a first outer surface of the semiconductor package and with the heat spreader exposed on a second outer surface of the semiconductor package.

IPC Classes  ?

  • H01L 23/498 - Leads on insulating substrates
  • H01L 23/367 - Cooling facilitated by shape of device
  • H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
  • H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
  • H01L 23/00 - SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR - Details of semiconductor or other solid state devices
  • H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different main groups of groups , e.g. forming hybrid circuits

41.

METHOD FOR COMPREHENSIVE INTEGRATION VERIFICATION OF MIXED-SIGNAL CIRCUITS

      
Application Number 17722445
Status Pending
Filing Date 2022-04-18
First Publication Date 2022-07-28
Owner Texas Instruments Incorporated (USA)
Inventor Surendran, Sudhakar

Abstract

Disclosed examples include methods for verifying mixed-signal circuit design, in which an executable specification file is generated including integration abstractions that represent an intended integration of ports and digital circuit blocks of the mixed-signal design, a formal properties file is automatically generated from the executable specification file, an analog circuit component of the mixed-signal circuit design is modeled as a digital circuit component in a model file, at least one analog circuit block of the mixed-signal circuit design is modeled as one or more ports in the model file, and correspondence of connections of the formal properties file and the model file is verified with the mixed-signal circuit design to generate a coverage report file.

IPC Classes  ?

  • G06F 30/367 - Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
  • G06F 30/33 - Design verification, e.g. functional simulation or model checking
  • G06F 30/3323 - Design verification, e.g. functional simulation or model checking using formal methods, e.g. equivalence checking or property checking

42.

MANAGING AND MAINTAINING MULTIPLE DEBUG CONTEXTS IN A DEBUG EXECUTION MODE FOR REAL-TIME PROCESSORS

      
Application Number 17722464
Status Pending
Filing Date 2022-04-18
First Publication Date 2022-07-28
Owner TEXAS INSTRUMENTS INCORPORATED (USA)
Inventor
  • Peck, Jason Lynn
  • Cooper, Gary A.
  • Koesler, Markus

Abstract

A real-time debugger implementation maintains and manages multiple debug contexts allowing developers to interact with real-time applications without “breaking” the system in which the debug application is executing. The debugger allows multiple debug contexts to exist and allows break points in real-time and non-real-time code portions of one or more applications executing on a debug enabled core of a processor. A debug monitor function may be implemented as a hardware logic module on the same integrated circuit as the processor. Higher priority interrupt service requests may be serviced while otherwise maintaining a context for the debug session (e.g., stopped at a developer defined breakpoint). Accordingly, the application developer executing the debugger may not have to be concerned with processing occurring on the processor that may be unrelated to the current debug session.

IPC Classes  ?

  • G06F 11/36 - Preventing errors by testing or debugging of software
  • G06F 9/48 - Program initiating; Program switching, e.g. by interrupt

43.

TAG UPDATE BUS FOR UPDATED COHERENCE STATE

      
Application Number 17723559
Status Pending
Filing Date 2022-04-19
First Publication Date 2022-07-28
Owner TEXAS INSTRUMENTS INCORPORATED (USA)
Inventor
  • Chachad, Abhijeet Ashok
  • Thompson, David Matthew
  • Bhoria, Naveen
  • Hippleheuser, Peter Michael

Abstract

An apparatus includes a CPU core and a L1 cache subsystem including a L1 main cache, a L1 victim cache, and a L1 controller. The apparatus includes a L2 cache subsystem coupled to the L1 cache subsystem by a transaction bus and a tag update bus. The L2 cache subsystem includes a L2 main cache, a shadow L1 main cache, a shadow L1 victim cache, and a L2 controller. The L2 controller receives a message from the L1 controller over the tag update bus, including a valid signal, an address, and a coherence state. In response to the valid signal being asserted, the L2 controller identifies an entry in the shadow L1 main cache or the shadow L1 victim cache having an address corresponding to the address of the message and updates a coherence state of the identified entry to be the coherence state of the message.

IPC Classes  ?

  • G06F 12/0811 - Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
  • G06F 12/0815 - Cache consistency protocols
  • G06F 12/128 - Replacement control using replacement algorithms adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel
  • G06F 12/0817 - Cache consistency protocols using directory methods
  • G06F 12/084 - Multiuser, multiprocessor or multiprocessing cache systems with a shared cache
  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
  • G06F 11/30 - Monitoring
  • G06F 12/0808 - Multiuser, multiprocessor or multiprocessing cache systems with cache invalidating means
  • G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline, look ahead
  • G06F 9/46 - Multiprogramming arrangements
  • G06F 9/54 - Interprogram communication
  • G06F 12/0895 - Caches characterised by their organisation or structure of parts of caches, e.g. directory or tag array
  • G06F 12/0831 - Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means

44.

SENSOR PACKAGES WITH WAVELENGTH-SPECIFIC LIGHT FILTERS

      
Application Number 17161581
Status Pending
Filing Date 2021-01-28
First Publication Date 2022-07-28
Owner TEXAS INSTRUMENTS INCORPORATED (USA)
Inventor
  • Bito, Jo
  • Cook, Benjamin Stassen

Abstract

In examples, a sensor package comprises a die pad and a semiconductor die on the die pad. The semiconductor die has an active surface. The sensor package includes a light sensor on the active surface of the semiconductor die. The sensor package includes a mold compound covering the die pad, the semiconductor die, and a portion of the active surface. The sensor package includes a light filter covering the light sensor and abutting the mold compound. The light filter includes a combination of silicone, metal particles, and an organic dye. The combination is configured to reject light having a wavelength in a target wavelength range. The light filter has a thickness of at least 0.5 millimeters.

IPC Classes  ?

  • H01L 31/0216 - Coatings
  • H01L 31/0203 - Containers; Encapsulations
  • H01L 23/29 - Encapsulation, e.g. encapsulating layers, coatings characterised by the material
  • H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
  • H01L 23/00 - SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR - Details of semiconductor or other solid state devices

45.

TRIM/TEST INTERFACE FOR DEVICES WITH LOW PIN COUNT OR ANALOG OR NO-CONNECT PINS

      
Application Number 17537872
Status Pending
Filing Date 2021-11-30
First Publication Date 2022-07-28
Owner TEXAS INSTRUMENTS INCORPORATED (USA)
Inventor
  • Chauhan, Rajat
  • Kaur, Divya
  • Gupta, Rishav

Abstract

A trim/test interface in a packaged integrated circuit device prevents high through-current between pins of the IC device and trim/test interface digital logic within the IC device using a floating-pin-tolerant always-on CMOS input buffer. The always-on buffer uses a coupling capacitor at its input to block signals at DC and a weak-latch feedback path to ensure that intermediate or floating inputs are provided through the buffer only at one of two digital levels (e.g., those provided by a ground pin GND and by a high supply voltage pin VDD). The described interfaces and methods provide for false-entry-free test mode activation for IC devices with a low pin count, where there are a limited number of pins to cover all test/trim functions, or in which only analog, no-connect, or failsafe pins are available for trim or test mode entry control or trim or test data input.

IPC Classes  ?

  • G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
  • H03K 19/007 - Fail-safe circuits

46.

A DIGITAL FILTER FOR A DELTA-SIGMA ANALOG-TO-DIGITAL CONVERTER

      
Application Number US2022013447
Publication Number 2022/159786
Status In Force
Filing Date 2022-01-24
Publication Date 2022-07-28
Owner TEXAS INSTRUMENTS INCORPORATED (USA)
Inventor Akondy Raja Raghupathi, Venkataratna

Abstract

An analog-to-digital converter (ADC) includes a modulator, an integrator circuit (210), and first and second differentiator circuits (220, 230). The modulator has a modulator input and a modulator output. The modulator input is configured to receive an analog signal, and the modulator is configured to generate digital data on the modulator output. The integrator circuit (210) has an integrator circuit input and an integrator output. The integrator input is coupled to the modulator output. The first differentiator circuit (220) is coupled to the integrator output, and the first differentiator circuit (220) is configured to be clocked with a first clock. The second differentiator circuit (230) is coupled to the integrator output, and the second differentiator circuit (230) configured to be clocked with a second clock. The second clock is out of phase with respect to the first clock.

IPC Classes  ?

  • H03H 17/06 - Non-recursive filters
  • H03M 3/00 - Conversion of analogue values to or from differential modulation

47.

DIGITAL FILTER FOR A DELTA-SIGMA ANALOG-TO-DIGITAL CONVERTER

      
Application Number 17381460
Status Pending
Filing Date 2021-07-21
First Publication Date 2022-07-28
Owner Texas Instruments Incorporated (USA)
Inventor Akondy Raja Raghupathi, Venkataratna Subrahmanya Bharathi

Abstract

An analog-to-digital converter (ADC) includes a modulator, an integrator circuit, and first and second differentiator circuits. The modulator has a modulator input and a modulator output. The modulator input is configured to receive an analog signal, and the modulator is configured to generate digital data on the modulator output. The integrator circuit has an integrator circuit input and an integrator output. The integrator input is coupled to the modulator output. The first differentiator circuit is coupled to the integrator output, and the first differentiator circuit is configured to be clocked with a first clock. The second differentiator circuit is coupled to the integrator output, and the second differentiator circuit configured to be clocked with a second clock. The second clock is out of phase with respect to the first clock.

IPC Classes  ?

  • H03M 3/00 - Conversion of analogue values to or from differential modulation

48.

SYSTEM AND METHOD FOR THE COMPRESSION OF ECHOLOCATION DATA

      
Application Number 17405303
Status Pending
Filing Date 2021-08-18
First Publication Date 2022-07-28
Owner TEXAS INSTRUMENTS INCORPORATED (USA)
Inventor
  • Subburaj, Karthik
  • Rao, Sandeep

Abstract

A method for compressing echolocation data is provided. The method includes dividing the echolocation data into a plurality of partitions, and selecting a first partition for processing. The method also includes combining echolocation data from the first partition with echolocation data within a second partition, and combining echolocation data from the first partition with echolocation data within a third partition. The method further includes storing the combined echolocation data for all of the plurality of partitions except for the first partition in a memory.

IPC Classes  ?

  • G01S 13/58 - Velocity or trajectory determination systems; Sense-of-movement determination systems
  • G01S 13/42 - Simultaneous measurement of distance and other coordinates

49.

Combined Capacitive and Piezoelectric Sensing in a Human Machine Interface

      
Application Number 17506139
Status Pending
Filing Date 2021-10-20
First Publication Date 2022-07-28
Owner Texas Instruments Incorporated (USA)
Inventor
  • Braathen, Jan Morten
  • Lehman, Dennis Patrick
  • Oljaca, Miroslav
  • Robertson, Maxwell G
  • Newman, Merril

Abstract

A human machine interface (HMI) system and method of operating. The system includes capacitive measurement circuitry coupled to one or more capacitive touch elements, and piezoelectric measurement circuit including interface circuitry coupled to one or more piezoelectric touch elements. The capacitive measurement circuitry includes a gain stage configured to amplify a signal corresponding to a capacitance at the one or more capacitor input terminals by a gain level for communication to processing circuitry. Gain control circuitry is configured to increase the gain level of the gain stage of the capacitive measurement circuitry responsive to the piezoelectric measurement circuitry receiving a user input from at least one of the piezoelectric touch elements. Implementations that further include piezoelectric drive circuitry for haptic output and clearing debris from the keypad are also disclosed.

IPC Classes  ?

  • G06F 3/044 - Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
  • G06F 3/041 - Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means

50.

FDAC/2 SPUR ESTIMATION AND CORRECTION

      
Application Number 17538746
Status Pending
Filing Date 2021-11-30
First Publication Date 2022-07-28
Owner Texas Instruments Incorporated (USA)
Inventor
  • Gunasekaran, Karthikeyan
  • Roychowdhury, Snehasish
  • Manjunath, Rakesh
  • V S, Aswath
  • Ramakrishnan, Sthanunathan
  • Gunturi, Sarma Sudareswara
  • Sharma, Rahul
  • Venkataraman, Jagannathan
  • Viswanathan, Nagarajan

Abstract

A spur correction system for a transmit chain having an interleaving multiplexer. In some embodiments, the spur correction system includes a spur sense chain, a correction controller, and a Q path corrector. The interleaving multiplexer combines signals from multiple bands in response to a clock signal. The spur sense chain estimates an error that is in phase with the clock signal (an I-phase error) and an error that is a derivative of the clock signal (a Q-phase error). The correction controller compensates for the estimated I-phase error by injecting an I-phase correction signal into the transmit chain. The Q path corrector compensates for the estimated Q-phase error by selectively connecting one or more capacitors within the interleaving multiplexer.

IPC Classes  ?

51.

DIRECT CURRENT (DC)-DC CONVERTER

      
Application Number US2022012870
Publication Number 2022/159424
Status In Force
Filing Date 2022-01-19
Publication Date 2022-07-28
Owner TEXAS INSTRUMENTS INCORPORATED (USA)
Inventor
  • Ragona, Scott, Edward
  • Chen, Rengang
  • Tadeparthy, Preetam, Charan Anand
  • Reutzel, Evan, Michael

Abstract

A converter stage having a control pin, an input voltage pin, an output pin, a ground pin, a high- side switch coupled between the input voltage pin and the output pin, a low-side switch coupled between the output pin and the ground pin, a current sensor configured to detect a current at the output pin, and control logic coupled to the control pin and the current sensor. The control logic is configured to control switching of the high-side and the low-side switches and in continuous conduction mode, discontinuous conduction mode, and body braking control for the converter stage in response to a first signal received via the control pin and a second signal received from the current sensor. A driver controls switching, based on the detected current and sequential event tracking, between an on state and an off state.

IPC Classes  ?

  • H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
  • G05F 1/573 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for protection with overcurrent detector

52.

MULTI-PERIPHERAL AND/OR MULTI-FUNCTION EXPORT

      
Application Number US2022013217
Publication Number 2022/159645
Status In Force
Filing Date 2022-01-21
Publication Date 2022-07-28
Owner TEXAS INSTRUMENTS INCORPORATED (USA)
Inventor
  • Govindarajan, Sriramakrishnan
  • Israel Vijayponraj, Kishon Vijay Abraham
  • Mody, Mihir, Narendra
  • Kanumuri, Vijaya Rama, Raju
  • Stewart, Cory, Dean

Abstract

A system (300) is provided. In some examples, the system includes a first peripheral circuit (370) and a memory management circuit (360) coupled to the first peripheral circuit. The memory management circuit comprises a first table (362) that associates virtual identification values with address space select values. The system also includes a transaction mapper circuit (342) coupled to the memory management circuit. The transaction mapper circuit comprises a second table that associates virtual identification values with bus-device-function values.

IPC Classes  ?

53.

SEMICONDUCTOR APPARATUS AND METHOD HAVING A LEAD FRAME WITH FLOATING LEADS

      
Application Number 17568625
Status Pending
Filing Date 2022-01-04
First Publication Date 2022-07-21
Owner Texas Instruments Incorporated (USA)
Inventor Shibuya, Makoto

Abstract

In described examples, a packaged semiconductor device includes a frame, a pre-fabricated interposer, and an integrated circuit die. The frame includes multiple conductive frame leads and multiple conductive connection points, as well as a hole in the frame surrounded by the frame leads and the conductive connection points. The pre-molded interposer has an external perimeter including multiple conductive interposer leads, and is for insertion into the hole. At least one of the interposer leads does not extend to the external perimeter of the interposer. The die is electrically coupled to selected ones of the frame leads and of the interposer leads. The interposer is inserted into the hole and coupled to the frame, and the frame, interposer, and die are together encapsulated by encapsulation material.

IPC Classes  ?

  • H01L 23/498 - Leads on insulating substrates
  • H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
  • H01L 23/00 - SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR - Details of semiconductor or other solid state devices

54.

OPERATING MODES FOR TESTING MONITOR CIRCUITS

      
Application Number 17576001
Status Pending
Filing Date 2022-01-14
First Publication Date 2022-07-21
Owner Texas Instruments Incorporated (USA)
Inventor
  • Xhafa, Ariton E.
  • Giaramita, Mathew
  • Fu, Minghua
  • Kandhalu, Arvind
  • Nafziger, Jonathan

Abstract

A system is provided. In some examples, the system includes a control circuit and a plurality of monitor circuits including a first monitor circuit. In a production mode, the control circuit is configured to test the plurality of monitor circuits. In a storage mode after testing the plurality of monitor circuits in the production mode, the control circuit is configured to test the plurality of monitor circuits more than once. In an assembly mode after testing the plurality of monitor circuits in the storage mode, the control circuit is configured to test the plurality of monitor circuits. In one or more examples, the control circuit is configured to skip the storage mode and test the plurality of monitor circuits in the assembly mode after testing in the production mode.

IPC Classes  ?

  • H02J 7/00 - Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
  • G01R 31/382 - Arrangements for monitoring battery or accumulator variables, e.g. SoC

55.

SCAN TESTABLE THROUGH SILICON VIAs

      
Application Number 17715006
Status Pending
Filing Date 2022-04-06
First Publication Date 2022-07-21
Owner TEXAS INSTRUMENTS INCORPORATED (USA)
Inventor Whetsel, Lee D.

Abstract

In one example, an integrated circuit comprises a die. The die has a first surface and a second surface, the second surface opposite to the first surface. The die also includes: a first contact on the first surface and a second contact on the second surface; a through silicon via having a first end and a second end, the first end coupled to the first contact and the second end coupled to the second contact; and a scan cell having a control input, a response input, and a stimulus output, the response input coupled to the first end and the stimulus output coupled to the second end.

IPC Classes  ?

  • H01L 21/66 - Testing or measuring during manufacture or treatment
  • G01R 31/3185 - Reconfiguring for testing, e.g. LSSD, partitioning
  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
  • H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

56.

CONFIGURABLE CACHE FOR MULTI-ENDPOINT HETEROGENEOUS COHERENT SYSTEM

      
Application Number 17715022
Status Pending
Filing Date 2022-04-06
First Publication Date 2022-07-21
Owner TEXAS INSTRUMENTS INCORPORATED (USA)
Inventor
  • Chirca, Kai
  • Pierson, Matthew David

Abstract

A device includes a memory bank. The memory bank includes data portions of a first way group. The data portions of the first way group include a data portion of a first way of the first way group and a data portion of a second way of the first way group. The memory bank further includes data portions of a second way group. The device further includes a configuration register and a controller configured to individually allocate, based on one or more settings in the configuration register, the first way and the second way to one of an addressable memory space and a data cache.

IPC Classes  ?

  • G06F 12/084 - Multiuser, multiprocessor or multiprocessing cache systems with a shared cache
  • G06F 12/0811 - Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
  • G06F 12/1009 - Address translation using page tables, e.g. page table structures
  • G06F 12/0875 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
  • G06F 12/10 - Address translation
  • G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
  • G06F 13/40 - Bus structure
  • G06F 12/0855 - Overlapped cache accessing, e.g. pipeline
  • G06F 12/06 - Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication
  • G06F 12/0817 - Cache consistency protocols using directory methods
  • G06F 12/0831 - Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
  • G06F 13/12 - Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
  • G06F 3/06 - Digital input from, or digital output to, record carriers
  • G06F 12/0815 - Cache consistency protocols
  • H03M 13/01 - Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
  • H03M 13/09 - Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
  • H03M 13/15 - Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
  • H03M 13/27 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline, look ahead
  • G06F 9/48 - Program initiating; Program switching, e.g. by interrupt
  • G06F 9/50 - Allocation of resources, e.g. of the central processing unit [CPU]
  • G06F 12/0891 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means

57.

PASSIVE COMPONENTS WITH IMPROVED CHARACTERISTICS

      
Application Number 17152230
Status Pending
Filing Date 2021-01-19
First Publication Date 2022-07-21
Owner TEXAS INSTRUMENTS INCORPORATED (USA)
Inventor
  • West, Jeffrey Alan
  • Williams, Byron Lovell
  • Stewart, Elizabeth Costner
  • Bonifeld, Thomas Dyer

Abstract

Described examples include a hybrid circuit having a component. The component has a first conductive element on a substrate having a configuration and having a first periphery and having an extension at the first periphery. The component also has a dielectric on the first conductive element. The component also has a second conductive element having the configuration on the dielectric that is proximate to and aligned with the first conductive element, and has a second periphery, the extension of the first conductive element extending past the second periphery.

IPC Classes  ?

58.

DEVICES AND METHODS TO CONTROL DYNAMIC AUDIO RANGE IN BOOSTED AUDIO SYSTEMS

      
Application Number 17340506
Status Pending
Filing Date 2021-06-07
First Publication Date 2022-07-21
Owner TEXAS INSTRUMENTS INCORPORATED (USA)
Inventor
  • Palit, Supriyo
  • Chawla, Mohit

Abstract

A controller regulates the voltage delivered to the load and current drawn from the battery in an audio system depending on ripple in the battery voltage which is input to the controller to allocate power for audio playback. Regulation maximizes available headroom while avoiding audio clipping. The effect of internal battery and external parasitic resistance (ESR) on ripple is compensated by an iterative process. ESR is rapidly increased whenever the minimum of the battery voltage input to the controller falls below a clipping threshold and slowly decreased whenever such voltage exceeds such threshold and the audio is under compression. A limiter allocates power to utilize more of the available audio headroom. A de-emphasis filter in each audio signal path compensates for capacitive ripple in the battery voltage input to the controller. As the frequency of the audio input changes, the filter(s) allow frequency-dependent power/current regulation to fill the full audio range without distortion.

IPC Classes  ?

  • G05F 1/625 - Regulating voltage or current wherein it is irrelevant whether the variable actually regulated is ac or dc
  • H03G 3/30 - Automatic control in amplifiers having semiconductor devices
  • H04R 3/04 - Circuits for transducers for correcting frequency response
  • H04R 29/00 - Monitoring arrangements; Testing arrangements
  • H04S 1/00 - Two-channel systems

59.

DUAL MODE DIGITAL FILTERS FOR RF SAMPLING TRANSCEIVERS

      
Application Number 17463317
Status Pending
Filing Date 2021-08-31
First Publication Date 2022-07-21
Owner Texas Instruments Incorporated (USA)
Inventor
  • Balakrishnan, Jaiganesh
  • Murali, Sriram
  • Gudipati, Kalyan
  • Pothapu, Venkateshwara Reddy
  • Gunturi, Sarma Sundareswara

Abstract

Dual mode filters having two reconfigurable multi-stage filters. In a dual band mode, each reconfigurable filter filters an input signal in a different band using every filter stage. In a single band mode, both reconfigurable filters are effectively divided into two sub-chains that include either the odd-numbered filter stages or the even-numbered filter stages. Together, the four sub-chains in the single band mode filter an input signal in a single band with a higher parallelization than each reconfigurable filter in the dual band mode. In some embodiments, the dual mode filter is a decimation filter. In other embodiments, the dual mode filter is a resampling filter. In still other embodiments, the dual mode filter is an interpolation filter.

IPC Classes  ?

60.

MULTI-PERIPHERAL AND/OR MULTI-FUNCTION EXPORT

      
Application Number 17538662
Status Pending
Filing Date 2021-11-30
First Publication Date 2022-07-21
Owner Texas Instruments Incorporated (USA)
Inventor
  • Govindarajan, Sriramakrishnan
  • Israel Vijayponraj, Kishon Vijay Abraham
  • Mody, Mihir Narendra
  • Kanumuri, Vijaya Rama Raju
  • Stewart, Cory Dean

Abstract

A system is provided. In some examples, the system includes a first peripheral circuit and a memory management circuit coupled to the first peripheral circuit. The memory management circuit comprises a first table that associates virtual identification values with address space select values. The system also includes a transaction mapper circuit coupled to the memory management circuit. The transaction mapper circuit comprises a second table that associates virtual identification values with bus-device-function values.

IPC Classes  ?

  • G06F 12/02 - Addressing or allocation; Relocation
  • G06F 12/06 - Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication
  • G06F 9/46 - Multiprogramming arrangements

61.

CONFIGURABLE LEADED PACKAGE

      
Application Number 17560229
Status Pending
Filing Date 2021-12-22
First Publication Date 2022-07-21
Owner Texas Instruments Incorporated (USA)
Inventor Koduri, Sreenivasan Kalyani

Abstract

A semiconductor package includes a base insulating layer; a semiconductor die attached to a portion of the base insulating layer; and a first continuous lead electrically connected to the semiconductor die. The first continuous lead includes a first lateral extension on a first surface of the base insulating layer, a second lateral extension on a second surface of the base insulating layer, and a connecting portion between the first lateral extension and the second lateral extension. The connecting portion penetrates through the base insulating layer.

IPC Classes  ?

  • H01L 23/498 - Leads on insulating substrates
  • H01L 23/00 - SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR - Details of semiconductor or other solid state devices
  • H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
  • H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups

62.

POWER CONVERTER CONTROL WITH SNOOZE MODE

      
Application Number US2022011760
Publication Number 2022/155079
Status In Force
Filing Date 2022-01-10
Publication Date 2022-07-21
Owner TEXAS INSTRUMENTS INCORPORATED (USA)
Inventor
  • Blanco, Andres, Arturo
  • Luo, Ming

Abstract

In an example, an apparatus (110) comprises a control signal generator (202) and a snooze mode controller (204). The control signal generator includes an error amplifier (208) having a first output, a first input, a second input, and a first snooze input, a first comparator (210) having a second output, a third input coupled to the first output, and a fourth input, and a second comparator (212) having a third output, a fifth input coupled to the third input, a sixth input, and a second snooze input. The control signal generator also includes a logic circuit (218) having a fourth output and logic circuit inputs, a first of the logic circuit inputs coupled to the second output, and a pulse generator (220) having a fifth output and a seventh input, the seventh input coupled to the fourth output. The snooze mode controller has a sixth output coupled to the first snooze input and the second snooze input.

IPC Classes  ?

  • H02M 3/156 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators

63.

CALIBRATION SCHEME FOR A NON-LINEAR ADC

      
Application Number US2022012066
Publication Number 2022/155161
Status In Force
Filing Date 2022-01-12
Publication Date 2022-07-21
Owner TEXAS INSTRUMENTS INCORPORATED (USA)
Inventor
  • Varshney, Himanshu
  • Nagarajan, Viswanathan
  • Babu, Charls
  • Rajagopal, Narasimhan
  • Miglani, Eeshan
  • Pentakota, Visvesvaraya, A.

Abstract

In described examples, an analog to digital converter (ADC) (100), having an input operable to receive an analog signal (110) and an output operable to output (130) a digital representation of the analog signal, includes a voltage to delay (VD) block (106). The VD block (106) is coupled to the input of the ADC (100) and generates a delay signal responsive to a calibration signal. A backend ADC (124) is coupled to the VD block (106), and receives the delay signal. The backend ADC (124) having multiple stages including a first stage. A calibration engine (102) is coupled to the multiple stages and the VD block (106). The calibration engine (102) measures an error count of the first stage and stores a delay value of the first stage for which the error count is minimum.

IPC Classes  ?

  • H03M 1/10 - Calibration or testing
  • H03M 1/42 - Sequential comparisons in series-connected stages with no change in value of analogue signal

64.

EXHAUST GAS MONITOR FOR PHOTORESIST ADHESION CONTROL

      
Application Number US2022012404
Publication Number 2022/155396
Status In Force
Filing Date 2022-01-14
Publication Date 2022-07-21
Owner TEXAS INSTRUMENTS INCORPORATED (USA)
Inventor Plourde, Joseph, Peter

Abstract

An exhaust stream monitoring system (100) for a photolithography track of an IC fabrication process comprises a reaction chamber (102) including a housing (104), an inflow port (106) and an outflow port (112), the housing (104) containing a thermal plate (108) for heating a semiconductor process wafer (110) for a predetermined amount of time. An influent pipe (117) coupled to the inflow port (106) supplies a photoresist adhesion promoter (119) in a gaseous form to the reaction chamber (102). An effluent pipe (130) coupled to the outflow port (112) is operative to remove byproducts from the reaction chamber (102) as an exhaust stream. At least one gas sensor manifold assembly (132) is coupled to the effluent pipe (130) for monitoring the exhaust stream from the reaction chamber (102) to detect presence of one or more byproducts of a reaction between the photoresist adhesion promoter (119) and the semiconductor process wafer (110).

IPC Classes  ?

  • H01L 21/027 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

65.

Direct Current (DC)-DC Converter

      
Application Number 17152223
Status Pending
Filing Date 2021-01-19
First Publication Date 2022-07-21
Owner Texas Instruments Incorporated (USA)
Inventor
  • Ragona, Scott Edward
  • Chen, Rengang
  • Tadeparthy, Preetam Charan Anand
  • Reutzel, Evan Michael

Abstract

A converter stage having a control pin, an input voltage pin, an output pin, a ground pin, a high-side switch coupled between the input voltage pin and the output pin, a low-side switch coupled between the output pin and the ground pin, a current sensor configured to detect a current at the output pin, and control logic coupled to the control pin and the current sensor. The control logic is configured to control switching of the high-side and the low-side switches in continuous conduction mode, discontinuous conduction mode, and body braking control for the converter stage in response to a first signal received via the control line and a second signal received from the current sensor. A driver controls switching, based on the detected current and sequential event tracking, between an on state and an off state.

IPC Classes  ?

  • H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
  • H02M 3/157 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
  • H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters

66.

Systems and Methods for Programming Electrical Fuse

      
Application Number 17411262
Status Pending
Filing Date 2021-08-25
First Publication Date 2022-07-21
Owner Texas Instruments Incorporated (USA)
Inventor
  • Paulose, Ajai
  • Ganesan, Aravind
  • Venkatraman, Sashidharan
  • Balakrishnan, Jaiganesh

Abstract

A system for programming an eFuse array in an integrated circuit (IC) includes an eFuse data file which has a first plurality of bits. The system includes a data compression module which has an input coupled to receive the eFuse data file. The data compression module reduces the size of the eFuse data file and provides a compressed data file. The compressed data file has fewer bits than the eFuse data file. The system includes an eFuse controller which has an input coupled to receive the compressed data file. The eFuse controller programs the eFuse array to permanently store the compressed data file in the eFuse array.

IPC Classes  ?

  • G06F 30/34 - Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
  • G06F 16/174 - Redundancy elimination performed by the file system

67.

DRAIN CONTACT EXTENSION LAYOUT FOR HARD SWITCHING ROBUSTNESS

      
Application Number 17499462
Status Pending
Filing Date 2021-10-12
First Publication Date 2022-07-21
Owner Texas Instruments Incorporated (USA)
Inventor
  • Lee, Dong Seup
  • Joh, Jungwoo

Abstract

A microelectronic device includes a GaN FET on a substrate such as silicon and a buffer layer of III-N semiconductor material. The GaN FET includes both source contacts and drain contacts to a channel layer of III-N semiconductor material. Source contacts to the source region are placed farther from the gate electrode fingertip than drain contacts to the drain region.

IPC Classes  ?

  • H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 29/66 - Types of semiconductor device

68.

OPEN LOOP WAKE-UP RADIO BASED ON TRANSMITTER FINGERPRINTING

      
Application Number 17712236
Status Pending
Filing Date 2022-04-04
First Publication Date 2022-07-21
Owner TEXAS INSTRUMENTS INCORPORATED (USA)
Inventor
  • Alpert, Yaron
  • Ben-Shachar, Matan
  • Shani, Oren Aharon

Abstract

A device (e.g., an IoT device) includes a first radio, and a memory device accessible to the first radio. The memory device is configured to store a fingerprinting feature for a specific transmitter device. A second radio and a processor are also included. The process is coupled to the first and second radios. The first radio is configured to extract a fingerprinting feature of a first received wireless signal, determine that the extracted feature matches the fingerprinting feature stored in the storage device, and responsive to the determination that the extracted feature matches the feature stored in the storage device, cause the second radio to transition from a lower power state to a higher power state of operation and continue to receive the incoming signal.

IPC Classes  ?

  • H04W 52/02 - Power saving arrangements
  • H04W 4/70 - Services for machine-to-machine communication [M2M] or machine type communication [MTC]

69.

Method and Apparatus for Dual Issue Multiply Instructions

      
Application Number 17713002
Status Pending
Filing Date 2022-04-04
First Publication Date 2022-07-21
Owner Texas Instruments Incorporated (USA)
Inventor
  • Anderson, Timothy David
  • Rahman, Mujibur

Abstract

A method is provided that includes performing, by a processor in response to a dual issue multiply instruction, multiplication of operands of the dual issue multiply instruction using multiplication units comprised in a data path of the processor and configured to operate together to determine a product of the operands, and storing, by the processor, the product in a storage location indicated by the dual issue multiply instruction.

IPC Classes  ?

  • G06F 12/1045 - Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
  • G06F 9/345 - Addressing or accessing the instruction operand or the result of multiple operands or results
  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline, look ahead
  • G06F 11/00 - Error detection; Error correction; Monitoring
  • G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
  • G06F 7/24 - Sorting, i.e. extracting data from one or more carriers, re-arranging the data in numerical or other ordered sequence, and re-recording the sorted data on the original carrier or on a different carrier or set of carriers
  • G06F 7/487 - Multiplying; Dividing
  • G06F 7/499 - Denomination or exception handling, e.g. rounding, overflow
  • G06F 7/53 - Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
  • G06F 7/57 - Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups  or for performing logical operations
  • G06F 9/48 - Program initiating; Program switching, e.g. by interrupt
  • G06F 17/16 - Matrix or vector computation
  • H03H 17/06 - Non-recursive filters
  • G06F 9/32 - Address formation of the next instruction, e.g. by incrementing the instruction counter
  • G06F 12/0875 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
  • G06F 12/0897 - Caches characterised by their organisation or structure with two or more cache hierarchy levels
  • G06F 12/0862 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
  • G06F 12/1009 - Address translation using page tables, e.g. page table structures

70.

POWER CONVERTER CONTROL WITH SNOOZE MODE

      
Application Number 17713107
Status Pending
Filing Date 2022-04-04
First Publication Date 2022-07-21
Owner TEXAS INSTRUMENTS INCORPORATED (USA)
Inventor
  • Blanco, Andres Arturo
  • Luo, Ming

Abstract

A control signal generator includes an error amplifier, a first comparator, a second comparator, a logic circuit and a pulse generator. The error amplifier has a first output, a first input, a second input and a first snooze input. The first comparator has a second output, a third input and a fourth input. The third input is coupled to the first output. The second comparator has a third output, a fifth input, a sixth input and a second snooze input. The fifth input is coupled to the third input. The logic circuit has a fourth output and logic circuit inputs, including a first logic circuit input coupled to the second output. The pulse generator has a fifth output and a seventh input. The seventh input is coupled to the fourth output. A snooze mode controller has a sixth output coupled to the first snooze input and the second snooze input.

IPC Classes  ?

  • H02M 3/335 - Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
  • H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion
  • H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters

71.

GLOBAL COHERENCE OPERATIONS

      
Application Number 17713287
Status Pending
Filing Date 2022-04-05
First Publication Date 2022-07-21
Owner TEXAS INSTRUMENTS INCORPORATED (USA)
Inventor
  • Chachad, Abhijeet Ashok
  • Bhoria, Naveen
  • Thompson, David Matthew
  • Muralidharan, Neelima

Abstract

A method includes receiving, by a L2 controller, a request to perform a global operation on a L2 cache and preventing new blocking transactions from entering a pipeline coupled to the L2 cache while permitting new non-blocking transactions to enter the pipeline. Blocking transactions include read transactions and non-victim write transactions. Non-blocking transactions include response transactions, snoop transactions, and victim transactions. The method further includes, in response to an indication that the pipeline does not contain any pending blocking transactions, preventing new snoop transactions from entering the pipeline while permitting new response transactions and victim transactions to enter the pipeline; in response to an indication that the pipeline does not contain any pending snoop transactions, preventing, all new transactions from entering the pipeline; and, in response to an indication that the pipeline does not contain any pending transactions, performing the global operation on the L2 cache.

IPC Classes  ?

  • G06F 9/46 - Multiprogramming arrangements
  • G06F 9/48 - Program initiating; Program switching, e.g. by interrupt
  • G06F 9/448 - Execution paradigms, e.g. implementations of programming paradigms
  • G06F 11/30 - Monitoring
  • G06F 9/54 - Interprogram communication
  • G06F 12/0811 - Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline, look ahead
  • G06F 12/0813 - Multiuser, multiprocessor or multiprocessing cache systems with a network or matrix configuration
  • G06F 12/0817 - Cache consistency protocols using directory methods
  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
  • G06F 12/0871 - Allocation or management of cache space
  • G06F 12/0891 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
  • G06F 12/12 - Replacement control
  • G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
  • G06F 12/0888 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using selective caching, e.g. bypass
  • G06F 12/0831 - Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
  • G06F 12/0855 - Overlapped cache accessing, e.g. pipeline

72.

OPAMP OVERLOAD POWER LIMIT CIRCUIT, SYSTEM, AND A METHOD THEREOF

      
Application Number 17715605
Status Pending
Filing Date 2022-04-07
First Publication Date 2022-07-21
Owner TEXAS INSTRUMENTS INCORPORATED (USA)
Inventor
  • Udayashankar, Sudarshan
  • Snoeij, Martijn Fridus

Abstract

An amplifier overload power limit circuit, system, and a method thereof comprising a monitoring of a current gain of a BJT based on a current detector and limiting power to the BJT based on the monitored current gain to prevent the BJT from driven into a saturation mode and the amplifier overdrive.

IPC Classes  ?

  • H03K 17/082 - Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit
  • H01L 29/66 - Types of semiconductor device

73.

INTEGRATED GUARD STRUCTURE FOR CONTROLLING CONDUCTIVITY MODULATION IN DIODES

      
Application Number US2022011763
Publication Number 2022/155080
Status In Force
Filing Date 2022-01-10
Publication Date 2022-07-21
Owner TEXAS INSTRUMENTS INCORPORATED (USA)
Inventor Appaswamy, Aravind, Chennimalai

Abstract

A microelectronic device (100) includes an integrated guard structure diode (102) on the substrate (104). The integrated guard structure diode (102) includes a first terminal of the diode (134), a second terminal of the diode (136), and a guard structure (138). The guard structure (138) is between the first terminal of the diode (134) and the second terminal of the diode (136). The first terminal of the diode (134) and guard structure (138) are electrically connected to each other. An optional switching element (154) may provide selective electrical connection between the first terminal of the diode (134) and the guard structure (138). Adding a guard structure (138) electrically connected first terminal of the diode (134), with the guard structure (138) between the first terminal of the diode (134) and the second terminal of the diode (136) provides higher break down voltage than a diode without a guard structure (138).

IPC Classes  ?

  • H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
  • H01L 29/861 - Diodes

74.

CALIBRATION OF PARAMETRIC ERROR OF DIGITAL-TO-TIME CONVERTERS

      
Application Number US2022012085
Publication Number 2022/155176
Status In Force
Filing Date 2022-01-12
Publication Date 2022-07-21
Owner TEXAS INSTRUMENTS INCORPORATED (USA)
Inventor Perrott, Michael Henderson

Abstract

In some examples, a circuit includes a clock divider (102) and a calibration circuit (104) coupled to the clock divider. The clock divider includes digital-to-time converter (DTC) (204). The calibration circuit configured to determine a gain error and a parametric integrated nonlinearity (INL) error of the DTC, determine a gain adjustment value and a INL adjustment value to compensate for the gain error and the INL error, and modify operation of the DTC according to the gain adjustment value and the INL adjustment value to correct for the gain error and the INL error.

IPC Classes  ?

  • H03M 1/82 - Digital/analogue converters with intermediate conversion to time interval
  • H03K 3/02 - Generators characterised by the type of circuit or by the means used for producing pulses

75.

SYSTEMS AND METHODS FOR PROGRAMMING ELECTRICAL FUSE

      
Application Number US2022012704
Publication Number 2022/155581
Status In Force
Filing Date 2022-01-18
Publication Date 2022-07-21
Owner TEXAS INSTRUMENTS INCORPORATED (USA)
Inventor
  • Paulose, Ajai
  • Ganesan, Aravind
  • Venkatraman, Sashidharan
  • Balakrishnan, Jaiganeshry

Abstract

A system for programming an eFuse array in an integrated circuit (IC) includes an cFuse data file (104) which has a first plurality of bits. The system includes a data compression module (110) which has an input (112) coupled to receive the eFuse data file (104). The data compression module (104) reduces the size of the eFuse data file (104) and provides a compressed data file. The compressed data file has fewer bits than the eFuse data file (104). The system includes an eFuse controller (120) which has an input (122) coupled to receive the compressed data file. The eFuse controller programs the eFuse array (130) to permanently store the compressed data file in the eFuse array(130).

IPC Classes  ?

  • G11C 16/12 - Programming voltage switching circuits
  • G06F 12/02 - Addressing or allocation; Relocation

76.

Methods, apparatus, and articles of manufacture to determine memory access integrity based on feedback from memory

      
Application Number 17187492
Grant Number 11392455
Status In Force
Filing Date 2021-02-26
First Publication Date 2022-07-19
Grant Date 2022-07-19
Owner Texas Instruments Incorporated (USA)
Inventor
  • Langadi, Saya Goud
  • Foley, David Peter

Abstract

Methods, apparatus, systems, and articles of manufacture are disclosed to determine memory access integrity based on feedback from memory. An example apparatus includes an access reconstruction controller including an output, a first input configured to be coupled to memory, and a second input configured to be coupled to a memory signal generator; a comparator including a first input coupled to the output of the access reconstruction controller, a second input configured to be coupled to an arbiter, and an output configured to be coupled to the arbiter; and a data integrity monitor including an input coupled to the second input of the comparator and configured to be coupled to the arbiter and an output coupled to the output of the comparator and configured to be coupled to the arbiter.

IPC Classes  ?

  • G11C 29/00 - Checking stores for correct operation; Testing stores during standby or offline operation
  • G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
  • G06F 11/07 - Responding to the occurrence of a fault, e.g. fault tolerance
  • G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
  • G06F 11/30 - Monitoring

77.

Dynamic image warping

      
Application Number 17232873
Grant Number 11394940
Status In Force
Filing Date 2021-04-16
First Publication Date 2022-07-19
Grant Date 2022-07-19
Owner TEXAS INSTRUMENTS INCORPORATED (USA)
Inventor
  • Martin, Samuel Edward
  • Schleich, Jackson Grant

Abstract

A system includes a first projector and a second projector offset from the first projector. The system includes a rail and a controller coupled to the first projector and to the second projector. The controller is configured to move the first projector and the second projector along the rail. The controller is also configured to apply a first warping correction to a first image projected by the first projector, based at least in part on a position of the first projector. The controller is further configured to apply a second warping correction to a second image projected by the second projector, based at least in part on a position of the second projector.

IPC Classes  ?

  • H04N 9/31 - Projection devices for colour picture display
  • G06F 3/01 - Input arrangements or combined input and output arrangements for interaction between user and computer
  • H04N 17/00 - Diagnosis, testing or measuring for television systems or their details
  • H04N 13/349 - Multi-view displays for displaying three or more geometrical viewpoints without viewer tracking
  • H04N 13/366 - Image reproducers using viewer tracking
  • H04N 13/327 - Calibration thereof

78.

SPRING BAR LEADFRAME, METHOD AND PACKAGED ELECTRONIC DEVICE WITH ZERO DRAFT ANGLE

      
Application Number 17683768
Status Pending
Filing Date 2022-03-01
First Publication Date 2022-07-14
Owner Texas Instruments Incorporated (USA)
Inventor
  • Lee, Lee Han Meng@eugene
  • Bin Abdul Aziz, Anis Fauzi
  • Lim, Sueann Wei Fen
  • Lim, Jin Keong

Abstract

A method includes attaching semiconductor dies to die attach pads of first and second columns of the lead frame; enclosing the semiconductor dies of the respective columns in respective first and second package structures; trimming the lead frame to separate respective first and second lead portions of adjacent ones of the first and second columns of the lead frame; moving the first columns along a column direction relative to the second columns; and separating individual packaged electronic devices of the respective first and second columns from one another.

IPC Classes  ?

  • H01L 23/495 - Lead-frames
  • H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
  • H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
  • H01L 23/00 - SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR - Details of semiconductor or other solid state devices
  • H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
  • H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement

79.

METHOD, SYSTEM AND APPARATUS FOR INTRA-REFRESH IN VIDEO SIGNAL PROCESSING

      
Application Number 17706607
Status Pending
Filing Date 2022-03-29
First Publication Date 2022-07-14
Owner Texas Instruments Incorporated (USA)
Inventor
  • Siddaramanna, Mahant
  • Dutt, Yashwant

Abstract

A video codec for encoding a sequence of video frames divides a video frame area into number of row segments. The Video encoder selects a different set of row segments in each video frame in a set of video frames and encodes the selected set of row segments by intra-prediction. As a result, the selected part of the frame is intra-refreshed. The video codec limits the maximum value of the vertical global motion vector GMVy to zero and video codec adjust the number of row segments in the select set of row segments based on the height of the search range configured for the motion estimation. As a result, the video codec may not refer to an un-refreshed portion in the previous frame for encoding an already refreshed area of the current frame.

IPC Classes  ?

  • H04N 19/527 - Global motion vector estimation
  • H04N 19/107 - Selection of coding mode or of prediction mode between spatial and temporal predictive coding, e.g. picture refresh
  • H04N 19/124 - Quantisation
  • H04N 19/174 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a slice, e.g. a line of blocks or a group of blocks
  • H04N 19/167 - Position within a video image, e.g. region of interest [ROI]

80.

PACKAGE SUBSTRATE WITH PARTIALLY RECESSED CAPACITOR

      
Application Number 17707872
Status Pending
Filing Date 2022-03-29
First Publication Date 2022-07-14
Owner TEXAS INSTRUMENTS INCORPORATED (USA)
Inventor
  • Williamson, Jaimal Mallory
  • Sinha, Snehamay

Abstract

A semiconductor package includes a multilayer substrate including a dielectric layer, a first conductive layer forming a first set of electrical contacts, a second conductive layer forming package electrical contacts and two capacitor electrical contacts, conductive vias extending through the dielectric layer between the first conductive layer with the second conductive layer, and a solder mask layer over the second conductive layer. The semiconductor package further includes a semiconductor die on the first side of the multilayer substrate electrically connected a capacitor on the second side of the multilayer substrate. A recessed portion of the capacitor is within a capacitor opening of the solder mask layer between the two capacitor electrical contacts and a board-side surface of the solder mask layer.

IPC Classes  ?

  • H01L 23/498 - Leads on insulating substrates
  • H01L 23/64 - Impedance arrangements
  • H01L 23/00 - SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR - Details of semiconductor or other solid state devices
  • H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups

81.

INVERSE TRANSFORMATION USING PRUNING FOR VIDEO CODING

      
Application Number 17710932
Status Pending
Filing Date 2022-03-31
First Publication Date 2022-07-14
Owner Texas Instruments Incorporated (USA)
Inventor
  • Budagavi, Madhukar
  • Sze, Vivienne

Abstract

A method for decoding an encoded video bit stream in a video decoder is provided that includes determining a scan pattern type for a transform block to be decoded, decoding a column position X and a row position Y of a last non-zero coefficient in the transform block from the encoded video bit stream, selecting a column-row inverse transform order when the scan pattern type is a first type, selecting a row-column inverse transform order when the scan pattern type is a second type, and performing one dimensional (1D) inverse discrete cosine transformation (IDCT) computations according to the selected transform order to inversely transform the transform block to generate a residual block.

IPC Classes  ?

  • G06F 17/14 - Fourier, Walsh or analogous domain transformations
  • H04N 19/176 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
  • H04N 19/46 - Embedding additional information in the video signal during the compression process
  • H04N 19/134 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or criterion affecting or controlling the adaptive coding
  • H04N 19/122 - Selection of transform size, e.g. 8x8 or 2x4x8 DCT; Selection of sub-band transforms of varying structure or type
  • H04N 19/61 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding in combination with predictive coding
  • H04N 19/14 - Coding unit complexity, e.g. amount of activity or edge presence estimation
  • H04N 19/18 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being a set of transform coefficients
  • H04N 19/48 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using compressed domain processing techniques other than decoding, e.g. modification of transform coefficients, variable length coding [VLC] data or run-length data
  • H04N 19/42 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals - characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation

82.

USING NATURAL MOVEMENTS OF A HAND-HELD DEVICE TO MANIPULATE DIGITAL CONTENT

      
Application Number 17710951
Status Pending
Filing Date 2022-03-31
First Publication Date 2022-07-14
Owner TEXAS INSTRUMENTS INCORPORATED (USA)
Inventor Sharma, Vinay

Abstract

A mobile device, such as a smart phone, is provided with a camera. Digital content displayed on display screen of the mobile device may be manipulated in response to natural movements of the mobile device by a user. Motion of the mobile device is detected relative to a nearby textured surface by analyzing images of the textured surface. The displayed digital content is manipulated in response to the detected motion of the mobile device.

IPC Classes  ?

  • G06F 3/01 - Input arrangements or combined input and output arrangements for interaction between user and computer
  • H04N 9/31 - Projection devices for colour picture display
  • G06T 7/73 - Determining position or orientation of objects or cameras using feature-based methods
  • G06F 3/03 - Arrangements for converting the position or the displacement of a member into a coded form
  • G06F 3/0346 - Pointing devices displaced or positioned by the user; Accessories therefor with detection of the device orientation or free movement in a 3D space, e.g. 3D mice, 6-DOF [six degrees of freedom] pointers using gyroscopes, accelerometers or tilt-sensors
  • G09G 5/377 - Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of individual graphic patterns using a bit-mapped memory - Details of the operation on graphic patterns for mixing or overlaying two or more graphic patterns
  • G06F 3/0482 - Interaction techniques based on graphical user interfaces [GUI] based on specific properties of the displayed interaction object or a metaphor-based environment, e.g. interaction with desktop elements like windows or icons, or assisted by a cursor's changing behaviour or appearance interaction with lists of selectable items, e.g. menus
  • G06F 3/04845 - Interaction techniques based on graphical user interfaces [GUI] for the control of specific functions or operations, e.g. selecting or manipulating an object or an image, setting a parameter value or selecting a range for image manipulation, e.g. dragging, rotation, expansion or change of colour
  • G06T 15/04 - Texture mapping

83.

ENABLING DOWN LINK RECEPTION OF SYSTEM AND CONTROL INFORMATION FROM INTRA-FREQUENCY NEIGHBORS WITHOUT GAPS IN THE EVOLVED-UTRA SYSTEMS

      
Application Number 17712958
Status Pending
Filing Date 2022-04-04
First Publication Date 2022-07-14
Owner Texas Instruments Incorporated (USA)
Inventor
  • Kangude, Shantanu
  • Bertrand, Pierre
  • Varadarajan, Badri N.

Abstract

Simplified communication between user equipment and a neighboring cell not the primary cell is achieved by restricting the transmission parameters, such as bandwidth, of the neighboring cell transmission and provision of a simplified secondary baseband processor in the user equipment.

IPC Classes  ?

  • H04W 36/04 - Reselecting a cell layer in multi-layered cells
  • H04L 5/00 - Arrangements affording multiple use of the transmission path
  • H04L 27/26 - Systems using multi-frequency codes
  • H04W 48/12 - Access restriction or access information delivery, e.g. discovery data delivery using downlink control channel

84.

Spatial Light Modulators

      
Application Number 17146363
Status Pending
Filing Date 2021-01-11
First Publication Date 2022-07-14
Owner Texas Instruments Incorporated (USA)
Inventor
  • Robb, Noah Alan
  • Jhaveri, Harsh Dinesh
  • Mathuria, Priyankar

Abstract

In a described example, a device includes: a semiconductor substrate; a memory array on the semiconductor substrate, the memory array comprising rows and columns of memory cells in a Manhattan pattern, the memory cells having a pitch in a direction along the columns; and an array of micromirrors in a diamond pattern over the memory cells, the micromirrors coupled to corresponding memory cells, the micromirrors having a diagonal pitch length in the direction along the columns that is between 1.8 times the pitch and 2.2 times the pitch.

IPC Classes  ?

  • H04N 9/31 - Projection devices for colour picture display
  • B81B 7/02 - Microstructural systems containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems (MEMS)
  • G11C 11/413 - Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
  • G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
  • G02B 26/08 - Optical devices or arrangements using movable or deformable optical elements for controlling the intensity, colour, phase, polarisation or direction of light, e.g. switching, gating or modulating for controlling the direction of light

85.

HIGH SPEED INTEGRATED CIRCUIT TESTING

      
Application Number 17321470
Status Pending
Filing Date 2021-05-16
First Publication Date 2022-07-14
Owner TEXAS INSTRUMENTS INCORPORATED (USA)
Inventor
  • Rajagopal, Devraj Matharampallil
  • Mishra, Nitesh

Abstract

An integrated circuit. The integrated circuit includes: (i) a clocked circuit operable in response to a clock; (ii) a clock providing circuit, coupled to clock the clocked circuit at a selectable frequency; (iii) a test circuit coupled to the clock providing circuit and the clocked circuit; and (iv) a pad configured to receive an external signal, wherein the selectable frequency is selected in response to the external signal.

IPC Classes  ?

  • G01R 31/317 - Testing of digital circuits
  • H01L 21/66 - Testing or measuring during manufacture or treatment
  • H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
  • G01R 31/3177 - Testing of logic operation, e.g. by logic analysers

86.

EXHAUST GAS MONITOR FOR PHOTORESIST ADHESION CONTROL

      
Application Number 17323767
Status Pending
Filing Date 2021-05-18
First Publication Date 2022-07-14
Owner Texas Instruments Incorporated (USA)
Inventor Plourde, Joseph Peter

Abstract

An exhaust stream monitoring system for a photolithography track of an IC fabrication process comprises a reaction chamber including a housing, an inflow port and an outflow port, the housing containing a thermal plate for heating a semiconductor process wafer for a predetermined amount of time. An influent pipe coupled to the inflow port supplies a photoresist adhesion promoter in a gaseous form to the reaction chamber. An effluent pipe coupled to the outflow port is operative to remove byproducts from the reaction chamber as an exhaust stream. At least one gas sensor manifold assembly is coupled to the effluent pipe for monitoring the exhaust stream from the reaction chamber to detect presence of one or more byproducts of a reaction between the photoresist adhesion promoter and the semiconductor process wafer.

IPC Classes  ?

  • G03F 7/20 - Exposure; Apparatus therefor
  • G01N 33/00 - Investigating or analysing materials by specific methods not covered by groups

87.

High Gain Detector Techniques for High Bandwidth Low Noise Phase-Locked Loops

      
Application Number 17461996
Status Pending
Filing Date 2021-08-31
First Publication Date 2022-07-14
Owner Texas Instruments Incorporated (USA)
Inventor
  • Perrott, Michael Henderson
  • Butler, Robert Karl

Abstract

In described examples, a phase locked loop (PLL) has a first phase detector cell (PD) that has a gain polarity. The first PD cell has a phase error output and inputs coupled to a reference frequency signal and a feedback signal. A second PD cell has an opposite gain polarity. The second PD cell has a phase error output and inputs coupled to the reference frequency signal and the feedback signal. A loop filter has a feedforward path and a (lossy) integrating path coupled to an output of the filter. The feedforward path has a third PD cell that has phase error output AC-coupled to the filter output. The integrating path includes an opamp that has an inverting input coupled to the first PD cell phase error output and a non-inverting input coupled to the second PD cell phase error output.

IPC Classes  ?

  • H03L 7/08 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop
  • H03L 7/107 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
  • H03L 7/04 - Automatic control of frequency or phase; Synchronisation using a frequency discriminator comprising a passive frequency-determining element wherein the frequency-determining element comprises distributed inductance and capacitance
  • H03L 7/187 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number using means for coarse tuning the voltage controlled oscillator of the loop
  • H03L 7/081 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop provided with an additional controlled phase shifter

88.

High Gain Detector Techniques for Low Bandwidth Low Noise Phase-Locked Loops

      
Application Number 17461997
Status Pending
Filing Date 2021-08-31
First Publication Date 2022-07-14
Owner Texas Instruments Incorporated (USA)
Inventor
  • Perrott, Michael Henderson
  • Chiu, Hon Kin

Abstract

In described examples, a feedback loop has phase detection (PD) circuitry that has a reference input to receive a reference frequency signal, a feedback input to receive a feedback signal, and phase difference outputs. A phase to digital converter (P2DC) includes a first phase to charge converter (PCC) that has a gain polarity and a first phase error output; a second PCC that has an opposite gain polarity and a second phase error output. A differential loop filter has an amplifier with an inverting input coupled to the first phase error output and a non-inverting input coupled to the second phase error output. An analog to digital converter (ADC) has an input coupled to an output of the differential loop filter. A feedback path is coupled to the output of the P2DC, with an output of the feedback path providing the feedback signal to the PD feedback input.

IPC Classes  ?

  • H03M 1/08 - Continuously compensating for, or preventing, undesired influence of physical parameters of noise
  • H03M 1/06 - Continuously compensating for, or preventing, undesired influence of physical parameters
  • H03M 1/18 - Automatic control for modifying the range of signals the converter can handle, e.g. gain ranging
  • G11C 11/4099 - Dummy cell treatment; Reference voltage generators
  • G11C 11/4093 - Input/output [I/O] data interface arrangements, e.g. data buffers

89.

SEMICONDUCTOR FORCE SENSORS

      
Application Number 17538782
Status Pending
Filing Date 2021-11-30
First Publication Date 2022-07-14
Owner TEXAS INSTRUMENTS INCORPORATED (USA)
Inventor
  • Fritz, Tobias Bernhard
  • Haroun, Baher S.
  • Cook, Benjamin Stassen
  • Koduri, Sreenivasan Kalyani
  • Szelong, Michael
  • Muellner, Ernst

Abstract

A force sensor including a semiconductor die, and a die pad coupled to the semiconductor die, the semiconductor die configured to detect a force in the die pad. In addition, the force sensor includes a mold compound covering the semiconductor die and having an outer perimeter, a first side, and a second side opposite the first side, the outer perimeter extending between the first side and the second side, the die pad exposed out of the mold compound along the first side. Further, the force sensor includes a mounting frame engaged with the die pad along the second side of the mold compound, the mounting frame including multiple mounting pads extended outward in multiple directions from the outer perimeter.

IPC Classes  ?

  • G01L 1/18 - Measuring force or stress, in general using properties of piezo-resistive materials, i.e. materials of which the ohmic resistance varies according to changes in magnitude or direction of force applied to the material
  • H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
  • H01L 23/495 - Lead-frames

90.

SEMICONDUCTOR PACKAGES INCLUDING INTERFACE MEMBERS FOR WELDING

      
Application Number 17538820
Status Pending
Filing Date 2021-11-30
First Publication Date 2022-07-14
Owner TEXAS INSTRUMENTS INCORPORATED (USA)
Inventor
  • Fritz, Tobias Bernhard
  • Zimnik, Marcus Rudolf

Abstract

An example semiconductor package includes a semiconductor die. In addition, the semiconductor package includes a mold compound having a first side, a second side opposite the first side, and an axis extending between the first side and the second side, the mold compound covering the semiconductor die. Further, the semiconductor package includes an interface member including a first portion and a second portion, the first portion is coupled to the second portion. The first portion is positioned along the first side, the second portion is positioned along the second side, and an engagement of a welding horn with the first portion is adapted to weld the second portion to a surface.

IPC Classes  ?

  • H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
  • H01L 23/14 - Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
  • G01L 1/18 - Measuring force or stress, in general using properties of piezo-resistive materials, i.e. materials of which the ohmic resistance varies according to changes in magnitude or direction of force applied to the material

91.

INSTRUCTION PACKING SCHEME FOR VLIW CPU ARCHITECTURE

      
Application Number US2022011525
Publication Number 2022/150532
Status In Force
Filing Date 2022-01-07
Publication Date 2022-07-14
Owner TEXAS INSTRUMENTS INCORPORATED (USA)
Inventor
  • Langadi, Saya Goud
  • Natarajan, Venkatesh
  • Tessarolo, Alexander

Abstract

A processor is provided and includes a core that is configured to perform a decode operation on a multi-instruction packet (500) comprising multiple instructions. The decode operation includes receiving the multi-instruction packet (500) that includes first and second instructions (502, 504). The first instruction (502) includes a primary portion (508) at a fixed first location and a secondary portion (510). The second instruction (504) includes a primary portion (512) at a fixed second location between the primary portion (508) of the first instruction (502) and the secondary portion (510) of the first instruction (502). An operational code portion of the primary portion (510, 512) of each of the first and second instructions (502, 504) is accessed and decoded. An instruction packet including the primary and secondary portions (508, 510) of the first instruction (502) is created, and a second instruction (504) packet including the primary portion (512) of the second instruction (504) is created. The first and second instructions packets are dispatched to respective first and second functional units.

IPC Classes  ?

  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline, look ahead

92.

METHODS AND SYSTEMS FOR ADAPTIVE EQUALIZATION WITH WIDE RANGE OF SIGNAL AMPLITUDES

      
Application Number US2022011891
Publication Number 2022/150733
Status In Force
Filing Date 2022-01-11
Publication Date 2022-07-14
Owner TEXAS INSTRUMENTS INCORPORATED (USA)
Inventor
  • Guo, Shita
  • Fan, Yanli
  • Erdogan, Mustafa, Ulvi
  • Wente, Douglas, Edward

Abstract

MMNN reference voltage levels. The method includes continuing to increase (528) an equalization level in predetermined steps to a next higher equalization level if the applied equalization level does not correspond to the over-equalization level and evaluating the distribution of the resulting hit counts for each increase to the next higher equalization level until the applied equalization level corresponds to the over-equalization level. The method includes decreasing (524) to the previously applied lower equalization level if the applied equalization level corresponds to the over-equalization level.

IPC Classes  ?

  • H04L 25/03 - Shaping networks in transmitter or receiver, e.g. adaptive shaping networks

93.

CALIBRATION SCHEME FOR A NON-LINEAR ADC

      
Application Number 17568972
Status Pending
Filing Date 2022-01-05
First Publication Date 2022-07-14
Owner TEXAS INSTRUMENTS INCORPORATED (USA)
Inventor
  • Varshney, Himanshu
  • Nagarajan, Viswanathan
  • Babu, Charls
  • Rajagopal, Narasimhan
  • Miglani, Eeshan
  • Pentakota, Visvesvaraya A.

Abstract

In described examples, an analog to digital converter (ADC), having an input operable to receive an analog signal and an output operable to output a digital representation of the analog signal, includes a voltage to delay (VD) block. The VD block is coupled to the input of the ADC and generates a delay signal responsive to a calibration signal. A backend ADC is coupled to the VD block, and receives the delay signal. The backend ADC having multiple stages including a first stage. A calibration engine is coupled to the multiple stages and the VD block. The calibration engine measures an error count of the first stage and stores a delay value of the first stage for which the error count is minimum.

IPC Classes  ?

94.

CALIBRATION OF PARAMETRIC ERROR OF DIGITAL-TO-TIME CONVERTERS

      
Application Number 17573323
Status Pending
Filing Date 2022-01-11
First Publication Date 2022-07-14
Owner TEXAS INSTRUMENTS INCORPORATED (USA)
Inventor Perrott, Michael Henderson

Abstract

In some examples, a circuit includes a clock divider and a calibration circuit coupled to the clock divider. The clock divider includes digital-to-time converter (DTC). The calibration circuit configured to determine a gain error and a parametric integrated nonlinearity (INL) error of the DTC, determine a gain adjustment value and a INL adjustment value to compensate for the gain error and the INL error, and modify operation of the DTC according to the gain adjustment value and the INL adjustment value to correct for the gain error and the INL error.

IPC Classes  ?

  • H03L 7/087 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
  • H03L 7/197 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division

95.

ADAPTIVE CAPACITVE FILTER CIRCUIT

      
Application Number 17573579
Status Pending
Filing Date 2022-01-11
First Publication Date 2022-07-14
Owner Texas Instruments Incorporated (USA)
Inventor Cohen, Isaac

Abstract

An adaptive capacitive filter circuit includes: a first terminal adapted to be coupled to a rectifier bridge output; a second terminal adapted to be coupled to a ground terminal; a first capacitor having a first electrode and a second electrode, the first electrode of the first capacitor coupled to the first terminal; a second capacitor having a first electrode and a second electrode, the second electrode of the second capacitor coupled to the second terminal; a first switch coupled between the second electrode of the first capacitor and the second terminal; a second switch coupled between the first terminal and the first electrode of the second capacitor; and a third switch coupled between the second electrode of the first capacitor and the first electrode of the second capacitor.

IPC Classes  ?

  • H03H 19/00 - Networks using time-varying elements, e.g. N-path filters
  • H02M 3/156 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
  • G01R 19/165 - Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
  • H03K 5/24 - Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
  • H03H 11/04 - Frequency selective two-port networks
  • H02M 1/15 - Arrangements for reducing ripples from dc input or output using active elements

96.

METHODS AND APPARATUS TO INCREASE AN OPERATIONAL RANGE OF A DUTY CYCLE OF A TWO-SWITCH FLYBACK CONVERTER

      
Application Number 17574355
Status Pending
Filing Date 2022-01-12
First Publication Date 2022-07-14
Owner Texas Instruments Incorporated (USA)
Inventor Cohen, Isaac

Abstract

An example apparatus includes: a first diode having a first diode terminal; a transformer having a transformer terminal; a second diode having a second diode terminal and a third diode terminal, the second diode terminal coupled to the transformer terminal; a first switch having a first current terminal and a second current terminal, the first current terminal coupled to the first diode terminal, the second current terminal coupled to the third diode terminal; a second switch having a third current terminal, the third current terminal coupled to the second diode terminal and the transformer terminal; a capacitor having a first capacitor terminal and a second capacitor terminal, the first capacitor terminal coupled to the second current terminal; and a third diode having a fourth diode terminal and a fifth diode terminal, the fourth diode terminal coupled to the first capacitor terminal, the fifth diode terminal coupled to the capacitor.

IPC Classes  ?

  • H02M 3/335 - Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
  • H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion
  • H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters

97.

VERTICAL TRENCH GATE FET WITH SPLIT GATE

      
Application Number 17147875
Status Pending
Filing Date 2021-01-13
First Publication Date 2022-07-14
Owner TEXAS INSTRUMENTS INCORPORATED (USA)
Inventor
  • Kim, Sunglyong
  • Sridhar, Seetharaman
  • Lee, Meng-Chia
  • Grebs, Thomas Eugene
  • Yang, Hong

Abstract

A semiconductor device includes first, second and third trenches formed in a semiconductor layer having a first conductivity type. Each trench includes a corresponding field plate and a corresponding gate over each field plate. A first body region having a second opposite conductivity type is between the first and second gates, and a second body region having the second conductivity type is located between the second and third gates. A first source region is located over the first body region and a second source region is located over the second body region, the first and second source regions having the first conductivity type. A first gate bus is conductively connected to the first gate and a second gate bus is conductively connected to the second gate, the first gate bus conductively isolated from the second gate bus.

IPC Classes  ?

  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 23/482 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of lead-in layers inseparably applied to the semiconductor body
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H01L 29/40 - Electrodes
  • H01L 21/765 - Making of isolation regions between components by field-effect
  • H01L 29/66 - Types of semiconductor device

98.

COMPACT AREA ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT

      
Application Number 17321466
Status Pending
Filing Date 2021-05-16
First Publication Date 2022-07-14
Owner TEXAS INSTRUMENTS INCORPORATED (USA)
Inventor
  • Disarro, James Paul
  • Appaswamy, Aravind Chennimalai
  • Chen, Zaichen

Abstract

An electrostatic discharge protection system with a node adapted to receive a signal and threshold detecting circuitry coupled to the node. The system includes an IGBT having an IGBT gate coupled to an output of the threshold detecting circuitry, a resistor coupled between an IGBT emitter of the IGBT and a low reference potential node, and a BJT having a BJT base coupled to the IGBT emitter.

IPC Classes  ?

  • H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
  • H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
  • H02H 9/04 - Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage

99.

ELECTROSTATIC DISCHARGE PROTECTION SYSTEM

      
Application Number 17321492
Status Pending
Filing Date 2021-05-16
First Publication Date 2022-07-14
Owner TEXAS INSTRUMENTS INCORPORATED (USA)
Inventor
  • Mysore Rajagopal, Krishna Praveen
  • Disarro, James Paul
  • Concannon, Ann Margaret
  • Sankaralingam, Rajkumar

Abstract

An ESD protection system including structure to operate an IC during nominal conditions, to protect the IC during an ESD event, and to allow the IC to operate during slow rising input node voltages that exceed nominal conditions.

IPC Classes  ?

  • H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
  • H02H 9/04 - Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage

100.

SCR HAVING SELECTIVE WELL CONTACTS

      
Application Number 17340255
Status Pending
Filing Date 2021-06-07
First Publication Date 2022-07-14
Owner Texas Instruments Incorporated (USA)
Inventor
  • Nagothu, Karmel Kranthi
  • Di Sarro, James Paul
  • Sankaralingam, Rajkumar

Abstract

A lateral semiconductor controlled rectifier (SCR) includes a pwell and an nwell A plurality of p+ contact regions connect to the pwell and are spaced apart from one another by a dielectric material along a width of the pwell. There are a plurality of n+ contact regions connect to the nwell and are spaced apart from one another by dielectric material along a width of the nwell.

IPC Classes  ?

  • H01L 29/74 - Thyristor-type devices, e.g. having four-zone regenerative action
  • H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
  • H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
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