Apparatuses, methods, and systems for receiving executable instructions from volatile memory are disclosed. In an example, a method can include storing executable instructions comprising a bootloader at a pre-defined memory address range in a non-volatile memory device of a solid state drive (SSD), copying the executable instructions from the pre-defined memory address range to a volatile memory device of the SSD in response to powering on the SSD, and transmitting the executable instructions from the volatile memory device to a host.
A method includes writing, to a first data structure, indices corresponding to address locations of a logical-to-physical (L2P) data structure that maps a plurality of logical block addresses (LBAs) associated with the L2P data structure, initiating performance of a media management operation involving one or more memory blocks in which data associated with the LBAs is written, and refraining from rewriting particular entries in the L2P table that correspond to LBAs whose index in the first data structure is a particular value during performance of the media management operation.
A method includes assigning a respective initial credit value to each LUN of a block stripe; performing an erase operation across the block stripe; reducing, in response to the erase operation, each respective initial credit value by a unit increment to provide a respective reduced credit value; refraining from programming to each LUN of the block stripe having a respective reduced credit value equal to zero; and programming to each LUN of the block stripe having a respective reduced credit value greater than zero.
An example memory apparatus includes clock circuitry. The clock circuitry can generate first and second clock signals based on a system clock signal, with the first and second clock signals being mutually out of phase. The apparatus can include detection circuitry to provide a detection result indicating whether an initial operation of a self-refresh exit operation coincides with a rising edge of the first clock signal or a rising edge of the second clock signal. The apparatus can include processing circuitry to provide an odd clock signal and an even clock signal based first and second clock signals and the detection result. The processing circuitry can provide the odd clock signal and the even clock signal out of phase or in phase with the first clock signal and the second clock signal depending on the detection result.
A control mechanism may be implemented in a back-end of a memory sub-system to refresh rows of a memory device. Rows of the memory device can be refreshed based on a quantity of times the rows have been updated in a duration of time. Rows of the memory device can also be updated based on a duration of time between receipt of the activation command for the row and a pre-charge command for the row. Row of the memory device clan further be updated utilizing a pair of counters that implement a ping pong mechanism to retain data between different consecutive durations of time.
A system for providing memory chip test pad access management to facilitate data security is disclosed. A host issues a command to access a non-volatile memory of a memory chip system via a test pad. A controller acknowledges the command by transmitting a response to the host to authenticate the host for access. The host then issues an authenticated command to modify a reserved byte of a protected memory partition of the non-volatile memory. The controller responds to the authenticated command and the reserved byte is modified. Firmware of the memory chip system monitors the modification of the reserved byte and notifies the memory chip system to activate a switch in an access control unit controlling access to the non-volatile memory. The switch is then activated, thereby closing a circuit to connect the test pad with the non-volatile memory. The host then access the non-volatile memory via the test pad.
Methods, systems, and devices for data handling during a reflow operation are described. The method may include a memory system receiving first signaling indicating that a reflow operation is to be performed on the memory system and determining whether an amount of data stored in a first set of memory cells within one or more memory devices of the memory system satisfy a threshold. The method may further include the memory system communicating an indication of whether the memory system is ready for the reflow operation based on the amount of data satisfying the threshold.
An access counter associated with a segment of a memory device is maintained. An access notification for a first line of the segment is received. An access type associated with the access notification is identified. A first value of the access counter is changed by a second value based on the access type. Based on the first value of the access counter, a memory management scheme is implemented.
Control logic in a memory device causes a pass voltage to be applied to a plurality of wordlines of a block of a memory array of the memory device, the block comprising a plurality of sub-blocks, and the pass voltage to boost a channel potential of each of the plurality of sub-blocks to a boost voltage. The control logic further selectively discharges the boost voltage from one or more of the plurality of sub-blocks according to a data pattern representing a sequence of bits to be programmed to respective memory cells of the plurality of sub-blocks. In addition, the control logic causes a single programming pulse to be applied to a selected wordline of the plurality of wordlines of the block to program the respective memory cells of the plurality of sub-blocks according to the data pattern.
G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
Methods, systems, and apparatuses include receiving a current free space value and a historic delta value. A delta value is calculated using the current free space value, a target free space value, and the historic delta value. A delta region is determined using the delta value. A new host rate is calculated using the determined delta region, the calculated delta value, and the historic delta value. The new host rate is sent to a host device causing the host device to change a current host rate to the new host rate.
Aspects of the present disclosure configure a system component, such as memory sub-system controller, to capture debugging information in memory sub-system operations in response to a critical event. The memory sub-system controller receives critical event trigger data and determines whether the critical event trigger data corresponds to a fatal condition. The memory sub-system controller selects an error handling mode from a plurality of error handling modes based on determining whether the critical event trigger data corresponds to the fatal condition. A first of the plurality of error handling modes corresponds to storing a first set of debugging information associated with a memory sub-system. A second of the plurality of error handling modes corresponds to storing a second set of debugging information associated with the memory sub-system without interrupting a host. The second set can be a subset of the first set of debugging information.
G06F 11/14 - Error detection or correction of the data by redundancy in operation, e.g. by using different operation sequences leading to the same result
A power loss protection failure is detected at a memory device. Based on detecting the power loss protection failure, a count of unused entries in a journal buffer is determined. A host command is received, and a number of entries needed to record the host command to the journal buffer is determined. In response to determining the count of unused entries in the journal buffer includes a least the number of entries needed to record the host command to the journal buffer, the host command is recorded in the journal buffer and the count of unused entries is reduced by the number of entries needed to record the host command to the journal buffer.
Aspects of the present disclosure configure a memory sub-system controller, to balance PEC across dies/planes of a memory sub-system. The memory sub-system controller determines that a first PEC of a first portion of a set of memory components is smaller than a second lifetime PEC of a second portion of the set of memory components. The memory sub-system controller performs a first memory operation on the first and second portions in response to a first request associated with the block stripe. The memory sub-system controller erases the block stripe comprising the first and second portions. The memory sub-system controller performs a second memory operation on the second portion of the set of memory components without performing the second memory operation on the first portion of the set of memory components in response to a second request associated with the block stripe.
Methods, systems, and devices for memory performance evaluation using address mapping information are described. A memory system may write a data file associated with a range of logical block addresses to a first set of blocks in a set of memory dies. The memory system may then determine, for a memory die of the set of memory dies that stores a portion of the data file, a quantity of read operations for reading the portion of the data file. The memory system may determine the quantity of read operations based on address mapping information that maps logical block addresses associated with the data file to physical addresses. After determining the quantity of read operations, the memory device may use the quantity of read operations to determine a performance metric associated with the data file and the first set of blocks.
Aspects of the present disclosure configure a memory sub-system controller to provide adaptive repair on short stripes. The memory controller groups a plurality of sets of blocks of a set of memory components into respective block stripes. The memory controller computes an average width across the block stripes, the average width representing an average quantity of blocks within each of the block stripes that is associated with a reliability grade that transgresses a threshold and determines that a first block stripe of the block stripes includes a lesser quantity of blocks, associated with reliability grades that transgress the threshold, than the average quantity of blocks. The memory controller, in response to determining that the first block stripe includes the fewer quantity of blocks than the average quantity of blocks, associates one or more blocks of a second block stripe of the block stripes with the first block stripe.
Data from a first page identified for folding is read. The first page corresponds to a page stripe that includes at least a second page. Parity data associated with the page stripe is read from the second page. Updated parity data for the page stripe is generated based on the data read from the first page and the parity data read from the second page. The updated parity data is written to a first location in the memory device determined based on a write cursor. The data read from the first page is folded to a second location in the memory device determined based on the write cursor.
A command manager can be configured to enforce respective command execution policies for each of multiple queues according to respective command fence instructions. In an example, the command manager can be configured to receive a first packet comprising a first fence instruction and a first command for a first queue and, responsive to the first fence instruction indicating fence participation, increment a fence counter and provide the first command to a command execution unit, such as a memory controller of a memory device. The command manager can receive a first response message from the command execution unit based on the first command and can decrement the fence counter. In an example, the command manager comprises a portion of an accelerator device that uses an unordered interconnect, such as a Compute Express Link (CXL) interconnect, to communicate with a host device.
A single-instruction/multiple-data (SIMD) processor uses a function unit that can perform a single operation on multiple data elements. The function unit operates at a higher speed than the rest of the processor, allowing each data element in the SIMD operand to be processed sequentially, using fewer compute resources and avoiding any processing throughput loss. The SIMD processor includes an input register that receives N data elements at the beginning of a clock cycle in a slow clock domain. Each data element of the operand is selected and passed to the function unit on consecutive clock cycles in a fast clock domain. The N results are generated on N successive clock cycles in the fast clock domain and combined to provide multiple results on a single clock cycle in the slow clock domain.
G06F 9/38 - Concurrent instruction execution, e.g. pipeline, look ahead
G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
G06F 15/78 - Architectures of general purpose stored program computers comprising a single central processing unit
G06F 15/80 - Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
G06F 7/72 - Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations using residue arithmetic
G06F 1/04 - Generating or distributing clock signals or signals derived directly therefrom
19.
MULTI-PARTITION FILE SYSTEM FOR STORING VIDEO STREAMS IN MANAGED NON-VOLATILE MEMORY DEVICE
Technologies for storing streaming data include, in some embodiments, in response to determining that the chunk size satisfies a chunk size threshold and the streaming data is sequential data of a size that satisfies a threshold sequential data size, writing the sequential data to a first file system partition of a file system comprising a plurality of file system partitions, and in response to determining that the chunk size does not satisfy the chunk size threshold or the chunk size satisfies the chunk size threshold and the streaming data is the first type of metadata, writing the streaming data to a second file system partition of the plurality of file system partitions.
G06F 11/14 - Error detection or correction of the data by redundancy in operation, e.g. by using different operation sequences leading to the same result
Methods, systems, and devices for performance monitoring for a memory system are described. A memory system may use a set of counters to determine state information for the memory system. The memory system may also use a set of timers to determine latency information for the memory system. In response to a request for performance information, the memory system may transmit state information, latency information, or both to a host system.
A system component is provided, such as a memory sub-system controller, to track a quantity of translational units stored for each of a plurality of namespaces on an individual namespace basis. To format a given one of the plurality of namespaces, the individually tracked quantity of translational units can be deducted from a global quantity tracked for each respective block of the memory sub-system.
Disclosed in some examples are methods, systems, computing devices, and machine-readable mediums in which the system maintains a list of resources available for each rollback session. In some examples, state data is kept that indicates available memory. If a write occurs for a particular session and the amount of available memory for a session has been used, a flag is set in metadata for the memory location and the write is not mirrored. In this manner, the technical problem of one undo logging session using too much memory and preventing other undo logging sessions from properly functioning is solved by the technical solution of setting resource limits for each undo logging session.
Control a coarse grained reconfigurable array during execution of an assembly language program identifying data flows through memory locations represented by memory variables. For example, a lowering program can be configured to receive the assembly language program, a hardware profile of the coarse grained reconfigurable array, and an instruction execution schedule to generate a configuration usable to control the coarse grained reconfigurable array. The lowering program can identify tile memories used to implement the memory locations represented by the memory variables in the assembly language program, and trace the data flows specified in the assembly language program. Using timing of instruction execution identified in the schedule, the lowering program can determine timing and controls for the dispatch interface, memory interfaces, and internal connections within tiles of the coarse grained reconfigurable array during execution of the assembly language program.
An assembly language program for a coarse grained reconfiguration array (CGRA), having dispatch interface information indicating operations to be performed via a dispatch interface of the CGRA to receive an input, memory interface information indicating operations to be performed via one or more memory interfaces of the CGRA, tile memory information indicating memory variables referring to memory locations to be implemented in tile memories of the CGRA, a flow description specifying one or more synchronous data flows, through the memory locations referenced via the memory variables in the tile memory information, to produce a result from the input using the CGRA.
Schedule instructions of a program for execution on a coarse grained reconfigurable array having a plurality of tiles operable in parallel. The program identifies data flows through memory locations represented by memory variables and identifies instructions configured to transform data in the data flows. Based on a hardware profile identifying features of the coarse grained reconfigurable array, a scheduler is configured to generate a memory map. The memory map identifies, for each respective memory variable in the program, one of the tiles that contains a memory location represented by the respective memory variable. Based on the memory map reducing possible choices for a brute force search, the scheduler assigns the instructions to the tiles for execution, and determines timing of execution of the instructions in the tiles.
An artificial neural network is trained via reinforcement learning to receive first data representative of execution dependency conditions of instructions of a program, second data representative of a schedule of a first portion of the instructions of the program for execution in a device having a plurality of circuits units operable in parallel, and third data identifying a next instruction selected from a second portion of the instructions of the program remaining to be scheduled for execution in the device. The artificial neural network selects a placement of the next instruction in one of the circuit units from a plurality of possible placements of the next instruction in the device. Performance of placements of instructions being tested in search for a valid schedule for running the program in the device can be measured to generate samples to train the artificial neural network via reinforcement learning.
An electronic device can be configured to enable a host to indirectly control testing associated with the electronic device. The interface between the host and the electronic device can be abstract, such that the host does not have direct control over the electronic device. Examples of the electronic device include a memory device and a power management integrated circuit. The electronic device can allow the host to discover a quantity of tests supported by the electronic device and corresponding test descriptors. The electronic device can interact with the host to configure tests and/or reporting of test results.
Methods, systems, and devices for techniques for efficiently handling misaligned sequential reads are described. A memory system may include a memory device that includes multiple memory dies. The memory system may receive a first read command and a second read command from a host system. The first read command may be associated with a first set of physical addresses and the second read command may be associated with a second set of physical addresses. The memory system may determine, based on the first set of physical addresses and the second set of physical addresses, that the first read command and the second read command are for a same memory die of the multiple memory dies. The memory system may then transmit to the memory die a read request that indicates the first set of physical addresses and the second set of physical addresses.
Methods, systems, and devices for a sorted change log for physical page table compression are described. A mapping between a logical address and a physical address may be stored in a change log buffer. The mapping may be stored at a location of the change log buffer based on the logical address of the mapping relative to logical addresses of other mappings stored in the change log buffer. Based on storing mappings in the change log buffer based on logical addresses of the mappings, a set of mappings in the change log may include a set of sequentially-indexed logical addresses. A compressed entry for a logical-to-physical table may be generated based on the set of mappings.
Methods, systems, and devices for compressing firmware data are described. A memory system may access firmware data associated with the memory system that includes bank data. The memory system may determine whether the bank data in the firmware data is compressed and, in cases that the bank data is compressed, the memory system may decompress the bank data prior to storing the bank data at a controller of the memory system. In some examples, a bank header in the firmware data may include information for the memory system to decompress the bank data. For example, the bank header may indicate the size of the compressed bank data associated with each bank. Additionally, the memory system may read the compressed bank data according to the indicated size and store the bank data at the controller or at a memory device of the memory system.
Methods, systems, and devices for error information storage for boot-up procedures are described. A memory system may detect an error associated with performing the boot-up procedure of the memory system and may store error information associated with the detected error in a persistent register at the memory system. In some cases, the memory system may additionally store the error information in a cache at the memory system. After storing the error information, the memory system may reset and, after resetting, may transfer the error information from the persistent register to a non-volatile memory device at the memory system. In cases that the memory system stores error information in the cache prior to the reset, the memory system may additionally transfer the error information from the cache to the non-volatile memory device.
Methods, systems, and devices for low-latency processing for unmap commands are described. A plurality of commands including one or more unmap commands and one or more other types of commands may be received from a device. The one or more unmap commands may be stored in a queue used for unmap commands and the other commands may be stored in another queue. Ready-to-transfer messages for the one or more unmap commands stored in the queue may be transmitted to the device. In response to the ready-to-transfer messages, one or more messages including data for executing the one or more unmap commands may be received and stored in a portion of a buffer used for unmap commands.
A controller can be configured to enable a host to control media testing on a memory device. The interface between the host and the memory can be abstract, such that the host does not have direct control over the memory. Instead, the controller can provide translation between a host protocol, such as compute express link (CXL), and a memory protocol, such as a protocol to control a dual data rate (DDR) interface. The controller can enable media test capability discovery, configuration, and/or control for the host. The controller can enable media test result reporting from the memory to the host.
Operations include monitoring a logical level of a first pin of the plurality of pins while a data burst is active, wherein the first pin is associated with at least one of a read enable signal or a data strobe signal, determining whether a period of time during which the logical level of the first pin is held at a first logical level satisfies a threshold condition, in response to determining that the period of time satisfies the threshold condition, continuing to monitor the logical level of the first pin, determining whether the logical level of the first pin changed from the first logical level to a second logical level, and in response to determining that the logical level of the first pin changed from the first logical to the second logical level, causing warmup cycles to be performed.
A memory device includes a memory array and processing logic, operatively coupled with the memory array, to perform operations including causing a data burst to be initiated by toggling a logical level of a control pin from a first level corresponding to a data burst inactive mode to a second level corresponding to a data burst active mode, wherein the data burst corresponds to a data transfer across an interface bus, causing the data burst to be suspended by toggling the logical level of the control pin from the second level to a third level corresponding to a data burst suspend mode, and causing the data burst to be resumed by toggling the logical level of the control pin from the third level to the second level.
Systems, apparatuses, and methods related to memory access statistics monitoring are described. A host is configured to map pages of memory for applications to a number of memory devices coupled thereto. A first memory device comprises a monitoring component configured to monitor access statistics of pages of memory mapped to the first memory device. A second memory device does not include a monitoring component capable of monitoring access statistics of pages of memory mapped thereto. The host is configured to map a portion of pages of memory for an application to the first memory device in order to obtain access statistics corresponding to the portion of pages of memory upon execution of the application despite there being space available on the second memory device and adjust mappings of the pages of memory for the application based on the obtained access statistics corresponding to the portion of pages.
Systems, apparatuses, and methods related to data stripe protection are described. An error management component can process multiple read/write/recovery requests concurrently. When read/write requests are to be processed on respective strips of a stripe, the error management component can process (e.g., concurrently) the read/write requests to determine a quantity of errors within each one of the strips and the determined quantity can be used to further determine whether to access other memory portions to correct the determined quantity.
G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
G06F 12/0866 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
38.
SELECTABLE CACHE WRITING POLICIES FOR CACHE MANAGEMENT
Systems, apparatuses, and methods related to selectable cache writing policies for cache management are described. A cache writing policy to manage a cache can be selected among cache writing policies based on a number of tracked criteria, which can provide cache management with a particular cache writing policy that will likely incur less latency than the other policies.
Methods, systems, and devices for associative computing for error correction are described. A device may receive first data representative of a first codeword of a size for error correction. The device may identify a set of content-addressable memory cells that stores data representative of a set of codewords each of which is the size of the first codeword. The device may identify second data representative of the first codeword in the set of content-addressable memory cells. Based on identifying the second data, the device may transmit an indication of a valid codeword that is mapped to the second data.
Methods, systems, and devices for training procedure change determination to detect an attack are described. A host device may perform one or more training procedures to train aspects of a memory device (e.g., a dynamic random-access memory (DRAM) component). A training procedure may depend on a current (e.g., present, within a threshold duration) metric associated with the memory device, such as a current channel metric for a channel between the memory device and the host device. The host device, memory device, or another device, may store a set of reference values associated with a training procedure and may compare a result of a training procedure to a reference value of the set to determine whether the training procedure has changed. If the training procedure or a related value has changed, the memory device may disable one or more features of the memory device to protect against a potential attack.
G06F 21/71 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
G06F 21/79 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data in semiconductor storage media, e.g. directly-addressable memories
G06F 21/55 - Detecting local intrusion or implementing counter-measures
Methods, systems, and devices for error detection signaling are described. In some examples, a memory device may include circuitry to detect one or more error conditions. As the memory device is operated, it may store or output a value (e.g., a high value, a "1") indicating the absence of an error condition. Upon the occurrence of an error condition, the memory device may either store or output a value (e.g., a low value, a "0"), which may allow for the error to be corrected or mitigated. Because storing or driving the value signifying the error condition may require a driver of the memory device to be coupled with a power supply, storing or outputting the value signifying an absence of an error condition (e.g., unless a normal or valid condition is detected) may mitigate errors that would otherwise render a safety mechanism of the memory device ineffective.
Systems and methods for providing memory' access commands to memory circuitry using a multi-clock cycle memory command protocol is described. A. command decoder (or controller) of the memory circuitry may efficiently receive a. memory access request (or a memory command) provided using multiple clock cycles. For example, the command decoder may receive a. header and a first portion of address bits of target memory cells of the memory command in a first clock cycle and a second portion of the address bits of the target memory cells in a subsequent clock cycle. Accordingly, the memory circuitry may receive a memory command provided over multiple clock cycles with one header. Such memory commands may efficiently include a high number of address bits received using input circuitry of the memory circuitry.
G11C 8/12 - Group selection circuits, e.g. for memory block selection, chip selection, array selection
G11C 8/18 - Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
G06F 3/06 - Digital input from, or digital output to, record carriers
43.
MULTIPLE DIFFERENTIAL WRITE CLOCK SIGNALS WITH DIFFERENT PHASES
Apparatuses and techniques for operating devices with multiple differential write clock signals having different phases are described. For example, a memory controller (114) (e.g., of a host device) can provide two differential write clock signals (122-1 and 122-2) to a memory device (108) over an interconnect (106). The two differential write clock signals (122-1 and 122-2) may have a phase offset of approximately ninety degrees. Instead of generating its own phase-delayed write clock signals using a component (e.g., a clock divider circuit) that can enter the metastable state, the memory device (108) can use the multiple differential write clocks signals (122-1 and 122-2) provided by the memory controller (114) to process memory requests.
A microelectronic device comprises stack structure comprising an alternating sequence of conductive material and insulative material arranged in tiers, and having blocks separated by dielectric slot structures. Each of the blocks comprises a stadium structure, a filled trench overlying the stadium structure, support structures extending through the filled trench and tiers of the stack structure, and dielectric liner structures covering sidewalls of the support structures. The stadium structure comprises staircase structures each having steps comprising edges of the tiers of the stack structure. The filled trench comprises a dielectric material interposed between at least two additional dielectric materials. The dielectric liner structures comprise first protrusions at vertical positions of the dielectric material, and second protrusions at vertical positions of the conductive material of the tiers of the stack structure. The second protrusions have greater horizontal dimensions than the first protrusions. Memory devices, electronic systems, and methods are also described.
H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 41/50 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
45.
APPARATUSES INCLUDING OUTPUT DRIVERS AND METHODS FOR PROVIDING OUTPUT DATA SIGNALS
Apparatuses including output drivers and methods for providing output data signals are described. An example apparatus includes a high logic level driver, a low logic level driver, and an intermediate logic level driver. The high logic level driver is provided a first voltage and provides a high logic level voltage to a data terminal when activated. The low logic level driver is provided a second voltage and provides a low logic level voltage to the data terminal when activated. The intermediate logic level driver is provided a third voltage having a magnitude that is between the first and second voltages, and provides an intermediate logic level voltage to the data terminal when activated. Each of the high, low, and intermediate logic level drivers are configured to be respectively activated based on one or more of a plurality of control signals.
G11C 11/4096 - Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
G11C 11/4074 - Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
46.
MEMORY DEVICE WITH DATA SCRUBBING CAPABILITY AND METHODS
A method to perform data scrub operations by operating a memory device, the memory device comprising a main memory, an internal Error Correction Code (ECC) engine and a scrub memory. The method comprising: receiving a read command; accessing, based on the receiving the read command, a location in the main memory to read data at the location; error correcting data read during the accessing; and storing at the scrub memory information of the location based at least in part on the correcting the data meeting or exceeding an ECC threshold.
G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
G11C 11/22 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
47.
MEMORY ARRAYS COMPRISING STRINGS OF MEMORY CELLS AND METHODS USED IN FORMING A MEMORY ARRAY COMPRISING STRINGS OF MEMORY CELLS
A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers directly above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The channel-material strings directly electrically couple with conductor material of the conductor tier. A through-array-via (TAV) region comprises TAVs that individually extend through the insulative tiers and the conductive tiers into the conductor tier. Individual of the TAVs comprise an upper portion directly above and joined with a lower portion. The individual TAVs comprise at least one external jog surface in a vertical cross-section where the upper and lower portions join. The lower portion is wider in the vertical cross-section than the upper portion where the upper and lower portions join. Other embodiments, including method, are disclosed.
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
Methods, systems, and devices for modification of a command timing pattern are described. A host device may transmit (e.g., issue), to a memory device, a quantity of deselect commands between activation or data access commands to satisfy configured timing constraints. Each deselect command may indicate a polarity (e.g., a high voltage or a low voltage) for a command and address (CA) pin at the memory device. In some examples, the quantity of deselect commands may include one or more sequences of deselect commands (e.g., low-high-high-high). The host device may truncate a sequence of deselect commands, for example to satisfy timing constraints without transmitting additional unnecessary commands. By dynamically configuring the quantity of deselect commands, the host device may improve latency and overall efficiency of system operations without violating the configured timing constraints.
Systems, apparatus, and methods related to parallel processing in a spiking neural network are described. In some examples, parallel processors may compute a time delta vector based on post- synaptic timestamp vector and a current timestamp. The processors may calculate a long-term depression (LTD) value based on the time delta vector and load synaptic weights from memory based on at least the time delta vector. The processors may compute a second time delta vector using various inputs, such as a pre-synaptic timestamp vector, the current timestamp, and pre-synaptic timestamps. The processors may calculate a long-term potentiation (LTP) value based on the second time delta vector and adjust a current synaptic weight vector based on the LTD value and LTP value to generate an updated synaptic weight vector. The updated synaptic weight vector may be written to volatile memory (e.g., DRAM) or non-volatile (e.g., NAND Flash).
Methods, systems, and devices for deck selection layouts in a memory device are described. In some implementations, a tile of a memory array may be associated with a level above a substrate, and may include a set of memory cells, a set of digit lines, and a set of word lines. Selection transistors associated with a tile of memory cells may be operable for coupling digit lines of the tile with circuitry outside the tile, and may be activated by various configurations of one or more access lines, where the various configurations may be implemented to trade off or otherwise support design and performance characteristics such as power consumption, layout complexity, operational complexity, and other characteristics. Such techniques may be implemented for other aspects of tile operations, including memory cell shunting or equalization, tile selection using transistors of a different level, or signal development, or various combinations thereof.
A memory device may enforce compliance with a refresh command requirement in some examples. When a controller fails to comply with the refresh command requirement, the memory device may prevent the controller from accessing a memory array. The controller may regain access by providing one or more commands, such as a refresh command. In some examples, the memory may enforce compliance with a refresh command requirement responsive to a value written to the mode register. In some examples, the memory may enforce compliance with the refresh command requirement after an initialization operation has completed.
Methods, systems, and devices for communications are described. A connection may be established between a remote device that includes an imaging device and a device. Based on establishing the connection, first visual data associated with the imaging device may be received at the device. A second connection between the device and a communication device may be established, where communications between the device and the communication device may be supported via an application running at the device. Based on establishing the second connection, the visual data may be transmitted from the mobile device to the communication device via the application.
H04W 4/60 - Subscription-based services using application servers or record carriers, e.g. SIM application toolkits
H04W 4/40 - Services specially adapted for particular environments, situations or purposes for vehicles, e.g. vehicle-to-pedestrians [V2P]
B60R 11/04 - Mounting of cameras operative during drive; Arrangement of controls thereof relative to the vehicle
H04N 23/00 - Cameras or camera modules comprising electronic image sensors; Control thereof
H04N 21/4788 - Supplemental services, e.g. displaying phone caller identification or shopping application communicating with other users, e.g. chatting
Disclosed herein is an apparatus that includes a plurality of memory banks and a refresh controller configured to perform a refresh operation on one or more of the plurality of memory banks having a first state without performing the refresh operation on one or more of the plurality of memory banks having a second state responsive to a first refresh command, and perform the refresh operation on a selected one of the plurality of memory banks responsive to a second refresh command. The refresh controller is configured to bring the selected one of the plurality of memory banks into the second state when the refresh operation is performed responsive to the second refresh command.
Memory circuitry comprising strings of memory cells comprising laterally-spaced memory blocks individually comprise a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers in a memory-array region. The insulative tiers and the conductive tiers of the laterally-spaced memory blocks extend from the memory-array region into a stair-step region. Individual stairs in the stairstep region comprise one of the conductive tiers and a riser. Conductive vias are individually directly against conductive material that is in the one conductive tier in one of the individual stairs. Individual of the conductive vias where directly against the conductive material are horizontally-longitudinally-elongated at an angle of 0° to 60° horizontally from the riser of the one individual stair. Other embodiments, including method, are disclosed.
H01L 27/11556 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 27/11524 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the memory core region with cell select transistors, e.g. NAND
H01L 27/1157 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the memory core region with cell select transistors, e.g. NAND
H01L 27/11519 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the top-view layout
H01L 27/11565 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the top-view layout
55.
FINFETS HAVING VARIOUS DIFFERENT THICKNESSES OF GATE OXIDES AND RELATED APPARATUS, METHODS, AND COMPUTING SYSTEMS
Fin field effect transistors (FinFETs) having various different thicknesses of gate oxides and related apparatuses, methods, and computing systems are disclosed. An apparatus includes first FinFETs, second FinFETs, and third FinFETs. The first FinFETs include a first gate oxide material, a second gate oxide material, and a third gate oxide material. The second FinFETs include the second gate oxide material and the third gate oxide material. The third FinFETs include the third gate oxide material. A method includes forming the first gate oxide material on first fins, second fins, and third fins; removing the first gate oxide material from the second fins and the third fins; forming a second gate oxide material over the first fins, the second fins, and the third fins; and removing the second gate oxide material from the third fins.
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
A semiconductor device assembly is provided. The assembly includes a first semiconductor device including a plurality of electrical contacts on an upper surface thereof; a monolithic silicon structure having a lower surface in contact with the upper surface of the first semiconductor device, the monolithic silicon structure including a cavity extending from the lower surface into a body of the monolithic silicon structure; and a second semiconductor device disposed in the cavity and including a plurality of interconnects, each operatively coupled to a corresponding one of the plurality of electrical contacts.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 23/367 - Cooling facilitated by shape of device
H01L 23/373 - Cooling facilitated by selection of materials for the device
57.
SEMICONDUCTOR DEVICE ASSEMBLIES INCLUDING MONOLITHIC SILICON STRUCTURES FOR THERMAL DISSIPATION AND METHODS OF MAKING THE SAME
A semiconductor device assembly includes a first semiconductor device including a plurality of electrical contacts on an upper surface thereof, a monolithic silicon structure having a lower surface in contact with the upper surface and a cavity extending from the lower surface into a body of the monolithic silicon structure; a second semiconductor device disposed in the cavity, the second semiconductor device including a first plurality of interconnects, each operatively coupled to a corresponding one of the plurality of electrical contacts, and a second plurality of interconnects on an upper surface of the second semiconductor device, each coupled to a corresponding TSV of a plurality of TSVs extending from the cavity to a top surface of the monolithic silicon structure; and a third semiconductor device disposed over the monolithic silicon structure and including a third plurality of interconnects, each operatively coupled to a corresponding one of the plurality of TSVs.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
Some embodiments include apparatuses and methods forming the apparatuses. One of the apparatuses includes a first transistor including a first channel region, and a charge storage structure separated from the first channel region; a second transistor including a second channel region formed over the charge storage structure; and a data line formed over and contacting the first channel region and the second channel region, the data line including a portion adjacent the first channel region and separated from the first channel region by a dielectric material.
Methods, systems, and devices for techniques for indicating row activation are described. A memory device may receive an indication associated with an activation command, which may enable the memory device to begin some aspects of an activation operation before receiving the associated activation command. The indication may include a location of a next row to access as part of the activation command. The indication may be included in a previous activation command or in a precharge command. The memory device may begin activation operations for the next row before the precharge operation of the current row is complete. The memory device may receive the activation command for the next row after receiving the indication, and may complete the activation operations upon receiving the activation command.
Apparatuses and methods for controlling hydrogen diffusion to a substrate in manufacturing memory devices are described. An example apparatus includes: a substrate; an active region in the substrate; at least one first conductive material above the active region; a hydrogen source layer on the at least one first conductive material, the hydrogen source layer including hydrogen atoms and/or molecules and the hydrogen source layer configured to release the hydrogen atoms and/or molecules; a hydrogen diffusion barrier layer on the conductive layer; and at least one second conductive material above the hydrogen diffusion barrier layer, the at least one second conductive material coupled to the at least one first conductive material. The at least one first conductive material has hydrogen diffusion properties. The hydrogen diffusion barrier layer has hydrogen barrier properties.
Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a memory cell including a first transistor, a second transistor, and a dielectric structure formed in a trench. The first transistor includes a first channel region, and a charge storage structure separated from the first channel region. The second transistor includes a second channel region formed over the charge storage structure. The dielectric structure includes a first dielectric portion formed on a first sidewall of the trench, and a second dielectric portion formed on a second sidewall of the trench. The charge storage structure is between and adjacent the first and second dielectric portions.
Some embodiments include apparatuses and methods forming the apparatuses. One of the apparatuses includes a first memory cell including a first transistor including a first channel region and a first charge storage structure, and a second transistor including a second channel region formed over the charge storage structure; a second memory cell adjacent the first memory cell, the second memory cell including a third transistor including a third channel region and a second charge storage structure, and a fourth transistor including a fourth channel region formed over the second charge storage structure; a first access line adjacent a side of the first memory cell; a second access line adjacent a side of the second memory cell; a first dielectric material adjacent the first channel region; a second dielectric material adjacent the third channel region; and a conductive structure between the first and second dielectric materials and adjacent the first and second dielectric materials.
The present disclosure relates to a memory device comprising an array including a plurality of memory cells and an operating unit, the operating unit comprising an encoding unit configured to store user data in a plurality of memory cells of the memory array and to store parity data associated with the user data in a number of parity cells of the memory array, the operating unit further comprising a decoding unit in turn comprising a syndrome generating unit configured to calculate an ECC syndrome from the stored user data and parity data, wherein the syndrome generating unit comprises a plurality of circuit portions, each circuit portion being configured to calculate a respective syndrome portion of the ECC syndrome. The operating unit is configured to activate a first circuit portion of the syndrome generating unit for calculating a first syndrome portion, and, based on the calculated first syndrome portion, decide whether to activate or not to activate a second circuit portion for the calculation of a second syndrome portion. Related methods and systems are also herein disclosed.
Memory devices (100) may perform read operations and write operations with different bit error correction rates to satisfy a bit error correction rate. However, improving the bit error correction rate of the memory device (100) using a single type of read command and/or write commands may result in longer read and write commands. Moreover, using longer read and write commands may result in undesirable higher memory power consumption and may reduce memory throughput. Accordingly, memory operations are described that may use combination of commands with increased bit error correction capability and reduced bit error correction capability. For example, the read operations (500) may use multiple (e.g., at least two) sets or groupings of read commands and the write operations (520) may use multiple (e.g., at least two) sets or groupings of write commands.
A plurality of temperature values of the memory device is received. A temperature value of the plurality of temperature values that satisfies a thermal throttling threshold of a plurality of thermal throttling thresholds is determined, wherein each thermal throttling threshold of the plurality of thermal throttling thresholds triggers a corresponding thermal throttling state of the memory device. In response to determining that the temperature value satisfies the respective thermal throttling threshold, a thermal throttling operation associated with the corresponding thermal throttling state is performed.
Some memory dies in a stack can be connected externally to the stack and other memory dies in the stack can be connected internally to the stack. The memory dies that are connected externally can act as interface dies for other memory dies that are connected internally thereto. The external connections can be used for transmitting signals indicative of data to and/or from the memory dies while the memory dies in the stack can be connected by a cascading connection for transmission of other signals such as command, address, power, ground, etc.
A microelectronic device comprises a first microelectronic device structure and a second microelectronic device structure attached to the first microelectronic device structure. The first microelectronic device structure comprises memory arrays comprising memory cells comprising access devices and storage node devices, digit lines coupled to the access devices and extending in a first direction to a digit line exit region, and word lines coupled to the access devices and extending in a second direction to a word line exit region. The second microelectronic device structure comprises control logic devices over and in electrical communication with the memory cells. The microelectronic device further comprises contact structures individually in contact with the digit lines in the digit line exit region and in electrical communication with at least some of the control logic devices, at least one of the contact structures comprising a first cross-sectional area at an interface of the first microelectronic device structure and the second microelectronic device structure, and a second cross-sectional area at an interface of one of digit lines, the second cross-sectional area smaller than the first cross-sectional area. Related microelectronic devices, memory devices, electronic systems, and methods are also described.
A method of forming a microelectronic device comprises forming a first microelectronic device structure comprising a preliminary stack structure comprising sacrificial structures and insulative structures vertically alternating with the sacrificial structures. A second microelectronic device structure comprising control logic circuitry is formed. The first microelectronic device structure is attached to the second microelectronic device structure to form an assembly. After forming the assembly, the sacrificial structures are at least partially replaced with conductive structures to form a stack structure. Contact structures are formed to extend through the stack structure. One or more of the contact structures are coupled to the control logic circuitry. Conductive line structures are formed over the stack structure. One or more of the conductive line structures are coupled to the one or more of the contact structures. Microelectronic devices, memory devices, and electronic systems are also described.
H01L 27/11556 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 27/11548 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the boundary region between the core and peripheral circuit regions
H01L 27/11575 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the boundary region between the core and peripheral circuit regions
H01L 27/11526 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the peripheral circuit region
H01L 27/11573 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the peripheral circuit region
Methods, systems, and devices for cross point array architecture for multiple decks are described. A memory array may include multiple decks, such as six or eight decks. The memory array may also include sockets for coupling access lines with associated decoders. The sockets may be included in sub-blocks of the array. A sub-block may be configured to include sockets for multiple access lines. A socket may intersect an access line in the middle of the access line, or at an end of the access line. Sub-blocks containing sockets for an access line may be separated by a period based on the access line.
Examples described herein utilize multi-layer neural networks, such as multi-layer recurrent neural networks, to estimate a bit error rate (BER) of encoded data based on a retrieved version of encoded data (e.g., data encoded using one or more encoding techniques) from a memory. The neural networks may have nonlinear mapping and distributed processing capabilities which may be advantageous to estimate a BER of encoded data, e.g., to facilitate decoding of the encoded data. In this manner, neural networks described herein may be used to improve or facilitate aspects of decoding at ECC decoders, e.g., by comparing an estimated BER to a threshold (e.g., a threshold BER level) prior to decoding of the encoded data. For example, an additional NN activation indication may be provided, e.g., to indicate that the encoded data may be decoded or to indicate that error present in the encoded data is to be reduced.
H03M 13/01 - Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
H03M 13/15 - Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
G06N 3/04 - Architecture, e.g. interconnection topology
Systems, methods, and apparatus related to selecting memory cells in a memory array of a memory device. In one approach, bias circuitry generates a voltage on an access line used to select a memory cell for programming. During programming, a controller connects a boost capacitor to the access line by controlling a switch. Connecting the boost capacitor causes an increase in the rate of discharge of the access line (e.g., discharge of a word line to a negative voltage). After programming, the controller disconnects the boost capacitor from the access line, and the boost capacitor is pre-charged in preparation for a next programming operation (e.g., on the same or a different memory cell).
G11C 7/12 - Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
G11C 7/22 - Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
G06F 3/06 - Digital input from, or digital output to, record carriers
72.
MANAGING A MEMORY SUB-SYSTEM BASED ON COMPOSITE TEMPERATURE
A plurality of device temperature values that are each indicative of a temperature at a respective device of a plurality of devices of a system is identified. A respective composite temperature threshold ratio is determined for each device of the plurality of devices. A respective normalization value based on the respective composite temperature threshold ratio and the respective device temperature value is determined for each device of the plurality of devices. A largest normalization value of the plurality of devices is determined. A composite temperature of the system based on the largest normalization value of the plurality of devices is set.
G11C 7/04 - Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
G06F 3/06 - Digital input from, or digital output to, record carriers
73.
MEMORY CONTROLLER FOR MANAGING DATA AND ERROR INFORMATION
A memory controller can include a front end portion configured to interface with a host, a central controller portion configured to manage data, a back end portion configured to interface with memory devices. The memory controller can manage memory devices according to different protocols. For a first protocol, the memory device performs error correction operations and for a second protocol, the memory controller performs error correction operations. For the first protocol, error correction information, error detection information, and/or metadata is exchanged between the memory devices and the memory controller via data pins. For the second protocol, error correction information, error detection information, and/or metadata is exchanged between the memory devices and the memory controller via data mask inversion pins. The second protocol can have some features disabled that are enabled according to the first protocol, such as low-power features.
Embodiments of the disclosure are drawn to apparatuses and methods for bad row mode. The memory may prevent proper access operations (e.g., read operations) from being performed on a selected bad row of the memory as part of a bad row mode. For example, the memory may store a bad row address and when an access address matches the bad row address, may suppress one or more signals, change data read from the address, or combinations thereof. The bad row mode may be used to provide a positive control for post package repair (PPR) operations on the memory. A controller may enter the memory into bad row mode and then test the memory to determine if the selected bad row can be located and repaired via PPR.
Disclosed in some examples are methods, systems, memory devices, and machine-readable mediums which store a single compressed value per line with a marker value in a front of the compressed version of the memory line. In some examples, the only value stored in the memory line is the value normally stored therein. This removes the complexity of the prediction tables and the inclusion of invalid values as well as preventing the penalty when those prediction tables are wrong. Furthermore, by inclusion of the marker in the beginning of the memory line, the system can quickly determine the compression status of the memory line without having to read the entire line. That is, it can quickly stop reading the rest of the memory line once the compressed data is read out which saves the memory device from having to read the entire line.
Disclosed in some examples are improved address prediction and memory preloading that leverages next-delta prediction and/or far-delta prediction for scheduling using a DNN. Previous memory access sequence data that identify one or more memory addresses previously accessed by one or more processors of a system may be processed and then converted into a sequence of delta values. The sequence of delta values are then mapped to one or more classes that are then input to a DNN. The DNN then outputs a predicted future class identifier sequence that represents addresses that the DNN predicts will be accessed by the processor in the future. The predicted future class identifier sequence is then converted back to a predicted delta value sequence and back into a set of one or more predicted addresses.
The present disclosure relates to a method for operating an array of memory cells, the method comprising storing user data in a plurality of memory cells of the array, storing parity data associated with the user data in a plurality of parity cells of the array, and, based on the stored parity data, selecting an Error Correction Code (ECC) correction capability and/or an ECC granularity according to which an ECC operation is to be performed, wherein the selection of the ECC correction capability and/or the ECC granularity is determined by the steps of updating a first register, said first register comprising values which indicate a required ECC correction capability and/or a required ECC granularity to be applied to the memory cells based on a current status of said memory cells, wherein the values of the first register are updated based on a variation of the current status of the memory cells, and wherein an update of the values of the first register corresponds to a variation of the required ECC correction capability and/or a required ECC granularity to be applied to said memory cells, and based on the updated values of the first register, executing an ECC switch command, wherein the ECC switch command is such as to vary a previously selected ECC correction capability and/or a previously selected ECC granularity, the method further comprising: updating a second register according to the varied ECC correction capability and/or ECC granularity, said second register comprising values indicating the selected ECC correction capability and the selected ECC granularity applied to the memory cells based on the current status thereof. Related apparatuses and systems are also herein disclosed.
A system and method for recovery data generation for partial memory block modifications. An example system including a memory device and a processing device, operatively coupled with the memory device, to perform operations including: receiving a command to modify a portion of a memory block that is stored by the memory device, wherein the command comprises user data and a location in the memory block; reading user data at the location and existing recovery data for the memory block; generating recovery data for the memory block based on the existing recovery data, the user data at the location, and the user data of the command; and writing the user data of the command and the generated recovery data to the memory device, wherein the user data overwrites the portion of the memory block at the location.
A plurality of codewords are programmed to one or more memory pages of a memory sub-system. Each memory page of the memory sub-system is associated with a logical unit of a plurality of logical units of the memory sub-system and at least one of a plane of a plurality of planes of the memory sub-system or a block of a plurality of blocks of the memory subsystem. Each codeword of the plurality of codewords comprises host data and base parity bits. A plurality of additional parity bits are programmed to the one or more memory pages of the memory sub-system, wherein each additional parity bit of the plurality of additional parity bits is associated with a codeword of the plurality of standard codewords. A first set of redundancy metadata is generated corresponding to each of the additional parity bits. The first set of redundancy metadata is programmed to a memory page separate from any memory page storing the additional parity bits.
An input/output (I/O) command referencing a logical address of a memory sub-system is received by an active input/output expander (AIOE). The I/O command is received from a memory sub-system controller via the AIOE. The AIOE identifies a physical block address corresponding to the logical block address. The AIOE identifies, among a plurality of memory devices, a memory device associated with the physical block address. The AIOE converts the I/O command received via the serial interface to a parallel interface compliant I/O command. The AIOE sends the parallel interface compliant I/O command to the memory device.
Disclosed is a system that comprises a memory device and a processing device, operatively coupled with the memory device, to perform operations that include, determining that a value of a write counter associated with the memory device satisfies a first threshold criterion. The operations performed by the processing device further include, responsive to determining that the value of the write counter satisfies the first threshold criterion, identifying a first memory unit and a second memory unit of the memory device, the second memory unit comprising one or more memory cells adjacent to one or more memory cells of the first memory unit. The operations performed by the processing device further include performing a read operation on the second memory unit to determine a set of failed bit count statistics corresponding to a plurality of codewords of the second memory unit. The operations performed by the processing device further include determining that the set of failed bit count statistics corresponding to the plurality of codewords of the second memory unit satisfies a second threshold criterion. The operations performed by the processing device further include, responsive to determining that the set of failed bit count statistics corresponding to the plurality of codewords of the second memory unit satisfies the second threshold criterion, performing a write scrub operation on the second memory unit.
A processing device of a memory sub-system is configured to perform a plurality of write operations on a memory device comprising a plurality of memory units; responsive to performing each write operation on a respective first memory unit of the memory device, the processing device is configured to identify a candidate memory unit that has been written to by a at least a threshold fraction of the plurality of write operations performed on the memory device; determine whether a threshold refresh criterion is satisfied; and responsive to determining that the threshold refresh criterion is satisfied, refresh data stored at one or more of the memory units that are proximate to the candidate memory unit.
Semiconductor devices and associated systems and methods are disclosed herein. In some embodiments, the semiconductor devices include a package substrate, a stack of dies carried by the package substrate, and one or more radiation shields configured to absorb neutrons from neutron radiation incident on the semiconductor device. The radiation shields can include one or more walls attached to a perimeter portion of the package substrate at least partially surrounding the stack of dies and/or a lid carried over the stack of dies. Each of the radiation shields can include hydrocarbon materials, boron, lithium, gadolinium, cadmium, and like materials that effectively absorb neutrons from neutron radiation. In some embodiments, the semiconductor devices also include a molding material over the stack of dies and the radiation shields, and a hydrocarbon coating over an external surface of the mold material.
H01L 23/552 - Protection against radiation, e.g. light
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
An apparatus can include a media management superblock component. The media management superblock component can determine that a quantity of blocks of a superblock of a non-volatile memory array are bad blocks. The media management superblock component can compare the quantity of bad blocks to a bad block criteria. The media management superblock component can write host data to the superblock with the quantity of bad blocks in response to the quantity of bad blocks meeting the bad block criteria.
A method includes allocating, via a tier allocation component, a first portion of data to a first tier memory component and writing the first portion of data to the first tier memory component in response to a first tier free list having an available entry. The method further includes evicting a second portion of data from the first tier memory component in response to the first tier free list being empty when the first portion of data is allocated to the first tier memory component and writing the first portion of data to the first tier memory component in response to evicting the second portion of data.
G06F 3/06 - Digital input from, or digital output to, record carriers
G06F 11/14 - Error detection or correction of the data by redundancy in operation, e.g. by using different operation sequences leading to the same result
86.
UNIFIED SEQUENCER CONCURRENCY CONTROLLER FOR A MEMORY SUB-SYSTEM
An input/output (I/O) command referencing a memory device is identified. A power limit of the memory device is determined. A power level associated with executing the I/O command is estimated. Responsive to determining that the power level satisfies the power limit, the I/O command is executed.
A system can include a memory devices and a processing device coupled with the memory devices. The processing device can receive a command and determine whether the command includes a value for a voltage associated with a read at the memory device. The processing device can also, responsive to the command failing to specify the value, select a second value, from multiple values, for the voltage associated with the read at the memory device based at on a duration subsequent to a previous write operation satisfying a threshold criterion. The processing device can also apply the voltage having the second value at memory cells of the memory device to determine a logic state for the memory cells.
Responsive to receiving a table flush command, a first portion of an address mapping table is identified. A first flush operation with respect to a first portion of the address mapping table is performed. Responsive to receiving at least one memory access command, flush operations for a subsequent portion of the address mapping table is suspended. At least one memory access operation specified by the at least one memory access command is performed. A second flush operation with respect to the subsequent portion of the address mapping table is performed.
A request to program host data to a memory device of a memory sub-system is received. Redundancy metadata associated with the host data is generated. A determination is made, in view of the received request, whether the host data is valid data or invalid data. In response to a determination that the host data is invalid data, updated redundancy metadata associated with the host data is generated. The updated redundancy metadata indicates that the host data is invalid data. The host data and the updated redundancy metadata is programmed to the memory device.
Systems and methods are disclosed including a method comprising sending, by a monitored central processing unit (CPU) to a monitoring CPU of a memory sub-system controller, an address range of a logging data structure stored within a local memory component of the monitored CPU; storing, in the logging data structure by the monitored CPU, a log file comprising system state information associated with one or more tasks performed by the monitored CPU; executing, by the monitoring CPU, a data-gathering task to retrieve the log file from the logging data structure; and sending, by the monitoring CPU, the log file to a host system.
A system and method for optimizing seasoning trim values based on form factors in memory sub-system manufacturing. An example method includes selecting a baseline set of trim values based on a set of memory sub-system form factors; generating a first modified set of trim values by modifying a first trim value of the baseline trim values; instructing each memory sub-system to perform seasoning operations using the first modified set of trim values; responsive to determining that each memory sub-system passed failure scanning operations, generating a second modified set of trim values; instructing each memory subsystem to perform seasoning operations using the second modified set; responsive to determining that a memory sub-system failed the failure scanning operations, determining whether the failed memory sub-system is defective; and responsive to determining that the failed memory sub-system does is not defective, storing the first modified trim values for the set of form factors.
A microelectronic device comprises array regions individually comprising memory cells comprising access devices and storage node device, digit lines coupled to the access devices and extending in a first direction, word lines coupled to the access devices and extending in a second direction orthogonal to the first direction, and control logic devices over and in electrical communication with the memory cells. The microelectronic device further comprises capacitor regions horizontally offset from the array regions in the first direction and having a dimension in the second direction greater than each individual array region in the second direction. The capacitor regions individually comprise additional control logic devices vertically overlying the memory cells, and capacitor structures within horizontal boundaries of the additional control logic devices. Related microelectronic devices, electronic systems, and methods are also described.
H01L 27/108 - Dynamic random access memory structures
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
Methods, systems, and devices for deck-level signal development cascodes are described. A memory device may include transistors that support both a signal development and decoding functionality. In a first operating condition (e.g., an open-circuit condition), a transistor may be operable to isolate first and second portions of an access line based on a first voltage applied to a gate of the transistor. In a second operating condition (e.g., a signal development condition), the transistor may be operable to couple the first and second portions of the access line and generate an access signal based on a second voltage applied to the gate of the transistor. In a third operating condition (e.g., a closed-circuit condition), the transistor may be operable to couple the first and second portions of the access line based on applying a third voltage greater than the second voltage to the gate of the transistor.
G11C 11/4074 - Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
G11C 11/4096 - Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
G11C 11/22 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
94.
METHODS OF FORMING MICROELECTRONIC DEVICES, AND RELATED MICROELECTRONIC DEVICES AND ELECTRONIC SYSTEMS
A method of forming a microelectronic device comprises forming a microelectronic device structure comprising memory cells, digit lines, word lines, and isolation material. Contact structures are formed to extend through the isolation material. Some of the contact structures are coupled to some of the digit lines, and some other of the contact structures are coupled to some of the word lines. Air gaps are formed to be interposed between the contact structures and the isolation material. An additional microelectronic device structure comprising control logic devices and additional isolation material is formed. After forming the air gaps, the additional microelectronic device structure is attached to the microelectronic device structure. Additional contact structures are formed to extend through the additional isolation material and to the contact structures. The additional contact structures are in electrical communication with the control logic devices. Microelectronic devices, electronic systems, and additional methods are also described.
Microelectronic devices include a stack structure having a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. At least one stadium, of stadiums within the stack structure, comprise staircase(s) having steps provided by a group of the conductive structures. Step contacts extend to the steps of the staircase(s) of the at least one of the stadiums. Each conductive structure of the group of conductive structures has more than one of the step contacts in contact therewith at at least one of the steps of the staircase(s). Additional microelectronic devices are also disclosed, as are methods of fabrication and electronic systems.
H01L 27/11556 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 27/11524 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the memory core region with cell select transistors, e.g. NAND
H01L 27/1157 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the memory core region with cell select transistors, e.g. NAND
H01L 27/11548 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the boundary region between the core and peripheral circuit regions
H01L 27/11575 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the boundary region between the core and peripheral circuit regions
96.
WRITE PERFORMANCE OPTIMIZATION FOR ERASE ON DEMAND
Methods, apparatuses, and systems relates to write performance optimization for erase on demand. The methods include erasing a portion of memory from a garbage pool in response to detecting an idle period. A request to write data to the memory is received and it is determined that a charge gain threshold has not been satisfied for the erased portion of memory. The data is written to the erased portion of memory in response to determining the charge gain threshold has not been satisfied.
A device (10) includes a first memory die (60) and a second memory die (62) directly coupled to the first memory die (60) via a first bus (64). The device (10) also includes a second bus (48) directly coupled to the first memory die (60). The first memory die (60) includes a first trim circuit (88) that when in operation adjusts a delay of signal transmission by the first memory die (60) to a first value, while the second memory die (62) comprises a second trim circuit (88) that when in operation adjusts a delay of signal transmission by the second memory die (62) by a second value.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices
The systems and methods described herein consider a first channel width of transistors of driver circuitry (60), where the first channel width may be set to match a second channel width of a power control transistor (82). A control circuit (66), for example, may match a second channel width of a set of power control transistors (82) to the first channel width by turning on one or more of the set of power control transistors (82). Matching the width of the switches of driver circuitry (60) and the width of the set of power control transistors (82) may reduce losses by helping to maintain impedances of the driver circuitry (60).
G11C 11/4096 - Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
G11C 11/4074 - Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
99.
MEMORY ARRAYS COMPRISING STRINGS OF MEMORY CELLS AND METHODS USED IN FORMING A MEMORY ARRAY COMPRISING STRINGS OF MEMORY CELLS
A memory array comprising strings of memory cells comprises conductor tier comprising conductor material. Laterally-spaced memory blocks individually comprising a vertical stack comprises alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Conducting material of a lower of the conductive tiers directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. The conducting material in the lower conductive tier comprises upper conductively-doped semiconductive material, lower conductively-doped semiconductive material, and intermediate material vertically there-between. Other embodiments, including method, are disclosed.
H01L 27/11556 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 27/11524 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the memory core region with cell select transistors, e.g. NAND
H01L 27/1157 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the memory core region with cell select transistors, e.g. NAND
H01L 27/11548 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the boundary region between the core and peripheral circuit regions
H01L 27/11575 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the boundary region between the core and peripheral circuit regions
A method includes determining a traffic pattern of access requests within a queue or a system, or both and dynamically adjusting, within a particular range, a queue depth of the queue based on the determined traffic pattern of access requests to balance bandwidth and latency associated with executing the access requests.
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