A dynamic memory system having multiple memory regions respectively storing multiple types of data. A controller coupled to the dynamic memory system via a communication channel and operatively to: monitor usage of a communication bandwidth of the communication channel; determine to reduce memory bandwidth penalty caused by refreshing the dynamic memory system; and in response, reduce a refresh rate of at least one of the memory regions based on a type of data stored in the respective memory region.
Methods, systems, and devices for switch and hold biasing for memory cell imprint recovery are described. A memory device may be configured to perform an imprint recovery procedure that includes applying one or more recovery pulses to memory cells, where each recovery pulse is associated with a voltage polarity and includes a first portion with a first voltage magnitude and a second portion with a second voltage magnitude that is lower than the first voltage magnitude. In some examples, the first voltage magnitude may correspond to a voltage that imposes a saturation polarization on a memory cell (e.g., on a ferroelectric capacitor, a polarization corresponding to the associated voltage polarity) and the second voltage magnitude may correspond to a voltage magnitude that is high enough to maintain the saturation polarization (e.g., to prevent a reduction of polarization) of the memory cell.
G11C 11/22 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
3.
END-TO-END QUALITY OF SERVICE MANAGEMENT FOR MEMORY DEVICE
A set of submission queues associated with a host system is identified. A first set of internal queues and a second set of internal queues is generated based on the set of submission queues. Responsive to fetching a first memory access command pending in a submission queue of the set of submission queues, a first internal queue of the first set of internal queues is populated. Responsive to processing the first memory access command from the first internal queue of the first set of internal queues, a second internal queue of the second set of internal queues is populated. Responsive to completion of the first memory access command from the second internal queue of the second set of internal queues, an indication of the completion of the first memory access command is returned to the host system.
Systems, apparatuses, and methods for transmission failure feedback associated with a memory device are described. A memory device may detect errors in received data and transmit an indication of the error when detected. The memory device may receive data and checksum information for the data from a controller. The memory device may generate a checksum for the received data and may detect transmission errors. The memory device may transmit an indication of detected errors to the controller, and the indication may be transmitted using a line that is different than an error detection code (EDC) line. A low-speed tracking clock signal may also be transmitted by the memory device over a line different than the EDC line. The memory device may transmit a generated checksum to the controller with a time offset applied to the checksum signaled over the EDC line.
A multi-interface memory can include a memory package that includes a memory device and host interfaces coupled to the memory device. Each of the host interfaces is configured to operate according to a different protocol. The memory package can be coupled to a host via one or more of the host interfaces. More than one of the host interfaces can share a contact.
A microelectronic device comprises a stack structure comprising a stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers, the stack structure divided into block structures separated from one another by slot structures, strings of memory cells vertically extending through the block structures of the stack structure, the strings of memory cells individually comprising a channel material vertically extending through the stack structure, an additional stack structure vertically overlying the stack structure and comprising a vertical sequence of additional conductive structures and additional insulative structures arranged in additional tiers, first pillars extending through the additional stack structure and vertically overlying the strings of memory cells, each of the first pillars horizontally offset from a center of a corresponding string of memory cells, second pillars extending through the additional stack structure and vertically overlying the strings of memory cells, and additional slot structures comprising a dielectric material extending through at least a portion of the additional stack structure and sub-dividing each of the block structures into sub-block structures, the additional slot structures horizontally neighboring the first pillars. Related microelectronic devices, electronic systems, and methods are also described.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
7.
METHODS OF FORMING ELECTRONIC DEVICES INCLUDING RECESSED CONDUCTIVE STRUCTURES AND RELATED SYSTEMS
An electronic device comprises a stack structure comprising vertically alternating insulative structures and conductive structures arranged in tiers, pillars extending vertically through the stack structure, and a barrier material overlying the stack structure. The electronic device comprises a first insulative material extending through the barrier material and into an upper tier portion of the stack structure, and a second insulative material laterally adjacent to the first insulative material and laterally adjacent to at least some of the conductive structures in the upper tier portion of the stack structure. At least a portion of the second insulative material is in vertical alignment with the barrier material. Additional electronic devices and related methods and systems are also disclosed.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
8.
ERROR DETECTION, CORRECTION, AND MEDIA MANAGEMENT ON A DRAM DEVICE
In a memory controller system, a system and method to identify memory errors which may require soft package repair or hard package repair to rows of DRAM memory. When data is written to a row of DRAM, the data is immediately and automatically read back and scanned for bit errors. If bit errors are identified, the data is corrected and written back to the same memory location. The memory location is re-read. If bit errors are again identified, the memory location is marked for soft or hard repair. If, upon rereading the memory location, additional bit errors are identified, a historical record of memory errors is reviewed to determine if bit errors have occurred previously at the same memory location. If yes, the memory location is again marked for a soft post package repair or a hard post package repair.
A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers in the memory blocks. The channel-material strings directly electrically couple to conductor material of the conductor tier. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The intervening material comprises a laterally-outer insulative lining extending longitudinally-along the immediately-laterally-adjacent memory-blocks. The laterally-outer insulative lining has its lowest surface between a top and a bottom of the lowest conductive tier. The laterally-outer insulative lining has its highest surface at or below a lowest surface of the next-lowest conductive tier. Laterally-inner insulating material extends longitudinally-along the immediately-laterally-adjacent memory blocks laterally-inward of the laterally-outer insulative lining. An interface is between the laterally-outer insulative lining and the laterally-inner insulating material. Methods are also disclosed.
H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 27/11556 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
A decoding operation is performed by altering at least one bit of the bit string from a first value to a second value and applying a bit mask to each bit of the bit string that is not altered from the first value to the second value. The decoding operation further includes writing an indication corresponding to a quantity of bits that have been altered from the first value to the second value to an array of memory cells, wherein the indication corresponds to a quantity of errors contained in the bit string, determining that the quantity of errors for the bit string has reached a threshold quantity of errors, and refraining from performing a subsequent operation to alter at least the one bit of the bit string, or a different bit of the bit string, or both, from the first value to the second value in response to determining that the quantity of errors for the bit string has reached the threshold quantity of errors.
H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
H03M 13/00 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
H03M 13/15 - Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
11.
ENHANCED VALLEY TRACKING WITH TRIM SETTING UPDATES IN A MEMORY DEVICE
Control logic in a memory device receives a request to perform a read operation to read data from a memory array of a memory device, the request comprising an indication of a segment of the memory array where the data is stored, and performs a first coarse valley tracking calibration operation on the segment of the memory array. The control logic further configures a read voltage level and one or more parameters associated with the read operation based on a result of the first coarse valley tracking calibration operation and performs a second fine valley tracking calibration operation on the segment of the memory array using the configured read voltage level and the configured one or more parameters.
Systems, apparatuses, and methods related to transferring data to a memory device based on importance are described. A memory apparatus includes a first memory device, a second memory device having a lower write latency than the first memory device, and a controller coupled to the first memory device and second memory device via a compute express link (CXL) interface. The controller is configured to assign an importance level to a write request based on data associated with the write request, a hierarchy of importance levels for different data types, and the second memory device having a lower write latency than the first memory device. The controller is further configured to transfer the data to the first memory device in response to the assigned importance level having a first value and transfer the data to the second memory device in response to the assigned importance level having a second value.
A request to perform a data operation associated with at least one memory unit in a plurality of memory units of a memory device is received. The at least one memory unit includes a first group of memory cells, each memory cell supporting a specified number of charge levels such that each memory cell having the specified charge level represents a non-integer number of bits. The first group of memory cells represents a first sequence of bits based on a first sequence of charge levels formed by the first group of memory cells. The data operation is performed with respect to the at least one memory unit based on a mapping stored on the system. The mapping assigns an individual sequence of charge levels from an individual group cell to an individual sequence of bits represented by the individual group of memory cells.
A memory device can include multiple memory cells and a processing device operatively coupled with the memory device to perform operations including grouping the memory cells into a groups based on a metric reflecting an electrical distance of a memory cell from a voltage source, and determining, for each group, a respective share of write operations, wherein the share of write operations is related to an aggregate value of the metric for memory cells of the group. The operations can also include distributing the write operations to each group according to the share of write operations determined for the group.
G11C 29/42 - Response verification devices using error correcting codes [ECC] or parity check
G11C 29/12 - Built-in arrangements for testing, e.g. built-in self testing [BIST]
G11C 29/20 - Address generation devices; Devices for accessing memories, e.g. details of addressing circuits using counters or linear-feedback shift registers [LFSR]
G11C 29/44 - Indication or identification of errors, e.g. for repair
15.
VERTICAL DIGIT LINES WITH ALTERNATING EPITAXIAL SILICON FOR HORIZONTAL ACCESS DEVICES IN 3D MEMORY
Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and storage nodes. The horizontally oriented access devices having a first source/drain regions and a second source drain regions separated by silicon (Si) channel regions. A digit line having a global digit line (GDL) contact is formed in a trench adjacent to the first source/drain regions. In one example, the digit line is electrically isolated from a neighboring digit line at the bottom of the trench. In another example, the digit line is formed continuously along a bottom surface of trench to form shared digit lines between horizontal access devices, in two separate arrays, on opposing second vertical surfaces. The memory cells have horizontally oriented storage nodes coupled to the second source/drain regions and vertical digit lines coupled to the first source/drain regions.
Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and storage nodes formed in tiers. And, more particularly, to multiple, alternating silicon germanium (SiGe) and single crystalline silicon (Si) in different thicknesses to form tiers in which to form the horizontal access devices in vertical three-dimensional (3D) memory. The horizontally oriented access devices can have a first source/drain regions and a second source drain regions separated by single crystalline silicon (Si) channel regions. The single crystalline silicon (Si) channel regions can include a dielectric material to provide support structure to the single crystalline channel regions when forming the horizontal access devices in vertical three-dimensional (3D) memory. Horizontally oriented access lines can connect to gate structures opposing the channel regions. Vertical digit lines coupled to the first source/drain regions.
In a memory controller system, a system and method to identify memory errors which may require soft package repair or hard package repair to rows of DRAM memory. When data is written to a row of DRAM, the data is immediately and automatically read back and scanned for bit errors. If bit errors are identified, the data is corrected and written back to the same memory location. The memory location is re-read. If bit errors are again identified, the memory location is marked for soft or hard repair. If, upon rereading the memory location, additional bit errors are identified, a historical record of memory errors is reviewed to determine if bit errors have occurred previously at the same memory location. If yes, the memory location is again marked for a soft post package repair or a hard post package repair.
In a compute express link (CXL) memory controller system, a system and method to identify memory errors which may require soft package repair or hard package repair to rows of DRAM memory. When data is written to a row of DRAM, the data is immediately and automatically read back and scanned for bit errors. If bit errors are identified, steps are taken to determine if the memory location requires no repair, soft repair, or hard repair. The data is corrected and written back to a new memory location which is memory-mapped to the original location, thus effecting the soft- or hard-repair. The present system and method does not repair the entire row of memory, but only repairs the specific die(s) that exhibit memory error in the row.
Methods, systems, and devices for counter management for memory systems are described. A memory system may include circuitry configured to test localized counters of the memory system, where the circuitry may be configured to test a set of memory cells storing a value of the counter. During testing, the memory system may activate a row of memory cells a quantity of times, and the circuitry may increment a test counter associated with a subset of the set of memory cells for each activation to determine whether the subset is associated with an error. If a flag generated by the circuitry indicating a test count does not match an expected value, there may be an error associated with the subset. The circuitry may be operable to configure one or more multiplexers to refrain from using the subset to store the value of the counter based on the flag.
Semiconductor devices are disclosed. A semiconductor device may include a hybrid transistor configured in a vertical orientation. The hybrid transistor may include a gate electrode, a drain material, a source material, and a channel material operatively coupled between the drain material and the source material. The source material and the drain material include a first material and the channel material includes a second, different material.
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
H10N 70/00 - Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
H10N 70/20 - Multistable switching devices, e.g. memristors
Methods, systems, and devices for testing operations for memory systems are described. A memory system may include a first circuit and a second circuit configured to test one or more counters tracking the quantity of activates to respective rows of memory cells. In some examples, the memory system may initiate an operation to validate a counter of the memory system. The first circuit may determine if a value of the counter is correct by comparing a set of counter bits representing the value of the counter to a set of parity bits. Subsequently, the second circuit may determine if the counter is incrementing correctly in accordance with a set quantity of activates to the corresponding row of memory cells. If the first circuit or the second circuit detect an error associated with the counter, the memory system may discard the row of memory cells associated with the faulty counter.
Methods, systems, and devices related to generating, by a pseudorandom binary sequence (PRBS) generator of a memory module, a PRBS comprising a first plurality of bits corresponding to a plurality of cycles of a clock signal of the memory module subsequent to a current cycle of the clock signal. Generation of the PRBS can be based on an intermediate PRBS comprising a second plurality of bits corresponding to the current cycle of the clock signal. During each respective cycle of the clock signal, a respective subset of the PRBS can be communicated from the PRBS generator to a memory device of the memory module. Each respective subset of the PRBS comprises a quantity of bits based on a frequency of a data strobe signal of the memory device relative to a frequency of the clock signal.
H03K 3/84 - Generating pulses having a predetermined statistical distribution of a parameter, e.g. random pulse generators
H03K 19/21 - EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
A method includes determining a quantity of errors for a bit string based on a quantity of bits having a logical value of one within the bit string and writing an indication corresponding to the quantity of errors for the bit string to an array of memory cells. The method can further include determining that the quantity of errors for the bit string has reached a threshold quantity of errors and refraining from performing a subsequent operation to determine the quantity of errors for the bit string in response to determining that the quantity of errors for the bit string has reached the threshold quantity of errors.
A system includes a processor and a hardware accelerator coupled to the processor. The hardware accelerator includes data analysis elements configured to analyze a data stream based on configuration data and to output a result, and an integrated circuit device that includes a DMA engine that writes input data to and read output data from the data analysis elements, one or more preprocessing cores that receive the input data from the DMA engine prior to the DMA engine writing the input data to the one or more data analysis elements and perform custom preprocessing functions on the input data, and one or more post-processing cores that receive the output data from the DMA engine after the output data is read from the data analysis elements but prior to the output data being output to the processor and perform custom post-processing functions on the output data.
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
G06F 13/10 - Program control for peripheral devices
According to one or more embodiments of the disclosure, an alignment-overlay mark is provided. The alignment-overlay mark includes a pair of first marks and a plurality of second marks. The first marks extend in a first direction and are arranged in parallel to each other in a second direction. The second direction is perpendicular to the first direction. The second marks are between the first marks, extend in the second direction and are arranged in parallel to each other in the first direction.
Multiple copies of a stored data are sensed from a subset of memory cells of an array of memory cells into a plurality of latch elements in a page buffer coupled to the array of memory cells. Two or more latch elements are selected by enabling a respective select line of each of the two or more latch elements. An output data is determined based on a sensing of the conducting line driven by the two or more latch elements.
A method for an autonomous vehicle includes: controlling at least one system of the vehicle by a host system; automatically collecting, by a memory device, data generated by the at least one system, where the data is collected by the memory device independently of control by the host system; and storing the data in the memory device.
G07C 5/08 - Registering or indicating performance data other than driving, working, idle, or waiting time, with or without registering driving, working, idle, or waiting time
B60W 50/02 - Ensuring safety in case of control system failures, e.g. by diagnosing, circumventing or fixing failures
G05D 1/00 - Control of position, course, altitude, or attitude of land, water, air, or space vehicles, e.g. automatic pilot
G06F 3/06 - Digital input from, or digital output to, record carriers
G07C 5/00 - Registering or indicating the working of vehicles
A processing device in a memory sub-system retrieves an input/output (IO) instruction of a plurality of IO instructions from an IO instruction memory in the memory sub-system, the IO instruction comprising a first number of bits. The processing device further generates an IO vector based on the IO instruction, the IO vector comprising a second number of bits, wherein the second number of bits is greater than the first number of bits. In addition, the processing device causes a plurality of IO signals, based on the IO vector, to be driven on a signal communication bus to a memory device in the memory sub-system, wherein the plurality of IO signals comprises a number of signals equal to the second number of bits of the IO vector.
Systems, methods, and apparatus related to a multi-level error correction architecture used for copying data in memory devices. In one approach, user data is stored in the first partition of a non-volatile memory. First error correction code data is generated for the user data and stored with the user data in the first partition. Second error correction code data is generated for the user data and stored outside the first partition. The second error correction code data provides an increased error correcting capability that is compatible with the error correction algorithm used with the first error correction code data. A copyback operation is used to copy the user data and the first error correction code, but not the second error correction code, to a second partition of the non-volatile memory. The second error correction code can be selectively used if there is a need to recover portions of the user data stored in the first partition.
G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
H03M 13/29 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
Systems, apparatuses, and methods related to memory access statistics monitoring are described. A host is configured to map pages of memory for applications to a number of memory devices coupled thereto. A first memory device comprises a monitoring component configured to monitor access statistics of pages of memory mapped to the first memory device. A second memory device does not include a monitoring component capable of monitoring access statistics of pages of memory mapped thereto. The host is configured to map a portion of pages of memory for an application to the first memory device in order to obtain access statistics corresponding to the portion of pages of memory upon execution of the application despite there being space available on the second memory device and adjust mappings of the pages of memory for the application based on the obtained access statistics corresponding to the portion of pages.
The disclosed embodiments include a memory array configured to store a membrane potential and a synaptic connection identifier of each of a plurality of neurons, a plurality of processors coupled to the memory array, the plurality of processors configured to: immediately perform a search and match operation in the memory array upon receiving a spike message identifying relevant synaptic connections in the memory array, generate a bitmask signifying a first source neuron identifier having a match to a second source neuron identifier in the memory array, perform a synaptic integration and a long-time depression computation on a subset of spike messages including the first spike message, update membrane potentials of the plurality of neurons upon receiving an indication that all the spike messages identified in a barrier message have been received in the memory array, generate a new spike message, and transmit the new spike message to a network.
A memory device includes a command interface configured to receive write commands from a host device. Additionally, the memory device includes an input buffer configured to buffer a strobe signal from the host device. Furthermore, the memory device includes a first ripple counter and a second ripple counter. The memory device includes command handling circuitry configured to alternatingly start the first ripple counter and the second ripple counter in response to consecutive write commands. The command handling circuitry and/or the first and second ripple counters are configured to suppress a reset of the input buffer if either the first ripple counter or the second ripple counter has not reached a threshold and is still counting.
A microelectronic device includes a stack structure including a block region and a non-block region. The block region includes blocks separated from one another in a first horizontal direction by insulative slot structures and each including a vertically alternating sequence of conductive material and insulative material arranged in tiers. At least one of the blocks has stadium structures individually including staircase structures having steps comprising edges of some of the tiers. The non-block region neighbors the block region in the first horizontal direction. The non-block region includes additional stadium structures individually terminating at a relatively higher vertical position within the stack structure than at least one of the stadium structures at least partially within boundaries thereof in a second horizontal direction orthogonal to the first horizontal direction. Related memory devices, electronic systems, and methods are also described.
H01L 23/528 - Layout of the interconnection structure
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/535 - Arrangements for conducting electric current within the device in operation from one component to another including internal interconnections, e.g. cross-under constructions
A memory device may be used to implement a Bloom filter. In some examples, the memory device may include a memory array to perform a multiply-accumulate operation to implement the Bloom filter. The memory device may store multiple portions of a reference genetic sequence in the memory array and compare the portions of the reference genetic sequence to a read sequence in parallel by performing the multiply-accumulate operation. The results of the multiply-accumulate operation between the read sequence and the portions of the reference genetic sequence may be used to determine where the read sequence aligns to the reference sequence.
Methods, systems, and devices for read disturb management for memory are described. In some instances, data may be read from a first page of a virtual block of a memory system. If the data includes one or more errors, the memory system may read data from a second page of the virtual block and determine whether one or more errors exist in the data. The memory system may continue reading pages of the virtual block until a page includes no (or relatively few errors). The memory system may then refresh the pages.
A method to enhance images, including: receiving, in an image processing logic circuit in an integrated circuit device, first data representative of an input image; generating, by the image processing logic circuit, input data for an inference logic circuit in the integrated circuit device; generating, by the inference logic circuit, a column of bits from the input data; performing, by the inference logic circuit using memory cells in the integrated circuit device having threshold voltages programmed to represent at least one weight matrix, operations of multiplication and accumulation, via reading concurrently rows of the memory cells selected according to the column of bits; generating, by the inference logic circuit, output data based on results of the operations multiplication and accumulation; and generating, by the image processing logic circuit using the output data, second data representative of an output image enhanced from the input image.
H04N 5/3745 - Addressed sensors, e.g. MOS or CMOS sensors having additional components embedded within a pixel or connected to a group of pixels within a sensor matrix, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
H04N 5/357 - Noise processing, e.g. detecting, correcting, reducing or removing noise
A method in an integrated circuit device to compress images, including: generating, by an image processing logic circuit and based on first data representative of an input image, input data; generating, by an inference logic circuit and based on the input data, a column of inputs; converting, by the inference logic circuit using voltage drivers connected to wordlines and memory cells storing a weight matrix, and into output currents of the memory cells summed in bitlines, results of bitwise multiplications of bits in the column of inputs and bits stored in the memory cells in a form of threshold voltages of the memory cells; digitizing currents summed in the bitlines to obtain column outputs; generating, by the inference logic circuit, output data based on the column outputs; and generating, using the output data, second data representative of an output image compressed from the input image.
H04N 5/341 - Extracting pixel data from an image sensor by controlling scanning circuits, e.g. by modifying the number of pixels having been sampled or to be sampled
38.
Surveillance Cameras Implemented using Integrated Circuit Devices having Analog Inference Capability
A surveillance camera having: an image sensing pixel array operable to generate first data representative of an input image; a memory cell array having memory cells, wherein threshold voltages of the memory cells are programmable in a first mode to store weight matrices and programmable in a second mode to store second data representative of an output image generated from the input image; voltage drivers; current digitizers; an inference logic circuit operable to perform operations of multiplication and accumulation using the voltage drivers, the current digitizers, and a first portion of the memory cells programmed in the first mode to store the weight matrices used in generation of the output image; a transceiver; and a microprocessor configured to use the transceiver to communicate, to a computer system, a report identifying the output image stored in the memory cell array.
An integrated circuit device having a memory cell array with first layers of memory cells configured for operations of multiplication and accumulation. Each pair of closest layers among the first layers are configured to be separate by at least one layer in second layers of memory cells, where access to, or usages of, the second layers can be restricted or limited to prevent activities in the second layers from corrupting the weight programming in the first layers.
H04N 5/3745 - Addressed sensors, e.g. MOS or CMOS sensors having additional components embedded within a pixel or connected to a group of pixels within a sensor matrix, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
G06F 3/06 - Digital input from, or digital output to, record carriers
A method for a digital camera adaptable to monitor a scene to detect a condition of interest to a user. The digital camera can program, in a first mode, first memory cells according to first weight matrices to classify images captured by the digital camera. Second memory cells are programmed in a second mode to store data representative of the images. The digital camera can perform operations of multiplication and accumulation using the first memory cells to compute first classifications of the images. In response to mismatches between the first classifications and second classifications identified by the user for the images, the digital camera can execute instructions to determine second weight matrices and program, in the first mode, third memory cells, according to the second weight matrices for improved capability in detecting the condition represented by image classifications in a predetermined category.
H04N 5/3745 - Addressed sensors, e.g. MOS or CMOS sensors having additional components embedded within a pixel or connected to a group of pixels within a sensor matrix, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
G06V 10/764 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using classification, e.g. of video objects
G06V 10/82 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using neural networks
G06V 10/94 - Hardware or software architectures specially adapted for image or video understanding
G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
G11C 11/54 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using elements simulating biological cells, e.g. neuron
41.
ADAPTIVE PRE-READ MANAGEMENT IN MULTI-PASS PROGRAMMING
Exemplary methods, apparatuses, and systems include an adaptive pre-read manager for controlling pre-reads of the memory device. The adaptive pre-read manager receives a first set of data bits for programming to memory. The adaptive pre-read manager performing a first pass of programming including a first subset of data bits from the set of data bits. The adaptive pre-read manager compares a set of threshold operating differences to a set of differences between multiple operating conditions during the first pass of programming and current operating conditions. The adaptive pre-read manager performs an internal pre-read of the programmed first subset of data bits. The adaptive pre-read manager performs a second pass of programming using the internal pre-read and a second subset of data bits from the first set of data bits.
An apparatus includes a TM control circuit that is configured to receive address information corresponding to a TM function and compare the address information with an authorized TM list stored in a memory of the apparatus to determine if there is a match. If there is a match, a latch load signal pulse is output. A TM latch circuit programs one or more latches based on the address information and based on the latch load signal pulse. The TM latch circuit decodes information in the one or more latches and, based on the decoded information, outputs a test mode signal to turn on test mode operations in circuits associated with the TM function. The apparatus includes a plurality of TM functions for testing various features of the apparatus and the authorized TM list identifies which of the plurality of TM functions has been authorized for customer use.
G11C 7/24 - Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
G11C 17/16 - Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
43.
MANAGEMENT OF ERROR-HANDLING FLOWS IN MEMORY DEVICES USING PROBABILITY DATA STRUCTURE
Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including running sample data through each of a set of error-handling operations performed on data residing in a segment of the memory device in an existing order associated with a workload; obtaining error recovery data as a result of running the sample data; and determining an optimized order of the set of error-handling operations based on probability of error recovery and latency data, wherein the probability of error recovery is based on the error recovery data, and wherein the optimized order comprises an adjustment to an order of one or more error-handling operations of the set of error-handling operations in the existing order.
Methods, apparatuses, and systems related to embedded metal pads are described. An example semiconductor device includes a dielectric material, a metal pad having side surface, where a lower portion of the side surface is embedded in the dielectric material, a mask material on a portion of a surface of the dielectric material, an upper portion of the side surface of the metal pad, and a portion of a top surface of the metal pad and a contact pillar on a second portion of the top surface of metal pad, the contact pillar comprising a metal pillar and a pillar bump.
Methods, systems, and devices related to built-in self-test burst patterns based on architecture of memory. A controller can be coupled to a memory device. The controller can include built-in self-test (BIST) circuitry. The BIST circuitry can include registers configured to store respective write burst patterns and read burst patterns based on an architecture of the memory device.
Methods, systems, and devices related to built-in self-test (BIST) circuitry of a controller. The controller can be coupled to multiple memory devices. The BIST circuitry can include registers configured to store burst patterns. The BIST circuitry can perform a BIST operation on the memory devices contemporaneously and using the number of burst patterns.
Methods, apparatuses, and systems related to an over-sculpted storage node are described. An example method includes forming an opening in a pattern of materials. The method further includes performing an etch to over-sculpt the opening. The method further includes depositing a storage node material in the over-sculpted opening to form an over-sculpted storage node. The method further includes performing an etch to remove portions of the pattern of materials. The method further includes performing an etch on the storage node material to trim the over-sculpted storage node.
A system comprises a memory device including a plurality of management units and a processing device. The processing device is operatively coupled with the memory device and configured to place the plurality of management units into a first protective state by erasing the plurality of management units, identify a cursor satisfying a cursor definition, identify a subset of the plurality of management units based on a location, on the memory device, referenced by the cursor, and place a selected management unit of the subset of the plurality of management units into a second protective state by programming a protective data pattern to the selected management unit.
Devices and techniques for self-scheduling threads in a programmable atomic unit are described herein. When it is determined that an instruction will not complete within a threshold prior to insertion into a pipeline of the processor, a thread identifier (ID) can be passed with the instruction. Here, the thread ID corresponds to a thread of the instruction. When a response to completion of the instruction is received that includes the thread ID, the thread is rescheduled using the thread ID in the response.
G06F 9/38 - Concurrent instruction execution, e.g. pipeline, look ahead
G06F 9/48 - Program initiating; Program switching, e.g. by interrupt
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
50.
CONNECTIVITY IN COARSE GRAINED RECONFIGURABLE ARCHITECTURE
A reconfigurable compute fabric can include multiple nodes, and each node can include multiple tiles with respective processing and storage elements. The tiles can be arranged in an array or grid and can be communicatively coupled. In an example, the tiles can be arranged in a one-dimensional array and each tile can be coupled to its respective adjacent neighbor tiles using a direct bus coupling. Each tile can be further coupled to at least one non-adjacent neighbor tile that is one tile, or device space, away using a passthrough bus. The passthrough bus can extend through intervening tiles.
Systems and methods for a semiconductor device having a front-end-of-line structure are provided. The semiconductor device may include a dielectric material having a backside formed on a front side of a semiconductor substrate material and a front side, and an interconnect structure extending through the dielectric material. The interconnect structure may be electrically connected to a semiconductor memory array proximate the front side of the dielectric material. The semiconductor device may further have an insulating material encasing at least a portion of the semiconductor memory array and an opening created during back-end-of-line processing through which the active contact surface at the backside of the interconnect structure is exposed for electrical connection.
A system and method for a memory sub-system to reduce latency by prefetching data blocks and preloading them into host memory of a host system. An example system including a memory device and a processing device, operatively coupled with the memory device, to perform operations including: receiving a request of a host system to access a data block in the memory device; determining the data block stored in a first buffer in host memory is related to a set of one or more data blocks stored at the memory device; and storing the set of one or more data blocks in a second buffer in the host memory, wherein the first buffer is controlled by the host system and the second buffer is controlled by a memory sub-system.
G06F 12/0862 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
53.
DATA INTEGRITY PROTECTION FOR RELOCATING DATA IN A MEMORY SYSTEM
Methods, apparatuses, and systems related to data management and security in a memory device are described. Data may be stored in a memory system, and as part of an operation to move data from one region to another in the memory system, the data may be validated using one or more hash functions. For example, a memory device may compute a hash value of some stored data, and use the hash value to validate another version of that stored data in the process of writing the other version stored data to a region of the memory system. The memory device may store another hash that is generated from the hash of the stored data and a record of transactions such that transactions are identifiable; the sequence of transactions within the memory system may also be identifiable. Hashes of transactions may be stored throughout the memory system or among memory systems.
H04L 9/06 - Arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for blockwise coding, e.g. D.E.S. systems
54.
ENHANCED WRITE PERFORMANCE UTILIZING PROGRAM INTERLEAVE
A system includes a memory and a processing device, operatively coupled to the memory, to perform operations including initiating a write operation to write data to a first multiple level cell (XLC) storage including a first XLC block and a second XLC storage including a second XLC block, and causing a first portion of the data to be written to a first number of pages of the first XLC block and a second portion of the data to be written to a second number of pages of the second XLC block using page level interleave. The first number of pages and the second number of pages are defined by an interleave mix including an interleave ratio between a first XLC write mode and a second XLC write mode.
Disclosed in some examples are methods, systems, and machine readable mediums that provide increased bandwidth caches to process requests more efficiently for more than a single address at a time. This increased bandwidth allows for multiple cache operations to be performed in parallel. In some examples, to achieve this bandwidth increase, multiple copies of the hit logic are used in conjunction with dividing the cache into two or more segments with each segment storing values from different addresses. In some examples, the hit logic may detect hits for each segment. That is, the hit logic does not correspond to a particular cache segment. Each address value may be serviced by any of the plurality of hit logic units.
G06F 12/06 - Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication
G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
56.
Methods of Forming One or More Covered Voids in a Semiconductor Substrate, Methods of Forming Field Effect Transistors, Methods of Forming Semiconductor-on-Insulator Substrates, Methods of Forming a Span Comprising Silicon Dioxide, Methods of Cooling Semiconductor Devices, Methods of Forming Electromagnetic Radiation Emitters and Conduits, Methods of Forming Imager Systems, Methods of Forming Nanofluidic Channels, Fluorimetry Methods, and Integrated Circuitry
Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.
A system includes a memory device and a processing device communicatively coupled to the memory device. The processing device is to write data to a number of groups of memory cells of the memory device in a physically non-contiguous manner. The processing device is further to track a sequence in which the number of groups of memory cells were written with the data. In response to a trigger event, the processing device is further to identify at least a portion of the number of groups of memory cells having data received over a predefined period preceding the trigger event based at least in part on the tracked sequence.
A memory device may be used to implement a Bloom filter. In some examples, the memory device may include a memory array to perform a multiply-accumulate operation to implement the Bloom filter. The memory device may store multiple portions of a reference genetic sequence in the memory array and compare the portions of the reference genetic sequence to a read sequence in parallel by performing the multiply-accumulate operation. The results of the multiply-accumulate operation between the read sequence and the portions of the reference genetic sequence may be used to determine where the read sequence aligns to the reference sequence.
G11C 7/16 - Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters
A microelectronic device is disclosed, comprising a base structure comprising: active regions individually comprising semiconductor material; and isolation regions horizontally alternating with the active regions and individually comprising insulative material; a transistor structure comprising: a channel within one of the active regions of the base structure and horizontally interposed between two of the isolation regions; a gate dielectric structure including a high-k material above the channel; a gate electrode stack on the gate dielectric structure and comprising: diffusion prevention material on the gate dielectric structure and partially horizontally overlapping the channel, an opening in the diffusion prevention material horizontally centered about a horizontal centerline of the channel and having a smaller horizontal dimension than the channel; a conductive material comprising lanthanum on the diffusion prevention material and substantially filling the opening.
An apparatus includes: a plurality of capacitors each including first and second conductive portions and a dielectric portion therebetween; a first conductive structure containing the plurality of capacitors therein, and electrically coupled to the second conductive portions of the plurality of capacitors; a second conductive structure on a top surface of the first conductive structure; and a third conductive structure on a top surface of the second conductive structure.
Methods, systems, and devices for access circuitry structures for three-dimensional (3D) memory arrays are described. A memory device may include levels of memory cells over a substrate. To support accessing memory cells at respective levels, the memory device may include a conductive pillar extending through the levels of memory cells and coupled with one or more memory cells at respective levels of memory cells. The memory device may include a bit line and a contact that is configured to couple the bit line with the conductive pillar. The conductive pillar may be formed such that it extends into a portion of the contact, and a contact resistance between the conductive pillar and the bit line may be based on the conductive pillar extending into the portion of the contact.
H01L 23/535 - Arrangements for conducting electric current within the device in operation from one component to another including internal interconnections, e.g. cross-under constructions
H01L 23/528 - Layout of the interconnection structure
H01L 27/11556 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
62.
Balance Accuracy and Power Consumption in Integrated Circuit Devices having Analog Inference Capability
A method to balance computation accuracy and energy consumption, including: programming thresholds voltages of first memory cells to store first weight matrices representative of a first artificial neural network; programming thresholds voltages of second memory cells to store second weight matrices representative of a second artificial neural network smaller than the first artificial neural network, where both the first artificial neural network and the second artificial neural network are operable to provide at least one common functionality in processing each of the inputs; selecting configurations of using the first memory cells, or the second memory cells, or both in processing a sequence of inputs; and performing, according to the configurations, operations of multiplication and accumulation using the first memory cells, and the second memory cells in computations of the first artificial neural network and the second artificial neural network in processing the sequence of the inputs.
G06V 10/94 - Hardware or software architectures specially adapted for image or video understanding
G06F 7/544 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices for evaluating functions by calculation
G06N 3/04 - Architecture, e.g. interconnection topology
G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
G06V 10/774 - Generating sets of training patterns; Bootstrap methods, e.g. bagging or boosting
An integrated circuit device including: a first integrated circuit die having an image sensing pixel array; a second integrated circuit die having an image processing logic circuit and an inference logic circuit; and a third integrated circuit die having a memory cell array. The second integrated circuit die and the third integrated circuit die are connected via a direct bond interconnect. The inference logic circuit is configured to process an image from the image sensing pixel array via multiplication and accumulation operations based on memory cells in the memory cell array having threshold voltages programmed to store data in multiplications and output currents from the memory cells connected to lines in summations.
H04N 5/3745 - Addressed sensors, e.g. MOS or CMOS sensors having additional components embedded within a pixel or connected to a group of pixels within a sensor matrix, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
A method of artificial neural network computations, including: receiving image data having pixel values; generating, from the pixel values, a column of inputs to a set of artificial neurons; identifying a region of memory cells of the integrated circuit device having threshold voltages programmed to represent a weight matrix for the set of artificial neurons; instructing voltage drivers in the integrated circuit device to apply voltages to the region of memory cells according to the column of inputs; obtaining, based on the region of memory cells responsive to the applied voltages, a first column of data from an operation of multiplication and accumulation applied on the weight matrix and the column of inputs; and applying activation functions of the set of artificial neurons to the first column of data to generate a second column of data representative of outputs of the set of artificial neuron.
H04N 5/3745 - Addressed sensors, e.g. MOS or CMOS sensors having additional components embedded within a pixel or connected to a group of pixels within a sensor matrix, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
A device configured with redundant computations to improve reliability of using memory cells to perform operations of multiplication and accumulation. The device can have a memory cell array and a logic circuit. Each respective memory cell in the memory cell array has a threshold voltage programmable in a first mode to perform operations of multiplication and accumulation and programmable in a second mode, different from the first mode, to store data. The memory cell array has a plurality of regions operable in parallel to perform redundant operations of multiplication and accumulation. The logic circuit is configured to compare a plurality of results, generated from the redundant operations of multiplication and accumulation performed using the plurality of regions respectively, to select an output result from the plurality of results.
A device having a memory cell array configured with inverted weight data for operations of multiplication and accumulation. Each respective memory cell in the memory cell array has a threshold voltage programmable in a first mode to perform operations of multiplication and accumulation. The memory cell array has a plurality of regions operable in parallel to perform operations of multiplication and accumulation. The plurality of regions include a first region and a second region. At least a second portion of weight bits stored in the second region is an inverted version of a first portion of weight bits stored in the first region. The device includes a logic circuit configured to adjust a computation result of multiplication and accumulation generated using the second region to account for weight inversion and generate an output result based on a plurality of results generated using the plurality of regions respectively.
G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
G06F 7/544 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices for evaluating functions by calculation
G11C 7/12 - Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
67.
Weight Calibration Check for Integrated Circuit Devices having Analog Inference Capability
An integrated circuit device having a mechanism to check calibration of memory cells configured to perform operations of multiplication and accumulation. The integrated circuit device programs, in a first mode, threshold voltages of first memory cells in a memory cell array to store weight data, and programs, in a second mode, threshold voltages of second memory cells in the memory cell array to store a first result of applying an operation of multiplication and accumulation to a sample input and the weight data. During a calibration check, the integrated circuit device performs the operation using the first memory cells to obtain a second result, and compares the first result, retrieved from the second memory cells, and the second result to determine whether calibration of output current characteristics of the first memory cells programmed in the first mode is corrupted.
G11C 16/12 - Programming voltage switching circuits
G06F 7/544 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices for evaluating functions by calculation
A memory device for extending addressable array space by incorporating virtual and physical memory arrays is disclosed. When extra storage space beyond a physical memory array is needed by a controller of the memory device, the storage space may be provided by extending the address space using a virtual array. The memory device incorporates the use of an extra row address bit to increase the addressable space, whereby the extra bit is utilized to address virtual rows in the virtual array. Spare or redundant physical memory elements utilized for memory repair may be programmed to a virtual address space for the virtual memory array. When a memory device operation is activated, the extra row address bit is set to high, and the virtual row address matches with a spare or redundant memory element, the virtual row in the virtual array space is activated for performance of the operation.
Methods, systems, and devices for loading data in a tiered memory system are described. A respective allocation of computing resources may be determined for each node in a cluster, where at least one of the nodes may include multiple memory tiers, and a data set to be processed by the nodes may be analyzed. Based on the allocation of computing resources and the analysis of the data set, respective data processing instructions indicating respective portions of the data set to be processed by respective nodes may be generated and sent to the respective nodes. The respective data processing instructions may also indicate a respective distribution of subsets of the respective portions of the data set across the multiple memory tiers at the respective nodes.
G06F 12/0862 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
70.
READ LEVEL COMPENSATION FOR PARTIALLY PROGRAMMED BLOCKS OF MEMORY DEVICES
A system can include a memory device containing blocks made up of wordlines respectively connected to sets of memory cells, and a processing device, operatively coupled with the memory device to perform operations including responsive to receiving a read request that specifies a block, determining a value of a metric reflective of a number of programmed wordlines of the block. The operations can also include responsive to determining, based on the value of the metric, that the block is in a partially programmed state, identifying a read voltage offset corresponding to the value of the metric, and performing, using the read voltage offset, a read operation responsive to the read request.
An interface shim layer for a tightly-coupled random access memory device is disclosed. The interface shim layer redirects and coalesces integrated channels and connections between a stacked plurality of memory die and an application specific integrated circuit and directly connects to the memory die and to the application specific integrated circuit. A passive version of the interface shim layer incorporates a plurality of routing layers to facilitate routing of signals to and from the stacked plurality of memory die and the application specific integrated circuit. An active version of the interface shim layer incorporates separate physical interfaces for both the stacked plurality of memory die and the application specific integrated circuit to facilitate routing. The active version of the interface shim layer may further incorporate memory controller functions, built-in self-test circuits, among other capabilities that are migratable into the active interface shim layer.
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
72.
MATRIX FORMATION FOR PERFORMING COMPUTATIONAL OPERATIONS IN MEMORY
Apparatuses, methods, and systems for matrix formation for performing computational operations in memory are included. An embodiment includes a memory having a plurality of levels, wherein each of the plurality of levels includes a plurality of memory cells, voltage circuitry configured to apply sub-threshold voltages to the memory cells of each respective level, a plurality of sense lines, sense circuitry coupled to the plurality of sense lines, wherein the sense circuitry coupled to each respective sense line is configured to sense a state for each of the number of memory cells coupled to that respective sense line responsive to the voltage circuitry applying the sub-threshold voltages to the memory cells of each respective level, and processing circuitry configured to utilize the states for each of the memory cells to form a matrix and perform computational operations on data stored in the memory using the matrix.
Systems, apparatuses, and methods related to conversion of access data based on memory device size are described herein. An example apparatus can include a memory device, a mode register, an address decoder, and a memory controller. The memory device can include an array of memory cells. The memory controller can cause performance of a memory access. Performance of the memory access can include receiving access data associated with a first memory device size to access data stored in the memory device. The memory device can be a second memory device size. Performance of the memory access can further include accessing the data in the memory device that is the second memory device size using the access data.
An apparatus can include memory devices and a memory controller coupled to the memory devices via memory channels. The memory channels can disable a first memory channel associated with a first memory die in a respective memory chip of a memory device and perform a memory operation via a second memory channel involving a second memory die in the respective memory chip.
Methods, systems, and devices for techniques for indicating a write link error are described. The method may include a memory device receiving, from a host device, a write command, data, and a first set of error control bits for the data. The memory device may determine that the data includes an uncorrectable error using the first set of error control bits and generate a second set of error control bits for the data based on determining that the data includes the uncorrectable error. Further, the method may include the memory device storing the data and the second set of error control bits in a memory device and transmitting, to the host device, the data and an indication that the data received from the host device included the uncorrectable error based on the second set of error control bits.
Apparatus and methods are disclosed, including transistors, semiconductor devices and systems. Example semiconductor devices and methods include isolation trenches between transistors that include a floating liner. Floating liner examples enable trench widths that scale smaller than trenches that do not include floating liners. This allows increases in device density without sacrificing electronic properties of devise shown.
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
A training operation may be performed by a memory controller to provide a system clock signal and a data clock signal having a desired temporal (e.g., phase) relationship to one another. The system clock and data clock signals may be provided to a memory. In some examples, the memory controller may provide a command to the memory to put the memory in a training mode. Once in the training mode, the memory controller may provide a write command and toggle the data clock signal a number of times. If the memory provides one output, the memory controller may adjust the relationship between the data clock and system clock signals. If the memory provides another output, the memory controller may maintain the relationship between the data clock and system clock signals and exit the training mode.
A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. Laterally-spaced memory-block regions are formed that individually comprise a vertical stack comprising alternating first tiers and second tiers directly above the conductor tier. Channel-material strings of memory cells extend through the first tiers and the second tiers. Horizontally-elongated lines are formed in the conductor tier between the laterally-spaced memory-block regions. The horizontally-elongated lines are of different composition from an upper portion of the conductor material and comprise metal material. After the horizontally-elongated lines are formed, conductive material is formed in a lower of the first tiers and that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. Other embodiments, including structure independent of method, are disclosed.
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
79.
DYNAMIC PARTITION COMMAND QUEUES FOR A MEMORY DEVICE
A partition command is stored at free memory address location of the local memory corresponding to an index of an address array. The index is associated with an entry in the address array. A last entry in a linked list of entries from a tail register is obtained based on an allocation of the stored partition command to a partition command queue of a plurality of partition command queues. The tail register corresponds to the partition command queue of the plurality of partition command queues. Responsive to obtaining the last entry in the linked list, an entry to the linked list after the last entry is appended. The entry corresponds to the index of the address array associated with the stored partition command.
A memory cell comprises channel material, charge-passage material, programmable material, a charge-blocking region, and a control gate. The programmable material comprises at least two regions comprising SiNx having a region comprising SiOy therebetween, where “x” is 0.5 to 3.0 and “y” is 1.0 to 3.0. Methods are disclosed.
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
81.
SEMICONDUCTOR DIE ASSEMBLIES WITH DECOMPOSABLE MATERIALS AND ASSOCIATED METHODS AND SYSTEMS
Semiconductor die assemblies with decomposable materials, and associated methods and systems are disclosed. In an embodiment, a semiconductor die assembly includes a memory controller die carrying one or more memory dies attached to its first side. The semiconductor die assembly also includes a biodegradable structure attached to its second side opposite to the first side. The biodegradable structure includes a conductive material and an insulating material, both of which are biodegradable and disintegrate in a wet process. The biodegradable structure can be configured to couple the memory controller die with an interface die. In this manner, when the biodegradable structure disintegrates (e.g., dissolve) in the wet process, the memory controller carrying the memory dies can be separated from the interface die to reclaim the memory controller with the memory dies and the interface die.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
82.
TEMPERATURE-COMPENSATED TIME ESTIMATE FOR A BLOCK TO REACH A UNIFORM CHARGE LOSS STATE
A processing device in a memory sub-system monitors a temperature associated with a block of a memory device, the block comprising a plurality of wordlines. The processing device further determines a first amount of time between when memory cells associated with a first wordline of the plurality of wordlines of the block were written and when memory cells associated with a last wordline of the plurality of wordlines of the block were written. That first amount of time is normalized according to the temperature associated with the block. The processing device further determines, based at last in part on the first amount of time and on an associated scaling factor, an estimate of when the block will reach a uniform charge loss state.
G11C 7/04 - Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
G06F 3/06 - Digital input from, or digital output to, record carriers
G11C 16/08 - Address circuits; Decoders; Word-line control circuits
G11C 16/26 - Sensing or reading circuits; Data output circuits
83.
ELECTRONIC DEVICES INCLUDING A METAL SILICIDE MATERIAL OVER A SOURCE CONTACT, AND RELATED MEMORY DEVICES, SYSTEMS, AND METHODS OF FORMING
An electronic device includes a source contact adjacent to a source stack, the source stack including one or more conductive materials, tiers of alternating conductive material and dielectric materials adjacent to the source contact, pillars extending vertically through the tiers and the source contact and at least partially into the source contact, a fill material extending vertically through the tiers to the source contact, and a metal silicide material between the fill material and an upper surface of the source contact. Related devices, systems, and methods are also disclosed.
H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
H01L 27/11565 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the top-view layout
84.
ADAPTIVE TEMPERATURE PROTECTION FOR A MEMORY CONTROLLER
Methods, systems, and devices for adaptive temperature protection for a memory controller are described. In some cases, a memory system may include a set of temperature sensors distributed across the memory system. The set of temperature sensors may be used to monitor or model the temperature of one or more sections of the memory system. Upon determining that the temperature of a section exceeds a threshold, the memory system may employ one or more mitigation techniques to reduce the temperature or the rate of change of the temperature of the section. For example, the memory system may reduce a clock frequency corresponding to the section, while maintaining separate clock frequencies for other sections of the memory system. Additionally or alternatively, the memory system may transfer data or other information from the section to a separate section.
Methods, systems, and devices for dividing blocks for special functions are described. Some memory systems may be configured to assign a block of the memory system as a special function block configured with a first portion for storing information associated with a first function of the memory system and a second portion for storing information associated with a second function of the memory system; write a first set of information to the first portion of the block based at least in part on assigning the block as the special function block, the first set of information associated with the first function of the memory system; and write a second set of information to the second portion of the block based at least in part on assigning the block as the special function block, the second set of information associated with the second function of the memory system.
Methods, systems, and devices for memory system logical unit number (LUN) procedures are described. A memory system may receive an indication to convert a LUN for storing LBAs associated with an application from a first type to a second type, where the second type is associated with a higher performance defragmentation process than the first type. The memory system may perform defragmentation on data associated with the LUN based on converting the LUN to the second type. The memory system may determine whether the LBAs stored in the LUN are ordered based on the defragmentation, and the memory system may operate (e.g., execute) the application based on the LBAs being ordered.
A microelectronic device, comprises a base structure comprising: active regions individually comprising semiconductor material; and isolation regions horizontally alternating with the active regions and individually comprising insulative material; epitaxial semiconductor material on the semiconductor material of one of the active regions, the epitaxial semiconductor material substantially confined within a horizontal area of the one of the active regions and offset from horizontal boundaries of two of the isolation regions horizontally neighboring the one of the active regions; gate dielectric material on the epitaxial semiconductor material, portions of the semiconductor material of the one of the active regions not covered by the epitaxial semiconductor material, and portions of the two of the isolation regions; and a gate electrode stack on the gate dielectric material.
A microelectronic device comprises a stack structure overlying a source tier. The stack structure comprises a vertically alternating sequence of conductive structures and insulative structures arranged in tiers. The microelectronic device comprises a staircase structure within the stack structure and having steps comprising lateral edges of the tiers, conductive contacts within a horizontal area of the staircase structure and vertically extending through the stack structure to the source tier, and strapping structures laterally adjacent to the conductive contacts and having upper surfaces substantially coplanar with upper surfaces of the conductive contacts. Each of the strapping structures are in contact with one of the conductive contacts and with one of the conductive structures of the stack structure at one of the steps of the staircase structure. Related memory devices, electronic systems, and methods of forming the microelectronic devices are also described.
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H01L 27/11519 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the top-view layout
H01L 27/11524 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the memory core region with cell select transistors, e.g. NAND
H01L 27/11551 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels
H01L 27/11565 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the top-view layout
H01L 27/1157 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the memory core region with cell select transistors, e.g. NAND
H01L 27/11578 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels
89.
MICROELECTRONIC DEVICE PACKAGES AND RELATED METHODS AND SYSTEMS
A microelectronic device package includes a microelectronic device, a masking material defined (MMD) contact, and a non-masking material defined (NMMD) contact. The microelectronic device is supported on, and electrically connected to, one of a package substrate and a redistribution layer. The MMD contact is located in a first region of the one of the package substrate and the redistribution layer and facilitates a first electrical connection between the microelectronic device and the one of the package substrate and the redistribution layer. The NMMD contact is located in a second, different region of the one of the package substrate and the redistribution layer and facilitates a second electrical connection between the microelectronic device and the one of the package substrate and the redistribution layer. Related methods and systems are also disclosed.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
90.
MICROELECTRONIC DEVICES INCLUDING CONTACT STRUCTURES, AND RELATED MEMORY DEVICES, ELECTRONIC SYSTEMS, AND METHODS
A microelectronic device comprises a stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers, the stack structure divided into block structures horizontally extending in parallel in a first direction and horizontally separated from one another in a second direction by dielectric slot structures. At least one of the block structures comprises a stadium structure comprising opposing staircase structures each having steps comprising edges of the tiers, and conductive contact structures vertically extending to and in contact with at least some of the conductive structures at the steps, the conductive contact structures positioned proximate horizontal boundaries of the stadium structure in the second direction. Related memory devices, electronic systems, and methods are also described.
H01L 23/528 - Layout of the interconnection structure
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/535 - Arrangements for conducting electric current within the device in operation from one component to another including internal interconnections, e.g. cross-under constructions
91.
METHODS OF FORMING MICROELECTRONIC DEVICES, AND RELATED MICROELECTRONIC DEVICES AND ELECTRONIC SYSTEMS
A microelectronic device is disclosed including a control logic structure that includes sense amplifiers clustered around sense amplifier exit regions; an upper memory array structure underlying the control logic structure and that includes memory cells coupled to some of the sense amplifiers of the control logic structure by way of routing extending through the sense amplifier exit regions; and a lower memory array structure underlying the upper memory array structure and that includes additional memory cells coupled to some other of the sense amplifiers of the control logic structure by way of additional routing extending through the sense amplifier exit regions.
Methods, systems, and devices for multi-host communications are described. In some examples, a memory system may be coupled with multiple host systems. The memory system may facilitate communications between the multiple host systems For example, a first host system may be coupled with a first buffer of the memory system and a second host system may be coupled with a second buffer of the memory system. The first host system may have read and write access to the first buffer and read access to the second buffer. In response to a write operation being initiated by the first host system, data may be written to the first buffer. The second host system may read the data written to the first buffer. The second host system may take an action or respond based on the data read from the first buffer.
Systems, apparatuses, and methods related to isolating virtual machines in a memory device are described. A memory apparatus includes a memory device and a controller coupled to the memory device, wherein the controller is configured to provide a plurality of Peripheral Component Interconnect express (PCIe) functions of the memory device and isolate access to each of the plurality of PCIe functions via respective passwords and digital signatures created from host keys.
Stacked semiconductor devices, and related systems and methods, are disclosed herein. In some embodiments, the stacked semiconductor device includes a package substrate and a die stack carried by the package substrate. The die stack can include at least a first semiconductor die carried by the package substrate, a second semiconductor die carried by the first semiconductor die. The first semiconductor die can have an upper surface and a first bond pad carried by the upper surface that includes a curvilinear concave depression formed in an uppermost surface of the first bond pad. The second semiconductor die has a lower surface and a second bond pad carried by the lower surface. The die stack can also include solder structure electrically coupling the first and second bond pads and at least partially filling the curvilinear concave depression formed in the uppermost surface of the first bond pad.
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
Methods, systems, and devices for a light hibernation mode for memory are described. A memory system may include volatile memory and non-volatile memory and may be configured to operate according to a first mode of operation (e.g., associated with relatively high power consumption), a light hibernation mode (e.g., a second mode associated with decreased power consumption in comparison to the first mode), and a full hibernation mode (e.g., a third mode of operation associated with decreased power consumption in comparison to the light hibernation mode). While operating according to the light hibernation mode, the memory system may maintain a greater quantity of data in the volatile memory relative to the full hibernation mode, which may avoid at least some power consumption related to data transfers between the volatile memory and non-volatile memory that may occur in connection with entering and exiting the full hibernation mode.
A method includes a liquid cooling manifold cooling a processor component of a system by liquid cooling a first cold plate coupled to the processor component, cooling a memory component of the system by liquid cooling the first cold plate coupled to the memory component, and a liquid cooling a drive component of the system by liquid cooling a second cold plate coupled to the drive component.
Arrays of memory cells including a data line, a common source, a conductive element between the data line and the common source, a first string of series-connected memory cells having a first segment of series-connected memory cells selectively connected to the conductive element and a second segment of series-connected memory cells selectively connected to the conductive element and selectively connected to its first segment of series-connected memory cells through the conductive element, and a second string of series-connected memory cells having a first segment of series-connected memory cells selectively connected to the conductive element and a second segment of series-connected memory cells selectively connected to the conductive element and selectively connected to its first segment of series-connected memory cells through the conductive element, as well as apparatus containing such arrays of memory cells and methods of their operation, and methods of their formation.
Methods, systems, and devices for thin film transistor random access memory are described. A memory device may include memory cells each having one or more transistors formed above a substrate. For example, a memory cell may include a transistor having a channel portion formed by one or more pillars or other structures formed above a substrate, and a gate portion including a conductor formed above the substrate and configured to activate the channel portion based at least in part on a voltage of the gate portion. A memory cell may include a set of two or more such transistors to support latching circuitry of the memory cell, or other circuitry configured to store a logic state, which may or may not be used in combination with one or more transistors formed at least in part from one or more portions of a substrate.
H10B 10/00 - Static random access memory [SRAM] devices
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
H01L 23/528 - Layout of the interconnection structure
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
The disclosed embodiments relate to per-process configuration caches in storage devices. A method is disclosed comprising initiating a new process, the new process associated with a process context; configuring a region in a memory device, the region associated with the process context, wherein the configuring comprises setting one or more cache parameters that modify operation of the memory device; and mapping the process context to the region of the memory device
Methods and apparatus for performing diversity matrix operations within a memory fabric. Various embodiments of the present disclosure are directed to converting a memory array into a matrix fabric for spatial diversity-related matrix transformations and performing matrix operations therein. Exemplary embodiments described herein perform MIMO-related matrix transformations (e.g., precoding, beamforming, or data recovery matrix operations) within a memory device that includes a matrix fabric and matrix multiplication unit (MMU). In one variant, the matrix fabric uses a “crossbar” construction of resistive elements. Each resistive element stores a level of impedance that represents the corresponding matrix coefficient value. The crossbar connectivity can be driven with an electrical signal representing the input vector as an analog voltage. The resulting signals can be converted from analog voltages to a digital values by an MMU to yield a matrix-vector product. The MMU may additionally perform various other logical operations within the digital domain.