Photonically steered impedance surface antennas are disclosed. A disclosed example apparatus includes a semiconductor substrate to be communicatively coupled to a radio frequency (RF) source, an at least partially transparent dielectric layer, the semiconductor substrate at a first side of the at least partially transparent dielectric layer, an at least partially transparent conductive film at a second side of the at least partially transparent dielectric layer that is opposite the first side of the at least partially transparent dielectric layer, and an illumination source to illuminate at least a portion of the semiconductor substrate to generate a photoinduced solid-state plasma pattern that beam steers an RF signal corresponding to the RF source.
H01Q 3/26 - Arrangements for changing or varying the orientation or the shape of the directional pattern of the waves radiated from an antenna or antenna system varying the distribution of energy across a radiating aperture
A method for authenticating features reported by a vehicle includes receiving, from a network, a map of an area with confidence weights corresponding to each feature on the map and/or a list of trusted users; upon the vehicle entering the area, checking whether the vehicle is on the list of trusted users; and checking features reported from the vehicle and matching the features to the map of the area.
H04W 4/46 - Services specially adapted for particular environments, situations or purposes for vehicles, e.g. vehicle-to-pedestrians [V2P] for vehicle-to-vehicle communication [V2V]
G08G 1/01 - Detecting movement of traffic to be counted or controlled
An apparatus and method to implement shared virtual memory in a trust zone. For example, one embodiment of a processor comprises: a plurality of cores; a memory controller coupled to the plurality of cores to establish a first private memory region in a system memory using a first key associated with a first trust domain of a first guest; an input/output memory management unit (IOMMU) coupled to the memory controller, the IOMMU to receive a memory access request by an input/output (IO) device, the memory access request comprising a first address space identifier and a guest virtual address (GVA), the IOMMU to access an entry in a first translation table using at least the first address space identifier to determine that the memory access request is directed to the first private memory region which is not directly accessible to the IOMMU, the IOMMU to generate an address translation request associated with the memory access request, wherein based on the address translation request, a virtual machine monitor (VMM) running on one or more of the plurality of cores is to initiate a secure transaction sequence with trust domain manager to cause a secure entry into the first trust domain to translate the GVA to a physical address based on the address space identifier, the IOMMU to receive the physical address from the VMM and to use the physical address to perform the requested memory access on behalf of the IO device.
An electronic device includes first and second external conductive pads coupled to route a first signal and third and fourth external conductive pads. The third and the fourth external conductive pads are between the first and the second external conductive pads on a surface of the electronic device.
Apparatuses, methods and storage medium for computing including determination of work placement on processor cores are disclosed herein. In embodiments, an apparatus may include one or more processors, devices, and/or circuitry to identify a favored core of the processor cores. The one or more processors, devices, and/or circuitry may be configured to determine whether to migrate a thread to or from the favored core. In some embodiments, the determination may be by a process executed by a driver and/or by an algorithm executed by a power control unit of the processor.
One embodiment provides a graphics processor comprising a set of processing resources configured to perform a supersampling anti-aliasing operation via a mixed precision convolutional neural network. The set of processing resources include circuitry configured to receive, at an input block of a neural network model, a set of data including previous frame data, current frame data, jitter offset data, and velocity data, pre-process the set of data to generate pre-processed data, provide pre-processed data to a feature extraction network of the neural network model and an output block of the neural network model, process the first pre-processed data at the feature extraction network via one or more encoder stages and one or more decoder stages, output tensor data from the feature extraction network to the output block, and generate an anti-aliased output frame via the output block based on the current frame data and the tensor data output from the feature extraction network.
Methods, systems, apparatus, and articles of manufacture to augment training data based on synthetic images are disclosed. An example apparatus disclosed herein includes programmable circuitry to generate, with one or more first layers of a generative adversarial network (GAN), a latent representation corresponding to a first image representative of a first racial domain, generate, with one or more second layers of the GAN, a second image based on the latent representation, the second image corresponding to a second racial domain different from the first racial domain, and augment a training dataset based on the second image.
Technologies for accelerated QUIC packet processing include a computing device having a network controller. The computing device programs the network controller with an encryption key associated with a QUIC protocol connection. The computing device may pass a QUIC packet to the network controller, which encrypts a payload of the QUIC packet using the encryption key. The network controller may segment the QUIC packet into multiple segmented QUIC packets before encryption. The network controller transmits encrypted QUIC packets to a remote host. The network controller may receive encrypted QUIC packets from a remote host. The network controller decrypts the encrypted payload of received QUIC packets and may evaluate an assignment function with an entropy source in the received QUIC packets and forward the received QUIC packets to a receive queue based on the assignment function. Each receive queue may be associated with a processor core. Other embodiments are described and claimed.
H04L 69/16 - Implementation or adaptation of Internet protocol [IP], of transmission control protocol [TCP] or of user datagram protocol [UDP]
H04L 69/164 - Adaptation or special uses of UDP protocol
H04L 69/321 - Interlayer communication protocols or service data unit [SDU] definitions; Interfaces between layers
H04L 69/324 - Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions in the data link layer [OSI layer 2], e.g. HDLC
9.
EXPANDED PUCCH TRANSMISSION BANDWIDTH FOR HIGH CARRIER FREQUENCY OPERATION
A user equipment (UE) configured for carrier frequency operations above 52.6 GHz may decode radio-resource control (RRC) signalling received from a gNodeB (gNB) to configure the UE with a number of resource blocks (RBs) (NRB) for a physical uplink control channel (PUCCH) resource for each of one or more enhanced PUCCH formats. The one or more enhanced PUCCH formats may include enhanced PUCCH format 0, enhanced PUCCH format 1 and enhanced PUCCH format 4. The number of RBs may be configurable to be more than one for the enhanced PUCCH format 0, the enhanced PUCCH format 1 and the enhanced PUCCH format 4. The UE may encode an enhanced PUCCH format for transmission in accordance with one of the enhanced PUCCH format 0, the enhanced PUCCH format 1 and the enhanced PUCCH format 4. The enhanced PUCCH format may be transmitted to occupy the number of RBs that are configured.
Systems, apparatuses and methods may provide for technology that detects a condition in which a plurality of atomic instructions target a common address and different bit positions in a mask, generates a combined read-lock request for the plurality of atomic instructions in response to the condition, and sends the combined read-lock request to a lock buffer coupled to a memory device associated with the common address.
Gate-all-around integrated circuit structures fabricated using alternate etch selective material, and the resulting structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is over the vertical arrangement of horizontal nanowires. A pair of dielectric spacers is along sides of the gate stack and over the vertical arrangement of horizontal nanowires. A metal oxide material is between adjacent ones of the vertical arrangement of horizontal nanowires at a location between the pair of dielectric spacers and the sides of the gate stack.
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
One or more non-transitory computer-readable media with instructions stored thereon, wherein the instructions are executable to cause one or more processor units to responsive to a data clear command issued by a tenant of a cloud service provider, issue a plurality of write commands to storage locations utilized by the tenant, the write commands to write a value based on an input provided by the tenant to the storage locations; and provide data read from at least a subset of the storage locations for attestation by the tenant of performance of the data clear command.
H04L 9/06 - Arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for blockwise coding, e.g. D.E.S. systems
13.
PACKAGE ARCHITECTURE WITH INTERCONNECT MIGRATION BARRIERS
Embodiments of a microelectronic assembly includes: a package substrate and an integrated circuit (IC) die coupled to a surface of the package substrate by first interconnects and second interconnects, the first interconnects and the second interconnects comprising solder. The first interconnects are larger than the second interconnects, the first interconnects and the second interconnects further comprise bumps on the IC die and bond-pads on the surface of the package substrate, with the solder coupled to the bumps and the bond-pads, lateral sides of the bumps have a coating of a material that prevents solder wicking, and the surface of the package substrate includes insulative baffles between the bond-pads.
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
14.
ELECTRONIC CIRCUITRY, SYSTEM, BASE STATION, MOBILE DEVICE AND METHOD
An electronic circuitry is proposed. The electronic circuitry comprises a directional coupler comprising a first port configured to receive an input signal from a signal source, a second port configured to output the input signal for transmission to a load, a third port configured to output a forward signal based on the input signal, and a fourth port configured to output a reverse signal based on a reflection of the input signal received at the second port. The electronic circuitry further comprises a Time-to-Digital converter, TDC, coupled to the third port and the fourth port. The TDC is configured to determine a phase difference between the forward signal and the reverse signal.
Methods, apparatus, and computer programs are disclosed for managing processor power consumption based on message queue utilization. In one embodiment, a method comprising: distributing messages to a set of processor cores of a processor, wherein one message is distributed per distribution round to one queue within a set of queues, each queue corresponding to one processor core within the set of processor cores and including one or more queue entries to be processed by the one processor core, and where the distribution is based on utilization of the set of queues; based on utilization of a corresponding queue for a processor core of the set of processor cores, determining a power state for the processor core to be changed to; and distributing a message to the corresponding queue, the message to cause the processor core to be set to the power state.
Contact over active gate (COAG) structures with conductive gate taps are described. In an example, an integrated circuit structure includes a plurality of gate structures above a substrate, each of the gate structures including a gate insulating layer thereon. Each of the plurality of gate structures includes a conductive tap structure protruding through the corresponding gate insulating layer. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a trench insulating layer thereon. An interlayer dielectric material is above the trench insulating layers and the gate insulating layers. An opening is in the interlayer dielectric material and exposes the conductive tap structure of one of the plurality of gate structures. A conductive structure is in the opening and is in direct contact with the conductive tap structure of one of the plurality of gate structures.
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
Systems, apparatus, articles of manufacture, and methods are disclosed to accelerate service execution. An example apparatus includes a system including first circuitry to initialize during a boot time period, and at least one of audio circuitry and networking circuitry to complete initialization and perform a service before expiration of the boot time period.
Examples described herein relate to utilizing a bus driver to present a peripheral device comprising a single physical function to a host operating system (OS) as a plurality of peripheral devices, associating the plurality of presented peripheral devices with a corresponding plurality of physical Ethernet ports; and enabling the host OS to interact with the plurality of peripheral devices. In some examples, the number of the plurality of peripheral devices correlates to the number of physical Ethernet ports associated with the peripheral device.
Methods and apparatuses relating to processing neural networks are described. In one embodiment, an apparatus to process a neural network includes a plurality of fully connected layer chips coupled by an interconnect; a plurality of convolutional layer chips each coupled by an interconnect to a respective fully connected layer chip of the plurality of fully connected layer chips and each of the plurality of fully connected layer chips and the plurality of convolutional layer chips including an interconnect to couple each of a forward propagation compute intensive tile, a back propagation compute intensive tile, and a weight gradient compute intensive tile of a column of compute intensive tiles between a first memory intensive tile and a second memory intensive tile.
The present disclosure relates to a signal generator including: a plurality of interpolators, each interpolator being configured to: receive a first input signal having a first phase, and a second input signal having a second phase; generate a plurality of interpolated signals based on a plurality of interpolations of the input signals, each interpolated signal having a respective phase based on the respective interpolation, and combine the interpolated signals to provide an output signal; the plurality of interpolators including: a first plurality of interpolators, each interpolator being configured to receive as input signals a first reference signal and a second reference signal; and a second plurality of interpolators, each interpolator being configured to receive as first input signal an output signal from an interpolator of the first plurality of interpolators and as second input signal another output signal from another interpolator of the first plurality of interpolators.
H03L 7/099 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
Embodiments are directed to providing integrity-protected command buffer execution. An embodiment of an apparatus includes a computer-readable memory comprising one or more command buffers and a processing device communicatively coupled to the computer-readable memory to read, from a command buffer of the computer-readable memory, a first command received from a host device, the first command executable by one or more processing elements on the processing device, the first command comprising an instruction and associated parameter data, compute a first authentication tag using a cryptographic key associated with the host device, the instruction and at least a portion of the parameter data, and authenticate the first command by comparing the first authentication tag with a second authentication tag computed by the host device and associated with the command.
H04L 9/32 - Arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system
This disclosure describes systems, methods, and devices related to sensing service coordination. A device may discover a Network Data Analytics Function (NWDAF) via a Network Function Repository Function (NRF). The device may send an Analytics request or subscribe to the selected NWDAF with a criteria based on a sensing data analytics ID, event ID, and event parameters. The device may select a Data Collection Coordination Function (DCCF) instance when DCCF is used for data collection, based on DCCF Serving Area Information. The device may receive sensing data or data analytics from the NWDAF after NWDAF has processed the data collected from DCCF.
Logic may parse an application function (AF) request from an AF, the AF request comprising a first set of parameters, the first set of parameters comprising a first geographical area and a sensing type. Logic may identify a radio access network (RAN) node based on the first geographical area. Logic may send a sensing request to the RAN node, the sensing request comprising a second set of parameters to identify sensing information, the second set of parameters comprising a second geographical area and a sensing type. Logic may receive a sensing result from the RAN node based on the second set of parameters. And logic may process the sensing result based on the AF request to determine a sensing report; and send, to the AF, the sensing report via the network interface.
The present disclosure provides various mechanisms to improve the communication of critical data, such as extended reality (XR) data, cloud gaming (CG) data, ultra-reliable low latency communications (URLLC) data, internet of things (IoT) data, and/or any other type of high priority data/traffic. The described mechanisms include enhancements to buffer status reporting mechanisms; packet, protocol data unit (PDU), and/or service data unit (SDU) discard mechanisms; mechanisms to resolve issues related to system frame number (SFN) wraparound; and network congestion detection mechanisms. Other embodiments may be described and/or claimed.
For example, a wireless communication device may be configured to determine a Concurrent Multiple Band (CMB) routing scheme based on Quality of Service (QoS) requirement information and network condition information, the CMB routing scheme to route a plurality of application streams to a plurality of radios of the wireless communication device for wireless communication over a plurality of wireless communication bands, the plurality of application streams corresponding to one or more applications to be executed by the wireless communication device; and to route the plurality of application streams to the plurality of radios by determining, based on the CMB routing scheme, to which radio of the plurality of radios to route the application stream of the plurality of application streams.
Methods, apparatus, systems, and articles of manufacture are disclosed to debug a hardware accelerator such as a neural network accelerator for executing Artificial Intelligence computational workloads. An example apparatus includes a core with a core input and a core output to execute executable code based on a machine-learning model to generate a data output based on a data input, and debug circuitry coupled to the core. The debug circuitry is configured to detect a breakpoint associated with the machine-learning model, compile executable code based on at least one of the machine-learning model or the breakpoint. In response to the triggering of the breakpoint, the debug circuitry is to stop the execution of the executable code and output data such as the data input, data output and the breakpoint for debugging the hardware accelerator.
An example apparatus to perform a convolution on an input tensor includes a parameters generator to: generate a horizontal hardware execution parameter for a horizontal dimension of the input tensor based on a kernel parameter and a layer parameter; and generate a vertical hardware execution parameter for a vertical dimension of the input tensor based on the kernel parameter and the layer parameter; an accelerator interface to configure a hardware accelerator circuitry based on the horizontal and vertical hardware execution parameters; a horizontal Iterator controller to determine when the hardware accelerator circuitry completes the first horizontal iteration of the convolution; and a vertical Iterator controller to determine when the hardware accelerator circuitry completes the first vertical iteration of the convolution.
Embodiments of apparatuses, methods, and systems for selective use of branch prediction hints are described. In an embodiment, an apparatus includes an instruction decoder and a branch predictor. The instruction decoder is to decode a branch instruction having a hint. The branch predictor is to provide a prediction and a hint-override indicator. The hint-override indicator is to indicate whether the prediction is based on stored information about the branch instruction. The prediction is to override the hint if the hint-override indicator indicates that the prediction is based on stored information about the branch instruction.
G06F 9/38 - Concurrent instruction execution, e.g. pipeline, look ahead
G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
G06F 12/0804 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
30.
METHODS AND APPARATUS FOR CONTAINER DEPLOYMENT IN A NETWORK-CONSTRAINED ENVIRONMENT
Systems, apparatus, articles of manufacture, and methods are disclosed for deployment of a container in a network-constrained environment. An example apparatus includes interface circuitry, machine readable instructions, and programmable circuitry to at least one of instantiate or execute the machine readable instructions to access a first unencrypted shared file, access a second encrypted file, create a third file by integrating contents of the first file and the second file, the third file being a Virtual Execution Environment (VEE) image, store the third file, and deploy the third file to a container runtime environment for execution.
Integrated circuit devices, methods, and circuitry for a digital signal processing (DSP) block that can selectively perform higher-precision DSP multiplication operations or lower-precision AI tensor multiplication operations. Flexible digital signal processing circuitry may include hardened multipliers, hardened summation circuitry, and an intermediate multiplexer network. The intermediate multiplexer network may be configurable to, in a first configuration, route data between the plurality of hardened multipliers and the hardened summation circuitry to perform a plurality of lower-precision multiplication operations. In a second configuration, the intermediate multiplexer network may route the data between the plurality of hardened multipliers and the hardened summation circuitry to perform at least one higher-precision multiplication operation.
G06F 7/544 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices for evaluating functions by calculation
G06F 30/34 - Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
32.
DEVICE AND METHODS FOR MANAGEMENT AND ACCESS OF DISTRIBUTED DATA SOURCES
A device and method for provided access to distributed data sources includes a cloud security server configured to associate any number of data sources and client devices with a cloud security server account. The cloud security server assigns trust levels to the data sources and the client devices. A client device requests data from the cloud security server. The cloud security server authenticates the client device and verifies the trust levels of the client device and the requested data. If verified, the cloud security server brokers a connection between the client device and the data source, and the client device accesses the requested data. Data sources may include cloud service providers and local storage devices. The cloud security server may assign a trust level to a client device for a limited time or revoke a trust level assigned to a client device. Other embodiments are described and claimed.
Methods, apparatus, systems and articles of manufacture are disclosed to map workloads. An example apparatus includes a constraint definer to define performance characteristic targets of the neural network, an action determiner to apply a first resource configuration to candidate resources corresponding to the neural network, a reward determiner to calculate a results metric based on (a) resource performance metrics and (b) the performance characteristic targets, and a layer map generator to generate a resource mapping file, the mapping file including respective resource assignments for respective corresponding layers of the neural network, the resource assignments selected based on the results metric.
Technologies for a field effect transistor (FET) with a ferroelectric gate dielectric are disclosed. In an illustrative embodiment, a perovskite stack is grown on a buffer layer as part of manufacturing a transistor. The perovskite stack includes one or more doped semiconductor layers alternating with other lattice-matched layers. Growing the doped semiconductor layers on lattice-matched layers can improve the quality of the doped semiconductor layers. The lattice-matched layers can be etched away, leaving the doped semiconductor layers as fins for a ribbon FET. A ferroelectric layer can be conformally grown on the fins, creating a high-quality ferroelectric layer above and below the fins. A gate can then be grown on the ferroelectric layer.
Methods, apparatus, and computer programs are disclosed for buffer management in load balancing. In one embodiment, a method is disclosed to comprise providing a set of buffers by a storage of a load balancer to store packets to be distributed by the load balancer, and distributing the packets by the load balancer to a set of cores of a computer processor to be processed by the set of cores. The method further comprises responsive to buffer utilization in the storage over a first threshold, obtaining by circuitry of the load balancer, from top of a memory stack coupled to the storage, additional buffers to store the packets to be distributed and responsive to buffer utilization in the storage below a second threshold, returning by the circuitry of the load balancer, available buffers in the storage to the top of the memory stack.
A memory device includes at least one bitcell coupled to a local bitline. The at least one bitcell includes multiple sets of a plurality of transistor devices. The first set of the plurality of transistor devices is configured to form a single write (1W) port for receiving digital data. The second set of the plurality of transistor devices is configured as an inverter pair. The inverter pair stores the digital data. The third set of the plurality of transistor devices is configured to form a single read (1R) port. The 1R port can be used to access the digital data stored at the inverter pair and output the digital data on the local bitline. The plurality of transistor devices includes an equal number of P-channel transistor devices and N-channel transistor devices.
Systems, apparatus, articles of manufacture, and methods are disclosed that include interface circuitry, machine readable instructions, and programmable circuitry to at least one of instantiate or execute the machine readable instructions to associate first datapoints of a first feature with a first node, associate second datapoints of a second feature with a second node, construct a graph from the first datapoints and the second datapoints, and perform a comparison of a graph accuracy with a baseline accuracy.
Embodiments of the invention describe semiconductor devices with high aspect ratio fins and methods for forming such devices. According to an embodiment, the semiconductor device comprises one or more nested fins and one or more isolated fins. According to an embodiment, a patterned hard mask comprising one or more isolated features and one or more nested features is formed with a hard mask etching process. A first substrate etching process forms isolated and nested fins in the substrate by transferring the pattern of the nested and isolated features of the hard mask into the substrate to a first depth. A second etching process is used to etch through the substrate to a second depth. According to embodiments of the invention, the first etching process utilizes an etching chemistry comprising HBr, O2 and CF4, and the second etching process utilizes an etching chemistry comprising Cl2, Ar, and CH4.
Examples include techniques for memory scrubbing associated with reliability, availability and serviceability (RAS) features. Examples include obtaining error correction code (ECC) encoded data stored in a physical memory unit maintained in a physical memory device in associated with a memory scrubbing operation. Examples include correcting detected errors in ECC encoded data and cause the corrected or scrubbed ECC encoded data to be stored in the physical memory unit. Examples include obtaining the scrubbed ECC encoded data from the physical memory unit and responsive to at least one detected error in the scrubbed ECC encoded data, trigger one or more RAS features.
Embodiments of a microelectronic assembly comprise: an interposer structure of glass, a substrate comprising organic dielectric material, the substrate coupled to a first side of the interposer structure; and a plurality of IC dies. A first IC die in the plurality of IC dies is coupled to the substrate by first interconnects, a second IC die in the plurality of IC dies is embedded in the organic dielectric material of the substrate, the second IC die is coupled to the first IC die by second interconnects, the second IC die is coupled to the first side of the interposer structure by third interconnects, and a third IC die in the plurality of IC dies is coupled to a second side of the interposer structure by fourth interconnects, the second side of the interposer structure being opposite the first side of the interposer structure.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
Embodiments herein relate to a photonic integrated circuit (PIC). The PIC may include a transmit module and a receive module. An optical port of the PIC may be coupled to the transmit module or the receive module. A semiconductor optical amplifier (SOA) may be positioned in a signal pathway between the optical port and the transmit module or the receive module. Other embodiments may be described and/or claimed.
G02B 6/12 - Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
H01S 5/026 - Monolithically integrated components, e.g. waveguides, monitoring photo-detectors or drivers
H01S 5/50 - Amplifier structures not provided for in groups
A computing system including two or more processing units shares virtual memory for a program between the two or more processing units. Each of the processing units may include memory management circuitry to manage a respective page table corresponding to the virtual memory. A first portion of the addresses of the virtual address space of the program are mapped to addresses of physical memory associated with a first one of the two or more processing units, while a second portion of the addresses of the virtual address space are mapped to addresses in physical memory associated with a second one of the two or more processing units.
A host device comprising first circuitry to receive one or more packets sent by a communication device over a serial communication interface between the communication device and the host device, wherein the one or more packets comprise media configuration information stored in a memory of the communication device and an indication of a mapping of the memory of the communication device; and second circuitry to transmit data packets over the serial communication interface after the host device has been configured based on the media configuration information.
Technologies for a high-voltage transmission gate are disclosed. In the illustrative embodiment, a companion chip is connected to a quantum processor. The companion chip provides voltages to gates of qubits on the quantum processor. The companion chip includes one or more high-voltage transmission gates that can be used to charge capacitors linked to gates of qubits on the quantum processor. The transmission gate includes transistors with a breakdown voltage less than a range of input and output voltages of the transmission gate. Control circuitry on the companion chip controls the voltages applied to transistors of the transmission gate to ensure that the voltage differences across the terminals of each transistor is below a breakdown voltage.
H03K 17/693 - Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors
G06N 10/40 - Physical realisations or architectures of quantum processors or components for manipulating qubits, e.g. qubit coupling or qubit control
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
09 - Scientific and electric apparatus and instruments
42 - Scientific, technological and industrial services, research and design
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installation of computer software; platform as a services (PaaS); software as a service (SaaS); Infrastructure as a Service (IaaS); application service provider (ASP); application programming interfaces (API); machine learning; artificial intelligence; enterprise services; enterprise software platforms; product research; consulting services; hosting content; technical support; consulting services in the field of design, selection, implementation and use of computer hardware and software systems for others; data conversion of computer programs and data, not physical conversion; platform as a service (PAAS) featuring computer software platforms for application development, machine instruction sequencing support and software development support; providing software as a service (SAAS) services featuring software for use in developing computer vision; providing software as a service (SAAS) services featuring software for training AI models for computer visions; platform as a services (PAAS) services featuring computer software that enables users to train and deploy deep-learning AI models; platform as a services (PAAS) services featuring computer software for use in training AI models for computer vision; providing temporary use of non-downloadable software featuring technology used to incorporate AI with other compatible products; providing temporary use of non-downloadable computer software for image processing; downloadable computer software used for document analysis, understanding, imaging, and recognition; Providing temporary use of non-downloadable computer software for data collection, data labeling, model selection and training, model optimization, and deployment; providing temporary use of non-downloadable computer software that enables users to create AI models; providing temporary use of non-downloadable computer software that allows users to train AI models for computer vision; providing temporary use of non-downloadable computer software, namely, software for image and signal processing, object detection and recognition, three-dimensional reconstruction, and motion analysis; providing temporary use of non-downloadable computer software for creating searchable databases of information and data on training AI models and incorporating AI models into compatible products; providing temporary use of non-downloadable software for use in designing and developing machine learning algorithms, deep neural networks, data analysis; providing cloud based computing services in the field of machine learning, artificial intelligence, learning algorithms and data analysis; cloud-based supercomputing featuring software for use in the fields of artificial intelligence, machine learning, deep learning, high performance computing, distributed computing, virtualization, statistical learning, and predictive analytics; Developing and managing application software for delivery of multi-media content, images, and data in the fields of artificial intelligence, machine learning, deep learning, high performance computing, distributed computing, virtualization, statistical learning, and predictive analytics; software platforms in the fields of infrastructure, virtualization, data center deployment, management, and reference architecture; software for creating, delivering, deploying, integrating and managing virtualized computer applications in the fields of communications, data security, system performance and monitoring, data center deployment, management, and reference architecture; Technical consulting services in the fields of datacenter architecture, public and private cloud computing solutions, and evaluation and implementation of internet technology and services; software for 3D visualization, 3D modeling and 3D rendering; electronic data storage; software as a services (SAAS) services featuring software development platform for use in connecting applications to enterprise systems and devices; services for providing a secure and trusted computing network; computer software service for providing computing capabilities for application developers and content providers; computer software service for providing cloud computing capabilities for application developers and content providers; computer services, namely, application programming interface (API), and software widget for machine learning, data mining, data query, and data analysis; scientific and technological services and research and design relating thereto; industrial analysis, industrial research and industrial design services; quality control and authentication services.
(1) Computers; computer hardware; integrated circuits; data processors; central processing units; printed circuit boards; computer firmware; cables and adapters; server access hardware; servers; circuit boards; accelerators; microcontrollers; processing units; computer software; computer software for computing; computer operating system software; computer software development kits; software libraries; enterprise software; downloadable computer software for connecting, operating, and managing internet of things (loT) enabled devices; downloadable and recorded vision software that uses artificial intelligence to see and interpret data, connect with hardware and store, manage and process data in the cloud; electronic control devices for the interface and control of computers and global computer and telecommunications networks with television and cable broadcasts and equipment; apparatus for recording, transmitting receiving and manipulating images and data; application programming interface (API) software for image rendering, image manipulation and processing; graphics software; hardware and software for streaming content, images, and data; software libraries for use in designing and developing machine learning algorithms and deep neural networks; software libraries for use in data analysis; downloadable software development kits (SDK); software for use in wireless infrastructure; wireless infrastructure equipment and accessories; software featuring technology that enables users to train and deploy deep learning AI models; downloadable software for use in training AI models for computer vision; artificial intelligence computers; downloadable computer software for database management, data storage and backup, data virtualization, networking, collaboration, remote access, remote support, cloud computing, data sharing, data security, access, administration and management of computer applications and computer hardware; computer hardware and software for computer application distribution, and for transmission of voice, data, images, audio, video, and information, and for content management, online project management, online conferences, meetings, demonstrations, tours, presentations and interactive communications; downloadable software and computer hardware for artificial intelligence, machine learning, deep learning, data mining, predictive analytics and business intelligence; computer hardware and software for an interface for facilitating interaction between humans and machines; computer software to optimize cloud based applications; computer software for network efficiency and network analytics; scientific, research, navigation, surveying, photographic, cinematographic, audiovisual, optical, weighing, measuring, signalling, detecting, testing, inspecting, life saving and teaching apparatus and instruments; apparatus and instruments for conducting, switching, transforming, accumulating, regulating or controlling the distribution or use of electricity (1) Computer services; computer programming; computer software consultancy; computer software design; computer system design; computer systems analysis; cloud computing; software development support; image processing software design; installation and maintenance of computer software; installation of computer software; platform as a services (PaaS); software as a service (SaaS); Infrastructure as a Service (IaaS); application service provider (ASP); application programming interfaces (API); machine learning; artificial intelligence; enterprise services; enterprise software platforms; product research; consulting services; hosting content; technical support; consulting services in the field of design, selection, implementation and use of computer hardware and software systems for others; data conversion of computer programs and data, not physical conversion; platform as a service (PAAS) featuring computer software platforms for application development, machine instruction sequencing support and software development support; providing software as a service (SAAS) services featuring software for use in developing computer vision; providing software as a service (SAAS) services featuring software for training AI models for computer visions; platform as a services (PAAS) services featuring computer software that enables users to train and deploy deep learning AI models; platform as a services (PAAS) services featuring computer software for use in training AI models for computer vision; providing temporary use of non downloadable software featuring technology used to incorporate AI with other compatible products; providing temporary use of non downloadable computer software for image processing; downloadable computer software used for document analysis, understanding, imaging, and recognition; Providing temporary use of non downloadable computer software for data collection, data labeling, model selection and training, model optimization, and deployment; providing temporary use of non downloadable computer software that enables users to create AI models; providing temporary use of non downloadable computer software that allows users to train AI models for computer vision; providing temporary use of non downloadable computer software, namely, software for image and signal processing, object detection and recognition, three dimensional reconstruction, and motion analysis; providing temporary use of non downloadable computer software for creating searchable databases of information and data on training AI models and incorporating AI models into compatible products; providing temporary use of non downloadable software for use in designing and developing machine learning algorithms, deep neural networks, data analysis; providing cloud based computing services in the field of machine learning, artificial intelligence, learning algorithms and data analysis; cloud based supercomputing featuring software for use in the fields of artificial intelligence, machine learning, deep learning, high performance computing, distributed computing, virtualization, statistical learning, and predictive analytics; Developing and managing application software for delivery of multi media content, images, and data in the fields of artificial intelligence, machine learning, deep learning, high performance computing, distributed computing, virtualization, statistical learning, and predictive analytics; software platforms in the fields of infrastructure, virtualization, data center deployment, management, and reference architecture; software for creating, delivering, deploying, integrating and managing virtualized computer applications in the fields of communications, data security, system performance and monitoring, data center deployment, management, and reference architecture; Technical consulting services in the fields of datacenter architecture, public and private cloud computing solutions, and evaluation and implementation of internet technology and services; software for 3D visualization, 3D modeling and 3D rendering; electronic data storage; software as a services (SAAS) services featuring software development platform for use in connecting applications to enterprise systems and devices; services for providing a secure and trusted computing network; computer software service for providing computing capabilities for application developers and content providers; computer software service for providing cloud computing capabilities for application developers and content providers; computer services, namely, application programming interface (API), and software widget for machine learning, data mining, data query, and data analysis; scientific and technological services and research and design relating thereto; industrial analysis, industrial research and industrial design services; quality control and authentication services
(1) Computers; computer hardware; integrated circuits; data processors; central processing units; printed circuit boards; computer firmware; cables and adapters; server access hardware; servers; circuit boards; accelerators; microcontrollers; processing units; computer software; computer software for computing; computer operating system software; computer software development kits; software libraries; enterprise software; downloadable computer software for connecting, operating, and managing internet of things (loT) enabled devices; downloadable and recorded vision software that uses artificial intelligence to see and interpret data, connect with hardware and store, manage and process data in the cloud; electronic control devices for the interface and control of computers and global computer and telecommunications networks with television and cable broadcasts and equipment; apparatus for recording, transmitting receiving and manipulating images and data; application programming interface (API) software for image rendering, image manipulation and processing; graphics software; hardware and software for streaming content, images, and data; software libraries for use in designing and developing machine learning algorithms and deep neural networks; software libraries for use in data analysis; downloadable software development kits (SDK); software for use in wireless infrastructure; wireless infrastructure equipment and accessories; software featuring technology that enables users to train and deploy deep learning AI models; downloadable software for use in training AI models for computer vision; artificial intelligence computers; downloadable computer software for database management, data storage and backup, data virtualization, networking, collaboration, remote access, remote support, cloud computing, data sharing, data security, access, administration and management of computer applications and computer hardware; computer hardware and software for computer application distribution, and for transmission of voice, data, images, audio, video, and information, and for content management, online project management, online conferences, meetings, demonstrations, tours, presentations and interactive communications; downloadable software and computer hardware for artificial intelligence, machine learning, deep learning, data mining, predictive analytics and business intelligence; computer hardware and software for an interface for facilitating interaction between humans and machines; computer software to optimize cloud based applications; computer software for network efficiency and network analytics; scientific, research, navigation, surveying, photographic, cinematographic, audiovisual, optical, weighing, measuring, signalling, detecting, testing, inspecting, life saving and teaching apparatus and instruments; apparatus and instruments for conducting, switching, transforming, accumulating, regulating or controlling the distribution or use of electricity (1) Computer services; computer programming; computer software consultancy; computer software design; computer system design; computer systems analysis; cloud computing; software development support; image processing software design; installation and maintenance of computer software; installation of computer software; platform as a services (PaaS); software as a service (SaaS); Infrastructure as a Service (IaaS); application service provider (ASP); application programming interfaces (API); machine learning; artificial intelligence; enterprise services; enterprise software platforms; product research; consulting services; hosting content; technical support; consulting services in the field of design, selection, implementation and use of computer hardware and software systems for others; data conversion of computer programs and data, not physical conversion; platform as a service (PAAS) featuring computer software platforms for application development, machine instruction sequencing support and software development support; providing software as a service (SAAS) services featuring software for use in developing computer vision; providing software as a service (SAAS) services featuring software for training AI models for computer visions; platform as a services (PAAS) services featuring computer software that enables users to train and deploy deep learning AI models; platform as a services (PAAS) services featuring computer software for use in training AI models for computer vision; providing temporary use of non downloadable software featuring technology used to incorporate AI with other compatible products; providing temporary use of non downloadable computer software for image processing; downloadable computer software used for document analysis, understanding, imaging, and recognition; Providing temporary use of non downloadable computer software for data collection, data labeling, model selection and training, model optimization, and deployment; providing temporary use of non downloadable computer software that enables users to create AI models; providing temporary use of non downloadable computer software that allows users to train AI models for computer vision; providing temporary use of non downloadable computer software, namely, software for image and signal processing, object detection and recognition, three dimensional reconstruction, and motion analysis; providing temporary use of non downloadable computer software for creating searchable databases of information and data on training AI models and incorporating AI models into compatible products; providing temporary use of non downloadable software for use in designing and developing machine learning algorithms, deep neural networks, data analysis; providing cloud based computing services in the field of machine learning, artificial intelligence, learning algorithms and data analysis; cloud based supercomputing featuring software for use in the fields of artificial intelligence, machine learning, deep learning, high performance computing, distributed computing, virtualization, statistical learning, and predictive analytics; Developing and managing application software for delivery of multi media content, images, and data in the fields of artificial intelligence, machine learning, deep learning, high performance computing, distributed computing, virtualization, statistical learning, and predictive analytics; software platforms in the fields of infrastructure, virtualization, data center deployment, management, and reference architecture; software for creating, delivering, deploying, integrating and managing virtualized computer applications in the fields of communications, data security, system performance and monitoring, data center deployment, management, and reference architecture; Technical consulting services in the fields of datacenter architecture, public and private cloud computing solutions, and evaluation and implementation of internet technology and services; software for 3D visualization, 3D modeling and 3D rendering; electronic data storage; software as a services (SAAS) services featuring software development platform for use in connecting applications to enterprise systems and devices; services for providing a secure and trusted computing network; computer software service for providing computing capabilities for application developers and content providers; computer software service for providing cloud computing capabilities for application developers and content providers; computer services, namely, application programming interface (API), and software widget for machine learning, data mining, data query, and data analysis; scientific and technological services and research and design relating thereto; industrial analysis, industrial research and industrial design services; quality control and authentication services
09 - Scientific and electric apparatus and instruments
42 - Scientific, technological and industrial services, research and design
Goods & Services
computers; computer hardware; integrated circuits; data processors; central processing units; printed circuit boards; computer firmware; cables and adapters; server access hardware; servers; circuit boards; accelerators; microcontrollers; processing units; computer software; computer software for computing; computer operating system software; computer software development kits; software libraries; enterprise software; downloadable computer software for connecting, operating, and managing internet of things (loT) enabled devices; downloadable and recorded vision software that uses artificial intelligence to see and interpret data, connect with hardware and store, manage and process data in the cloud; electronic control devices for the interface and control of computers and global computer and telecommunications networks with television and cable broadcasts and equipment; apparatus for recording, transmitting receiving and manipulating images and data; application programming interface (API) software for image rendering, image manipulation and processing; graphics software; hardware and software for streaming content, images, and data; software libraries for use in designing and developing machine learning algorithms and deep neural networks; software libraries for use in data analysis; downloadable software development kits (SDK); software for use in wireless infrastructure; wireless infrastructure equipment and accessories; software featuring technology that enables users to train and deploy deep-learning AI models; downloadable software for use in training AI models for computer vision; artificial intelligence computers; downloadable computer software for database management, data storage and backup, data virtualization, networking, collaboration, remote access, remote support, cloud computing, data sharing, data security, access, administration and management of computer applications and computer hardware; computer hardware and software for computer application distribution, and for transmission of voice, data, images, audio, video, and information, and for content management, online project management, online conferences, meetings, demonstrations, tours, presentations and interactive communications; downloadable software and computer hardware for artificial intelligence, machine learning, deep learning, data mining, predictive analytics and business intelligence; computer hardware and software for an interface for facilitating interaction between humans and machines; computer software to optimize cloud-based applications; computer software for network efficiency and network analytics; scientific, research, navigation, surveying, photographic, cinematographic, audiovisual, optical, weighing, measuring, signaling, detecting, testing, inspecting, life-saving and teaching apparatus and instruments; apparatus and instruments for conducting, switching, transforming, accumulating, regulating or controlling the distribution or use of electricity. computer services; computer programming; computer software consultancy; computer software design; computer system design; computer systems analysis; cloud computing; software development support; image processing software design; installation and maintenance of computer software; installation of computer software; platform as a services (PaaS); software as a service (SaaS); Infrastructure as a Service (IaaS); application service provider (ASP); application programming interfaces (API); machine learning; artificial intelligence; enterprise services; enterprise software platforms; product research; consulting services; hosting content; technical support; consulting services in the field of design, selection, implementation and use of computer hardware and software systems for others; data conversion of computer programs and data, not physical conversion; platform as a service (PAAS) featuring computer software platforms for application development, machine instruction sequencing support and software development support; providing software as a service (SAAS) services featuring software for use in developing computer vision; providing software as a service (SAAS) services featuring software for training AI models for computer visions; platform as a services (PAAS) services featuring computer software that enables users to train and deploy deep-learning AI models; platform as a services (PAAS) services featuring computer software for use in training AI models for computer vision; providing temporary use of non-downloadable software featuring technology used to incorporate AI with other compatible products; providing temporary use of non-downloadable computer software for image processing; downloadable computer software used for document analysis, understanding, imaging, and recognition; Providing temporary use of non-downloadable computer software for data collection, data labeling, model selection and training, model optimization, and deployment; providing temporary use of non-downloadable computer software that enables users to create AI models; providing temporary use of non-downloadable computer software that allows users to train AI models for computer vision; providing temporary use of non-downloadable computer software, namely, software for image and signal processing, object detection and recognition, three-dimensional reconstruction, and motion analysis; providing temporary use of non-downloadable computer software for creating searchable databases of information and data on training AI models and incorporating AI models into compatible products; providing temporary use of non-downloadable software for use in designing and developing machine learning algorithms, deep neural networks, data analysis; providing cloud based computing services in the field of machine learning, artificial intelligence, learning algorithms and data analysis; cloud-based supercomputing featuring software for use in the fields of artificial intelligence, machine learning, deep learning, high performance computing, distributed computing, virtualization, statistical learning, and predictive analytics; Developing and managing application software for delivery of multi-media content, images, and data in the fields of artificial intelligence, machine learning, deep learning, high performance computing, distributed computing, virtualization, statistical learning, and predictive analytics; software platforms in the fields of infrastructure, virtualization, data center deployment, management, and reference architecture; software for creating, delivering, deploying, integrating and managing virtualized computer applications in the fields of communications, data security, system performance and monitoring, data center deployment, management, and reference architecture; Technical consulting services in the fields of datacenter architecture, public and private cloud computing solutions, and evaluation and implementation of internet technology and services; software for 3D visualization, 3D modeling and 3D rendering; electronic data storage; software as a services (SAAS) services featuring software development platform for use in connecting applications to enterprise systems and devices; services for providing a secure and trusted computing network; computer software service for providing computing capabilities for application developers and content providers; computer software service for providing cloud computing capabilities for application developers and content providers; computer services, namely, application programming interface (API), and software widget for machine learning, data mining, data query, and data analysis; scientific and technological services and research and design relating thereto; industrial analysis, industrial research and industrial design services; quality control and authentication services.
09 - Scientific and electric apparatus and instruments
42 - Scientific, technological and industrial services, research and design
Goods & Services
computers; computer hardware; integrated circuits; data processors; central processing units; printed circuit boards; computer firmware; cables and adapters; server access hardware; servers; circuit boards; accelerators; microcontrollers; processing units; computer software; computer software for computing; computer operating system software; computer software development kits; software libraries; enterprise software; downloadable computer software for connecting, operating, and managing internet of things (loT) enabled devices; downloadable and recorded vision software that uses artificial intelligence to see and interpret data, connect with hardware and store, manage and process data in the cloud; electronic control devices for the interface and control of computers and global computer and telecommunications networks with television and cable broadcasts and equipment; apparatus for recording, transmitting receiving and manipulating images and data; application programming interface (API) software for image rendering, image manipulation and processing; graphics software; hardware and software for streaming content, images, and data; software libraries for use in designing and developing machine learning algorithms and deep neural networks; software libraries for use in data analysis; downloadable software development kits (SDK); software for use in wireless infrastructure; wireless infrastructure equipment and accessories; software featuring technology that enables users to train and deploy deep-learning AI models; downloadable software for use in training AI models for computer vision; artificial intelligence computers; downloadable computer software for database management, data storage and backup, data virtualization, networking, collaboration, remote access, remote support, cloud computing, data sharing, data security, access, administration and management of computer applications and computer hardware; computer hardware and software for computer application distribution, and for transmission of voice, data, images, audio, video, and information, and for content management, online project management, online conferences, meetings, demonstrations, tours, presentations and interactive communications; downloadable software and computer hardware for artificial intelligence, machine learning, deep learning, data mining, predictive analytics and business intelligence; computer hardware and software for an interface for facilitating interaction between humans and machines; computer software to optimize cloud-based applications; computer software for network efficiency and network analytics; scientific, research, navigation, surveying, photographic, cinematographic, audiovisual, optical, weighing, measuring, signalling, detecting, testing, inspecting, life-saving and teaching apparatus and instruments; apparatus and instruments for conducting, switching, transforming, accumulating, regulating or controlling the distribution or use of electricity computer services; computer programming; computer software consultancy; computer software design; computer system design; computer systems analysis; cloud computing; software development support; image processing software design; installation and maintenance of computer software; installation of computer software; platform as a services (PaaS); software as a service (SaaS); Infrastructure as a Service (IaaS); application service provider (ASP); application programming interfaces (API); machine learning; artificial intelligence; enterprise services; enterprise software platforms; product research; consulting services; hosting content; technical support; consulting services in the field of design, selection, implementation and use of computer hardware and software systems for others; data conversion of computer programs and data, not physical conversion; platform as a service (PAAS) featuring computer software platforms for application development, machine instruction sequencing support and software development support; providing software as a service (SAAS) services featuring software for use in developing computer vision; providing software as a service (SAAS) services featuring software for training AI models for computer visions; platform as a services (PAAS) services featuring computer software that enables users to train and deploy deep-learning AI models; platform as a services (PAAS) services featuring computer software for use in training AI models for computer vision; providing temporary use of non-downloadable software featuring technology used to incorporate AI with other compatible products; providing temporary use of non-downloadable computer software for image processing; downloadable computer software used for document analysis, understanding, imaging, and recognition; Providing temporary use of non- downloadable computer software for data collection, data labeling, model selection and training, model optimization, and deployment; providing temporary use of non-downloadable computer software that enables users to create AI models; providing temporary use of non-downloadable computer software that allows users to train AI models for computer vision; providing temporary use of non-downloadable computer software, namely, software for image and signal processing, object detection and recognition, three-dimensional reconstruction, and motion analysis; providing temporary use of non-downloadable computer software for creating searchable databases of information and data on training AI models and incorporating AI models into compatible products; providing temporary use of non-downloadable software for use in designing and developing machine learning algorithms, deep neural networks, data analysis; providing cloud based computing services in the field of machine learning, artificial intelligence, learning algorithms and data analysis; cloud-based supercomputing featuring software for use in the fields of artificial intelligence, machine learning, deep learning, high performance computing, distributed computing, virtualization, statistical learning, and predictive analytics; Developing and managing application software for delivery of multi-media content, images, and data in the fields of artificial intelligence, machine learning, deep learning, high performance computing, distributed computing, virtualization, statistical learning, and predictive analytics; software platforms in the fields of infrastructure, virtualization, data center deployment, management, and reference architecture; software for creating, delivering, deploying, integrating and managing virtualized computer applications in the fields of communications, data security, system performance and monitoring, data center deployment, management, and reference architecture; Technical consulting services in the fields of datacenter architecture, public and private cloud computing solutions, and evaluation and implementation of internet technology and services; software for 3D visualization, 3D modeling and 3D rendering; electronic data storage; software as a services (SAAS) services featuring software development platform for use in connecting applications to enterprise systems and devices; services for providing a secure and trusted computing network; computer software service for providing computing capabilities for application developers and content providers; computer software service for providing cloud computing capabilities for application developers and content providers; computer services, namely, application programming interface (API), and software widget for machine learning, data mining, data query, and data analysis; scientific and technological services and research and design relating thereto; industrial analysis, industrial research and industrial design services; quality control and authentication services
50.
HYBRID BONDING TECHNOLOGIES WITH THERMAL EXPANSION COMPENSATION STRUCTURES
Microelectronic integrated circuit package structures include a first substrate coupled to a second substrate by a conductive interconnect structure and a dielectric material adjacent to the conductive interconnect structure. A cavity in a surface of the first substrate is adjacent to the conductive interconnect structure. A portion of the dielectric material is within the cavity.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 23/13 - Mountings, e.g. non-detachable insulating substrates characterised by the shape
51.
DUAL SIDED EMBEDDED PASSIVES VIA PANEL LEVEL THERMAL COMPRESSION BONDING
An electronic device includes a substrate including a core layer; buildup layers on a first surface of the core layer, the buildup layers including first contact pads below the top surface of the buildup layers and second contact pads on a top surface of the buildup layers; and a discrete passive electronic component disposed in the buildup layers, the discrete component including bottom contact pads on a bottom surface of the discrete component and top contact pads on a top surface of the discrete component. The bottom contact pads of the discrete component are bonded to the first contacts pads of the buildup layers and the top contact pads of the discrete component are electrically connected to the second contact pads of the buildup layers.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
Embodiments herein relate to providing uniform servicing of workloads at a set of servers in a computer network. A platform determines and meets the performance requirements of a workload by scaling a performance capability of a group of processing units such as central processing units (CPUs) which are assigned to service the workload. This can involve increasing the power (P) state of one or more of the processing units to a highest P state in the group, so that every processing units in the group provides the same performance for a given workload. The platform can manage scaling of the processing units performance by reading a performance profile list which indicates minimum and maximum scaling points for programs that are executed to service the workload.
Methods, device structures, and wafer treatment chemistries related to backside wafer treatments to reduce distortions and overlay errors due to wafer deformation during wafer chucking are described. A backside layer is applied to the wafer prior to chucking. The chemistry of the backside layer lowers the surface free energy of the wafer during chucking to eliminate or mitigate wafer deformation during wafer processing.
Multi-die packages including at least one glass substrate within a space between two adjacent IC dies or surrounding an interconnect bridge die. The various IC dies may be placed within recesses formed in the glass substrate. The IC die and glass substrate, along with any conductive vias extending through the glass substrate may be planarized. The bridge die may be directly bonded or soldered to the adjacent IC dies, providing fine pitch interconnect. The opposite side of the adjacent IC dies and glass substrate may be attached to a host component or may be built up with package dielectric material. Metallization features formed on the second side of the glass substrate may electrically interconnect the IC dies to package interconnect interfaces that may be further coupled to a host with solder interconnects.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
H01L 23/13 - Mountings, e.g. non-detachable insulating substrates characterised by the shape
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different main groups of groups , or in a single subclass of , , e.g. forming hybrid circuits
55.
METHODS AND APPARATUS TO OPERATE CLOSED-LID PORTABLE COMPUTERS
Methods and apparatus to operate closed-lid portable computers are disclosed. An example portable computer includes a first display on a lid of the portable computer, the first display to be deactivated when the lid is in a closed position; a second display distinct from the first display, the second display to be visible when the lid is in the closed position; instructions; and processor circuitry to execute the instructions to cause activation of the first display in response to a user interaction with the second display while the lid is in the closed position.
An integrated circuit (IC) device comprises a substrate comprising a glass core. The glass core includes a first surface, a second surface opposite the first surface, a sidewall between the first surface and the second surface, and a corner region where the first sidewall meets the first surface. A first build-up layer is on at least the first surface. In some embodiments, the corner region comprises a recess and a dielectric material within the recess. In other embodiments, the corner region comprises a first compressive stress and the glass core comprises a second region. The second region comprises a second compressive stress. The first compressive stress is greater than the second compressive stress.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
H01L 23/13 - Mountings, e.g. non-detachable insulating substrates characterised by the shape
A memory device includes a group of ferroelectric capacitors with a shared plate that extends through the ferroelectric capacitors, has a greatest width between ferroelectric capacitors, and is coupled to an access transistor. The shared plate may be vertically between ferroelectric layers of the ferroelectric capacitors at the shared plate's greatest width. The memory device may include an integrated circuit die and be coupled to a power supply. Forming a group of ferroelectric capacitors includes forming an opening through an alternating stack of insulators and conductive plates, selectively forming ferroelectric material on the conductive plates rather than the insulators, and forming a shared plate in the opening over the ferroelectric material.
G11C 11/22 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
H01L 27/11507 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with ferroelectric memory capacitors characterised by the memory core region
Various embodiments disclosed relate to embedded components in glass core layers for semiconductor assemblies. The present disclosure includes a semiconductor assembly with a glass core having one or more cavities and a component embedded into the glass core at the one or more cavities portion, the component at least partially embedded in the glass core, and a semiconductor die attached to the substrate.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
An integrated circuit includes laterally adjacent first and second devices. The first device includes (i) first source and drain regions, (ii) a first body including semiconductor material laterally extending between the first source and drain regions, (iii) a first sub-fin below the first body, and (iv) a first gate structure on the first body. The second device includes (i) second source and drain regions, (ii) a second body including semiconductor material laterally extending from the second source and drain regions, (iii) a second sub-fin below the second body, and (iv) a second gate structure on the second body. A second dielectric material is laterally between the first and second sub-fins. A third dielectric material is laterally between the first and second sub-fins, and above the second dielectric material. A gate cut including first dielectric material is laterally between the first and second gate structures, and above the third dielectric material.
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
Materials and techniques for recessing heterogenous materials in integrated circuit (IC) dies. A first etch may reveal a surface at a desired depth, and a second etch may remove material laterally to reveal sidewalls down to the desired depth of the recess. The first etch may be a cyclical etch, and the second etch may be a continuous etch. The first and second etches may occur in a same chamber. The first and second etches may each be selective to materials with similarities. An IC die may have different, substantially coplanar materials at a recessed surface between and below sidewalls of another material. The recess may have squared profile. The recess may be over transistor structures.
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
Described herein is a technique to enable the construction of hierarchical clock gating architectures via e-graph rewriting. Automated clock gating relies on multiplexor (mux) tree analysis and constructs simple register enable signals. A framework is provided to detect non-mux based opportunities and construct more complex clock gating signals.
Techniques related to training and implementing convolutional neural networks for object recognition are discussed. Such techniques may include applying, at a first convolutional layer of the convolutional neural network, 3D filters of different spatial sizes to an 3D input image segment to generate multi-scale feature maps such that each feature map has a pathway to fully connected layers of the convolutional neural network, which generate object recognition data corresponding to the 3D input image segment.
G06N 3/084 - Backpropagation, e.g. using gradient descent
G06F 18/213 - Feature extraction, e.g. by transforming the feature space; Summarisation; Mappings, e.g. subspace methods
G06N 3/04 - Architecture, e.g. interconnection topology
G06V 10/44 - Local feature extraction by analysis of parts of the pattern, e.g. by detecting edges, contours, loops, corners, strokes or intersections; Connectivity analysis, e.g. of connected components
G06V 10/764 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using classification, e.g. of video objects
G06V 10/82 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using neural networks
G06V 20/56 - Context or environment of the image exterior to a vehicle by using sensors mounted on the vehicle
G06V 20/58 - Recognition of moving objects or obstacles, e.g. vehicles or pedestrians; Recognition of traffic objects, e.g. traffic signs, traffic lights or roads
Technologies for a field effect transistor (FET) with a ferroelectric gate dielectric are disclosed. In an illustrative embodiment, a perovskite stack is grown on a buffer layer as part of manufacturing a transistor. The perovskite stack includes one or more doped semiconductor layers alternating with other lattice-matched layers, such as undoped semiconductor layers. Growing the doped semiconductor layers on lattice-matched layers can improve the quality of the doped semiconductor layers. The lattice-matched layers can be preferentially etched away, leaving the doped semiconductor layers as fins for a ribbon FET. In another embodiment, an interlayer can be deposited on top of a semiconductor layer, and a ferroelectric layer can be deposited on the interlayer. The interlayer can bridge a gap in lattice parameters between the semiconductor layer and the ferroelectric layer.
H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/465 - Chemical or electrical treatment, e.g. electrolytic etching
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/24 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only inorganic semiconductor materials not provided for in groups , , or
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
Microelectronic integrated circuit package structures include a first substrate comprising a first bond plane structure on a surface of the first substrate, and a second substrate comprising a second bond plane structure on a surface of the second substrate, where the first and second bond plane structures are in direct physical contact. A conductive trace on the surface of the first substrate is adjacent to a bonding interface between the first and second bond plane structures and over a recessed surface of the first substrate. A first air gap is between the conductive trace and the recessed surface of the first substrate and a second air gap is between the conductive trace and the bonding interface.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for forming a plug within a metal layer of a semiconductor device, where the plug is formed within a cavity that is created through the metal layer. The plug may extend through the metal layer and into a layer below the metal layer, which may be a layer that includes a dielectric and one or more electrical routing features. The plug may include an electrical insulator material. The cavity may be formed by placing a mask above the metal layer and performing an etch through the metal layer subsequently filled with a dielectric, where the plug will be tapered and wider at the top of the plug and become narrower as the plug continues through the metal layer and reaches the layer below the metal layer. Other embodiments may be described and/or claimed.
H01L 23/528 - Layout of the interconnection structure
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
66.
Apparatus for providing a connection to a wide area network for voice calls, a power management circuit, and a method for providing a connection to a wide area network for voice calls
An apparatus for providing a connection to a wide area network for voice calls includes a wide area network circuit configured to transmit voice call data packets, a phone connection circuit configured to receive a voice call signal from a phone, a processor circuit configured to generate voice call data packets based on a voice call signal received by the phone connection circuit and a power management circuit configured to switch off at least a part of the apparatus to reach a power down mode of the apparatus, if a supply voltage drops below a supply voltage threshold.
In one example an apparatus comprises processing circuitry to measure a statistical distance between a marginal distribution of a coordinate of a potential signature (z) over a first interval and a uniform distribution over the first interval and use the statistical distance to determine one or more thresholds of a rejection sampling operation in a lattice-based digital signature algorithm. Other examples may be described.
H04L 9/32 - Arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system
68.
WALL COUPLED WITH TWO STACKS OF NANORIBBONS TO ELECTRICAL ISOLATE GATE METALS
Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for techniques for creating a wall within a forkFET transistor structure, where the wall is adjacent to a first stack of nanoribbons on a first side of the wall and a second stack of nanoribbons on a second side of the wall opposite the first side of the wall. In embodiments, the wall extends beyond the top of the first stack of nanoribbons and electrically isolates a first gate metal coupled with the first stack of nanoribbons and a second gate metal coupled with the second stack of nanoribbons from each other. Other embodiments may be described and/or claimed.
Technologies for a transistor with a thin-film ferroelectric gate dielectric are disclosed. In the illustrative embodiment, a transistor has a thin layer of scandium aluminum nitride (ScxAl1-xN) ferroelectric gate dielectric. The channel of the transistor may be, e.g., gallium nitride or molybdenum disulfide. In one embodiment, the ferroelectric polarization changes when voltage is applied and removed from a gate electrode, facilitating switching of the transistor at a lower applied voltage. In another embodiment, the ferroelectric polarization of a gate dielectric of a transistor changes when the voltage is past a positive threshold value or a negative threshold value. Such a transistor can be used as a one-transistor memory cell.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 29/24 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only inorganic semiconductor materials not provided for in groups , , or
A multi-link device (MLD) apparatus, including at least two transmission queues and first medium access control (MAC) circuitry and second MAC circuitry. The first MAC circuitry and the second MAC circuitry can transmit data of the at least two transmission queues over respective links responsive to receiving a trigger indicating that a transmission opportunity (TXOP) is available on the link corresponding to the respective first MAC circuitry and second MAC circuitry.
A user equipment (UE) configured for operation in a fifth-generation new radio (5G NR) system may be configured for multi physical downlink shared channel (PDSCH) scheduling and may decode a first downlink control information (DCI) and a second DCI received from a gNodeB (gNB). The first DCI may schedule multiple PDSCHs and the second DCI may schedule one or more PDSCHs. The UE may check the timing relations of the scheduled PDSCHs for validity when the first DCI and the second DCI end at a same symbol. When the multiple PDSCHs scheduled by the first DCI and the one or more PDSCHs scheduled by the second DCI are determined to have overlapping time spans, the UE may identify all the PDSCHs scheduled by the first DCI the second DCI as invalid.
H04W 72/1273 - Mapping of traffic onto schedule, e.g. scheduled allocation or multiplexing of flows of downlink data flows
H04L 1/1829 - Arrangements specially adapted for the receiver end
H04W 72/232 - Control channels or signalling for resource management in the downlink direction of a wireless link, i.e. towards a terminal the control data signalling from the physical layer, e.g. DCI signalling
72.
PROTECTED DATA ACCESSES USING REMOTE COPY OPERATIONS
Examples herein relate to an interface selectively providing access to a memory region for a work request from an entity by providing selective access to a physical address of the memory region and selective access to a cryptographic key for use by a memory controller to access the memory region. In some examples, providing selective access to a physical address conversion is based on one or more of: validation of a certificate received with the work request and an identifier of the entity being associated with a process with access to the memory region. Access to the memory region can be specified to be one or more of: create, read, update, delete, write, or notify. A memory region can be a page or sub-page sized region. Different access rights can be associated with different sub-portions of the memory region, wherein the access rights comprise one or more of: create, read, update, delete, write, or notify.
G06F 15/173 - Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star or snowflake
H04L 9/32 - Arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system
A network of matrix processing units (MPUs) is provided on a device, where each MPU is connected to at least one other MPU in the network, and each MPU is to perform matrix multiplication operations. Computer memory stores tensor data and a master control central processing unit (MCC) is provided on the device to receive an instruction from a host device, where the instruction includes one or more tensor operands based on the tensor data. The MCC invokes a set of operations on one or more of the MPUs based on the instruction, where the set of operations includes operations on the tensor operands. A result is generated from the set of operations, the result embodied as a tensor value.
Multiple-ferroelectric capacitor structures in memory devices, including in integrated circuit devices, and techniques for forming the structures. Insulators separating individual outer plates in a ferroelectric capacitor array are supported between wider portions of a shared, inner plate. Wider portions of an inner plate may be formed in lateral recesses between insulating layers. Ferroelectric material may be deposited over the inner plate between insulating layers after removing sacrificial layers. An etch-stop layer may protect the inner plate when sacrificial layers are removed. An etch-stop or interface layer may remain over the inner plate adjacent insulators.
H01L 27/11507 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with ferroelectric memory capacitors characterised by the memory core region
H01L 27/11514 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with ferroelectric memory capacitors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
75.
FABRICATION OF RECONFIGURABLE ARCHITECTURES USING FERROELECTRICS
An apparatus is provided which comprises: a plurality of logic blocks comprising transistors on a substrate, the logic blocks to implement logic functions; a plurality of input/output (I/O) blocks connecting the logic blocks with components external to the apparatus; a plurality of interconnect layers comprising wires and vias surrounded by interlayer dielectric above the substrate, the wires and vias conductively coupling the plurality of logic blocks and the plurality of I/O blocks; a plurality of programmable switches to configure connections between the plurality of logic blocks and the plurality of I/O blocks; and a ferroelectric material in a capacitor coupled to the gate or on the gate dielectric itself of one or more of the transistors. Other embodiments are also disclosed and claimed.
Integrated circuit structures having fin isolation regions recessed for gate contact are described. In an example, an integrated circuit structure includes a vertical stack of horizontal nanowires over a first sub-fin. A gate structure is over the vertical stack of horizontal nanowires and on the first sub-fin. A dielectric structure is laterally spaced apart from the gate structure. The dielectric structure is not over a channel structure but is on a second sub-fin. A dielectric gate cut plug is between the gate structure and the dielectric structure. A recess is in the dielectric structure and in the dielectric gate cut plug. A conductive structure is in the recess, the conductive structure in lateral contact with a gate electrode of the gate structure.
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
Embodiments detailed herein relate to matrix (tile) operations. For example, decode circuitry to decode an instruction having fields for an opcode and a memory address; and execution circuitry to execute the decoded instruction to set a tile configuration for the processor to utilize tiles in matrix operations based on a description retrieved from the memory address, wherein a tile a set of 2-dimensional registers are discussed.
A method for motion tracking is provided including receive first data, receive second data, transform the second data to generate transformed second data corresponding to the first frame; determine a first weighting factor for the first data and a second weighting factor for the transformed second data; weight the first data using the first weighting factor to generate first weighted data; weight the transformed second data using the second weighting factor to generate second weighted data; and combine the weighted first data and the weighted second data to generate combined image data. The first data include a first frame of a first scene of an environment detected by a camera or image sensor. The second data include a second frame of a second scene of an environment detected by a light detection and ranging (LIDAR) sensor. At least a subset of the second scene corresponds to the first scene.
This disclosure describes systems, methods, and devices related to enhanced low-density parity-check (LDPC) coding. A device may generate a frame comprising a data field, wherein the data field comprises a number of information bits. The device may calculate a required initial number of orthogonal frequency-division multiplexing (OFDM) symbols based on the number of information bits. The device may calculate an initial number of segments in a last OFDM symbol of the number of OFDM symbols. The device may calculate a number of data bits that can be filled within an initial number of OFDM symbols. The device may determine an LDPC codeword length based on the calculated number of data bits that can be filled. The device may cause to send the frame to one or more devices based on the LDPC codeword length.
Systems, apparatuses and methods may provide for technology that includes a capacitor ladder, a plurality of memory cells coupled to the capacitor ladder, the plurality of memory cells to control the capacitor ladder to conduct multi-bit multiply accumulate (MAC) operations during a computation phase, and a successive approximation register (SAR) coupled to the capacitor ladder, the SAR to control the capacitor ladder to digitize results of the multi-bit MAC operations during a digitization phase.
H03M 1/46 - Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
G11C 7/16 - Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters
An electronic device can include an interposer, a first porous polymer layer, and one or more die. The interposer can include a metallic through via extending from a first surface of the interposer to a second surface of the interposer. The first polymer layer can be adjacent to the first surface of the interposer. The one or more dies can be coupled to the first porous polymer layer and connected to the metallic through via.
B05D 3/02 - Pretreatment of surfaces to which liquids or other fluent materials are to be applied; After-treatment of applied coatings, e.g. intermediate treating of an applied coating preparatory to subsequent applications of liquids or other fluent materials by baking
B05D 3/04 - Pretreatment of surfaces to which liquids or other fluent materials are to be applied; After-treatment of applied coatings, e.g. intermediate treating of an applied coating preparatory to subsequent applications of liquids or other fluent materials by exposure to gases
B05D 5/00 - Processes for applying liquids or other fluent materials to surfaces to obtain special surface effects, finishes or structures
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
H01L 23/14 - Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
82.
TECHNOLOGIES FOR DYNAMICALLY MANAGING RESOURCES IN DISAGGREGATED ACCELERATORS
Technologies for dynamically managing resources in disaggregated accelerators include an accelerator. The accelerator includes acceleration circuitry with multiple logic portions, each capable of executing a different workload. Additionally, the accelerator includes communication circuitry to receive a workload to be executed by a logic portion of the accelerator and a dynamic resource allocation logic unit to identify a resource utilization threshold associated with one or more shared resources of the accelerator to be used by a logic portion in the execution of the workload, limit, as a function of the resource utilization threshold, the utilization of the one or more shared resources by the logic portion as the logic portion executes the workload, and subsequently adjust the resource utilization threshold as the workload is executed. Other embodiments are also described and claimed.
G06F 15/16 - Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
G06F 16/901 - Indexing; Data structures therefor; Storage structures
G08C 17/02 - Arrangements for transmitting signals characterised by the use of a wireless electrical link using a radio link
G11C 5/02 - Disposition of storage elements, e.g. in the form of a matrix array
G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
G11C 14/00 - Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
H03M 7/30 - Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
H03M 7/40 - Conversion to or from variable length codes, e.g. Shannon-Fano code, Huffman code, Morse code
H04B 10/25 - Arrangements specific to fibre transmission
H04L 43/0817 - Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters by checking availability by checking functioning
H04L 43/0876 - Network utilisation, e.g. volume of load or congestion level
Multi-die packages including a glass substrate within a space between adjacent IC dies. Two or more IC die may be placed within recesses formed in a glass substrate. The IC die and glass substrate, along with any conductive vias extending through the glass substrate may be planarized. Organic package dielectric material may then be built up on both sides of the IC dies and glass substrate. Metallization features formed within package dielectric material built up on a first side of the IC die may electrically interconnect the IC dies to package interconnect interfaces that may be further coupled to a host with solder interconnects. Metallization features formed within package dielectric material built up on a second side of the first and second IC dies may electrically interconnect the first IC die to the second IC die.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 21/52 - Mounting semiconductor bodies in containers
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
84.
HYBRID BONDED PASSIVE INTEGRATED DEVICES ON GLASS CORE
An electronic device includes a substrate including a glass core layer and first contact pads on a first surface of the glass core layer; one or more discrete passive electronic components disposed on the first surface of the glass core layer, the one or more discrete passive electronic components including second contact pads on a bottom surface of the one or more discrete passive electronic components; and hybrid bonds between the first contact pads of the glass core layer and the second contact pads of the one or more discrete passive electronic components.
H01F 41/00 - Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties
H01G 2/06 - Mountings specially adapted for mounting on a printed-circuit support
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different main groups of groups , or in a single subclass of , , e.g. forming hybrid circuits
85.
APPARATUS, SYSTEM, AND METHOD OF A MULTI-MODE POWER AMPLIFIER
For example, an apparatus may include an input to receive an input signal in a first voltage domain; a multi-mode power amplifier switchable between a plurality of power modes to generate an output signal based on the input signal; and an output to provide the output signal. For example, the multi-mode power amplifier may be configured to provide the output signal in the first voltage domain at a first power mode, and to provide the output signal in a second voltage domain at a second power mode. For example, a maximal voltage of the second voltage domain may be at least two times a maximal voltage of the first voltage domain.
Disclosed embodiments are related to beam management in cellular communication networks, and in particular, provide a new tranmission (Tx) beamforming indication based on the flexible Tx beam-forming assignment on the corresponding reference signal configured in a transmission configuration indicator (TCI) state for downlink (DL) or spatial relation information in the uplink (UL). The Tx beam-forming on the reference signal of the TCI state configured for the DL physical channel/reference signal can be updated based on reported Tx beam in the UL or using UL measurements from Sounding Reference Signal (SRS) transmission. Similarly, spatial relation information configuration used to indicate Tx beam-forming in the UL, may be also updated based on the reference signal measurements in DL or by suing Downlink Control Information (DCI) based beam indication in a scheduling request indicator (SRI). Other embodiments may be described and/or claimed.
For example, a phase shifter may include an input to receive an input clock signal having an input frequency and an input phase. For example, the phase shifter may include a quadrature phase-shift generator configured to generate a first signal and a second signal based on the input clock signal, the first and second signals having the input frequency, wherein a phase of the first signal is based on the input phase, wherein a phase of the second signal is shifted by a quadrature phase-shift relative to the phase of the first signal. For example, the phase shifter may include an output to provide an output based on the first signal and the second signal.
Techniques for prefetching by a hardware processor are described. In certain examples, a hardware processor includes execution circuitry, cache memories, and prefetcher circuitry. The execution circuitry is to execute instructions to access data at a memory address. The cache memories include a first cache memory at a first cache level and a second cache memory at a second cache level. The prefetcher circuitry is to prefetch the data from a system memory to at least one of the plurality of cache memories, and it includes a first-level prefetcher to prefetch the data to the first cache memory, a second-level prefetcher to prefetch the data to the second cache memory, and a plurality of prefetch filters. One of the prefetch filters is to filter exclusively for the first-level prefetcher. Another of the prefetch filters is to maintain a history of demand and prefetch accesses to pages in the system memory and to use the history to provide training information to the second-level prefetcher.
G06F 12/0862 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
G06F 9/345 - Addressing or accessing the instruction operand or the result of multiple operands or results
Disclosed herein are microelectronics package architectures utilizing in-situ high surface area capacitor in substrate packages and methods of manufacturing the same. The substrates may include an anode material, a cathode material, and a conductive material. The anode material may have an anode surface that may define a plurality of anode peaks and anode valleys. The cathode material may have a cathode surface that may define a plurality of cathode peaks and cathode valleys complementary to the plurality of anode peaks and anode valleys. The conductive material may be located at the anode peaks.
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different main groups of groups , or in a single subclass of , , e.g. forming hybrid circuits
90.
Apparatus, Device, Method and Computer Program for Generating Code using an LLM
Examples relate to an apparatus, device, method and computer program for generating code. The apparatus is to obtain information on an existing application architecture of a modular application, the information on the existing application architecture comprising, for components of the existing architecture, a formal description of the functionality and usage of the component of the existing architecture, obtain a prompt of a user for generating code for implementing an additional component for the modular application, the prompt comprising a textual description of a desired functionality of the additional component, provide the information on the existing application architecture and the prompt as input for a Large Language Model (LLM), obtain an output of the LLM, the output comprising a portion of the code for implementing the additional component, and provide the code for implementing the additional component based on the output of the LLM.
Detailed herein are examples of hybrid (heterogenous) performance monitoring unit enumeration. In some examples, a processor supports an instruction that enumerates performance monitoring unit enumeration. For example, the processor comprises decoder circuitry to decode an instance of a single instruction, the single instruction to include a field for an opcode; and execution circuitry to execute the decoded instruction according to the opcode to return the processor identification and feature information including an enumeration of heterogenous performance monitoring unit capabilities.
Examples include techniques to reduce power consumption for a distributed computational model mapped onto a multi-processing node system. Examples are described of processing nodes relaying indicator information to enable clock gate circuitry to determine whether or not to gate a clock to stall consuming compute circuitry based on availability of data to consume. Examples are also described of processing nodes relaying indicator information to enable clock gate circuitry to determine whether or not to gate a clock to stall producing compute circuitry based on available buffer capacity at a consuming compute circuitry.
An improved circuit for generating a crosstalk noise cancellation signal may be used for combining the crosstalk noise cancellation signal with a victim signal without a crosstalk cancelling capacitor. The improved crosstalk cancellation circuit may be used to provide improved TX crosstalk cancellation, and may be used to provide improved performance of increasingly higher speed memory systems regardless of memory process technology, enabling improvements to existing and future memory systems and other communication systems. The improved crosstalk cancellation circuit may include a transmission amplifier to receive a first digital signal and generate a first analog output signal, a crosstalk cancellation circuit to receive the second digital signal and generate an analog cancellation signal, and a first conductive node to generate a first crosstalk canceled signal by combining the first analog output signal with the analog cancellation signal.
The present disclosure relates to a method including providing a die including a cavity therein, wherein the die further may include a die fiducial on a top surface. The method further includes placing a lens structure in the cavity of the die, wherein the lens structure may include a lens fiducial on a front surface. The method also includes moving the lens structure in the cavity to a position until a lens fiducial image may be captured in an image processing system when the lens fiducial and the die fiducial coincide and lie in a plane orthogonal to the top surface of the die. A corresponding system is also disclosed herein.
Inverted pillar capacitors that have a U-shaped insulating layer are oriented with the U-shaped opening of the insulating layer opening toward the surface of the substrate on which the inverted pillar capacitors are formed. The bottom electrodes of adjacent inverted pillar capacitors are isolated from each other by the insulating layers of the adjacent electrodes and the top electrode that fills the volume between the electrodes. By avoiding the need to isolate adjacent bottom electrodes by an isolation dielectric region, inverted pillar capacitors can provide for a greater capacitor density relative to non-inverted pillar capacitors. The insulating layer in inverted pillar capacitors can comprise a ferroelectric material or an antiferroelectric material. The inverted pillar capacitor can be used in memory circuits (e.g., DRAMs) or non-memory applications.
G11C 11/22 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
H01L 27/108 - Dynamic random access memory structures
H01L 29/94 - Metal-insulator-semiconductors, e.g. MOS
96.
ENCRYPTED PROCESSING UNIT EMULATED WITH HOMOMORPHIC ENCRYPTION CIRCUITS
An apparatus comprises processing circuitry to implement an encrypted processing unit (EPU) client comprising a secure enclave, an encrypted processing unit (EPU) server comprising an encrypted processing unit (EPU) communicatively coupled to the secure enclave and at least one pseudo-clock generator, and a memory server communicatively coupled to the encrypted processing unit (EPU) client and to the encrypted processing unit (EPU) server, the memory server to manage a homomorphically encrypted memory.
H04L 9/00 - Arrangements for secret or secure communications; Network security protocols
G06F 21/72 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in cryptographic circuits
An apparatus to facilitate ordered thread dispatch for thread teams is disclosed. The apparatus includes one or more processors including a graphic processor, the graphics processor including a plurality of processing resources, and wherein the graphics processor is to: allocate a thread team local identifier (ID) for respective threads of a thread team comprising a plurality of hardware threads that are to be executed solely by a processing resource of the plurality of processing resources; and dispatch the respective threads together into the processing resource, the respective threads having the thread team local ID allocated.
Methods, apparatus, systems, and articles of manufacture are disclosed includes an integrated circuit (IC) package including a first die including a first surface and a second surface opposite the first surface, the first surface defined by a bulk semiconductor region of the first die, a second die including a third surface and a fourth surface opposite the third surface, the third surface defined by a bulk semiconductor region of the second die, the fourth surface facing towards the second surface, a first bonding layer between the second and fourth surfaces, the first bonding layer including first metal vias disposed therein, and a second bonding layer between the second and fourth surfaces, the second bonding layer including second metal vias disposed therein, the first bonding layer in direct contact with the second bonding layer, ones of the first metal vias in direct contact with ones of the second metal vias to electrically couple the first die to the second die.
H01L 25/10 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices having separate containers
H01L 21/66 - Testing or measuring during manufacture or treatment
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
99.
DEVICE, METHOD AND SYSTEM TO PROVIDE A RANDOM ACCESS MEMORY WITH A FERROELECTRIC RESISTIVE JUNCTION
Techniques and mechanisms for storing data with a memory cell which comprises a ferroelectric (FE) resistive junction. In an embodiment, a memory cell comprises a transistor and a FE resistive junction structure which is coupled to the transistor. The FE resistive junction structure comprises electrode structures, and a layer of a material which is between said electrode structures, wherein the material is a FE oxide or a FE semiconductor. The FE resistive junction structure selectively provides any of various levels of resistance, each to represent a respective one or more bits. A current flow through the FE resistive junction structure is characterized by thermionic emission through a Schottky barrier at an interface with one of the electrode structures. In another embodiment, the FE resistive junction structure further comprises one or more dielectric layers each between the layer of material and a different respective one of the electrode structures.
G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
G11C 11/22 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
The application relates to an apparatus and method used in Wireless Local Area Networks (WLANs). The apparatus includes: a Radio Frequency (RF) interface; and processor circuitry coupled with the RF interface and configured to: generate a transmission signal sequence by performing Cyclic Shift Diversity (CSD) operation and phase rotation on a base signal sequence; and provide the transmission signal sequence to the RF interface for transmitting in a duplicate transmission mode on different sub-channels.
