Intel Corporation

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1.

Systems And Methods For Coupling Integrated Circuit Dies

      
Application Number 18206840
Status Pending
Filing Date 2023-06-07
First Publication Date 2024-03-21
Owner Intel Corporation (USA)
Inventor
  • Hossain, Md Altaf
  • Kumashikar, Mahesh
  • Nalamalpu, Ankireddy

Abstract

A circuit system includes a support device having an interconnection conductor. The circuit system also includes first, second, and third integrated circuits that are mounted on the support device. The interconnection conductor couples the first integrated circuit to the third integrated circuit. The second integrated circuit is between the first integrated circuit and the third integrated circuit.

IPC Classes  ?

  • H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

2.

COMPACT AND WIDEBAND BEAM-SWITCHING ANTENNA ARRAY ARCHITECTURE

      
Application Number 17933331
Status Pending
Filing Date 2022-09-19
First Publication Date 2024-03-21
Owner Intel Corporation (USA)
Inventor
  • Hu, Kexin
  • Yang, Tae Young
  • Suh, Seong-Youp John
  • Skinner, Harry
  • Ravi, Ashoke
  • Degani, Ofir
  • Kronfeld, Ronen

Abstract

An antenna array architecture is provided for beamforming applications. The antenna array architecture facilitates a compact and wideband dual-polarized beam-switching antenna array architecture, which may be implemented in a cost-effective multi-layer PCB or package. The antenna array architecture is implemented as part of a package substrate having a number of layers. Each of the layers comprises various conductive elements such as conductive segments and/or traces that are disposed thereon in accordance with the respective antenna components.

IPC Classes  ?

  • H01Q 3/24 - Arrangements for changing or varying the orientation or the shape of the directional pattern of the waves radiated from an antenna or antenna system varying the orientation by switching energy from one active radiating element to another, e.g. for beam switching
  • H01Q 5/28 - Arrangements for establishing polarisation or beam width over two or more different wavebands
  • H01Q 5/385 - Two or more parasitic elements
  • H01Q 5/392 - Combination of fed elements with parasitic elements the parasitic elements having dual-band or multi-band characteristics

3.

HYBRID MANUFACTURING OF ACCESS TRANSISTORS FOR MEMORY

      
Application Number 17933589
Status Pending
Filing Date 2022-09-20
First Publication Date 2024-03-21
Owner Intel Corporation (USA)
Inventor
  • Sharma, Abhishek A.
  • Ghani, Tahir
  • Gomes, Wilfred
  • Murthy, Anand S.
  • Ranade, Pushkar Sharad
  • Suthram, Sagar

Abstract

Hybrid manufacturing of access transistors for memory, presented herein, explores how IC components fabricated by different manufacturers may be combined in an IC device to achieve advantages in terms of, e.g., performance, density, number of active memory layers, fabrication approaches, and so on. In one aspect, an IC device may include a support, a first circuit over a first portion of the support, a second circuit over a second portion of the support, a scribe line between the first circuit and the second circuit, and one or more electrical traces extending over the scribe line. In another aspect, an IC device may include a support, a memory array, comprising a first circuit over a first portion of the support and one or more layers of capacitors over the first circuit, and a second circuit over a second portion of the support.

IPC Classes  ?

  • H01L 27/108 - Dynamic random access memory structures
  • G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
  • G11C 5/10 - Arrangements for interconnecting storage elements electrically, e.g. by wiring for interconnecting capacitors
  • H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 27/11507 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with ferroelectric memory capacitors characterised by the memory core region
  • H01L 27/11509 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with ferroelectric memory capacitors characterised by the peripheral circuit region
  • H01L 27/11514 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with ferroelectric memory capacitors characterised by the three-dimensional arrangements, e.g. with cells on different height levels

4.

ASSYMMETRICAL DATA RATES FOR HIGH SPEED INTERCONNECTS

      
Application Number 18525289
Status Pending
Filing Date 2023-11-30
First Publication Date 2024-03-21
Owner Intel Corporation (USA)
Inventor
  • Dakshinamurthy, Sampath
  • Jadhav, Pooja
  • O.U., Neethumol
  • Seshan, Lakshmipriya

Abstract

Embodiments described herein may include apparatus, systems, techniques, or processes that are directed to semiconductor interconnects, such as on-package die-to-die (D2D) interconnects, for example. Specifically, embodiments herein may relate to on-package D2D interconnects for memory that use or relate to the Universal Chiplet Interconnect Express (UCIe) adapter or physical layer (PHY). Other embodiments are described and claimed.

IPC Classes  ?

  • G06F 13/42 - Bus transfer protocol, e.g. handshake; Synchronisation

5.

CAMERA REGISTRATION VIA ROBOT

      
Application Number 18254182
Status Pending
Filing Date 2020-12-25
First Publication Date 2024-03-21
Owner Intel Corporation (USA)
Inventor
  • Shi, Xuesong
  • Wang, Yujie
  • Wang, Zhigang
  • Wang, Peng
  • Watts, Robert

Abstract

The disclosure provides techniques for registering a camera into a map via a robot. A method for registering a camera into a map may include: collecting an observation of a calibration marker from an image captured by the camera, the calibration maker being attached to a robot capable of moving in a view of the camera; calculating, for the observation of the calibration marker, a transform T (camera, marker) between a camera frame of the camera and a marker frame of the calibration marker; obtaining, for the observation of the calibration marker, a transform T (world, robot) between a world frame of the map and a robot frame of the robot; and performing, when more than a predetermined number of observations of the calibration marker are collected during movement of the robot, a calibration process to calculate a transform T(world, camera) between the world frame and the camera frame based on the transform T (camera, marker) and the transform T(world, robot) for each observation of the calibration marker.

IPC Classes  ?

  • G06T 7/80 - Analysis of captured images to determine intrinsic or extrinsic camera parameters, i.e. camera calibration
  • G06T 7/33 - Determination of transform parameters for the alignment of images, i.e. image registration using feature-based methods
  • G06T 7/73 - Determining position or orientation of objects or cameras using feature-based methods

6.

TECHNOLOGIES FOR LOWER DEAD SPACE VAPOR CHAMBER

      
Application Number 18526948
Status Pending
Filing Date 2023-12-01
First Publication Date 2024-03-21
Owner Intel Corporation (USA)
Inventor
  • Srikanth, Ravishankar
  • R, Vijith Halestoph
  • Kurma Raju, Prakash
  • Sen, Arnab
  • Garg, Isha
  • Poulose, Ezekiel
  • Aravindan, Avinash Manu

Abstract

Techniques for a vapor chamber with less dead space are disclosed. In an illustrative embodiment, a vapor chamber is formed by folding a sheet and sealing the edges. The edges seal the vapor chamber but take up a relatively large amount of space without allowing for vapor to be transported in that space. The folded edge takes up less space, reducing the overall footprint of the vapor chamber. The vapor chamber with a smaller footprint can allow for, e.g., more space for motherboard area, more space for a battery, and/or a smaller form factor overall.

IPC Classes  ?

  • H05K 7/20 - Modifications to facilitate cooling, ventilating, or heating

7.

NETWORK CONTROLLED SMALL GAP (NCSG) OPERATIONS FOR NEW RADIO (NR)

      
Application Number 18267869
Status Pending
Filing Date 2021-12-21
First Publication Date 2024-03-21
Owner Intel Corporation (USA)
Inventor
  • Huang, Rui
  • Chervyakov, Andrey
  • Heo, Youn Hyoung
  • Li, Hua
  • Yiu, Candy

Abstract

In a fifth-generation (5G) new radio (NR) network, a generation node B (gNB) determines parameters for a Network Controlled Small Gap (NCSG) to reduce and/or eliminate interruptions at a user equipment (UE) for use when the UE is transitioning to a new target frequency for measurements or when the UE is switching or transiting between bandwidth parts (BWPs). The NCSG may be configured to align with one or more fundamental parameters of a legacy measurement gap (MG) pattern to reduce the interruptions.

IPC Classes  ?

8.

SCANDIUM PRECURSOR FOR SC2O3 OR SC2S3 ATOMIC LAYER DEPOSITION

      
Application Number 18522056
Status Pending
Filing Date 2023-11-28
First Publication Date 2024-03-21
Owner Intel Corporation (USA)
Inventor Romero, Patricio E.

Abstract

Described are precursor compounds and methods for atomic layer deposition of films containing scandium(III) oxide or scandium(III) sulfide. Such films may be utilized as dielectric layers in semiconductor manufacturing processes, particular for depositing dielectric films and the use of such films in various electronic devices.

IPC Classes  ?

  • C07F 5/00 - Compounds containing elements of Groups 3 or 13 of the Periodic System
  • C23C 16/30 - Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
  • C23C 16/40 - Oxides
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 29/51 - Insulating materials associated therewith

9.

SCALABLE I/O VIRTUALIZATION INTERRUPT AND SCHEDULING

      
Application Number 18459311
Status Pending
Filing Date 2023-08-31
First Publication Date 2024-03-21
Owner Intel Corporation (USA)
Inventor
  • Puffer, David
  • Shah, Ankur
  • Cooray, Niranjan
  • White, Bryan
  • Vembu, Balaji
  • Nalluri, Hema Chand
  • Bala, Kritika

Abstract

Embodiments described herein provide techniques to facilitate scalable interrupts and workload submission for a virtualized graphics processor. The techniques include memory-based interrupt reporting and shared work queue submission for multiple software domains.

IPC Classes  ?

  • G06F 13/24 - Handling requests for interconnection or transfer for access to input/output bus using interrupt
  • G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus

10.

INTEGRATED CIRCUIT STRUCTURES HAVING GATE CUT PLUG REMOVED FROM TRENCH CONTACT USING ANGLED DIRECTIONAL ETCH

      
Application Number 17949861
Status Pending
Filing Date 2022-09-21
First Publication Date 2024-03-21
Owner Intel Corporation (USA)
Inventor
  • Guler, Leonard P.
  • Alazizi, Ala
  • Chang, Tsuan-Chung

Abstract

Integrated circuit structures having gate cut plugs removed from trench contacts, and methods of fabricating integrated circuit structures having gate cut plugs removed from trench contacts, are described. For example, an integrated circuit structure includes a vertical stack of horizontal nanowires. A gate electrode is over the vertical stack of horizontal nanowires. A conductive trench contact is adjacent to the gate electrode. A dielectric sidewall spacer is between the gate electrode and the conductive trench contact. A gate cut plug extends through the gate electrode and the dielectric sidewall spacer. The gate cut plug extends to and is conformal with a side of the conductive trench contact.

IPC Classes  ?

  • H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/786 - Thin-film transistors

11.

TECHNOLOGIES FOR UNTRUSTED CODE EXECUTION WITH PROCESSOR SANDBOX SUPPORT

      
Application Number 18526279
Status Pending
Filing Date 2023-12-01
First Publication Date 2024-03-21
Owner Intel Corporation (USA)
Inventor
  • Zhang, Mingwei
  • Sun, Mingqiu
  • Sahita, Ravi L.
  • Zhang, Chunhui
  • Li, Xiaoning

Abstract

Technologies for untrusted code execution include a computing device having a processor with sandbox support. The computing device executes code included in a native domain in a non-privileged, native processor mode. The computing device may invoke a sandbox jump processor instruction during execution of the code in the native domain to enter a sandbox domain. The computing device executes code in the sandbox domain in a non-privileged, sandbox processor mode in response to invoking the sandbox jump instruction. While executing in the sandbox processor mode, the processor denies access to memory outside of the sandbox domain and may deny execution of one or more prohibited instructions. From the sandbox domain, the computing device may execute a sandbox exit instruction to exit the sandbox domain and resume execution in the native domain. The computing device may execute processor instructions to configure the sandbox domain. Other embodiments are described and claimed.

IPC Classes  ?

  • G06F 21/53 - Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems during program execution, e.g. stack integrity, buffer overflow or preventing unwanted data erasure by executing in a restricted environment, e.g. sandbox or secure virtual machine
  • G06F 8/41 - Compilation
  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline, look ahead
  • G06F 21/12 - Protecting executable software

12.

FERRORELECTRIC FIELD-EFFECT TRANSISTOR (FEFET) DEVICES WITH LOW OPERATING VOLTAGE CAPABILITIES

      
Application Number 17947071
Status Pending
Filing Date 2022-09-16
First Publication Date 2024-03-21
Owner Intel Corporation (USA)
Inventor
  • Debashis, Punyashloka
  • Steinhardt, Rachel A.
  • Holybee, Brandon
  • O'Brien, Kevin P.
  • Nikonov, Dmitri Evgenievich
  • Plombon, John J.
  • Young, Ian Alexander
  • Kim, Raseong
  • Rogan, Carly
  • Adams, Dominique A.
  • Sen Gupta, Arnab
  • Radosavljevic, Marko
  • Clendenning, Scott B.
  • Auluck, Gauri
  • Li, Hai
  • Metz, Matthew V.
  • Tronic, Tristan A.
  • Tung, I-Cheng

Abstract

In one embodiment, a transistor device includes a gate material layer on a substrate, a ferroelectric (FE) material layer on the gate material, a semiconductor channel material layer on the FE material layer, a first source/drain material on the FE material layer and adjacent the semiconductor channel material layer, and a second source/drain material on the FE material layer and adjacent the semiconductor channel material layer and on an opposite side of the semiconductor channel material layer from the first source/drain material. A first portion of the FE material layer is directly between the gate material and the first source/drain material, and a second portion of the FE material layer is directly between the gate material and the second source/drain material.

IPC Classes  ?

  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 29/51 - Insulating materials associated therewith

13.

MICROELECTRONIC ASSEMBLIES WITH MIXED COPPER AND SOLDER INTERCONNECTS HAVING DIFFERENT THICKNESSES

      
Application Number 17932624
Status Pending
Filing Date 2022-09-15
First Publication Date 2024-03-21
Owner Intel Corporation (USA)
Inventor
  • Tanaka, Hiroki
  • May, Robert Alan
  • Ozkan, Onur
  • Lehaf, Ali
  • Cho, Steve
  • Duan, Gang
  • Zhang, Jieping
  • Manepalli, Rahul N.
  • Mahajan, Ravindranath Vithal
  • Azimi, Hamid

Abstract

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a substrate having a surface including first conductive contacts and second conductive contacts, wherein the first conductive contacts have a first thickness and the second conductive contacts have a second thickness different than the first thickness; a first microelectronic component having third conductive contacts, wherein respective ones of the third conductive contacts are coupled to respective ones of the first conductive contacts by first interconnects, wherein the first interconnects include solder having a thickness between 2 microns and 35 microns; and a second microelectronic component having fourth conductive contact, wherein respective ones of the fourth conductive contacts are coupled to respective ones of the second conductive contacts by second interconnects, wherein the second interconnects include solder having a thickness between 5 microns and 50 microns.

IPC Classes  ?

  • H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
  • H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
  • H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

14.

Methods and Systems for Recursive Descent Parsing

      
Application Number 18516830
Status Pending
Filing Date 2023-11-21
First Publication Date 2024-03-21
Owner Secure Computing, LLC (USA)
Inventor
  • Heart, Karen
  • Rasin, Alexander

Abstract

Methods, systems, and devices for parsing text are described herein. A method of securing executable files is performed at a computing device having one or more processors and memory. The memory stories one or more programs configured for execution by the one or more processors. The computing device obtains source text that comprises a disassembled executable file and identifies, via a general parser module, the syntax of the source text by performing a recursive descent parsing of the source text. The device generates an abstract syntax tree (AST) for the source text based on the identified syntax and generates a transformed AST from the generated AST by replacing one or more system calls with respective protected system functions. The device also generates a secured executable file by assembling the transformed AST.

IPC Classes  ?

  • G06F 21/62 - Protecting access to data via a platform, e.g. using keys or access control rules

15.

DEVICE LAYER INTERCONNECTS

      
Application Number 18520872
Status Pending
Filing Date 2023-11-28
First Publication Date 2024-03-21
Owner Intel Corporation (USA)
Inventor
  • Bohr, Mark
  • Kobrinsky, Mauro J.
  • Nabors, Marni

Abstract

Described herein are integrated circuit (IC) structures, devices, and methods associated with device layer interconnects. For example, an IC die may include a device layer including a transistor array along a semiconductor fin, and a device layer interconnect in the transistor array, wherein the device layer interconnect is in electrical contact with multiple different source/drain regions of the transistor array.

IPC Classes  ?

  • H01L 23/528 - Layout of the interconnection structure
  • H01L 21/762 - Dielectric regions
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 21/8234 - MIS technology
  • H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
  • H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched

16.

NON-PLANAR INTEGRATED CIRCUIT STRUCTURES HAVING MITIGATED SOURCE OR DRAIN ETCH FROM REPLACEMENT GATE PROCESS

      
Application Number 18523637
Status Pending
Filing Date 2023-11-29
First Publication Date 2024-03-21
Owner Intel Corporation (USA)
Inventor
  • Kang, Jun Sung
  • Cheong, Kai Loon
  • Thompson, Erica J.
  • Guha, Biswajeet
  • Hsu, William
  • Crum, Dax M.
  • Ghani, Tahir
  • Beattie, Bruce

Abstract

Non-planar integrated circuit structures having mitigated source or drain etch from replacement gate process are described. For example, an integrated circuit structure includes a fin or nanowire. A gate stack is over the fin or nanowire. The gate stack includes a gate dielectric and a gate electrode. A first dielectric spacer is along a first side of the gate stack, and a second dielectric spacer is along a second side of the gate stack. The first and second dielectric spacers are over at least a portion of the fin or nanowire. An insulating material is vertically between and in contact with the portion of the fin or nanowire and the first and second dielectric spacers. A first epitaxial source or drain structure is at the first side of the gate stack, and a second epitaxial source or drain structure is at the second side of the gate stack.

IPC Classes  ?

  • H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
  • H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/161 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form including two or more of the elements provided for in group
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 29/51 - Insulating materials associated therewith
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

17.

FINGERPRINT-BASED vRAN CELL INTEGRITY MONITORING

      
Application Number 18514418
Status Pending
Filing Date 2023-11-20
First Publication Date 2024-03-21
Owner Intel Corporation (USA)
Inventor
  • Palermo, Stephen T.
  • Parker, Valerie J.
  • Gupta, Vishal
  • Connor, Patrick L.
  • Bross, Kevin W.

Abstract

Various approaches for the deployment and coordination of network operation processing, compute processing, and communications for 5G networks, including with the use of fingerprint-based vRAN cell integrity monitoring, are discussed. In an example, analyzing a state of a 5G network includes: obtaining initial fingerprint reference data of a network state between a virtualized radio access network (vRAN) node and at least one fingerprint reference unit (FRU) device wirelessly connected to the vRAN node; comparing the initial fingerprint reference data to subsequent fingerprint data of the network state between the vRAN node (e.g., operating as vRAN gNB, or as an IAB Donor or IAB Node) and the at least one FRU device to detect a changed network condition; and performing an action at the vRAN node to modify or disable a component of the 5G network, in response to detection of the changed network condition.

IPC Classes  ?

  • H04W 16/18 - Network planning tools
  • H04L 5/00 - Arrangements affording multiple use of the transmission path
  • H04W 40/22 - Communication route or path selection, e.g. power-based or shortest path routing using selective relaying for reaching a BTS [Base Transceiver Station] or an access point

18.

LICENSE MANAGEMENT FOR SOFTWARE DEFINED SILICON

      
Application Number 18474081
Status Pending
Filing Date 2023-09-25
First Publication Date 2024-03-21
Owner Intel Corporation (USA)
Inventor
  • Bartfai-Walcott, Katalin
  • Oriol, Mariusz
  • Srinivasan, Vasudevan
  • Irelan, Peggy
  • Stepka, Mariusz
  • Murphy, Kaitlin
  • Pillilli, Bharat
  • Baldwin, Mark
  • Bronk, Mateusz
  • Karim, Fariaz
  • Berent, Arkadiusz
  • Chilukuri, Vasuki

Abstract

Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to implement license management solutions for software defined silicon (SDSi) products are disclosed. Example license management solutions disclosed herein include, but are not limited to, virtual resource migration using SDSi, resource configuration management using SDSi, hardware self-configuration using SDSi, reduced footprint agents using SDSi, performing SDSi usage evaluation and corresponding license transfer responsive to detected and/or predicted failures, transferring node locked SDSi licenses, transfer of SDSi licenses without a trusted license server, community license generation, expirable SDSi licenses via a reliable clock, non-node locked licenses via blockchain, and activating hardware features with a pre-generated hardware license.

IPC Classes  ?

  • G06F 21/10 - Protecting distributed programs or content, e.g. vending or licensing of copyrighted material
  • G06F 9/455 - Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines

19.

60 GIGAHERTZ (GHZ) OPERATION WITH NEW LEGACY SIGNAL FIELD

      
Application Number 18521840
Status Pending
Filing Date 2023-11-28
First Publication Date 2024-03-21
Owner Intel Corporation (USA)
Inventor
  • Kenney, Thomas J.
  • Cariou, Laurent
  • Fang, Juan

Abstract

This disclosure describes systems, methods, and devices related to enhanced L-SIG. A device may generate a frame for 60 gigahertz (GHz) transmission, the frame comprising one or more fields to carry information associated with one or more station devices (STAs). The device may generate a special legacy signal (L-SIG) field comprising one or more subfields for operation in the 60 gigahertz (GHz) transmission. The device may include the L-SIG field in the frame. The device may cause to send the frame to the one or more STAs.

IPC Classes  ?

  • H04L 27/26 - Systems using multi-frequency codes
  • H04L 5/00 - Arrangements affording multiple use of the transmission path

20.

COOLING SYSTEMS WITH MAIN AND REMOTE COOLING MASSES HAVING INTEGRATED FLEXIBILITY

      
Application Number 18520425
Status Pending
Filing Date 2023-11-27
First Publication Date 2024-03-21
Owner Intel Corporation (USA)
Inventor
  • Geng, Phil
  • Shia, David
  • Miele, Ralph V.
  • Tan, Guixiang
  • Chuang, Jimmy
  • Ahuja, Sandeep
  • Saha, Sanjoy K.
  • Smalley, Jeffory L.
  • Sprenger, Mark E.

Abstract

An apparatus is described. The apparatus includes a semiconductor chip package, a main cooling mass, a heat pipe and a remote cooling mass. The apparatus further includes: a) a channel in one of the main and remote cooling masses into which the heat pipe is inserted, the channel being wide enough to allow movement of the heat pipe within the channel in response to relative movement of the main and remote cooling masses, wherein, the main cooling mass comprises a chamber with liquid, the heat pipe comprises a fluidic channel that is coupled to the chamber and vapor from the liquid is to be condensed within the heat pipe; b) a flexible region integrated into the heat pipe; and/or, c) a flexible connector into which the heat pipe is inserted.

IPC Classes  ?

  • H01L 23/427 - Cooling by change of state, e.g. use of heat pipes

21.

BASE PLUS OFFSET ADDRESSING FOR LOAD/STORE MESSAGES

      
Application Number 17949904
Status Pending
Filing Date 2022-09-21
First Publication Date 2024-03-21
Owner Intel Corporation (USA)
Inventor
  • Wiegert, John
  • Ray, Joydeep
  • Bauer, Timothy
  • Valerio, James

Abstract

Embodiments described herein provide a technique to decompose 64-bit per-lane virtual addresses to access a plurality of data elements on behalf of a multi-lane parallel processing execution resource of a graphics or compute accelerator. The 64-bit per-lane addresses are decomposed into a base address and a plurality of per-lane offsets for transmission to memory access circuitry. The memory access circuitry then combines the base address and the per-lane offsets to reconstruct the per-lane addresses.

IPC Classes  ?

  • G06F 15/78 - Architectures of general purpose stored program computers comprising a single central processing unit
  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode

22.

METHODS AND DEVICES FOR DETERMINATION OF AN UPDATE TIMESCALE FOR RADIO RESOURCE MANAGEMENT ALGORITHMS

      
Application Number 17948267
Status Pending
Filing Date 2022-09-20
First Publication Date 2024-03-21
Owner Intel Corporation (USA)
Inventor
  • Singh, Vaibhav
  • Maciocco, Christian
  • Metsch, Thijs
  • Srivastava, Amar

Abstract

A device may include a memory and a processor configured to obtain cell data representative of one or more attributes associated with a state of a cell of a mobile communication network, wherein radio resources of the cell are managed based on a radio resource management model, determine, for the radio resource management model, an update timescale based on the cell data, and communicate timescale information representative of the determined update timescale to the radio resource management model, wherein the timescale information is configured to cause the radio resource management model to update model parameters to manage the radio resources of the cell based on the determined update timescale.

IPC Classes  ?

  • H04W 28/16 - Central resource management; Negotiation of resources or communication parameters, e.g. negotiating bandwidth or QoS [Quality of Service]
  • H04W 16/22 - Traffic simulation tools or models
  • H04W 24/02 - Arrangements for optimising operational condition
  • H04W 48/16 - Discovering; Processing access restriction or access information

23.

USER-LEVEL EXCEPTION-BASED INVOCATION OF SOFTWARE INSTRUMENTATION HANDLERS

      
Application Number 17949353
Status Pending
Filing Date 2022-09-21
First Publication Date 2024-03-21
Owner Intel Corporation (USA)
Inventor
  • Lemay, Michael
  • Constable, Scott
  • Durham, David M.

Abstract

Techniques for improving exception-based invocation of instrumentation handler programs include executing, by a processor, an interrupt instruction of an instrumented program, the interrupt instruction having an interrupt number; searching for the interrupt number in an interrupt table; and in response to the interrupt number being found in the interrupt table, saving an address of a next instruction of the instrumented program after the interrupt instruction as a return address, determining a destination address, in an interrupt destination table, of a beginning of an instrumentation handler program associated with the interrupt number and transferring control of the instrumented program to the instrumentation handler program at the destination address.

IPC Classes  ?

  • G06F 9/48 - Program initiating; Program switching, e.g. by interrupt

24.

INTEGRATED CIRCUIT (IC) DEVICE WITH HYBRID METAL LAYER

      
Application Number 17933000
Status Pending
Filing Date 2022-09-16
First Publication Date 2024-03-21
Owner Intel Corporation (USA)
Inventor
  • Choi, June
  • Wallace, Charles Henry
  • Schenker, Richard E.
  • Mehta, Nikhil Jasvant

Abstract

An IC device includes a transistor, a first layer, and a second layer. The first layer is coupled to the transistors and is between the transistor and the second layer in a first direction. The first layer includes a first structure and a second structure. The first structure includes a first metal (e.g., Ru). The second structure includes a second metal (e.g., Cu). The second structure may be wrapped around by a different material that may include a third metal (e.g., Co). The first structure may be shorter than the second structure in the first direction and narrower than the second structure in a second direction orthogonal to the first direction. The first structure may be closer to the second layer than the second structure in the first direction. The first structure may be a wordline of a memory. The second structure may be a bitline.

IPC Classes  ?

  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 23/528 - Layout of the interconnection structure
  • H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials

25.

IC PACKAGE WITH LEDS

      
Application Number 17949857
Status Pending
Filing Date 2022-09-21
First Publication Date 2024-03-21
Owner Intel Corporation (USA)
Inventor
  • Marin, Brandon C.
  • Ahmed, Khaled
  • Pietambaram, Srinivas V.
  • Tanaka, Hiroki
  • West, Paul
  • Darmawikarta, Kristof
  • Duan, Gang
  • Ecton, Jeremy D.
  • Nad, Suddhasattwa

Abstract

Integrated circuit (IC) packages are disclosed. In some embodiments, an IC package includes a glass substrate, a micro light emitting diode (LED), a semiconductor die, one or more through glass vias (TGVs) and a package substrate. The micro LED is positioned over the glass substrate. The TGVs are integrated into the glass substrate and connect the micro LED to the semiconductor die. The semiconductor die is connected to the package substrate to receive external signals when connected to a motherboard.

IPC Classes  ?

  • H01L 33/48 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the semiconductor body packages
  • H01L 25/075 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 33/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof
  • H01L 33/32 - Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen
  • H01L 33/62 - Arrangements for conducting electric current to or from the semiconductor body, e.g. leadframe, wire-bond or solder balls

26.

TECHNOLOGIES FOR A PLUGGABLE OPTICAL CONNECTOR

      
Application Number 17949417
Status Pending
Filing Date 2022-09-21
First Publication Date 2024-03-21
Owner Intel Corporation (USA)
Inventor
  • Morgan, Wesley B.
  • Shia, David
  • Prabhugoud, Mohanraj
  • Moret, Eric J. M.
  • Tadayon, Pooya

Abstract

Technologies for pluggable optical connectors are disclosed. In the illustrative embodiment, an optical plug includes a ferrule with one or more optical fibers. The optical plug also includes a ferrule holder that holds the ferrule and a housing that encloses the ferrule and ferrule holder. The ferrule holder can move relative to the house, and the ferrule can move relative to the ferrule holder and the housing. As the optical plug is plugged into a socket, alignment features in the housing coarsely align the ferrule. Intermediate alignment features in the ferrule holder then engage, aligning the ferrule more precisely. As the optical plug is fully plugged in, fine alignment features in the ferrule engage, precisely aligning the ferrule and the optical fibers with the optical socket.

IPC Classes  ?

  • G02B 6/38 - Mechanical coupling means having fibre to fibre mating means

27.

THIN FILM CAPACITORS

      
Application Number 17948586
Status Pending
Filing Date 2022-09-20
First Publication Date 2024-03-21
Owner Intel Corporation (USA)
Inventor
  • Mohammadighaleni, Mahdi
  • Duong, Benjamin
  • Kaviani, Shayan
  • Stacey, Joshua
  • Ngan, Miranda
  • Seneviratne, Dilan
  • Heaton, Thomas
  • Pietambaram, Srinivas Venkata Ramanuja
  • Bryks, Whitney
  • Kong, Jieying

Abstract

An apparatus, system, and method for in-situ three-dimensional (3D) thin-film capacitor (TFC) are provided. A 3D TFC can include a glass core, a through glass via (TGV) in the glass core including first conductive material, the first conductive material forming a first electrode of the 3D MIM capacitor, a second conductive material acting as a second electrode of the 3D MIM capacitor, and a dielectric material in contact with the first and second conductive materials, the dielectric material extending vertically and horizontally and physically separating the first and second conductive materials.

IPC Classes  ?

  • H01G 4/33 - Thin- or thick-film capacitors
  • H01G 4/012 - Form of non-self-supporting electrodes

28.

CARRIER CHUCK AND METHODS OF FORMING AND USING THEREOF

      
Application Number 17949258
Status Pending
Filing Date 2022-09-21
First Publication Date 2024-03-21
Owner Intel Corporation (USA)
Inventor
  • Turan, Deniz
  • Kornbluth, Yosef
  • Li, Yonggang

Abstract

The present disclosure is directed to a carrier chuck having a base plate with a top surface, at least one electrode positioned in a first carrier region of the top surface and configured to produce an electrostatic force to retain a panel placed on the carrier chuck during panel processing, and a dielectric layer positioned over the at least one electrode. The at least one electrode extends from the top surface by a height of at least 20 um.

IPC Classes  ?

  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
  • H01L 21/677 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for conveying, e.g. between different work stations

29.

DRY FILM LAMINATION WITH DYNAMIC FEEDBACK CONTROL

      
Application Number 17949276
Status Pending
Filing Date 2022-09-21
First Publication Date 2024-03-21
Owner Intel Corporation (USA)
Inventor
  • Stacey, Joshua
  • Kornbluth, Yosef
  • Bryks, Whitney

Abstract

The present disclosure is directed to a position-controlled lamination tool or press that includes an array or plurality of pressure sensors and an array or plurality of heating/cooling elements or components, which may be coupled together, for preventing or reducing laminating film or material bleed out and improving thickness variation performance. The pressure sensors may provide a controller, which is coupled to the lamination tool, with real-time feedback on any thickness variations across a substrate panel and the controller may adjust the temperature output of the heating and cooling elements to locally modify the viscosity of the laminating material in one or more regions of the substrate panel to either decrease or increase the flowability of the laminating material.

IPC Classes  ?

  • B32B 41/00 - Arrangements for controlling or monitoring lamination processes; Safety arrangements
  • B32B 37/06 - Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding characterised by the heating method
  • B32B 37/08 - Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding characterised by the cooling method
  • B32B 37/10 - Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding characterised by the pressing technique, e.g. using direct action of vacuum or fluid pressure
  • H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups

30.

ANALOG-TO-DIGITAL CONVERTER, RECEIVER, BASE STATION, MOBILE DEVICE AND METHOD FOR A TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERTER

      
Application Number 17933512
Status Pending
Filing Date 2022-09-20
First Publication Date 2024-03-21
Owner Intel Corporation (USA)
Inventor
  • Kundu, Somnath
  • Whitcombe, Amy L.
  • Pellerano, Stefano
  • Sagazio, Peter
  • Carlton, Brent

Abstract

An analog-to-digital converter, ADC, is provided. The ADC comprises multiple time-interleaved sub-ADCs, a detection circuit, and a calibration circuit. The sub-ADCs are configured to, when the ADC is in a calibration mode, generate a first signal by sampling a calibration signal based on a first clock signal and at least a second clock signal. The first clock signal comprises a phase shift relative to the second clock signal. The calibration circuit is configured to determine a first mismatch between the phase shift and a phase shift threshold based on the first signal. The detection circuit is configured to, when the ADC is in an operation mode, generate a second signal by sampling one of a biased signal to be received by the sub-ADCs or a second calibration signal based on at least one of the first clock signal and the second clock signal. The calibration circuit is configured to determine a second mismatch between the phase shift and the phase shift threshold based on the second signal and calibrate the ADC based on the first and the second mismatch.

IPC Classes  ?

31.

DYNAMIC EXPLAINABLE ARTIFICIAL INTELLIGENCE PIPELINE COMPOSABILITY AND CUSTOMIZATION

      
Application Number US2023016946
Publication Number 2024/058823
Status In Force
Filing Date 2023-03-30
Publication Date 2024-03-21
Owner INTEL CORPORATION (USA)
Inventor
  • Cheruvu, Ria
  • Bajpai, Harsha
  • Mehmood, Arshad
  • Sharmin, Saima

Abstract

Various systems and methods are described for explainable artificial intelligence (Al) operations, workflows, and implementing systems are discussed. In an example, explainable Al operations are coordinated in a computing system, by: receiving a schema for the explainable Al operations, the schema corresponding to a persona role used to evaluate an Al model; coordinating or performing the explainable Al operations, the explainable Al operations including: data analysis on output data produced from the Al model, and model analysis on performance of the Al model; and outputting explanation data from the explainable Al operations, the explanation data customized based on the schema. The explanation data may include a variety of data metrics and values used for reports, deployment, and monitoring.

IPC Classes  ?

32.

NUMEROLOGY, FRAME STRUCTURE, AND SIGNAL RESOURCE DIMENSIONING FOR JOINT COMMUNICATION AND SENSING SYSTEMS

      
Application Number US2023032025
Publication Number 2024/058955
Status In Force
Filing Date 2023-09-06
Publication Date 2024-03-21
Owner INTEL CORPORATION (USA)
Inventor
  • Hamidi-Sepehr, Fatemeh
  • Hewavithana, Thushara
  • Chatterjee, Debdeep
  • Lehne, Mark
  • Li, Qian

Abstract

An apparatus and system are described for joint communication and sensing. A sensing frame structure design is described within the next generation cellular system frame and numerology, as are the use of Positioning Reference Signals (PRS) for sensing with various expansions and adaptations. Speed/ direction related measurements of a user equipment (UE) allow velocity estimation in localization/positioning. Specifics of sequence-based signal generation and initialization in which a Gold sequence is used are also described.

IPC Classes  ?

  • H04L 5/00 - Arrangements affording multiple use of the transmission path

33.

PROGRAMMING STATEMENTS IN EMBEDDED DOMAIN SPECIFIC LANGUAGE

      
Application Number CN2022119150
Publication Number 2024/055262
Status In Force
Filing Date 2022-09-15
Publication Date 2024-03-21
Owner INTEL CORPORATION (USA)
Inventor
  • Li, Zhibin
  • Ling, Liyang
  • Chen, Xinghong

Abstract

An apparatus for compiling code comprising programming statements in an embedded do-main specific language is configured to obtain code comprising a first set of programming statements in an embedded domain-specific programming language and a second set of pro-gramming statements in a second programming language, the first set of programming state-ments comprising one or more pre-defined programming statements encapsulating a block of programming statements. The apparatus is configured to compile the first set of programming statements to generate a first set of transformed programming statements according to an in-termediate representation, the encapsulated programming statements being represented as a function call to a function comprising transformed programming statements corresponding to the encapsulated programming statements. The apparatus is configured to compile the second set of programming statements, the first set of programming statements being represented by the first set of transformed programming statements during the compilation of the second set of programming statements.

IPC Classes  ?

34.

ACCELERATION OF COMMUNICATIONS

      
Application Number US2023030956
Publication Number 2024/058923
Status In Force
Filing Date 2023-08-23
Publication Date 2024-03-21
Owner INTEL CORPORATION (USA)
Inventor
  • Manohar, Rajit
  • Soule, Robert
  • Tsai, Jr-Shian
  • Chen, Edmund
  • Cummings, Uri V.
  • Bressana, Pietro
  • Li, Rui

Abstract

Examples described herein relate to a network interface device that includes packet processing circuitry and circuitry. In some examples, the circuitry is to execute a first process of partitioned processes to provide a remote procedure call (RPC) interface for a second process. In some examples, the second process of the partitioned processes includes a business logic. In some examples, the partitioned processes comprise resource and deployment definition are based on an Interface Description Language (IDL) and a memory allocation.

IPC Classes  ?

35.

WIRELESS TECHNOLOGIES FOR HEALTH MONITORING

      
Application Number 17943394
Status Pending
Filing Date 2022-09-13
First Publication Date 2024-03-14
Owner INTEL CORPORATION (USA)
Inventor
  • El Hajj, Walid
  • Shababo, Elad

Abstract

An apparatus can include an antenna, transmitter circuitry coupled to the antenna, and processing circuitry coupled to the transmitter circuitry. The processing circuitry can measure a first reflection coefficient of the antenna in free space and a second reflection coefficient of the antenna when the antenna is proximate biological tissues. The processing circuitry can determine a contextual property of the biological tissues based on a comparison between the first coefficient and the reflection coefficient proximate biological tissues.

IPC Classes  ?

  • A61B 5/05 - Detecting, measuring or recording for diagnosis by means of electric currents or magnetic fields; Measuring using microwaves or radio waves
  • A61B 5/00 - Measuring for diagnostic purposes ; Identification of persons
  • A61B 5/145 - Measuring characteristics of blood in vivo, e.g. gas concentration, pH-value
  • G08B 21/18 - Status alarms

36.

CODING SCHEME INDICATION FOR 802.11BN

      
Application Number 18382346
Status Pending
Filing Date 2023-10-20
First Publication Date 2024-03-14
Owner INTEL CORPORATION (USA)
Inventor
  • Li, Qinghua
  • Fang, Juan
  • Song, Hao
  • Kenney, Thomas J.
  • Stacey, Robert J.

Abstract

An apparatus and method of signaling coding type is disclosed. The coding types include binary convolutional coding (BCC), legacy lifted Low-Density Parity Check (LDPC) code, and lifted LDPC code having a length that is a multiple of the maximum legacy LDPC code. The number of bits used to indicate the coding type in a User Info field depends on whether multiple lifted LDPC codes are available for encoding, whether the lifted LDPC code is an optional coding type, or a payload size. The frame containing the User Info field is transmitted to another STA and the response contains a payload encoded using the indicated coding type.

IPC Classes  ?

  • H04L 1/00 - Arrangements for detecting or preventing errors in the information received
  • H03M 13/25 - Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]

37.

ADAPTIVE FABRIC ALLOCATION FOR LOCAL AND REMOTE EMERGING MEMORIES BASED PREDICTION SCHEMES

      
Application Number 18371513
Status Pending
Filing Date 2023-09-22
First Publication Date 2024-03-14
Owner Intel Corporation (USA)
Inventor
  • Graniello, Benjamin
  • Bernat, Francesc Guim
  • Kumar, Karthik
  • Willhalm, Thomas

Abstract

Methods, apparatus and systems for adaptive fabric allocation for local and remote emerging memories-based prediction schemes. In conjunction with performing memory transfers between a compute host and memory device connected via one or more interconnect segments, memory read and write traffic is monitored for at least one interconnect segment having reconfigurable upstream lanes and downstream lanes. Predictions of expected read and write bandwidths for the at least one interconnect segment are then made. Based on the expected read and write bandwidths, the upstream lanes and downstream lanes are dynamically reconfigured. The interconnect segments include interconnect links such as Compute Exchange Link (CXL) flex buses and memory channels for local memory implementations, and fabric links for remote memory implementations. For local memory, management messages may be used to provide telemetry information containing the expected read and write bandwidths. For remote memory, telemetry information is provided to a fabric management component that is used to dynamically reconfigure one or more fabric links.

IPC Classes  ?

  • G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
  • G06F 3/06 - Digital input from, or digital output to, record carriers
  • G06F 9/50 - Allocation of resources, e.g. of the central processing unit [CPU]
  • G06F 11/30 - Monitoring
  • G06F 12/02 - Addressing or allocation; Relocation
  • G06F 15/78 - Architectures of general purpose stored program computers comprising a single central processing unit

38.

OFFLOAD COMPUTING PROTOCOL

      
Application Number 18371881
Status Pending
Filing Date 2023-09-22
First Publication Date 2024-03-14
Owner Intel Corporation (USA)
Inventor
  • O'Hare, Fearghal
  • Nolan, Michael
  • O'Neill, James A.

Abstract

Systems and methods for are provided for offloading computing tasks from constrained devices. An example apparatus includes an offload computing protocol (OCP) enabled device. The OCP enabled device includes OCP extensions to the operating system to enable the offloading of computing tasks. A proximity locator may use a radio transceiver to locate an OCP device that can accept a computing task. The OCP enabled device may include an OCP bundle comprising code and data, wherein the OCP bundle is to be sent to the OCP device.

IPC Classes  ?

  • G06F 9/50 - Allocation of resources, e.g. of the central processing unit [CPU]
  • H04L 67/00 - Network arrangements or protocols for supporting network services or applications
  • H04L 67/10 - Protocols in which an application is distributed across nodes in the network
  • H04L 67/1001 - Protocols in which an application is distributed across nodes in the network for accessing one among a plurality of replicated servers

39.

INSTRUCTION PREFETCH MECHANISM

      
Application Number 18470553
Status Pending
Filing Date 2023-09-20
First Publication Date 2024-03-14
Owner Intel Corporation (USA)
Inventor
  • Porpodas, Vasileios
  • Lueh, Guei-Yuan
  • Maiyuran, Subramaniam
  • Chen, Wei-Yu

Abstract

An apparatus to facilitate data prefetching is disclosed. The apparatus includes a cache, one or more execution units (EUs) to execute program code, prefetch logic to maintain tracking information of memory instructions in the program code that trigger a cache miss and compiler logic to receive the tracking information, insert one or more pre-fetch instructions in updated program code to prefetch data from a memory for execution of one or more of the memory instructions that triggered a cache miss and download the updated program code for execution by the one or more EUs.

IPC Classes  ?

  • G06F 12/0862 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
  • G06F 8/41 - Compilation
  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
  • G06F 12/0875 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack

40.

NEURAL NETWORK SCHEDULING MECHANISM

      
Application Number 18471843
Status Pending
Filing Date 2023-09-21
First Publication Date 2024-03-14
Owner Intel Corporation (USA)
Inventor
  • Ma, Liwei
  • Satish, Nadathur Rajagopalan
  • Bottleson, Jeremy
  • Akhbari, Farshad
  • Nurvitadhi, Eriko
  • Sakthivel, Chandrasekaran
  • Lakshmanan, Barath
  • Jin, Jingyi
  • Gottschlich, Justin E.
  • Strickland, Michael

Abstract

An apparatus to facilitate workload scheduling is disclosed. The apparatus includes one or more clients, one or more processing units to processes workloads received from the one or more clients, including hardware resources and scheduling logic to schedule direct access of the hardware resources to the one or more clients to process the workloads.

IPC Classes  ?

  • G06N 3/044 - Recurrent networks, e.g. Hopfield networks
  • G06F 9/50 - Allocation of resources, e.g. of the central processing unit [CPU]
  • G06N 3/045 - Combinations of networks
  • G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
  • G06N 3/084 - Backpropagation, e.g. using gradient descent

41.

DETERMINING TRANSLATION SCALE IN A MULTI-CAMERA DYNAMIC CALIBRATION SYSTEM

      
Application Number 18507593
Status Pending
Filing Date 2023-11-13
First Publication Date 2024-03-14
Owner Intel Corporation (USA)
Inventor Kumar, Avinash

Abstract

Multi-camera dynamic calibration can be performed using three or more images, each from a separate camera viewing the same 3D scene. Multi-camera translation magnitude can be determined by incorporating information from an additional image. A relative translation scale is determined for a configuration of three cameras using a ratio of translation magnitudes. The translation scale can be expanded to configurations having more than three cameras using the relative scale of the pair-wise camera translations to determine translation scales for a multi-camera set-up. If the ground-truth translation is known for a pair of cameras, then the translation magnitude can be determined for all pairs of cameras to ground-truth accuracy. Multi-camera scale estimation is divided into smaller overlapping triplet-camera scale estimation, and the translation scale determination corresponding to each image pair is applied iteratively to overlapping sets of three images. The estimates can be merged by linearly aligning overlapping sets of estimates.

IPC Classes  ?

  • H04N 23/695 - Control of camera direction for changing a field of view, e.g. pan, tilt or based on tracking of objects
  • G06V 10/44 - Local feature extraction by analysis of parts of the pattern, e.g. by detecting edges, contours, loops, corners, strokes or intersections; Connectivity analysis, e.g. of connected components
  • G06V 10/74 - Image or video pattern matching; Proximity measures in feature spaces

42.

GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING DUAL NANORIBBON CHANNEL STRUCTURES

      
Application Number 18510402
Status Pending
Filing Date 2023-11-15
First Publication Date 2024-03-14
Owner Intel Corporation (USA)
Inventor
  • Trivedi, Tanuj
  • Ramaswamy, Rahul
  • Kim, Jeong Dong
  • Fallahazad, Babak
  • Chang, Hsu-Yu
  • Chang, Ting
  • Nidhi, Nidhi
  • Hafez, Walid M.

Abstract

Gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, and methods of fabricating gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires above a substrate. A dielectric cap is over the first vertical arrangement of nanowires. A second vertical arrangement of nanowires is above the substrate. Individual ones of the second vertical arrangement of nanowires are laterally staggered with individual ones of the first vertical arrangement of nanowires and the dielectric cap.

IPC Classes  ?

  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H01L 29/165 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form including two or more of the elements provided for in group in different semiconductor regions
  • H01L 29/66 - Types of semiconductor device

43.

PATCH ACCOMMODATING EMBEDDED DIES HAVING DIFFERENT THICKNESSES

      
Application Number 18511641
Status Pending
Filing Date 2023-11-16
First Publication Date 2024-03-14
Owner Intel Corporation (USA)
Inventor
  • Pietambaram, Srinivas
  • May, Robert Alan
  • Darmawikarta, Kristof
  • Tanaka, Hiroki
  • Manepalli, Rahul N.
  • Boyapati, Sri Ranga Sai

Abstract

Techniques for a patch to couple one or more surface dies to an interposer or motherboard are provided. In an example, the patch can include multiple embedded dies. In an example, a microelectronic device can be formed to include a patch on an interposer, where the patch can include multiple embedded dies and each die can have a different thickness.

IPC Classes  ?

  • H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices
  • H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
  • H01L 23/498 - Leads on insulating substrates
  • H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

44.

AUTOMATIC CODE GENERATION OF OPTIMIZED RTL VIA REDUNDANT CODE REMOVAL

      
Application Number 18512518
Status Pending
Filing Date 2023-11-17
First Publication Date 2024-03-14
Owner Intel Corporation (USA)
Inventor
  • Drane, Theo
  • Morini, Emiliano
  • Schmerge, Jordan
  • Coward, Samuel

Abstract

Described herein is a technique for automatic generation of optimized RTL via redundant code removal. By automatically introducing local mutations into the original RTL and using equivalence checking tools to confirm that the functionality it is not affected, optimized RTL can be produced automatically without requiring human intervention.

IPC Classes  ?

  • G06F 8/41 - Compilation
  • G06F 30/327 - Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist

45.

PATTERNABLE DIE ATTACH MATERIALS AND PROCESSES FOR PATTERNING

      
Application Number 18513015
Status Pending
Filing Date 2023-11-17
First Publication Date 2024-03-14
Owner Intel Corporation (USA)
Inventor
  • Nie, Bai
  • Duan, Gang
  • Pietambaram, Srinivas
  • Jones, Jesse
  • Kanaoka, Yosuke
  • Feng, Hongxia
  • Xu, Dingying
  • Manepalli, Rahul
  • Paital, Sameer
  • Darmawikarta, Kristof
  • Li, Yonggang
  • Jiao, Meizi
  • Zhang, Chong
  • Tingey, Matthew
  • Han, Jung Kyu
  • Chen, Haobo

Abstract

A die assembly is disclosed. The die assembly includes a die, one or more die pads on a first surface of the die and a die attach film on the die where the die attach film includes one or more openings that expose the one or more die pads and that extend to one or more edges of the die.

IPC Classes  ?

  • H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
  • H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
  • H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
  • H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement

46.

GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING DEPOPULATED CHANNEL STRUCTURES USING SELECTIVE BOTTOM-UP APPROACH

      
Application Number 18513028
Status Pending
Filing Date 2023-11-17
First Publication Date 2024-03-14
Owner Intel Corporation (USA)
Inventor
  • Thomas, Nicole
  • Mannebach, Ehren
  • Huang, Cheng-Ying
  • Radosavljevic, Marko

Abstract

Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using a selective bottom-up approach, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a substrate. The vertical arrangement of nanowires has one or more active nanowires above one or more oxide nanowires. A first gate stack is over and around the one or more active nanowires. A second gate stack is over and around the one or more oxide nanowires.

IPC Classes  ?

  • H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/786 - Thin-film transistors

47.

MIGRATION FROM A LEGACY NETWORK APPLIANCE TO A NETWORK FUNCTION VIRTUALIZATION (NFV) APPLIANCE

      
Application Number 18513261
Status Pending
Filing Date 2023-11-17
First Publication Date 2024-03-14
Owner Intel Corporation (USA)
Inventor
  • Connor, Patrick
  • Chilikin, Andrey
  • Ryan, Brendan
  • Macnamara, Chris
  • Browne, John J.
  • Jambur Sathyanarayana, Krishnamurthy
  • Doyle, Stephen
  • Kantecki, Tomasz
  • Kelly, Anthony
  • Loftus, Ciara
  • Trahe, Fiona

Abstract

A computing device includes an appliance status table to store at least one of reliability and performance data for one or more network functions virtualization (NFV) appliances and one or more legacy network appliances. The computing device includes a load controller to configure an Internet Protocol (IP) filter rule to select a packet for which processing of the packet is to be migrated from a selected one of the one or more legacy network appliances to a selected one of the one or more NFV appliances, and to update the appliance status table with received at least one of reliability and performance data for the one or more legacy network appliances and the one or more NFV appliances. The computing device includes a packet distributor to receive the packet, to select one of the one or more NFV appliances based at least in part on the appliance status table, and to send the packet to the selected NFV appliance. Other embodiments are described herein.

IPC Classes  ?

  • H04L 47/125 - Avoiding congestion; Recovering from congestion by balancing the load, e.g. traffic engineering
  • G06F 8/76 - Adapting program code to run in a different environment; Porting
  • G06F 9/455 - Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
  • H04L 43/0817 - Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters by checking availability by checking functioning
  • H04L 47/2441 - Traffic characterised by specific attributes, e.g. priority or QoS relying on flow classification, e.g. using integrated services [IntServ]

48.

FREQUENCY OVERSHOOT AND VOLTAGE DROOP MITIGATION APPARATUS AND METHOD

      
Application Number 18514807
Status Pending
Filing Date 2023-11-20
First Publication Date 2024-03-14
Owner Intel Corporation (USA)
Inventor
  • Mosalikanti, Praveen
  • Kurd, Nasser A.
  • Gendler, Alexander

Abstract

An apparatus and method are described, which prior to an event that could result in frequency overshoot, sends a signal to a voltage regulator or generator requesting a temporary supply voltage and/or current boost. This enables a clocking source, such as a phase locked loop (PLL) to lock fast while not needing any long-term voltage guard bands. The apparatus and scheme allows for on-the-fly change in supply voltage and/or clock frequency for a processor with little to no impact on Vmin. During the clock frequency overshoot, the supply voltage is temporarily boosted and then reduced down to the expected voltage level of the power supply. Such boost allows for absorbing the clock frequency overshoot impact. The supply voltage level can be reduced in a step-wise fashion to avoid any potential undershoot in clock frequency.

IPC Classes  ?

  • G06F 1/3296 - Power saving characterised by the action undertaken by lowering the supply or operating voltage
  • G01R 19/25 - Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques
  • H03K 5/24 - Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
  • H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
  • H03L 7/093 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
  • H03L 7/095 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using a lock detector

49.

NANOWIRE TRANSISTOR STRUCTURE AND METHOD OF SHAPING

      
Application Number 18514974
Status Pending
Filing Date 2023-11-20
First Publication Date 2024-03-14
Owner Intel Corporation (USA)
Inventor
  • Thompson, Erica J.
  • Kasukurti, Aditya
  • Kang, Jun Sung
  • Cheong, Kai Loon
  • Guha, Biswajeet
  • Hsu, William
  • Beattie, Bruce

Abstract

A nanowire device includes one or more nanowire having a first end portion, a second end portion, and a body portion between the first end portion and the second end portion. A first conductive structure is in contact with the first end portion and a second conductive structure is in contact with the second end portion. The body portion of the nanowire has a first cross-sectional shape and the first end portion has a second cross-sectional shape different from the first cross-sectional shape. Integrated circuits including the nanowire device and a method of cleaning a semiconductor structure are also disclosed.

IPC Classes  ?

  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H01L 29/66 - Types of semiconductor device

50.

GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING INSULATOR FIN ON INSULATOR SUBSTRATE

      
Application Number 18514995
Status Pending
Filing Date 2023-11-20
First Publication Date 2024-03-14
Owner Intel Corporation (USA)
Inventor
  • Lilak, Aaron D.
  • Mehandru, Rishabh
  • Weber, Cory
  • Rachmady, Willy
  • Mishra, Varun

Abstract

Gate-all-around integrated circuit structures having an insulator fin on an insulator substrate, and methods of fabricating gate-all-around integrated circuit structures having an insulator fin on an insulator substrate, are described. For example, an integrated circuit structure includes an insulator fin on an insulator substrate. A vertical arrangement of horizontal semiconductor nanowires is over the insulator fin. A gate stack surrounds a channel region of the vertical arrangement of horizontal semiconductor nanowires, and the gate stack is overlying the insulator fin. A pair of epitaxial source or drain structures is at first and second ends of the vertical arrangement of horizontal semiconductor nanowires and at first and second ends of the insulator fin.

IPC Classes  ?

  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/8234 - MIS technology
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H01L 29/165 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form including two or more of the elements provided for in group in different semiconductor regions
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 29/786 - Thin-film transistors

51.

SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITHOUT FIN END GAP

      
Application Number 18516595
Status Pending
Filing Date 2023-11-21
First Publication Date 2024-03-14
Owner Intel Corporation (USA)
Inventor
  • Liao, Szuya S.
  • Clendenning, Scott B.
  • Torres, Jessica
  • Baumgartel, Lukas
  • Chikkadi, Kiran
  • Lancaster, Diane
  • Metz, Matthew V.
  • Gstrein, Florian
  • Mitan, Martin M.
  • Hourani, Rami

Abstract

Self-aligned gate endcap (SAGE) architectures without fin end gaps, and methods of fabricating self-aligned gate endcap (SAGE) architectures without fin end gaps, are described. In an example, an integrated circuit structure includes a semiconductor fin having a cut along a length of the semiconductor fin. A gate endcap isolation structure has a first portion parallel with the length of the semiconductor fin and is spaced apart from the semiconductor fin. The gate endcap isolation structure also has a second portion in a location of the cut of the semiconductor fin and in contact with the semiconductor fin.

IPC Classes  ?

  • H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
  • H01L 21/762 - Dielectric regions
  • H01L 21/8234 - MIS technology
  • H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
  • H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
  • H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors

52.

SYSTEMS AND METHODS FOR UPDATING MEMORY SIDE CACHES IN A MULTI-GPU CONFIGURATION

      
Application Number 18516716
Status Pending
Filing Date 2023-11-21
First Publication Date 2024-03-14
Owner Intel Corporation (USA)
Inventor
  • Koker, Altug
  • Ray, Joydeep
  • Anantaraman, Aravindh
  • Andrei, Valentin
  • Appu, Abhishek
  • Coleman, Sean
  • Galoppo Von Borries, Nicolas
  • George, Varghese
  • K, Pattabhiraman
  • Kim, Sungye
  • Macpherson, Mike
  • Maiyuran, Subramaniam
  • Ould-Ahmed-Vall, Elmoustapha
  • Ranganathan, Vasanth
  • Valerio, James

Abstract

Systems and methods for updating remote memory side caches in a multi-GPU configuration are disclosed herein. In one embodiment, a graphics processor for a multi-tile architecture includes a first graphics processing unit (GPU) having a first memory, a first memory side cache memory, a first communication fabric, and a first memory management unit (MMU). The graphics processor includes a second graphics processing unit (GPU) having a second memory, a second memory side cache memory, a second memory management unit (MMU), and a second communication fabric that is communicatively coupled to the first communication fabric. The first MMU is configured to control memory requests for the first memory, to update content in the first memory, to update content in the first memory side cache memory, and to determine whether to update the content in the second memory side cache memory.

IPC Classes  ?

  • G06F 15/78 - Architectures of general purpose stored program computers comprising a single central processing unit
  • G06F 7/544 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices for evaluating functions by calculation
  • G06F 7/575 - Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry
  • G06F 7/58 - Random or pseudo-random number generators
  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline, look ahead
  • G06F 9/50 - Allocation of resources, e.g. of the central processing unit [CPU]
  • G06F 12/02 - Addressing or allocation; Relocation
  • G06F 12/06 - Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication
  • G06F 12/0802 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
  • G06F 12/0804 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
  • G06F 12/0811 - Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
  • G06F 12/0862 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
  • G06F 12/0866 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
  • G06F 12/0871 - Allocation or management of cache space
  • G06F 12/0875 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
  • G06F 12/0882 - Page mode
  • G06F 12/0888 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using selective caching, e.g. bypass
  • G06F 12/0891 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
  • G06F 12/0893 - Caches characterised by their organisation or structure
  • G06F 12/0895 - Caches characterised by their organisation or structure of parts of caches, e.g. directory or tag array
  • G06F 12/0897 - Caches characterised by their organisation or structure with two or more cache hierarchy levels
  • G06F 12/1009 - Address translation using page tables, e.g. page table structures
  • G06F 12/128 - Replacement control using replacement algorithms adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel
  • G06F 15/80 - Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
  • G06F 17/16 - Matrix or vector computation
  • G06F 17/18 - Complex mathematical operations for evaluating statistical data
  • G06T 1/20 - Processor architectures; Processor configuration, e.g. pipelining
  • G06T 1/60 - Memory management
  • H03M 7/46 - Conversion to or from run-length codes, i.e. by representing the number of consecutive digits, or groups of digits, of the same kind by a code word and a digit indicative of that kind

53.

FULL WAFER DEVICE WITH FRONT SIDE PASSIVE ELECTRONIC COMPONENTS

      
Application Number 17930825
Status Pending
Filing Date 2022-09-09
First Publication Date 2024-03-14
Owner Intel Corporation (USA)
Inventor
  • Sharma, Abhishek A.
  • Ghani, Tahir
  • Gomes, Wilfred
  • Murthy, Anand S.
  • Ranade, Pushkar Sharad
  • Suthram, Sagar

Abstract

Described herein are full wafer devices that include passive devices formed in one or more interconnect layers. Interconnect layers are formed over a front side of the full wafer device. A passive device is formed using an additive process that results in a seam running through the passive device. The seam may be, for example, an air gap, a change in material structure, or a region with a different chemical makeup from the surrounding passive device. In some embodiments, the passive devices are formed in global interconnect layers coupling multiple does of the full wafer device.

IPC Classes  ?

  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 49/02 - Thin-film or thick-film devices

54.

SECURE MULTIPARTY COMPUTE USING HOMOMORPHIC ENCRYPTION

      
Application Number 17931438
Status Pending
Filing Date 2022-09-12
First Publication Date 2024-03-14
Owner Intel Corporation (USA)
Inventor
  • Race, Kylan
  • Zamora Ramos, Ernesto
  • Bottleson, Jeremy
  • Jin, Jingyi

Abstract

A method comprises receiving, from a remote device, a first encrypted data set encrypted using a first encryption scheme, performing a set of computations on the first encrypted data set to generate a first set of encrypted results, encrypting the first set of encrypted results using a second encryption scheme to generate a second set of encrypted results, sending the second set of encrypted results to the remote device, receiving, from the remote device, third set of encrypted results in which the first encryption scheme has been decrypted, and generating a set of decrypted results by applying a decryption algorithm to the third set of encrypted results to decrypt the second encryption scheme.

IPC Classes  ?

  • H04L 9/00 - Arrangements for secret or secure communications; Network security protocols
  • H04L 9/06 - Arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for blockwise coding, e.g. D.E.S. systems

55.

BARRIER LAYER FOR DIELECTRIC RECESS MITIGATION

      
Application Number 17940195
Status Pending
Filing Date 2022-09-08
First Publication Date 2024-03-14
Owner Intel Corporation (USA)
Inventor
  • Chu, Tao
  • Jang, Minwoo
  • Lin, Chia-Ching
  • Luo, Yanbin
  • Hung, Ting-Hsiang
  • Zhang, Feng
  • Xu, Guowei

Abstract

Techniques are provided herein to form semiconductor devices that include a layer across an upper surface of a dielectric fill between devices and configured to prevent or otherwise reduce recessing of the dielectric fill. In this manner, the layer may be referred to as a barrier layer or recess-inhibiting layer. The semiconductor regions of the devices extend above a subfin region that may be native to the substrate. These subfin regions are separated from one another using a dielectric fill that acts as a shallow trench isolation (STI) structure to electrically isolate devices from one another. A barrier layer is formed over the dielectric fill early in the fabrication process to prevent or otherwise reduce the dielectric fill from recessing during subsequent processing. The layer may include oxygen and a metal, such as aluminum.

IPC Classes  ?

  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 21/762 - Dielectric regions
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

56.

FIN TRIM PLUG STRUCTURES WITH METAL FOR IMPARTING CHANNEL STRESS

      
Application Number 17940944
Status Pending
Filing Date 2022-09-08
First Publication Date 2024-03-14
Owner Intel Corporation (USA)
Inventor
  • Chu, Tao
  • Zhang, Feng
  • Jang, Minwoo
  • Luo, Yanbin
  • Lin, Chia-Ching
  • Hung, Ting-Hsiang

Abstract

Fin trim plug structures with metal for imparting channel stress are described. In an example, an integrated circuit structure includes a fin including silicon, the fin having a top and sidewalls, wherein the top has a longest dimension along a direction. A first isolation structure is over a first end of the fin. A gate structure including a gate electrode is over the top of and laterally adjacent to the sidewalls of a region of the fin. The gate structure is spaced apart from the first isolation structure along the direction. A second isolation structure is over a second end of the fin, the second end opposite the first end, the second isolation structure spaced apart from the gate structure along the direction. The first isolation structure and the second isolation structure both include a dielectric material laterally surrounding an isolated metal structure.

IPC Classes  ?

  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 27/11 - Static random access memory structures

57.

TECHNIQUES FOR A TRUSTED EXECUTION ENVIRONMENT AT A COMPUTE SERVER TO USE A REMOTE ACCELERATOR

      
Application Number 17942466
Status Pending
Filing Date 2022-09-12
First Publication Date 2024-03-14
Owner Intel Corporation (USA)
Inventor Kakaiya, Utkarsh Y.

Abstract

Examples include techniques for a trusted execution environment (TEE) at a compute server to request a service to be performed by an accelerator that is located at or with a service server. Examples are described of the TEE at the compute server authenticating the remote accelerator to enable establishment of one or more secure communication sessions for the accelerator to decrypt encrypted data, perform a transformation on the decrypted data and then re-encrypt the transformed data. Examples are also described of the TEE at the compute server authenticating a service TEE at the service server as well as the accelerator to enable the service TEE and the accelerator to collaboratively decrypt encrypted data, perform a transformation on the decrypted data and then re-encrypt the transformed data.

IPC Classes  ?

  • H04L 9/40 - Network security protocols
  • G06F 21/53 - Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems during program execution, e.g. stack integrity, buffer overflow or preventing unwanted data erasure by executing in a restricted environment, e.g. sandbox or secure virtual machine
  • H04L 9/32 - Arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system

58.

TECHNOLOGIES FOR GLASS CORE INDUCTOR

      
Application Number 17943354
Status Pending
Filing Date 2022-09-13
First Publication Date 2024-03-14
Owner Intel Corporation (USA)
Inventor
  • Marin, Brandon Christian
  • Nad, Suddhasattwa
  • Pietambaram, Srinivas V.
  • Ecton, Jeremy D.
  • Rahman, Mohammad
  • Duan, Gang

Abstract

Techniques for a glass core inductor are disclosed. In the illustrative embodiment, an integrated circuit component includes a glass substrate and a fully-integrated voltage regulator (FIVR). The FIVR includes a glass core inductor that is embedded in the glass substrate. Each inductor turn of the inductor includes two angled through-glass vias and a trace on top of the glass substrate connecting the angled through-glass vias, resulting in an inductor with a cross-section in the shape of a triangle or trapezoid. The inductor may have a relatively large inductance per unit area, requiring less space or allowing for a larger inductance.

IPC Classes  ?

  • H01L 49/02 - Thin-film or thick-film devices
  • H01F 27/29 - Terminals; Tapping arrangements
  • H01L 23/498 - Leads on insulating substrates
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different main groups of groups , or in a single subclass of , , e.g. forming hybrid circuits
  • H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,

59.

GATE CUTS IN A GRATING PATTERN ACROSS AN INTEGRATED CIRCUIT

      
Application Number 17943443
Status Pending
Filing Date 2022-09-13
First Publication Date 2024-03-14
Owner Intel Corporation (USA)
Inventor
  • Koh, Shao-Ming
  • Guler, Leonard P.
  • Singh, Gurpreet
  • Chandhok, Manish
  • Prince, Matthew J.

Abstract

Techniques are provided herein to form an integrated circuit having a grating pattern of gate cut structures such that a gate cut structure extends between the gate layers of adjacent semiconductor devices and between the source or drain regions (e.g., epitaxial regions) of the adjacent semiconductor devices. In an example, neighboring semiconductor devices each include a semiconductor region extending between a source region and a drain region, and a gate structure extending over the semiconductor regions of the neighboring semiconductor devices. In some such examples, a gate cut structure is present between each pair of neighboring semiconductor devices thus interrupting the gate structure and isolating the gate electrode of one semiconductor device from the gate electrode of the other semiconductor device. The gate cut structure further extends to separate the source or drain regions of the neighboring semiconductor devices. Subsequent processes allow neighboring gate or source or drain regions connections.

IPC Classes  ?

  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 21/8234 - MIS technology
  • H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
  • H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
  • H01L 29/786 - Thin-film transistors

60.

TRANSISTOR DEVICES WITH EXTENDED DRAIN

      
Application Number 17943557
Status Pending
Filing Date 2022-09-13
First Publication Date 2024-03-14
Owner Intel Corporation (USA)
Inventor
  • Kar, Ayan
  • Thomson, Nicholas A.
  • Kolluru, Kalyan C.
  • Orr, Benjamin

Abstract

An integrated circuit structure includes a sub-fin, a source region in contact with a first portion of the sub-fin, and a drain region in contact with a second portion of the sub-fin. A body including semiconductor material is above the sub-fin, where the body extends laterally between the source region and the drain region. A gate structure is on the body and includes (i) a gate electrode, and (ii) a gate dielectric between the gate electrode and the body. In an example, a first distance between the drain region and the gate electrode is at least two times a second distance between the source region and the gate electrode, where the first and second distances are measured in a same horizontal plane that runs in a direction parallel to the body. In an example, the body is a nanoribbon, a nanosheet, a nanowire, or a fin.

IPC Classes  ?

  • H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier

61.

DIODES WITH BACKSIDE CONTACT

      
Application Number 17943812
Status Pending
Filing Date 2022-09-13
First Publication Date 2024-03-14
Owner Intel Corporation (USA)
Inventor
  • Thomson, Nicholas A.
  • Kolluru, Kalyan C.
  • Kar, Ayan
  • Kobrinsky, Mauro J.

Abstract

An integrated circuit structure includes a sub-fin having at least a portion that is doped with a first type of dopant, and a diffusion region doped with a second type of dopant. The diffusion region is in contact with the sub-fin and extends upward from the sub-fin. The first type of dopant is one of a p-type or an n-type dopant, and the second type of dopant is the other of the p-type or the n-type dopant. In an example, a first conductive contact is above and on the diffusion region, and a second conductive contact is in contact with the portion of the sub-fin. In an example, the diffusion region is at least a part of one of an anode or a cathode of a diode, and the portion of the sub-fin is at least a part of the other of the anode or the cathode of the diode.

IPC Classes  ?

  • H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/861 - Diodes

62.

TARGETED SUB-FIN ETCH DEPTH

      
Application Number 17943815
Status Pending
Filing Date 2022-09-13
First Publication Date 2024-03-14
Owner Intel Corporation (USA)
Inventor
  • Thomson, Nicholas A.
  • Kar, Ayan
  • Kolluru, Kalyan C.
  • Kobrinsky, Mauro J.

Abstract

An integrated circuit structure includes laterally adjacent first and second devices. The first device has (i) a first diffusion region, (ii) a first body including semiconductor material extending laterally from the first diffusion region, and (iii) a first gate structure on the first body. The first diffusion region has a first lower section that extends below a lower surface of the first gate structure, the first lower section having a first height. The second device has (i) a second diffusion region, (ii) a second body including semiconductor material extending laterally from the second diffusion region, and (iii) a second gate structure on the second body. The second diffusion region has a second lower section that extends below a lower surface of the second gate structure, the second lower section having a second height. In an example, the first height is at least 2 nanometers greater than the second height.

IPC Classes  ?

  • H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
  • H01L 21/8234 - MIS technology

63.

COPPER CLAD LAMINATE (CCL) FOR PLATING PADS WITHIN A GLASS CAVITY FOR GLASS CORE APPLICATIONS

      
Application Number 17943915
Status Pending
Filing Date 2022-09-13
First Publication Date 2024-03-14
Owner Intel Corporation (USA)
Inventor
  • Marin, Brandon C.
  • Duan, Gang
  • Pietambaram, Srinivas V.
  • Darmawikarta, Kristof
  • Ecton, Jeremy D.
  • Nad, Suddhasattwa
  • Tanaka, Hiroki
  • Tadayon, Pooya

Abstract

Embodiments disclosed herein include interposers and methods of forming interposers. In an embodiment, an interposer comprises a substrate with a first surface and a second surface opposite from the first surface, where the substrate comprises glass. In an embodiment, the interposer further comprises a cavity into the first surface of the substrate, a via through the substrate below the cavity, a first pad in the cavity over the via, and a second pad on the second surface of the substrate under the via.

IPC Classes  ?

  • H01L 23/15 - Ceramic or glass substrates
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates

64.

CHIPLET STATE AWARE AND DYNAMIC VOLTAGE REGULATOR EVENT HANDLING

      
Application Number 17944310
Status Pending
Filing Date 2022-09-14
First Publication Date 2024-03-14
Owner Intel Corporation (USA)
Inventor
  • Dai, Jianwei
  • Suvarna, Yashwitha
  • Ang, Boon Hui
  • Shah, Pranali

Abstract

Embodiments described herein may include apparatus, systems, techniques or processes that are directed to chiplet state aware and dynamic prioritization of voltage regulator event indication handling. An intelligent arbiter notifies chiplets of VR events in a dynamic priority scheme that considers multiple factors such as chiplet state (for example, active, sleep, deep sleep, and the like), chiplet power consumption and time frame for transitioning to an active state, outstanding VR requests, chiplet latency sensitivity and the like in its prioritization of chiplet notifications. As chiplet states themselves are dynamic with a chiplet transitioning between multiple states during operation, the intelligent arbiter may also utilize a dynamic prioritization scheme to maximize efficiency and minimize power consumption.

IPC Classes  ?

  • G06F 1/3296 - Power saving characterised by the action undertaken by lowering the supply or operating voltage
  • G06F 9/52 - Program synchronisation; Mutual exclusion, e.g. by means of semaphores

65.

OFFSET SCALING IN LOAD/STORE MESSAGES

      
Application Number 17944500
Status Pending
Filing Date 2022-09-14
First Publication Date 2024-03-14
Owner Intel Corporation (USA)
Inventor
  • Wiegert, John
  • Ray, Joydeep
  • Bauer, Timothy
  • Valerio, James

Abstract

Embodiments described herein enable the offload of address calculations required to access a data element within an array of data elements from primary compute resources of a graphics processor to the memory access circuitry of the graphics processor. The memory access circuitry is configured to receive a message to access a data element of an array of data elements in the memory, the message to include an index of the data element in the array of data elements, calculate a byte address for the data element based in part on the index of the data element in the array of data elements, and submit a memory access request to the memory to access the data element at the byte address.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers
  • G06T 1/20 - Processor architectures; Processor configuration, e.g. pipelining
  • G06T 1/60 - Memory management

66.

IMAGE PROCESSING WITH FACE MASK DETECTION

      
Application Number CN2022117834
Publication Number 2024/050760
Status In Force
Filing Date 2022-09-08
Publication Date 2024-03-14
Owner INTEL CORPORATION (USA)
Inventor
  • Li, Fuwen
  • Xia, Yu
  • Zhou, Lan

Abstract

Methods, apparatus, systems, and articles of manufacture are disclosed to automatically process an image based on a detection of a face mask. An example article of manufacture includes instructions that, when executed, cause programmable circuitry to at least: map a characteristic of an upper area (402) of a face of a person in an image to a color plot including a face skin tone cone (302); map a characteristic of a lower area (404) of the face to the color plot; and identify a presence or an absence of a face mask based on the respective positions of the characteristic of the upper area (402) and the characteristic of the lower area (404) relative to the skin tone cone (302).

IPC Classes  ?

  • G06K 11/00 - Methods or arrangements for graph-reading or for converting the pattern of mechanical parameters, e.g. force or presence, into electrical signals
  • G06V 40/16 - Human faces, e.g. facial parts, sketches or expressions
  • H04L 27/00 - Modulated-carrier systems

67.

METHODS AND ARRANGEMENTS TO COMMUNICATE UE CONTEXT INFORMATION

      
Application Number US2023032006
Publication Number 2024/054454
Status In Force
Filing Date 2023-09-05
Publication Date 2024-03-14
Owner INTEL CORPORATION (USA)
Inventor
  • Han, Jaemin
  • Whinnett, Nicholas
  • Ying, Dawei
  • Ruan, Leifeng
  • Schreck, Jan

Abstract

Logic may determine user equipment (UE) context information associated with a UE, the UE context information comprising new information related to establishment of a new connection with the UE or related to an update of the UE context information for an existing connection with the UE. Logic may identify an event trigger associated with new information. And logic may respond to a query from the near-RT RIC for UE context information associated with the UE, wherein the UE supports a non-grid of beams mode for beamforming.

IPC Classes  ?

  • H04W 8/24 - Transfer of terminal data
  • H04L 5/00 - Arrangements affording multiple use of the transmission path
  • H04B 7/06 - Diversity systems; Multi-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station

68.

INTEGRATED CIRCUIT SUPPORTS WITH MICROSTRIPS

      
Application Number 18260810
Status Pending
Filing Date 2021-02-26
First Publication Date 2024-03-14
Owner Intel Corporation (USA)
Inventor
  • Wang, Wenzhi
  • Ye, Xiaoning
  • Chu, Yunhui
  • Ye, Chunfei
  • Mccall, James A.

Abstract

Disclosed herein are integrated circuit (IC) supports with microstrips, and related embodiments. For example, an IC support may include a plurality of microstrips and a plurality of conductive segments. Individual ones of the conductive segments may be at least partially over at least two microstrips, a dielectric material may be between the plurality of microstrips and the plurality of conductive segments, and the conductive segments are included in a tape.

IPC Classes  ?

  • H01L 23/66 - High-frequency adaptations
  • H01L 23/498 - Leads on insulating substrates
  • H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
  • H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
  • H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass

69.

SCHEDULING OF THREADS FOR EXECUTION UTILIZING LOAD BALANCING OF THREAD GROUPS

      
Application Number 18365595
Status Pending
Filing Date 2023-08-04
First Publication Date 2024-03-14
Owner Intel Corporation (USA)
Inventor
  • Vembu, Balaji
  • Appu, Abhishek R.
  • Ray, Joydeep
  • Koker, Altug

Abstract

An apparatus to facilitate thread scheduling is disclosed. The apparatus includes logic to store barrier usage data based on a magnitude of barrier messages in an application kernel and a scheduler to schedule execution of threads across a plurality of multiprocessors based on the barrier usage data.

IPC Classes  ?

  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline, look ahead
  • G06F 9/46 - Multiprogramming arrangements
  • G06F 9/48 - Program initiating; Program switching, e.g. by interrupt
  • G06F 9/50 - Allocation of resources, e.g. of the central processing unit [CPU]
  • G06F 9/52 - Program synchronisation; Mutual exclusion, e.g. by means of semaphores
  • G06F 9/54 - Interprogram communication
  • G06F 12/0842 - Multiuser, multiprocessor or multiprocessing cache systems for multiprocessing or multitasking
  • G06F 12/0866 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
  • G06F 12/0897 - Caches characterised by their organisation or structure with two or more cache hierarchy levels
  • G06F 15/16 - Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
  • G06F 15/76 - Architectures of general purpose stored program computers
  • G06T 1/20 - Processor architectures; Processor configuration, e.g. pipelining
  • G06T 1/60 - Memory management

70.

METHODS AND SYSTEMS FOR BUDGETED AND SIMPLIFIED TRAINING OF DEEP NEURAL NETWORKS

      
Application Number 18371934
Status Pending
Filing Date 2023-09-22
First Publication Date 2024-03-14
Owner Intel Corporation (USA)
Inventor
  • Guo, Yiwen
  • Hou, Yuqing
  • Yao, Anbang
  • Cai, Dongqi
  • Xu, Lin
  • Hu, Ping
  • Wang, Shandong
  • Cheng, Wenhua
  • Chen, Yurong
  • Wang, Libin

Abstract

Methods and systems for budgeted and simplified training of deep neural networks (DNNs) are disclosed. In one example, a trainer is to train a DNN using a plurality of training sub-images derived from a down-sampled training image. A tester is to test the trained DNN using a plurality of testing sub-images derived from a down-sampled testing image. In another example, in a recurrent deep Q-network (RDQN) having a local attention mechanism located between a convolutional neural network (CNN) and a long-short time memory (LSTM), a plurality of feature maps are generated by the CNN from an input image. Hard-attention is applied by the local attention mechanism to the generated plurality of feature maps by selecting a subset of the generated feature maps. Soft attention is applied by the local attention mechanism to the selected subset of generated feature maps by providing weights to the selected subset of generated feature maps in obtaining weighted feature maps. The weighted feature maps are stored in the LSTM. A Q value is calculated for different actions based on the weighted feature maps stored in the LSTM.

IPC Classes  ?

  • G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
  • G06F 18/21 - Design or setup of recognition systems or techniques; Extraction of features in feature space; Blind source separation
  • G06F 18/213 - Feature extraction, e.g. by transforming the feature space; Summarisation; Mappings, e.g. subspace methods
  • G06F 18/214 - Generating training patterns; Bootstrap methods, e.g. bagging or boosting
  • G06N 3/044 - Recurrent networks, e.g. Hopfield networks
  • G06N 3/045 - Combinations of networks
  • G06N 3/08 - Learning methods
  • G06V 10/44 - Local feature extraction by analysis of parts of the pattern, e.g. by detecting edges, contours, loops, corners, strokes or intersections; Connectivity analysis, e.g. of connected components
  • G06V 10/764 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using classification, e.g. of video objects
  • G06V 10/82 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using neural networks
  • G06V 10/94 - Hardware or software architectures specially adapted for image or video understanding
  • G06V 20/00 - Scenes; Scene-specific elements

71.

TEMPORAL DATA STRUCTURES IN A RAY TRACING ARCHITECTURE

      
Application Number 18372783
Status Pending
Filing Date 2023-09-26
First Publication Date 2024-03-14
Owner INTEL CORPORATION (USA)
Inventor
  • Woop, Sven
  • Afra, Attila
  • Benthin, Carsten
  • Wald, Ingo
  • Guenther, Johannes

Abstract

A graphics processing apparatus comprising bounding volume hierarchy (BVH) construction circuitry to perform a spatial analysis and temporal analysis related to a plurality of input primitives and responsively generate a BVH comprising spatial, temporal, and spatial-temporal components that are hierarchically arranged, wherein the spatial components include a plurality of spatial nodes with children, the spatial nodes bounding the children using spatial bounds, and the temporal components comprise temporal nodes with children, the temporal nodes bounding their children using temporal bounds and the spatial-temporal components comprise spatial-temporal nodes with children, the spatial-temporal nodes bounding their children using spatial and temporal bounds; and ray traversal/intersection circuitry to traverse a ray or a set of rays through the BVH in accordance with the spatial and temporal components.

IPC Classes  ?

  • G06T 15/00 - 3D [Three Dimensional] image rendering
  • G06T 1/20 - Processor architectures; Processor configuration, e.g. pipelining
  • G06T 15/06 - Ray-tracing

72.

PACKET BUFFERING TECHNOLOGIES

      
Application Number 18388780
Status Pending
Filing Date 2023-11-10
First Publication Date 2024-03-14
Owner Intel Corporation (USA)
Inventor
  • Rahman, Md Ashiqur
  • Penaranda Cebrian, Roberto
  • Vasudevan, Anil
  • Alemania, Allister
  • Yebenes Segura, Pedro

Abstract

Examples described herein relate to a switch. In some examples, the switch includes circuitry that is configured to: based on receipt of a packet and a level of a first queue, select among a first memory and a second memory device among multiple second memory devices to store the packet, based on selection of the first memory, store the packet in the first memory, and based on selection of the second memory device among multiple second memory devices, store the packet into the selected second memory device. In some examples, the packet is associated with an ingress port and an egress port, and the selected second memory device is associated with a third port that is different than the ingress port or the egress port associated with the packet.

IPC Classes  ?

73.

INSTRUCTION AND LOGIC FOR TRACKING FETCH PERFORMANCE BOTTLENECKS

      
Application Number 18473088
Status Pending
Filing Date 2023-09-22
First Publication Date 2024-03-14
Owner Intel Corporation (USA)
Inventor Yasin, Ahmad

Abstract

A processor includes a front end, an execution unit, a retirement stage, a counter, and a performance monitoring unit. The front end includes logic to receive an event instruction to enable supervision of a front end event that will delay execution of instructions. The execution unit includes logic to set a register with parameters for supervision of the front end event. The front end further includes logic to receive a candidate instruction and match the candidate instruction to the front end event. The counter includes logic to generate the front end event upon retirement of the candidate instruction.

IPC Classes  ?

  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline, look ahead
  • G06F 11/30 - Monitoring

74.

Regional Adjustment of Render Rate

      
Application Number 18474361
Status Pending
Filing Date 2023-09-26
First Publication Date 2024-03-14
Owner Intel Corporation (USA)
Inventor
  • Asperheim, Eric J.
  • Maiyuran, Subramaniam
  • Veernapu, Kiran C.
  • Jahagirdar, Sanjeev S.
  • Vembu, Balaji
  • Burke, Devan
  • Laws, Philip R.
  • Sinha, Kamal
  • Appu, Abhishek R.
  • Ould-Ahmed-Vall, Elmoustapha
  • Doyle, Peter L.
  • Ray, Joydeep
  • Schluessler, Travis T.
  • Feit, John H.
  • Kaburlasos, Nikos
  • Kwiatkowski, Jacek
  • Koker, Altug

Abstract

In accordance with some embodiments, the render rate is varied across and/or up and down the display screen. This may be done based on where the user is looking in order to reduce power consumption and/or increase performance. Specifically the screen display is separated into regions, such as quadrants. Each of these regions is rendered at a rate determined by at least one of what the user is currently looking at, what the user has looked at in the past and/or what it is predicted that the user will look at next. Areas of less focus may be rendered at a lower rate, reducing power consumption in some embodiments.

IPC Classes  ?

  • G06F 3/14 - Digital output to display device
  • G06F 3/01 - Input arrangements or combined input and output arrangements for interaction between user and computer
  • G06F 3/0484 - Interaction techniques based on graphical user interfaces [GUI] for the control of specific functions or operations, e.g. selecting or manipulating an object, an image or a displayed text element, setting a parameter value or selecting a range
  • G09G 5/391 - Resolution modifying circuits, e.g. variable screen formats

75.

APPARATUS, SYSTEM, AND METHOD OF WIRELESS MEDIUM PRIORITIZED ACCESS

      
Application Number 18479008
Status Pending
Filing Date 2023-09-30
First Publication Date 2024-03-14
Owner Intel Corporation (USA)
Inventor
  • Cariou, Laurent
  • Kenney, Thomas J.
  • Akhmetov, Dmitry
  • Das, Dibakar

Abstract

For example, an Access Point (AP) may be configured to transmit a frame including a prioritized-access enabled/disabled field to indicate whether a prioritized-access contention mechanism is to be enabled or disabled over a wireless medium. For example, the prioritized-access contention mechanism may be configured to allow a prioritized station (STA) to transmit a reservation signal over the wireless medium at a reservation signal transmission time, and to contend the wireless medium according to a high-priority contention policy to obtain a Transmit Opportunity (TxOP) after transmission of the reservation signal. For example, the reservation signal transmission time may be based on an end of a predefined time duration from a start of a contention period. For example, the reservation signal may be configured to indicate a busy Clear Channel Assessment (CCA) to a receiving STA.

IPC Classes  ?

  • H04W 74/08 - Non-scheduled access, e.g. random access, ALOHA or CSMA [Carrier Sense Multiple Access]

76.

INSTRUCTION BASED CONTROL OF MEMORY ATTRIBUTES

      
Application Number 18491474
Status Pending
Filing Date 2023-10-20
First Publication Date 2024-03-14
Owner Intel Corporation (USA)
Inventor
  • Ray, Joydeep
  • Koker, Altug
  • George, Varghese
  • Macpherson, Mike
  • Anantaraman, Aravindh
  • Appu, Abhishek R.
  • Ould-Ahmed-Vall, Elmoustapha
  • Galoppo Von Borries, Nicolas
  • Ashbaugh, Ben J.

Abstract

Embodiments described herein provide techniques to facilitate instruction-based control of memory attributes. One embodiment provides a graphics processor comprising a processing resource, a memory device, a cache coupled with the processing resources and the memory, and circuitry to process a memory access message received from the processing resource. The memory access message enables access to data of the memory device. To process the memory access message, the circuitry is configured to determine one or more cache attributes that indicate whether the data should be read from or stored the cache. The cache attributes may be provided by the memory access message or stored in state data associated with the data to be accessed by the access message.

IPC Classes  ?

  • G06F 15/78 - Architectures of general purpose stored program computers comprising a single central processing unit
  • G06F 7/544 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices for evaluating functions by calculation
  • G06F 7/575 - Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry
  • G06F 7/58 - Random or pseudo-random number generators
  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline, look ahead
  • G06F 9/50 - Allocation of resources, e.g. of the central processing unit [CPU]
  • G06F 12/02 - Addressing or allocation; Relocation
  • G06F 12/06 - Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication
  • G06F 12/0802 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
  • G06F 12/0804 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
  • G06F 12/0811 - Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
  • G06F 12/0862 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
  • G06F 12/0866 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
  • G06F 12/0871 - Allocation or management of cache space
  • G06F 12/0875 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
  • G06F 12/0882 - Page mode
  • G06F 12/0888 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using selective caching, e.g. bypass
  • G06F 12/0891 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
  • G06F 12/0893 - Caches characterised by their organisation or structure
  • G06F 12/0895 - Caches characterised by their organisation or structure of parts of caches, e.g. directory or tag array
  • G06F 12/0897 - Caches characterised by their organisation or structure with two or more cache hierarchy levels
  • G06F 12/1009 - Address translation using page tables, e.g. page table structures
  • G06F 12/128 - Replacement control using replacement algorithms adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel
  • G06F 15/80 - Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
  • G06F 17/16 - Matrix or vector computation
  • G06F 17/18 - Complex mathematical operations for evaluating statistical data
  • G06T 1/20 - Processor architectures; Processor configuration, e.g. pipelining
  • G06T 1/60 - Memory management
  • H03M 7/46 - Conversion to or from run-length codes, i.e. by representing the number of consecutive digits, or groups of digits, of the same kind by a code word and a digit indicative of that kind

77.

DISAGGREGATED COMPUTING FOR DISTRIBUTED CONFIDENTIAL COMPUTING ENVIRONMENT

      
Application Number 18511296
Status Pending
Filing Date 2023-11-16
First Publication Date 2024-03-14
Owner Intel Corporation (USA)
Inventor
  • Lal, Reshma
  • Pappachan, Pradeep
  • Kida, Luis
  • Desai, Soham Jayesh
  • Sen, Sujoy
  • Panneer, Selvakumar
  • Sharp, Robert

Abstract

An apparatus to facilitate disaggregated computing for a distributed confidential computing environment is disclosed. The apparatus includes one or more processors to facilitate receiving a manifest corresponding to graph nodes representing regions of memory of a remote client machine, the graph nodes corresponding to a command buffer and to associated data structures and kernels of the command buffer used to initialize a hardware accelerator and execute the kernels, and the manifest indicating a destination memory location of each of the graph nodes and dependencies of each of the graph nodes; identifying, based on the manifest, the command buffer and the associated data structures to copy to the host memory; identifying, based on the manifest, the kernels to copy to local memory of the hardware accelerator; and patching addresses in the command buffer copied to the host memory with updated addresses of corresponding locations in the host memory.

IPC Classes  ?

  • G06F 9/50 - Allocation of resources, e.g. of the central processing unit [CPU]
  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline, look ahead
  • G06T 1/20 - Processor architectures; Processor configuration, e.g. pipelining
  • G06T 1/60 - Memory management

78.

NEIGHBORING GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING DISJOINED EPITAXIAL SOURCE OR DRAIN REGIONS

      
Application Number 18511604
Status Pending
Filing Date 2023-11-16
First Publication Date 2024-03-14
Owner Intel Corporation (USA)
Inventor
  • Guler, Leonard P.
  • Guha, Biswajeet
  • Ghani, Tahir
  • Sivakumar, Swaminathan

Abstract

Neighboring gate-all-around integrated circuit structures having disjoined epitaxial source or drain regions, and methods of fabricating neighboring gate-all-around integrated circuit structures having disjoined epitaxial source or drain regions, are described. For example, a structure includes first and second vertical arrangements of nanowires, the nanowires of the second vertical arrangement of nanowires having a horizontal width greater than a horizontal width of the nanowires of the first vertical arrangement of nanowires. First and second gate stacks are over the first and second vertical arrangements of nanowires, respectively. First epitaxial source or drain structures are at ends of the first vertical arrangement of nanowires, and second epitaxial source or drain structures are at ends of the second vertical arrangement of nanowires. An intervening dielectric structure is between neighboring ones of the first epitaxial source or drain structures and of the second epitaxial source or drain structures.

IPC Classes  ?

  • H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
  • H01L 21/8234 - MIS technology
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

79.

SCALABLE HIGH SPEED HIGH BANDWIDTH IO SIGNALING PACKAGE ARCHITECTURE AND METHOD OF MAKING

      
Application Number 18516579
Status Pending
Filing Date 2023-11-21
First Publication Date 2024-03-14
Owner Intel Corporation (USA)
Inventor
  • Ganesan, Sanka
  • Sankman, Robert L.
  • Sain, Arghya
  • Chavali, Sri Chaitra Jyotsna
  • Wang, Lijiang
  • Geyik, Cemil

Abstract

Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a package substrate, wherein the package substrate comprises a first routing architecture. In an embodiment, the electronic package further comprises a first die on the package substrate, a second die on the package substrate, wherein the first die is electrically coupled to the second die by a bridge embedded in the package substrate, and a routing patch on the package substrate. In an embodiment, the routing patch is electrically coupled to the second die, and wherein the routing patch comprises a second routing architecture that is different than the first routing architecture.

IPC Classes  ?

  • H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
  • H01L 23/498 - Leads on insulating substrates

80.

FULL WAFER DEVICE WITH BACK SIDE PASSIVE ELECTRONIC COMPONENTS

      
Application Number 17930801
Status Pending
Filing Date 2022-09-09
First Publication Date 2024-03-14
Owner Intel Corporation (USA)
Inventor
  • Sharma, Abhishek A.
  • Ghani, Tahir
  • Gomes, Wilfred
  • Murthy, Anand S.

Abstract

Described herein are full wafer devices that include passive devices formed in a power delivery structure. Power is delivered to the full wafer device on a backside of the full wafer device. A passive device in a backside layer is formed using an additive process that results in a seam running through the passive device. The seam may be, for example, an air gap, a change in material structure, or a region with a different chemical makeup from the surrounding passive device.

IPC Classes  ?

  • H01L 23/528 - Layout of the interconnection structure
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body

81.

FULL WAFER DEVICE WITH BACK SIDE INTERCONNECTS AND WAFER-SCALE INTEGRATION

      
Application Number 17930841
Status Pending
Filing Date 2022-09-09
First Publication Date 2024-03-14
Owner Intel Corporation (USA)
Inventor
  • Sharma, Abhishek A.
  • Ghani, Tahir
  • Gomes, Wilfred
  • Murthy, Anand S.
  • Suthram, Sagar

Abstract

Described herein are full wafer devices that include interconnect layers on a back side of the device. The backside interconnect layers couple together different dies of the full wafer device. The backside interconnect layers include an active layer that includes active devices, such as transistors. The active devices may act as switches, e.g., to control routing of signals between different dies of the full wafer device.

IPC Classes  ?

  • H01L 23/528 - Layout of the interconnection structure
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body

82.

PRIVACY PRESERVING DIGITAL PERSONAL ASSISTANT

      
Application Number 17931007
Status Pending
Filing Date 2022-09-09
First Publication Date 2024-03-14
Owner Intel Corporation (USA)
Inventor
  • Bottleson, Jeremy
  • Zamora Ramos, Ernesto
  • Race, Kylan
  • Dias Moreira De Souza, Fillipe
  • De Lassus, Hubert
  • Jin, Jingyi

Abstract

A method comprises receiving, from an input device, an input speech signal, encoding the input speech signal to generate a first homomorphically encrypted string, sending the homomorphically encrypted string to a remote device via communication link, receiving, from the remote device, a reply comprising a second homomorphically encrypted string, decoding the second homomorphically encrypted string into an output speech signal, and outputting the output speech signal on an audio output device.

IPC Classes  ?

  • H04L 9/00 - Arrangements for secret or secure communications; Network security protocols
  • G10L 15/26 - Speech to text systems
  • H04L 9/08 - Key distribution

83.

BLUETOOTH REPORT EVENTS FOR ULTRA LOW LATENCY

      
Application Number 17940049
Status Pending
Filing Date 2022-09-08
First Publication Date 2024-03-14
Owner Intel Corporation (USA)
Inventor
  • Haggai, Oren
  • Devadiga, Yashodhara
  • Balaban, Nir Yizhak
  • Desai, Prasanna

Abstract

The present disclosure relates to a method of managing a data transmission from a second device to a first device, the method including: determining a reference time point for the data transmission from the second device to the first device; determining a time offset associated with the second device, wherein the reference time point and the time offset define a starting time point for the second device to start the data transmission; and carrying out the data transmission from the second device to the first device in accordance with the starting time point, wherein the data transmission includes transmitting isochronous data from the second device to the first device.

IPC Classes  ?

  • H04W 4/80 - Services using short range communication, e.g. near-field communication [NFC], radio-frequency identification [RFID] or low energy communication

84.

EPITAXIAL REGIONS EXTENDING BETWEEN INNER GATE SPACERS

      
Application Number 17940194
Status Pending
Filing Date 2022-09-08
First Publication Date 2024-03-14
Owner Intel Corporation (USA)
Inventor
  • Chu, Tao
  • Xu, Guowei
  • Zhang, Feng
  • Hung, Ting-Hsiang
  • Lin, Chia-Ching

Abstract

Techniques are provided herein to form semiconductor devices having epitaxial growth laterally extending between inner spacer structures to mitigate issues caused by the inner spacer structures either being too thick or too thin. A directional etch is performed along the side of a multilayer fin to create a relatively narrow opening for a source or drain region to increase the usable fin space for forming the inner spacer structures. After the inner spacer structures are formed around ends of the semiconductor layers within the fin, the exposed ends of the semiconductor layers are laterally recessed inwards from the outermost sidewalls of the inner spacer structures. Accordingly, the epitaxial source or drain region is grown from the recessed semiconductor ends and thus fills in the recessed regions between the spacer structures.

IPC Classes  ?

  • H01L 29/66 - Types of semiconductor device
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/786 - Thin-film transistors

85.

SELECTIVE CHECKING FOR ERRORS

      
Application Number 17941960
Status Pending
Filing Date 2022-09-09
First Publication Date 2024-03-14
Owner Intel Corporation (USA)
Inventor
  • Guim Bernat, Francesc
  • Kumar, Karthik
  • Misra, Amruta

Abstract

An apparatus comprising first circuitry to process a request generated by a first device, the request specifying a memory address range of a second device to monitor for errors; and second circuitry to, based on a determination that a read request targets the memory address range of the second device, compare first data read from the second device with second data read from a memory to determine whether an error has occurred.

IPC Classes  ?

  • G06F 11/30 - Monitoring
  • G06F 11/07 - Responding to the occurrence of a fault, e.g. fault tolerance
  • G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens

86.

CURRENT AND HEAT BALANCING CONSTANT VOLTAGE CHARGING

      
Application Number 17942392
Status Pending
Filing Date 2022-09-12
First Publication Date 2024-03-14
Owner Intel Corporation (USA)
Inventor
  • Matsumura, Naoki
  • Carver, Colin
  • Schiff, Tod

Abstract

A constant voltage may be used during battery charging to reduce or avoid the formation of a dendrite, such as a stepped constant voltage. For each charging period, each level of the stepped constant voltage may be calculated to ensure a corresponding current level within each period remains below a safe current limit. A voltage transition between any two periods may occur in response to expiration of a predetermined time, or in response to a determination that the current level has fallen below a lower current limit. A current level during each period may be maintained such that the battery heat is maintained below a reference heat level, which may increase battery cycle life (e.g., battery capacity or maximum recharging cycles). The battery heat may be measured directly or indirectly, or may be estimated based on other measured or controlled values.

IPC Classes  ?

  • H02J 7/00 - Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
  • G01R 31/389 - Measuring internal impedance, internal conductance or related variables

87.

DYNAMIC VOLTAGE AND FREQUENCY SCALING FOR MEMORY IN HETEROGENEOUS CORE ARCHITECTURES

      
Application Number 17942415
Status Pending
Filing Date 2022-09-12
First Publication Date 2024-03-14
Owner Intel Corporation (USA)
Inventor
  • Begum, Rizwana
  • Phatak, Rohit Sharad
  • Heit, Eric
  • Lou, Xiangdong

Abstract

Embodiments described herein may include apparatus, systems, techniques, and/or processes that are directed to optimizing memory frequency based on the bandwidth and latency needs of heterogeneous processing cores in a computer system. According to various embodiments, adjustments to the frequency of memory may be applied differently depending on the type of core requesting more bandwidth and/or faster response. According to various embodiments, the frequency is increased more sparingly for energy-efficient cores, while the frequency is increased more generously for high-performance cores. Additionally, when memory traffic decreases, the frequency of memory is decreased more generously when the previous request for higher frequency was from an energy-efficient core than a high-performance core. By considering the type of core that is requesting more bandwidth and/or faster response, performance and power consumption may be more optimally balanced.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

88.

TEMPERATURE AND VOLTAGE INSENSITIVE CROSSTALK CANCELLATION

      
Application Number 17942516
Status Pending
Filing Date 2022-09-12
First Publication Date 2024-03-14
Owner Intel Corporation (USA)
Inventor Sumesaglam, Taner

Abstract

An improved circuit for crosstalk cancellation may be used to provide improved receiver crosstalk cancelation. These solutions may include a high-pass filter that is configured to be matched to victim path. These solutions may reduce or eliminate the use of a unity gain buffer and in-line high-pass filter, which may reduce design complexity and improve performance. These solutions provide crosstalk cancellation that requires less power, is less complex, is less sensitive to temperature and voltage, and is more effective at providing crosstalk cancellation. This improved crosstalk cancellation further provides channel eye height improvement, reduced EHI temperature sensitivity, reduced EHI voltage sensitivity, reduced design complexity, and reduced silicon circuit area.

IPC Classes  ?

  • G06F 13/38 - Information transfer, e.g. on bus
  • H03K 5/1252 - Suppression or limitation of noise or interference

89.

WIDE CHANNEL DIODE STRUCTURE INCLUDING SUB-FIN

      
Application Number 17943819
Status Pending
Filing Date 2022-09-13
First Publication Date 2024-03-14
Owner Intel Corporation (USA)
Inventor
  • Thomson, Nicholas A.
  • Kolluru, Kalyan C.
  • Kar, Ayan
  • Liang, Chu-Hsin
  • Orr, Benjamin
  • Guha, Biswajeet
  • Greene, Brian
  • Lin, Chung-Hsun
  • Omar, Sabih U.
  • Joglekar, Sameer Jayanta

Abstract

An integrated circuit structure includes a sub-fin having (i) a first portion including a p-type dopant and (ii) a second portion including an n-type dopant. A first body of semiconductor material is above the first portion of the sub-fin, and a second body of semiconductor material is above the second portion of the sub-fin. In an example, the first portion of the sub-fin and the second portion of the sub-fin are in contact with each other, to form a PN junction of a diode. For example, the first portion of the sub-fin is part of an anode of the diode, and wherein the second portion of the sub-fin is part of a cathode of the diode.

IPC Classes  ?

  • H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/861 - Diodes

90.

TRANSISTOR DEVICES WITH INTEGRATED DIODES

      
Application Number 17943840
Status Pending
Filing Date 2022-09-13
First Publication Date 2024-03-14
Owner INTEL CORPORATION (USA)
Inventor
  • Thomson, Nicholas A.
  • Kar, Ayan
  • Kolluru, Kalyan C.
  • Kobrinksy, Mauro J.
  • Orr, Benjamin

Abstract

An integrated circuit structure includes a sub-fin having a first type of dopant, a first diffusion region having the first type of dopant and in contact with the sub-fin, and a second diffusion region and a third diffusion region having a second type of dopant and in contact with the sub-fin. The first type of dopant is one of p-type or n-type dopant, and where the second type of dopant is the other of the p-type or n-type dopant. A first body of semiconductor material extends from the second diffusion region to the third diffusion region, and a second body of semiconductor material extends from the first diffusion region towards the second diffusion region. The first diffusion region is a tap diffusion region contacting the sub-fin. In an example, the first diffusion region facilitates formation of a diode for electrostatic discharge (ESD) protection of the integrated circuit structure.

IPC Classes  ?

  • H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
  • H01L 23/528 - Layout of the interconnection structure
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/861 - Diodes

91.

MERGING ATOMICS TO THE SAME CACHE LINE

      
Application Number 17944542
Status Pending
Filing Date 2022-09-14
First Publication Date 2024-03-14
Owner Intel Corporation (USA)
Inventor
  • Ray, Joydeep
  • Appu, Abhishek R.
  • Shinde, Prathamesh Raghunath
  • Wiegert, John

Abstract

Embodiments described herein provide a technique to merge partial cache line writes to a cache memory. One embodiment provides a graphics processor comprising a graphics core, a cache coupled with the graphics core, and memory access circuitry to process memory access messages received from the graphics core. The memory access circuitry includes partial cache line write merge circuitry configured to merge a first partial write to a cache line of the cache with a second partial write to the cache line of the cache.

IPC Classes  ?

  • G06T 1/60 - Memory management
  • G06T 1/20 - Processor architectures; Processor configuration, e.g. pipelining

92.

TRANSISTOR OVER-VOLTAGE PROTECTION

      
Application Number 17993412
Status Pending
Filing Date 2022-11-23
First Publication Date 2024-03-14
Owner Intel Corporation (USA)
Inventor
  • Nedalgi, Dharmaray
  • Nirikhi, Lavanya Manohar

Abstract

An apparatus comprises a first supply node to provide a first voltage and a second supply node to provide a second voltage lower than the first voltage. First and second transistors, of a first conductivity type, are coupled in series at a first common node, wherein the first transistor is coupled to the first supply node, and the second transistor is coupled to an output node. Third and fourth transistors, of a second conductivity type, coupled in series at a second common node, wherein the fourth transistor is coupled to a third node that is to provide a third voltage, and the third transistor is coupled to the output node. First impedance circuitry is coupled to a gate terminal of the second transistor, the second supply node, and to a gate terminal of the first transistor.

IPC Classes  ?

  • H03K 17/082 - Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit

93.

ENHANCED IMAGE AND VIDEO OBJECT DETECTION USING MULTI-STAGE PARADIGM

      
Application Number CN2022118175
Publication Number 2024/050827
Status In Force
Filing Date 2022-09-09
Publication Date 2024-03-14
Owner INTEL CORPORATION (USA)
Inventor
  • Wei, Haoran
  • Guo, Ping
  • Wang, Peng
  • Wu, Xiangbin
  • Wu, Jiajie

Abstract

This disclosure describes systems, methods, and devices related to object detection in images. A device may input an image, representing an object, to a manual labeling learner system; identify, using the system, first coordinates of an upper left corner of a bounding box representing the object based on a heatmap indicative of a probability of the first coordinates representing the upper left corner; identify, using the system, second coordinates of a bottom right corner of the bounding box based on the first coordinates and a first distance regression map indicative of coordinate differences between the second coordinates and ground truth coordinates input to the machine learning model as training data; generate, using the system, adjustments to the first coordinates and the second coordinates based on a second regression map; and generate, using the system, the adjusted first and second coordinates, the bounding box.

IPC Classes  ?

  • G06V 10/20 - Image preprocessing
  • G06T 7/246 - Analysis of motion using feature-based methods, e.g. the tracking of corners or segments
  • H04L 27/00 - Modulated-carrier systems

94.

HARDWARE APPARATUSES AND METHODS TO SWITCH SHADOW STACK POINTERS

      
Application Number 18324788
Status Pending
Filing Date 2023-05-26
First Publication Date 2024-03-07
Owner Intel Corporation (USA)
Inventor
  • Shanbhogue, Vedvyas
  • Brandt, Jason W.
  • Sahita, Ravi L.
  • Huntley, Barry E.
  • Patel, Baiju V.
  • Gupta, Deepak K.

Abstract

Methods and apparatuses relating to switching of a shadow stack pointer are described. In one embodiment, a hardware processor includes a hardware decode unit to decode an instruction, and a hardware execution unit to execute the instruction to: pop a token for a thread from a shadow stack, wherein the token includes a shadow stack pointer for the thread with at least one least significant bit (LSB) of the shadow stack pointer overwritten with a bit value of an operating mode of the hardware processor for the thread, remove the bit value in the at least one LSB from the token to generate the shadow stack pointer, and set a current shadow stack pointer to the shadow stack pointer from the token when the operating mode from the token matches a current operating mode of the hardware processor.

IPC Classes  ?

  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
  • G06F 9/46 - Multiprogramming arrangements
  • G06F 21/52 - Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems during program execution, e.g. stack integrity, buffer overflow or preventing unwanted data erasure

95.

APPARATUSES, METHODS, AND SYSTEMS FOR INSTRUCTIONS OF A MATRIX OPERATIONS ACCELERATOR

      
Application Number 18360793
Status Pending
Filing Date 2023-07-27
First Publication Date 2024-03-07
Owner Intel Corporation (USA)
Inventor
  • Gradstein, Amit
  • Rubanovich, Simon
  • Meller, Sagi
  • Kharouf, Saeed
  • Berger, Gavri
  • Sperber, Zeev
  • Yallouz, Jose
  • Schneider, Ron

Abstract

Systems, methods, and apparatuses relating to a matrix operations accelerator are described. In one embodiment, a processor includes a matrix operations accelerator circuit that includes a two-dimensional grid of fused multiply accumulate circuits that is switchable to a scheduling mode for execution of a decoded single instruction where the matrix operations accelerator circuit loads a first buffer of the two-dimensional grid of fused multiply accumulate circuits from a first plurality of registers that represents a first input two-dimensional matrix, checks if a second buffer of the two-dimensional grid of fused multiply accumulate circuits stores an immediately prior input two-dimension matrix that is the same as a second input two-dimensional matrix from a second plurality of registers that represents the first input two-dimensional matrix, and when the second buffer of the two-dimensional grid of fused multiply accumulate circuits stores the immediately prior input two-dimension matrix, from execution of a previous instruction, that is the same as the second input two-dimensional matrix: prevents reclamation of the second buffer between execution of the previous instruction and the decoded single instruction, performs an operation on the first input two-dimensional matrix from the first buffer and the immediately prior input two-dimension matrix from the second buffer to produce a resultant, and stores the resultant in resultant storage, and when the second buffer of the two-dimensional grid of fused multiply accumulate circuits does not store the immediately prior input two-dimension matrix, from execution of the previous instruction, that is the same as the second input two-dimensional matrix: loads the second input two-dimensional matrix into the second buffer of the two-dimensional grid of fused multiply accumulate circuits, performs the operation on the first input two-dimensional matrix from the first buffer and the second input two-dimension matrix from the second buffer to produce a resultant, and stores the resultant in the resultant storage.

IPC Classes  ?

  • G06F 17/16 - Matrix or vector computation
  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline, look ahead

96.

TECHNIQUES FOR ARTIFICIAL INTELLIGENCE CAPABILITIES AT A NETWORK SWITCH

      
Application Number 18375934
Status Pending
Filing Date 2023-10-02
First Publication Date 2024-03-07
Owner Intel Corporation (USA)
Inventor
  • Guim Bernat, Francesc
  • Prabhakaran, Suraj
  • Doshi, Kshitij A.
  • Ganesh, Brinda
  • Verrall, Timothy

Abstract

Examples include techniques for artificial intelligence (AI) capabilities at a network switch. These examples include receiving a request to register a neural network for loading to an inference resource located at the network switch and loading the neural network based on information included in the request to support an AI service to be provided by users requesting the AI service.

IPC Classes  ?

  • H04L 41/16 - Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks using machine learning or artificial intelligence
  • G06N 3/04 - Architecture, e.g. interconnection topology
  • G06N 5/04 - Inference or reasoning models
  • H04L 41/0816 - Configuration setting characterised by the conditions triggering a change of settings the condition being an adaptation, e.g. in response to network events
  • H04L 41/5009 - Determining service level performance parameters or violations of service level contracts, e.g. violations of agreed response time or mean time between failures [MTBF]
  • H04L 41/5019 - Ensuring fulfilment of SLA
  • H04L 41/5051 - Service on demand, e.g. definition and deployment of services in real time

97.

TECHNIQUES FOR DECOUPLED ACCESS-EXECUTE NEAR-MEMORY PROCESSING

      
Application Number 18388797
Status Pending
Filing Date 2023-11-10
First Publication Date 2024-03-07
Owner Intel Corporation (USA)
Inventor
  • Akin, Berkin
  • Alameldeen, Alaa R.

Abstract

Techniques for decoupled access-execute near-memory processing include examples of first or second circuitry of a near-memory processor receiving instructions that cause the first circuitry to implement system memory access operations to access one or more data chunks and the second circuitry to implement compute operations using the one or more data chunks.

IPC Classes  ?

  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode

98.

DATA PROCESSING NEAR DATA STORAGE

      
Application Number 18389525
Status Pending
Filing Date 2023-11-14
First Publication Date 2024-03-07
Owner Intel Corporation (USA)
Inventor
  • Shah, Nilesh N.
  • Chauhan, Chetan
  • Tomishima, Shigeki
  • Hassan, Nahid
  • Ling, Andrew Chaang

Abstract

Examples herein relate to a solid state drive that includes a media, first circuitry, and second circuitry. In some examples, the first circuitry is to execute one or more commands. In some examples, the second circuitry is to receive a configuration of at one type of command, where the configuration is to define an amount of media bandwidth allocated for the at one type of command; receive a command; and assign the received command to the first circuitry for execution.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers
  • G06N 5/04 - Inference or reasoning models
  • G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or

99.

DEVICE, SYSTEM AND METHOD OF SIMULTANEOUSLY COMMUNICATING WITH A GROUP OF WIRELESS COMMUNICATION DEVICES

      
Application Number 18466530
Status Pending
Filing Date 2023-09-13
First Publication Date 2024-03-07
Owner INTEL CORPORATION (USA)
Inventor
  • Gong, Michelle X.
  • Stacey, Robert J.

Abstract

Some demonstrative embodiments include devices, systems and/or methods of simultaneously communicating with a group of wireless communication devices. For example, a device may include a wireless communication unit to communicate with at least one group of a plurality of wireless communication devices over a wireless communication medium, wherein the wireless communication unit is to reserve the wireless communication medium for a time period, during which the wireless communication unit is to simultaneously transmit two or more different wireless communication transmissions to two or more wireless communication devices of the group, respectively. Other embodiments are described and claimed.

IPC Classes  ?

  • H04B 7/06 - Diversity systems; Multi-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station
  • H04B 7/0417 - Feedback systems
  • H04W 72/30 - Resource management for broadcast services
  • H04W 74/08 - Non-scheduled access, e.g. random access, ALOHA or CSMA [Carrier Sense Multiple Access]

100.

COMPRESSION FOR DEEP LEARNING IN CASE OF SPARSE VALUES MAPPED TO NON-ZERO VALUE

      
Application Number 18466981
Status Pending
Filing Date 2023-09-14
First Publication Date 2024-03-07
Owner Intel Corporation (USA)
Inventor
  • Singh, Ajit
  • Daga, Bharat
  • Behar, Michael

Abstract

Embodiments described herein provide a processing apparatus comprising compute circuitry to generate neural network data for a convolutional neural network (CNN) and write the neural network data to a memory buffer. The compute circuitry additionally includes a direct memory access (DMA) controller including a hardware codec having encode circuitry and a decode circuitry. The DMA controller reads the neural network data from the memory buffer, encode the neural network data via the encode circuit, writes encoded neural network data to a memory device coupled with the processing apparatus, writes metadata for the encoded neural network data to the memory device coupled with the processing apparatus, and decodes encoded neural network data via the decode circuit in response to a request from the compute circuitry.

IPC Classes  ?

  • G06N 5/046 - Forward inferencing; Production systems
  • G06F 13/10 - Program control for peripheral devices
  • G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
  • G06F 17/16 - Matrix or vector computation
  • G06N 3/04 - Architecture, e.g. interconnection topology
  • G06N 3/08 - Learning methods
  • G06N 20/00 - Machine learning
  • G06T 9/00 - Image coding
  • G06T 15/20 - Perspective computation
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