Kioxia Corporation

Japan

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G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS 1,475
G06F 3/06 - Digital input from, or digital output to, record carriers 1,190
H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels 1,011
G11C 16/26 - Sensing or reading circuits; Data output circuits 877
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1.

NON-VOLATILE STORAGE DEVICE OFFLOADING OF HOST TASKS

      
Application Number 17954987
Status Pending
Filing Date 2022-09-28
First Publication Date 2024-03-28
Owner Kioxia Corporation (Japan)
Inventor Saluja, Mohinder

Abstract

Various implementations relate to receiving, by a non-volatile memory device from a host, a host command include device context information of non-volatile memory devices. The device context includes an address of a buffer of each non-volatile memory device. In response to receiving the host command, portions of host data are divided among the non-volatile memory devices. The non-volatile memory device sends to the host a transfer request indicating transfer of each portion of the host data to a respective one of the non-volatile memory devices. The non-volatile memory device sends to another non-volatile memory device a peer command based on the device context information.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

2.

NON-VOLATILE STORAGE DEVICE OFFLOADING OF HOST TASKS

      
Application Number 17955040
Status Pending
Filing Date 2022-09-28
First Publication Date 2024-03-28
Owner Kioxia Corporation (Japan)
Inventor Saluja, Mohinder

Abstract

Various implementations relate to grouping a plurality of non-volatile memory devices into at least one first group, determining that a number of the at least one first group is greater than 1, selecting a first leader device from first non-volatile memory devices in each of the at least one first group, and determining first result data by performing an operation based on first data from at least one of the first non-volatile memory devices in each of the at least one first group.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

3.

STORAGE SYSTEM, STORAGE APPARATUS, AND STORAGE METHOD

      
Application Number 18458757
Status Pending
Filing Date 2023-08-30
First Publication Date 2024-03-28
Owner Kioxia Corporation (Japan)
Inventor Akiyama, Haruhiko

Abstract

A storage system includes a storage apparatus that includes a storage circuit storing key-value data including a key-value pair, and a controller, a host apparatus connected to the storage apparatus and a recording medium. The host apparatus transmits a first command and input data including first information to the controller. In response to the first command, the controller updates the first information to generate second information, reads the key-value data from the storage circuit, generates output data including the key-value data and the second information associated with the key-value data, and transmits the output data to the host apparatus. The host apparatus stores the output data into the recording medium.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

4.

SEMICONDUCTOR MEMORY DEVICE

      
Application Number 18460262
Status Pending
Filing Date 2023-09-01
First Publication Date 2024-03-28
Owner Kioxia Corporation (Japan)
Inventor Takahashi, Eietsu

Abstract

A semiconductor memory device includes: a first bit line connected to a first string including memory cell transistors; a second bit line connected to a second string including memory cell transistors; a source line connected to the first string and the second string; a word line connected to gates of the memory cell transistors in same rows of the first and strings; a voltage generation circuit configured to apply a first voltage to the first bit line according to a first target level, apply a second voltage to the second bit line according to a second target level, and apply a third voltage to the source line; and a row decoder configured to apply a fourth voltage to the word line to which a first memory cell transistor of the first string and a second memory cell transistor of the second string are connected during a verification operation.

IPC Classes  ?

  • G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
  • G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • G11C 16/08 - Address circuits; Decoders; Word-line control circuits
  • G11C 16/26 - Sensing or reading circuits; Data output circuits

5.

INFORMATION PROCESSING APPARATUS AND INFORMATION PROCESSING METHOD

      
Application Number 18456209
Status Pending
Filing Date 2023-08-25
First Publication Date 2024-03-28
Owner Kioxia Corporation (Japan)
Inventor
  • Yoshinaga, Yuma
  • Maesono, Atsushi
  • Torii, Osamu
  • Tomioka, Shinichiro
  • Manabe, Shinichiro

Abstract

An information processing apparatus that updates a regression coefficient parameter based on a predetermined objective function including a regularization term for each of a plurality of elements characterized by a task and a feature value, the information processing apparatus comprising processing circuitry. The processing circuitry selects an element which is an update target of the regression coefficient parameter from the plurality of elements, fixes a value of the regularization term of an unselected element, selects a calculation expression for updating a regression coefficient parameter of the selected element based on a regression coefficient parameter of the unselected element, and updates the regression coefficient parameter of the selected element based on the selected calculation expression.

IPC Classes  ?

  • G05B 19/042 - Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors

6.

SEMICONDUCTOR MEMORY DEVICE

      
Application Number 18458891
Status Pending
Filing Date 2023-08-30
First Publication Date 2024-03-28
Owner Kioxia Corporation (Japan)
Inventor Maejima, Hiroshi

Abstract

A semiconductor memory device includes first, second, and third chips. The first chip includes a first memory cell. The second chip includes a second memory cell. The third chip includes a row decoder and a sense amplifier. The first and second memory cells are commonly connected to the row decoder via a first word line. The first and second memory cells are connected to the sense amplifier via first and second bit lines, respectively. The sense amplifier includes a first node selectively connectable to the first and second bit lines. The sense amplifier is configured to sense a voltage at the first node to read data in the first memory cell when the first node is connected to the first bit line and sense the voltage at the first node to read data in the second memory cell when the first node is connected to the second bit line.

IPC Classes  ?

  • G11C 16/26 - Sensing or reading circuits; Data output circuits
  • G11C 7/06 - Sense amplifiers; Associated circuits
  • G11C 16/08 - Address circuits; Decoders; Word-line control circuits
  • G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention

7.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

      
Application Number 18461232
Status Pending
Filing Date 2023-09-05
First Publication Date 2024-03-28
Owner Kioxia Corporation (Japan)
Inventor
  • Sahara, Eri
  • Omodaka, Ai

Abstract

In one embodiment, a semiconductor device includes a stacked film including a plurality of first insulators and a plurality of electrode layers that are alternately stacked in a first direction. The device includes a first plug provided on a first electrode layer among the plurality of electrode layers, and having a tube shape extending in the first direction. The device includes a second insulator provided in the first plug and the first electrode layer, and having a columnar shape extending in the first direction. Furthermore, a diameter of a side face of the first plug enclosing the second insulator is larger than a diameter of a side face of the first electrode layer enclosing the second insulator.

IPC Classes  ?

  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
  • H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout

8.

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE

      
Application Number 18458023
Status Pending
Filing Date 2023-08-29
First Publication Date 2024-03-28
Owner Kioxia Corporation (Japan)
Inventor
  • Itakura, Satoru
  • Miura, Masayuki

Abstract

According to one embodiment, a method of manufacturing a semiconductor device includes placing a first semiconductor element on a wiring board, forming a first mask having an opening on the wiring board so that the first semiconductor element is positioned in the opening, putting a liquid first resin precursor into the opening of the first mask, curing the first resin precursor to obtain a first resin layer, and then removing the first mask.

IPC Classes  ?

  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 21/027 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or
  • H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
  • H01L 23/29 - Encapsulation, e.g. encapsulating layers, coatings characterised by the material

9.

MEMORY SYSTEM AND CONTROL METHOD

      
Application Number 18459365
Status Pending
Filing Date 2023-08-31
First Publication Date 2024-03-28
Owner Kioxia Corporation (Japan)
Inventor Tadokoro, Mitsunori

Abstract

According to one embodiment, a memory system includes a storage unit with a plurality of pages of a plurality of nonvolatile memory cells, each page having a lower page unit and a higher page unit. A correction processing unit for correcting errors in the data stored in the storage unit on a page-by-page basis is provided. A controller is further configured to track a storage location of multi-level data in the storage unit, detect pages for which data is stored only in the lower page unit, cause the correction processing unit to generate an error correction code for the detected page units in an encoding frame, and write the error correction code to a next page unit among the plurality of pages in a set writing order after the last lower page unit in the encoding frame.

IPC Classes  ?

  • G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
  • G06F 11/14 - Error detection or correction of the data by redundancy in operation, e.g. by using different operation sequences leading to the same result

10.

SEMICONDUCTOR STORAGE DEVICE

      
Application Number 18327446
Status Pending
Filing Date 2023-06-01
First Publication Date 2024-03-28
Owner Kioxia Corporation (Japan)
Inventor Fujise, Shinya

Abstract

A semiconductor storage device of an embodiment includes a plurality of conductive layers and a plurality of insulation layers, a first contact plug, and a second contact plug. The plurality of conductive layers and the plurality of insulation layers are alternately stacked in a first direction. The first contact plug contacts a first conductive layer included in the plurality of conductive layers and extends in the first direction. The second contact plug contacts a second conductive layer that is a conductive layer directly above the first conductive layer of the plurality of conductive layers and extends in the first direction through the first conductive layer. The second contact plug includes a second conductor layer, and an insulation layer that is provided between the second conductor layer and the first conductive layer and is configured to insulate the second conductor layer and the first conductive layer.

IPC Classes  ?

  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
  • H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass

11.

SEMICONDUCTOR CIRCUIT AND SEMICONDUCTOR DEVICE

      
Application Number JP2022035382
Publication Number 2024/062599
Status In Force
Filing Date 2022-09-22
Publication Date 2024-03-28
Owner KIOXIA CORPORATION (Japan)
Inventor
  • Matsuno, Junya
  • Hirashima, Yasuhiro
  • Kouchi, Toshiyuki

Abstract

A semiconductor circuit according to an embodiment includes transistors PM10 to PM12, NM10, and NM11, and a constant current source CS10. The transistor PM10 is connected between nodes VDD and ND10, and a gate end is connected to the node ND 10 through a resistor R10. The transistor PM11 is connected between the nodes VDD and ND11, and a gate end is connected to the node ND10. The node ND11 is connected to an output node OUT. The transistor NM10 is connected between the nodes ND10 and ND12, and a gate end is connected to an input node IN. The transistor NM11 is connected between the nodes ND11 and ND12, and a gate end is connected to an input node /IN. One end and the other end of the constant current source CS10 are connected between the nodes ND12 and VSS. The transistor PM12 is connected between the node VDD and the input node /IN, and a gate end is connected to the gate end of the transistor PM10.

IPC Classes  ?

12.

COMPRESSION DEVICE AND COMPRESSION METHOD

      
Application Number 18208745
Status Pending
Filing Date 2023-06-12
First Publication Date 2024-03-28
Owner Kioxia Corporation (Japan)
Inventor
  • Fukazawa, Youhei
  • Kodama, Sho
  • Nakanishi, Keiri

Abstract

According to one embodiment, a compression device includes a substring generator and a match information generator. The substring generator receives generates substrings which are stored in a memory. Byte positions of the substrings are different from each other. The match information generator determines a first string, at least part thereof matching at least part of one of the substrings, and outputs match information. The match information includes a position of the memory storing the first string and a length of the at least part of the first string matching the at least part of one of the substrings.

IPC Classes  ?

  • H03M 7/30 - Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction

13.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

      
Application Number 18459841
Status Pending
Filing Date 2023-09-01
First Publication Date 2024-03-28
Owner Kioxia Corporation (Japan)
Inventor
  • Shiroshita, Naoya
  • Miura, Masayuki

Abstract

A semiconductor device includes: a wiring substrate; at least one first semiconductor element provided above the wiring substrate; a first resin layer configured to seal the first semiconductor element; and a second resin layer provided on an outer surface of the first resin layer. A Young's modulus of the second resin layer is greater than a Young's modulus of the first resin layer, and/or a linear thermal expansion coefficient of the second resin layer is greater than a linear thermal expansion coefficient of the first resin layer.

IPC Classes  ?

  • H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
  • H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 23/29 - Encapsulation, e.g. encapsulating layers, coatings characterised by the material

14.

SEMICONDUCTOR INTEGRATED CIRCUIT, SEMICONDUCTOR DEVICE, AND MEMORY SYSTEM

      
Application Number 18458775
Status Pending
Filing Date 2023-08-30
First Publication Date 2024-03-28
Owner Kioxia Corporation (Japan)
Inventor Usuda, Masayuki

Abstract

A semiconductor integrated circuit includes a first regulator configured to output a first output voltage at a predetermined level from a first output terminal, a second regulator configured to output a second output voltage at the predetermined level from a second output terminal connected to the first output terminal, and a control circuit. The control circuit is configured to turn on the second regulator and then turn off the first regulator such that the first and second regulators both remain on for a certain period of time when a regulator to be used is switched from the first regulator to the second regulator, and during the certain period of time, cause the second output voltage of the second regulator to be increased to a level higher than the predetermined level.

IPC Classes  ?

  • G11C 11/4074 - Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
  • G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
  • G11C 5/14 - Power supply arrangements

15.

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR STORAGE DEVICE

      
Application Number 18460486
Status Pending
Filing Date 2023-09-01
First Publication Date 2024-03-28
Owner Kioxia Corporation (Japan)
Inventor
  • Yamasawa, Kiyoe
  • Matsuda, Yasuyuki

Abstract

A latch group includes a first latch circuit, a second latch circuit, and a third latch circuit. A clock signal of which a signal value is inverted from a clock signal of the second latch circuit is input to the first latch circuit and the third latch circuit. A control circuit is configured to operate the latch group in a normal mode, and first and second test modes. The control circuit, while operating the latch group in a first test mode, transmits a control signal to the first switch circuit to connect the electrical path between the first data output terminal and the second data input terminal, and while operating the latch group in the second test mode, transmits a control signal to the second switch circuit to connect the electrical path between the second data output terminal and the third data input terminal.

IPC Classes  ?

  • G11C 29/12 - Built-in arrangements for testing, e.g. built-in self testing [BIST]

16.

SEMICONDUCTOR INTEGRATED CIRCUIT, TRANSMITTER, AND SEMICONDUCTOR DEVICE

      
Application Number 18460086
Status Pending
Filing Date 2023-09-01
First Publication Date 2024-03-28
Owner Kioxia Corporation (Japan)
Inventor Yagi, Toshihiro

Abstract

A semiconductor integrated circuit includes a front stage circuit and a rear stage circuit. The rear stage circuit includes first, second, fifth, and sixth transistors and a plurality of seventh transistors. The front stage circuit includes first and second inverters and third and fourth transistors. The third transistor is between the first inverter and the rear stage circuit, and has a gate connected to a first power supply node. The fourth transistor is between the second inverter and the rear stage circuit, and has a gate connected to the first power supply node. A breakdown voltage of each of the third and fourth transistors in the front stage circuit is lower than that of the first, second, fifth, sixth, and seventh transistors in the rear stage circuit.

IPC Classes  ?

  • H02M 7/537 - Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters

17.

DATA GENERATION APPARATUS, DATA GENERATION METHOD, AND COMPUTER-READABLE STORAGE MEDIUM

      
Application Number 18332203
Status Pending
Filing Date 2023-06-09
First Publication Date 2024-03-28
Owner Kioxia Corporation (Japan)
Inventor
  • Kodera, Katsuyoshi
  • Mimotogi, Shoji
  • Magoshi, Shunko
  • Ogawa, Ryuji
  • Kimura, Taiki

Abstract

A data generation apparatus of one embodiment includes a processing unit, an evaluation unit, and a conversion unit. The processing unit designs, through optical proximity correction based on a target pattern formed on a substrate using the photomask, a mask pattern corresponding to the target pattern and including a plurality of rectangular regions. The evaluation unit evaluates the mask pattern using a cost function having, as a parameter, a jog length indicating a length of each of the rectangular regions included in the mask pattern in a first direction. The conversion unit converts mask pattern data indicating the mask pattern with an evaluation that meets a predetermined condition to drawing data corresponding to a variable shaped beam drawing process.

IPC Classes  ?

  • H01J 37/317 - Electron-beam or ion-beam tubes for localised treatment of objects for changing properties of the objects or for applying thin layers thereon, e.g. ion implantation

18.

METHOD OF MANAGING MANUFACTURING LINE

      
Application Number 18335682
Status Pending
Filing Date 2023-06-15
First Publication Date 2024-03-28
Owner Kioxia Corporation (Japan)
Inventor Tennoji, Teruhiko

Abstract

According to one embodiment, there is provided a method of managing a manufacturing line. The method comprises obtaining a capability variation characteristic of each resource based on a throughput result of a process area among multi process areas arranged in the manufacturing line, each of the process areas including a multi resources. The method comprises determining number of additional resources for achievement of a quota in the process area based on the number of resources in the process area and the obtained capability variation characteristic.

IPC Classes  ?

  • G05B 19/418 - Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control (DNC), flexible manufacturing systems (FMS), integrated manufacturing systems (IMS), computer integrated manufacturing (CIM)

19.

SEMICONDUCTOR MEMORY DEVICE

      
Application Number 18530418
Status Pending
Filing Date 2023-12-06
First Publication Date 2024-03-28
Owner KIOXIA CORPORATION (Japan)
Inventor Yoshida, Kiyomitsu

Abstract

According to one embodiment, a semiconductor memory device includes a first insulating layer; a first conductive layer provided in the first insulating layer and extending in the first direction; a second conductive layer extending in the first direction and provided adjacent to the first conductive layer in a second direction; and a contact plug coupled to one surface of the first conductive layer in a third direction. Thicknesses in the third direction of portions of the first and second conductive layers that overlap the contact plug in the third direction are smaller than thicknesses in the third direction of portions of the first and second conductive layers that do not overlap the contact plug in the third direction.

IPC Classes  ?

  • H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
  • H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
  • H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region

20.

NON-VOLATILE STORAGE DEVICE OFFLOADING OF HOST TASKS

      
Application Number 17955014
Status Pending
Filing Date 2022-09-28
First Publication Date 2024-03-28
Owner Kioxia Corporation (Japan)
Inventor Saluja, Mohinder

Abstract

Various implementations relate to receiving, by a first non-volatile memory device from a host, a host command including device context information of a plurality of non-volatile memory devices. The device context includes an address of a buffer of each of the plurality of non-volatile memory devices, in response to receiving the host command. The first non-volatile memory device divides portions of host data corresponding to the host command among the plurality of non-volatile memory devices. The first non-volatile memory device sends to the host a transfer request indicating transfer of each of the portions of the host data to a respective one of the plurality of non-volatile memory devices. The first non-volatile memory device sends to each of the plurality of non-volatile memory devices other than the first non-volatile memory device, a peer command based on the device context information.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

21.

TARGET PROCESSING DEVICE AND TARGET PROCESSING METHOD

      
Application Number 18164053
Status Pending
Filing Date 2023-02-03
First Publication Date 2024-03-21
Owner Kioxia Corporation (Japan)
Inventor
  • Motokawa, Takeharu
  • Sakurai, Noriko
  • Sakurai, Hideaki

Abstract

A target processing method includes: importing a target into a processing chamber; forming a film including carbon on the target using at least one of first ion including carbon and a first plasma including carbon; and removing the film by a reaction between a second plasma and the film, wherein the forming of the film and the removing of the film are alternately performed a number of times in the processing chamber without removing the target from the processing chamber.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • C01B 32/05 - Preparation or purification of carbon not covered by groups , , ,
  • G03F 1/58 - Absorbers, e.g. opaque materials having two or more different absorber layers, e.g. stacked multilayer absorbers
  • G03F 1/80 - Etching

22.

SEMICONDUCTOR STORAGE DEVICE

      
Application Number 18178460
Status Pending
Filing Date 2023-03-03
First Publication Date 2024-03-21
Owner Kioxia Corporation (Japan)
Inventor
  • Nihei, Ryota
  • Matsuo, Koji

Abstract

According to one embodiment, a semiconductor storage device has first and second gate electrodes extending in one direction. A first semiconductor layer is between the first gate electrode and the second gate electrode. A second semiconductor layer is also between the first semiconductor layer and the second gate electrode but separated from the first semiconductor layer. A third semiconductor layer is between the first gate electrode and the second gate electrode but is spaced from the first semiconductor layer by a gap. A first charge trapping layer is between the first gate electrode and the first semiconductor layer. A second charge trapping layer is between the second gate electrode and the second semiconductor layer. A third charge trapping layer is between the first gate electrode and the third semiconductor layer.

IPC Classes  ?

  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
  • H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND

23.

MEMORY SYSTEM

      
Application Number 18162275
Status Pending
Filing Date 2023-01-31
First Publication Date 2024-03-21
Owner Kioxia Corporation (Japan)
Inventor
  • Wakutsu, Takashi
  • Nakazato, Yasuaki
  • Nakano, Takeshi

Abstract

A controller assigns a first plurality of blocks among a plurality of blocks provided in a non-volatile memory to a first area, assigns a second plurality of blocks to a second area, and assigns a third plurality of blocks to a third area. The controller uses each block assigned to the first area in a first mode, uses each block assigned to the second area in a second mode in which the number of bits of data written in each memory cell is larger than that in the first mode, and uses each block assigned to the third area in the first mode or the second mode. The controller writes data received from a host device to an area that corresponds to a designation from the host device out of the first area and the third area. The controller transcribes valid data written to the first area and the third area to the second area.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

24.

MEMORY SYSTEM

      
Application Number 18176452
Status Pending
Filing Date 2023-02-28
First Publication Date 2024-03-21
Owner Kioxia Corporation (Japan)
Inventor
  • Kantani, Tomoyuki
  • Fujita, Kousuke
  • Endo, Iku

Abstract

A memory system includes a memory controller configured to write data in a first mode to a first block of a first area of a non-volatile memory. The first mode is a write mode for writing data with a first number of bits per memory cell. The memory controller is further configured to execute copy processing on the data written in the first mode to the first block, by writing system data written in the first block to a second block of the first area in the first mode and writing user data written in the first block to a third block of a second area of the non-volatile memory in the second mode. The second mode is a write mode for writing data with a second number of bits larger than the first number of bits per memory cell.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

25.

SEMICONDUCTOR MEMORY DEVICE

      
Application Number 18177704
Status Pending
Filing Date 2023-03-02
First Publication Date 2024-03-21
Owner Kioxia Corporation (Japan)
Inventor
  • Sakaguchi, Natsuki
  • Maeda, Takashi
  • Funatsuki, Rieko
  • Shiga, Hidehiro

Abstract

A control circuit of a semiconductor memory device performs a write operation on a memory cell transistor of the semiconductor memory device by performing a first pulse application operation of lowering a threshold voltage of the memory cell transistor, a precharge operation, and then a second pulse application operation. In the precharge operation, in a state in which first and second select transistors connected to the memory cell transistor are turned on, a bit line connected to the memory cell transistor is charged by applying a ground voltage to a word line connected to a gate of the memory cell transistor and applying a voltage higher than the ground voltage to a source line. In the second pulse application operation, in a state in which the first select transistor is turned on and the second select transistor is turned off, a program voltage is applied to the word line.

IPC Classes  ?

  • G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • G11C 7/06 - Sense amplifiers; Associated circuits
  • G11C 16/24 - Bit-line control circuits

26.

SEMICONDUCTOR MANUFACTURING APPARATUS AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD

      
Application Number 18171992
Status Pending
Filing Date 2023-02-21
First Publication Date 2024-03-21
Owner Kioxia Corporation (Japan)
Inventor
  • Arakawa, Shohei
  • Osada, Yuta

Abstract

A semiconductor manufacturing apparatus includes: a chamber including a top plate; a holder provided in the chamber and configured to place a substrate; a high-frequency power source configured to apply high-frequency power to the holder; a gas supply pipe configured to supply a gas to the chamber; a gas discharge pipe configured to discharge a gas from the chamber; and a plurality of lift pins configured to move the substrate in a direction away from the holder to the top plate, which allows tip ends of the lift pins to move from an upper surface of the holder to a position with a first distance, wherein the first distance is equal to or greater than about 70% of a second distance between the upper surface of the holder and the top plate.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches

27.

SEMICONDUCTOR INTEGRATED CIRCUIT, METHOD OF CONTROLLING SEMICONDUCTOR INTEGRATED CIRCUIT, AND CIRCUIT SYSTEM

      
Application Number 18175456
Status Pending
Filing Date 2023-02-27
First Publication Date 2024-03-21
Owner Kioxia Corporation (Japan)
Inventor Sato, Kiyohito

Abstract

In a semiconductor integrated circuit, a first oscillation circuit receives a first clock signal and outputs a second clock signal synchronized with the first clock signal in frequency and phase. A second oscillation circuit receives a control signal and outputs a third clock signal having a frequency corresponding to the received control signal. A detection circuit detects a frequency difference between the second clock signal and the third clock signal. A determination circuit determines whether a frequency locked state is established between the first clock signal and the second clock signal. A control circuit varies the control signal, such that the frequency difference decreases while the frequency locked state has not been established and increases after the frequency locked state is established.

IPC Classes  ?

  • H03L 7/099 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop

28.

MEMORY SYSTEM

      
Application Number 18172562
Status Pending
Filing Date 2023-02-22
First Publication Date 2024-03-21
Owner Kioxia Corporation (Japan)
Inventor Miura, Takeshi

Abstract

A memory system includes a nonvolatile memory including first and second planes each including a plurality of memory cells, and a memory controller configured to transmit commands to the first and second planes via a first signal line and receive data from the first and second planes via a second signal line. The memory controller is configured such that, when the first plane is executing a first process, the memory controller suspends transmission of a first command instructing reservation of the first process to the second plane until a first condition is satisfied.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

29.

PROCESSING APPARATUS USING LASER, METHOD OF LASER LIFT-OFF AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

      
Application Number 18332508
Status Pending
Filing Date 2023-06-09
First Publication Date 2024-03-21
Owner Kioxia Corporation (Japan)
Inventor
  • Okubo, Takuro
  • Hayashi, Hidekazu

Abstract

A processing apparatus using laser according to an embodiment includes a stage configured to hold a substrate and rotate, and a laser irradiation apparatus capable of moving in a radial direction of the rotation. The laser irradiation apparatus includes a control unit configured to control an output of an infrared pulsed laser so that L1/L2 satisfies 1.2 or more and 10 or less when a distance between laser spots adjacent to each other in a rotation direction of the stage is L1 and a distance between laser spots adjacent to each other in the radial direction of the rotation is L2.

IPC Classes  ?

  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
  • B23K 26/073 - Shaping the laser spot
  • B23K 26/08 - Devices involving relative movement between laser beam and workpiece
  • B23K 26/18 - Working by laser beam, e.g. welding, cutting or boring using absorbing layers on the workpiece, e.g. for marking or protecting purposes
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices

30.

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR MEMORY DEVICE

      
Application Number 18457645
Status Pending
Filing Date 2023-08-29
First Publication Date 2024-03-21
Owner Kioxia Corporation (Japan)
Inventor
  • Matsushita, Saori
  • Shioda, Tomonari
  • Yamanaka, Takanori
  • Fujitsuka, Ryota

Abstract

A semiconductor memory device includes: a stacked body in which a plurality of conductive layers and a plurality of insulating layers are stacked one by one alternately; and a pillar that extends in the stacked body in a stacking direction of the stacked body and includes a memory cell formed at each of intersections with the plurality of conductive layers, in which the pillar includes a semiconductor layer extending in the stacking direction, a silicon oxynitride layer covering a side wall of the semiconductor layer, a silicon nitride layer covering a side wall of the silicon oxynitride layer, and a silicon oxide layer covering a side wall of the silicon nitride layer, in which the silicon oxynitride layer has a hydrogen concentration of 1×1020 atm/cc or less in terms of average value.

IPC Classes  ?

  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

31.

MEMORY DEVICE

      
Application Number 18306654
Status Pending
Filing Date 2023-04-25
First Publication Date 2024-03-21
Owner Kioxia Corporation (Japan)
Inventor
  • Futatsuyama, Takuya
  • Abe, Kenichi

Abstract

A memory device includes a semiconductor column extending above a substrate, a first conductive layer on a first side of the semiconductor column, a second conductive layer on a second side of the semiconductor column, opposite to the first conductive layer, a third conductive layer above or below the first conductive layer and on the first side of the semiconductor column, a fourth conductive layer on the second side of the semiconductor column, opposite to the third conductive layer, and a bit line connected to the semiconductor column. During reading in which a positive voltage is applied to the bit line, first, second, third, and fourth voltages applied to the first, second, third, and fourth conductive layers, respectively, wherein the first voltage and the third voltage are higher than each of the second voltage and the fourth voltage, and the third voltage is higher than the first voltage.

IPC Classes  ?

  • G11C 16/26 - Sensing or reading circuits; Data output circuits
  • G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • G11C 16/08 - Address circuits; Decoders; Word-line control circuits
  • G11C 16/10 - Programming or data input circuits
  • H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND

32.

PLASMA PROCESSING DEVICE, PLASMA PROCESSING METHOD, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD

      
Application Number 18450625
Status Pending
Filing Date 2023-08-16
First Publication Date 2024-03-21
Owner Kioxia Corporation (Japan)
Inventor Sasaki, Toshiyuki

Abstract

A plasma processing device includes a chamber, a plurality of direct current power supplies, and a controller. The direct current power supplies are provided in an upper portion and on a side wall of the chamber, wherein the direct current power supplies are configured to operate individually. The controller is configured to control the direct current power supplies such that the direct current power supplies apply respective direct current voltages independent of each other.

IPC Classes  ?

33.

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR MEMORY DEVICE

      
Application Number 18460203
Status Pending
Filing Date 2023-09-01
First Publication Date 2024-03-21
Owner Kioxia Corporation (Japan)
Inventor Nagashima, Satoshi

Abstract

A semiconductor memory device includes a first stacked body, a second stacked body, an interposed portion, and a columnar body. The interposed portion is disposed between the first stacked body and the second stacked body. The columnar body includes a first columnar portion extending in a first direction inside the first stacked body, a second columnar portion extending in the first direction inside the second stacked body, and a connection portion disposed in the interposed portion and connecting the first columnar portion to the second columnar portion. At least part of the interposed portion has a first layer containing a first insulating material, a second layer disposed between the first layer and the second stacked body in the first direction and containing the first insulating material, and a third layer disposed between the first layer and the second layer in the first direction and containing a first material different from the first insulating material.

IPC Classes  ?

  • G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
  • H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
  • H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND

34.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

      
Application Number 18334720
Status Pending
Filing Date 2023-06-14
First Publication Date 2024-03-21
Owner Kioxia Corporation (Japan)
Inventor Sonoda, Yasuyuki

Abstract

A semiconductor device includes: a first conductor; a second conductor; an oxide semiconductor layer provided between the first conductor and the second conductor and extending in a first direction; a first wiring extending in a second direction across the first direction and surrounding the oxide semiconductor layer; an insulating film provided between the first wiring and the oxide semiconductor layer; a second wiring provided on the second conductor and extending in a third direction across each of the first direction and the second direction; a first insulating layer provided on a side surface of the second wiring and having a first void; and a second insulating layer provided on the first insulating layer and having a second void.

IPC Classes  ?

  • H10B 12/00 - Dynamic random access memory [DRAM] devices

35.

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

      
Application Number 18446583
Status Pending
Filing Date 2023-08-09
First Publication Date 2024-03-21
Owner Kioxia Corporation (Japan)
Inventor
  • Sumiya, Mariko
  • Yamamoto, Ryosuke

Abstract

A method for manufacturing a semiconductor device includes: forming a release layer including a first polycrystalline semiconductor layer provided on a first substrate, and a second polycrystalline semiconductor layer provided between the first substrate and the first polycrystalline semiconductor layer and having a p-type impurity concentration which is lower than that of the first polycrystalline semiconductor layer, and an n-type impurity concentration which is higher than that of the first polycrystalline semiconductor layer; subjecting the first polycrystalline semiconductor layer to anodic chemical conversion to form a first porous layer; forming a first device layer on the first porous layer; and bonding together the first device layer and a second device layer provided on a second substrate.

IPC Classes  ?

  • H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/20 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region

36.

SEMICONDUCTOR STORAGE DEVICE

      
Application Number 18460496
Status Pending
Filing Date 2023-09-01
First Publication Date 2024-03-21
Owner Kioxia Corporation (Japan)
Inventor
  • Sakurai, Katsuaki
  • Tategami, Tooru

Abstract

A semiconductor storage device includes a first region including a level shifter, a second region including a level shifter, a power input pad, and an internal power generation circuit configured to generate an internal power supply voltage using a first power supply voltage supplied through the power input pad and supply the internal power supply voltage to the first and second regions. The internal power generation circuit separately transmits a first signal to the level shifter of the first region for triggering a start of a first operation of the first region and a second signal to the level shifter of the second region for triggering a start of a second operation of the second region.

IPC Classes  ?

  • G11C 16/30 - Power supply circuits
  • G11C 16/08 - Address circuits; Decoders; Word-line control circuits

37.

MEMORY SYSTEM

      
Application Number 18460284
Status Pending
Filing Date 2023-09-01
First Publication Date 2024-03-21
Owner Kioxia Corporation (Japan)
Inventor
  • Yamaguchi, Kensaku
  • Iwasaki, Kiyotaka
  • Takemoto, Takashi
  • Oikawa, Kohei

Abstract

A memory system includes a non-volatile memory and a controller. The controller is configured to perform a write operation of a first data cluster and a first partial overwrite operation of the first data cluster with first overwrite data. The write operation includes compressing and then encrypting the first data cluster, and writing the compressed and encrypted first data cluster into a first physical location of the non-volatile memory. The first partial overwrite operation includes encrypting the first overwrite data without performing compression, reading the compressed and encrypted first data cluster from the first physical location of the non-volatile memory, generating a first composite data cluster with the compressed and encrypted first data cluster read from the first physical location and the encrypted first overwrite data that is not compressed, and writing the first composite data cluster into a second physical location of the non-volatile memory.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

38.

SEMICONDUCTOR STORAGE DEVICE

      
Application Number 18360711
Status Pending
Filing Date 2023-07-27
First Publication Date 2024-03-21
Owner Kioxia Corporation (Japan)
Inventor Sasaki, Kenta

Abstract

According to one embodiment, a semiconductor storage device includes a first chip with a substrate and a second chip. The second chip has a memory cell array with wiring layers spaced apart from each other in a first direction and a memory pillar that penetrates the wiring layers in the first direction. Connection pads are in a boundary between the first and second chips. Contacts extend in the first direction from the connection pads. An insulator layer surrounds the contacts in a plane parallel to the substrate. A first member is adjacent to the insulator layer in the plane. The insulator layer separates the first member from the first contacts, and the first member has a stress value different from a stress value of the first insulator layer.

IPC Classes  ?

  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 23/528 - Layout of the interconnection structure
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
  • H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
  • H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
  • H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass

39.

SUBSTRATE PROCESSING METHOD AND SUBSTRATE PROCESSING DEVICE

      
Application Number 18333572
Status Pending
Filing Date 2023-06-13
First Publication Date 2024-03-21
Owner Kioxia Corporation (Japan)
Inventor
  • Tanabe, Mana
  • Umezawa, Kaori
  • Takai, Kosuke

Abstract

According to an embodiment, a substrate processing method includes forming a liquid film on a substrate including a first region provided with a first film on an outermost surface thereof and a second region provided with a second film on an outermost surface thereof, the first film and the second film being different from each other in material. The method further includes forming a solidified film by solidifying the liquid film. The method further includes causing the solidified film on the first region to melt prior to the solidified film on the second region.

IPC Classes  ?

  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches

40.

MAGNETORESISTANCE MEMORY DEVICE AND METHOD FOR MANUFACTURING MAGNETORESISTANCE MEMORY DEVICE

      
Application Number 18337576
Status Pending
Filing Date 2023-06-20
First Publication Date 2024-03-21
Owner Kioxia Corporation (Japan)
Inventor
  • Ahn, Hyung-Woo
  • Eeh, Young Min
  • Oikawa, Tadaaki
  • Isoda, Taiga

Abstract

A magnetoresistance memory device includes a lower electrode, a barrier layer, a variable resistance layer, an upper electrode, and a first layer stack. The lower electrode contains one of amorphous carbon and amorphous carbon nitride. The barrier layer is provided on the lower electrode and contains one of tungsten nitride (WN) and silicon tungsten nitride (WSiN). The variable resistance layer is provided on the barrier layer and contains a variable resistance material. The upper electrode is provided on the variable resistance layer and contains one of amorphous carbon and amorphous carbon nitride. The first layer stack is provided on the upper electrode and includes a first ferromagnetic layer, a second ferromagnetic layer, and an insulating layer between the first ferromagnetic layer and the second ferromagnetic layer.

IPC Classes  ?

41.

SEMICONDUCTOR STORAGE DEVICE

      
Application Number 18337589
Status Pending
Filing Date 2023-06-20
First Publication Date 2024-03-21
Owner Kioxia Corporation (Japan)
Inventor Date, Hiroki

Abstract

In one embodiment, a semiconductor storage device includes memory cell transistors, and a word line electrically connected to the memory cell transistors. The device further includes a voltage generator configured to generate a first voltage transferred to the word line, the voltage generator including a voltage divider configured to divide the first voltage with first and second resistance elements, the first or second resistance element being a variable resistance element that receives a first digital signal indicating a resistance value and is changeable to the resistance value. The device further includes a control unit configured to output the first digital signal, wherein the control unit outputs the first digital signal such that a theoretical waveform of the first voltage in boosting the first voltage in an erasing verifying operation is different from a theoretical waveform of the first voltage in boosting the first voltage in a reading operation.

IPC Classes  ?

  • G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
  • G11C 16/08 - Address circuits; Decoders; Word-line control circuits
  • G11C 16/26 - Sensing or reading circuits; Data output circuits

42.

MEMORY SYSTEM AND METHOD

      
Application Number 18335390
Status Pending
Filing Date 2023-06-15
First Publication Date 2024-03-21
Owner Kioxia Corporation (Japan)
Inventor Tang, Yifan

Abstract

According to one embodiment, a memory system comprises a first memory including a nonvolatile memory cell array, a second memory configured to operate at higher speed than the first memory, and a memory controller. The memory controller executes, in response to a write command from a host, data transfer from the host to the second memory, a data-in operation, and a program operation, with respect to first data instructed to be written by the write command. After the data-in operation for the first data is started and before the data-in operation is completed, the memory controller transfers the first data from the second memory to the host in response to a read command to read the first data. After the program operation for the first data is started, the memory controller transfers the first data from the first memory to the host in response to the read command.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

43.

STORAGE DEVICE AND MEMORY SYSTEM

      
Application Number 18447505
Status Pending
Filing Date 2023-08-10
First Publication Date 2024-03-21
Owner Kioxia Corporation (Japan)
Inventor Tagami, Shinichiro

Abstract

A storage device includes: a non-volatile memory; a parameter storage unit that stores a plurality of parameters for setting different operating conditions in the non-volatile memory; an access pattern analysis unit that analyzes an access pattern indicating a tendency to access the non-volatile memory by a command from a host device; a parameter selection unit that selects an optimal parameter from among the plurality of parameters based on the access pattern analyzed by the access pattern analysis unit; and an access control unit that accesses the non-volatile memory in a state where the optimal parameter is set in the non-volatile memory.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

44.

NONVOLATILE SEMICONDUCTOR MEMORY AND MANUFACTURING METHOD THEREFOR

      
Application Number 18459962
Status Pending
Filing Date 2023-09-01
First Publication Date 2024-03-21
Owner Kioxia Corporation (Japan)
Inventor
  • Suzuki, Kunifumi
  • Kamimuta, Yuuichi

Abstract

A memory cell includes: a core structure extending in a first direction orthogonal to a semiconductor substrate; a semiconductor layer extending in the first direction and in contact with the core structure; an insulating layer extending in the first direction and in contact with the semiconductor layer; a ferroelectric layer extending in the first direction and in contact with the insulating layer; a first electrode extending in a second direction orthogonal to the first direction and in contact with the ferroelectric layer; a second electrode adjacent to the first electrode in the first direction, extending in the second direction, and in contact with the ferroelectric layer; an insulating layer stacked in the first direction and disposed between the first and second electrodes; and an antiferroelectric layer disposed between the first and second electrodes, and in contact with the insulating layer and the ferroelectric layer.

IPC Classes  ?

  • G11C 11/22 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
  • G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
  • H01L 29/51 - Insulating materials associated therewith
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H10B 51/10 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the top-view layout
  • H10B 51/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 51/30 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the memory core region

45.

METHOD AND INFORMATION PROCESSING DEVICE

      
Application Number 18333949
Status Pending
Filing Date 2023-06-13
First Publication Date 2024-03-21
Owner Kioxia Corporation (Japan)
Inventor
  • Miyashita, Daisuke
  • Ikeda, Taiga
  • Deguchi, Jun

Abstract

According to an embodiment, a method includes receiving a query, and selecting one of first objects on the basis of the query and a neural network model. Each of the first objects is associated with one or more pieces of first data in a group of first data stored on a first memory. The method further includes calculating a metric of a distance between the query and one or more pieces of second data. The one or more pieces of second data are one or more pieces of first data associated with a second object. The second object is the one of the first objects having been selected. The method further includes identifying third data on the basis of the metric of the distance. The third data is first data closest to the query in the group of the first data.

IPC Classes  ?

46.

TRANSMISSION DEVICE AND RECEPTION DEVICE

      
Application Number 18459917
Status Pending
Filing Date 2023-09-01
First Publication Date 2024-03-21
Owner Kioxia Corporation (Japan)
Inventor
  • Jimbo, Ushio
  • Watanabe, Manabu
  • Sonoda, Daisuke

Abstract

A transmission device includes an encoding circuit and a modulation circuit. The encoding circuit is configured to encode first and second data stream portions of a transmission data stream in accordance with first and second encoding protocols, respectively, convert each M bit of the encoded second data stream portion into a high-resolution value of N bit, and generate a baseband data stream including the encoded first data stream portion and the converted second data stream portion. The modulation circuit is configured to perform a 2N-level pulse amplitude modulation with respect to each N bit of the encoded first data stream portion in the baseband data stream and each N bit of the converted second data stream portion in the baseband data stream, to generate a transmission signal. M is an integer equal to or greater than 1 and N is an integer greater than M.

IPC Classes  ?

  • H04L 25/49 - Transmitting circuits; Receiving circuits using three or more amplitude levels
  • H03M 5/14 - Code representation, e.g. transition, for a given bit cell depending on the information in one or more adjacent bit cells, e.g. delay modulation code, double density code

47.

SUBSTRATE PROCESSING APPARATUS, SUBSTRATE PROCESSING METHOD, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

      
Application Number 18456652
Status Pending
Filing Date 2023-08-28
First Publication Date 2024-03-21
Owner Kioxia Corporation (Japan)
Inventor
  • Ito, Fuyuma
  • Takagi, Jun
  • Mori, Ai
  • Maruyama, Yosuke
  • Akeboshi, Yuya
  • Watanabe, Takashi
  • Iimori, Hiroyasu

Abstract

A substrate processing apparatus includes: a plurality of roller pairs configured to place a plurality of substrates, respectively, wherein the substrates are arranged side by side in a horizontal direction with a predetermined interval, and rotate the plurality of substrates, respectively, in a circumferential direction; a first, second, and third circulation groove that are disposed along outer peripheral portions of each of the plurality of substrates; a chemical solution supplier configured to supply a chemical solution to the outer peripheral portions of the plurality of substrates through the first circulation groove; a rinse solution supplier configured to supply a rinse solution to the outer peripheral portions of the plurality of substrates through the second circulation groove; and a fluid supplier configured to supply a fluid for drying the rinse solution to the outer peripheral portions of the plurality of substrates through the third circulation groove.

IPC Classes  ?

  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01L 21/311 - Etching the insulating layers
  • H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer

48.

PATTERN FORMATION METHOD, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, AND IMPRINT APPARATUS

      
Application Number 18457983
Status Pending
Filing Date 2023-08-29
First Publication Date 2024-03-21
Owner Kioxia Corporation (Japan)
Inventor
  • Mitsuyasu, Masaki
  • Ogawa, Ryo
  • Mitra, Anupam

Abstract

According to one embodiment, a pattern formation method includes holding a substrate on a suction chuck that an outer suction region for an outer edge portion of the substrate and an inner suction region for an inner region of the substrate. A partial shot region at an outer edge of the substrate has a first alignment mark in the inner region and a second alignment mark at the outer edge portion. While a template is being pressed against a resin film in the shot region, position alignment using the second and fourth alignment marks is performed by adjusting a suction force for the outer suction region for changing a warpage amount of the substrate while observing the second and fourth alignment marks through the template.

IPC Classes  ?

  • G03F 1/42 - Alignment or registration features, e.g. alignment marks on the mask substrates
  • G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
  • G03F 9/00 - Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
  • H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer

49.

SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD

      
Application Number 18460506
Status Pending
Filing Date 2023-09-01
First Publication Date 2024-03-21
Owner Kioxia Corporation (Japan)
Inventor Iguchi, Tadashi

Abstract

According to one embodiment, a semiconductor memory device has a first film and a stacked body on the first film. The stacked body includes insulating films and conductive films stacked in a first direction. A first pillar extends through the stacked body and has a first semiconductor portion and a first insulator portion on an outer peripheral surface. A plurality of second pillars extend in the stacked body and reach the first film. The second pillars each comprise an insulator material and have a bottom surface with a protrusion protruding into the first film. A third pillar extends in the stacked body between adjacent second pillars. The third pillar comprises a conductor material that is electrically connected to one of the conductive films of the stacked body.

IPC Classes  ?

  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

50.

SEMICONDUCTOR MEMORY DEVICE

      
Application Number 18460509
Status Pending
Filing Date 2023-09-01
First Publication Date 2024-03-21
Owner Kioxia Corporation (Japan)
Inventor Kanno, Hiroshi

Abstract

According to one embodiment, a semiconductor memory device includes a first wiring layer above a first semiconductor layer in a first direction and a second wiring layer above the first semiconductor layer and spaced from the first wiring layer in a second direction. A first memory pillar extends through the first wiring layer. A second memory pillar extends through the second wiring layer. A member is between the first and second wiring layers in the second direction and includes a first conductor contacting the first semiconductor layer, a first insulator between the wiring layers and the first conductor, and a plurality of second insulators arranged along a third direction and between the first conductor and the first semiconductor layer in the first direction.

IPC Classes  ?

  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

51.

STORAGE DEVICE

      
Application Number 18459745
Status Pending
Filing Date 2023-09-01
First Publication Date 2024-03-21
Owner Kioxia Corporation (Japan)
Inventor
  • Kosako, Hiroaki
  • Nishikawa, Kota
  • Kikuchi, Kenrou

Abstract

A first select transistor is connected to a first wiring. A first memory cell transistor and a second memory cell transistor are connected in series between the first select transistor and a second select transistor. A first word line is connected to the first memory cell transistor. A second word line is connected to the second memory cell transistor. During a first period in which the first voltage is applied to the first wiring, a second voltage lower than a first voltage is applied in parallel to the first word line and the second word line. During a second period in which a third voltage higher than the first voltage is applied to the first wiring, the second voltage is applied to the first word line, and a fourth voltage higher than the second voltage and lower than the third voltage is applied to the second word line. During a third period in which the third voltage is applied to the first wiring, the fourth voltage is applied to the first word line, and the second voltage is applied to the second word line.

IPC Classes  ?

  • G11C 16/16 - Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
  • G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention

52.

MEMORY SYSTEM AND CONTROL METHOD

      
Application Number 18456248
Status Pending
Filing Date 2023-08-25
First Publication Date 2024-03-21
Owner Kioxia Corporation (Japan)
Inventor Matsumoto, Mariko

Abstract

A memory system includes a memory, a control circuit, and an interface circuit. The interface circuit includes a first terminal capable of receiving a first clock supplied from an outside, and a second terminal capable of receiving a first signal. When in a first state, the control circuit transitions to a second state in response to input of a first signal, and to a third state in response to input of the first clock. When in the second state, the control circuit executes initialization processing of a first mode for an operation based on an internally generated second clock or is in an operable state in the first mode, and ends the operable state in the first mode in response to input of the first clock and transitions to the third state. When in the third state, the control circuit transitions to a fourth state in response to input of the first signal. When in the fourth state, the control circuit executes initialization processing of a second mode for an operation based on the first clock or is in an operable state in the second mode.

IPC Classes  ?

  • G11C 7/22 - Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
  • G06F 13/42 - Bus transfer protocol, e.g. handshake; Synchronisation
  • G11C 7/20 - Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory

53.

SEMICONDUCTOR STORAGE DEVICE

      
Application Number 18462709
Status Pending
Filing Date 2023-09-07
First Publication Date 2024-03-21
Owner Kioxia Corporation (Japan)
Inventor
  • Akamine, Kazuki
  • Kobayashi, Shigeki

Abstract

A semiconductor storage device includes: a stacked body in which a plurality of electrically conductive layers is stacked with an insulating layer interposed in between; and a circuit section that is provided to overlap with the stacked body in a stack direction. The stacked body includes a memory section in which a plurality of memory cells is disposed and a staircase section in which the plurality of electrically conductive layers has stepped ends. The circuit section includes row decoders that are joined to the plurality of electrically conductive layers. The staircase section includes a first structure in which the row decoders are provided to overlap with each other in the stack direction and a second structure different from the first structure. The second structure has a greater step gap than a step gap of the first structure.

IPC Classes  ?

  • H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,

54.

SUBSTRATE PROCESSING APPARATUS, SUBSTRATE PROCESSING METHOD, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

      
Application Number 18460759
Status Pending
Filing Date 2023-09-05
First Publication Date 2024-03-21
Owner Kioxia Corporation (Japan)
Inventor Aiso, Fumiki

Abstract

A substrate processing apparatus according to an embodiment includes a boat capable of accommodating a plurality of substrates taken out from a storage container, a reactor capable of housing the boat and processing the plurality of substrates, and first and second arms that transfer the plurality of substrates. The boat accommodates the substrates in a first direction intersecting surfaces of the substrates. The first arm holds both ends of one substrate in a second direction intersecting the first direction, and is capable of transferring the one substrate between the storage container and the second arm. The second arm has a first holder that can support two substrates in a third direction intersecting the first and second directions, and is capable of transferring the two substrates between the first arm and the boat.

IPC Classes  ?

  • H01L 21/673 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components using specially adapted carriers
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber

55.

SEMICONDUCTOR INTEGRATED CIRCUIT, RECEIVING DEVICE, AND MEMORY SYSTEM

      
Application Number 18336302
Status Pending
Filing Date 2023-06-16
First Publication Date 2024-03-21
Owner Kioxia Corporation (Japan)
Inventor
  • Ikeda, Shinichi
  • Kawakami, Shinya

Abstract

According to one embodiment, a semiconductor integrated circuit includes an equalizer circuit and a toggle detection circuit. The equalizer circuit is configured to amplify an input signal that are externally input to output an amplified signal as a first signal. The toggle detection circuit is configured to detect toggling of the first signal and to dynamically switch a gain of the equalizer circuit based on whether or not toggling of the first signal is detected.

IPC Classes  ?

  • G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
  • G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
  • H04L 25/03 - Shaping networks in transmitter or receiver, e.g. adaptive shaping networks

56.

SEMICONDUCTOR STORAGE DEVICE

      
Application Number 18458071
Status Pending
Filing Date 2023-08-29
First Publication Date 2024-03-21
Owner Kioxia Corporation (Japan)
Inventor
  • Nakazawa, Shingo
  • Inuzuka, Yuki

Abstract

A semiconductor storage device includes a first word line, a second word line, a first select gate line, a second select gate line, a third select gate line, a fourth select gate line, a first memory pillar including a first memory cell connected to the first word line, a first select transistor connected to the first select gate line, a second memory cell connected to the second word line, and a second select transistor connected to the second select gate line, and a logic control circuit configured to perform a read operation to read threshold voltages of the first and second memory cells, respectively. The logic control circuit independently controls the first to fourth select gate lines during the read operation to turn the select transistors electrically connected to memory cells other than the memory cell to be read to off state.

IPC Classes  ?

  • G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
  • G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
  • G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • G11C 16/08 - Address circuits; Decoders; Word-line control circuits
  • G11C 16/26 - Sensing or reading circuits; Data output circuits

57.

MEMORY DEVICE

      
Application Number 18345266
Status Pending
Filing Date 2023-06-30
First Publication Date 2024-03-21
Owner Kioxia Corporation (Japan)
Inventor
  • Iwasaki, Takeshi
  • Matsushima, Yosuke
  • Komatsu, Katsuyoshi

Abstract

According to one embodiment, memory device includes a first, second, and third conductive layers in this order, a resistance change layer between the first and the second conductive layers, and a switching layer between the second and the third conductive layers. The switching layer contains: at least one first substance from a group consisting of oxide of at least one element from a group consisting of Cr, La, Ce, Y, Sc, Zr, and Hf, nitride of the at least one element, and oxynitride of the at least one element; a second substance being at least one metal from a group consisting of Te, Se, Sb, Bi, Ge, and Sn; and at least one third substance from a group consisting of oxide of the second substance, nitride of the second substance, and oxynitride of the second substance.

IPC Classes  ?

  • H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices

58.

SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR MEMORY DEVICE

      
Application Number 18458069
Status Pending
Filing Date 2023-08-29
First Publication Date 2024-03-21
Owner Kioxia Corporation (Japan)
Inventor
  • Hashimoto, Junichi
  • Sasaki, Toshiyuki

Abstract

According to one embodiment, a semiconductor memory device includes a lower layer, a stacked body above the lower layer with first conductive layers and first insulating layers alternately stacked. A pillar penetrates through the stacked body to reach the lower layer. At least one first insulating layer other than the lowest among the first insulating layers in a first region of the stacked body is thicker than first insulating layers in a second region above the first region. The pillar has a first bowing shape at the height of the at least one thicker first insulating layer and a second bowing shape at a height in the second region.

IPC Classes  ?

  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
  • H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass

59.

SEMICONDUCTOR MEMORY DEVICE

      
Application Number 18335680
Status Pending
Filing Date 2023-06-15
First Publication Date 2024-03-21
Owner Kioxia Corporation (Japan)
Inventor
  • Date, Kohei
  • Suda, Keisuke

Abstract

According to one embodiment, a semiconductor memory device includes: stacked interconnects including a first interconnect layer and a second interconnect layer, the first interconnect layer including a first area and a second area arranged in a first direction, the second interconnect layer being arranged above the first interconnect layer in a second direction intersecting the first direction, the second interconnect layer not including the first area and including the second area; a first memory pillar arranged in the first area and passing through the first interconnect layer in the second direction; and a second memory pillar arranged in the second area and passing through the first interconnect layer and the second interconnect layer in the second direction.

IPC Classes  ?

  • G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • H01L 23/528 - Layout of the interconnection structure
  • H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
  • H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
  • H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND

60.

STORAGE DEVICE

      
Application Number 18454960
Status Pending
Filing Date 2023-08-24
First Publication Date 2024-03-21
Owner Kioxia Corporation (Japan)
Inventor
  • Iwasaki, Takeshi
  • Qi, Zhu
  • Komatsu, Katsuyoshi
  • Zhang, Jieqiong

Abstract

A storage device includes a first conductive layer, a second conductive layer, a third conductive layer, a variable resistance layer disposed between the first conductive layer and the second conductive layer, and a switching layer disposed between the second conductive layer and the third conductive layer. The second conductive layer is disposed between the first conductive layer and the third conductive layer. The switching layer includes a first area, a second area, and a third area disposed between the first area and the second area. The first area includes a first element selected from Sn, Ga, Zn, Ta, Ti, and In, and O or N. The second area includes a second element selected from Sn, Ga, Zn, Ta, Ti, and In, and O or N. The third area includes a third element selected from Zr, Y, Ce, Hf, Al, Mg, and Nb, O or N, and a metal element selected from Te, Sb, Bi, Ti, and Zn.

IPC Classes  ?

  • H10N 50/10 - Magnetoresistive devices
  • G11C 5/08 - Arrangements for interconnecting storage elements electrically, e.g. by wiring for interconnecting magnetic elements, e.g. toroidal cores
  • H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
  • H10N 50/85 - Magnetic active materials

61.

SEMICONDUCTOR MEMORY DEVICE

      
Application Number 18459353
Status Pending
Filing Date 2023-08-31
First Publication Date 2024-03-21
Owner Kioxia Corporation (Japan)
Inventor
  • Ishihara, Takamitsu
  • Matsuzawa, Kazuya

Abstract

A semiconductor memory device includes a gate electrode and a first and second semiconductor layer surrounding the gate electrode. A first electrode layer surrounds the gate electrode and contacts the first semiconductor layer. A second electrode layer surrounds the gate electrode and contacts the first and second semiconductor layers. The first semiconductor layer is between the first and second electrode layers. A third electrode layer surrounds the gate electrode and contacts the second semiconductor layer. The second semiconductor layer is between the second and third electrode layers. A first charge storage layer is between the gate electrode and the first semiconductor layer. A second charge storage layer is between the gate electrode and the second semiconductor layer.

IPC Classes  ?

  • H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
  • H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

62.

MEMORY SYSTEM, CONTROL DEVICE, AND METHOD

      
Application Number 18461661
Status Pending
Filing Date 2023-09-06
First Publication Date 2024-03-21
Owner Kioxia Corporation (Japan)
Inventor Ootomo, Goichi

Abstract

According to one embodiment, a memory system includes a semiconductor memory device and a control device. The memory system includes a first device and first channels. The first channels are each connected to one or more second devices. The control device is connected to the first device via a second channel. The control device includes first circuits and a second circuit. The first circuits each execute data transfer to the second device as an access destination. The second circuit is provided between the first circuits and the second channel. The second circuit combines data from the first circuits and transfers the combined data to the second channel at a transfer rate higher than that of pre-combining data. The second circuit divides data received via the second channel and distributes pieces of divided data to the first circuits at a transfer rate lower than that of pre-dividing data.

IPC Classes  ?

  • G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
  • G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens

63.

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

      
Application Number 18458284
Status Pending
Filing Date 2023-08-30
First Publication Date 2024-03-21
Owner Kioxia Corporation (Japan)
Inventor Nomura, Kotaro

Abstract

A semiconductor memory device of an embodiment includes a first region having a first stack and a first pillar, and a second region having a second stack and a second pillar. The first stack comprises an alternate stack in a first direction of a plurality of first insulating films containing oxygen and a plurality of first conductive films. The first pillar comprises a semiconductor layer and extends in the first direction within the first stack. The second stack comprises a repeated stack in the first direction of the plurality of first insulating films, a plurality of second insulating films, and a plurality of third insulating films in the order of the first insulating film, the second insulating film, and the third insulating film. The second insulating film contains nitrogen. The third insulating film contains nitrogen and at least one of oxygen and hydrogen. The second pillar comprises a semiconductor layer and extends in the first direction within the second stack. The first region and the second region are adjacent to each other in a second direction intersecting the first direction.

IPC Classes  ?

  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

64.

SEMICONDUCTOR DEVICE

      
Application Number 18458050
Status Pending
Filing Date 2023-08-29
First Publication Date 2024-03-21
Owner Kioxia Corporation (Japan)
Inventor
  • Nishikawa, Daichi
  • Ikeno, Daisuke
  • Sakata, Atsuko

Abstract

According to one embodiment, a semiconductor device includes a pillar of an oxide semiconductor material and a gate insulating layer that surrounds a side surface of the pillar. The gate insulating layer includes a lower portion, an upper portion, and an intermediate portion. A gate electrode surrounds the intermediate portion of the gate insulating layer. A lower electrode is provided that includes a first oxide conductor portion that is connected to a lower surface of the pillar. An upper electrode is provided connected to an upper surface of the pillar. The gate electrode includes a metal portion containing a metallic element and a first nitrogen-containing portion between the metal portion and the gate insulating layer. The first oxide conductor portion includes a second nitrogen-containing at an interface between the first oxide conductor portion and the gate insulating layer.

IPC Classes  ?

65.

PATTERN FORMING METHOD, MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE

      
Application Number 18458056
Status Pending
Filing Date 2023-08-29
First Publication Date 2024-03-21
Owner Kioxia Corporation (Japan)
Inventor
  • Ueha, Koki
  • Kodera, Katsuyoshi

Abstract

According to one embodiment, a pattern forming method uses a template having a first region with a first recessed portion and a second region adjacent to the first region. The second region has a second recessed portion therein. The recessed portions satisfy a specific relationship (D1>2(H1+H2)/π), where D1 is a shortest distance between the first and second recessed portions, H1 is a depth of the first recessed portion, and H2 is a depth of the second recessed portion. The pattern forming method includes placing an imprint material on an object and pressing the template against the material to mold the imprint material. The molded imprint material is then cured, and the template removed.

IPC Classes  ?

  • H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
  • G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device

66.

MEMORY SYSTEM AND POWER CONTROL CIRCUIT

      
Application Number 18358387
Status Pending
Filing Date 2023-07-25
First Publication Date 2024-03-21
Owner Kioxia Corporation (Japan)
Inventor Matsumoto, Hajime

Abstract

According to one embodiment, a memory system connectable to a host includes a nonvolatile memory, a controller, and a power control circuit. The controller controls the nonvolatile memory. The power control circuit controls power to be supplied to the controller and the nonvolatile memory and includes one or more DC/DC converters. The nonvolatile memory and the controller include one or more circuit blocks. Each of the one or more DC/DC converters supplies an internal power supply voltage to one of the one or more circuit blocks. A first DC/DC converter of the one or more DC/DC converters transitions to a forced pulse width modulation mode in response to the memory system that has transitioned from a low power consumption mode to a normal operation mode.

IPC Classes  ?

  • H02M 3/20 - Conversion of dc power input into dc power output without intermediate conversion into ac by combination of dynamo-electric with other dynamic or static converters
  • G06F 13/42 - Bus transfer protocol, e.g. handshake; Synchronisation
  • H02M 3/157 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control

67.

SEMICONDUCTOR MEMORY DEVICE

      
Application Number 18519872
Status Pending
Filing Date 2023-11-27
First Publication Date 2024-03-21
Owner Kioxia Corporation (Japan)
Inventor
  • Fukuzumi, Yoshiaki
  • Aochi, Hideaki
  • Matsuo, Mie
  • Yoshii, Kenichiro
  • Shindo, Koichiro
  • Kawasaki, Kazushige
  • Sanuki, Tomoya

Abstract

According to one embodiment, the array chip includes a three-dimensionally disposed plurality of memory cells and a memory-side interconnection layer connected to the memory cells. The circuit chip includes a substrate, a control circuit provided on the substrate, and a circuit-side interconnection layer provided on the control circuit and connected to the control circuit. The circuit chip is stuck to the array chip with the circuit-side interconnection layer facing to the memory-side interconnection layer. The bonding metal is provided between the memory-side interconnection layer and the circuit-side interconnection layer. The bonding metal is bonded to the memory-side interconnection layer and the circuit-side interconnection layer.

IPC Classes  ?

  • H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
  • H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 43/30 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
  • H10B 43/50 - EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions

68.

MAGNETIC MEMORY DEVICE

      
Application Number 18465759
Status Pending
Filing Date 2023-09-12
First Publication Date 2024-03-21
Owner Kioxia Corporation (Japan)
Inventor
  • Akiyama, Naoki
  • Yoshino, Kenichi
  • Sawada, Kazuya
  • Cho, Hyungjun
  • Shimano, Takuya

Abstract

According to one embodiment, a magnetic memory device includes a lower insulating layer, first and second conductive portions provided in the lower insulating layer, first and second memory cells provided on the lower insulating layer and on the respective first and second conductive portions, and each including a magnetoresistance effect element, a switching element and a bottom electrode connected to corresponding one of the first and second conductive portions. As viewed from a third direction, a width of each of the first and second conductive portions is less than a width of a corresponding bottom electrode. The lower insulating layer has a void under a region between the first and second memory cells.

IPC Classes  ?

  • H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices

69.

MAGNETIC MEMORY DEVICE

      
Application Number 18466727
Status Pending
Filing Date 2023-09-13
First Publication Date 2024-03-21
Owner Kioxia Corporation (Japan)
Inventor
  • Yoshino, Kenichi
  • Oikawa, Tadaaki
  • Sawada, Kazuya
  • Akiyama, Naoki
  • Shimano, Takuya
  • Cho, Hyungjun

Abstract

According to one embodiment, a magnetic memory device includes a first wiring line extending in a first direction, a second wiring line provided on an upper layer side of the first wiring line and extending in a second direction intersecting the first direction, and a memory cell provided between the first wiring line and the second wiring line and including a magnetoresistance effect element and a switching element which are stacked in a third direction intersecting the first direction and the second direction. The first wiring line includes a first conductive layer and a second conductive layer provided on the first conductive layer and formed of a material containing carbon (C).

IPC Classes  ?

  • H10N 50/85 - Magnetic active materials
  • G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
  • H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
  • H10N 50/10 - Magnetoresistive devices

70.

SEMICONDUCTOR MEMORY DEVICE

      
Application Number 18524458
Status Pending
Filing Date 2023-11-30
First Publication Date 2024-03-21
Owner Kioxia Corporation (Japan)
Inventor Maejima, Hiroshi

Abstract

A semiconductor memory device includes a memory cell array having memory strings that include memory cells and first and second selection transistors. During a read operation, a controller applies a first voltage higher than ground to a source line, and a second voltage to a first and second selection gate lines that are connected to a selected memory string. The second voltage is also applied to the first selection gate lines connected to non-selected memory strings during a first period of the read operation. A third voltage higher than ground and lower than the second voltage is applied to the first selection gate lines connected to non-selected memory strings during a second period of the read operation subsequent to the first period.

IPC Classes  ?

  • G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • G11C 16/08 - Address circuits; Decoders; Word-line control circuits
  • G11C 16/24 - Bit-line control circuits
  • G11C 16/26 - Sensing or reading circuits; Data output circuits
  • G11C 16/28 - Sensing or reading circuits; Data output circuits using differential sensing or reference cells, e.g. dummy cells
  • G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention

71.

SEMICONDUCTOR DEVICE, METHOD FOR DESIGNING SAME, AND METHOD FOR MANUFACTURING SAME

      
Application Number JP2022034748
Publication Number 2024/057528
Status In Force
Filing Date 2022-09-16
Publication Date 2024-03-21
Owner KIOXIA CORPORATION (Japan)
Inventor
  • Watanabe, Yoshinori
  • Yamano, Satoshi

Abstract

According to an embodiment of the present invention, a semiconductor device comprises a first cell including a first PMOS transistor, a second PMOS transistor arranged side by side with the first PMOS transistor, a first NMOS transistor, a second NMOS transistor arranged side by side with the first NMOS transistor, and a seventh wire electrically connected to none of the first PMOS transistor, the second PMOS transistor, the first NMOS transistor, and the second NMOS transistor.

IPC Classes  ?

  • H01L 21/82 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
  • H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout

72.

SEMICONDUCTOR DEVICE

      
Application Number 18178038
Status Pending
Filing Date 2023-03-03
First Publication Date 2024-03-21
Owner Kioxia Corporation (Japan)
Inventor
  • Watanabe, Fumiya
  • Watanabe, Toshifumi
  • Satou, Kazuhiko
  • Ozaki, Shouichi
  • Kubota, Kenro
  • Saeki, Atsuko
  • Tsuchiya, Ryota
  • Abe, Harumi

Abstract

A semiconductor device includes a first pad, a second pad, a first output driver provided for the first pad and configured to output a first transmission signal to the first pad, a second output driver provided for the second pad and configured to output a second transmission signal to the second pad, a register that stores first and second calibration values, a first reference resistor for the first pad and having a resistance value that is set according to the first calibration value, a second reference resistor for the second pad and having a resistance value that is set according to the second calibration value, a first setting circuit configured to calibrate a resistance value of the first output driver using the first reference resistor, and a second setting circuit configured to calibrate a resistance value of the second output driver using the second reference resistor.

IPC Classes  ?

  • H03K 3/011 - Modifications of generator to compensate for variations in physical values, e.g. voltage, temperature
  • G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
  • H03K 17/14 - Modifications for compensating variations of physical values, e.g. of temperature

73.

SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

      
Application Number 18182529
Status Pending
Filing Date 2023-03-13
First Publication Date 2024-03-21
Owner Kioxia Corporation (Japan)
Inventor Fujii, Kotaro

Abstract

A semiconductor storage device according to an embodiment includes a first wiring, a second wiring, a first insulating layer, a first insulator, and a conductor. The first insulating layer has a first portion, a second portion, and a third portion. The first portion is stacked on the first wiring. The second portion is stacked on the second wiring. The third portion is on the opposite side of the first wiring and the second wiring with respect to the first portion and the second portion.

IPC Classes  ?

  • H01L 23/528 - Layout of the interconnection structure
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
  • H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
  • H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND

74.

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

      
Application Number 18177353
Status Pending
Filing Date 2023-03-02
First Publication Date 2024-03-21
Owner Kioxia Corporation (Japan)
Inventor Sasaki, Toshiyuki

Abstract

A method for manufacturing a semiconductor device includes forming, on a to-be-processed film above an underlying film, a mask material containing a first metal and comprising a first mask layer which is provided on the to-be-processed film and whose content of the first metal is lower than a first predetermined percentage, and a second mask layer which is provided on the first mask layer and whose content of the first metal is equal to or higher than the first predetermined percentage. The manufacturing method includes patterning the mask material. The manufacturing method includes processing the to-be-processed film using the mask material as a mask. The processing of the to-be-processed film includes performing a first treatment to process the to-be-processed film at a first temperature in an atmosphere of a first gas. The processing of the to-be-processed film includes performing a second treatment to process the to-be-processed film at a second temperature higher than the first temperature in an atmosphere of a second gas different from the first gas.

IPC Classes  ?

  • H01L 21/033 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or comprising inorganic layers
  • H01L 21/311 - Etching the insulating layers

75.

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MEMORY DEVICE

      
Application Number 18165595
Status Pending
Filing Date 2023-02-07
First Publication Date 2024-03-21
Owner Kioxia Corporation (Japan)
Inventor
  • Watanabe, Daisuke
  • Gawase, Akifumi
  • Iwasaki, Takeshi
  • Katono, Kazuhiro
  • Muto, Yusuke
  • Miki, Yusuke
  • Kimura, Akinori

Abstract

A semiconductor device including a first electrode, a second electrode, an oxide semiconductor disposed between the first electrode and the second electrode, and a first oxide layer containing a predetermined element, oxygen, and an additional element and disposed between the first electrode and the oxide semiconductor, wherein the predetermined element is at least one of tantalum, boron, hafnium, silicon, zirconium, or niobium, and the additional element is at least one of phosphorus, sulfur, copper, zinc, gallium, germanium, arsenic, selenium, silver, indium, tin, antimony, tellurium, or bismuth.

IPC Classes  ?

76.

MEMORY SYSTEM AND CONTROL METHOD

      
Application Number 18176455
Status Pending
Filing Date 2023-02-28
First Publication Date 2024-03-21
Owner Kioxia Corporation (Japan)
Inventor Tadokoro, Mitsunori

Abstract

A controller assigns, for each namespace, one logical area of a logical address space as a first logical area including a last logical address of the namespace and assigns one or more of logical areas as second logical areas. The controller divides a memory region in which an address translation table is stored into buffer regions. For each second logical area, the controller assigns one buffer region for storing map segments corresponding to the second logical area, and manages a first pointer indicating a storage location of the buffer region assigned thereto. The controller also assigns one buffer region for map segments corresponding to the first logical areas of two or more namespaces, and manages second pointers respectively indicating storage locations in the one buffer region, in which the map segments corresponding to the first logical areas of the two or more namespaces are respectively stored.

IPC Classes  ?

  • G06F 12/1009 - Address translation using page tables, e.g. page table structures

77.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

      
Application Number 18179922
Status Pending
Filing Date 2023-03-07
First Publication Date 2024-03-21
Owner Kioxia Corporation (Japan)
Inventor Omura, Yuya

Abstract

According to one embodiment, transistors and a resistance-capacitance element are provided. The transistors each have a gate insulating film with a gate dielectric film and a gate electrode of a metal material. The resistance-capacitance element is provided by stacking a first insulating film, a first conductive layer, a stopper insulating film, a second insulating film, and a second conductive layer on an upper surface of a semiconductor substrate. The second insulating film includes the gate dielectric film like the gate insulating film. The second conductive layer is made of the same metal material as the gate electrode. The first conductive layer is a conductive material having a higher resistance than the second conductive layer.

IPC Classes  ?

  • H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
  • H01L 29/94 - Metal-insulator-semiconductors, e.g. MOS

78.

SEMICONDUCTOR INTEGRATED CIRCUIT AND RECEIVER DEVICE

      
Application Number 18209380
Status Pending
Filing Date 2023-06-13
First Publication Date 2024-03-21
Owner Kioxia Corporation (Japan)
Inventor Ngo, Huy Cu

Abstract

According to one embodiment, a semiconductor integrated circuit includes: first and second converters respectively configured to determine first and second bit strings based on first and second clock signals; a circuit. The circuit includes: first, second, and third capacitors; first and second switching elements; and first, second, and third buffers. The first buffer includes an output end coupled to the first capacitor, a first end of the each of the first and second switching elements. The second buffer includes an output end coupled to the second capacitor, a second end of the first switching element, and the first converter. The third buffer includes an output end coupled to the third capacitor, a second end of the second switching element, and the second converter. A reference voltage is supplied to an input end of each of the first, second, and third buffers.

IPC Classes  ?

  • H03M 1/46 - Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
  • H03M 1/14 - Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit

79.

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

      
Application Number 18181148
Status Pending
Filing Date 2023-03-09
First Publication Date 2024-03-21
Owner Kioxia Corporation (Japan)
Inventor Nagashima, Yoshiki

Abstract

A semiconductor memory device includes a first memory die, a second memory die disposed above the first memory die via adhesives, a first wiring connected to the first memory die, and configured to apply a power supply voltage to the first memory die, a first switch element connected to the first wiring, a second wiring connected to the second memory die, and configured to apply the power supply voltage to the second memory die, a second switch element connected to the second wiring, and a third wiring configured to electrically connect to the first wiring via the first switch element, and configured to electrically connect to the second wiring via the second switch element. The first switch element and the second switch element are independently controllable.

IPC Classes  ?

  • H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass

80.

STORAGE DEVICE

      
Application Number 18174864
Status Pending
Filing Date 2023-02-27
First Publication Date 2024-03-21
Owner Kioxia Corporation (Japan)
Inventor Kobayashi, Hirotomo

Abstract

According to one embodiment, a storage device includes a nonvolatile memory and a controller. The controller manages first user identification information and first authentication information including a hash value calculated from the first user identification information and a first device identification information of a first client device. The controller receives an access request to the nonvolatile memory, user identification information, and authentication information transmitted from an external device, and accepts the access request in a case where the user identification information received matches the first user identification information, and the authentication information received matches the first authentication information.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

81.

NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD

      
Application Number 18179895
Status Pending
Filing Date 2023-03-07
First Publication Date 2024-03-21
Owner Kioxia Corporation (Japan)
Inventor
  • Takahashi, Kensuke
  • Takashima, Daisaburo
  • Kai, Naoki
  • Ishimoto, Yasumi

Abstract

According to one embodiment, a cell block includes memory cells and select transistors. The memory cells correspond are connected in parallel between a local source line and a local bit line. The select transistor is connected between the local bit line and a bit line. The memory cell includes a cell transistor and a resistance change element. A gate of the cell transistor is connected to a word line. The resistance change element is connected to the cell transistor in series between the local source line and the local bit line. Each cell block is configured as a columnar structure penetrating a plurality of conductive films functioning as word lines. The select transistor and the local bit line are connected at a contact portion formed of a material different from a material of the local bit line.

IPC Classes  ?

  • H10B 63/00 - Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
  • H10B 63/10 - Phase change RAM [PCRAM, PRAM] devices

82.

MEMORY SYSTEM

      
Application Number 18177685
Status Pending
Filing Date 2023-03-02
First Publication Date 2024-03-21
Owner Kioxia Corporation (Japan)
Inventor
  • Yu, Dongxiao
  • Kiyooka, Masahiro
  • Nishikawa, Suguru
  • Kojima, Yoshihisa

Abstract

A memory system includes a semiconductor memory that includes a cell unit having a plurality of memory cells, and a control circuit for controlling the plurality of memory cells, and a memory controller configured to control the semiconductor memory. The control circuit is configured to execute a data read operation on the cell unit by using one or more read voltages, acquire first data by the data read operation, generate second data with a data size smaller than the first data, based on the first data, and transmit the second data to the memory controller. The memory controller is configured to determine, based on the second data, whether or not to rewrite the page data written in the cell unit.

IPC Classes  ?

  • G11C 16/26 - Sensing or reading circuits; Data output circuits
  • G11C 16/08 - Address circuits; Decoders; Word-line control circuits
  • G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention

83.

IMAGING DEVICE AND IMAGE GENERATION METHOD

      
Application Number 18456311
Status Pending
Filing Date 2023-08-25
First Publication Date 2024-03-21
Owner Kioxia Corporation (Japan)
Inventor Yamane, Takeshi

Abstract

An imaging device includes an image processor configured to: i) determine that a detection intensity distribution indicating detection intensity with respect to position coordinates of a stage is a convolution of an image intensity distribution on an extension line of a linear pixel and a window function; (ii) calculate an image intensity distribution for each linear pixel by deconvolution from the detection intensity distribution; and (iii) generate an image of the subject by disposing the image intensity distribution calculated in all the linear pixels in an arrangement direction of the linear pixels.

IPC Classes  ?

  • G21K 7/00 - Gamma ray or X-ray microscopes
  • G02B 21/06 - Means for illuminating specimen
  • G02B 21/26 - Stages; Adjusting means therefor
  • G02B 21/36 - Microscopes arranged for photographic purposes or projection purposes

84.

MEMORY SYSTEM

      
Application Number 18458755
Status Pending
Filing Date 2023-08-30
First Publication Date 2024-03-21
Owner Kioxia Corporation (Japan)
Inventor Matsukawa, Shinichi

Abstract

A memory system includes a non-volatile memory and a memory controller. The memory controller is configured to perform write, read, and erase operations in accordance with write commands, read commands, and erase commands, respectively, from a host, and receive, from the host, time information indicating times when the write, read, and erase commands have been transmitted from or issued by the host. The memory controller is further configured to generate, from the received time information, history data including a value representing a busy state of the memory system with respect to each time range in a predetermined time period, and perform a maintenance operation with respect to the non-volatile memory upon time at which a command received from the host has been transmitted from or issued by the host falling in one or more of the time ranges corresponding to values smaller than the other of the time ranges.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

85.

SEMICONDUCTOR DEVICE

      
Application Number 18467887
Status Pending
Filing Date 2023-09-15
First Publication Date 2024-03-21
Owner Kioxia Corporation (Japan)
Inventor
  • Inukai, Takashi
  • Tokuhira, Hiroki
  • Inaba, Tsuneo

Abstract

According to one embodiment, a semiconductor device includes a first wiring line provided in a first layer and extending in a first direction, a second wiring line provided in a second layer and extending in the first direction, a first semiconductor layer penetrating the first wiring line without penetrating the second wiring line and extending in a second direction, a second semiconductor layer penetrating the second wiring line without penetrating the first wiring line and extending in the second direction, a first insulating layer provided between the first wiring line and the first semiconductor layer, a second insulating layer provided between the second wiring line and the second semiconductor layer.

IPC Classes  ?

  • H10B 12/00 - Dynamic random access memory [DRAM] devices

86.

MEMORY SYSTEM

      
Application Number 18337137
Status Pending
Filing Date 2023-06-19
First Publication Date 2024-03-21
Owner Kioxia Corporation (Japan)
Inventor
  • Shono, Atsuo
  • Iwasaki, Kiyotaka

Abstract

According to one embodiment, a system includes: a memory, and a controller, wherein the memory includes a first die including first and second planes and a second die including a third plane, and the controller issues a read command to the first and second dies, if a read time for first data in the first plane has ended, a read time for second data in the second plane has ended after the end of the read time for the first data, and a read time for third data in the third plane has ended after the end of the read time for the second data, receives the first data from the first die, receives the third data from the second die after completion of receiving the first data, and receives the second data from the first die after completion of receiving the third data.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

87.

SEMICONDUCTOR MEMORY DEVICE

      
Application Number 18465244
Status Pending
Filing Date 2023-09-12
First Publication Date 2024-03-21
Owner Kioxia Corporation (Japan)
Inventor
  • Sato, Toshiaki
  • Unno, Masaki

Abstract

A semiconductor memory device includes a plurality of sense amplifier regions, a first wiring layer including a plurality of bit lines electrically connected to a plurality of semiconductor layers, and a second wiring layer including a plurality of first wirings electrically connecting the respective plurality of sense amplifier regions to the plurality of bit lines. The semiconductor substrate includes a first region and a second region arranged in a second direction. The (n1) (n1 is an integer of 2 or more) first wirings arranged in the third direction are disposed at a position where the first region overlaps with the sense amplifier region viewed in the first direction. The (n2) (n2 is an integer of 2 or more different from n1) first wirings arranged in the third direction are disposed at a position where the second region overlaps with the other sense amplifier region viewed in the first direction.

IPC Classes  ?

  • H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,

88.

MEMORY SYSTEM AND NON-VOLATILE MEMORY

      
Application Number 18450607
Status Pending
Filing Date 2023-08-16
First Publication Date 2024-03-21
Owner Kioxia Corporation (Japan)
Inventor Takahashi, Keisuke

Abstract

A memory system includes a non-volatile memory and a controller. The non-volatile memory includes a memory cell array and a register storing first table data including feature information indicating feature of an address designating a storage area in the memory cell array. The controller can control the non-volatile memory. When receiving address information indicating the address from the controller, the non-volatile memory reads the feature information from the first table data in the register and transmits the feature information to the controller. When receiving the feature information from the non-volatile memory, the controller can execute a response operation in response to a request with respect to the address based on the received feature information.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers
  • G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • G11C 16/10 - Programming or data input circuits
  • G11C 16/26 - Sensing or reading circuits; Data output circuits

89.

MEMORY DEVICE

      
Application Number 18359531
Status Pending
Filing Date 2023-07-26
First Publication Date 2024-03-21
Owner Kioxia Corporation (Japan)
Inventor Inukai, Takashi

Abstract

According to one embodiment, a memory device includes word lines, bit lines, transistors, capacitors, and a plate line. The transistors include first transistors and second transistors. The first and second transistors are coupled to first and second word lines, respectively. The first and second transistors are arranged to alternate each other in a first direction. The bit lines include first to fourth bit lines arranged sequentially in the first direction. The first and third bit lines are coupled to the other end of the first and second transistors. The second bit line is coupled to the other end of the first transistors and is not coupled to the other end of the second transistors. The fourth bit line is coupled to the other end of the second transistors and is not coupled to the other end of the first transistors.

IPC Classes  ?

  • H10B 12/00 - Dynamic random access memory [DRAM] devices

90.

SOCKET BOARD AND METHOD FOR INSPECTING A SEMICONDUCTOR DEVICE

      
Application Number 18460495
Status Pending
Filing Date 2023-09-01
First Publication Date 2024-03-21
Owner Kioxia Corporation (Japan)
Inventor
  • Kita, Tsunehiro
  • Ibaraki, Soichiro

Abstract

A socket board used for testing a semiconductor device having one or more terminals, by raising a temperature of the semiconductor device to a predetermined temperature, includes a substrate, a socket that is provided on the substrate and capable of holding the semiconductor device, a pin that penetrates a bottom portion of the socket, and has an upper portion that is to come into contact with a terminal of the semiconductor device, and a heat conductive material that is disposed on the bottom portion of the socket to come into contact with the terminals of the semiconductor device held in the socket. The heat conductive material includes a macromolecular gel, and electrically-insulating metal-containing particles added to the macromolecular gel.

IPC Classes  ?

  • G01R 1/04 - Housings; Supporting members; Arrangements of terminals
  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer

91.

MEMORY SYSTEM AND METHOD

      
Application Number 18450239
Status Pending
Filing Date 2023-08-15
First Publication Date 2024-03-21
Owner Kioxia Corporation (Japan)
Inventor
  • Takada, Marie
  • Shirakawa, Masanobu
  • Takeda, Naomi

Abstract

According to an embodiment, a controller acquires a first temperature detection value and executes an acquisition operation on a first storage area. The controller converts a first voltage value into a second voltage value representing the read voltage in a temperature set value based on the first temperature detection value and records the second voltage value. The acquisition operation is an operation of determining, by using the read voltages, whether memory cells are ON or OFF and acquiring the first voltage value representing the read voltage for suppressing error bits. After that, the controller acquires a second temperature detection value and converts the second voltage value into a third voltage value representing the read voltage in the second temperature detection value. The controller reads data from the memory cells by using, as the read voltage, a voltage indicated by the third voltage value.

IPC Classes  ?

  • G06F 11/07 - Responding to the occurrence of a fault, e.g. fault tolerance
  • G06F 12/02 - Addressing or allocation; Relocation

92.

MEMORY, MEMORY SYSTEM AND METHOD OF CONTROLLING STORAGE DEVICE

      
Application Number 18463730
Status Pending
Filing Date 2023-09-08
First Publication Date 2024-03-21
Owner Kioxia Corporation (Japan)
Inventor Yamazaki, Atsushi

Abstract

A memory having a first authentication code includes a communication port configured to transmit information including debug data to or receive the information including debug data from the external device; and a debug port controller that is usable for blocking of a communication path connecting to the communication port. The debug port controller is configured to receive an authentication request including a second authentication code from an external device, determine whether the second authentication code matches the first authentication code, and block the communication path if the second authentication code is not determined to match the first authentication code. The communication port may be configured to be disabled until the second authentication code matches the first authentication code.

IPC Classes  ?

93.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

      
Application Number 18460236
Status Pending
Filing Date 2023-09-01
First Publication Date 2024-03-21
Owner Kioxia Corporation (Japan)
Inventor Funabasama, Tomoyuki

Abstract

A semiconductor device is provided with a substrate, a first transistor, and a second transistor. The first transistor has a first diffusion layer region, a second diffusion layer region, a first gate insulating film, a first gate electrode, and a first silicide layer. The first silicide layer is provided on the first diffusion layer region and the second diffusion layer region. The second transistor has a third diffusion layer region, a fourth diffusion layer region, a second gate insulating film, a second gate electrode, and a second silicide layer. The second silicide layer is provided on the third diffusion layer region and the fourth diffusion layer region. A distance between the first silicide layer and the first gate insulating film is larger than a distance between the second silicide layer and the second gate insulating film.

IPC Classes  ?

  • H01L 29/786 - Thin-film transistors
  • H01L 29/66 - Types of semiconductor device
  • H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
  • H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND

94.

MEMORY SYSTEM INCLUDING NONVOLATILE MEMORY AND METHOD OF CONTROLLING THE SAME

      
Application Number 18463396
Status Pending
Filing Date 2023-09-08
First Publication Date 2024-03-21
Owner Kioxia Corporation (Japan)
Inventor
  • Kanno, Shinichi
  • Tran, Aurelien Nam Phong
  • Sasaki, Yuki

Abstract

According to one embodiment, in response to restoration of power to a memory system, a controller in the memory system notifies a host that the memory system is ready. When an input/output command specifying a logical address belonging to a logical address range is received, the controller selects a block corresponding to the logical address range and rebuilds, based on address translation information and an update log which are stored in the selected block, the latest address translation information corresponding to the logical address range. The controller updates the rebuilt latest address translation information, based on a list of logical addresses corresponding to lost write data, stored in the selected block.

IPC Classes  ?

  • G06F 12/02 - Addressing or allocation; Relocation
  • G06F 12/1027 - Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]

95.

INFORMATION PROCESSING APPARATUS AND INFORMATION PROCESSING METHOD

      
Application Number 18453105
Status Pending
Filing Date 2023-08-21
First Publication Date 2024-03-21
Owner Kioxia Corporation (Japan)
Inventor
  • Torii, Osamu
  • Manabe, Shinichiro

Abstract

An information processing apparatus comprising processing circuitry. The processing circuitry is configured to acquire objective variables and explanatory variables which are regression analysis targets, extract a plurality of first explanatory variables having a high degree of influence on the objective variable from among the explanatory variables by sparse modeling using a first regression equation, and extract a second explanatory variable having a high degree of influence on the plurality of first explanatory variables by sparse modeling using a second regression equation.

IPC Classes  ?

  • G06F 17/18 - Complex mathematical operations for evaluating statistical data

96.

MEMORY SYSTEM

      
Application Number 18466413
Status Pending
Filing Date 2023-09-13
First Publication Date 2024-03-21
Owner Kioxia Corporation (Japan)
Inventor Katagiri, Toru

Abstract

According to one embodiment, a controller of a memory system receives, from a host, a first read command that specifies a first logical address and a data pointer, the first logical address corresponding to first data stored in the nonvolatile memory, the data pointer indicating a first data buffer of a memory of the host to which the first data is to be transferred. The controller performs read access to the first data buffer of the memory of the host, based on the data pointer specified by the first read command.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

97.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

      
Application Number 18456623
Status Pending
Filing Date 2023-08-28
First Publication Date 2024-03-21
Owner Kioxia Corporation (Japan)
Inventor Honda, Shingo

Abstract

A semiconductor device includes a first layer including a first recess portion on an upper surface; and a second recess portion that extends from a bottom surface of the first recess portion in the first layer, and the second recess portion has a tapered shape in which a width in a first direction along a surface direction of the first layer reduces from the bottom surface of the first recess portion in a depth direction of the first layer.

IPC Classes  ?

  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H10B 69/00 - Erasable-and-programmable ROM [EPROM] devices not provided for in groups , e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

98.

MAGNETIC MEMORY DEVICE

      
Application Number 18466868
Status Pending
Filing Date 2023-09-14
First Publication Date 2024-03-21
Owner Kioxia Corporation (Japan)
Inventor
  • Sawada, Kazuya
  • Nagase, Toshihiko
  • Yoshino, Kenichi
  • Cho, Hyungjun
  • Akiyama, Naoki
  • Shimano, Takuya
  • Oikawa, Tadaaki

Abstract

According to one embodiment, a magnetic memory device includes an electrode, and a magnetoresistance effect element provided on the electrode. The electrode includes a first electrode portion and a second electrode portion provided between the magnetoresistance effect element and the first electrode portion and containing a metal element selected from molybdenum (Mo) and ruthenium (Ru).

IPC Classes  ?

  • H10N 50/80 - Constructional details
  • H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
  • H10N 50/01 - Manufacture or treatment
  • H10N 50/20 - Spin-polarised current-controlled devices

99.

SEMICONDUCTOR DEVICE

      
Application Number 18456419
Status Pending
Filing Date 2023-08-25
First Publication Date 2024-03-21
Owner Kioxia Corporation (Japan)
Inventor
  • Kasahara, Yusuke
  • Imamura, Kappei
  • Gawase, Akifumi
  • Mori, Shinji
  • Kajita, Akihiro

Abstract

According to one embodiment, a semiconductor device includes a first conductive layer between first and second insulating layers with an oxide semiconductor column extending in the first direction through these layers. A third insulating layer covers the column. The column has a first semiconductor portion at a first position matching the first insulating layer, a second semiconductor portion at a second position matching second insulating layer, and a third semiconductor portion at a third position matching the first conductive layer. The first semiconductor portion is continuous along a second direction between the third insulating layer, the second semiconductor portion is continuous along the second direction between the third insulating layer, but the third semiconductor portion is not continuous between the third insulating layer.

IPC Classes  ?

  • H01L 29/786 - Thin-film transistors
  • H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
  • H10B 12/00 - Dynamic random access memory [DRAM] devices

100.

END MATERIAL RECOVERY APPARATUS

      
Application Number 18333779
Status Pending
Filing Date 2023-06-13
First Publication Date 2024-03-21
Owner Kioxia Corporation (Japan)
Inventor Yonezawa, Takafumi

Abstract

An end material recovery apparatus includes a plurality of cages each in which an upper portion is opened, the plurality of cages each having at least one surface formed of at least one of a mesh-like surface and a porous surface, the plurality of cages being configured to receive a mixed liquid in which an end material is mixed with a liquid from the upper portion, collect at least a part of the end material in the mixed liquid, and discharge the liquid from the at least one surface; a rotation drive mechanism configured to individually rotate the plurality of cages in a direction in which the upper portion faces downward; and a plurality of recovery containers configured to recover the end material dropped by individually rotating the plurality of cages in the direction in which the upper portion faces downward.

IPC Classes  ?

  • B01D 29/35 - Self-supporting filtering elements arranged for outward flow filtration
  • B01D 29/92 - Filters with filtering elements stationary during filtration, e.g. pressure or suction filters, not covered by groups ;   Filtering elements therefor having feed or discharge devices for discharging filtrate
  • B01D 29/94 - Filters with filtering elements stationary during filtration, e.g. pressure or suction filters, not covered by groups ;   Filtering elements therefor having feed or discharge devices for discharging the filter cake, e.g. chutes
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