G05B 19/408 - Numerical control (NC), i.e. automatically operating machines, in particular machine tools, e.g. in a manufacturing environment, so as to execute positioning, movement or co-ordinated operations by means of programme data in numerical form characterised by data handling or data format, e.g. reading, buffering or conversion of data
G05B 19/4155 - Numerical control (NC), i.e. automatically operating machines, in particular machine tools, e.g. in a manufacturing environment, so as to execute positioning, movement or co-ordinated operations by means of programme data in numerical form characterised by programme execution, i.e. part programme or machine function execution, e.g. selection of a programme
G05B 19/4097 - Numerical control (NC), i.e. automatically operating machines, in particular machine tools, e.g. in a manufacturing environment, so as to execute positioning, movement or co-ordinated operations by means of programme data in numerical form characterised by using design data to control NC machines, e.g. CAD/CAM
A memory-testing circuit in a circuit comprises: a test controller; a memory data source selection device configured to select input data for a write port of the memory from test data outputted from the test controller and data from an output of the memory; and a memory address source selection device configured to select an address for an address port of the memory from an address outputted from the test controller and one of one or more preset addresses of the memory. The one or more preset addresses correspond to one or more preserved locations of the memory configured to temporarily store data for one or more locations of the memory to be tested.
A computer-implemented method of editing, at a local client device, an engineering design (CAD model), hosted on a remote server is described. The local client device and the remote server communicate over a communications network and are remote from each other. The remote server configures an operation within a CAD model based on user input during an edit of the CAD model involving a drag. This results in a subset of the CAD model and the solving instructions required to perform the user update being generated and sent as a data package comprising the subset of the CAD model and the solving instructions to the local client device. The CAD model and any associated algorithms stored on the remote server are not communicated to the local client device.
G06F 30/12 - Geometric CAD characterised by design entry means specially adapted for CAD, e.g. graphical user interfaces [GUI] specially adapted for CAD
G06F 30/17 - Mechanical parametric or variational design
G06F 111/02 - CAD in a network environment, e.g. collaborative CAD or distributed simulation
A computer-implemented method of modelling engineering design components in a Computer-Aided Design (CAD) system is disclosed, wherein an engineering design component includes a feature having at least three occurrences of a shape element arranged in a regular pattern is described. The method is split into three stages: definition of a core set of behavioral characteristics; definition of an optional set of behavioral characteristics; and a hierarchical implementation of the optional characteristics by solving optional constraints after constraints corresponding to the core behavioral characteristics have been solved.
G06F 30/12 - Geometric CAD characterised by design entry means specially adapted for CAD, e.g. graphical user interfaces [GUI] specially adapted for CAD
An address-skipping trim search performed by a memory built-in self-test system comprises: perform memory read operations on one memory bank to determine whether it fails to correctly sense values of stored data based on a reference trim value for a previous memory bank; if the present memory bank fails, perform memory read operations to search for a new reference trim value for the present memory bank; or otherwise, treat the present reference trim value as the one for the present memory bank and proceed to testing a next memory bank. The range for searching for the new reference trim value can be limited by the present reference trim value.
G11C 29/02 - Detection or location of defective auxiliary circuits, e.g. defective refresh counters
G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
6.
METHOD OF RENDERING A TWO-DIMENSIONAL IMAGE TO A DESIGNER
A computer-implemented method of rendering, to a designer, a two-dimensional image of an assembly of part instances in a three-dimensional assembly space within a computer-aided design (CAD) system utilizing double precision to describe part assemblies is described. Such assemblies are considered to be distant from a nominal observer. A viewport on a two-dimensional image plane is defined, and a combined transform is defined in quadruple precision to enable the generation of clipping lines and/or clipping points. The clipping lines and clipping points clipping the faces and edges of the part instance in the assembly to the portion of the assembly that lies within the viewport.
The present invention discloses a method and a system for determining an assembling risk for an electronic component to be mounted to a printed circuit board, said method comprising the steps of: providing a component library comprising a number of electronic components and its specific component identifier wherein said component identifier comprises an identifier string of letters and numbers thereby providing an information for a number of physical attributes of the electronic component; providing an evaluation scheme for each of the number of physical attributes; selecting an electronic component from the component library and evaluating each of the number of physical attributes; determining for each of the number of physical attributes the intermediate risk value and calculating from the intermediate risk values a final risk score; and determining the assembling risk associated with the final risk score by comparing the final risk'score against a pre-defined risk scale.
A circuit comprises: scan chains comprising scan cells, the scan chains configured to shift in test patterns, apply the test patterns to the circuit, capture test responses of the circuit, and shift out the test responses; a decompressor configured to decompress compressed test patterns into the test patterns; and a test response compactor configured to compact the test responses, the test response compactor comprising: first X-masking circuitry configured to mask, based on first masking information, some of X bits in the test responses, the first masking information remaining the same while a test response for each of the test patterns is being shifted out, the first masking information being different for at least two of the test patterns; and second Xmasking circuitry configured to mask, based on second masking information, rest of the X bits in the test responses.
A computer-implemented method of enabling a user to select at least one component from a group comprising identical and/or non-identical components forming part of a computer-aided design (CAD) model is described. The method comprising the steps of a) receiving a seed component selection from a user via a user input device, the seed component representing component criteria desired by the user; and b)on the basis of the seed component, generating a selection comprising at least one component sharing common shape elements with the seed component. The HDBSCAN algorithm is used to cluster together components within a CAD application, which are then displayed to a user on the basis of the seed component. This enables a user to select similar components quickly and simply.
G06F 30/12 - Geometric CAD characterised by design entry means specially adapted for CAD, e.g. graphical user interfaces [GUI] specially adapted for CAD
G06F 16/532 - Query formulation, e.g. graphical querying
G06F 16/583 - Retrieval characterised by using metadata, e.g. metadata not derived from the content or metadata generated manually using metadata automatically derived from the content
G06T 19/20 - Editing of 3D images, e.g. changing shapes or colours, aligning objects or positioning parts
10.
MULTI-LEVEL PREDICTIONS IN WORKFLOW LOGIC OF COMPUTER-AIDED DESIGN APPLICATIONS
A computing system (100) may logic construction engine (110) configured to construct, via multi-level prediction, workflow logic (220) to process a computer-aided design (CAD) model. The logic construction engine (110 may do so by identifying a multi-node sequence (230, 430) inserted into the workflow logic (220), aggregating past workflow data (240) specific to the multi-node sequence (230, 430), determining a node prediction (250, 350, 450) in the workflow logic (220) for the multi-node sequence (230, 430) based on the aggregated past workflow data (240), and providing the node prediction (250, 350, 450) as a suggested insertion for the workflow logic (220).
G05B 19/4097 - Numerical control (NC), i.e. automatically operating machines, in particular machine tools, e.g. in a manufacturing environment, so as to execute positioning, movement or co-ordinated operations by means of programme data in numerical form characterised by using design data to control NC machines, e.g. CAD/CAM
A computing system (100) may include a computer-aided design (CAD) face access engine (108) configured to access a CAD object and an imprint-based meshing engine (110) configured to define an imprint region (220, 320, 520, 610, 720) for a face (210, 310, 510, 710) of the CAD object and determine that the imprint region (220, 320, 520, 610, 720) meets constraint criteria. Responsive to a determination that the imprint region meets the constraint criteria, the imprint-based meshing engine (110) may modify the imprint region (220, 320, 520, 610, 720) into an adapted imprint region (330, 530, 620, 820) and generate an output mesh (410, 910) using the adapted imprint region (330, 530, 620, 820).
The invention relates to a computer implemented method for providing a recommender system (SRS) for a design process of a complex system, wherein the recommender system (SRS) is shared by a plurality of users (UlCl, U2C1, U1C2), wherein the complex system comprises a plurality of connectable com- ponents and is designed in a design process by a sequence of design steps (DS1, DS2) wherein in each design step a partial design (PD) is created until a completed design (CD) is obtained, wherein a partial design (PD) of one step and a partial de- sign (PD) of a subsequent step differ in a design difference (DELTA) reflecting a difference in at least one element comprising a component or/and connection of the components, and wherein the shared recommender system (SRS) provides at each design step (DS1, DS2) a prediction of the subsequent design difference (DELTA).
G06F 30/12 - Geometric CAD characterised by design entry means specially adapted for CAD, e.g. graphical user interfaces [GUI] specially adapted for CAD
G06F 30/27 - Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
G06F 111/02 - CAD in a network environment, e.g. collaborative CAD or distributed simulation
nn thnn thnn th level expansion are marked as displayable. The process is repeated for all other branch values shown in the initial view. A revised view showing only those values from the initial view in which the branch value, a child value or a descendant value were marked as displayable is then displayed to the user.
This application discloses a computing system to receive measurements of solder paste disposed on a printed circuit board using a solder paste stencil, and correlate the measurements of the solder paste disposed on the printed circuit board to a solder stencil design describing the solder paste stencil utilized during an application of the solder paste on the printed circuit board. The computing system can correlate the solder paste measurements to the solder stencil design by determining a transfer efficiency of the solder paste on the printed circuit board based, at least in part, on the solder paste stencil and the measurements of the solder paste disposed on the printed circuit board. The computing system can detect a cause of a production defect associated with the printed circuit board based, at least in part, on the transfer efficiency of the solder paste on the printed circuit board.
H05K 13/08 - Monitoring manufacture of assemblages
H05K 3/12 - Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using printing techniques to apply the conductive material
15.
AUTOMATED CELL BLACK BOXING FOR LAYOUT VERSUS SCHEMATIC
Text containers comprising information of cell ports are determined based on statements for cell ports in a rule file. Drawn layers comprising cell ports are determined based on the determined text containers or based on statements for attaching each of the test containers to a layout design layer in the rule file. Layout design layers connected to the drawn layers comprising cell ports are determined based on statements for connecting layout design layers in the rule file. A file for cell port detection is generated which associates each of the text containers comprising information of cell ports with one or more of the drawn layers comprising cell ports and one or more of the layout design layers connected to the one or more of the drawn layers comprising cell ports. The file for cell port detection can be used for extracting ports for cells to be black boxed.
There is described building automation systems, methods, and computer readable media for piping graphic control. Field devices (120-126) associated with HVAC equipment are identified and an HVAC piping graphic associated with the field devices (120-126) are generated at the management device (104-108). The HVAC piping graphic is modified at a processor (206) of the management device (104-108) in response to receiving user input at a user interface (111) of the management device (104-108). In particular, a pipe element (358) and a pipe coupling element (360) are integrated with the HVAC piping graphic based on the user input. Data points of the building automation system (100) are provided at the user interface (222) based on the pipe element (358) and the pipe coupling element (360). Runtime values are monitored, and the building automation system (100) are dynamically controlled at the management device (104-108) based on the data points.
A computing system to parse a schematic design illustrating a circuit design for an electronic system to identify text and enclosures representing circuit devices of the electronic system, The computing system can classify the text based on a proximity of the text to the enclosures in the schematic diagram, and match the text to the enclosures in the schematic diagram based on the classifications, which correlates the circuit devices represented by the enclosures to the text matched to the enclosures. The computing system can identify one of the circuit devices includes a connector having one or more pins, and correlate the text matched to the enclosure to at least one of the pins based on a relative alignment of the pins with the text. The computing system can generate an interactive technical file that includes the correlations of the circuit devices and pins to the text matched to the enclosures.
G06V 10/764 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using classification, e.g. of video objects
A computer-implemented method of determining the dimensions of a space-filling lattice in a solid model is disclosed. Initially information including a lattice, a set of faces and data indicating a spatial relationship between the lattice and each face in the set is received. A set of points indicating the intersection positions where each rod intersects a face is then identified, and each intersecting rod is classified based upon whether or not each subset of mutually tolerantly coincident points within the set indicates that a rod is divided by a face. If a rod is divided the lattice is modified by adding a new ball where the rod is divided and classifying the new rods either side of it. These classifications are then spread to adjacent rods without crossing any new ball to establish the complete set of surviving rods. Each connected set of surviving rods is used to instantiate a new lattice.
A method of monitoring messages from a sensor using an integrated circuit is provided, wherein the messages include data measured by that sensor. The method includes: reading a first message from interconnect circuitry of the integrated circuit, the interconnect circuitry connecting the sensor to one or more core devices configured to process the message; calculating a first hash value for the first message; comparing the first hash value to one or more prior hash values stored in a hash store, each prior hash value corresponding to a message that was read from the interconnect circuitry prior to the first message; and performing a corrective action if the difference between the first hash value and at least one of the prior hash values stored in the hash store is above a predetermined threshold.
G08C 25/00 - Arrangements for preventing or correcting errors; Monitoring arrangements
H04Q 9/00 - Arrangements in telecontrol or telemetry systems for selectively calling a substation from a main station, in which substation desired apparatus is selected for applying a control signal thereto or for obtaining measured values therefrom
G06F 11/07 - Responding to the occurrence of a fault, e.g. fault tolerance
20.
METHOD OF MEASURING THE JUNCTION TEMPERATURE OF A SEMICONDUCTOR DEVICE
Tjj Tjj j . Each of the plurality of measurements of the first temperature-sensitive parameter and the at least second temperature-sensitive parameter is synchronized with a switching event of the semiconductor switching element.
G01K 7/01 - Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat using semiconducting elements having PN junctions
21.
CONSTRUCTION OF CONFORMAL COOLING CHANNELS FOR INJECTION MOLD DESIGNS
A computing system (100) may include a design access engine (108) configured to access an injection mold design (210) and a channel construction engine (110) configured to construct conformal cooling channels (510) for the injection mold design (210). The channel construction engine (110) may do so by extracting a cooling surface (600) of the injection mold design (210), generating a central offset surface (220) with a same shape as the cooling surface (600), projecting cooling lines (310) on to the central offset surface (220), detecting sharp portions (410) of the projected cooling lines (320), smoothing the detected sharp portions (410) of the projected cooling lines (320), and generating the conformal cooling channels (510) using the smoothed cooling lines (420) along the central offset surface (220) as a center line for the conformal cooling channels (510). It also relates to the method and a non-transitory machine-readable medium (820) comprising instructions (822, 824).
B29C 33/02 - SHAPING OR JOINING OF PLASTICS; SHAPING OF MATERIAL IN A PLASTIC STATE, NOT OTHERWISE PROVIDED FOR; AFTER-TREATMENT OF THE SHAPED PRODUCTS, e.g. REPAIRING - Details thereof or accessories therefor with incorporated heating or cooling means
B29C 64/386 - Data acquisition or data processing for additive manufacturing
The current disclosure describes method of verifying integri¬ ty of data from a device under test. The method comprises ob¬ taining network data from the device under test, wherein the network data is generated by the device under test based on a test data from a source device by transforming the test data from a first domain to a second domain and framing the trans¬ formed test data in a first protocol, deframing the received network data from the first protocol to a second protocol for extracting the transformed test data, obtaining the test data from the source device for verifying the transformed test da¬ ta and verifying the integrity of the transformed test data based on the test data using one of a block error rate (BLER) and bit error rate (BER).
A computing system (100) may include a quantifier determination engine (110) configured to determine a defectivity quantifier (310) for a lithographical circuit fabrication process performed with a target value (210) for a process parameter, including by modifying the target value (210) to obtain an off-target value (220) for the process parameter, determining a defectivity quantifier (250) for the lithographical circuit fabrication process performed with the off-target value (220), and extrapolating the defectivity quantifier (310) for the lithographical circuit fabrication process performed with the target value (210) from the determined defectivity quantifier (250) for the lithographical circuit fabrication process performed with the off-target value (220). The computing system (100) may also include a quantifier provision engine (112) configured to provide the determined defectivity quantifier (310) for assessment of the lithographical circuit fabrication process.
G06F 30/20 - Design optimisation, verification or simulation
G06F 30/367 - Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
A computing system implementing a design characterization tool can sample a distribution of values for manufacturing variation of an integrated circuit described by a circuit design. The design characterization tool can order the samples based on predicted output values of the circuit design set with characteristics in the samples of the values for manufacturing variation. The computing system can implement an analog simulator to simulate the circuit design utilizing a subset of the samples of values for manufacturing variation to identify simulated output values for an output distribution model. The design characterization tool can estimate an error in the order of the samples associated with the predicted outputs of the circuit design based on the simulated output values in the output distribution model. The design characterization tool can modify the output distribution model to correct a bias based on the estimated error in the order of the samples.
The current disclosure describes a method of generating a simulated multipath fading channel data. The method comprises obtaining an IQ sample data, selecting one or more radio samples from the IQ sample data for appending to the IQ sample data, generating a second IQ sample data by appending the selected one or more radio samples prior to the start radio sample of the IQ sample data and generating the simulated multipath fading channel using the second IQ sample data and a predefined set of propagation delay and attenuation coefficients associated with a channel model.
This application discloses a computing system (400) to generate a product model (409) that describes attributes of a product including an electronic system (401). The computing system (400) can implement a machine-learning algorithm having been trained with metadata populated in previously generated product models for different electronic systems, which can determine one or more sets of metadata capable of being correlated to the electronic system included in the product model based on the attributes of the electronic system described in the product model. The sets of metadata can correspond to different design constraints in the product model associated with electrical connectivity for the electronic system and their corresponding parameter values. The computing system can populate at least one of the sets of metadata into the product model to correlate with the electronic system.
G06F 30/27 - Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
A computing system (100) may include a voxel access engine (108) configured to access voxel data (210, 310) and a voxel processing engine (110). The voxel processing engine (110) may identify and label thin features in the voxel data (210, 310), smooth the voxel data (210, 310) to preserve the thin features, and convert the voxel data (210, 310) to form a faceted representation (320). The voxel processing engine (110) may also adaptively perform a pressing process on the faceted representation (320). Responsive to a determination that a pressing reapplication criterion is satisfied, the voxel processing engine (110) may modify the voxel data (210, 310), convert the modified voxel data (340) to form the faceted representation (320) of the object, and perform the pressing process on the faceted representation (320) of the object formed through the modified voxel data (340).
Today's automation or manufacturing systems are engineered based on solution documents that are typically written in natural language (e.g. English) with domain-specific vocabulary. It is recognized that it can be cumbersome (e.g., time, cost, etc.) to engineer systems, for instance develop software, that operate in multiple domains, based on such solution documents. An engineering computing system can generate executable code (e.g., tenant-specific executable metadata) for an application from the requirements document that defines business requirements written in natural language.
This application discloses distributed forward error correction in hardware assisted verification platforms (300) including a hardware- assisted verification system (320) to emulate an electronic system (322) described by a circuit design (301). The hardware-assisted verification system (320) can implement forward error correction circuitry (324) to analyse a data packet (311) for use by the emulated electronic system (322) during functional verification operations of the circuit design (301), which can identify that the data packet includes one or more corrupted bits (321). The forward error correction circuitry (324) can transmit the corrupted data packet (321) to a computing system (330) implementing an error correction algorithm configured to perform error correction operations (332) on the corrupted data packet (321). The computing system implementing the error correction algorithm (330) can generate a corrected data packet (331) during the error correction operations and transmit the corrected data packet to the hardware-assisted verification system (320) for use by the emulated electronic system (322) during functional verification operations of the circuit design (301).
G06F 30/331 - Design verification, e.g. functional simulation or model checking using simulation with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
G06F 11/36 - Preventing errors by testing or debugging of software
H04L 1/00 - Arrangements for detecting or preventing errors in the information received
30.
SHAPE MATCHING-BASED LAYOUT VERSUS SCHEMATIC FOR PHOTONIC CIRCUITS
A preliminary netlist comprising the photonic devices and location and rotation information for each of the photonic devices is extracted from the original layout design. In the extraction, each of the photonic devices is treated as a black box. A geometric pattern for the each of the photonic devices is then identified in a group of geometric patterns for each of the photonic devices based on physical properties of the each of the photonic devices specified in the circuit design. A new layout design is generated based on the identified geometric pattern for each of the photonic devices, the location and rotation information for each of the photonic devices, and the preliminary netlist. Geometric elements in each of the photonic devices in the new layout design are compared with corresponding geometric elements in the original layout design.
G02B 6/12 - Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
G06F 30/3308 - Design verification, e.g. functional simulation or model checking using simulation
G06F 30/367 - Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
G06F 30/398 - Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
A computing system (100) may include a linear mesh access engine (108) configured to access a linear mesh (120, 210) and a target geometry (130) as well as curved mesh generation engine (110) configured to construct a curved mesh (140). Construction of the curved mesh (140) may include projecting (406) the linear mesh (120, 210) on to the target geometry (130) to form a projected mesh (220), determining (408) deformation patches included in the projected mesh (220), selecting (410) a cost function (340) to apply to the deformation patches from a set of available cost functions (320), iteratively adapting (412) the deformation patches based on the selected cost function (340) to obtain adjusted mesh elements (350), and forming (414) the curved mesh (140) as a combination of the adjusted mesh elements (350) and portions of the projected mesh (220) not determined as part of the deformation patches.
A computing system (100) includes a computer-aided design (CAD) face access engine (108) configured to access a CAD object and an imprint-based meshing engine (110) configured to define an imprint region (220) for a face (210, 310) of the CAD object and decompose the face (210, 310) into virtual faces, including an imprinted virtual face (240, 320) and a remainder virtual face (250, 330). The imprint¬ based meshing engine (110) is also configured to mesh the imprinted virtual face, mesh the remainder virtual face, and merge the imprint region mesh and the remainder region mesh together to form an output mesh (350, 400, 700), including by extending a portion of the imprint region mesh into the remainder portion (230) of the face (210, 310) or extending a portion of the remainder region mesh into the imprint region (220).
A computer-implemented method of bounding spatial data in a hierarchical product structure with hierarchical transforms is described. Initially, the part or part assembly at the lowest level of a hierarchical assembly path is selected. Then, a hierarchical merge of the spatial bounds of the bounding box(es) of the part or part assembly is performed to generate a set of intermediate spatial bounds. Following this, a merge of the set of oriented bounds of the bounding box(es) of the part or part assembly is performed to generate a reduced set of oriented bounds. Finally, the intermediate bounds and the reduced set of oriented bounds are stored for use in configuring the assembly path when building a product from the hierarchical product structure.
A computer-implemented method of extending a mixed sheet within a B-rep model is described. The mixed sheet comprises surfaces having different geometries, such as a mesh positioned between first and second classical geometry surfaces. A first guide curve is defined, located at the boundary of a first surface for a length corresponding to the desired mixed sheet extension adjacent the first surface. A second guide curve may also be defined, located at the boundary of a second surface for a length corresponding to the desired mixed sheet extension adjacent the second surface. At least one extension mesh rung is created by generating facets between the two external mesh vertices using first and second extension vectors, wherein the first extension vector has a pre-determined spatial relationship to the first guide curve. If included, the second extension vector has a pre-determined spatial relationship to the second guide curve.
A computer-implemented method of handling large transforms in a computer-aided design (CAD) solid model utilising double precision to describe a physical assembly of parts is described. If the unit size of a transform of interest exceeds a pre-determined threshold, the double precision of the transform is converted to quadruple precision whilst maintaining the double precision of the assembly (108). The results of any operation are output in double precision (112). A computer program and method of adapting an existing CAD model are also described.
Embodiments of the present disclosure provide a method and system for digital plant system model creation and simulation and a storage medium. The method includes: receiving a digital model created by a user based on a modeling library; in the modeling library, a digital plant system is divided into multiple subsystems, and motion joints in each subsystem are set with at least one option of at least one solution parameter of dynamics, kinematics and articulation; for each motion joint in the digital model, associating a corresponding algorithm engine in a simulation engine with the motion joint according to a solution parameter of the motion joint; the simulation engine comprises a kinematics algorithm engine, a dynamics algorithm engine and an articulation algorithm engine; using the corresponding algorithm engine to solve the motion joint associated with the algorithm engine. The technical scheme in embodiments of the present disclosure can improve the performance, stability and accuracy of the virtual digital plant.
G05B 19/418 - Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control (DNC), flexible manufacturing systems (FMS), integrated manufacturing systems (IMS), computer integrated manufacturing (CIM)
G06F 30/20 - Design optimisation, verification or simulation
G06F 9/455 - Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
37.
SPATIAL DECOMPOSITION-BASED INFILLS OF UNIT CELL DESIGNS FOR COMPUTER-AIDED DESIGN (CAD) OBJECTS
A computing system (100) may include a decomposition engine (110) configured to access a unit cell design (210) and a fill region (220) of a computer-aided design (CAD) object to infill with instances of the unit cell design (210) and spatially decompose the fill region (220) into power-of-two boxes (240). The power-of-two boxes (240) may have dimensions equal to dimensions of the unit cell design (210) multiplied by a power of two. The computing system (100) may also include an infill engine (112) configured to infill the fill region (220) by performing a joining operation of aggregated bodies based on the spatial decomposition of the fill region (220). Each given aggregated body may comprise a number of unit cell designs equal to a power of two that are joined together to form the given aggregated body.
This application discloses a hotspot identification system to generate process variability bands for structures of an integrated circuit capable of being fabricated utilizing at least one lithographic mask based, at least in part, on a mask layout data describing the lithographic mask and a distribution of manufacturing parameters during fabrication. The hotspot identification system can utilize the process variability bands to identify a subset of the structures that correspond to hotspots in the integrated circuit and identify corresponding values for the manufacturing parameters associated with the identified hotspots. A wafer testing system can implement a real-time wafer assessment process by comparing measured manufacturing parameters associated with a fabricated integrated circuit to the values for the manufacturing parameters associated with the identified hotspots, and dynamically identifying a disposition for the fabricated integrated circuit corresponding to one or more structures associated with the identified hotspot based on the comparison.
A method of generating and monitoring a digital signature representing activity observed on signals on an integrated chip in a normal mode of operation is disclosed. A signal se- lector feeds a signal as a selected signal to a temporary memory store to create a value in the temporary memory store. This value is used as the basis of a digital signature repre- senting activity observed on the signal and is compared to a corresponding stored digital signature representing expected activity on the signal. If the comparing indicates a mis- match between the digital signature and the corresponding stored digital signature, an alarm signal is generated. An integrated chip digital signal generator and monitor is also disclosed.
G06F 21/71 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
40.
MODELING METHOD AND SYSTEM FOR TUBULAR STRUCTURE, AND COMPUTER-READABLE STORAGE MEDIUM THEREOF
A modeling method for a tubular structure includes: acquiring a structural wire-frame; generating, at each of non-manifold nodes of the structural wire-frame, a polyhedral structure formed by faces of a polyhedron; generating, at each of manifold nodes of the structural wire-frame, a connecting face; generating, at each of end nodes of the structural wire-frame, an end face; connecting vertices of the connecting wire-frame, vertices of the connecting face, and vertices of the end face; and carrying out curved-surface subdivision.
This application discloses a computing system implementing a shared management system (340) to distribute virtual product models (343), each corresponding to a shared product model (341) describing a product having an electronic device with multiple printed circuit boards, to multiple printed circuit board layout tools (320-1 to 320-N). The printed circuit board layout tools (320-1 to 320-N) separately modify the corresponding virtual product models (343) to generate layout designs for the multiple print circuit boards and generate at least one system-level design rule describing a physical limitation for the electronic device. The shared management system (340) can update the shared product model (341) based on the modifications to at least one of the virtual product models by the printed circuit board layout tools (320-1 to 320-N), and transmit a notification (347) to at least one of the printed circuit board layout tools when the updated shared product model (341) conflicts with the physical limitation for the electronic device described in the at least one system-level design rule.
The current disclosure describes a method of determining a bit length of an IQ sample associated with a first data frame. The method comprises determining a first parameter associated with a payload length of the first data frame, determining a second parameter indicative of a number of physical resource blocks in the first data frame, detecting a presence of a compression header based on the first and second parameters and determining the bit length of the IQ sample from one of the detected compression header and the first and second parameters. Accordingly, in accordance with the above method, the bit length of the IQ sample can be determined automatically from the information available in the data frame. Accordingly, this eliminates the need for manual entry of parameters into the packet analyzer and additionally eliminates the likelihood of errors to due incorrect entry.
A computing system (100) may include physical devices (221, 222, 223, 224, 225, 226) of a manufacturing facility (210) and a message processing engine (110). The message processing engine (110) may be configured to receive, from the physical devices (221, 222, 223, 224, 225, 226) of the manufacturing facility (210), update messages (230) for product manufacture processes performed by the manufacturing facility (210) and parse the update messages (230) to determine a value of a promoted attribute (240) for each of the update messages (230). The message processing engine (110) may also be configured to group the update messages into different message groups according to the determined value of the promoted attribute (240) and sequentially process update messages grouped into a particular message group (310) for a particular value of the promoted attribute (240).
Verification of model-based systems engineering artifacts A method of verifying a model-based system engineering, MBSE, artifact comprising the steps of: translating (SI), by a translator implemented in software, the MBSE artifact into formulas of a first- order logic, checking (S4), by a solver executing a decision procedure implemented in software and operating on the formulas of the first order logic, whether or not a conjunction of the formulas is satisfiable.
A first circuit design and a second circuit design are analyzed to determine part of the second circuit design structurally similar to part of the first circuit design. A first set of test patterns for the first circuit design is modified to generate a second set of test patterns for the second circuit design by reusing values of bits in the first set of test patterns associated with the part of the first circuit design as values of bits in the second set of test patterns associated with the part of the second circuit design. Fault simulation is performed on the second circuit design using the second set of test patterns to determine a subset of faults undetectable by the second set of test patterns. Test pattern generation is performed for the subset of faults to generate a third set of test patterns for the second circuit design.
Systems and a method for detecting a false error in a set of errors detected on components of a board inspected by an AOI machine. Input data are received and wherein the input data comprise data originated from AOI machine's inspection results of a given inspected board marked as failed. A false error detector is applied to the input data and wherein the detector is modeled with a trained function and wherein the detector generates output data. The output data is provided and wherein the output data determines whether at least one of the component errors reported by the AOI machine for the given board is a false error.
A computing system (100) may include a database system (112) and an application server (102). The application server (102) may include a logic packaging engine configured to identify a product (210) at a particular stage of a manufacturing process, extract parameter values for the product (210), and determine processing logic (220) applicable to the product (210). The processing logic (220) may be designed to query the product database (122) for the product (210). The logic packaging engine (110) may also be configured to generate an execution package (230) for the database system (112) to perform the query on the product database (122), and the execution package (230) can include the parameter values for the product (210) at the particular stage in the manufacturing process and metadata references (324, 334, 344) to corresponding query templates (410) stored on the database system (112).
ALLOCATION OF SECONDARY COMPUTING RESOURCE FOR MULTIPLE OPTICAL PROXIMITY CORRECTION (OPC) PROCESSES OF AN ELECTRONIC DESIGN AUTOMATION (EDA) APPLICATION
A computing device (100) may include a CPU (106) and a secondary computing resource (108), such as a GPU (210). The computing device (100) may also include a lithography simulation server engine (110) configured to identify a first OPC process (221) of an EDA application to perform a first OPC simulation task through the computing device (100) as well as a second OPC process (222) of the EDA application to perform a second OPC simulation task through the computing device (100). The lithography simulation server engine (110) may further be configured to control access to the secondary computing resource (108) for performing the first OPC simulation task and the second OPC simulation task via a single multi-threaded process, instead of allowing access to the secondary computing resource (108) by multiple OPC processes that include the first OPC process (221) and the second OPC process (222).
A computing system implementing a design characterization tool can sample a distribution of values describing manufacturing variation for an integrated circuit described by a circuit design. The design characterization tool can utilize a set of the samples to generate a surrogate model of the circuit design, and can order another set of the samples based on predicted outputs of the surrogate model. The design characterization tool can simulate the surrogate model or the circuit design utilizing the ordered samples, and stop the simulations prior to all of the samples from the distribution having been utilized in the simulations. The design characterization tool can utilize a confidence interval stopping condition or a drought stopping condition to determine when to stop the simulations. The design characterization tool can utilize results of the simulations to characterize operational variation of the circuit design to the manufacturing variation described in the distribution of the values.
G06F 30/3308 - Design verification, e.g. functional simulation or model checking using simulation
G06F 30/367 - Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
50.
TRANSITION STRUCTURE GENERATIONS FOR INTERNAL LATTICE STRUCTURE OF COMPUTER-AIDED DESIGN (CAD) OBJECTS
A computing system (100) may include a transition generation engine (110) configured to access a computer-aided design (CAD) object (210) comprising an external surface (220) and an internal lattice structure (222) represented through repeating unit cells (224) of a lattice design, the internal lattice structure (222) represented as a signed distance field (SDF). The transition generation engine (110) may generate a transition structure (230) for the CAD object (210) within a transition distance (310) from the external surface (220), including by applying a secondary SDF (320) to modify a portion of the internal lattice structure (222) within the transition distance (310) from the external surface (220). The computing system (100) may also include an object processing engine (112) may be configured to process the CAD object (210) comprising the transition structure (230) in support of physical manufacture of the CAD object (210).
G06F 30/12 - Geometric CAD characterised by design entry means specially adapted for CAD, e.g. graphical user interfaces [GUI] specially adapted for CAD
G06F 30/17 - Mechanical parametric or variational design
G06F 111/20 - Configuration CAD, e.g. designing by assembling or positioning modules selected from libraries of predesigned modules
52.
METHOD AND SYSTEM FOR ACTIVATING A PCB ANALYSIS UTILIZING MANUFACTURING CAPABILITY DATA
Systems and a method for activating a PCB analysis utilizing manufacturing capability data shared in a multi-tenant collaborative network in a mixed cloud and on-premise environment. Access to a tenant's account of a DFM application deployed on a tenant's premise is provided. The DFM application is enabled to activate a PCB analysis on a DFM profile comprising manufacturing capability data. Via the tenant's account, a cloud data layer is requested an utilization authorization of a given DFM profile stored in the cloud data layer. In case of authorized utilization, the given DFM profile is downloaded into the premise, embedded in a locked DFM envelope, hereinafter called DFM envelope. The DFM envelope is by locking together the given DFM profile with an injected identifier identifying said authorized tenant's account. Via the DFM application when logged into the tenant's account, a PCB analysis is activated by permitting the unlocking of the DFM profile from the DFM envelope only when the identifier of the tenant's account is the same as the injected identifier.
G06F 7/66 - Digital differential analysers, i.e. computing devices for differentiation, integration or solving differential or integral equations, using pulses representing increments; Other incremental computing devices for solving difference equations wherein pulses represent unitary increments only
A testing circuit configured to test and diagnose a read-only memory comprises two multiple-input signature registers configured to generate two sets of signatures for multiple iterations of reading some or all of words stored in the read-only memory, control circuitry configured to control, according to a test algorithm, from which of the outputs of the read-only memory each of the two multiple-input signature registers receives test response signal bits for each of the reading operations during each of the iterations, and a faulty element location determination device configured to generate a faulty element location signal for the read-only memory based on results of comparing the two sets of signatures with reference signatures.
A computing system (100) includes a model access engine (108) configured to access a CAD model (210) comprised of multiple CAD parts. The computing system (100) also includes a model explosion engine (110) configured to construct a blocking data structure (230) for the CAD model (210) that stores a blocking state for each pair of CAD parts of the CAD model (210) as well as an explosion graph (310) for the CAD model (210). Iterative generation of the explosion graph (310) by the model explosion engine (110) includes querying the blocking data structure (230) to determine unblocked CAD parts for which to insert a node into the explosion graph (310). The model explosion engine (110) also is configured to generate an exploded view representation (410) of the CAD model (210) using the constructed explosion graph (310).
The described method as a key enabler for Optical Inspection dynamically uses individual marks like fiducials, barcodes, data matrix codes ("markers") in the scenes, beyond their basic presence, meaning the change of situation between a first processing status and a subsequent processing status in the processing station. The same markers are simultaneously used for a) the identification of components ("comp") b) the identification of locations ("loc") and c) the definition of dependencies between identity and location (valid, invalid) and d) the automated detection and evaluation of the dependencies.
G05B 19/418 - Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control (DNC), flexible manufacturing systems (FMS), integrated manufacturing systems (IMS), computer integrated manufacturing (CIM)
H01B 13/012 - Apparatus or processes specially adapted for manufacturing conductors or cables for manufacturing wire harnesses
56.
METHOD AND SYSTEM FOR DYNAMICALLY RECOMMENDING COMMANDS FOR PERFORMING A PRODUCT DATA MANAGEMENT OPERATION
A method and system for dynamically recommending commands for performing a PDM operation on product data objects in a product data management environment is disclosed. In one embodiment, a method includes determining a context in which a user is operating within a product data management environment. The method includes dynamically determining a set of commands suitable for performing a candidate PDM operation on the product data objects based on the determined context. Furthermore, the method includes computing a score for each of the commands suitable for performing the candidate PDM operation on the product data objects. Moreover, the method includes assigning a rank to said each command suitable for performing the candidate PDM operation based on the score associated with said each command, and outputting one or more commands from the set of commands on a graphical user interface based on the rank assigned to said each command.
A method and system for validating product and manufacturing information associated with a geometric model in a computer-aided design environment is disclosed. The method (200) includes the steps of generating (202) a geometric model of a physical object in the computer-aided design environment, wherein the geometric model of the physical object includes product and manufacturing information. The method further includes extracting (204) the product and manufacturing information from the geometric model, and validating (208) the extracted product and manufacturing information using at least one checker, wherein the checker includes one or more logical elements capable of validating the product and manufacturing information. The method includes outputting (210) the results of validation of the product and manufacturing information on a graphical user interface.
Aspects of the disclosed technology relate to techniques for applying optical proximity correction to free form shapes. Each optical proximity correction iteration comprises: computing edge adjustment values for the straight line fragments based on edge placement errors derived from an optical proximity correction iteration immediately preceding the each of the plurality of optical proximity correction iterations, adjusting locations of the straight line fragments based on the determined edge adjustment values, determining smooth boundary lines for the layout features based on the straight line fragments on the adjusted locations, performing a simulation process on the layout features having the smooth boundary lines to determine a simulated image of the layout features, and deriving the edge adjustment errors for the straight line fragments based on comparing the simulated image with a target image of the layout features.
G03F 1/36 - Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
G03F 1/70 - Adapting basic layout or design of masks to lithographic process requirements, e.g. second iteration correction of mask patterns for imaging
A computing system implementing a design verification system can classify a mixed-signal circuit design describing an electronic device based on a design topology of the mixed-signal circuit design. This classification can be performed by identifying a top-level design block in the mixed-signal circuit design, traversing a connectivity of a design hierarchy to identify lower-level design blocks in the mixed-signal circuit design, and classifying the mixed-signal circuit design based on at least one of a design type of the top-level design block, design types of the lower-level design blocks, or a connectivity of design blocks in the mixed-signal circuit design. The design verification system can selectively partition the mixed-signal circuit design into an analog partition and a digital partition based on the classification, and simulate the analog partition of the mixed-signal circuit design with an analog simulator and the digital partition of the mixed-signal circuit design with a digital simulator.
A method and system for generating a three-dimensional model of a multi-thickness object in a formed state in a computer-aided design (CAD) environment is disclosed. The method includes receiving a request to generate a feature of a three-dimensional model, creating a virtual datum plane, and dynamically computing an offset value for the feature with reference to the virtual datum plane based on a thickness value. The offset value determines an offset between the virtual datum plane and one surface of the feature. The method includes generating the feature of the three-dimensional model in the formed state with reference to the virtual datum plane based on the thickness value, a location of the feature, and the offset value. The method also includes outputting the three-dimensional model of the multi-thickness object having the generated feature in the formed state.
A computing system (100) may include a constraint learning engine (110) and a constraint generation engine (112). The constraint learning engine (110) may be configured to access a computer- aided design (CAD) assembly (130) comprising multiple CAD parts and generate a representation graph of the CAD assembly (130), determine constraints in the CAD assembly (130), wherein the constraints limit a degree of movement between geometric faces of different CAD parts in the CAD assembly (130), insert constraint edges into the representation graph that represent the determined constraints; and provide the representation graph as training data to train a machine-learning model (120). The constraint generation engine (112) may be configured to generate constraints for a different CAD assembly by applying the machine-learning model (120) for the different CAD assembly.
G06F 30/12 - Geometric CAD characterised by design entry means specially adapted for CAD, e.g. graphical user interfaces [GUI] specially adapted for CAD
Systems and methods for simulation and testing of multiple virtual electronic control units (VECUs). A method (1000) includes executing, by one or more computer systems (101), a first VECU (502). The method includes executing a virtual bus (510), the virtual bus (510) associated with the first VECU (502). The method includes executing at least one second VECU. The method includes simulating a multiple-VECU system by managing communications, using the virtual bus (510), between the first VECU (502) and the at least one second VECU.
A computing system to generate models of managed devices and applications in an Internet of Things (IOT) system by identifying each endpoint in the managed devices and applications capable of transmitting or receiving the data and defining flows for data from the endpoints in sensors to endpoints of IOT servers via endpoints of the programmable edge device applications. The computing system can develop a data flow map to define a connectivity of the programmable edge device applications to the sensors and the servers in the IOT system for exchanging the data from the sensors to the servers in the IOT system via the programmable edge device applications. The computing system can prompt configuration of the managed devices and applications in the IOT system based on the data flow map, which implements the connectivity of the programmable edge device applications to the sensors and to servers in the IOT system.
A method of protocol processing comprising a main program code (MC), the main program code (MC) comprising instructions for processing different protocol elements (MAC SA, MAC DA) of a data packet stream (S1) of a transport protocol (TP), the main program code (MC) comprising one or more code segments, the method comprising the steps of: assigning a latency requirement and/or bandwidth requirement to one or more of the code segments of the main program code (MC), compiling each of the code segments according to the assigned latency and/or bandwidth requirement into a respective target code for executing each of the target codes by different processors (P1, P11, P12, P13, P2).
A method and a system for constructing a final computer-aided design model of an object, the method comprising: displaying a first model of the object, the first model defining a plurality of regions arranged so as to represent the object; responsive to a first user actuation, receiving a first modification to the first model; comparing the first modification to the first model so as to generate a first difference between the first modification and the first model; responsive to a second user actuation, receiving a second modification to the first model; comparing the second modification to the first model as to generate a second difference between the second modification and the first model; before altering the first model, making a comparison of the first difference and the second difference; and based on the comparison, generating the final model of the object.
The present invention discloses a computer implemented method of dynamically verifying clock domain crossing (CDC) paths in a register-transfer level (RTL) design. In addition to static analysis, formal analysis and simulation steps, each CDC path is allocated a persistent unique identifier. This enables the updating of a centralized results data-base using the persistent unique identifier to label the associated CDC protocol assertions, functional coverage and results of the formal analysis and simulation. In addition, prior to simulation analysis, CDC protocol assertions that have been proven during formal analysis are turned off, resulting in the simulation run only being carried out for non-proven CDC protocol assertions.
A method is provided for generating test data for testing radio equipment (DU, RU, UE). The method comprises the steps of: determining, by a test apparatus (10), one or more beam identifiers (1,..., n); selecting, by the test apparatus, based on the one or more beam identifiers (1,..., n) one or more radio channel models; receiving, by the test apparatus (10), a baseband signal representing I/Q data of one or more beamforming antennas; processing, by the test apparatus (10), the baseband signal representing I/Q data according to the selected radio channel model; and transmitting, by the test apparatus (10), the processed baseband signal representing I/Q data to a radio equipment under test (DU, RU, UE).
A computing system (100) may include a design space access engine (108) configured to access a design space (210) of a physical structure. The computing system (100) may also include a structural design engine (110) configured to encode the design space (210) into a set of 3-dimensional (3D) rectangles (222). Each 3D rectangle (222) may define candidate beam locations (224) in the physical structure and candidate beam locations (224) of the 3D rectangles may be defined by lines between vertex pairs of each 3D rectangle (222). The structural design engine (110) may also provide the encoded design space (220, 320, 420, 520) as an input to a machine-learning (ML) model (120), generate, through the ML model (120), a design of the physical structure based on the encoded design space (220, 320, 420, 520), and provide the design of the physical structure in support of manufacture of the physical structure.
A method and system for performing clearance analysis of a product assembly in a computer- aided design (CAD) environment is disclosed. A method includes receiving a request for evaluating clearance between components of a product assembly in a CAD environment from a user device. The request includes a unique identifier of the product assembly. The method includes obtaining product data associated with the product assembly from a PDM database based on the unique identifier of the product assembly, and iteratively decomposing a product space including the product assembly in the CAD environment into a plurality of variable¬ sized partitions based on the product data. The method also includes selecting one or more variable-sized partitions for evaluating clearance between the components in the product assembly from the plurality of the variable-sized partitions, and evaluating clearance between the components in the selected variable-sized partitions.
G06F 30/13 - Architectural design, e.g. computer-aided architectural design [CAAD] related to design of buildings, bridges, landscapes, production plants or roads
G01B 7/14 - Measuring arrangements characterised by the use of electric or magnetic techniques for measuring distance or clearance between spaced objects or spaced apertures
G06F 9/50 - Allocation of resources, e.g. of the central processing unit [CPU]
The current disclosure describes a method of programming a software module associated with a firmware unit of a device. The method comprises obtaining a register transfer level pro- gram associated with the firmware unit, the register transfer level program comprising a plurality of register variables indicative of a plurality of registers in the firmware unit, defined within a first namespace of the register transfer level program; and linking the first namespace associated with the register transfer level program with a namespace as- sociated with a software module for referencing at least one of the register variable from the plurality of register vari- ables. The register transfer level program includes design level description of one or more operations associated with the firmware unit in a high-level programming language.
A computing system (100) may include an upgrade access engine (108) configured to access a database upgrade to perform for a production database (210). The computing system (100) may also include a database upgrade engine (110) configured to generate multiple clones of the production database (210), including a production clone (230) and a delta clone (240) with instance data (220) removed. The database upgrade engine 110 may perform the database upgrade on the production clone (230), track changes to the production database (210), and push the tracked changes (320) to the delta clone (240). After the database upgrade on the production clone completes, the database upgrade engine (110) may perform the database upgrade on the delta clone (240), push upgraded data (420) of the delta clone to the upgraded production clone (330), and set the upgraded production clone (330) as an upgraded version of the production database (210).
Surface editing is performed in typical computer-aided design (CAD) software products by using special tools to edit special surfaces, such as b-splines or subdivision surfaces. It is recognized herein that current approaches to editing surfaces are not generally applicable. For example, common CAD and surface modeling software products are tailored to a specific surface type or vendor specific format, or otherwise are not generally applicable to given analytical and non-analytical surfaces. In various embodiments described herein, subdivision surfaces can be generated to represent any surface. Further, surfaces can be manipulated using a control cage associated with the subdivision surface.
A method and system for providing a three-dimensional Computer-Aided Design (CAD) model of an object in a CAD environment is disclosed. A method includes receiving a request for a three-dimensional CAD model of a physical object. The request includes a two-dimensional image of the object. An image vector is generated from the two-dimensional image using a first trained machine learning algorithm. The method includes generating a three-dimensional point cloud model of the object based on the generated image vector using a second trained machine learning algorithm, and generating a three-dimensional CAD model of the object using the three-dimensional point cloud model of the object. The method also includes outputting the three-dimensional CAD model of the object on a graphical user interface.
G06F 30/27 - Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
G06N 3/04 - Architecture, e.g. interconnection topology
G06F 119/20 - Design reuse, reusability analysis or reusability optimisation
G06F 111/20 - Configuration CAD, e.g. designing by assembling or positioning modules selected from libraries of predesigned modules
76.
HYBRID SWITCHING ARCHITECTURE FOR SERDES COMMUNICATION CHANNELS IN RECONFIGURABLE HARDWARE MODELING CIRCUITS
Various aspects of the present disclosed technology relate to hybrid static and dynamic switching in a reconfigurable hardware modeling circuit for flexible and low latency communications. The reconfigurable hardware modeling circuit comprises serializer circuitry and deserializer circuitry for one or more communication ports, wherein the serializer circuitry has first sub-channels for receiving data to be sent out from the reconfigurable hardware modeling circuit, and the deserializer circuitry has second sub-channels for outputting data received by the reconfigurable hardware modeling circuit. The reconfigurable hardware modeling circuit also comprises static switching circuitry configurable to couple each of first zero or one or more sub-channels in the first sub-channels with one of signal sources comprising the second sub-channels and dynamic switching circuitry configurable to couple, in a time-division multiplexing mode, each of second zero or one or more sub-channels in the first sub-channels with more than one of the signal sources.
G06F 30/331 - Design verification, e.g. functional simulation or model checking using simulation with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
High Bandwidth IJTAG Through High Speed Parallel Bus A system in a circuit comprises: a first network (710) configurable to transmit data in parallel in the circuit, the first network (710) comprising circuit block interface devices, each of the circuit block interface devices being coupled to ports of one of circuit blocks in the circuit; a plurality of second networks (720, 725, 727), each of the plurality of second networks (720, 725, 727) configurable to transmit data in serial in one of the circuit blocks in the circuit; a third network (730) configurable to transmit data in serial in the circuit when being coupled to the plurality of second networks (720, 725, 727); and a plurality of network switching interface devices (740, 745, 747), each of the plurality of network switching interface devices (740, 745, 747) configurable to couple either the first network (710) or the third network (730) to one of the plurality of second networks (720, 725, 727) based on a control signal stored in the each of the plurality of interface devices (740, 745, 747).
G06F 13/37 - Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control using a physical-position-dependent priority, e.g. daisy chain, round robin or token passing
G06F 13/42 - Bus transfer protocol, e.g. handshake; Synchronisation
G01R 31/3185 - Reconfiguring for testing, e.g. LSSD, partitioning
H04L 12/24 - Arrangements for maintenance or administration
A method (700) may include the steps of accessing (702) an input data set (210) of hotspot locations on manufactured circuits of a circuit design. The hotspot locations may be confirmed through a high precision imaging process from a set of candidate locations of the circuit design determined by a low precision imaging process. The method (700) may further include correlating (704) the hotspot locations to layout data (240) for the circuit design, extracting (706) fragment feature vectors (250, 410, 510) for the hotspot locations from optical proximity correction (OPC) fragments of the layout data (240), processing (708) the fragment feature vectors (250, 410, 510), providing (710) the processed fragment feature vectors as a training set for training a machine-learning model (610), and applying (712) the machine-learning model (610) to down select a different set of candidate locations determined by the low precision imaging process.
G06F 30/398 - Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
G06F 30/27 - Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
79.
HYPERSPACE-BASED PROCESSING OF DATASETS FOR ELECTRONIC DESIGN AUTOMATION (EDA) APPLICATIONS
A computing system (100) may include a hyperspace generation engine (110) and a hyperspace processing engine (112). The hyperspace generation engine (110) may be configured to access a feature vector set (210, 420, 520), and feature vectors in the feature vector set may represent values for multiple parameters of data points in a dataset. The hyperspace generation engine (110) may further be configured to perform a principal component analysis on the feature vector set (210, 420, 520) and quantize the principal component space (230, 310) into a hyperspace (240, 340, 410, 510) comprised of hyperboxes. The hyperspace processing engine (112) may be configured to process the dataset according to a mapping of the feature vector set (210, 420, 520) into the hyperboxes of the hyperspace (240, 340, 410, 510).
A computing system (100) may include a hotspot processing engine (110) and a hotspot prediction engine (112). The hotspot processing engine (110) may be configured to access an input data set (210) of hotspot locations on manufactured circuits of a circuit design, correlate the hotspot locations to layout data (240) for the circuit design, and extract fragment feature vectors (250, 410, 510) for the hotspot locations. The hotspot processing engine (110) may further be configured to process the fragment feature vectors (250, 410, 510) such that hotspot fragment feature vectors (251, 411, 511) are a threshold percentage of the total number of feature vectors in the fragment feature vectors (250, 410, 510) and provide the processed fragment feature vectors as a training set for training a machine-learning model (610). The hotspot prediction engine (112) may be configured to apply the machine learning model (610) to characterize locations of the circuit design as a hotspot location or a non-hotspot location.
G06F 30/398 - Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
G06F 30/27 - Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
81.
METHOD AND SYSTEM FOR GENERATING A GEOMETRIC COMPONENT USING MACHINE LEARNING MODELS
A method and system for generating a geometric component in a computer-aided design (CAD) environment using machine learning models is disclosed. A computer-implemented method for generating a geometric component in a CAD environment includes determining a geometric operation to be performed on at least one geometric component in the CAD environment based on a CAD command selected by a user. The method also includes determining one or more candidate groups including one or more candidates in the geometric component suitable for performing the geometric operation using one or more trained machine learning models. The method includes identifying at least one candidate group from the one or more candidate groups on which the geometric operation is to be performed. The method also includes performing the geometric operation on the one or more candidates in the identified candidate group.
G06F 30/27 - Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
82.
HEAT-AWARE TOOLPATH GENERATION FOR 3D PRINTING OF PHYSICAL PARTS
A computing system (100) may include an access engine (108) and a heat-aware toolpath engine (110). The access engine (108) may be configured to access (702) a slice (230) of a 3-dimensional (3D) computer-aided design (CAD) object (210), wherein the 3D CAD object (210) represents a physical part and wherein the slice (230) represents a physical layer for 3D printing of the physical part. The heat-aware toolpath engine (110) may be configured to generate a layer toolpath (260) to control the 3D printing of the physical layer, including by partitioning the slice (230) into zones (251) and determining a zone order, based on a heat-aware criterion, for the layer toolpath (260) to traverse for the 3D printing of the physical layer. The heat-aware toolpath engine (110) may also be configured to provide the layer toolpath (260) to support the 3D printing of the physical part.
The invention provides a computer-implemented method of indexing a hierarchical data structure or product structure. For a product structure comprising a product and a plurality of items associated with the product, wherein each item shares a parent-child relationship with at least one other item or the product, the method comprising several steps. Firstly, a packed configuration-independent index of the product structure is generated by enumerating an unconfigured item-path from the product to an item for each item. Then, if one or more unconfigured item-paths are identical, only one of the identical unconfigured item-paths is maintained. The index may also be combined with an unconfigured item-path spatial-bounds index. Both product structure and spatial location queries can be filtered against the combined index.
A computing system (100) may include an access engine (108) and a toolpath reordering engine (110). The access engine (108) may be configured to access an original layer toolpath for slice of a 3D CAD object as well as a heat criticality measure (240, 340, 540) for the original layer toolpath. The heat criticality measure may specify a heat impact for different points on the multiple toolpath segments of the original layer toolpath for the 3D printing of the physical part using the original layer toolpath. The toolpath reordering engine (110) may be configured to reorder the multiple toolpath segments into a modified layer toolpath (250, 350, 550), and the modified layer toolpath (250, 350, 550) may have a heat criticality measure with a lesser heat impact on the physical part than the heat criticality measure (240, 340, 540) for the original layer toolpath.
G06F 30/27 - Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
B22F 10/85 - Data acquisition or data processing for controlling or regulating additive manufacturing processes
B29C 64/393 - Data acquisition or data processing for additive manufacturing for controlling or regulating additive manufacturing processes
B33Y 50/02 - Data acquisition or data processing for additive manufacturing for controlling or regulating additive manufacturing processes
B23K 9/04 - Welding for other purposes than joining, e.g. built-up welding
A method and system for trimming intersecting bodies of a geometric model in a computer-aided design environment is disclosed. In one embodiment, a method includes determining a plurality of bodies of the geometric model intersecting with each other. The method includes computing volume of one or more intersecting bodies in the geometric model to be trimmed from the geometric model. Also, the method includes determining a trim offset value for at least one intersecting body in the geometric model, and recomputing the volume of the at least one intersecting body in the geometric model which is to be trimmed from the geometric model based on the trim offset value. Moreover, the method includes generating a modified geometric model by performing a trim operation on the volume of the one or more intersecting bodies of the geometric model.
G06F 30/17 - Mechanical parametric or variational design
G06F 30/27 - Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
B21D 5/00 - Bending sheet metal along straight lines, e.g. to form simple curves
A method of monitoring messages from a sensor using an integrated circuit, the messages comprising data measured by that sensor, the method comprising: reading a first message from interconnect circuitry of the integrated circuit, the interconnect circuitry connecting the sensor to one or more core devices configured to process the message; calculating a first hash value for the first message; comparing the first hash value to one or more prior hash values stored in a hash store, each prior hash value corresponding to a message that was read from the interconnect circuitry prior to the first message; and performing a corrective action if the difference between the first hash value and at least one of the prior hash values stored in the hash store is below a predetermined threshold.
G08C 25/00 - Arrangements for preventing or correcting errors; Monitoring arrangements
H04Q 9/00 - Arrangements in telecontrol or telemetry systems for selectively calling a substation from a main station, in which substation desired apparatus is selected for applying a control signal thereto or for obtaining measured values therefrom
G06F 11/07 - Responding to the occurrence of a fault, e.g. fault tolerance
87.
COMBINED SERVER REQUESTS FOR COMPUTER-AIDED DESIGN (CAD) APPLICATIONS
A computing system may include a combined request generation engine (108) and a combined request communication engine (110). The combined request generation engine (108) may be configured to identify a computer-aided design (CAD) operation to be performed through a CAD application client, determine a first server request and a second server request to transmit to a server computing system (204) in order to perform the CAD operation, and combine the first server request and second server request into a combined server request (220, 310, 510). The combined request communication engine (110) may be configured to transmit the combined server request (220, 310, 510), with the first and second server requests combined together, to the server computing system (204) to perform the CAD operation instead of sending separate server requests for the first server request and the second server request.
This application discloses a computing system implementing a yield enhancer tool to extract characteristics of cells from a physical layout design for an integrated circuit, determine locations of vacant regions in the physical layout design, apply electrical design rules for manufacture of the integrated circuit to the extracted characteristics in order to identify cells in the physical layout design that would violate the electrical design rules. The computing system can select filler cells for the vacant regions based, at least in part, on extracted characteristics of the cells abutting the vacant regions and the electrical design rules, and insert the selected filler cells in the vacant regions of the physical design layout. The computing system can perform a design rule check operation, which applies the electrical design rules to the physical design layout having been inserted with the selected filler cells.
A memory-testing circuit configured to perform a test of reference bits in a memory. In a read operation, outputs of data bit columns are compared with one or more reference bit columns. The memory-testing circuit comprises: a test controller and association adjustment circuitry configurable by the test controller to associate another one or more reference bit columns or one or more data bit columns with the data bit columns in the read operation. The test controller can determine whether the original one or more reference bit columns have a defect based on results from the two different association.
System and method for differentiable networks trainable to learn an optimized query of a 3D model database used for object recognition includes training a first differentiable network configured as a differentiable renderer by generating 2D images from 3D models of a first object of a dissimilar second object while optimizing rendering parameters for producing 2D images by gradient descent of a first triple loss function. Visual variation among the images is maximized. A second differentiable network configured as a convolutional neural network defined by a regression function is trained by generating searchable feature vectors of the 2D images. The feature vectors are determined using optimized neural network parameters determined by gradient descent of a second triple loss function to achieve high correlation to an input image of the first object and low correlation to images of the second object.
A computing system (100) may include a metamaterial representation engine (110) configured to represent a metamaterial of a three-dimensional (3D) object (220) as program code (210). The metamaterial may define an internal geometry of the 3D object (220) and may be configured to be physically constructed via additive manufacturing. Representation of the metamaterial as program code (210) may include assigning a value of a code parameter of the metamaterial as a probability distribution (240). The computing system (100) may also include a metamaterial analysis engine (112) configured to analyze the metamaterial through the probability distribution (240) assigned for the value of the code parameter of the program code (210).
A computing system may include a scene access engine and a scene simplification engine. The scene access engine may be configured to access a 3-dimensional (3D) scene comprised of multiple scene objects, and each scene object may be represented through a tessellated 3D model comprised of multiple mesh faces. The scene simplification engine may be configured to generate a simplified 3D scene from the 3D scene, including by classifying the multiple scene objects into different object classes, simplifying the multiple scene objects based on the object classes to obtain simplified scene objects, and forming the simplified 3D scene by replacing the multiple scene objects in the 3D scene with the simplified scene objects. The scene simplification may also provide the simplified 3D scene for processing instead of the 3D scene.
This application discloses a memory built-in self-test system to prompt a memory device to sense values of stored data using a reference trim during memory read operations. The memory built-in self-test system can automatically set the reference trim for the memory device. The memory built-in self-test system includes a memory built-in self-test controller to prompt the memory device to perform the memory read operations with different test values for the reference trim. The memory built-in self-test system also includes a trim feedback circuit to determine when the memory device fails to correctly sense the values of the stored data using the test values for the reference trim, and set the reference trim for the memory device based, at least in part, on the failures of the memory device to correctly sense the stored data.
A computer-implemented method for determining a cut pattern (1) of a lathe (2) which is numerically controlled by a control device (6) and which includes a tool (3) with a cutter (4) acting on a workpiece (5), the workpiece (5) having a start contour (7) and a target contour (8) to be achieved by cutting the workpiece (5) according to the cut pattern (1), the method including: determining a path of a n-th layer of the cut pattern (6), the n-th layer including: for n greater than or equal to 2: an infeed path which is linear and/or parallel to the target contour (8) starting at point E_n-1 and ending at point S_n; a circular infeed path starting tangent to the target contour (8) at point S_n with a radius rS_n and ending at point IS_n; an intermediate path which is linear and/or parallel to the target contour (8) starting at point IS_n and ending at point IE_n; a circular outfeed path starting at point IE_n and ending tangent to the target contour (8) at point E_n with a radius rE_n; for n greater than or equal to 2: a smoothing path which is linear and/or parallel to the target contour (8) starting at point E_n, including point S_n-1, and ending at point E_n.
G05B 19/4093 - Numerical control (NC), i.e. automatically operating machines, in particular machine tools, e.g. in a manufacturing environment, so as to execute positioning, movement or co-ordinated operations by means of programme data in numerical form characterised by part programming, e.g. entry of geometrical information as taken from a technical drawing, combining this with machining and material information to obtain control information, named part programme, for the NC machine
95.
METHOD AND APPARATUS FOR DESIGNING AND MANUFACTURING A COMPONENT IN A COMPUTER-AIDED DESIGN AND MANUFACTURING ENVIRONMENT
A method and apparatus for designing and manufacturing a component in a computer-aided design and manufacturing environment is disclosed. A method includes obtaining a geometric model of a component from a geometric model database, and determining at least one orientation parameter value associated with the geometric model of the component. The at least one orientation parameter value is associated with an orientation parameter that defines orientation of the component during additive manufacturing of the component. The method includes performing volumetric analysis of the component based on the at least one orientation parameter value associated with the component using the geometric model of the component. The method also includes computing one or more overheating areas in the component corresponding to the at least one orientation parameter value based on the volumetric analysis of the geometric model of the component, and outputting a multi-dimensional visual representation of the geometric model of the component Indicating one or more overheating areas in the component.
A memory device can sense stored data during memory read operations using a reference trim, and a memory built-in self-test system can perform a multiple step process to set the reference trim for the memory device. The memory built-in self-test system can set a reference trim range that corresponds to a range of available reference trim values and then select one of the reference trim values in the reference trim range as the reference trim for the memory device. The memory built-in self-test system can set the reference trim range by prompting performance of the memory read operations using different positions of the reference trim range relative to read characteristics of the memory device and set a position for the reference trim range relative to the read characteristics of the memory device based on failures of the memory device to correctly sense the stored data during the memory read operations.
G11C 29/02 - Detection or location of defective auxiliary circuits, e.g. defective refresh counters
G11C 29/12 - Built-in arrangements for testing, e.g. built-in self testing [BIST]
G11C 29/44 - Indication or identification of errors, e.g. for repair
G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
A computing system may include an instance identification engine configured to determine a selected subset of pattern instances of a programmatic pattern used to represent a geometry of a computer-aided design (CAD) object, including by identifying a CAD operation to perform on the CAD object; determining a sampled point set in the CAD object applicable to the CAD operation; providing the sampled point set as an input to an inversion machine-learning (ML) model trained to output a given pattern instance of the programmatic pattern for an input point of the CAD object; and determining, as the selected subset, an output set of pattern instances provided by the inversion ML model for the sampled point set. The system may also include an object incarnation engine configured to incarnate a geometry of the selected subset of pattern instances to perform the CAD operation on the CAD object.
A method of identifying a cause of an anomalous feature measured from system circuitry on an integrated circuit (IC) chip, the IC chip comprising the system circuitry and monitoring circuitry for monitoring the system circuitry by measuring features of the system circuitry in each window of a series of windows, the method comprising: (i) from a set of windows prior to the anomalous window comprising the anomalous feature, identifying a candidate window set in which to search for the cause of the anomalous feature; (ii) for each of the measured features of the system circuitry: (a) calculating a first feature probability distribution of that measured feature for the candidate window set; (b) calculating a second feature probability distribution of that measured feature for window(s) not in the candidate window set; (c) comparing the first and second feature probability distributions; and (d) identifying that measured feature in the timeframe of the candidate window set as a cause of the anomalous feature if the first and second feature probability distributions differ by more than a threshold value; (iii) iterating steps (i) and (ii) for further candidate window sets from the set of windows prior to the anomalous window; and (iv) outputting a signal indicating those measured feature(s) of step (ii)(d) identified as a cause of the anomalous feature.
A computing system may include an object representation engine and an object incarnation engine. The object representation engine may be configured to define a computer-aided design (CAD) object in a CAD model as a combination of an object boundary comprised of bounding faces that encapsulate the CAD object and a microstructure that defines an internal geometry of the CAD object in a procedural representation. The procedural representation may be a representation of the internal geometry of the CAD object in a non-incarnated form. The object incarnation engine may be configured to incarnate, via the procedural representation of the microstructure, the internal geometry of the CAD object into a geometric representation to perform a CAD operation on the CAD object.
An integrated circuit (1C) chip includes system circuitry having system memory, and a master processor and a checker processor configured to operate in lockstep; and monitoring circuitry comprising an internal lockstep monitor, a master tracer and a checker tracer. The internal lockstep monitor is configured to: observe states of internal signals of the master processor and the checker processor, compare corresponding observed states of the master processor and the checker processor, and if the corresponding observed states differ: trigger the master tracer to output stored master trace data recorded from the output of the master processor, and trigger the checker tracer to output stored checker trace data recorded from the output of the checker processor.
patents
