A circuit comprises scan chains comprising scan cells and one or more observation scan chains. The scan chains comprise scan cells. The one or more observation scan chains comprises observation scan cells. Testing the circuit comprises a scan-capture phase and an observation scan phase. During the scan-capture phase, both the scan cells and the observation scan cells operate in a shift mode and a capture mode alternately. During the observation scan phase, the scan cells operating in the shift mode and the observation scan cells operating in a shift-observation mode.
The invention provides an apparatus for monitoring an operability of a production system, the apparatus comprising: - an input unit configured to input production-related data of the production system, - a mapping engine configured to map the production-related data to instance data of a first knowledge graph according to a given mapping definition, - a first validation unit configured to validate a consistency and/or an integrity of the instance data by means of declarative constraints and to output a first validation result, - a simulator configured to generate a computer-implemented material flow simulation model of the production system based on the instance data and depending on the first validation result, - a generator configured to generate simulated production logs using the material flow simulation model, - a second validation unit configured to validate the simulated production logs against measured production logs of the production system and to output a second validation result, and - an output unit configured to output the second validation result for monitoring the operability of the production system.
G05B 17/02 - Systems involving the use of models or simulators of said systems electric
G05B 19/418 - Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control (DNC), flexible manufacturing systems (FMS), integrated manufacturing systems (IMS), computer integrated manufacturing (CIM)
An integrated circuit including at least two interconnected sub-blocks in a System-on-Chip (SoC) arrangement and a method for communicating data in the integrated circuit are provided. The method includes transmitting a first signal asserting that a first sub-block is ready to transmit data to a second sub-block, receiving a second signal asserting that the second sub-block is ready to receive data from the first sub-block and transmitting data including one or more contiguous messages via a third signal from the first sub-block to the second sub-block. The first signal includes information that enables the second sub-block to determine a position of the end of the last message in the contiguous messages.
A method for an integrated circuit including a plurality of interconnected sub-blocks in a System-on-Chip (SoC) arrangement is provided. The method includes transmitting a message from a first sub-block to at least one sub-block of the plurality of interconnected sub-blocks, in response to an event on the integrated circuit and transmitting a signal from the first sub-block to the at least one sub-block of the plurality of interconnected sub-blocks. The signal includes information identifying a class of the event based on a classification of events associated to the integrated circuit into one or more classes.
A computing system can parse a schematic diagram illustrating an electronic system to identify design blocks and wire lines coupled to the design blocks in the schematic diagram. The computing system, implementing at least one supervised machine-learning classification algorithm, can classify the design blocks and the wire lines. The classification of the design blocks can correspond to one or more symbols representing components of the electronic system. The classification of the wire lines can correspond to one or more links representing connectivity for at least one of the components of the electronic system. The computing system can generate a system design describing the electronic system based, at least in part, on the symbols representing the components of the electronic system classified to the design blocks and the links representing connectivity for at least one of the components of the electronic system classified to the wire lines.
G06F 30/27 - Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
G06F 113/16 - Cables, cable trees or wire harnesses
8.
USER CREDENTIAL PARAMETER SPACE PARTITIONING IN A RULE BASED ACCESS CONTROL SYSTEM
This application discloses a computing system to process rules defining access privileges for product data stored in a product data management system, which identifies accessor parameters capable of satisfying the rules for accessing the product data. The computing system can identify session parameters corresponding to user characteristics in an organization for a plurality of users, and correlate the accessor parameters for the product data to the session parameters for the users, which can partition a parameter space of the session parameters for the plurality of the users. The computing system can selectively evaluate the access privileges to the product data for at least one of the users by selecting one of the users in each partition, evaluating the access privileges to the product data using the session parameters of the selected users, and skipping evaluation of the access privileges to the product data using the session parameters of non-selected users.
Computer-implemented system and method are provided for generating an additive manufacturing (AM) build program used to build an object having a manifold boundary body. A manufacturing definition module merges build information and AM machine schema information for a manufacturing definition. The build information includes specification of region-based build parameters and the machine schema information includes AM machine specific parameters related to material build by layers. Slice generation module performs a direct slicing algorithm of a 3D CAD model defining the geometry for the object, wherein slices of the model are defined according to layer thickness along a slicing direction. A region based recipe module is configured to generate annotated slices, wherein each slice is annotated with information based on the manufacturing definition. The annotated slices are sent to an edge computing device controlling the AM machine to be converted to a final build file with tool path and process parameters.
A computing system (100) may include a database identification engine (108) configured to identify databases (111, 112) of different systems (121, 122). The computing system (100) may also include a link discovery engine (110) configured to construct a supergraph (220) that represents the data elements stored in the databases (111, 112), including by constructing graphs (211, 212) for tables in the databases (111, 112) and merging the graphs (211, 212) into the supergraph (220), including by performing a cell fusion to merge multiple nodes (311, 312) from the graphs (211, 212) with an identical data element value into a fused node (320) in the supergraph (220). The link discovery engine (110) also be configured to process the supergraph (220) according to cross-domain linking criteria to determine cross-domain links (410) for data stored in the databases (111, 112) of the different systems (121, 122).
An integrated circuit and a method of monitoring behaviour in an integrated circuit are provided. The integrated circuit includes sub-blocks in a system-on-chip (SoC) arrangement, interconnect circuitry configured to transport transactions between the sub-blocks and a monitor configured to observe the behaviour of the integrated circuit. The monitor includes a filter configured to filter data observed by the monitor, at least two registers communicatively coupled to the filter and including a configuration profile for the filter, and a profile selector configured to select one of the registers and implement the configuration profile of the selected register as the active configuration of the filter.
A computing system (100) may include a toolpath access engine (108) configured to access a robotic toolpath (121) for a robot, a target value (122) for a robotic degree of freedom of the robot, and a resolution range (123). The computing system (100) may also include a toolpath modification engine (110) configured to determine violation locations (220) in the robotic toolpath (121) based on the target value (122), determine safe values (241, 242, 243) for the robotic degree of freedom within the resolution range (123) that do not cause a violation at the violation locations (220) in the robotic toolpath (121), and modify the robotic toolpath (121) by setting the robotic degree of freedom at each of the violation locations (220) in the robotic toolpath (121) to a selected safe value in the resolution range (123).
A computing system can parse a physical verification file to identify physical verification operations to perform on a layout design describing an integrated circuit. The computing system can divide input data corresponding to the layout design into multiple non-uniform sized data tiles, correlate the data tiles to processing tasks for processing cores of the computing system to process in parallel, and assign the processing tasks to the processing cores based on sizes of the data tiles. The computing system can assign, to the processing cores, the processing tasks correlated to the data tiles having larger relative sizes before assigning the processing tasks to the processing cores having smaller relative sizes. The computing system can assign the processing tasks independent of contents of the data tiles. The processing cores can process the processing tasks in parallel to perform the physical verification operations described in the physical verification file.
G06F 30/331 - Design verification, e.g. functional simulation or model checking using simulation with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
G06F 119/12 - Timing analysis or timing optimisation
15.
DIAGNOSTICS-BASED MATERIALIZATION OF ELEMENTS IN KNOWLEDGE GRAPHS
A computing system (100) may include an access engine (108) configured to access a diagnostic report (230) for a knowledge graph (210) and a constraint set (212) of the knowledge graph (210). The computing system (100) may also include a materializer engine (110) configured to determine, from the diagnostic report (230), a violation in the knowledge graph (210) caused by a failure to satisfy a given constraint in the constraint set (212) of the knowledge graph (210), compute a gap (310) in the knowledge graph (210) that causes the violation, and materialize an element (240) in the knowledge graph (210) to fill the gap (310) by satisfying the given constraint in the constraint set (212) of the knowledge graph (210).
A computing system (100) may include a surface identification engine (108) configured to identify a surface of a 3D computer-aided design (CAD) object (202, 302) and a toolpath generation engine (110) configured to generate a toolpath to perform an operation on the surface (210, 310, 410). The toolpath generation engine (110) may generate the toolpath by constructing a path based on a medial axis of the surface, a convex hull of the surface, or a medial axis of a convex hull of the surface, performing a curve-smoothing process on the path, adjusting the path to account for a collision point detected in the path, and outputting the path as the generated toolpath. The toolpath generation engine (110) may further be configured to provide the toolpath for performing the operation on a physical surface modeled by the 3D CAD object (202, 302).
G05B 19/19 - Numerical control (NC), i.e. automatically operating machines, in particular machine tools, e.g. in a manufacturing environment, so as to execute positioning, movement or co-ordinated operations by means of programme data in numerical form characterised by positioning or contouring control systems, e.g. to control position from one programmed point to another or to control movement along a programmed continuous path
G05B 19/4093 - Numerical control (NC), i.e. automatically operating machines, in particular machine tools, e.g. in a manufacturing environment, so as to execute positioning, movement or co-ordinated operations by means of programme data in numerical form characterised by part programming, e.g. entry of geometrical information as taken from a technical drawing, combining this with machining and material information to obtain control information, named part programme, for the NC machine
G05B 19/4097 - Numerical control (NC), i.e. automatically operating machines, in particular machine tools, e.g. in a manufacturing environment, so as to execute positioning, movement or co-ordinated operations by means of programme data in numerical form characterised by using design data to control NC machines, e.g. CAD/CAM
Hashing circuitry is configured to mimic a hashing function that can transform a random number into a hash value. The hashing circuitry comprises combinational circuitry with its inputs receiving bits of the random number and a ring generator configured to be initialized by a secret key, to be injected with bits from outputs of the combinational circuitry, and to output the hash value after a predefined number of clock cycles. The combinational circuitry comprises logic gates configured to serve as nonlinear Boolean operators. The random number may be generated by a random number generator comprising a ring generator and one or more inverter-based ring oscillators. The hash value may be employed by retrieving circuitry to retrieve one or more configuration masks from a response signal generated by a computing device based on the random number.
H04L 9/06 - Arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for blockwise coding, e.g. D.E.S. systems
G09C 1/00 - Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system
G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
A circuit comprises: a random number generator configured to generate a random number; hashing circuitry configured to mimic a hashing function that can transform the random number into a hash value; and retrieving circuitry configured to use the hash value to retrieve one or more configuration masks from a response signal received by the circuit. The response signal is generated based on the random number by a computing device. The generation of the response signal comprises: generating the hash value for the random number, and combining the hash value with the one or more configuration masks. The random number generator may comprise a ring generator and one or more inverter-based ring oscillators configured to inject bits into the ring generator at a plurality of location.
H04L 9/32 - Arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system
G06F 7/58 - Random or pseudo-random number generators
19.
RING-GENERATOR-BASED TRUE RANDOM NUMBER GENERATOR FOR HARDWARE ROOT OF TRUST
A random number generator comprises a ring generator and one or more inverter-based ring oscillators. The one or more inverter-based ring oscillators is configured to inject bits into the ring generator at a plurality of location. If there is more than one inverter-based ring oscillators, the inverter-based ring oscillators may have different numbers of inverting elements and may inject bits into the ring generator at different locations. At least one of the one or more inverterbased ring oscillators may be configured to inject bits into the ring generator at different locations from outputs of some or all its inverting elements. The random number generator may further comprise blocking circuitry configured to convert, based on a blocking signal, the ring generator into a circular shift register by blocking both the injection from the plurality of inverter-based ring oscillators and internal feedbacks in the ring generator.
An electronic device configured for retail display includes an antenna, a memory in which security monitoring instructions are stored, and a processor configured to execute the security monitoring instructions to monitor a profile of wireless beacon devices detected via the antenna. The processor is further configured via the execution of the security monitoring instructions to, upon detection of a profile of wireless beacon devices that exceeds a threshold, initiate a security measure for the electronic device
A method and data processing apparatus for performing anomaly detection in a device are disclosed. The method includes receiving time series data from a monitoring system in the device over a time period, generating a vector of data values representing characteristics of the time series data over the time period, and executing a predictive model based on an input including the vector to identify anomalous device behavior
This application discloses a design verification system (310) to extract timing information associated with a library design cell file and statically analyse the extracted timing information to identify at least one clock signal (500) by identifying one or more candidate clock signals in the extracted timing information and traversing timing checks in the extracted timing information for each of the candidate clock signals to determine at least one of the candidate clock signals corresponds to a clock signal. The design verification system can correlate circuitry described in the library design cell file to a portion of a circuit design describing an electronic system and modify a compiled version of the circuit design (314) based on the identified clock signal for the circuitry and the correlation of the circuitry to the portion of the circuit design. The design verification system can simulate the electronic system using the modified version of the compiled circuit design (316).
For an improved engineering of a physical system (150), especially for an improved traceability of the engineering information (120) of the physical system (150), a computer- implemented method is suggested comprising: • providing a set of first engineering artifacts (122) and a set of second engineering artifacts (124) of engineering information (120) of the physical system (150); • determining a first annotation tree (126) comprising first nodes (128) representing the set of first engineering artifacts (122) and determining a second annotation tree (130) comprising second nodes (132) representing the set of second engineering artifacts (124); • providing at least one ontology (134) relating to the engineering information (120); • determining a respective similarity value (136) of the respective first node (128) and the respective second node (132) using the respective ontology (134), wherein the respective similarity value (136) depends on the respective distance (138) between the respective first node (128) and the respective second node (132) in the respective ontology (134); • determining at least one of the first nodes (128) which is related to at least one of the second nodes (132) using the respective similarity value (136); and • generating a respective connector (140) linking the respective first engineering artifact (122) corresponding to the respective first node (128) with the respective second engineering artifact (124) corresponding to the related, respective second node (132).
A method for determining timing accuracy of one or more radio data packets (10), the method comprising the steps of: gener¬ ating stimulus data (20), the stimulus data (20) comprising the radio data packets (10) and a reference time (T_Ra) for transmission of the radio data packets (10) over the air, storing the stimulus data (20) on a test device (1), replay¬ ing the stimulus data (20), by the test device (1), in order to determine the timing accuracy of the transmission of the one or more radio data packets (10) by a device under test (2,3).
A system on a chip (SoC) (10) is provided. The SoC (10) includes an integrated circuit (12), an embedded analytics monitor (14) configured to generate analytics data by monitoring one or more interactions within the integrated circuit (12), and a diagnostics module (16) including a machine learning algorithm trained to detect an anomaly in the analytics data indicative of a fault condition of the integrated circuit (12).
A computer-implemented method of executing a method code, written in C#, from another C language is provided. The computer-implemented method includes identifying an attribution written in C# script, and identifying a method corresponding to the attribute. The method is written in the C# script. The computer-implemented method includes calling the C# method from C. In this way, legacy source code written in another language such as C or C++ may be modified by a user in C#.
A system on a chip (SoC) is provided. The SoC includes an integrated circuit, an embedded analytics monitor configured to generate analytics data by monitoring one or more interactions within the integrated circuit, and a diagnostics module including a machine learning algorithm trained to detect an anomaly in the analytics data indicative of a fault condition of the integrated circuit.
A system on a chip (SoC) (10) is provided. The SoC (10) includes an integrated circuit (12), an embedded analytics monitor (14) configured to generate analytics data by monitoring one or more interactions within the integrated circuit (12), and a diagnostics module (16) including a machine learning algorithm trained to detect an anomaly in the analytics data indicative of a fault condition of the integrated circuit (12).
A method comprising: applying pre-determined DC voltage values to analog inputs of an analog or mixed signal circuit design (710); applying a plurality of sets of bit values generated for scan-based structural testing of circuits manufactured based on the circuit design, one set during each of a plurality of consecutive time intervals, to inputs of one or more node-connecting devices coupled to or to be coupled to one or more selected internal nodes of the circuit design, to one or more selected digital inputs of the circuit design, or both (720); and performing a simulation of the circuit design to determine, for each set of bit values, expected test response bit values at outputs of one or more threshold-comparing convertors and at selected digital signal nodes if the circuit design has the selected digital signal nodes (730). These operations may be repeated on the circuit design with defects being injected.
A test circuit configured to test a circuit being at least partially analog, comprising: one or more scan chains and one or more threshold-comparing convertors. Each of the one or more thresholdcomparing convertors, comprising one or more threshold-comparing sub-convertors for one or more preset thresholds, is coupled to a selected node of the circuit, and wherein each of the one or more threshold-comparing sub-convertors is configured to output, based on comparing a voltage value at the selected node with one of the one or more preset thresholds, a bit value of the test response to a scan cell of the one or more scan chains. The test circuit may further comprise one or more node-connecting devices with inputs coupled to the one or more scan chains and with outputs coupled to one or more selected internal nodes of the circuit.
A computing system (100,700) may include an eject direction determination engine (110) configured to determine an ejection for an injection mold design, including by determining a set of candidate eject directions (210) for the injection mold design, including a bounding box candidate eject direction (231,232,233) determined based on a minimum bounding box (230) of an object (220) representative of a product to be manufactured through the injection mold design and selecting the eject direction (520) for the injection mold design from the set of candidate eject directions (210) based on eject direction determination criteria (510,606). The computing system (100,700) may also include an eject direction application engine (112) configured to set the determined eject direction (520) for the injection mold design so that physical mold pieces constructed from the injection mold design are configured to separate from one another in the determined eject direction during an injection mold production process to manufacture the product (608).
G06F 17/00 - Digital computing or data processing equipment or methods, specially adapted for specific functions
B29C 33/38 - SHAPING OR JOINING OF PLASTICS; SHAPING OF MATERIAL IN A PLASTIC STATE, NOT OTHERWISE PROVIDED FOR; AFTER-TREATMENT OF THE SHAPED PRODUCTS, e.g. REPAIRING - Details thereof or accessories therefor characterised by the material or the manufacturing process
A method for determining timing accuracy of one or more radio data packets (10), the method comprising the steps of: recording, by a test device (1), a reference time (TRa), for one or more radio data packets (10) received at an antenna interface (Ra) of a first radio equipment (2), generating, by the test device (1), a time window based on the reference time, e.g., based on a predetermined time delay of the first radio equipment (2) and/or fronthaul transmis¬ sion, and transmitting, by the first radio equipment (2), the one or more data packets (10) to a second radio equipment (3), recording, by the test device (1), an arrival time at which the one or more radio data packets (10) are received by the second radio equipment (3), and comparing, by the test device ( 1 ), the arrival time with the time window in order to determine the timing accuracy of the one or more radio data packets (10).
This application discloses a computing system implementing a reliability verification tool to identify a portion of a layout design describing an integrated circuit includes a victim transistor having a gate connected to an aggressor transistor. The reliability verification tool can extract a resistance network for connections between the victim transistor and the aggressor transistor, and simulate the resistive network to determine connectivity between the wells of the victim transistor and the aggressor transistor occurs prior to the victim transistor having a gate connected to an aggressor transistor.
G06F 21/71 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
A computing system may include an image access engine (108) configured to access a panoramic point cloud image (210, 220) of a physical environment. The computing system may also include an environment location-aware text engine (110) configured to transform the panoramic point cloud image (210, 220) into an alternate representation (230) that reduces distortion in the panoramic point cloud image (210, 220) and perform an optical character recognition (OCR) process on the alternate representation (230) to determine text in the panoramic point cloud image (210, 220). The environment location-aware text engine (110) may further be configured to construct text labels to track the text determined in the panoramic point cloud image (210, 220) and support text searches for the physical environment through the text labels.
G06V 10/24 - Aligning, centring, orientation detection or correction of the image
G06V 30/146 - Aligning or centering of the image pick-up or image-field
G06F 16/583 - Retrieval characterised by using metadata, e.g. metadata not derived from the content or metadata generated manually using metadata automatically derived from the content
35.
MANAGING MACHINING INFORMATION, ESP. DETERMINING STEP FEATURES FROM A SAMPLE MACHINING PROCESS, METHOD, COMPUTER SYSTEM AND MACHINE TOOL
Managing machining information, esp. determining step features from a sample machining process, method, computer system and machine tool. For an improved management of machining information, esp. for a facilitated determination of step features (126) from a sample machining process, a computer-implemented method is suggested comprising: - providing a sample machining process (120s) for machining a sample workpiece (140s) from a sample blank (148s), the sample machining process (120s) comprising at least two consecutive sample machining steps (120s-i) performed by the respective tool (142-i) starting with a respective sample start part (Iwf-i) and ending with a respective sample end part (mwf-i), wherein the respective sample end part (mwf-i) of the respective sample machining step (120s-i) is the respective sample start part (lwf-i+1) of the respective subsequent sample machining step (120s-i+1); - determining a respective step tool volume (122-i) corresponding to a movement of the respective tool (142-i) during the respective sample machining step (120s-i); - determining a respective step volume (124-i) corresponding to the respective sample start part (Iwf-i) of the respective sample machining step (120s-i) changed by the respective step tool volume (122-i); - determining at least one respective step feature (126) corresponding to the respective step volume (124-i); and - storing the respective step feature (126) in a machining information database (128).
G05B 19/4093 - Numerical control (NC), i.e. automatically operating machines, in particular machine tools, e.g. in a manufacturing environment, so as to execute positioning, movement or co-ordinated operations by means of programme data in numerical form characterised by part programming, e.g. entry of geometrical information as taken from a technical drawing, combining this with machining and material information to obtain control information, named part programme, for the NC machine
G05B 19/418 - Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control (DNC), flexible manufacturing systems (FMS), integrated manufacturing systems (IMS), computer integrated manufacturing (CIM)
36.
MANAGING A POSTPROCESSOR, ESP. DETERMINING A NEW POSTPROCESSOR, FOR MACHINING WITH A MACHINE TOOL METHOD, COMPUTER SYSTEM AND MACHINE TOOL
G05B 19/408 - Numerical control (NC), i.e. automatically operating machines, in particular machine tools, e.g. in a manufacturing environment, so as to execute positioning, movement or co-ordinated operations by means of programme data in numerical form characterised by data handling or data format, e.g. reading, buffering or conversion of data
G05B 19/4155 - Numerical control (NC), i.e. automatically operating machines, in particular machine tools, e.g. in a manufacturing environment, so as to execute positioning, movement or co-ordinated operations by means of programme data in numerical form characterised by programme execution, i.e. part programme or machine function execution, e.g. selection of a programme
G05B 19/4097 - Numerical control (NC), i.e. automatically operating machines, in particular machine tools, e.g. in a manufacturing environment, so as to execute positioning, movement or co-ordinated operations by means of programme data in numerical form characterised by using design data to control NC machines, e.g. CAD/CAM
A memory-testing circuit in a circuit comprises: a test controller; a memory data source selection device configured to select input data for a write port of the memory from test data outputted from the test controller and data from an output of the memory; and a memory address source selection device configured to select an address for an address port of the memory from an address outputted from the test controller and one of one or more preset addresses of the memory. The one or more preset addresses correspond to one or more preserved locations of the memory configured to temporarily store data for one or more locations of the memory to be tested.
A computer-implemented method of editing, at a local client device, an engineering design (CAD model), hosted on a remote server is described. The local client device and the remote server communicate over a communications network and are remote from each other. The remote server configures an operation within a CAD model based on user input during an edit of the CAD model involving a drag. This results in a subset of the CAD model and the solving instructions required to perform the user update being generated and sent as a data package comprising the subset of the CAD model and the solving instructions to the local client device. The CAD model and any associated algorithms stored on the remote server are not communicated to the local client device.
G06F 30/12 - Geometric CAD characterised by design entry means specially adapted for CAD, e.g. graphical user interfaces [GUI] specially adapted for CAD
G06F 30/17 - Mechanical parametric or variational design
G06F 111/02 - CAD in a network environment, e.g. collaborative CAD or distributed simulation
A computer-implemented method of modelling engineering design components in a Computer-Aided Design (CAD) system is disclosed, wherein an engineering design component includes a feature having at least three occurrences of a shape element arranged in a regular pattern is described. The method is split into three stages: definition of a core set of behavioral characteristics; definition of an optional set of behavioral characteristics; and a hierarchical implementation of the optional characteristics by solving optional constraints after constraints corresponding to the core behavioral characteristics have been solved.
G06F 30/12 - Geometric CAD characterised by design entry means specially adapted for CAD, e.g. graphical user interfaces [GUI] specially adapted for CAD
An address-skipping trim search performed by a memory built-in self-test system comprises: perform memory read operations on one memory bank to determine whether it fails to correctly sense values of stored data based on a reference trim value for a previous memory bank; if the present memory bank fails, perform memory read operations to search for a new reference trim value for the present memory bank; or otherwise, treat the present reference trim value as the one for the present memory bank and proceed to testing a next memory bank. The range for searching for the new reference trim value can be limited by the present reference trim value.
G11C 29/02 - Detection or location of defective auxiliary circuits, e.g. defective refresh counters
G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
41.
METHOD OF RENDERING A TWO-DIMENSIONAL IMAGE TO A DESIGNER
A computer-implemented method of rendering, to a designer, a two-dimensional image of an assembly of part instances in a three-dimensional assembly space within a computer-aided design (CAD) system utilizing double precision to describe part assemblies is described. Such assemblies are considered to be distant from a nominal observer. A viewport on a two-dimensional image plane is defined, and a combined transform is defined in quadruple precision to enable the generation of clipping lines and/or clipping points. The clipping lines and clipping points clipping the faces and edges of the part instance in the assembly to the portion of the assembly that lies within the viewport.
The present invention discloses a method and a system for determining an assembling risk for an electronic component to be mounted to a printed circuit board, said method comprising the steps of: providing a component library comprising a number of electronic components and its specific component identifier wherein said component identifier comprises an identifier string of letters and numbers thereby providing an information for a number of physical attributes of the electronic component; providing an evaluation scheme for each of the number of physical attributes; selecting an electronic component from the component library and evaluating each of the number of physical attributes; determining for each of the number of physical attributes the intermediate risk value and calculating from the intermediate risk values a final risk score; and determining the assembling risk associated with the final risk score by comparing the final risk'score against a pre-defined risk scale.
A circuit comprises: scan chains comprising scan cells, the scan chains configured to shift in test patterns, apply the test patterns to the circuit, capture test responses of the circuit, and shift out the test responses; a decompressor configured to decompress compressed test patterns into the test patterns; and a test response compactor configured to compact the test responses, the test response compactor comprising: first X-masking circuitry configured to mask, based on first masking information, some of X bits in the test responses, the first masking information remaining the same while a test response for each of the test patterns is being shifted out, the first masking information being different for at least two of the test patterns; and second Xmasking circuitry configured to mask, based on second masking information, rest of the X bits in the test responses.
A computer-implemented method of enabling a user to select at least one component from a group comprising identical and/or non-identical components forming part of a computer-aided design (CAD) model is described. The method comprising the steps of a) receiving a seed component selection from a user via a user input device, the seed component representing component criteria desired by the user; and b)on the basis of the seed component, generating a selection comprising at least one component sharing common shape elements with the seed component. The HDBSCAN algorithm is used to cluster together components within a CAD application, which are then displayed to a user on the basis of the seed component. This enables a user to select similar components quickly and simply.
G06F 30/12 - Geometric CAD characterised by design entry means specially adapted for CAD, e.g. graphical user interfaces [GUI] specially adapted for CAD
G06F 16/532 - Query formulation, e.g. graphical querying
G06F 16/583 - Retrieval characterised by using metadata, e.g. metadata not derived from the content or metadata generated manually using metadata automatically derived from the content
G06T 19/20 - Editing of 3D images, e.g. changing shapes or colours, aligning objects or positioning parts
45.
MULTI-LEVEL PREDICTIONS IN WORKFLOW LOGIC OF COMPUTER-AIDED DESIGN APPLICATIONS
A computing system (100) may logic construction engine (110) configured to construct, via multi-level prediction, workflow logic (220) to process a computer-aided design (CAD) model. The logic construction engine (110 may do so by identifying a multi-node sequence (230, 430) inserted into the workflow logic (220), aggregating past workflow data (240) specific to the multi-node sequence (230, 430), determining a node prediction (250, 350, 450) in the workflow logic (220) for the multi-node sequence (230, 430) based on the aggregated past workflow data (240), and providing the node prediction (250, 350, 450) as a suggested insertion for the workflow logic (220).
G05B 19/4097 - Numerical control (NC), i.e. automatically operating machines, in particular machine tools, e.g. in a manufacturing environment, so as to execute positioning, movement or co-ordinated operations by means of programme data in numerical form characterised by using design data to control NC machines, e.g. CAD/CAM
A computing system (100) may include a computer-aided design (CAD) face access engine (108) configured to access a CAD object and an imprint-based meshing engine (110) configured to define an imprint region (220, 320, 520, 610, 720) for a face (210, 310, 510, 710) of the CAD object and determine that the imprint region (220, 320, 520, 610, 720) meets constraint criteria. Responsive to a determination that the imprint region meets the constraint criteria, the imprint-based meshing engine (110) may modify the imprint region (220, 320, 520, 610, 720) into an adapted imprint region (330, 530, 620, 820) and generate an output mesh (410, 910) using the adapted imprint region (330, 530, 620, 820).
The invention relates to a computer implemented method for providing a recommender system (SRS) for a design process of a complex system, wherein the recommender system (SRS) is shared by a plurality of users (UlCl, U2C1, U1C2), wherein the complex system comprises a plurality of connectable com- ponents and is designed in a design process by a sequence of design steps (DS1, DS2) wherein in each design step a partial design (PD) is created until a completed design (CD) is obtained, wherein a partial design (PD) of one step and a partial de- sign (PD) of a subsequent step differ in a design difference (DELTA) reflecting a difference in at least one element comprising a component or/and connection of the components, and wherein the shared recommender system (SRS) provides at each design step (DS1, DS2) a prediction of the subsequent design difference (DELTA).
G06F 30/12 - Geometric CAD characterised by design entry means specially adapted for CAD, e.g. graphical user interfaces [GUI] specially adapted for CAD
G06F 30/27 - Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
G06F 111/02 - CAD in a network environment, e.g. collaborative CAD or distributed simulation
nn thnn thnn th level expansion are marked as displayable. The process is repeated for all other branch values shown in the initial view. A revised view showing only those values from the initial view in which the branch value, a child value or a descendant value were marked as displayable is then displayed to the user.
This application discloses a computing system to receive measurements of solder paste disposed on a printed circuit board using a solder paste stencil, and correlate the measurements of the solder paste disposed on the printed circuit board to a solder stencil design describing the solder paste stencil utilized during an application of the solder paste on the printed circuit board. The computing system can correlate the solder paste measurements to the solder stencil design by determining a transfer efficiency of the solder paste on the printed circuit board based, at least in part, on the solder paste stencil and the measurements of the solder paste disposed on the printed circuit board. The computing system can detect a cause of a production defect associated with the printed circuit board based, at least in part, on the transfer efficiency of the solder paste on the printed circuit board.
H05K 13/08 - Monitoring manufacture of assemblages
H05K 3/12 - Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using printing techniques to apply the conductive material
50.
AUTOMATED CELL BLACK BOXING FOR LAYOUT VERSUS SCHEMATIC
Text containers comprising information of cell ports are determined based on statements for cell ports in a rule file. Drawn layers comprising cell ports are determined based on the determined text containers or based on statements for attaching each of the test containers to a layout design layer in the rule file. Layout design layers connected to the drawn layers comprising cell ports are determined based on statements for connecting layout design layers in the rule file. A file for cell port detection is generated which associates each of the text containers comprising information of cell ports with one or more of the drawn layers comprising cell ports and one or more of the layout design layers connected to the one or more of the drawn layers comprising cell ports. The file for cell port detection can be used for extracting ports for cells to be black boxed.
There is described building automation systems, methods, and computer readable media for piping graphic control. Field devices (120-126) associated with HVAC equipment are identified and an HVAC piping graphic associated with the field devices (120-126) are generated at the management device (104-108). The HVAC piping graphic is modified at a processor (206) of the management device (104-108) in response to receiving user input at a user interface (111) of the management device (104-108). In particular, a pipe element (358) and a pipe coupling element (360) are integrated with the HVAC piping graphic based on the user input. Data points of the building automation system (100) are provided at the user interface (222) based on the pipe element (358) and the pipe coupling element (360). Runtime values are monitored, and the building automation system (100) are dynamically controlled at the management device (104-108) based on the data points.
A computing system to parse a schematic design illustrating a circuit design for an electronic system to identify text and enclosures representing circuit devices of the electronic system, The computing system can classify the text based on a proximity of the text to the enclosures in the schematic diagram, and match the text to the enclosures in the schematic diagram based on the classifications, which correlates the circuit devices represented by the enclosures to the text matched to the enclosures. The computing system can identify one of the circuit devices includes a connector having one or more pins, and correlate the text matched to the enclosure to at least one of the pins based on a relative alignment of the pins with the text. The computing system can generate an interactive technical file that includes the correlations of the circuit devices and pins to the text matched to the enclosures.
G06V 10/764 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using classification, e.g. of video objects
A computer-implemented method of determining the dimensions of a space-filling lattice in a solid model is disclosed. Initially information including a lattice, a set of faces and data indicating a spatial relationship between the lattice and each face in the set is received. A set of points indicating the intersection positions where each rod intersects a face is then identified, and each intersecting rod is classified based upon whether or not each subset of mutually tolerantly coincident points within the set indicates that a rod is divided by a face. If a rod is divided the lattice is modified by adding a new ball where the rod is divided and classifying the new rods either side of it. These classifications are then spread to adjacent rods without crossing any new ball to establish the complete set of surviving rods. Each connected set of surviving rods is used to instantiate a new lattice.
A method of monitoring messages from a sensor using an integrated circuit is provided, wherein the messages include data measured by that sensor. The method includes: reading a first message from interconnect circuitry of the integrated circuit, the interconnect circuitry connecting the sensor to one or more core devices configured to process the message; calculating a first hash value for the first message; comparing the first hash value to one or more prior hash values stored in a hash store, each prior hash value corresponding to a message that was read from the interconnect circuitry prior to the first message; and performing a corrective action if the difference between the first hash value and at least one of the prior hash values stored in the hash store is above a predetermined threshold.
G08C 25/00 - Arrangements for preventing or correcting errors; Monitoring arrangements
H04Q 9/00 - Arrangements in telecontrol or telemetry systems for selectively calling a substation from a main station, in which substation desired apparatus is selected for applying a control signal thereto or for obtaining measured values therefrom
G06F 11/07 - Responding to the occurrence of a fault, e.g. fault tolerance
55.
METHOD OF MEASURING THE JUNCTION TEMPERATURE OF A SEMICONDUCTOR DEVICE
Tjj Tjj j . Each of the plurality of measurements of the first temperature-sensitive parameter and the at least second temperature-sensitive parameter is synchronized with a switching event of the semiconductor switching element.
G01K 7/01 - Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat using semiconducting elements having PN junctions
56.
METHOD OF VERIFYING INTEGRITY OF DATA FROM A DEVICE UNDER TEST
The current disclosure describes method of verifying integri¬ ty of data from a device under test. The method comprises ob¬ taining network data from the device under test, wherein the network data is generated by the device under test based on a test data from a source device by transforming the test data from a first domain to a second domain and framing the trans¬ formed test data in a first protocol, deframing the received network data from the first protocol to a second protocol for extracting the transformed test data, obtaining the test data from the source device for verifying the transformed test da¬ ta and verifying the integrity of the transformed test data based on the test data using one of a block error rate (BLER) and bit error rate (BER).
A computing system (100) may include a quantifier determination engine (110) configured to determine a defectivity quantifier (310) for a lithographical circuit fabrication process performed with a target value (210) for a process parameter, including by modifying the target value (210) to obtain an off-target value (220) for the process parameter, determining a defectivity quantifier (250) for the lithographical circuit fabrication process performed with the off-target value (220), and extrapolating the defectivity quantifier (310) for the lithographical circuit fabrication process performed with the target value (210) from the determined defectivity quantifier (250) for the lithographical circuit fabrication process performed with the off-target value (220). The computing system (100) may also include a quantifier provision engine (112) configured to provide the determined defectivity quantifier (310) for assessment of the lithographical circuit fabrication process.
G06F 30/20 - Design optimisation, verification or simulation
G06F 30/367 - Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
A computing system implementing a design characterization tool can sample a distribution of values for manufacturing variation of an integrated circuit described by a circuit design. The design characterization tool can order the samples based on predicted output values of the circuit design set with characteristics in the samples of the values for manufacturing variation. The computing system can implement an analog simulator to simulate the circuit design utilizing a subset of the samples of values for manufacturing variation to identify simulated output values for an output distribution model. The design characterization tool can estimate an error in the order of the samples associated with the predicted outputs of the circuit design based on the simulated output values in the output distribution model. The design characterization tool can modify the output distribution model to correct a bias based on the estimated error in the order of the samples.
A computing system (100) may include a design access engine (108) configured to access an injection mold design (210) and a channel construction engine (110) configured to construct conformal cooling channels (510) for the injection mold design (210). The channel construction engine (110) may do so by extracting a cooling surface (600) of the injection mold design (210), generating a central offset surface (220) with a same shape as the cooling surface (600), projecting cooling lines (310) on to the central offset surface (220), detecting sharp portions (410) of the projected cooling lines (320), smoothing the detected sharp portions (410) of the projected cooling lines (320), and generating the conformal cooling channels (510) using the smoothed cooling lines (420) along the central offset surface (220) as a center line for the conformal cooling channels (510). It also relates to the method and a non-transitory machine-readable medium (820) comprising instructions (822, 824).
B29C 33/02 - SHAPING OR JOINING OF PLASTICS; SHAPING OF MATERIAL IN A PLASTIC STATE, NOT OTHERWISE PROVIDED FOR; AFTER-TREATMENT OF THE SHAPED PRODUCTS, e.g. REPAIRING - Details thereof or accessories therefor with incorporated heating or cooling means
B29C 64/386 - Data acquisition or data processing for additive manufacturing
The current disclosure describes a method of generating a simulated multipath fading channel data. The method comprises obtaining an IQ sample data, selecting one or more radio samples from the IQ sample data for appending to the IQ sample data, generating a second IQ sample data by appending the selected one or more radio samples prior to the start radio sample of the IQ sample data and generating the simulated multipath fading channel using the second IQ sample data and a predefined set of propagation delay and attenuation coefficients associated with a channel model.
This application discloses a computing system (400) to generate a product model (409) that describes attributes of a product including an electronic system (401). The computing system (400) can implement a machine-learning algorithm having been trained with metadata populated in previously generated product models for different electronic systems, which can determine one or more sets of metadata capable of being correlated to the electronic system included in the product model based on the attributes of the electronic system described in the product model. The sets of metadata can correspond to different design constraints in the product model associated with electrical connectivity for the electronic system and their corresponding parameter values. The computing system can populate at least one of the sets of metadata into the product model to correlate with the electronic system.
G06F 30/27 - Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
A computing system (100) may include a voxel access engine (108) configured to access voxel data (210, 310) and a voxel processing engine (110). The voxel processing engine (110) may identify and label thin features in the voxel data (210, 310), smooth the voxel data (210, 310) to preserve the thin features, and convert the voxel data (210, 310) to form a faceted representation (320). The voxel processing engine (110) may also adaptively perform a pressing process on the faceted representation (320). Responsive to a determination that a pressing reapplication criterion is satisfied, the voxel processing engine (110) may modify the voxel data (210, 310), convert the modified voxel data (340) to form the faceted representation (320) of the object, and perform the pressing process on the faceted representation (320) of the object formed through the modified voxel data (340).
Today's automation or manufacturing systems are engineered based on solution documents that are typically written in natural language (e.g. English) with domain-specific vocabulary. It is recognized that it can be cumbersome (e.g., time, cost, etc.) to engineer systems, for instance develop software, that operate in multiple domains, based on such solution documents. An engineering computing system can generate executable code (e.g., tenant-specific executable metadata) for an application from the requirements document that defines business requirements written in natural language.
This application discloses distributed forward error correction in hardware assisted verification platforms (300) including a hardware- assisted verification system (320) to emulate an electronic system (322) described by a circuit design (301). The hardware-assisted verification system (320) can implement forward error correction circuitry (324) to analyse a data packet (311) for use by the emulated electronic system (322) during functional verification operations of the circuit design (301), which can identify that the data packet includes one or more corrupted bits (321). The forward error correction circuitry (324) can transmit the corrupted data packet (321) to a computing system (330) implementing an error correction algorithm configured to perform error correction operations (332) on the corrupted data packet (321). The computing system implementing the error correction algorithm (330) can generate a corrected data packet (331) during the error correction operations and transmit the corrected data packet to the hardware-assisted verification system (320) for use by the emulated electronic system (322) during functional verification operations of the circuit design (301).
G06F 30/331 - Design verification, e.g. functional simulation or model checking using simulation with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
G06F 11/36 - Preventing errors by testing or debugging of software
H04L 1/00 - Arrangements for detecting or preventing errors in the information received
65.
SHAPE MATCHING-BASED LAYOUT VERSUS SCHEMATIC FOR PHOTONIC CIRCUITS
A preliminary netlist comprising the photonic devices and location and rotation information for each of the photonic devices is extracted from the original layout design. In the extraction, each of the photonic devices is treated as a black box. A geometric pattern for the each of the photonic devices is then identified in a group of geometric patterns for each of the photonic devices based on physical properties of the each of the photonic devices specified in the circuit design. A new layout design is generated based on the identified geometric pattern for each of the photonic devices, the location and rotation information for each of the photonic devices, and the preliminary netlist. Geometric elements in each of the photonic devices in the new layout design are compared with corresponding geometric elements in the original layout design.
G02B 6/12 - Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
G06F 30/3308 - Design verification, e.g. functional simulation or model checking using simulation
G06F 30/367 - Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
G06F 30/398 - Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
A computing system (100) may include a linear mesh access engine (108) configured to access a linear mesh (120, 210) and a target geometry (130) as well as curved mesh generation engine (110) configured to construct a curved mesh (140). Construction of the curved mesh (140) may include projecting (406) the linear mesh (120, 210) on to the target geometry (130) to form a projected mesh (220), determining (408) deformation patches included in the projected mesh (220), selecting (410) a cost function (340) to apply to the deformation patches from a set of available cost functions (320), iteratively adapting (412) the deformation patches based on the selected cost function (340) to obtain adjusted mesh elements (350), and forming (414) the curved mesh (140) as a combination of the adjusted mesh elements (350) and portions of the projected mesh (220) not determined as part of the deformation patches.
A computing system (100) includes a computer-aided design (CAD) face access engine (108) configured to access a CAD object and an imprint-based meshing engine (110) configured to define an imprint region (220) for a face (210, 310) of the CAD object and decompose the face (210, 310) into virtual faces, including an imprinted virtual face (240, 320) and a remainder virtual face (250, 330). The imprint¬ based meshing engine (110) is also configured to mesh the imprinted virtual face, mesh the remainder virtual face, and merge the imprint region mesh and the remainder region mesh together to form an output mesh (350, 400, 700), including by extending a portion of the imprint region mesh into the remainder portion (230) of the face (210, 310) or extending a portion of the remainder region mesh into the imprint region (220).
A computer-implemented method of bounding spatial data in a hierarchical product structure with hierarchical transforms is described. Initially, the part or part assembly at the lowest level of a hierarchical assembly path is selected. Then, a hierarchical merge of the spatial bounds of the bounding box(es) of the part or part assembly is performed to generate a set of intermediate spatial bounds. Following this, a merge of the set of oriented bounds of the bounding box(es) of the part or part assembly is performed to generate a reduced set of oriented bounds. Finally, the intermediate bounds and the reduced set of oriented bounds are stored for use in configuring the assembly path when building a product from the hierarchical product structure.
A computer-implemented method of extending a mixed sheet within a B-rep model is described. The mixed sheet comprises surfaces having different geometries, such as a mesh positioned between first and second classical geometry surfaces. A first guide curve is defined, located at the boundary of a first surface for a length corresponding to the desired mixed sheet extension adjacent the first surface. A second guide curve may also be defined, located at the boundary of a second surface for a length corresponding to the desired mixed sheet extension adjacent the second surface. At least one extension mesh rung is created by generating facets between the two external mesh vertices using first and second extension vectors, wherein the first extension vector has a pre-determined spatial relationship to the first guide curve. If included, the second extension vector has a pre-determined spatial relationship to the second guide curve.
A computer-implemented method of handling large transforms in a computer-aided design (CAD) solid model utilising double precision to describe a physical assembly of parts is described. If the unit size of a transform of interest exceeds a pre-determined threshold, the double precision of the transform is converted to quadruple precision whilst maintaining the double precision of the assembly (108). The results of any operation are output in double precision (112). A computer program and method of adapting an existing CAD model are also described.
Embodiments of the present disclosure provide a method and system for digital plant system model creation and simulation and a storage medium. The method includes: receiving a digital model created by a user based on a modeling library; in the modeling library, a digital plant system is divided into multiple subsystems, and motion joints in each subsystem are set with at least one option of at least one solution parameter of dynamics, kinematics and articulation; for each motion joint in the digital model, associating a corresponding algorithm engine in a simulation engine with the motion joint according to a solution parameter of the motion joint; the simulation engine comprises a kinematics algorithm engine, a dynamics algorithm engine and an articulation algorithm engine; using the corresponding algorithm engine to solve the motion joint associated with the algorithm engine. The technical scheme in embodiments of the present disclosure can improve the performance, stability and accuracy of the virtual digital plant.
G05B 19/418 - Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control (DNC), flexible manufacturing systems (FMS), integrated manufacturing systems (IMS), computer integrated manufacturing (CIM)
G06F 30/20 - Design optimisation, verification or simulation
G06F 9/455 - Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
72.
SPATIAL DECOMPOSITION-BASED INFILLS OF UNIT CELL DESIGNS FOR COMPUTER-AIDED DESIGN (CAD) OBJECTS
A computing system (100) may include a decomposition engine (110) configured to access a unit cell design (210) and a fill region (220) of a computer-aided design (CAD) object to infill with instances of the unit cell design (210) and spatially decompose the fill region (220) into power-of-two boxes (240). The power-of-two boxes (240) may have dimensions equal to dimensions of the unit cell design (210) multiplied by a power of two. The computing system (100) may also include an infill engine (112) configured to infill the fill region (220) by performing a joining operation of aggregated bodies based on the spatial decomposition of the fill region (220). Each given aggregated body may comprise a number of unit cell designs equal to a power of two that are joined together to form the given aggregated body.
This application discloses a hotspot identification system to generate process variability bands for structures of an integrated circuit capable of being fabricated utilizing at least one lithographic mask based, at least in part, on a mask layout data describing the lithographic mask and a distribution of manufacturing parameters during fabrication. The hotspot identification system can utilize the process variability bands to identify a subset of the structures that correspond to hotspots in the integrated circuit and identify corresponding values for the manufacturing parameters associated with the identified hotspots. A wafer testing system can implement a real-time wafer assessment process by comparing measured manufacturing parameters associated with a fabricated integrated circuit to the values for the manufacturing parameters associated with the identified hotspots, and dynamically identifying a disposition for the fabricated integrated circuit corresponding to one or more structures associated with the identified hotspot based on the comparison.
A modeling method for a tubular structure includes: acquiring a structural wire-frame; generating, at each of non-manifold nodes of the structural wire-frame, a polyhedral structure formed by faces of a polyhedron; generating, at each of manifold nodes of the structural wire-frame, a connecting face; generating, at each of end nodes of the structural wire-frame, an end face; connecting vertices of the connecting wire-frame, vertices of the connecting face, and vertices of the end face; and carrying out curved-surface subdivision.
A method of generating and monitoring a digital signature representing activity observed on signals on an integrated chip in a normal mode of operation is disclosed. A signal se- lector feeds a signal as a selected signal to a temporary memory store to create a value in the temporary memory store. This value is used as the basis of a digital signature repre- senting activity observed on the signal and is compared to a corresponding stored digital signature representing expected activity on the signal. If the comparing indicates a mis- match between the digital signature and the corresponding stored digital signature, an alarm signal is generated. An integrated chip digital signal generator and monitor is also disclosed.
G06F 21/71 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
76.
ELECTRO-MECHANICAL MULTI-BOARD ASSEMBLY AND PLACEMENT COLLABORATION
This application discloses a computing system implementing a shared management system (340) to distribute virtual product models (343), each corresponding to a shared product model (341) describing a product having an electronic device with multiple printed circuit boards, to multiple printed circuit board layout tools (320-1 to 320-N). The printed circuit board layout tools (320-1 to 320-N) separately modify the corresponding virtual product models (343) to generate layout designs for the multiple print circuit boards and generate at least one system-level design rule describing a physical limitation for the electronic device. The shared management system (340) can update the shared product model (341) based on the modifications to at least one of the virtual product models by the printed circuit board layout tools (320-1 to 320-N), and transmit a notification (347) to at least one of the printed circuit board layout tools when the updated shared product model (341) conflicts with the physical limitation for the electronic device described in the at least one system-level design rule.
The current disclosure describes a method of determining a bit length of an IQ sample associated with a first data frame. The method comprises determining a first parameter associated with a payload length of the first data frame, determining a second parameter indicative of a number of physical resource blocks in the first data frame, detecting a presence of a compression header based on the first and second parameters and determining the bit length of the IQ sample from one of the detected compression header and the first and second parameters. Accordingly, in accordance with the above method, the bit length of the IQ sample can be determined automatically from the information available in the data frame. Accordingly, this eliminates the need for manual entry of parameters into the packet analyzer and additionally eliminates the likelihood of errors to due incorrect entry.
A computing system (100) may include physical devices (221, 222, 223, 224, 225, 226) of a manufacturing facility (210) and a message processing engine (110). The message processing engine (110) may be configured to receive, from the physical devices (221, 222, 223, 224, 225, 226) of the manufacturing facility (210), update messages (230) for product manufacture processes performed by the manufacturing facility (210) and parse the update messages (230) to determine a value of a promoted attribute (240) for each of the update messages (230). The message processing engine (110) may also be configured to group the update messages into different message groups according to the determined value of the promoted attribute (240) and sequentially process update messages grouped into a particular message group (310) for a particular value of the promoted attribute (240).
Verification of model-based systems engineering artifacts A method of verifying a model-based system engineering, MBSE, artifact comprising the steps of: translating (SI), by a translator implemented in software, the MBSE artifact into formulas of a first- order logic, checking (S4), by a solver executing a decision procedure implemented in software and operating on the formulas of the first order logic, whether or not a conjunction of the formulas is satisfiable.
A first circuit design and a second circuit design are analyzed to determine part of the second circuit design structurally similar to part of the first circuit design. A first set of test patterns for the first circuit design is modified to generate a second set of test patterns for the second circuit design by reusing values of bits in the first set of test patterns associated with the part of the first circuit design as values of bits in the second set of test patterns associated with the part of the second circuit design. Fault simulation is performed on the second circuit design using the second set of test patterns to determine a subset of faults undetectable by the second set of test patterns. Test pattern generation is performed for the subset of faults to generate a third set of test patterns for the second circuit design.
Systems and a method for detecting a false error in a set of errors detected on components of a board inspected by an AOI machine. Input data are received and wherein the input data comprise data originated from AOI machine's inspection results of a given inspected board marked as failed. A false error detector is applied to the input data and wherein the detector is modeled with a trained function and wherein the detector generates output data. The output data is provided and wherein the output data determines whether at least one of the component errors reported by the AOI machine for the given board is a false error.
A computing system (100) may include a database system (112) and an application server (102). The application server (102) may include a logic packaging engine configured to identify a product (210) at a particular stage of a manufacturing process, extract parameter values for the product (210), and determine processing logic (220) applicable to the product (210). The processing logic (220) may be designed to query the product database (122) for the product (210). The logic packaging engine (110) may also be configured to generate an execution package (230) for the database system (112) to perform the query on the product database (122), and the execution package (230) can include the parameter values for the product (210) at the particular stage in the manufacturing process and metadata references (324, 334, 344) to corresponding query templates (410) stored on the database system (112).
ALLOCATION OF SECONDARY COMPUTING RESOURCE FOR MULTIPLE OPTICAL PROXIMITY CORRECTION (OPC) PROCESSES OF AN ELECTRONIC DESIGN AUTOMATION (EDA) APPLICATION
A computing device (100) may include a CPU (106) and a secondary computing resource (108), such as a GPU (210). The computing device (100) may also include a lithography simulation server engine (110) configured to identify a first OPC process (221) of an EDA application to perform a first OPC simulation task through the computing device (100) as well as a second OPC process (222) of the EDA application to perform a second OPC simulation task through the computing device (100). The lithography simulation server engine (110) may further be configured to control access to the secondary computing resource (108) for performing the first OPC simulation task and the second OPC simulation task via a single multi-threaded process, instead of allowing access to the secondary computing resource (108) by multiple OPC processes that include the first OPC process (221) and the second OPC process (222).
A computing system implementing a design characterization tool can sample a distribution of values describing manufacturing variation for an integrated circuit described by a circuit design. The design characterization tool can utilize a set of the samples to generate a surrogate model of the circuit design, and can order another set of the samples based on predicted outputs of the surrogate model. The design characterization tool can simulate the surrogate model or the circuit design utilizing the ordered samples, and stop the simulations prior to all of the samples from the distribution having been utilized in the simulations. The design characterization tool can utilize a confidence interval stopping condition or a drought stopping condition to determine when to stop the simulations. The design characterization tool can utilize results of the simulations to characterize operational variation of the circuit design to the manufacturing variation described in the distribution of the values.
G06F 30/3308 - Design verification, e.g. functional simulation or model checking using simulation
G06F 30/367 - Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
85.
TRANSITION STRUCTURE GENERATIONS FOR INTERNAL LATTICE STRUCTURE OF COMPUTER-AIDED DESIGN (CAD) OBJECTS
A computing system (100) may include a transition generation engine (110) configured to access a computer-aided design (CAD) object (210) comprising an external surface (220) and an internal lattice structure (222) represented through repeating unit cells (224) of a lattice design, the internal lattice structure (222) represented as a signed distance field (SDF). The transition generation engine (110) may generate a transition structure (230) for the CAD object (210) within a transition distance (310) from the external surface (220), including by applying a secondary SDF (320) to modify a portion of the internal lattice structure (222) within the transition distance (310) from the external surface (220). The computing system (100) may also include an object processing engine (112) may be configured to process the CAD object (210) comprising the transition structure (230) in support of physical manufacture of the CAD object (210).
G06F 30/12 - Geometric CAD characterised by design entry means specially adapted for CAD, e.g. graphical user interfaces [GUI] specially adapted for CAD
G06F 30/17 - Mechanical parametric or variational design
G06F 111/20 - Configuration CAD, e.g. designing by assembling or positioning modules selected from libraries of predesigned modules
87.
METHOD AND SYSTEM FOR ACTIVATING A PCB ANALYSIS UTILIZING MANUFACTURING CAPABILITY DATA
Systems and a method for activating a PCB analysis utilizing manufacturing capability data shared in a multi-tenant collaborative network in a mixed cloud and on-premise environment. Access to a tenant's account of a DFM application deployed on a tenant's premise is provided. The DFM application is enabled to activate a PCB analysis on a DFM profile comprising manufacturing capability data. Via the tenant's account, a cloud data layer is requested an utilization authorization of a given DFM profile stored in the cloud data layer. In case of authorized utilization, the given DFM profile is downloaded into the premise, embedded in a locked DFM envelope, hereinafter called DFM envelope. The DFM envelope is by locking together the given DFM profile with an injected identifier identifying said authorized tenant's account. Via the DFM application when logged into the tenant's account, a PCB analysis is activated by permitting the unlocking of the DFM profile from the DFM envelope only when the identifier of the tenant's account is the same as the injected identifier.
G06F 7/66 - Digital differential analysers, i.e. computing devices for differentiation, integration or solving differential or integral equations, using pulses representing increments; Other incremental computing devices for solving difference equations wherein pulses represent unitary increments only
A testing circuit configured to test and diagnose a read-only memory comprises two multiple-input signature registers configured to generate two sets of signatures for multiple iterations of reading some or all of words stored in the read-only memory, control circuitry configured to control, according to a test algorithm, from which of the outputs of the read-only memory each of the two multiple-input signature registers receives test response signal bits for each of the reading operations during each of the iterations, and a faulty element location determination device configured to generate a faulty element location signal for the read-only memory based on results of comparing the two sets of signatures with reference signatures.
A computing system (100) includes a model access engine (108) configured to access a CAD model (210) comprised of multiple CAD parts. The computing system (100) also includes a model explosion engine (110) configured to construct a blocking data structure (230) for the CAD model (210) that stores a blocking state for each pair of CAD parts of the CAD model (210) as well as an explosion graph (310) for the CAD model (210). Iterative generation of the explosion graph (310) by the model explosion engine (110) includes querying the blocking data structure (230) to determine unblocked CAD parts for which to insert a node into the explosion graph (310). The model explosion engine (110) also is configured to generate an exploded view representation (410) of the CAD model (210) using the constructed explosion graph (310).
The described method as a key enabler for Optical Inspection dynamically uses individual marks like fiducials, barcodes, data matrix codes ("markers") in the scenes, beyond their basic presence, meaning the change of situation between a first processing status and a subsequent processing status in the processing station. The same markers are simultaneously used for a) the identification of components ("comp") b) the identification of locations ("loc") and c) the definition of dependencies between identity and location (valid, invalid) and d) the automated detection and evaluation of the dependencies.
G05B 19/418 - Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control (DNC), flexible manufacturing systems (FMS), integrated manufacturing systems (IMS), computer integrated manufacturing (CIM)
H01B 13/012 - Apparatus or processes specially adapted for manufacturing conductors or cables for manufacturing wire harnesses
91.
METHOD AND SYSTEM FOR DYNAMICALLY RECOMMENDING COMMANDS FOR PERFORMING A PRODUCT DATA MANAGEMENT OPERATION
A method and system for dynamically recommending commands for performing a PDM operation on product data objects in a product data management environment is disclosed. In one embodiment, a method includes determining a context in which a user is operating within a product data management environment. The method includes dynamically determining a set of commands suitable for performing a candidate PDM operation on the product data objects based on the determined context. Furthermore, the method includes computing a score for each of the commands suitable for performing the candidate PDM operation on the product data objects. Moreover, the method includes assigning a rank to said each command suitable for performing the candidate PDM operation based on the score associated with said each command, and outputting one or more commands from the set of commands on a graphical user interface based on the rank assigned to said each command.
A method and system for validating product and manufacturing information associated with a geometric model in a computer-aided design environment is disclosed. The method (200) includes the steps of generating (202) a geometric model of a physical object in the computer-aided design environment, wherein the geometric model of the physical object includes product and manufacturing information. The method further includes extracting (204) the product and manufacturing information from the geometric model, and validating (208) the extracted product and manufacturing information using at least one checker, wherein the checker includes one or more logical elements capable of validating the product and manufacturing information. The method includes outputting (210) the results of validation of the product and manufacturing information on a graphical user interface.
Aspects of the disclosed technology relate to techniques for applying optical proximity correction to free form shapes. Each optical proximity correction iteration comprises: computing edge adjustment values for the straight line fragments based on edge placement errors derived from an optical proximity correction iteration immediately preceding the each of the plurality of optical proximity correction iterations, adjusting locations of the straight line fragments based on the determined edge adjustment values, determining smooth boundary lines for the layout features based on the straight line fragments on the adjusted locations, performing a simulation process on the layout features having the smooth boundary lines to determine a simulated image of the layout features, and deriving the edge adjustment errors for the straight line fragments based on comparing the simulated image with a target image of the layout features.
G03F 1/36 - Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
G03F 1/70 - Adapting basic layout or design of masks to lithographic process requirements, e.g. second iteration correction of mask patterns for imaging
A computing system implementing a design verification system can classify a mixed-signal circuit design describing an electronic device based on a design topology of the mixed-signal circuit design. This classification can be performed by identifying a top-level design block in the mixed-signal circuit design, traversing a connectivity of a design hierarchy to identify lower-level design blocks in the mixed-signal circuit design, and classifying the mixed-signal circuit design based on at least one of a design type of the top-level design block, design types of the lower-level design blocks, or a connectivity of design blocks in the mixed-signal circuit design. The design verification system can selectively partition the mixed-signal circuit design into an analog partition and a digital partition based on the classification, and simulate the analog partition of the mixed-signal circuit design with an analog simulator and the digital partition of the mixed-signal circuit design with a digital simulator.
A method and system for generating a three-dimensional model of a multi-thickness object in a formed state in a computer-aided design (CAD) environment is disclosed. The method includes receiving a request to generate a feature of a three-dimensional model, creating a virtual datum plane, and dynamically computing an offset value for the feature with reference to the virtual datum plane based on a thickness value. The offset value determines an offset between the virtual datum plane and one surface of the feature. The method includes generating the feature of the three-dimensional model in the formed state with reference to the virtual datum plane based on the thickness value, a location of the feature, and the offset value. The method also includes outputting the three-dimensional model of the multi-thickness object having the generated feature in the formed state.
A computing system (100) may include a constraint learning engine (110) and a constraint generation engine (112). The constraint learning engine (110) may be configured to access a computer- aided design (CAD) assembly (130) comprising multiple CAD parts and generate a representation graph of the CAD assembly (130), determine constraints in the CAD assembly (130), wherein the constraints limit a degree of movement between geometric faces of different CAD parts in the CAD assembly (130), insert constraint edges into the representation graph that represent the determined constraints; and provide the representation graph as training data to train a machine-learning model (120). The constraint generation engine (112) may be configured to generate constraints for a different CAD assembly by applying the machine-learning model (120) for the different CAD assembly.
G06F 30/12 - Geometric CAD characterised by design entry means specially adapted for CAD, e.g. graphical user interfaces [GUI] specially adapted for CAD
The current disclosure describes a method of programming a software module associated with a firmware unit of a device. The method comprises obtaining a register transfer level pro- gram associated with the firmware unit, the register transfer level program comprising a plurality of register variables indicative of a plurality of registers in the firmware unit, defined within a first namespace of the register transfer level program; and linking the first namespace associated with the register transfer level program with a namespace as- sociated with a software module for referencing at least one of the register variable from the plurality of register vari- ables. The register transfer level program includes design level description of one or more operations associated with the firmware unit in a high-level programming language.
Systems and methods for simulation and testing of multiple virtual electronic control units (VECUs). A method (1000) includes executing, by one or more computer systems (101), a first VECU (502). The method includes executing a virtual bus (510), the virtual bus (510) associated with the first VECU (502). The method includes executing at least one second VECU. The method includes simulating a multiple-VECU system by managing communications, using the virtual bus (510), between the first VECU (502) and the at least one second VECU.
A computing system to generate models of managed devices and applications in an Internet of Things (IOT) system by identifying each endpoint in the managed devices and applications capable of transmitting or receiving the data and defining flows for data from the endpoints in sensors to endpoints of IOT servers via endpoints of the programmable edge device applications. The computing system can develop a data flow map to define a connectivity of the programmable edge device applications to the sensors and the servers in the IOT system for exchanging the data from the sensors to the servers in the IOT system via the programmable edge device applications. The computing system can prompt configuration of the managed devices and applications in the IOT system based on the data flow map, which implements the connectivity of the programmable edge device applications to the sensors and to servers in the IOT system.
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