For an improved management of a postprocessor, for machining with a machine tool, a computer-implemented method includes providing toolpath data for machining a workpiece with a tool along a corresponding toolpath. The tool is comprised by a machine tool that is numerically controlled by a control device. Sample machine code is provided. Atrial postprocessor software component for determining machine code using toolpath data is provided. Trial machine code is determined using the trial postprocessor software component and the toolpath data. A sample code architecture of the sample machine code and a trial code architecture of the trial machine code are determined. Characteristics of the sample machine code are determined by comparing the sample code architecture with the trial code architecture, and a new postprocessor software component is determined by incorporating the characteristics into the trial postprocessor software component.
G05B 19/29 - Numerical control (NC), i.e. automatically operating machines, in particular machine tools, e.g. in a manufacturing environment, so as to execute positioning, movement or co-ordinated operations by means of programme data in numerical form characterised by positioning or contouring control systems, e.g. to control position from one programmed point to another or to control movement along a programmed continuous path using an absolute digital measuring device for point-to-point control
G05B 19/4093 - Numerical control (NC), i.e. automatically operating machines, in particular machine tools, e.g. in a manufacturing environment, so as to execute positioning, movement or co-ordinated operations by means of programme data in numerical form characterised by part programming, e.g. entry of geometrical information as taken from a technical drawing, combining this with machining and material information to obtain control information, named part programme, for the NC machine
2.
Hybrid Switching Architecture For SerDes Communication Channels In Reconfigurable Hardware Modeling Circuits
Various aspects of the present disclosed technology relate to hybrid static and dynamic switching in a reconfigurable hardware modeling circuit for flexible and low latency communications. The reconfigurable hardware modeling circuit comprises serializer circuitry and deserializer circuitry for one or more communication ports, wherein the serializer circuitry has first sub-channels for receiving data to be sent out from the reconfigurable hardware modeling circuit, and the deserializer circuitry has second sub-channels for outputting data received by the reconfigurable hardware modeling circuit. The reconfigurable hardware modeling circuit also comprises static switching circuitry configurable to couple each of first zero or one or more sub-channels in the first sub-channels with one of signal sources comprising the second sub-channels and dynamic switching circuitry configurable to couple, in a time-division multiplexing mode, each of second zero or one or more sub-channels in the first sub-channels with more than one of the signal sources.
G06F 30/331 - Design verification, e.g. functional simulation or model checking using simulation with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
A computer implemented method of dynamically verifying clock domain crossing (CDC) paths in a register-transfer level (RTL) design is provided. In addition to static analysis, formal analysis, and simulation steps, each CDC path is allocated a persistent unique identifier. This enables the updating of a centralized results database using the persistent unique identifier to label the associated CDC protocol assertions, functional coverage, and results of the formal analysis and simulation. In addition, prior to simulation analysis, CDC protocol assertions that have been proven during formal analysis are turned off, resulting in the simulation run only being carried out for non-proven CDC protocol assertions.
Surface editing is performed in typical computer-aided design (CAD) software products by using special tools to edit special surfaces, such as b-splines or subdivision surfaces. It is recognized herein that current approaches to editing surfaces are not generally applicable. For example, common CAD and surface modeling software products are tailored to a specific surface type or vendor specific format, or otherwise are not generally applicable to given analytical and non-analytical surfaces. In various embodiments described herein, subdivision surfaces can be generated to represent any surface. Further, surfaces can be manipulated using a control cage associated with the subdivision surface.
High Bandwidth IJTAG Through High Speed Parallel Bus A system in a circuit comprises: a first network (710) configurable to transmit data in parallel in the circuit, the first network (710) comprising circuit block interface devices, each of the circuit block interface devices being coupled to ports of one of circuit blocks in the circuit; a plurality of second networks (720, 725, 727), each of the plurality of second networks (720, 725, 727) configurable to transmit data in serial in one of the circuit blocks in the circuit; a third network (730) configurable to transmit data in serial in the circuit when being coupled to the plurality of second networks (720, 725, 727); and a plurality of network switching interface devices (740, 745, 747), each of the plurality of network switching interface devices (740, 745, 747) configurable to couple either the first network (710) or the third network (730) to one of the plurality of second networks (720, 725, 727) based on a control signal stored in the each of the plurality of interface devices (740, 745, 747).
Various aspects of the present disclosed technology relate to techniques for classifying layout patterns. First, a set of density feature vectors for a set of layout regions in the layout design are extracted using a set of rings. Each component of a density feature vector in the set of density feature vectors corresponds to a ring in the set of rings. The set of rings do not overlap with each other and cover a whole area of a circle when being placed together. Next, a machine learning-based clustering process is performed to separate layout features in the set of layout regions into clusters of layout features based on the set of density feature vectors. Each of the clusters of layout features may be further divided into subclusters based on one or more properties.
G06F 30/27 - Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
G06F 30/392 - Floor-planning or layout, e.g. partitioning or placement
7.
HEAT-AWARE TOOLPATH GENERATION FOR 3D
PRINTING OF PHYSICAL PARTS
A computing system may include an access engine and a heat-aware toolpath engine. The access engine may be configured to access a slice of a 3-dimensional (3D) computer-aided design (CAD) object, wherein the 3D CAD object represents a physical part and wherein the slice represents a physical layer for 3D printing of the physical part. The heat-aware toolpath engine may be configured to generate a layer toolpath to control the 3D printing of the physical layer, including by partitioning the slice into zones and determining a zone order, based on a heat-aware criterion, for the layer toolpath to traverse for the 3D printing of the physical layer. The heat-aware toolpath engine may also be configured to provide the layer toolpath to support the 3D printing of the physical part.
A method of protocol processing including a main program code that has one or more code segments and instructions for processing different protocol elements of a data packet stream of a transport protocol is disclosed herein. The method includes assigning a latency requirement and/or bandwidth requirement to one or more of the code segments of the main program code; and compiling each of the code segments according to the assigned latency and/or bandwidth requirement into a respective target code for executing each of the target codes by different processors.
A database stores a set of items, with each item having technical attributes, and with each item representing a module that can be used in an engineering project of a first user, u1. A feature encoder embeds each item based on its technical attributes into a low-dimensional vector space. Then, in a second step, a graph neural network pools over these item embeddings to compute an updated user embedding for the first user A decoder mapping then addresses the recommendation task by outputting recommendation scores for each item. That means, heuristically speaking, that the method and system lift the recommendation task to the level of technical attributes to overcome the sparsity problem caused by item sets that are not overlapping between user groups. Thus, when matching similar users, the method does not rely on users configuring exactly the same modules but rather on configured modules that are similar from a technical point of view.
G05B 13/02 - Adaptive control systems, i.e. systems automatically adjusting themselves to have a performance which is optimum according to some preassigned criterion electric
10.
MACHINE LEARNING-BASED GENERATION OF CONSTRAINTS FOR COMPUTER-AIDED DESIGN (CAD) ASSEMBLIES
A computing system may include a constraint learning engine and a constraint generation engine. The constraint learning engine may be configured to access a computer-aided design (CAD) assembly comprising multiple CAD parts and generate a representation graph of the CAD assembly, determine constraints in the CAD assembly, wherein the constraints limit a degree of movement between geometric faces of different CAD parts in the CAD assembly, insert constraint edges into the representation graph that represent the determined constraints; and provide the representation graph as training data to train a machine-learning model. The constraint generation engine may be configured to generate constraints for a different CAD assembly by applying the machine-learning model for the different CAD assembly.
G06F 30/27 - Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
Systems and methods for simulation and testing of multiple virtual electronic control units (VECUs). A method (1000) includes executing, by one or more computer systems (101), a first VECU (502). The method includes executing a virtual bus (510), the virtual bus (510) associated with the first VECU (502). The method includes executing at least one second VECU. The method includes simulating a multiple-VECU system by managing communications, using the virtual bus (510), between the first VECU (502) and the at least one second VECU.
H04L 43/20 - Arrangements for monitoring or testing data switching networks the monitoring system or the monitored elements being virtualised, abstracted or software-defined entities, e.g. SDN or NFV
A method and system for generating a geometric component in a computer-aided design (CAD) environment using machine learning models is provided. A computer-implemented method for generating a geometric component in a CAD environment includes determining a geometric operation to be performed on at least one geometric component in the CAD environment based on a CAD command selected by a user. The method also includes determining one or more candidate groups including one or more candidates in the geometric component suitable for performing the geometric operation using one or more trained machine learning models. The method also includes identifying at least one candidate group from the one or more candidate groups on which the geometric operation is to be performed. The method also includes performing the geometric operation on the one or more candidates in the identified candidate group.
G06F 30/27 - Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
A computing system may include an access engine and a toolpath reordering engine. The access engine may be configured to access an original layer toolpath for slice of a 3D CAD object as well as a heat criticality measure for the original layer toolpath. The heat criticality measure may specify a heat impact for different points on the multiple toolpath segments of the original layer toolpath for the 3D printing of the physical part using the original layer toolpath. The toolpath reordering engine may be configured to reorder the multiple toolpath segments into a modified layer toolpath, and the modified layer toolpath may have a heat criticality measure with a lesser heat impact on the physical part than the heat criticality measure for the original layer toolpath.
A computing system may include a hotspot processing engine and a hotspot prediction engine. The hotspot processing engine may be configured to access an input data set of hotspot locations on manufactured circuits of a circuit design, correlate the hotspot locations to layout data for the circuit design, and extract fragment feature vectors for the hotspot locations. The hotspot processing engine may further be configured to process the fragment feature vectors such that hotspot fragment feature vectors are a threshold percentage of the total number of feature vectors in the fragment feature vectors and provide the processed fragment feature vectors as a training set for training a machine-learning model. The hotspot prediction engine may be configured to apply the machine-learning model to characterize locations of the circuit design as a hotspot location or a non-hotspot location.
G06F 30/398 - Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
G06F 30/27 - Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
A method is provided for generating test data for testing radio equipment. The method includes: determining, by a test apparatus, one or more beam identifiers; selecting, by the test apparatus, based on the one or more beam identifiers, one or more radio channel models; receiving, by the test apparatus, a baseband signal representing I/Q data of one or more beamforming antennas; processing, by the test apparatus, the baseband signal representing I/Q data according to the selected radio channel model; and transmitting, by the test apparatus, the processed baseband signal representing I/Q data to a radio equipment under test.
H04B 7/06 - Diversity systems; Multi-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station
H04B 7/08 - Diversity systems; Multi-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the receiving station
A computing system may include an upgrade access engine configured to access a database upgrade to perform for a production database. The computing system may also include a database upgrade engine configured to generate multiple clones of the production database, including a production clone and a delta clone with instance data removed. The database upgrade engine may perform the database upgrade on the production clone, track changes to the production database, and push the tracked changes to the delta clone. After the database upgrade on the production clone completes, the database upgrade engine may perform the database upgrade on the delta clone, push upgraded data of the delta clone to the upgraded production clone, and set the upgraded production clone as an upgraded version of the production database.
G06F 16/21 - Design, administration or maintenance of databases
G06F 16/27 - Replication, distribution or synchronisation of data between databases or within a distributed database system; Distributed database system architectures therefor
A method of monitoring messages from a sensor using an integrated circuit is provided. The messages include data measured by that sensor. The method includes reading a first message from interconnect circuitry of the integrated circuit. The interconnect circuitry connects the sensor to one or more core devices configured to process the messages. A first hash value is calculated for the first message. The first hash value is compared to one or more prior hash values stored in a hash store. Each prior hash value of the one or more prior hash values corresponds to a message that was read from the interconnect circuitry prior to the first message. A corrective action is performed when a difference between the first hash value and at least one of the prior hash values stored in the hash store is below a predetermined threshold.
A computing system may include a hyperspace generation engine and a hyperspace processing engine. The hyperspace generation engine may be configured to access a feature vector set, and feature vectors in the feature vector set may represent values for multiple parameters of data points in a dataset. The hyperspace generation engine may further be configured to perform a principal component analysis on the feature vector set and quantize the principal component space into a hyperspace comprised of hyperboxes. The hyperspace processing engine may be configured to process the dataset according to a mapping of the feature vector set into the hyperboxes of the hyperspace.
A method and system for trimming intersecting bodies of a geometric model in a computer-aided design environment is disclosed. In one embodiment, a method includes determining a plurality of bodies of the geometric model intersecting with each other. The method includes computing volume of one or more intersecting bodies in the geometric model to be trimmed from the geometric model. Also, the method includes determining a trim offset value for at least one intersecting body in the geometric model and recomputing the volume of the at least one intersecting body in the geometric model which is to be trimmed from the geometric model based on the trim offset value. Moreover, the method includes generating a modified geometric model by performing a trim operation on the volume of the one or more intersecting bodies of the geometric model.
G06F 30/17 - Mechanical parametric or variational design
G06F 30/27 - Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
A computer-implemented method of indexing a hierarchical data structure or product structure is disclosed. For a product structure including a product and a plurality of items associated with the product, each item shares a parent-child relationship with at least one other item or the product. The method includes generating a packed configuration-independent index of the product structure by enumerating an unconfigured item-path from the product to an item for each item. Then, when one or more unconfigured item-paths are identical, only one of the identical unconfigured item-paths is maintained. The index may also be combined with an unconfigured item-path spatial-bounds index. Both product structure and spatial location queries may be filtered against the combined index.
A memory-testing circuit configured to perform a test of reference bits in a memory. In a read operation, outputs of data bit columns are compared with one or more reference bit columns. The memory-testing circuit comprises: a test controller and association adjustment circuitry configurable by the test controller to associate another one or more reference bit columns or one or more data bit columns with the data bit columns in the read operation. The test controller can determine whether the original one or more reference bit columns have a defect based on results from the two different association.
This application discloses a computing system implementing a yield enhancer tool to extract characteristics of cells from a physical layout design for an integrated circuit, determine locations of vacant regions in the physical layout design, apply electrical design rules for manufacture of the integrated circuit to the extracted characteristics in order to identify cells in the physical layout design that would violate the electrical design rules. The computing system can select filler cells for the vacant regions based, at least in part, on extracted characteristics of the cells abutting the vacant regions and the electrical design rules, and insert the selected filler cells in the vacant regions of the physical design layout. The computing system can perform a design rule check operation, which applies the electrical design rules to the physical design layout having been inserted with the selected filler cells.
A method, executed by at least one processor of a computer, of generating a heatsink configuration meeting a predetermined performance constraint is disclosed. The method includes establishing an initial heatsink configuration having a heatsink base including at least one layer formed of a plurality of tessellated rods and setting a thermal evaluation parameter. An initial thermal simulation of a heat source positioned proximate the heatsink base is performed to determine the initial thermal performance of the heatsink. Based on the initial thermal simulation, three revised heatsink configurations are examined, and simulations are carried out to generate first, second, and third revised thermal performances. These are compared with an initial thermal performance, and the heatsink configuration showing the greatest improvement in thermal performance compared with the initial thermal performance is selected. This process is repeated until a heatsink configuration meeting the predetermined performance constraint is generated.
A computing system may include a metamaterial representation engine configured to represent a metamaterial of a three-dimensional (3D) object as program code. The metamaterial may define an internal geometry of the 3D object and may be configured to be physically constructed via additive manufacturing. Representation of the metamaterial as program code may include assigning a value of a code parameter of the metamaterial as a probability distribution. The computing system may also include a metamaterial analysis engine configured to analyze the metamaterial through the probability distribution assigned for the value of the code parameter of the program code.
G06F 30/12 - Geometric CAD characterised by design entry means specially adapted for CAD, e.g. graphical user interfaces [GUI] specially adapted for CAD
25.
ASYNCHRONOUS INTERFACE FOR TRANSPORTING TEST-RELATED DATA VIA SERIAL CHANNELS
A circuit comprises: a first clock gating device clocked by a first clock signal and configured to generate first clock pulses when a shift enable signal is active, a first transition detecting device clocked by a second clock signal and configured to generate shift gating pulses when detecting active transitions of the first clock pulses, a second clock gating device clocked by the second clock signal and configured to generate shift clock pulses based on the shift gating pulses to clock second scan elements for a shift operation with first scan elements clocked by the first clock signal, and a first retiming device triggered by active pulse edges of the first clock signal and configurable to hold a value for the shift operation. The circuit may further comprise a delay generating device configured to generate delayed shift gating pulses for generating the shift clock pulses.
System and method for differentiable networks trainable to learn an optimized query of a 3D model database used for object recognition includes training a first differentiable network configured as a differentiable renderer by generating 2D images from 3D models of a first object of a dissimilar second object while optimizing rendering parameters for producing 2D images by gradient descent of a first triple loss function. Visual variation among the images is maximized. A second differentiable network configured as a convolutional neural network defined by a regression function is trained by generating searchable feature vectors of the 2D images. The feature vectors are determined using optimized neural network parameters determined by gradient descent of a second triple loss function to achieve high correlation to an input image of the first object and low correlation to images of the second object.
Various aspects of the present disclosed technology relate to techniques for inverse-lithography-technology-based optical proximity correction. A layout design is received. A machine learning-based clustering process is then performed to separate layout features in the layout design into groups of layout features. For layout features in each of the groups of layout features, preliminary corrections are determined. The determination may be based on inverse lithography technology. The preliminary corrections are applied to the layout design to generate a pre-processed layout design. An inverse lithography technology process is performed on the pre-processed layout design to generate a processed layout design. Masks can be manufactured based on the processed layout design.
G03F 1/36 - Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
G03F 1/70 - Adapting basic layout or design of masks to lithographic process requirements, e.g. second iteration correction of mask patterns for imaging
G06F 30/27 - Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
28.
VARIANT MODEL-BASED COMPILATION FOR ANALOG SIMULATION
A computing system implementing a design verification system can detect multiple analog design blocks in a circuit design describing an electronic device. The design verification system can generate equivalent networks for the analog design blocks using different sets of the parameters of the analog design blocks by selectively collapsing nodes and braches in the analog design blocks based on values of the different sets of the parameters. The equivalent networks can correspond to behavioral topologies of the analog design blocks having the different sets of the parameters. The design verification system can selectively compile a subset of the analog design blocks into multiple compiled variant models based on a comparison of the equivalent networks. The design verification system can include an analog simulator to simulate the analog design blocks in the circuit design using the compiled variant models.
G06F 30/367 - Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
G06F 30/323 - Translation or migration, e.g. logic to logic, hardware description language [HDL] translation or netlist translation
29.
CONTROLLABLE PATTERN CLUSTERING FOR CHARACTERIZED SEMICONDUCTOR LAYOUT DESIGNS
A computing system implementing a physical verification tool can determine principal feature components describing geometric patterns around points of interest in a semiconductor layout design. The principal feature components include topological features indicating whether structures are present around the points of interest, and include dimensional features corresponding to measurements associated with the structures present around the points of interest. The physical verification tool can generate a topological signature for each of the points of interest based on the topological features, and cluster the points of interest into different subsets based on the topological signature. The physical verification tool can perform design rule check operations on the semiconductor layout design to identify whether one or more of the points of interest correspond to a design rule violation and perform pattern matching to identify whether other points of interest match the point of interest corresponding to the design rule violation.
This application discloses a computing system implementing a mask synthesis system to generate synthetic image clips of design shapes and corresponding mask data for the synthetic image clips. The mask data can describe lithographic masks capable of being used to fabricate the design shapes on an integrated circuit. The mask synthesis system can utilize the synthetic image clips of the design shapes and the corresponding mask data to train a machine-learning system to determine pixelated output masks from portions of the layout design. The mask synthesis system can identify one or more pixelated output masks for portions of a layout design describing an electronic system using the trained machine-learning. The mask synthesis system can synthesize a mask layout design for the electronic system based, at least in part, on the layout design describing the electronic system and the one or more pixelated output masks for the layout design.
G05B 19/4093 - Numerical control (NC), i.e. automatically operating machines, in particular machine tools, e.g. in a manufacturing environment, so as to execute positioning, movement or co-ordinated operations by means of programme data in numerical form characterised by part programming, e.g. entry of geometrical information as taken from a technical drawing, combining this with machining and material information to obtain control information, named part programme, for the NC machine
G06F 30/392 - Floor-planning or layout, e.g. partitioning or placement
This application discloses a computing system implementing a power estimator can read in waveform data generated during functional verification of a circuit design describing an electronic device, detect toggles in the signals of the waveform data, correlate the detected toggles in the signals to arcs associated with logic gates in the circuit design, and track a number of times each of the arcs has been correlated to the detected toggles. After the waveform data has been read, the power estimator can look-up power values for each arc having been correlated to a detected signal toggle, multiple the power values by the tracked number of times each of the arcs been correlated to the detected toggles to compute power estimates, and generate an estimate of power consumption for the circuit design during the functional verification by accumulating the power estimates for the arcs associated with the logic gates.
G06F 30/33 - Design verification, e.g. functional simulation or model checking
G06F 30/3308 - Design verification, e.g. functional simulation or model checking using simulation
G06F 30/327 - Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
G06F 30/398 - Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
G06F 30/367 - Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
G01R 21/00 - Arrangements for measuring electric power or power factor
32.
MACHINE LEARNING-BASED UNRAVEL ENGINE FOR INTEGRATED CIRCUIT PACKAGING DESIGN
This application discloses a computing system to identify net lines corresponding to connections between pins of a source layout design describing a first electronic device and pins of a target layout design describing a second electronic device, scan the net lines in an order selected based, at least in part, on an orientation of the net lines between pins of the source layout design and the pins of the target layout design, identify a plurality of the scanned net lines cross each other, and unravel the crossed net lines by swapping pin assignments of the crossed net lines. The computing system can implement a machine learning algorithm having a first stage to determine a scan order for the net lines and having a second stage to identify the net lines that cross each other and unravel the crossed net lines.
A computing system may include a virtual cross metrology engine configured to construct a given virtual metrology model. The given virtual metrology model may take, as inputs, process parameters applied for the given step of a semiconductor fabrication process. The virtual cross metrology engine may also be configured to construct a subsequent virtual metrology model, and the subsequent step is performed after the given step in the semiconductor fabrication process. Doing so may include determining inputs for the subsequent virtual metrology model from a combination of the process parameters applied for the given step of the semiconductor fabrication process, process parameters applied for the subsequent step of the semiconductor fabrication process, and a wafer value for the given step of the semiconductor fabrication process that the given virtual metrology model is configured to predict.
G05B 19/418 - Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control (DNC), flexible manufacturing systems (FMS), integrated manufacturing systems (IMS), computer integrated manufacturing (CIM)
G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
34.
PARALLEL SIMULATION QUALIFICATION WITH PERFORMANCE PREDICTION
A simulator can simulate a circuit design describing an electronic device using a single processing device of a computing system. The simulator can generate profile data associated with compilation of the circuit design and the single processing device simulation of the compiled circuit design. The profile data can identify multiple different ways to partition the circuit design and include information corresponding to the single processing device simulation of the compiled circuit design. A parallel simulation qualifier can determine a parallelism factor corresponding to an expected performance of the computing system in a multiple processing device simulation of the circuit design based on the profile data from the single processing device simulation of the circuit design. The simulator can utilize the parallelism factor to partition the circuit design in one of the different ways, and simulate the partitioned circuit design with multiple processing devices of the computing system.
A computing system may include a client device and a server. The client device may be configured to access a stream of image frames that depict an environment, determine, from the stream of image frames, environment images that satisfy selection criteria, and transmit the environment images to the server. The server may be configured to receive the environment images from the client device, construct a spatial view of the environment based on position data included with the environment images, and navigate the spatial view, including by receiving a movement direction and progressing from a current environment image depicted for the spatial view to a next environment image based on the movement direction.
A memory device can sense stored data during memory read operations using a reference trim, and a memory built-in self-test system can perform a multiple step process to set the reference trim for the memory device. The memory built-in self-test system can set a reference trim range that corresponds to a range of available reference trim values and then select one of the reference trim values in the reference trim range as the reference trim for the memory device. The memory built-in self-test system can set the reference trim range by prompting performance of the memory read operations using different positions of the reference trim range relative to read characteristics of the memory device and set a position for the reference trim range relative to the read characteristics of the memory device based on failures of the memory device to correctly sense the stored data during the memory read operations.
A computer-implemented method of incarnating a self-intersecting lattice structure as a mesh in a three-dimensional model is described. A pair of bodies in the lattice is chosen. An initial set of sample points is created by intersecting a set of constant parameter curves within the parameter range lying on the surface of one of the bodies of the pair with the surface of the other body of the pair. Chords between adjacent sample points in the initial set of samples that lie within a pre-determined tolerance of the surfaces of both bodies in the pair are calculated and iterated over until all the sample points are within the pre-determined tolerance. Once this is done for all bodies in the lattice, a mesh is incarnated.
A method and device for testing a base station comprising one or more radio units and a baseband unit connectable to the one or more radio units, wherein the device includes a configuration module configured to generate a first test case configuration associated with the one or more radio units and the baseband unit, where the first test case configuration includes a first protocol stack including a first protocol associated with a first layer and a second protocol associated with a second layer, and where a first set of protocol parameters associated with the first protocol is in a first namespace and a second set of protocol parameters associated with the second protocol is in a second namespace that is distinct from the first name space.
A method for determining a set of output configuration values characterizing a specific configuration of a complex product, includes receiving a set of input configuration parameters, providing at least a part of the input configuration parameters as an input to a solver, using the solver to calculate at least one output value from the provided input configuration parameters, and determining the set of output configuration values from at least the output value calculated by the solver. The solver is configured for solving a first order logic function encoding an algorithm of a trained deep neural network or DNN, wherein the algorithm of the DNN has been trained for modeling a function of an external configuration tool or ECT that is required for determining the specific configuration of the complex product. A system for determining the set of output configuration values, and a training system, are also provided.
G06Q 10/04 - Forecasting or optimisation specially adapted for administrative or management purposes, e.g. linear programming or "cutting stock problem"
G06Q 10/06 - Resources, workflows, human or project management; Enterprise or organisation planning; Enterprise or organisation modelling
A method is provided for transmission rate adaptation of one or more data units, the method including: receiving, by an adapter, the adapter including an adaptation circuitry, a plurality of data units according to a first transmission rate and at least one delay character separating two consecutive data units; and transmitting, by the adapter, each of the plurality of data units received according to a second transmission rate, wherein the second transmission rate is determined based on the at least one delay character received.
A computer-implemented method is provided for determining a cut pattern of a lathe. The lathe is numerically controlled by a control device and includes a tool with a cutter acting on a workpiece. The workpiece has a start contour and a target contour to be achieved by cutting the workpiece according to the cut pattern. The method includes determining a path of a n-th layer of the cut pattern, wherein the n-th layer includes: for n≥2: an infeed path linear and/or parallel to the target contour; a circular infeed path starting tangent to the target contour; an intermediate path linear and/or parallel to the target contour; a circular outfeed path ending tangent to the target contour; and for n≥2: a smoothing path linear and/or parallel to the target contour.
G05B 19/4093 - Numerical control (NC), i.e. automatically operating machines, in particular machine tools, e.g. in a manufacturing environment, so as to execute positioning, movement or co-ordinated operations by means of programme data in numerical form characterised by part programming, e.g. entry of geometrical information as taken from a technical drawing, combining this with machining and material information to obtain control information, named part programme, for the NC machine
42.
METHOD AND APPARATUS FOR DESIGNING AND MANUFACTURING A COMPONENT IN A COMPUTER-AIDED DESIGN AND MANUFACTURING ENVIRONMENT
A method and apparatus for designing and manufacturing a component in a computer-aided design and manufacturing environment is disclosed. A method includes obtaining a geometric model of a component from a geometric model database, and determining at least one orientation parameter value associated with the geometric model of the component. The at least one orientation parameter value is associated with an orientation parameter that defines orientation of the component during additive manufacturing of the component. The method includes performing volumetric analysis of the component based on the at least one orientation parameter value associated with the component using the geometric model of the component. The method also includes computing one or more overheating areas in the component corresponding to the at least one orientation parameter value based on the volumetric analysis of the geometric model of the component, and outputting a multi-dimensional visual representation of the geometric model of the component Indicating one or more overheating areas in the component.
A method of detecting anomalous latencies in communications between components on an integrated circuit (IC) chip. The method includes: (i) monitoring communications between a first component of the IC chip and other components of the IC chip, each communication comprising a command sent from the first component to another component, and a response received by the first component from that other component, the monitoring comprising: measuring the number of communications in each of a series of monitored time windows, and measuring the latency of each communication in the series of monitored time windows; (ii) calculating a maximum tolerable latency for each operational time window of the first component from the number of communications in that operational time window, an available stall time of the first component in that operational time window, and a latency penalty factor for that operational time window; and (iii) determining a measured latency to be anomalous if the measured latency is greater than the maximum tolerable latency.
A method of identifying a cause of an anomalous feature measured from system circuitry on an integrated circuit (IC) chip, the IC chip comprising the system circuitry and monitoring circuitry for monitoring the system circuitry by measuring features of the system circuitry in each window of a series of windows, the method comprising: (i) from a set of windows prior to the anomalous window comprising the anomalous feature, identifying a candidate window set in which to search for the cause of the anomalous feature; (ii) for each of the measured features of the system circuitry: (a) calculating a first feature probability distribution of that measured feature for the candidate window set; (b) calculating a second feature probability distribution of that measured feature for window(s) not in the candidate window set; (c) comparing the first and second feature probability distributions; and (d) identifying that measured feature in the timeframe of the candidate window set as a cause of the anomalous feature if the first and second feature probability distributions differ by more than a threshold value; (iii) iterating steps (i) and (ii) for further candidate window sets from the set of windows prior to the anomalous window; and (iv) outputting a signal indicating those measured feature(s) of step (ii)(d) identified as a cause of the anomalous feature.
A computing system may include an object representation engine and an object incarnation engine. The object representation engine may be configured to define a computer-aided design (CAD) object in a CAD model as a combination of an object boundary comprised of bounding faces that encapsulate the CAD object and a microstructure that defines an internal geometry of the CAD object in a procedural representation. The procedural representation may be a representation of the internal geometry of the CAD object in a non-incarnated form. The object incarnation engine may be configured to incarnate, via the procedural representation of the microstructure, the internal geometry of the CAD object into a geometric representation to perform a CAD operation on the CAD object.
G06F 30/12 - Geometric CAD characterised by design entry means specially adapted for CAD, e.g. graphical user interfaces [GUI] specially adapted for CAD
46.
MACHINE LEARNING-BASED SELECTIVE INCARNATION OF COMPUTER-AIDED DESIGN OBJECTS
A computing system may include an instance identification engine configured to determine a selected subset of pattern instances of a programmatic pattern used to represent a geometry of a computer-aided design (CAD) object, including by identifying a CAD operation to perform on the CAD object; determining a sampled point set in the CAD object applicable to the CAD operation; providing the sampled point set as an input to an inversion machine-learning (ML) model trained to output a given pattern instance of the programmatic pattern for an input point of the CAD object; and determining, as the selected subset, an output set of pattern instances provided by the inversion ML model for the sampled point set. The system may also include an object incarnation engine configured to incarnate a geometry of the selected subset of pattern instances to perform the CAD operation on the CAD object.
G06F 30/27 - Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
An integrated circuit (IC) chip includes system circuitry having system memory, and a master processor and a checker processor configured to operate in lockstep; and monitoring circuitry comprising an internal lockstep monitor, a master tracer and a checker tracer. The internal lockstep monitor is configured to: observe states of internal signals of the master processor and the checker processor, compare corresponding observed states of the master processor and the checker processor, and if the corresponding observed states differ: trigger the master tracer to output stored master trace data recorded from the output of the master processor, and trigger the checker tracer to output stored checker trace data recorded from the output of the checker processor.
A computing system may include a metal stack tuning engine and a tuned metal stack application engine. The metal stack tuning engine may be configured to access an obscured metal stack definition specified for an integrated circuit (IC) manufacture process and tune selected metal stack parameters of the obscured metal stack definition to obtain a tuned metal stack definition. The metal stack tuning engine may do so by generating sampled metal stack definitions, constructing sampled layout geometries from the sampled metal stack definitions, computing parasitic capacitance value sets for the sampled layout geometries, and determining tuned values for the selected metal stack parameters through a curve fitting process. The tuned metal stack application engine may be configured to use the tuned metal stack definition to perform a parasitic capacitance extraction process for an input IC design.
A scan network configured to transport repair information between memories and a controller for a non-volatile storage device comprises: repair registers coupled in parallel to repair information generation circuitry for one of the memories and segment selection devices that divide the repair registers into repair register segments. Each of the segment selection devices comprises: a storage element configured to store a segment selection bit and segment selection bit generation circuitry configured to generate the segment selection bit based on the repair information. Each of the segment selection devices is configurable to include or not include the corresponding repair register segment in a scan path of the scan network in a shift operation based on the segment selection bit.
This application discloses a computing system implementing a design verification tool to perform functional verification on a circuit design describing an electronic device and collect samples of performance data during the functional verification. The computing system can also include a performance visualization tool to generate a profile presentation based on the samples of performance data. The profile presentation, when displayed, can annunciate portions of the circuit design corresponding to at least one performance hotspot. The performance visualization tool can receive a data reduction request based on the performance hotspot annunciated by the profile presentation. The data reduction request can identify a subset of the performance data in the profile presentation. The performance visualization tool can generate a refined profile presentation based, at least in part, on the samples of performance data and the subset of the performance data identified in the data reduction request.
A computer-implemented method includes receiving toolpath data for machining a workpiece with a tool along a toolpath. The tool is comprised by a machine tool that is numerically controlled by a control device. Machine code for the machine tool corresponding to the toolpath data is received. A map linking at least one item of the toolpath data and at least one item of the machine code corresponding to the least one item of the toolpath data is created. At least one first item of the toolpath data and one or more second items of the machine code corresponding to the at least one first item are displayed to a user using the created map. A control device and a machine tool arranged and configured to execute the computer-implemented method are also provided.
G05B 19/402 - Numerical control (NC), i.e. automatically operating machines, in particular machine tools, e.g. in a manufacturing environment, so as to execute positioning, movement or co-ordinated operations by means of programme data in numerical form characterised by control arrangements for positioning, e.g. centring a tool relative to a hole in the workpiece, additional detection means to correct position
G05B 19/408 - Numerical control (NC), i.e. automatically operating machines, in particular machine tools, e.g. in a manufacturing environment, so as to execute positioning, movement or co-ordinated operations by means of programme data in numerical form characterised by data handling or data format, e.g. reading, buffering or conversion of data
G05B 19/409 - Numerical control (NC), i.e. automatically operating machines, in particular machine tools, e.g. in a manufacturing environment, so as to execute positioning, movement or co-ordinated operations by means of programme data in numerical form - characterised by control panel details, by setting parameters
G05B 19/4069 - Simulating machining process on screen
52.
ADDITIVE MANUFACTURING OF MONOLITHIC PRODUCTS THAT INCLUDE BRIDGE STRUCTURES
Methods for computer-aided design, engineering, visualization, or manufacturing (CAx) operations and corresponding systems and computer-readable mediums are disclosed herein. A method includes receiving, by a data processing system, a computer-aided design, engineering, visualization, or manufacturing model of a product to be manufactured. The CAx model comprises a bridge structure and at least two leg structures. The method includes slicing the CAx model into a plurality of layers, wherein each layer in each leg structure has a corresponding layer number in a sequence of layer numbers for that leg structure. The method includes maintaining an association between corresponding layer numbers of each of the leg structures. The method includes manufacturing the product according to the sequence of layer numbers and the associations, including manufacturing at least one layer of each leg structure in turn. Each leg structure completes manufacture at substantially the same time.
A method and system for computer aided design, (e.g., of products and other items), are disclosed herein. The method may include receiving a CAD model having a behavior defined by a plurality of relationships, receiving a user operation to edit a seed feature in the CAD model, and identifying a set of problem relationships from the plurality of relationships, wherein the set of problem relationships prevent implementation of the received user operation to the received CAD model. A category for each relationship in the set of problem relationships is selected. The behavior of the CAD model is reconfigured based on the selected category for each problem relationship by retaining any user-defined relationships, optionally retaining any optional relationships, and ignoring any relaxed relationships. The user operation is then performed according to the reconfigured behavior to produce a modified CAD model.
G06F 30/12 - Geometric CAD characterised by design entry means specially adapted for CAD, e.g. graphical user interfaces [GUI] specially adapted for CAD
G06F 30/17 - Mechanical parametric or variational design
54.
ROLLBACK FOR COMMUNICATION LINK ERROR RECOVERY IN EMULATION
Each of a plurality of reconfigurable hardware modeling circuits in a reconfigurable hardware modeling device comprises: a plurality of communication ports; error monitoring circuitry configured to monitor, while the reconfigurable hardware modeling device is performing an operation for verifying a circuit design, whether data received from the plurality of communication ports contain an error or not, and send out an error signal indicating the monitoring result; and rollback circuitry configured to, if data received by any of the plurality of reconfigurable hardware modeling circuits contain an error, enable the reconfigurable hardware modeling circuit to repeat the operation from a state before the error is received, and if data received by the plurality of reconfigurable hardware modeling circuits contain no error, allow the reconfigurable hardware modeling circuit to continue the operation.
A computing system may include a shadow feature model training engine configured to access a set of integrated circuit (IC) layouts and capacitance values determined for components of the set of IC layouts. The shadow feature model training engine may construct shadow feature training data for the set of IC layouts, including by extracting shadow features for components of the set of IC layouts, combine extracted shadow features and determined capacitance values to form the shadow feature training data, and may further train a machine-learning (ML) model with the shadow feature training data. The computing system may also include a shadow feature application engine configured to extract shadow features for components of an input IC layout and determine capacitance values for the input IC layout via the trained ML model.
G06F 30/398 - Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
G06F 30/27 - Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
G06F 30/392 - Floor-planning or layout, e.g. partitioning or placement
G01R 27/26 - Measuring inductance or capacitance; Measuring quality factor, e.g. by using the resonance method; Measuring loss factor; Measuring dielectric constants
Systems and methods for analyzing a semiconductor layout design around a point of interest (POI) are disclosed. Semiconductor layout designs are a representation of an integrated circuit in terms of planar geometric shapes which make up the components of the integrated circuit, and are used to manufacture the integrated circuit. The layout design may be analyzed using one or more POI-based approaches to determine whether to modify the layout design. In one POI-based approach, set of kernels, tailored to the downstream application, are convolved with a representation of the layout design about or around the POI in order to generate a signature associated with the POI. In turn, the signatures may be analyzed based on the downstream application. Another POI-based approach consists of analyzing geometrical parameters associated with the POI, which may be used during a design stage to identify and modify problem areas in the layout design.
G06F 30/392 - Floor-planning or layout, e.g. partitioning or placement
G06F 30/27 - Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
57.
DUPLICATE CIRCUIT SECTION IDENTIFICATION AND PROCESSING FOR OPTICAL PROXIMITY CORRECTION (OPC) PROCESSES IN ELECTRONIC DESIGN AUTOMATION (EDA) APPLICATIONS
A computing system may include a circuit design access engine configured to access a circuit design. The computing system may also include a duplicate section processing engine configured to partition the circuit design into multiple circuit sections and determine, from among the multiple circuit sections, an identical section set based on duplicate criteria. Circuit sections of the identical section set may satisfy the duplicate criteria with respect to one another. The duplicate section processing engine may further be configured to perform an OPC processing operation on a selected circuit section of the identical section set and apply an OPC result of the performed OPC processing operation for other circuit sections of the identical section set instead of or without performing the OPC processing operation on the other circuit sections of the identical section set.
A circuit comprises scan gating devices inserted between outputs of scan chains and inputs of a test response compactor. The scan gating devices divides the scan chains into groups of scan chains. Each of the scan gating devices operates in either an enabled mode or a disenabled mode based on a first signal. A scan gating device operating in the enabled mode blocks, blocks only at some clock cycles, or does not block a portion of a test response of a test pattern captured by and outputted from a scan chain in the associated scan chain group based on a second signal. Scan gating devices operating in the disenabled mode do not block, or based on a third signal, either block or do not block, a portion of the test response captured by and outputted from all scan chains in each of the associated scan chain groups.
A system and method for scheduling optical proximity correction (OPC) or other resolution enhancement technique (RET) operations on a layout design is disclosed. A layout design is divided into a plurality of regions, such as a plurality of tiles. OPC is performed on the plurality of tiles in order to generate a modified layout design. Performing OPC on the plurality of tiles may be time consuming. In order to more efficiently distribute the processing of OPC, estimates of OPC processing times for the plurality of tiles is performed. The estimate of the OPC processing time for a respective tile may be based on one or both of analysis of: analysis of the respective tile; or analysis of tile(s) that neighbor the respective tile. Based on the estimates, tiles that have a longer estimated processing fore tiles that have a shorter estimated processing time, thereby potentially resulting in more efficient OPC processing.
A computing system may include a geometry access engine configured to access geometries associated with a topology optimization process, including an original geometry that represents a design space upon which the topology optimization process applies to as well as a topology optimized geometry that represents an output of the topology optimization process performed for the original geometry. The system may also include geometry processing engine configured to generate a final geometry from the topology optimized geometry, including by conforming the topology optimized geometry to the original geometry at portions of the topology optimized geometry that correspond to fixed regions of the original geometry as well as smoothing the topology optimized geometry at portions that correspond to non-fixed regions of the original geometry.
A computing system may include a design access engine configured to access a digital design of a part designed for construction through an additive manufacturing process. The computing system may also include a detachable support structure engine configured to insert, into the digital design, a support structure configured to support construction of a surface of the part. The inserted support structure may include a shape-memory element configured to be in a diminished shape during the additive manufacturing process and expand into an expanded shape after the additive manufacturing process ends as well as an element enclosure attached to the surface of the part and configured to hold the shape-memory element in the diminished shape and break from the part as the shape-memory element expands into the expanded shape.
A computing system may include an access engine and a defect detection engine. The access engine may be configured to access a slice contour of a given layer of a 3-dimensional (3D) object designed for manufacture through an additive manufacturing process and obtain hatch tracking for the slice contour, the hatch tracking representative of an energy path to melt metal powder for constructing the given layer through the additive manufacturing process. The defect detection engine may be configured to construct, from the slice contour, an as-built image for the given layer by rendering the hatch tracking in the slice contour; construct, from the slice contour, an idealized image for the given layer; and identify defects in the given layer via image analysis between the as-built image and the idealized image.
B29C 64/393 - Data acquisition or data processing for additive manufacturing for controlling or regulating additive manufacturing processes
B29C 64/153 - Processes of additive manufacturing using only solid materials using layers of powder being selectively joined, e.g. by selective laser sintering or melting
A method and system for classifying components in a product data management (PDM) environment is disclosed. A method includes obtaining data files having information associated with a component to be classified in a PDM database. Each data file includes different types of information associated with the component. A series of predictions indicating a probability of the component belonging to one or more categories is computed based on each type of information associated with the component using one or more artificial intelligence models. An overall probability of the component belonging to the one or more categories is computed based on each of the series of predictions. The component is classified in at least one category of the one or more categories based on the computed probability of the component belonging to the one or more categories. The category associated with the classified component is output on a graphical user interface.
A computing system may include a design access engine and a design processing engine. The design access engine may be configured to access an object design to be constructed through additive manufacturing. The design processing engine may be configured to represent the object design as a combination of coarse geometric elements and high-resolution lattice elements and process the object design based on both the coarse geometric elements and the high-resolution lattice elements. Processing of the object design may include generation of lattice infills, lattice simulations, or a combination of both.
A client computing system may include a model visualization engine and a model interaction engine. The model visualization system may be configured to access, from a server computing system remote to the client computing system, visualization data to display a computer-aided design (CAD) model in a viewing window of the client computing system. The model interaction engine may be configured to query the server computing system for interaction data of a selected portion of the CAD model, but not other portions of the CAD model, wherein the interaction data comprises CAD model data that supports user interaction with the selected portion of the CAD model.
G06F 30/12 - Geometric CAD characterised by design entry means specially adapted for CAD, e.g. graphical user interfaces [GUI] specially adapted for CAD
66.
SYSTEM AND METHOD FOR MULTI-USER SPATIAL IMPACT ANALYSIS AND MANAGEMENT
Methods for CAD operations and corresponding systems and computer-readable mediums are disclosed herein. A method includes accessing (302), by a data processing system (202, 500), a computer-aided design, engineering, visualization, or manufacturing (CAx) model (208) of a part or assembly to be manufactured. The method includes storing (304) a plurality of impact definitions (204) corresponding to the CAx model (208). The method includes receiving (306), from a first client system (220A), an indication of a first spatial area of the CAx model (208) and, from a second client system (220B), an indication of a second spatial area of the CAx model (208). The method includes receiving (308) a notification of a save event created by the first client system (220A) for the first spatial area. The method includes performing impact detection (310) according to the save event, the first spatial area, and the impact definitions (204) to detect a potential impact. The method includes sending (312) an impact notification to the first client system (220A) and the second client system (220B).
Systems and methods for repairing a memory. A method includes performing a repair analysis of the embedded memories to produce repair information. The method includes storing the repair information in the registers, where the registers are organized into groups having chains of identical length. The method includes performing collision detection between the repair information in each of the groups. The method includes merging the repair information in each of the groups. The method includes repairing the embedded memories using the merged repair information.
This application discloses a computing system implementing a line balancing tool to generate a structured bill of materials for a wire harness based on a harness design and available fabrication processes. The computing system can decompose the structured bill of materials into tasks and assign the tasks to workstations in a production line configured to manufacture the wire harness. The computing system can determine dependencies between a plurality of the tasks and verify the tasks assigned to the workstation conform to the dependencies between the plurality of the tasks. The dependencies can indicate an order for performance of the operations associated with the tasks. The computing system can identify unassigned tasks capable of assignment to one or more of the workstations and determine which of the workstations the unassigned assembly tasks, if assigned, would conform with the dependencies between the plurality of the assembly tasks.
G05B 19/418 - Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control (DNC), flexible manufacturing systems (FMS), integrated manufacturing systems (IMS), computer integrated manufacturing (CIM)
69.
Device and Method for Configuring a Technical System
Device and method for configuring a technical system are disclosed, wherein the method includes generating a configuration model from configuration criteria for the technical system and the configuration model represents the technical system as an information model, where generating the configuration model includes validating the configuration criteria based on constraints associated with the technical system and identifying a maximum satisfiable rule set for the validated configuration criteria, the maximum satisfiable rule set being identified by determining a minimum number of conflicting rules to be removed to resolve conflicts with the validated configuration criteria, where the minimum number of conflicting rules being determined for rules ranked below the threshold severity; and by removing at least one of the minimum number of conflicting rules to generate the maximum satisfiable rule set.
Methods for CAD operations and corresponding systems and computer-readable mediums are disclosed herein. A method can be performed by a data processing system and includes receiving a model of a part to be manufactured, wherein the model includes a first partial volume connected via a gap to a second partial volume. The method includes receiving a wall-distance value and applying the wall-distance value to the first partial volume of the model to define an initial volume having initial-volume boundaries. The method includes refining the initial-volume boundaries, generating at least one new surface in the model, and storing a modified model of the part to be manufactured, including the new surface.
A computing system implementing a design verification system can elaborate a mixed-signal circuit design having a complex sandwich hierarchy using a standard digital solver and a standard analog solver, as opposed to a tightly coupled custom elaboration engine. The design verification system can parse the mixed-signal circuit design to identify analog design blocks and flatten the analog design blocks into the structural proxy blocks having parameter connections to digital design blocks in the mixed-signal circuit design. The design verification system can replace an analog portion of the mixed-signal circuit design with the structural proxy blocks and elaborate the structural proxy blocks and digital design blocks associated with a digital portion of the mixed-signal circuit design. The design verification system can elaborate the analog portion of the mixed-signal design and simulate the elaborated analog portion with an analog simulator and the elaborated digital portion with a digital simulator.
Systems, methods, logic, and devices may support machine learning-based anomaly detections for embedded software applications. In a learning phase, an anomaly model training engine may construct an anomaly detection model, and the anomaly detection model configured to provide a determination of whether the embedded software application exhibits abnormal behavior based on activity measure and application parameter inputs. In a run-time phase, an anomaly detection engine may sample the embedded software application to obtain an activity measure and application parameters during the run-time execution and provide, as inputs to the anomaly detection model, the activity measure and the application parameters sampled during the run-time execution. The anomaly detection engine may further determine whether the embedded software application exhibits abnormal behavior based on an output from the anomaly detection model for the provided inputs.
G06F 21/52 - Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems during program execution, e.g. stack integrity, buffer overflow or preventing unwanted data erasure
A design and manufacturing system includes a multi-axis machine tool including a cutting head able to support a plurality of available tools and a part support, the cutting head and part support fully controllable in at least two axes, a design system operable using a computer to generate a 3-D model of a part to be manufactured, and a machine learning model operable using the computer to analyze the part to be manufactured to identify features and develop a manufacturing plan at least partially based on the multi-axis machine tool and the plurality of available tools, the manufacturing plan including a type of tool used for each feature, a feed-rate for each type of tool for each feature, and a speed of the tool for each type of tool for each feature.
G05B 19/4099 - Surface or curve machining, making 3D objects, e.g. desktop manufacturing
G05B 19/408 - Numerical control (NC), i.e. automatically operating machines, in particular machine tools, e.g. in a manufacturing environment, so as to execute positioning, movement or co-ordinated operations by means of programme data in numerical form characterised by data handling or data format, e.g. reading, buffering or conversion of data
G05B 17/02 - Systems involving the use of models or simulators of said systems electric
G05B 13/04 - Adaptive control systems, i.e. systems automatically adjusting themselves to have a performance which is optimum according to some preassigned criterion electric involving the use of models or simulators
74.
Programmable test compactor for improving defect determination
A circuit comprises: scan chains comprising scan cells, the scan chains configured to shift in test patterns, apply the test patterns to the circuit, capture test responses of the circuit, and shift out the test responses; a decompressor configured to decompress compressed test patterns into the test patterns; a test response compactor configured to compact the test responses; and shuffler circuitry inserted between outputs of the scan chains and inputs of the test response compactor, the shuffler circuitry comprising state elements configured to delay output signals from some of the scan chains for one or more clock cycles based on a control signal, the control signal varying with the test patterns.
A computer executable system that runs symbolic simulation with formal X-analysis along with logic simulation to determine if Xs produced in logic simulation are real or not. Simulated values in logic simulation shown to be incorrect are rectified using formal analysis results to produce X-accurate simulation results that match real hardware.
Systems, methods, logic, and devices may support computer-aided design (CAD) based sensor design and analysis. In some examples, a system may include a sensor design engine and a sensor analysis engine. The sensor design engine may be configured to access a CAD model of a part and define a sensor in the CAD model as a component of the part, including by specifying: design parameters for the sensor, manufacturing constraints for physical construction of the part including the sensor; and a signal type produced by the sensor. The sensor analysis engine may be configured to perform a simulation analysis on the part defined in the CAD model to include the sensor, including digitally simulating operation of the sensor as a component of the part.
A single radio equipment test device includes a control unit for testing a plurality of antennas, (e.g., an antenna array). The control unit includes a first interface to operatively couple the control unit to an antenna under test, (e.g., arranged in a test chamber). The control unit further includes a second interface to operatively couple the control unit to a reference antenna, (e.g., also arranged in the test chamber). The control unit is configured to control and/or monitor the antenna under test and the reference antenna.
This application discloses a computing system to identify structures of an integrated circuit capable of being fabricated utilizing a lithographic mask described by mask layout data and to generate process windows for the identified structures based, at least in part, on the mask layout data and a failure definition for the identified structures. The computing system utilizes process windows for the identified structures to determine failure rates for the identified structures based on a distribution of the manufacturing parameters. The computing system determines frequency of occurrences for the identified structures from the mask layout data and generates a die yield metric for the integrated circuit by aggregating the failure rates for the identified structures based on the frequency of occurrences for the identified structures in the integrated circuit. These increases in yield of the integrated circuit allow manufacturers to produce more units per fixed processing cost of the wafer.
G06F 30/398 - Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
G03F 1/36 - Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
G06F 119/18 - Manufacturability analysis or optimisation for manufacturability
G06F 119/22 - Yield analysis or yield optimisation
79.
ADAPTIVE USER INTERFACES FOR COMPUTER-AIDED TECHNOLOGY APPLICATIONS
A system may support adaptive user interfaces (Us) for computer-aided technology (CAx) applications. The system may include a CAx tracking engine configured to track command usage of a computer-aided technology (CAx) application to obtain command usage data for the CAx application and a CAx training engine configured to train a machine learning model with the command usage data. The system may also include a CAx adaptive UI engine configured to obtain real-time command usage by a user of the CAx application; and apply the machine learning model to adaptively transform a UI of the CAx application, including by inputting the real-time command usage of the CAx application to the machine learning model to determine a predicted command based on the real-time command usage and dynamically updating a selected sub-section of the UI of the CAx application to present the predicted command to the user.
G06F 30/27 - Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
G06F 30/12 - Geometric CAD characterised by design entry means specially adapted for CAD, e.g. graphical user interfaces [GUI] specially adapted for CAD
This application discloses a computing system implementing an automatic test pattern generation tool to convert a transistor-level model of a library cell describing a digital circuit into a switch-level model of the library cell, generate test patterns configured to enable detection of target defects injected into the switch-level model of the library cell, and bifurcate the test patterns into a first subset of the test patterns and a second set of the test patterns based on detection types for the target defects enabled by the test patterns. The computing system can implement a cell model generation tool to perform an analog simulation of the transistor-level model of the library cell using the second subset of the test patterns to verify that they enable detection of target defects, while skipping performance of the analog simulation of the transistor-level model of the library cell using the first subset of the test patterns.
G01R 31/00 - Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
This application discloses a distributed computing system implementing multiple participating processes to separately compile different portions of a circuit design describing an electronic device over multiple phases. The distributed computing system can implement a management process to utilize a synchronization protocol to identify operational states of the participating processes during compilation of the different portions of the circuit design, maintain the operational states of the participating processes, and separately determine when the participating processes have completed compilation of the circuit design portions for one of the phases based on the operational states of the participating processes. The management process can determine to have the participating processes synchronously transition to another one of the phases or that the participating processes have compiled the circuit design into a compiled design corresponding to the circuit design, and deploy the compiled design in an emulator for verification of a functionality of the electronic device.
Systems and methods for calculating a printed area metric indicative of stochastic variations of the lithographic process are disclosed. Lithography is a process that uses light to transfer a geometric pattern from a photomask, based on a layout design, to a resist on a substrate. The lithographic process is subject to random stochastic phenomena, with the resulting stochastic randomness potentially becoming a major challenge. To characterize the stochastic phenomena, a printed area metric may be generated analytically (rather than via simulations) and comprise one or more defined moments for a printed area distribution associated with the printed area that are indicative of one or more aspects associated with printing. For example, the printed area metric may be indicative of the likelihood of printing within the printed area or the variance of printing within the printed area due to stochastic randomness in one or both of exposure or resist process.
Systems and methods for emulate or prototyping of hardware, such as memory, are disclosed. A memory compiler may receive information, such as system calls, indicative of one or more aspects of latency. Responsive to the information, the memory compiler may create infrastructure, such as pipelines and FIFOs, based on the aspects of latency, for emulation or prototyping of the hardware. Using the created infrastructure may improve emulation compile speed, such as by creating a pipeline-based cache structure, and may improve emulation runtime speed, such as by utilizing earlier unused model clocks to fetch data from host sooner.
Systems and methods for semi-supervised hotspot detection and classification are disclosed. Hotspots comprise layout pattern that induce printability issues in the lithography process. To detect hotspots, one feature vector, such as an n-dimensional feature vector, is compared with other feature vector(s). The comparison between feature vectors may comprise determining a distance, such as a Euclidian distance, in order to determine closeness between the feature vectors. For example, a training dataset, that includes known hotspots and known non-hotspots, is used in order to determine threshold(s). In particular, for one, some, or all of the known hotspots in the training dataset, a distance to a closest known hotspot and a closest known non-hotspot may be calculated to determine the threshold(s). In turn, a layout under examination, which includes indeterminate spots, may be analyzed using the known hotspots in the training dataset and the threshold(s) to identify the indeterminate spots as potential hotspots.
This application discloses a computing system implementing an automatic test pattern generation tool to perform scan chain diagnosis-driven compaction setting. The computing system can perform fault simulation on scan chains in a circuit design describing an integrated circuit, which loads test patterns to the simulated scan chains and unloads test responses from the simulated scan chains. The computing system can determine locations of sensitive bits and locations of unknown bits in each of the scan chains based on the test responses from the simulated scan chains, and generate a configuration for a compactor in the integrated circuit based, at least in part, on the locations of the sensitive bits and the locations of the unknown bits in each of the scan chains, wherein the compactor is configured to compact test responses from the scan chains in the integrated circuit based on the configuration.
A computing system can implement a circuit verification tool to perform scaled sampling of parameter values in a foundry model describing parameter variations for a manufacturing process capable of fabricating an integrated circuit described in a circuit design. The computing system can simulate the circuit design with the scaled samples of the parameter values, and build a geometric model to describe a response of the circuit design to the scaled samples of the parameter values during the simulation. The geometric model can include one or more failure regions corresponding to geometric descriptions for failures of the circuit design to meet a specification during simulation with the scaled samples of the parameter values. The computing system can estimate a yield for an output of the integrated circuit described by the circuit design based on the failure regions in the geometric model.
Methods and systems are disclosed for a computer aided design system for designing multilevel lattice structures. A coarse lattice module defines a coarse lattice of balls connected by beams within a first boundary. A fine lattice module defines a fine lattice of balls connected by beams within a second boundary. The coarse lattice and the fine lattice have intersecting regions. A trimming module constructs a multilevel lattice structure according to a trimming operation based on the intersecting regions.
A circuit comprises a plurality of scan chains. The plurality of scan chains comprises bidirectional scan cells. Each of the bidirectional scan cells comprises two serial input-output ports serving as either a serial data input port or a serial data output port based on a control signal. Each of the plurality of scan chains is configured to perform a shift operation in either a first direction or a second direction based on the control signal. The first direction is opposite to the second direction.
This application discloses a server to transmit an embedded application to a remote gateway device. The embedded application, when executed, prompts the remote gateway device to generate application messages including information associated with the execution of the embedded application by the remote gateway device. The server is configured to track the execution of the embedded application in the remote gateway device to determine operational states of the embedded application based, at least in part, on the application messages received from the remote gateway device. The server is configured to generate a parameter message for transmission to the remote gateway device based, at least in part, on the operational states of the embedded application deployed in the remote gateway device. The parameter message is configured to prompt the remote gateway device to transmit an application parameter associated with the execution of the embedded application.
A system and method for software checkpoint-restoration between distinctly compiled executables is disclosed. A first compiled version of the software, such as Version A, is executed. After which, checkpointing is performed in order to generate a checkpoint image. After checkpointing, restarting execution is performed with at least some of a second compiled version of the software, such as Version B, being executed using a switching function that is configured to switch execution upon restart at least partly to the second compiled version of the software. In this way, different executable versions may be used during the restart than during the initial execution, such as an unoptimized build during the restart versus an optimized build during the initial execution, so that software testing and/or debugging may be performed more efficiently.
A computing system may include an assembly access engine configured to access a computer-aided design (CAD) assembly that digitally represents a product component that includes multiple parts. The computing system may also include a part determination engine configured to determine a recommended part for the CAD assembly, including by providing the CAD assembly as an input to a machine-learning (ML) model trained with assembly structure data of CAD assemblies of a common product type as the CAD assembly, generating a candidate part set through the ML model, filtering the candidate part set based on physical and cost characteristics of the different candidate parts of the candidate part set, and identifying the recommended part from the filtered candidate part set. The part recommendation engine may also be configured to insert the recommended part into the CAD assembly and provide the CAD assembly in support of physical manufacture.
A method aligns a first panoramic image and a second panoramic image in a navigation procedure. The method includes using a computer vision algorithm for extracting features that are present in the panoramic images and use the extracted features to prepare a first feature vector for the first panoramic image and a second feature vector for the second panoramic image. The first and the second feature vectors are compared and matches in both the first and the second feature vectors that are above a determined threshold are identified. For the identified matches in each of the first and the second feature vectors for each of the two images, the perspective angle between a reference point of the respective image and the features according to the identified matches are determined. Finally, a difference between the determined perspective angles for a part of the identified matches in the panoramic images is determined.
G06V 10/44 - Local feature extraction by analysis of parts of the pattern, e.g. by detecting edges, contours, loops, corners, strokes or intersections; Connectivity analysis, e.g. of connected components
G06T 3/40 - Scaling of a whole image or part thereof
93.
Multi-capture at-speed scan test based on a slow clock signal
A circuit comprises a plurality of clock control devices. Each of the clock control devices is configured to generate a scan test clock signal for a particular clock domain in the circuit and comprises circuitry configured to select clock pulses of a fast clock signal as scan capture clock pulses for the particular clock domain based on a particular clock pulse of a slow clock signal and a scan enable signal. The order and spacing between the groups of the scan capture clock pulses for different clock domains correspond to the order and spacing of the clock pulses of the slow clock signal.
Various aspects of the disclosed technology relate to predicting physical failure analysis-oriented diagnosis resolution. Fault simulation is performed on a circuit design to derive test responses for a set of faults and test patterns for testing circuits fabricated according to the circuit design. The set of faults is grouped into groups of equivalent faults based on the test responses. A group of equivalent faults consists of faults having the same test responses for all test patterns in the test patterns that can activate the faults. A PFA (physical failure analysis)-oriented diagnosis resolution evaluation value is computed by averaging weighted sizes of the groups of equivalent faults. The weight factors for the groups of equivalent faults with sizes greater than a certain number being smaller than the weight factors for rest of the groups of equivalent faults.
G06F 30/333 - Design for testability [DFT], e.g. scan chain or built-in self-test [BIST]
G06F 30/398 - Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
G06F 30/3308 - Design verification, e.g. functional simulation or model checking using simulation
G06F 30/367 - Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
A switching activity report of simulated switching activities of a semiconductor circuit is accessed. A plurality of glitch bottleneck ratios corresponding to a plurality of pins in the semiconductor circuit are determined, comprising by: setting an initial bottleneck ratio on a leaf output pin; and backward traversing the semiconductor circuit to determine a plurality of glitch bottleneck ratios of pins in a fan-in cone of the leaf output pin.
A plurality of total glitch powers associated with the plurality of pins is determined, a total glitch power of the plurality of total glitch powers being determined based on a glitch bottleneck ratio and a glitch power of a corresponding pin. One or more critical bottleneck pins among the plurality of pins are identified based on the plurality of total glitch powers. One or more gates associated with the one or more critical bottleneck pins are adjusted to reduce corresponding one or more total glitch powers of the one or more gates.
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
G01R 31/00 - Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
96.
Integrated simulator and analysis and optimization engine
A signoff process includes: accessing circuit information of a circuit; performing, using an analysis and optimization engine, power analysis and optimization on the circuit to generate an optimized circuit, the power analysis and optimization being performed using an input pattern; performing, using a simulator, a simulation on at least a portion of an optimized circuit, the simulation being performed using the input pattern used in the power analysis and optimization; and outputting a simulation result to the analysis and optimization engine; wherein the analysis and optimization engine and the simulator are integrated.
A circuit design in a hierarchical description is analyzed. The analysis comprises identifying electrical properties of circuit blocks in the circuit design. Circuit components of the circuit design are associated with geometric elements of a layout design. Then instances of each of the circuit blocks are classified into groups of instances based on the electrical properties. Rule checking is performed on one or more groups in the groups of instances for each of the circuit blocks by analyzing geometric elements associate with components of one instance for each of the one or more groups.
A computing system implementing an optical proximity correction model verification tool can determine parameters for design patterns associated with an integrated circuit described in a layer file, and determine differences between the design patterns and calibration patterns utilized to calibrate an optical proximity correction (OPC) model configured to predict a printed image on a substrate corresponding to a layout design for the integrated circuit by determining distances between the determined parameters for the design patterns and parameters for the calibration patterns. The computing system can classify the design patterns with a modeling capability of the OPC model for the design patterns based on the differences between design patterns and the calibration patterns and possibly error rates of the OPC model associated with the calibration patterns or lithographic difficulty of the calibration patterns. The computing system can modify the layer file to include the classifications of the design patterns.
A system for testing a circuit comprises scan chains, a controller configured to generate a bit-inverting signal based on child test pattern information, and bit-inverting circuitry coupled to the controller and configured to invert bits of a parent test pattern associated with a plurality of shift clock cycles based on the bit-inverting signal to generate a child test pattern during a shift operation. Here, the plurality of shift clock cycles for bit inverting occur every m shift clock cycles, and the child test pattern information comprises information of m and location of the plurality of shift clock cycles in the shift operation.
A system may include a set of compute engines. The compute engines may be configured to perform electronic design automation (EDA) operations on a hierarchical dataset representative of an integrated circuit (IC) design. The system may also include a dynamic resource balancing engine configured to allocate computing resources to the set of compute engines and reallocate a particular computing resource allocated to a first compute engine based on an operation priority of an EDA operation performed by a second compute engine, an idle indicator for the first compute engine, or a combination of both.
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