Various aspects of the present disclosed technology relate to techniques for classifying layout patterns. First, a set of density feature vectors for a set of layout regions in the layout design are extracted using a set of rings. Each component of a density feature vector in the set of density feature vectors corresponds to a ring in the set of rings. The set of rings do not overlap with each other and cover a whole area of a circle when being placed together. Next, a machine learning-based clustering process is performed to separate layout features in the set of layout regions into clusters of layout features based on the set of density feature vectors. Each of the clusters of layout features may be further divided into subclusters based on one or more properties.
G06F 30/27 - Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
G06F 30/392 - Floor-planning or layout, e.g. partitioning or placement
A memory-testing circuit in a circuit comprises: a test controller; a memory data source selection device configured to select input data for a write port of the memory from test data outputted from the test controller and data from an output of the memory; and a memory address source selection device configured to select an address for an address port of the memory from an address outputted from the test controller and one of one or more preset addresses of the memory. The one or more preset addresses correspond to one or more preserved locations of the memory configured to temporarily store data for one or more locations of the memory to be tested.
A computing system may include an access engine and a heat-aware toolpath engine. The access engine may be configured to access a slice of a 3-dimensional (3D) computer-aided design (CAD) object, wherein the 3D CAD object represents a physical part and wherein the slice represents a physical layer for 3D printing of the physical part. The heat-aware toolpath engine may be configured to generate a layer toolpath to control the 3D printing of the physical layer, including by partitioning the slice into zones and determining a zone order, based on a heat-aware criterion, for the layer toolpath to traverse for the 3D printing of the physical layer. The heat-aware toolpath engine may also be configured to provide the layer toolpath to support the 3D printing of the physical part.
A method of protocol processing including a main program code that has one or more code segments and instructions for processing different protocol elements of a data packet stream of a transport protocol is disclosed herein. The method includes assigning a latency requirement and/or bandwidth requirement to one or more of the code segments of the main program code; and compiling each of the code segments according to the assigned latency and/or bandwidth requirement into a respective target code for executing each of the target codes by different processors.
A computer-implemented method of editing, at a local client device, an engineering design (CAD model), hosted on a remote server is described. The local client device and the remote server communicate over a communications network and are remote from each other. The remote server configures an operation within a CAD model based on user input during an edit of the CAD model involving a drag. This results in a subset of the CAD model and the solving instructions required to perform the user update being generated and sent as a data package comprising the subset of the CAD model and the solving instructions to the local client device. The CAD model and any associated algorithms stored on the remote server are not communicated to the local client device.
G06F 30/12 - Geometric CAD characterised by design entry means specially adapted for CAD, e.g. graphical user interfaces [GUI] specially adapted for CAD
G06F 30/17 - Mechanical parametric or variational design
G06F 111/02 - CAD in a network environment, e.g. collaborative CAD or distributed simulation
A database stores a set of items, with each item having technical attributes, and with each item representing a module that can be used in an engineering project of a first user, u1. A feature encoder embeds each item based on its technical attributes into a low-dimensional vector space. Then, in a second step, a graph neural network pools over these item embeddings to compute an updated user embedding for the first user A decoder mapping then addresses the recommendation task by outputting recommendation scores for each item. That means, heuristically speaking, that the method and system lift the recommendation task to the level of technical attributes to overcome the sparsity problem caused by item sets that are not overlapping between user groups. Thus, when matching similar users, the method does not rely on users configuring exactly the same modules but rather on configured modules that are similar from a technical point of view.
G05B 13/02 - Adaptive control systems, i.e. systems automatically adjusting themselves to have a performance which is optimum according to some preassigned criterion electric
7.
METHOD OF MODELLING ENGINEERING DESIGN COMPONENTS WITH PATTERNS AND CONSTRAINTS
A computer-implemented method of modelling engineering design components in a Computer-Aided Design (CAD) system is disclosed, wherein an engineering design component includes a feature having at least three occurrences of a shape element arranged in a regular pattern is described. The method is split into three stages: definition of a core set of behavioral characteristics; definition of an optional set of behavioral characteristics; and a hierarchical implementation of the optional characteristics by solving optional constraints after constraints corresponding to the core behavioral characteristics have been solved.
G06F 30/12 - Geometric CAD characterised by design entry means specially adapted for CAD, e.g. graphical user interfaces [GUI] specially adapted for CAD
A computing system may include a constraint learning engine and a constraint generation engine. The constraint learning engine may be configured to access a computer-aided design (CAD) assembly comprising multiple CAD parts and generate a representation graph of the CAD assembly, determine constraints in the CAD assembly, wherein the constraints limit a degree of movement between geometric faces of different CAD parts in the CAD assembly, insert constraint edges into the representation graph that represent the determined constraints; and provide the representation graph as training data to train a machine-learning model. The constraint generation engine may be configured to generate constraints for a different CAD assembly by applying the machine-learning model for the different CAD assembly.
G06F 30/27 - Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
Systems and methods for simulation and testing of multiple virtual electronic control units (VECUs). A method (1000) includes executing, by one or more computer systems (101), a first VECU (502). The method includes executing a virtual bus (510), the virtual bus (510) associated with the first VECU (502). The method includes executing at least one second VECU. The method includes simulating a multiple-VECU system by managing communications, using the virtual bus (510), between the first VECU (502) and the at least one second VECU.
H04L 43/20 - Arrangements for monitoring or testing data switching networks the monitoring system or the monitored elements being virtualised, abstracted or software-defined entities, e.g. SDN or NFV
A method and system for generating a geometric component in a computer-aided design (CAD) environment using machine learning models is provided. A computer-implemented method for generating a geometric component in a CAD environment includes determining a geometric operation to be performed on at least one geometric component in the CAD environment based on a CAD command selected by a user. The method also includes determining one or more candidate groups including one or more candidates in the geometric component suitable for performing the geometric operation using one or more trained machine learning models. The method also includes identifying at least one candidate group from the one or more candidate groups on which the geometric operation is to be performed. The method also includes performing the geometric operation on the one or more candidates in the identified candidate group.
G06F 30/27 - Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
An address-skipping trim search performed by a memory built-in self-test system comprises: perform memory read operations on one memory bank to determine whether it fails to correctly sense values of stored data based on a reference trim value for a previous memory bank; if the present memory bank fails, perform memory read operations to search for a new reference trim value for the present memory bank; or otherwise, treat the present reference trim value as the one for the present memory bank and proceed to testing a next memory bank. The range for searching for the new reference trim value can be limited by the present reference trim value.
G11C 29/02 - Detection or location of defective auxiliary circuits, e.g. defective refresh counters
G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
12.
HEAT-AWARE TOOLPATH REORDERING FOR 3D PRINTING OF PHYSICAL PARTS
A computing system may include an access engine and a toolpath reordering engine. The access engine may be configured to access an original layer toolpath for slice of a 3D CAD object as well as a heat criticality measure for the original layer toolpath. The heat criticality measure may specify a heat impact for different points on the multiple toolpath segments of the original layer toolpath for the 3D printing of the physical part using the original layer toolpath. The toolpath reordering engine may be configured to reorder the multiple toolpath segments into a modified layer toolpath, and the modified layer toolpath may have a heat criticality measure with a lesser heat impact on the physical part than the heat criticality measure for the original layer toolpath.
A computing system may include a hotspot processing engine and a hotspot prediction engine. The hotspot processing engine may be configured to access an input data set of hotspot locations on manufactured circuits of a circuit design, correlate the hotspot locations to layout data for the circuit design, and extract fragment feature vectors for the hotspot locations. The hotspot processing engine may further be configured to process the fragment feature vectors such that hotspot fragment feature vectors are a threshold percentage of the total number of feature vectors in the fragment feature vectors and provide the processed fragment feature vectors as a training set for training a machine-learning model. The hotspot prediction engine may be configured to apply the machine-learning model to characterize locations of the circuit design as a hotspot location or a non-hotspot location.
G06F 30/398 - Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
G06F 30/27 - Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
14.
METHOD OF RENDERING A TWO-DIMENSIONAL IMAGE TO A DESIGNER
A computer-implemented method of rendering, to a designer, a two-dimensional image of an assembly of part instances in a three-dimensional assembly space within a computer-aided design (CAD) system utilizing double precision to describe part assemblies is described. Such assemblies are considered to be distant from a nominal observer. A viewport on a two-dimensional image plane is defined, and a combined transform is defined in quadruple precision to enable the generation of clipping lines and/or clipping points. The clipping lines and clipping points clipping the faces and edges of the part instance in the assembly to the portion of the assembly that lies within the viewport.
A method of monitoring messages from a sensor using an integrated circuit is provided. The messages include data measured by that sensor. The method includes reading a first message from interconnect circuitry of the integrated circuit. The interconnect circuitry connects the sensor to one or more core devices configured to process the messages. A first hash value is calculated for the first message. The first hash value is compared to one or more prior hash values stored in a hash store. Each prior hash value of the one or more prior hash values corresponds to a message that was read from the interconnect circuitry prior to the first message. A corrective action is performed when a difference between the first hash value and at least one of the prior hash values stored in the hash store is below a predetermined threshold.
A method is provided for generating test data for testing radio equipment. The method includes: determining, by a test apparatus, one or more beam identifiers; selecting, by the test apparatus, based on the one or more beam identifiers, one or more radio channel models; receiving, by the test apparatus, a baseband signal representing I/Q data of one or more beamforming antennas; processing, by the test apparatus, the baseband signal representing I/Q data according to the selected radio channel model; and transmitting, by the test apparatus, the processed baseband signal representing I/Q data to a radio equipment under test.
H04B 7/06 - Diversity systems; Multi-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station
H04B 7/08 - Diversity systems; Multi-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the receiving station
A computing system may include an upgrade access engine configured to access a database upgrade to perform for a production database. The computing system may also include a database upgrade engine configured to generate multiple clones of the production database, including a production clone and a delta clone with instance data removed. The database upgrade engine may perform the database upgrade on the production clone, track changes to the production database, and push the tracked changes to the delta clone. After the database upgrade on the production clone completes, the database upgrade engine may perform the database upgrade on the delta clone, push upgraded data of the delta clone to the upgraded production clone, and set the upgraded production clone as an upgraded version of the production database.
G06F 16/21 - Design, administration or maintenance of databases
G06F 16/27 - Replication, distribution or synchronisation of data between databases or within a distributed database system; Distributed database system architectures therefor
The present invention discloses a method and a system for determining an assembling risk for an electronic component to be mounted to a printed circuit board, said method comprising the steps of: providing a component library comprising a number of electronic components and its specific component identifier wherein said component identifier comprises an identifier string of letters and numbers thereby providing an information for a number of physical attributes of the electronic component; providing an evaluation scheme for each of the number of physical attributes; selecting an electronic component from the component library and evaluating each of the number of physical attributes; determining for each of the number of physical attributes the intermediate risk value and calculating from the intermediate risk values a final risk score; and determining the assembling risk associated with the final risk score by comparing the final risk'score against a pre-defined risk scale.
A computing system may include a hyperspace generation engine and a hyperspace processing engine. The hyperspace generation engine may be configured to access a feature vector set, and feature vectors in the feature vector set may represent values for multiple parameters of data points in a dataset. The hyperspace generation engine may further be configured to perform a principal component analysis on the feature vector set and quantize the principal component space into a hyperspace comprised of hyperboxes. The hyperspace processing engine may be configured to process the dataset according to a mapping of the feature vector set into the hyperboxes of the hyperspace.
A method and system for trimming intersecting bodies of a geometric model in a computer-aided design environment is disclosed. In one embodiment, a method includes determining a plurality of bodies of the geometric model intersecting with each other. The method includes computing volume of one or more intersecting bodies in the geometric model to be trimmed from the geometric model. Also, the method includes determining a trim offset value for at least one intersecting body in the geometric model and recomputing the volume of the at least one intersecting body in the geometric model which is to be trimmed from the geometric model based on the trim offset value. Moreover, the method includes generating a modified geometric model by performing a trim operation on the volume of the one or more intersecting bodies of the geometric model.
G06F 30/17 - Mechanical parametric or variational design
G06F 30/27 - Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
A computer-implemented method of indexing a hierarchical data structure or product structure is disclosed. For a product structure including a product and a plurality of items associated with the product, each item shares a parent-child relationship with at least one other item or the product. The method includes generating a packed configuration-independent index of the product structure by enumerating an unconfigured item-path from the product to an item for each item. Then, when one or more unconfigured item-paths are identical, only one of the identical unconfigured item-paths is maintained. The index may also be combined with an unconfigured item-path spatial-bounds index. Both product structure and spatial location queries may be filtered against the combined index.
A circuit comprises: scan chains comprising scan cells, the scan chains configured to shift in test patterns, apply the test patterns to the circuit, capture test responses of the circuit, and shift out the test responses; a decompressor configured to decompress compressed test patterns into the test patterns; and a test response compactor configured to compact the test responses, the test response compactor comprising: first X-masking circuitry configured to mask, based on first masking information, some of X bits in the test responses, the first masking information remaining the same while a test response for each of the test patterns is being shifted out, the first masking information being different for at least two of the test patterns; and second Xmasking circuitry configured to mask, based on second masking information, rest of the X bits in the test responses.
A computer-implemented method of enabling a user to select at least one component from a group comprising identical and/or non-identical components forming part of a computer-aided design (CAD) model is described. The method comprising the steps of a) receiving a seed component selection from a user via a user input device, the seed component representing component criteria desired by the user; and b)on the basis of the seed component, generating a selection comprising at least one component sharing common shape elements with the seed component. The HDBSCAN algorithm is used to cluster together components within a CAD application, which are then displayed to a user on the basis of the seed component. This enables a user to select similar components quickly and simply.
G06F 30/12 - Geometric CAD characterised by design entry means specially adapted for CAD, e.g. graphical user interfaces [GUI] specially adapted for CAD
G06F 16/532 - Query formulation, e.g. graphical querying
G06F 16/583 - Retrieval characterised by using metadata, e.g. metadata not derived from the content or metadata generated manually using metadata automatically derived from the content
G06T 19/20 - Editing of 3D images, e.g. changing shapes or colours, aligning objects or positioning parts
24.
MULTI-LEVEL PREDICTIONS IN WORKFLOW LOGIC OF COMPUTER-AIDED DESIGN APPLICATIONS
A computing system (100) may logic construction engine (110) configured to construct, via multi-level prediction, workflow logic (220) to process a computer-aided design (CAD) model. The logic construction engine (110 may do so by identifying a multi-node sequence (230, 430) inserted into the workflow logic (220), aggregating past workflow data (240) specific to the multi-node sequence (230, 430), determining a node prediction (250, 350, 450) in the workflow logic (220) for the multi-node sequence (230, 430) based on the aggregated past workflow data (240), and providing the node prediction (250, 350, 450) as a suggested insertion for the workflow logic (220).
G05B 19/4097 - Numerical control (NC), i.e. automatically operating machines, in particular machine tools, e.g. in a manufacturing environment, so as to execute positioning, movement or co-ordinated operations by means of programme data in numerical form characterised by using design data to control NC machines, e.g. CAD/CAM
A computing system (100) may include a computer-aided design (CAD) face access engine (108) configured to access a CAD object and an imprint-based meshing engine (110) configured to define an imprint region (220, 320, 520, 610, 720) for a face (210, 310, 510, 710) of the CAD object and determine that the imprint region (220, 320, 520, 610, 720) meets constraint criteria. Responsive to a determination that the imprint region meets the constraint criteria, the imprint-based meshing engine (110) may modify the imprint region (220, 320, 520, 610, 720) into an adapted imprint region (330, 530, 620, 820) and generate an output mesh (410, 910) using the adapted imprint region (330, 530, 620, 820).
nn thnn thnn th level expansion are marked as displayable. The process is repeated for all other branch values shown in the initial view. A revised view showing only those values from the initial view in which the branch value, a child value or a descendant value were marked as displayable is then displayed to the user.
The invention relates to a computer implemented method for providing a recommender system (SRS) for a design process of a complex system, wherein the recommender system (SRS) is shared by a plurality of users (UlCl, U2C1, U1C2), wherein the complex system comprises a plurality of connectable com- ponents and is designed in a design process by a sequence of design steps (DS1, DS2) wherein in each design step a partial design (PD) is created until a completed design (CD) is obtained, wherein a partial design (PD) of one step and a partial de- sign (PD) of a subsequent step differ in a design difference (DELTA) reflecting a difference in at least one element comprising a component or/and connection of the components, and wherein the shared recommender system (SRS) provides at each design step (DS1, DS2) a prediction of the subsequent design difference (DELTA).
G06F 30/12 - Geometric CAD characterised by design entry means specially adapted for CAD, e.g. graphical user interfaces [GUI] specially adapted for CAD
G06F 30/27 - Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
G06F 111/02 - CAD in a network environment, e.g. collaborative CAD or distributed simulation
28.
REFERENCE BITS TEST AND REPAIR USING MEMORY BUILT-IN SELF-TEST
A memory-testing circuit configured to perform a test of reference bits in a memory. In a read operation, outputs of data bit columns are compared with one or more reference bit columns. The memory-testing circuit comprises: a test controller and association adjustment circuitry configurable by the test controller to associate another one or more reference bit columns or one or more data bit columns with the data bit columns in the read operation. The test controller can determine whether the original one or more reference bit columns have a defect based on results from the two different association.
This application discloses a computing system to receive measurements of solder paste disposed on a printed circuit board using a solder paste stencil, and correlate the measurements of the solder paste disposed on the printed circuit board to a solder stencil design describing the solder paste stencil utilized during an application of the solder paste on the printed circuit board. The computing system can correlate the solder paste measurements to the solder stencil design by determining a transfer efficiency of the solder paste on the printed circuit board based, at least in part, on the solder paste stencil and the measurements of the solder paste disposed on the printed circuit board. The computing system can detect a cause of a production defect associated with the printed circuit board based, at least in part, on the transfer efficiency of the solder paste on the printed circuit board.
H05K 13/08 - Monitoring manufacture of assemblages
H05K 3/12 - Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using printing techniques to apply the conductive material
A method, executed by at least one processor of a computer, of generating a heatsink configuration meeting a predetermined performance constraint is disclosed. The method includes establishing an initial heatsink configuration having a heatsink base including at least one layer formed of a plurality of tessellated rods and setting a thermal evaluation parameter. An initial thermal simulation of a heat source positioned proximate the heatsink base is performed to determine the initial thermal performance of the heatsink. Based on the initial thermal simulation, three revised heatsink configurations are examined, and simulations are carried out to generate first, second, and third revised thermal performances. These are compared with an initial thermal performance, and the heatsink configuration showing the greatest improvement in thermal performance compared with the initial thermal performance is selected. This process is repeated until a heatsink configuration meeting the predetermined performance constraint is generated.
This application discloses a computing system implementing a yield enhancer tool to extract characteristics of cells from a physical layout design for an integrated circuit, determine locations of vacant regions in the physical layout design, apply electrical design rules for manufacture of the integrated circuit to the extracted characteristics in order to identify cells in the physical layout design that would violate the electrical design rules. The computing system can select filler cells for the vacant regions based, at least in part, on extracted characteristics of the cells abutting the vacant regions and the electrical design rules, and insert the selected filler cells in the vacant regions of the physical design layout. The computing system can perform a design rule check operation, which applies the electrical design rules to the physical design layout having been inserted with the selected filler cells.
A computing system may include a metamaterial representation engine configured to represent a metamaterial of a three-dimensional (3D) object as program code. The metamaterial may define an internal geometry of the 3D object and may be configured to be physically constructed via additive manufacturing. Representation of the metamaterial as program code may include assigning a value of a code parameter of the metamaterial as a probability distribution. The computing system may also include a metamaterial analysis engine configured to analyze the metamaterial through the probability distribution assigned for the value of the code parameter of the program code.
G06F 30/12 - Geometric CAD characterised by design entry means specially adapted for CAD, e.g. graphical user interfaces [GUI] specially adapted for CAD
33.
AUTOMATED CELL BLACK BOXING FOR LAYOUT VERSUS SCHEMATIC
Text containers comprising information of cell ports are determined based on statements for cell ports in a rule file. Drawn layers comprising cell ports are determined based on the determined text containers or based on statements for attaching each of the test containers to a layout design layer in the rule file. Layout design layers connected to the drawn layers comprising cell ports are determined based on statements for connecting layout design layers in the rule file. A file for cell port detection is generated which associates each of the text containers comprising information of cell ports with one or more of the drawn layers comprising cell ports and one or more of the layout design layers connected to the one or more of the drawn layers comprising cell ports. The file for cell port detection can be used for extracting ports for cells to be black boxed.
There is described building automation systems, methods, and computer readable media for piping graphic control. Field devices (120-126) associated with HVAC equipment are identified and an HVAC piping graphic associated with the field devices (120-126) are generated at the management device (104-108). The HVAC piping graphic is modified at a processor (206) of the management device (104-108) in response to receiving user input at a user interface (111) of the management device (104-108). In particular, a pipe element (358) and a pipe coupling element (360) are integrated with the HVAC piping graphic based on the user input. Data points of the building automation system (100) are provided at the user interface (222) based on the pipe element (358) and the pipe coupling element (360). Runtime values are monitored, and the building automation system (100) are dynamically controlled at the management device (104-108) based on the data points.
A circuit comprises: a first clock gating device clocked by a first clock signal and configured to generate first clock pulses when a shift enable signal is active, a first transition detecting device clocked by a second clock signal and configured to generate shift gating pulses when detecting active transitions of the first clock pulses, a second clock gating device clocked by the second clock signal and configured to generate shift clock pulses based on the shift gating pulses to clock second scan elements for a shift operation with first scan elements clocked by the first clock signal, and a first retiming device triggered by active pulse edges of the first clock signal and configurable to hold a value for the shift operation. The circuit may further comprise a delay generating device configured to generate delayed shift gating pulses for generating the shift clock pulses.
System and method for differentiable networks trainable to learn an optimized query of a 3D model database used for object recognition includes training a first differentiable network configured as a differentiable renderer by generating 2D images from 3D models of a first object of a dissimilar second object while optimizing rendering parameters for producing 2D images by gradient descent of a first triple loss function. Visual variation among the images is maximized. A second differentiable network configured as a convolutional neural network defined by a regression function is trained by generating searchable feature vectors of the 2D images. The feature vectors are determined using optimized neural network parameters determined by gradient descent of a second triple loss function to achieve high correlation to an input image of the first object and low correlation to images of the second object.
Various aspects of the present disclosed technology relate to techniques for inverse-lithography-technology-based optical proximity correction. A layout design is received. A machine learning-based clustering process is then performed to separate layout features in the layout design into groups of layout features. For layout features in each of the groups of layout features, preliminary corrections are determined. The determination may be based on inverse lithography technology. The preliminary corrections are applied to the layout design to generate a pre-processed layout design. An inverse lithography technology process is performed on the pre-processed layout design to generate a processed layout design. Masks can be manufactured based on the processed layout design.
G03F 1/36 - Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
G03F 1/70 - Adapting basic layout or design of masks to lithographic process requirements, e.g. second iteration correction of mask patterns for imaging
G06F 30/27 - Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
38.
HARVESTING CIRCUIT INFORMATION FROM SCHEMATIC IMAGES
A computing system to parse a schematic design illustrating a circuit design for an electronic system to identify text and enclosures representing circuit devices of the electronic system, The computing system can classify the text based on a proximity of the text to the enclosures in the schematic diagram, and match the text to the enclosures in the schematic diagram based on the classifications, which correlates the circuit devices represented by the enclosures to the text matched to the enclosures. The computing system can identify one of the circuit devices includes a connector having one or more pins, and correlate the text matched to the enclosure to at least one of the pins based on a relative alignment of the pins with the text. The computing system can generate an interactive technical file that includes the correlations of the circuit devices and pins to the text matched to the enclosures.
G06V 10/764 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using classification, e.g. of video objects
A computer-implemented method of determining the dimensions of a space-filling lattice in a solid model is disclosed. Initially information including a lattice, a set of faces and data indicating a spatial relationship between the lattice and each face in the set is received. A set of points indicating the intersection positions where each rod intersects a face is then identified, and each intersecting rod is classified based upon whether or not each subset of mutually tolerantly coincident points within the set indicates that a rod is divided by a face. If a rod is divided the lattice is modified by adding a new ball where the rod is divided and classifying the new rods either side of it. These classifications are then spread to adjacent rods without crossing any new ball to establish the complete set of surviving rods. Each connected set of surviving rods is used to instantiate a new lattice.
A method of monitoring messages from a sensor using an integrated circuit is provided, wherein the messages include data measured by that sensor. The method includes: reading a first message from interconnect circuitry of the integrated circuit, the interconnect circuitry connecting the sensor to one or more core devices configured to process the message; calculating a first hash value for the first message; comparing the first hash value to one or more prior hash values stored in a hash store, each prior hash value corresponding to a message that was read from the interconnect circuitry prior to the first message; and performing a corrective action if the difference between the first hash value and at least one of the prior hash values stored in the hash store is above a predetermined threshold.
G08C 25/00 - Arrangements for preventing or correcting errors; Monitoring arrangements
H04Q 9/00 - Arrangements in telecontrol or telemetry systems for selectively calling a substation from a main station, in which substation desired apparatus is selected for applying a control signal thereto or for obtaining measured values therefrom
G06F 11/07 - Responding to the occurrence of a fault, e.g. fault tolerance
41.
METHOD OF MEASURING THE JUNCTION TEMPERATURE OF A SEMICONDUCTOR DEVICE
Tjj Tjj j . Each of the plurality of measurements of the first temperature-sensitive parameter and the at least second temperature-sensitive parameter is synchronized with a switching event of the semiconductor switching element.
G01K 7/01 - Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat using semiconducting elements having PN junctions
42.
VARIANT MODEL-BASED COMPILATION FOR ANALOG SIMULATION
A computing system implementing a design verification system can detect multiple analog design blocks in a circuit design describing an electronic device. The design verification system can generate equivalent networks for the analog design blocks using different sets of the parameters of the analog design blocks by selectively collapsing nodes and braches in the analog design blocks based on values of the different sets of the parameters. The equivalent networks can correspond to behavioral topologies of the analog design blocks having the different sets of the parameters. The design verification system can selectively compile a subset of the analog design blocks into multiple compiled variant models based on a comparison of the equivalent networks. The design verification system can include an analog simulator to simulate the analog design blocks in the circuit design using the compiled variant models.
G06F 30/367 - Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
G06F 30/323 - Translation or migration, e.g. logic to logic, hardware description language [HDL] translation or netlist translation
43.
CONTROLLABLE PATTERN CLUSTERING FOR CHARACTERIZED SEMICONDUCTOR LAYOUT DESIGNS
A computing system implementing a physical verification tool can determine principal feature components describing geometric patterns around points of interest in a semiconductor layout design. The principal feature components include topological features indicating whether structures are present around the points of interest, and include dimensional features corresponding to measurements associated with the structures present around the points of interest. The physical verification tool can generate a topological signature for each of the points of interest based on the topological features, and cluster the points of interest into different subsets based on the topological signature. The physical verification tool can perform design rule check operations on the semiconductor layout design to identify whether one or more of the points of interest correspond to a design rule violation and perform pattern matching to identify whether other points of interest match the point of interest corresponding to the design rule violation.
This application discloses a computing system implementing a mask synthesis system to generate synthetic image clips of design shapes and corresponding mask data for the synthetic image clips. The mask data can describe lithographic masks capable of being used to fabricate the design shapes on an integrated circuit. The mask synthesis system can utilize the synthetic image clips of the design shapes and the corresponding mask data to train a machine-learning system to determine pixelated output masks from portions of the layout design. The mask synthesis system can identify one or more pixelated output masks for portions of a layout design describing an electronic system using the trained machine-learning. The mask synthesis system can synthesize a mask layout design for the electronic system based, at least in part, on the layout design describing the electronic system and the one or more pixelated output masks for the layout design.
G05B 19/4093 - Numerical control (NC), i.e. automatically operating machines, in particular machine tools, e.g. in a manufacturing environment, so as to execute positioning, movement or co-ordinated operations by means of programme data in numerical form characterised by part programming, e.g. entry of geometrical information as taken from a technical drawing, combining this with machining and material information to obtain control information, named part programme, for the NC machine
G06F 30/392 - Floor-planning or layout, e.g. partitioning or placement
This application discloses a computing system implementing a power estimator can read in waveform data generated during functional verification of a circuit design describing an electronic device, detect toggles in the signals of the waveform data, correlate the detected toggles in the signals to arcs associated with logic gates in the circuit design, and track a number of times each of the arcs has been correlated to the detected toggles. After the waveform data has been read, the power estimator can look-up power values for each arc having been correlated to a detected signal toggle, multiple the power values by the tracked number of times each of the arcs been correlated to the detected toggles to compute power estimates, and generate an estimate of power consumption for the circuit design during the functional verification by accumulating the power estimates for the arcs associated with the logic gates.
This application discloses a computing system to identify net lines corresponding to connections between pins of a source layout design describing a first electronic device and pins of a target layout design describing a second electronic device, scan the net lines in an order selected based, at least in part, on an orientation of the net lines between pins of the source layout design and the pins of the target layout design, identify a plurality of the scanned net lines cross each other, and unravel the crossed net lines by swapping pin assignments of the crossed net lines. The computing system can implement a machine learning algorithm having a first stage to determine a scan order for the net lines and having a second stage to identify the net lines that cross each other and unravel the crossed net lines.
A computing system (100) may include a quantifier determination engine (110) configured to determine a defectivity quantifier (310) for a lithographical circuit fabrication process performed with a target value (210) for a process parameter, including by modifying the target value (210) to obtain an off-target value (220) for the process parameter, determining a defectivity quantifier (250) for the lithographical circuit fabrication process performed with the off-target value (220), and extrapolating the defectivity quantifier (310) for the lithographical circuit fabrication process performed with the target value (210) from the determined defectivity quantifier (250) for the lithographical circuit fabrication process performed with the off-target value (220). The computing system (100) may also include a quantifier provision engine (112) configured to provide the determined defectivity quantifier (310) for assessment of the lithographical circuit fabrication process.
G06F 30/20 - Design optimisation, verification or simulation
G06F 30/367 - Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
A computing system implementing a design characterization tool can sample a distribution of values for manufacturing variation of an integrated circuit described by a circuit design. The design characterization tool can order the samples based on predicted output values of the circuit design set with characteristics in the samples of the values for manufacturing variation. The computing system can implement an analog simulator to simulate the circuit design utilizing a subset of the samples of values for manufacturing variation to identify simulated output values for an output distribution model. The design characterization tool can estimate an error in the order of the samples associated with the predicted outputs of the circuit design based on the simulated output values in the output distribution model. The design characterization tool can modify the output distribution model to correct a bias based on the estimated error in the order of the samples.
A computing system (100) may include a design access engine (108) configured to access an injection mold design (210) and a channel construction engine (110) configured to construct conformal cooling channels (510) for the injection mold design (210). The channel construction engine (110) may do so by extracting a cooling surface (600) of the injection mold design (210), generating a central offset surface (220) with a same shape as the cooling surface (600), projecting cooling lines (310) on to the central offset surface (220), detecting sharp portions (410) of the projected cooling lines (320), smoothing the detected sharp portions (410) of the projected cooling lines (320), and generating the conformal cooling channels (510) using the smoothed cooling lines (420) along the central offset surface (220) as a center line for the conformal cooling channels (510). It also relates to the method and a non-transitory machine-readable medium (820) comprising instructions (822, 824).
B29C 33/02 - SHAPING OR JOINING OF PLASTICS; SHAPING OF MATERIAL IN A PLASTIC STATE, NOT OTHERWISE PROVIDED FOR; AFTER-TREATMENT OF THE SHAPED PRODUCTS, e.g. REPAIRING - Details thereof or accessories therefor with incorporated heating or cooling means
B29C 64/386 - Data acquisition or data processing for additive manufacturing
The current disclosure describes method of verifying integri¬ ty of data from a device under test. The method comprises ob¬ taining network data from the device under test, wherein the network data is generated by the device under test based on a test data from a source device by transforming the test data from a first domain to a second domain and framing the trans¬ formed test data in a first protocol, deframing the received network data from the first protocol to a second protocol for extracting the transformed test data, obtaining the test data from the source device for verifying the transformed test da¬ ta and verifying the integrity of the transformed test data based on the test data using one of a block error rate (BLER) and bit error rate (BER).
A computing system may include a virtual cross metrology engine configured to construct a given virtual metrology model. The given virtual metrology model may take, as inputs, process parameters applied for the given step of a semiconductor fabrication process. The virtual cross metrology engine may also be configured to construct a subsequent virtual metrology model, and the subsequent step is performed after the given step in the semiconductor fabrication process. Doing so may include determining inputs for the subsequent virtual metrology model from a combination of the process parameters applied for the given step of the semiconductor fabrication process, process parameters applied for the subsequent step of the semiconductor fabrication process, and a wafer value for the given step of the semiconductor fabrication process that the given virtual metrology model is configured to predict.
G05B 19/418 - Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control (DNC), flexible manufacturing systems (FMS), integrated manufacturing systems (IMS), computer integrated manufacturing (CIM)
G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
52.
A METHOD OF GENERATING A SIMULATED MULTIPATH FADING CHANNEL DATA
The current disclosure describes a method of generating a simulated multipath fading channel data. The method comprises obtaining an IQ sample data, selecting one or more radio samples from the IQ sample data for appending to the IQ sample data, generating a second IQ sample data by appending the selected one or more radio samples prior to the start radio sample of the IQ sample data and generating the simulated multipath fading channel using the second IQ sample data and a predefined set of propagation delay and attenuation coefficients associated with a channel model.
This application discloses a computing system (400) to generate a product model (409) that describes attributes of a product including an electronic system (401). The computing system (400) can implement a machine-learning algorithm having been trained with metadata populated in previously generated product models for different electronic systems, which can determine one or more sets of metadata capable of being correlated to the electronic system included in the product model based on the attributes of the electronic system described in the product model. The sets of metadata can correspond to different design constraints in the product model associated with electrical connectivity for the electronic system and their corresponding parameter values. The computing system can populate at least one of the sets of metadata into the product model to correlate with the electronic system.
G06F 30/27 - Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
A computing system (100) may include a voxel access engine (108) configured to access voxel data (210, 310) and a voxel processing engine (110). The voxel processing engine (110) may identify and label thin features in the voxel data (210, 310), smooth the voxel data (210, 310) to preserve the thin features, and convert the voxel data (210, 310) to form a faceted representation (320). The voxel processing engine (110) may also adaptively perform a pressing process on the faceted representation (320). Responsive to a determination that a pressing reapplication criterion is satisfied, the voxel processing engine (110) may modify the voxel data (210, 310), convert the modified voxel data (340) to form the faceted representation (320) of the object, and perform the pressing process on the faceted representation (320) of the object formed through the modified voxel data (340).
A memory device can sense stored data during memory read operations using a reference trim, and a memory built-in self-test system can perform a multiple step process to set the reference trim for the memory device. The memory built-in self-test system can set a reference trim range that corresponds to a range of available reference trim values and then select one of the reference trim values in the reference trim range as the reference trim for the memory device. The memory built-in self-test system can set the reference trim range by prompting performance of the memory read operations using different positions of the reference trim range relative to read characteristics of the memory device and set a position for the reference trim range relative to the read characteristics of the memory device based on failures of the memory device to correctly sense the stored data during the memory read operations.
A simulator can simulate a circuit design describing an electronic device using a single processing device of a computing system. The simulator can generate profile data associated with compilation of the circuit design and the single processing device simulation of the compiled circuit design. The profile data can identify multiple different ways to partition the circuit design and include information corresponding to the single processing device simulation of the compiled circuit design. A parallel simulation qualifier can determine a parallelism factor corresponding to an expected performance of the computing system in a multiple processing device simulation of the circuit design based on the profile data from the single processing device simulation of the circuit design. The simulator can utilize the parallelism factor to partition the circuit design in one of the different ways, and simulate the partitioned circuit design with multiple processing devices of the computing system.
A computing system may include a client device and a server. The client device may be configured to access a stream of image frames that depict an environment, determine, from the stream of image frames, environment images that satisfy selection criteria, and transmit the environment images to the server. The server may be configured to receive the environment images from the client device, construct a spatial view of the environment based on position data included with the environment images, and navigate the spatial view, including by receiving a movement direction and progressing from a current environment image depicted for the spatial view to a next environment image based on the movement direction.
Today's automation or manufacturing systems are engineered based on solution documents that are typically written in natural language (e.g. English) with domain-specific vocabulary. It is recognized that it can be cumbersome (e.g., time, cost, etc.) to engineer systems, for instance develop software, that operate in multiple domains, based on such solution documents. An engineering computing system can generate executable code (e.g., tenant-specific executable metadata) for an application from the requirements document that defines business requirements written in natural language.
A computer-implemented method of incarnating a self-intersecting lattice structure as a mesh in a three-dimensional model is described. A pair of bodies in the lattice is chosen. An initial set of sample points is created by intersecting a set of constant parameter curves within the parameter range lying on the surface of one of the bodies of the pair with the surface of the other body of the pair. Chords between adjacent sample points in the initial set of samples that lie within a pre-determined tolerance of the surfaces of both bodies in the pair are calculated and iterated over until all the sample points are within the pre-determined tolerance. Once this is done for all bodies in the lattice, a mesh is incarnated.
42 - Scientific, technological and industrial services, research and design
Goods & Services
SaaS, IaaS, PaaS in connection with computer
hardware-assisted verification for computer hardware and
software for electronic design automation (term considered
to vague by the International Bureau - Rule 13 (2) (b) of
the Regulations).
A method and device for testing a base station comprising one or more radio units and a baseband unit connectable to the one or more radio units, wherein the device includes a configuration module configured to generate a first test case configuration associated with the one or more radio units and the baseband unit, where the first test case configuration includes a first protocol stack including a first protocol associated with a first layer and a second protocol associated with a second layer, and where a first set of protocol parameters associated with the first protocol is in a first namespace and a second set of protocol parameters associated with the second protocol is in a second namespace that is distinct from the first name space.
A method for determining a set of output configuration values characterizing a specific configuration of a complex product, includes receiving a set of input configuration parameters, providing at least a part of the input configuration parameters as an input to a solver, using the solver to calculate at least one output value from the provided input configuration parameters, and determining the set of output configuration values from at least the output value calculated by the solver. The solver is configured for solving a first order logic function encoding an algorithm of a trained deep neural network or DNN, wherein the algorithm of the DNN has been trained for modeling a function of an external configuration tool or ECT that is required for determining the specific configuration of the complex product. A system for determining the set of output configuration values, and a training system, are also provided.
G06Q 10/04 - Forecasting or optimisation specially adapted for administrative or management purposes, e.g. linear programming or "cutting stock problem"
G06Q 10/06 - Resources, workflows, human or project management; Enterprise or organisation planning; Enterprise or organisation modelling
63.
DISTRIBUTED HANDLING OF FORWARD ERROR CORRECTION IN HARDWARE ASSISTED VERIFICATION PLATFORMS
This application discloses distributed forward error correction in hardware assisted verification platforms (300) including a hardware- assisted verification system (320) to emulate an electronic system (322) described by a circuit design (301). The hardware-assisted verification system (320) can implement forward error correction circuitry (324) to analyse a data packet (311) for use by the emulated electronic system (322) during functional verification operations of the circuit design (301), which can identify that the data packet includes one or more corrupted bits (321). The forward error correction circuitry (324) can transmit the corrupted data packet (321) to a computing system (330) implementing an error correction algorithm configured to perform error correction operations (332) on the corrupted data packet (321). The computing system implementing the error correction algorithm (330) can generate a corrected data packet (331) during the error correction operations and transmit the corrected data packet to the hardware-assisted verification system (320) for use by the emulated electronic system (322) during functional verification operations of the circuit design (301).
G06F 30/331 - Design verification, e.g. functional simulation or model checking using simulation with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
G06F 11/36 - Preventing errors by testing or debugging of software
H04L 1/00 - Arrangements for detecting or preventing errors in the information received
A method is provided for transmission rate adaptation of one or more data units, the method including: receiving, by an adapter, the adapter including an adaptation circuitry, a plurality of data units according to a first transmission rate and at least one delay character separating two consecutive data units; and transmitting, by the adapter, each of the plurality of data units received according to a second transmission rate, wherein the second transmission rate is determined based on the at least one delay character received.
A preliminary netlist comprising the photonic devices and location and rotation information for each of the photonic devices is extracted from the original layout design. In the extraction, each of the photonic devices is treated as a black box. A geometric pattern for the each of the photonic devices is then identified in a group of geometric patterns for each of the photonic devices based on physical properties of the each of the photonic devices specified in the circuit design. A new layout design is generated based on the identified geometric pattern for each of the photonic devices, the location and rotation information for each of the photonic devices, and the preliminary netlist. Geometric elements in each of the photonic devices in the new layout design are compared with corresponding geometric elements in the original layout design.
G02B 6/12 - Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
G06F 30/3308 - Design verification, e.g. functional simulation or model checking using simulation
G06F 30/367 - Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
G06F 30/398 - Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
66.
Determining a cut pattern of a lathe method, control device, and lathe
A computer-implemented method is provided for determining a cut pattern of a lathe. The lathe is numerically controlled by a control device and includes a tool with a cutter acting on a workpiece. The workpiece has a start contour and a target contour to be achieved by cutting the workpiece according to the cut pattern. The method includes determining a path of a n-th layer of the cut pattern, wherein the n-th layer includes: for n≥2: an infeed path linear and/or parallel to the target contour; a circular infeed path starting tangent to the target contour; an intermediate path linear and/or parallel to the target contour; a circular outfeed path ending tangent to the target contour; and for n≥2: a smoothing path linear and/or parallel to the target contour.
G05B 19/4093 - Numerical control (NC), i.e. automatically operating machines, in particular machine tools, e.g. in a manufacturing environment, so as to execute positioning, movement or co-ordinated operations by means of programme data in numerical form characterised by part programming, e.g. entry of geometrical information as taken from a technical drawing, combining this with machining and material information to obtain control information, named part programme, for the NC machine
67.
METHOD AND APPARATUS FOR DESIGNING AND MANUFACTURING A COMPONENT IN A COMPUTER-AIDED DESIGN AND MANUFACTURING ENVIRONMENT
A method and apparatus for designing and manufacturing a component in a computer-aided design and manufacturing environment is disclosed. A method includes obtaining a geometric model of a component from a geometric model database, and determining at least one orientation parameter value associated with the geometric model of the component. The at least one orientation parameter value is associated with an orientation parameter that defines orientation of the component during additive manufacturing of the component. The method includes performing volumetric analysis of the component based on the at least one orientation parameter value associated with the component using the geometric model of the component. The method also includes computing one or more overheating areas in the component corresponding to the at least one orientation parameter value based on the volumetric analysis of the geometric model of the component, and outputting a multi-dimensional visual representation of the geometric model of the component Indicating one or more overheating areas in the component.
A method of detecting anomalous latencies in communications between components on an integrated circuit (IC) chip. The method includes: (i) monitoring communications between a first component of the IC chip and other components of the IC chip, each communication comprising a command sent from the first component to another component, and a response received by the first component from that other component, the monitoring comprising: measuring the number of communications in each of a series of monitored time windows, and measuring the latency of each communication in the series of monitored time windows; (ii) calculating a maximum tolerable latency for each operational time window of the first component from the number of communications in that operational time window, an available stall time of the first component in that operational time window, and a latency penalty factor for that operational time window; and (iii) determining a measured latency to be anomalous if the measured latency is greater than the maximum tolerable latency.
A method of identifying a cause of an anomalous feature measured from system circuitry on an integrated circuit (IC) chip, the IC chip comprising the system circuitry and monitoring circuitry for monitoring the system circuitry by measuring features of the system circuitry in each window of a series of windows, the method comprising: (i) from a set of windows prior to the anomalous window comprising the anomalous feature, identifying a candidate window set in which to search for the cause of the anomalous feature; (ii) for each of the measured features of the system circuitry: (a) calculating a first feature probability distribution of that measured feature for the candidate window set; (b) calculating a second feature probability distribution of that measured feature for window(s) not in the candidate window set; (c) comparing the first and second feature probability distributions; and (d) identifying that measured feature in the timeframe of the candidate window set as a cause of the anomalous feature if the first and second feature probability distributions differ by more than a threshold value; (iii) iterating steps (i) and (ii) for further candidate window sets from the set of windows prior to the anomalous window; and (iv) outputting a signal indicating those measured feature(s) of step (ii)(d) identified as a cause of the anomalous feature.
A computing system may include an object representation engine and an object incarnation engine. The object representation engine may be configured to define a computer-aided design (CAD) object in a CAD model as a combination of an object boundary comprised of bounding faces that encapsulate the CAD object and a microstructure that defines an internal geometry of the CAD object in a procedural representation. The procedural representation may be a representation of the internal geometry of the CAD object in a non-incarnated form. The object incarnation engine may be configured to incarnate, via the procedural representation of the microstructure, the internal geometry of the CAD object into a geometric representation to perform a CAD operation on the CAD object.
G06F 30/12 - Geometric CAD characterised by design entry means specially adapted for CAD, e.g. graphical user interfaces [GUI] specially adapted for CAD
71.
MACHINE LEARNING-BASED SELECTIVE INCARNATION OF COMPUTER-AIDED DESIGN OBJECTS
A computing system may include an instance identification engine configured to determine a selected subset of pattern instances of a programmatic pattern used to represent a geometry of a computer-aided design (CAD) object, including by identifying a CAD operation to perform on the CAD object; determining a sampled point set in the CAD object applicable to the CAD operation; providing the sampled point set as an input to an inversion machine-learning (ML) model trained to output a given pattern instance of the programmatic pattern for an input point of the CAD object; and determining, as the selected subset, an output set of pattern instances provided by the inversion ML model for the sampled point set. The system may also include an object incarnation engine configured to incarnate a geometry of the selected subset of pattern instances to perform the CAD operation on the CAD object.
G06F 30/27 - Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
A computing system (100) may include a linear mesh access engine (108) configured to access a linear mesh (120, 210) and a target geometry (130) as well as curved mesh generation engine (110) configured to construct a curved mesh (140). Construction of the curved mesh (140) may include projecting (406) the linear mesh (120, 210) on to the target geometry (130) to form a projected mesh (220), determining (408) deformation patches included in the projected mesh (220), selecting (410) a cost function (340) to apply to the deformation patches from a set of available cost functions (320), iteratively adapting (412) the deformation patches based on the selected cost function (340) to obtain adjusted mesh elements (350), and forming (414) the curved mesh (140) as a combination of the adjusted mesh elements (350) and portions of the projected mesh (220) not determined as part of the deformation patches.
A computing system (100) includes a computer-aided design (CAD) face access engine (108) configured to access a CAD object and an imprint-based meshing engine (110) configured to define an imprint region (220) for a face (210, 310) of the CAD object and decompose the face (210, 310) into virtual faces, including an imprinted virtual face (240, 320) and a remainder virtual face (250, 330). The imprint¬ based meshing engine (110) is also configured to mesh the imprinted virtual face, mesh the remainder virtual face, and merge the imprint region mesh and the remainder region mesh together to form an output mesh (350, 400, 700), including by extending a portion of the imprint region mesh into the remainder portion (230) of the face (210, 310) or extending a portion of the remainder region mesh into the imprint region (220).
A computer-implemented method of bounding spatial data in a hierarchical product structure with hierarchical transforms is described. Initially, the part or part assembly at the lowest level of a hierarchical assembly path is selected. Then, a hierarchical merge of the spatial bounds of the bounding box(es) of the part or part assembly is performed to generate a set of intermediate spatial bounds. Following this, a merge of the set of oriented bounds of the bounding box(es) of the part or part assembly is performed to generate a reduced set of oriented bounds. Finally, the intermediate bounds and the reduced set of oriented bounds are stored for use in configuring the assembly path when building a product from the hierarchical product structure.
A computer-implemented method of extending a mixed sheet within a B-rep model is described. The mixed sheet comprises surfaces having different geometries, such as a mesh positioned between first and second classical geometry surfaces. A first guide curve is defined, located at the boundary of a first surface for a length corresponding to the desired mixed sheet extension adjacent the first surface. A second guide curve may also be defined, located at the boundary of a second surface for a length corresponding to the desired mixed sheet extension adjacent the second surface. At least one extension mesh rung is created by generating facets between the two external mesh vertices using first and second extension vectors, wherein the first extension vector has a pre-determined spatial relationship to the first guide curve. If included, the second extension vector has a pre-determined spatial relationship to the second guide curve.
A computer-implemented method of handling large transforms in a computer-aided design (CAD) solid model utilising double precision to describe a physical assembly of parts is described. If the unit size of a transform of interest exceeds a pre-determined threshold, the double precision of the transform is converted to quadruple precision whilst maintaining the double precision of the assembly (108). The results of any operation are output in double precision (112). A computer program and method of adapting an existing CAD model are also described.
An integrated circuit (IC) chip includes system circuitry having system memory, and a master processor and a checker processor configured to operate in lockstep; and monitoring circuitry comprising an internal lockstep monitor, a master tracer and a checker tracer. The internal lockstep monitor is configured to: observe states of internal signals of the master processor and the checker processor, compare corresponding observed states of the master processor and the checker processor, and if the corresponding observed states differ: trigger the master tracer to output stored master trace data recorded from the output of the master processor, and trigger the checker tracer to output stored checker trace data recorded from the output of the checker processor.
Embodiments of the present disclosure provide a method and system for digital plant system model creation and simulation and a storage medium. The method includes: receiving a digital model created by a user based on a modeling library; in the modeling library, a digital plant system is divided into multiple subsystems, and motion joints in each subsystem are set with at least one option of at least one solution parameter of dynamics, kinematics and articulation; for each motion joint in the digital model, associating a corresponding algorithm engine in a simulation engine with the motion joint according to a solution parameter of the motion joint; the simulation engine comprises a kinematics algorithm engine, a dynamics algorithm engine and an articulation algorithm engine; using the corresponding algorithm engine to solve the motion joint associated with the algorithm engine. The technical scheme in embodiments of the present disclosure can improve the performance, stability and accuracy of the virtual digital plant.
G05B 19/418 - Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control (DNC), flexible manufacturing systems (FMS), integrated manufacturing systems (IMS), computer integrated manufacturing (CIM)
G06F 30/20 - Design optimisation, verification or simulation
G06F 9/455 - Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
09 - Scientific and electric apparatus and instruments
42 - Scientific, technological and industrial services, research and design
Goods & Services
Computer software for manufacturing solutions, products and
processes; computer software for the design of manufacturing
solutions, products and processes; computer software in the
fields of product lifecycle management; computer software
for collaborative engineering and collaborative product
development. Design and development of computer software; computer
software and hardware integration for manufacturing
solutions, products and process (term considered too vague
by the International Bureau - Rule 13 (2) (b) of the
Regulations); computer software and hardware integration for
design of manufacturing solutions, products and processes
(term considered too vague by the International Bureau -
Rule 13 (2) (b) of the Regulations); computer software and
hardware integration for collaborative engineering and
collaborative product development services for others; and
collaborative engineering and collaborative product
development services for others.
80.
SPATIAL DECOMPOSITION-BASED INFILLS OF UNIT CELL DESIGNS FOR COMPUTER-AIDED DESIGN (CAD) OBJECTS
A computing system (100) may include a decomposition engine (110) configured to access a unit cell design (210) and a fill region (220) of a computer-aided design (CAD) object to infill with instances of the unit cell design (210) and spatially decompose the fill region (220) into power-of-two boxes (240). The power-of-two boxes (240) may have dimensions equal to dimensions of the unit cell design (210) multiplied by a power of two. The computing system (100) may also include an infill engine (112) configured to infill the fill region (220) by performing a joining operation of aggregated bodies based on the spatial decomposition of the fill region (220). Each given aggregated body may comprise a number of unit cell designs equal to a power of two that are joined together to form the given aggregated body.
A computing system may include a metal stack tuning engine and a tuned metal stack application engine. The metal stack tuning engine may be configured to access an obscured metal stack definition specified for an integrated circuit (IC) manufacture process and tune selected metal stack parameters of the obscured metal stack definition to obtain a tuned metal stack definition. The metal stack tuning engine may do so by generating sampled metal stack definitions, constructing sampled layout geometries from the sampled metal stack definitions, computing parasitic capacitance value sets for the sampled layout geometries, and determining tuned values for the selected metal stack parameters through a curve fitting process. The tuned metal stack application engine may be configured to use the tuned metal stack definition to perform a parasitic capacitance extraction process for an input IC design.
This application discloses a hotspot identification system to generate process variability bands for structures of an integrated circuit capable of being fabricated utilizing at least one lithographic mask based, at least in part, on a mask layout data describing the lithographic mask and a distribution of manufacturing parameters during fabrication. The hotspot identification system can utilize the process variability bands to identify a subset of the structures that correspond to hotspots in the integrated circuit and identify corresponding values for the manufacturing parameters associated with the identified hotspots. A wafer testing system can implement a real-time wafer assessment process by comparing measured manufacturing parameters associated with a fabricated integrated circuit to the values for the manufacturing parameters associated with the identified hotspots, and dynamically identifying a disposition for the fabricated integrated circuit corresponding to one or more structures associated with the identified hotspot based on the comparison.
A method of generating and monitoring a digital signature representing activity observed on signals on an integrated chip in a normal mode of operation is disclosed. A signal se- lector feeds a signal as a selected signal to a temporary memory store to create a value in the temporary memory store. This value is used as the basis of a digital signature repre- senting activity observed on the signal and is compared to a corresponding stored digital signature representing expected activity on the signal. If the comparing indicates a mis- match between the digital signature and the corresponding stored digital signature, an alarm signal is generated. An integrated chip digital signal generator and monitor is also disclosed.
G06F 21/71 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
84.
MODELING METHOD AND SYSTEM FOR TUBULAR STRUCTURE, AND COMPUTER-READABLE STORAGE MEDIUM THEREOF
A modeling method for a tubular structure includes: acquiring a structural wire-frame; generating, at each of non-manifold nodes of the structural wire-frame, a polyhedral structure formed by faces of a polyhedron; generating, at each of manifold nodes of the structural wire-frame, a connecting face; generating, at each of end nodes of the structural wire-frame, an end face; connecting vertices of the connecting wire-frame, vertices of the connecting face, and vertices of the end face; and carrying out curved-surface subdivision.
This application discloses a computing system implementing a shared management system (340) to distribute virtual product models (343), each corresponding to a shared product model (341) describing a product having an electronic device with multiple printed circuit boards, to multiple printed circuit board layout tools (320-1 to 320-N). The printed circuit board layout tools (320-1 to 320-N) separately modify the corresponding virtual product models (343) to generate layout designs for the multiple print circuit boards and generate at least one system-level design rule describing a physical limitation for the electronic device. The shared management system (340) can update the shared product model (341) based on the modifications to at least one of the virtual product models by the printed circuit board layout tools (320-1 to 320-N), and transmit a notification (347) to at least one of the printed circuit board layout tools when the updated shared product model (341) conflicts with the physical limitation for the electronic device described in the at least one system-level design rule.
A scan network configured to transport repair information between memories and a controller for a non-volatile storage device comprises: repair registers coupled in parallel to repair information generation circuitry for one of the memories and segment selection devices that divide the repair registers into repair register segments. Each of the segment selection devices comprises: a storage element configured to store a segment selection bit and segment selection bit generation circuitry configured to generate the segment selection bit based on the repair information. Each of the segment selection devices is configurable to include or not include the corresponding repair register segment in a scan path of the scan network in a shift operation based on the segment selection bit.
The current disclosure describes a method of determining a bit length of an IQ sample associated with a first data frame. The method comprises determining a first parameter associated with a payload length of the first data frame, determining a second parameter indicative of a number of physical resource blocks in the first data frame, detecting a presence of a compression header based on the first and second parameters and determining the bit length of the IQ sample from one of the detected compression header and the first and second parameters. Accordingly, in accordance with the above method, the bit length of the IQ sample can be determined automatically from the information available in the data frame. Accordingly, this eliminates the need for manual entry of parameters into the packet analyzer and additionally eliminates the likelihood of errors to due incorrect entry.
A computing system (100) may include physical devices (221, 222, 223, 224, 225, 226) of a manufacturing facility (210) and a message processing engine (110). The message processing engine (110) may be configured to receive, from the physical devices (221, 222, 223, 224, 225, 226) of the manufacturing facility (210), update messages (230) for product manufacture processes performed by the manufacturing facility (210) and parse the update messages (230) to determine a value of a promoted attribute (240) for each of the update messages (230). The message processing engine (110) may also be configured to group the update messages into different message groups according to the determined value of the promoted attribute (240) and sequentially process update messages grouped into a particular message group (310) for a particular value of the promoted attribute (240).
Verification of model-based systems engineering artifacts A method of verifying a model-based system engineering, MBSE, artifact comprising the steps of: translating (SI), by a translator implemented in software, the MBSE artifact into formulas of a first- order logic, checking (S4), by a solver executing a decision procedure implemented in software and operating on the formulas of the first order logic, whether or not a conjunction of the formulas is satisfiable.
This application discloses a computing system implementing a design verification tool to perform functional verification on a circuit design describing an electronic device and collect samples of performance data during the functional verification. The computing system can also include a performance visualization tool to generate a profile presentation based on the samples of performance data. The profile presentation, when displayed, can annunciate portions of the circuit design corresponding to at least one performance hotspot. The performance visualization tool can receive a data reduction request based on the performance hotspot annunciated by the profile presentation. The data reduction request can identify a subset of the performance data in the profile presentation. The performance visualization tool can generate a refined profile presentation based, at least in part, on the samples of performance data and the subset of the performance data identified in the data reduction request.
A computer-implemented method includes receiving toolpath data for machining a workpiece with a tool along a toolpath. The tool is comprised by a machine tool that is numerically controlled by a control device. Machine code for the machine tool corresponding to the toolpath data is received. A map linking at least one item of the toolpath data and at least one item of the machine code corresponding to the least one item of the toolpath data is created. At least one first item of the toolpath data and one or more second items of the machine code corresponding to the at least one first item are displayed to a user using the created map. A control device and a machine tool arranged and configured to execute the computer-implemented method are also provided.
G05B 19/402 - Numerical control (NC), i.e. automatically operating machines, in particular machine tools, e.g. in a manufacturing environment, so as to execute positioning, movement or co-ordinated operations by means of programme data in numerical form characterised by control arrangements for positioning, e.g. centring a tool relative to a hole in the workpiece, additional detection means to correct position
G05B 19/408 - Numerical control (NC), i.e. automatically operating machines, in particular machine tools, e.g. in a manufacturing environment, so as to execute positioning, movement or co-ordinated operations by means of programme data in numerical form characterised by data handling or data format, e.g. reading, buffering or conversion of data
G05B 19/409 - Numerical control (NC), i.e. automatically operating machines, in particular machine tools, e.g. in a manufacturing environment, so as to execute positioning, movement or co-ordinated operations by means of programme data in numerical form - characterised by control panel details, by setting parameters
G05B 19/4069 - Simulating machining process on screen
92.
ADDITIVE MANUFACTURING OF MONOLITHIC PRODUCTS THAT INCLUDE BRIDGE STRUCTURES
Methods for computer-aided design, engineering, visualization, or manufacturing (CAx) operations and corresponding systems and computer-readable mediums are disclosed herein. A method includes receiving, by a data processing system, a computer-aided design, engineering, visualization, or manufacturing model of a product to be manufactured. The CAx model comprises a bridge structure and at least two leg structures. The method includes slicing the CAx model into a plurality of layers, wherein each layer in each leg structure has a corresponding layer number in a sequence of layer numbers for that leg structure. The method includes maintaining an association between corresponding layer numbers of each of the leg structures. The method includes manufacturing the product according to the sequence of layer numbers and the associations, including manufacturing at least one layer of each leg structure in turn. Each leg structure completes manufacture at substantially the same time.
A first circuit design and a second circuit design are analyzed to determine part of the second circuit design structurally similar to part of the first circuit design. A first set of test patterns for the first circuit design is modified to generate a second set of test patterns for the second circuit design by reusing values of bits in the first set of test patterns associated with the part of the first circuit design as values of bits in the second set of test patterns associated with the part of the second circuit design. Fault simulation is performed on the second circuit design using the second set of test patterns to determine a subset of faults undetectable by the second set of test patterns. Test pattern generation is performed for the subset of faults to generate a third set of test patterns for the second circuit design.
A method and system for computer aided design, (e.g., of products and other items), are disclosed herein. The method may include receiving a CAD model having a behavior defined by a plurality of relationships, receiving a user operation to edit a seed feature in the CAD model, and identifying a set of problem relationships from the plurality of relationships, wherein the set of problem relationships prevent implementation of the received user operation to the received CAD model. A category for each relationship in the set of problem relationships is selected. The behavior of the CAD model is reconfigured based on the selected category for each problem relationship by retaining any user-defined relationships, optionally retaining any optional relationships, and ignoring any relaxed relationships. The user operation is then performed according to the reconfigured behavior to produce a modified CAD model.
G06F 30/12 - Geometric CAD characterised by design entry means specially adapted for CAD, e.g. graphical user interfaces [GUI] specially adapted for CAD
G06F 30/17 - Mechanical parametric or variational design
95.
ROLLBACK FOR COMMUNICATION LINK ERROR RECOVERY IN EMULATION
Each of a plurality of reconfigurable hardware modeling circuits in a reconfigurable hardware modeling device comprises: a plurality of communication ports; error monitoring circuitry configured to monitor, while the reconfigurable hardware modeling device is performing an operation for verifying a circuit design, whether data received from the plurality of communication ports contain an error or not, and send out an error signal indicating the monitoring result; and rollback circuitry configured to, if data received by any of the plurality of reconfigurable hardware modeling circuits contain an error, enable the reconfigurable hardware modeling circuit to repeat the operation from a state before the error is received, and if data received by the plurality of reconfigurable hardware modeling circuits contain no error, allow the reconfigurable hardware modeling circuit to continue the operation.
Systems and a method for detecting a false error in a set of errors detected on components of a board inspected by an AOI machine. Input data are received and wherein the input data comprise data originated from AOI machine's inspection results of a given inspected board marked as failed. A false error detector is applied to the input data and wherein the detector is modeled with a trained function and wherein the detector generates output data. The output data is provided and wherein the output data determines whether at least one of the component errors reported by the AOI machine for the given board is a false error.
A computing system may include a shadow feature model training engine configured to access a set of integrated circuit (IC) layouts and capacitance values determined for components of the set of IC layouts. The shadow feature model training engine may construct shadow feature training data for the set of IC layouts, including by extracting shadow features for components of the set of IC layouts, combine extracted shadow features and determined capacitance values to form the shadow feature training data, and may further train a machine-learning (ML) model with the shadow feature training data. The computing system may also include a shadow feature application engine configured to extract shadow features for components of an input IC layout and determine capacitance values for the input IC layout via the trained ML model.
G06F 30/398 - Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
G06F 30/27 - Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
G06F 30/392 - Floor-planning or layout, e.g. partitioning or placement
G01R 27/26 - Measuring inductance or capacitance; Measuring quality factor, e.g. by using the resonance method; Measuring loss factor; Measuring dielectric constants
Systems and methods for analyzing a semiconductor layout design around a point of interest (POI) are disclosed. Semiconductor layout designs are a representation of an integrated circuit in terms of planar geometric shapes which make up the components of the integrated circuit, and are used to manufacture the integrated circuit. The layout design may be analyzed using one or more POI-based approaches to determine whether to modify the layout design. In one POI-based approach, set of kernels, tailored to the downstream application, are convolved with a representation of the layout design about or around the POI in order to generate a signature associated with the POI. In turn, the signatures may be analyzed based on the downstream application. Another POI-based approach consists of analyzing geometrical parameters associated with the POI, which may be used during a design stage to identify and modify problem areas in the layout design.
G06F 30/392 - Floor-planning or layout, e.g. partitioning or placement
G06F 30/27 - Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
99.
EXECUTION PACKAGES FOR QUERY GENERATION AND EXECUTION BY DATABASE SYSTEMS
A computing system (100) may include a database system (112) and an application server (102). The application server (102) may include a logic packaging engine configured to identify a product (210) at a particular stage of a manufacturing process, extract parameter values for the product (210), and determine processing logic (220) applicable to the product (210). The processing logic (220) may be designed to query the product database (122) for the product (210). The logic packaging engine (110) may also be configured to generate an execution package (230) for the database system (112) to perform the query on the product database (122), and the execution package (230) can include the parameter values for the product (210) at the particular stage in the manufacturing process and metadata references (324, 334, 344) to corresponding query templates (410) stored on the database system (112).
A circuit comprises scan gating devices inserted between outputs of scan chains and inputs of a test response compactor. The scan gating devices divides the scan chains into groups of scan chains. Each of the scan gating devices operates in either an enabled mode or a disenabled mode based on a first signal. A scan gating device operating in the enabled mode blocks, blocks only at some clock cycles, or does not block a portion of a test response of a test pattern captured by and outputted from a scan chain in the associated scan chain group based on a second signal. Scan gating devices operating in the disenabled mode do not block, or based on a third signal, either block or do not block, a portion of the test response captured by and outputted from all scan chains in each of the associated scan chain groups.
