Abstract

Novel tools and techniques are provided for implementing encoding or decoding of adaptive bitrate streams. In various embodiments, one or more first computing systems may divide a live media content stream into one or more segments, each segment might include a starting segment boundary and an ending segment boundary. The one or more first computing systems might encode the one or more segments into one or more primary adaptive bitrate streams. The one or more first computing systems might also divide the one or more segments of the live media content stream into one or more subsegments. Each subsegment might be less than a length of a corresponding segment of the one or more segments. The one or more first computing systems might the encode and/or a second computing system might decode the one or more subsegments into or from one or more secondary adaptive bitrate streams.

IPC Classes  ?

• H04L 65/75 - Media network packet handling
• H04L 65/61 - Network streaming of media packets for supporting one-way streaming services, e.g. Internet radio
• H04L 65/70 - Media network packetisation

Abstract

A semiconductor device with a hybrid bonded interface having microfluidic channels is provided. The semiconductor device includes a first die comprising a first passivation layer, wherein the first passivation layer includes one or more first trenches, and a second die comprising a second passivation layer, wherein the second passivation layer includes one or more second trenches. The first die is bonded to the second die via hybrid copper-to-copper bonding, wherein the one or more first trenches and the one or more second trenches form one or more channels.

IPC Classes  ?

• H01L 23/473 - Arrangements for cooling, heating, ventilating or temperature compensation involving the transfer of heat by flowing fluids by flowing liquids
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/373 - Cooling facilitated by selection of materials for the device
• H01L 23/433 - Auxiliary members characterised by their shape, e.g. pistons
• H01L 23/467 - Arrangements for cooling, heating, ventilating or temperature compensation involving the transfer of heat by flowing fluids by flowing gases, e.g. air

Abstract

Systems and methods of communicating use device level throttling. Some embodiments relate to a method of communicating in a network. The systems and methods can provide a first communication associated with a device for issuance, issue the first communication if a queue depth value for the device is less than an issued communication value, and listing the first communication on a pend list for the device if a queue depth value for the device is less than the issued communication value.

IPC Classes  ?

• G06F 13/40 - Bus structure

Abstract

In some aspects, the disclosure is directed to methods and systems for reducing memory utilization and increasing efficiency during affine merge mode for versatile video coding by utilizing motion vectors stored in a motion data line buffer for a prediction unit of a second coding tree unit neighboring a first coding tree unit to derive control point motion vectors for the first coding tree unit.

IPC Classes  ?

• H04N 19/426 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals - characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements using memory downsizing methods
• H04N 19/105 - Selection of the reference unit for prediction within a chosen coding or prediction mode, e.g. adaptive choice of position and number of pixels used for prediction
• H04N 19/139 - Analysis of motion vectors, e.g. their magnitude, direction, variance or reliability
• H04N 19/176 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
• H04N 19/513 - Processing of motion vectors

Abstract

A system includes a first circuit configured to provide a digitally pre-distorted input signal, a digital-to-analog converter including a number of unit elements, a digital input, and a digital output. Each unit element is configured to receive a reference voltage and to be controllable by a control signal provided in response to the digitally pre-distorted input signal. The digital-to-analog converter provides an analog output. The first circuit is configured to reduce distortion due to signal dependent changes to the reference voltage. The signal dependent changes can be due at least in part to current through the supply network that supplies the reference voltage. The digital to analog converter can be a voltage mode converter.

IPC Classes  ?

• H03M 1/06 - Continuously compensating for, or preventing, undesired influence of physical parameters

Abstract

One way to stop electromagnetic fields from leaking outside of a module is an electric wall. Embodiments of the present disclosure are directed to emulating an electric wall with through vias. The through vias may be arranged around cavities in the printed circuit board. The density of the through vias may be selected based on an expected wavelength of the electromagnetic fields. The printed circuit board may then self-isolate components within the cavities from the electromagnetic fields.

IPC Classes  ?

• H05K 1/02 - Printed circuits - Details
• H01L 23/498 - Leads on insulating substrates
• H01L 23/552 - Protection against radiation, e.g. light

Abstract

An apparatus, a system, and a communication device. The apparatus includes a substrate and a circuit formed on the substrate. The circuit includes a first transformer having first input nodes and first output nodes. The circuit further includes a second transformer having second input nodes and second output nodes. The first input nodes of the first transformer and the second input nodes of the second transformer are connected. At least one first output node of the first output nodes of the first transformer and at least one second output node of the second output nodes of the second transformer are connected. The circuit further includes a first capacitor connected to one of the first output nodes of the first transformer and to one of the second output nodes of the second transformer. The first capacitor is connected to a first ground.

IPC Classes  ?

• H03K 3/012 - Modifications of generator to improve response time or to decrease power consumption
• H03H 11/32 - Balance-unbalance networks

Abstract

A system includes memory and at least one processor coupled to the memory. The processor processes a received bitstream to generate quantized data and control data. The process also generates decoded motion data based on a portion of the control data, fetches one or more reference blocks associated with a current prediction unit (PU) of a DPR based on the decoded motion data and generates refined motion data based on the decoded motion data and the one or more reference blocks. The processor further generates one or more inter-prediction blocks based on the refined motion data and the one or more reference blocks by performing a motion compensation operation.

IPC Classes  ?

• H04N 19/513 - Processing of motion vectors
• H04N 19/119 - Adaptive subdivision aspects e.g. subdivision of a picture into rectangular or non-rectangular coding blocks
• H04N 19/137 - Motion inside a coding unit, e.g. average field, frame or block difference
• H04N 19/423 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals - characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements
• H04N 19/88 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using pre-processing or post-processing specially adapted for video compression involving rearrangement of data among different coding units, e.g. shuffling, interleaving, scrambling or permutation of pixel data or permutation of transform coefficient data among different blocks

Abstract

Described herein are systems and methods related to a converter includes a number of unit cells. The unit cells each include a first transistor and a second transistor. The first transistor is coupled in series with an output of the unit cell, and the second transistor is configured to have a capacitive characteristic that reduces a non-linear capacitive characteristic of the first transistor. The converter can be a voltage or current mode digital to analog converter.

IPC Classes  ?

• H03M 1/06 - Continuously compensating for, or preventing, undesired influence of physical parameters

Abstract

A manufacturing method of a chip package, performing a coupling of first and second interconnecting layers between one or more top dies and one or more bottom dies via hybrid copper bonding; depositing a material to at least partially cover the second interconnecting layer; thinning a second surface of the one or more top dies, wherein both the one or more top dies and the material define a continuous surface; coupling a first surface of a support die to the second surface of at least one of the one or more top dies; thinning a second surface of at least one of the one or more bottom dies; and coupling the second surface of at least one of the one or more bottom dies to a plurality of microbumps.

IPC Classes  ?

• H01L 23/46 - Arrangements for cooling, heating, ventilating or temperature compensation involving the transfer of heat by flowing fluids
• H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements

Abstract

An integrated circuit including an optical waveguide is described. The optical waveguide includes cascaded Mach-Zehnder interferometers (MZI) filters. The cascaded MZI filters are used for multiplexing and/or demultiplexing. The cascaded MZI filters achieve a desired level of center waveguide accuracy. The center waveguide accuracy may be achieved by any one or more of the following: trimming the MZI filters to a target thickness, interleaving phase sections of the cascaded MZI filters, nonlinear tapers, compact directional couplers, dummification, and/or phase sections with widths selected for phase compensation.

IPC Classes  ?

• G02B 6/12 - Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
• G02B 6/122 - Basic optical elements, e.g. light-guiding paths
• G02B 6/125 - Bends, branchings or intersections
• G02B 6/132 - Integrated optical circuits characterised by the manufacturing method by deposition of thin films
• G02F 1/21 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour by interference

Abstract

Systems and methods are related to a successive approximation analog to digital converter (SAR ADC). The SAR ADC includes a sample and digital to analog conversion (DAC) circuit configured to sample an input voltage, a comparator circuit coupled to the sample and DAC circuit and having an output, a first set of storage circuits, and a comparator driver. The comparator driver is disposed between the output and the first set of storage circuits (e.g., ratioed latched. The first set of storage circuits are coupled to the comparator circuit and the sample and DAC circuit. The comparator driver can include a first driver and second driver. The first driver is coupled to a first input of a first storage circuit of the first set of storage circuits, and the second driver is coupled to first inputs of a second set of storage circuits within the first set of storage circuits.

IPC Classes  ?

• H03M 1/06 - Continuously compensating for, or preventing, undesired influence of physical parameters

Abstract

A system is disclosed. The system includes a first circuit that includes a first receiver configured to receive a wireless power input, a first conductor, and operably coupled to the first receiver, and a switch network operably coupled to the first conductor configured to rectify the wireless power input and generate a rectified voltage. The first circuit further includes a first field effect transistor operably coupled to the first conductor and configured to receive a portion of the wireless power input from the first conductor and output an output voltage back to the first conductor based upon a gate input. In one or more embodiments, the first circuit further includes a first controller configured to determine if the rectified voltage is greater than a voltage threshold and transmit a transmission of the gate input to the first field effect transistor if the rectified voltage is above the voltage threshold

IPC Classes  ?

• H02J 50/12 - Circuit arrangements or systems for wireless supply or distribution of electric power using inductive coupling of the resonant type
• H02J 7/02 - Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries for charging batteries from ac mains by converters
• H02J 50/80 - Circuit arrangements or systems for wireless supply or distribution of electric power involving the exchange of data, concerning supply or distribution of electric power, between transmitting devices and receiving devices
• H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
• H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load

Abstract

The method includes providing at least one bit in an extended capability information element of a beacon frame or a probe response frame used during association of an access point and a station. The at least one bit indicates availability or unavailability of the access point to provide service to the station. The method also includes receiving the beacon frame or the probe response frame and cancelling the association in response to the at least one bit indicating the unavailability of the access point to provide the service to the station.

IPC Classes  ?

• H04W 48/16 - Discovering; Processing access restriction or access information
• H04W 8/22 - Processing or transfer of terminal data, e.g. status or physical capabilities
• H04W 72/08 - Wireless resource allocation based on quality criteria

Abstract

A device is provided that includes a counter circuit configured to count cycles of an input clock signal and to generate an output clock signal periodically based on a cycle count of the input clock signal; a multi-phase clock generator configured to generate a plurality of multi-phase clock signals from a system clock signal; a multiplexer circuit coupled to the multi-phase clock generator and configured to provide a multi-phase clock signal selected from the plurality of multi-phase clock signals to the counter circuit as the input clock signal; and a selection circuit configured to provide a selection signal to the multiplexer circuit periodically to switch the multi-phase clock signal provided to the counter circuit from a current multi-phase clock signal to a next multi-phase clock signal selected from the plurality of multi-phase clock signals.

IPC Classes  ?

• H03K 3/012 - Modifications of generator to improve response time or to decrease power consumption
• G06F 1/08 - Clock generators with changeable or programmable clock frequency
• H03K 21/02 - Input circuits

Abstract

A device includes integer multiplier circuits, a multiplexer circuit configured to provide portions of mantissas of a set of first data elements having a floating-point data type and portions of mantissas of a set of second data elements having the floating-point data type to respective integer multiplier circuits, wherein each integer multiplier circuit is configured to multiply a respective portion of the mantissa of a first data element by a respective portion of the mantissa of a second data element to generate a partial product. The device further includes output circuits configured to generate an output data element based on the partial products generated by the integer multiplier circuits and exponents of the set of first data elements and of the set of second data elements. The multiplexer circuit is further configured to bypass providing least-significant portions of the mantissas of the set of first data elements to integer multiplier circuits for multiplication with least-significant portions of the mantissas of the set of second data elements.

IPC Classes  ?

• G06F 7/483 - Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers
• G06F 7/544 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices for evaluating functions by calculation
• G06F 7/74 - Selecting or encoding within a word the position of one or more bits having a specified value, e.g. most or least significant one or zero detection, priority encoders

Abstract

A wireless power transfer device may include a circuit couplable with a coil to transmit or receive a first signal providing wireless power through the coil. The first signal may be modulated with second signals. A packet within any of the second signals may include first bits associated with a preamble and second bits associated with data. The device may further include a controller to measure temporal variations of at least one of the first signal, a rectified version of the first signal, or the one or more second signals. The controller may further determine thresholds for distinguishing between bits in the packet based on the temporal variations. The device may further demodulate the signals using the one or more thresholds to identify the preamble of the packet and extract the second bits associated with data from the packet when the preamble of the packet is identified.

IPC Classes  ?

• H02J 50/80 - Circuit arrangements or systems for wireless supply or distribution of electric power involving the exchange of data, concerning supply or distribution of electric power, between transmitting devices and receiving devices
• H04B 5/00 - Near-field transmission systems, e.g. inductive loop type
• H04L 27/04 - Modulator circuits; Transmitter circuits
• H04L 27/12 - Modulator circuits; Transmitter circuits

Abstract

An apparatus may include a first clock generator configured to receive an input clock signal, and generate two or more first-level clock signals of a track-and-hold circuit, a phase interpolator configured to generate an interpolated clock signals, wherein the interpolated clock signal is based on the two or more first-level clock signals, and a second clock generator configured to generate two or more second-level clock signals based on the interpolated clock signal, wherein the phase of the two or more second-level clock signals relative to the phase of a respective first-level clock signal is determined, at least in part, by the phase of the interpolated clock signal.

IPC Classes  ?

• H03M 1/06 - Continuously compensating for, or preventing, undesired influence of physical parameters
• G06F 1/06 - Clock generators producing several clock signals
• H03K 5/13 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
• H03L 7/087 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
• H03K 5/00 - Manipulation of pulses not covered by one of the other main groups of this subclass

Abstract

Novel solutions for calibration of a digital-to-analog converter (DAC). Some solutions allow for the calibration of a DAC without an isolation switch and/or calibration based on signal measurements taken at the output stage of a device comprising the DAC.

IPC Classes  ?

• H03M 1/10 - Calibration or testing

Abstract

Described herein are related to a device including a digital-to-analog converter (DAC) configured to convert a digital signal into an analog signal. In one aspect, the device includes a first circuit configured to generate a first signal. In one aspect, the device includes a second circuit coupled to the first circuit. The second circuit may be configured to generate a second signal, based on the first signal. The second signal may have a first edge according to the first signal. In one aspect, the device includes a third circuit coupled to the second circuit. The third circuit may be configured to generate a third signal having a second edge, in response to the first edge of the second signal. In one aspect, an amplitude of the third signal may correspond to one bit.

IPC Classes  ?

• H03M 1/10 - Calibration or testing

Abstract

A digital-to-analog converter (DAC) calibration system comprising: a DAC configured to convert digital input to an analog input, a detector configured to measure the analog outputs of the plurality of DAC unit cells and combine the analog outputs to create an overall analog output signal, and a calibration engine. The calibration engine is configured to calibrate the DAC.

IPC Classes  ?

• H03M 1/10 - Calibration or testing

Abstract

Described herein are related to a calibration circuit for a digital to analog converter (DAC) including a plurality of DAC cells. The calibration circuit including a chopper circuit configured to receive a first signal from a first DAC cell of the plurality of DAC cells and receive a second signal from a second DAC cell of the plurality of DAC cells. The calibration circuit including a comparator circuit configured to receive the first signal and the second signal from the chopper circuit, provide a third signal indicating at least one of the first signal or the second signal. The calibration circuit also including a second circuit configured to offset a first voltage associated with the comparator circuit and configured to offset a second voltage associated with the chopper circuit.

IPC Classes  ?

• H03M 1/10 - Calibration or testing

Abstract

Described herein are related to a device for communication. In one aspect, the device a first circuit configured to generate a signal. In one aspect, the device includes a port. In one aspect, the device includes a set of switches. Each switch of the set of switches may be coupled in parallel between the first circuit and the port. In one aspect, the device includes a second circuit configured to enable a subset of the set of switches, according to an amplitude of the signal.

IPC Classes  ?

• H03H 11/24 - Frequency-independent attenuators

Abstract

A wireless power transfer device may include a first circuit configured to be connected in series with a coil, a second circuit, and a switch, where switching a state of the switch may selectively couple the second circuit to the first circuit. The switch may be driven by a pulse width modulation (PWM) signal. The device may further include a PWM controller to receive measurements indicative of wireless power transferred through the coil, generate the PWM signal, and adjust the PWM signal to provide the wireless power transferred through the coil according to a selected metric.

IPC Classes  ?

• H02J 50/10 - Circuit arrangements or systems for wireless supply or distribution of electric power using inductive coupling
• H02J 7/00 - Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries

Abstract

Described herein are related to a device for communication. In one aspect, the device includes a first circuit configured to generate a first signal and a second signal at a first frequency, according to a third signal at a second frequency higher than the first frequency. The first signal and the second signal may have opposite phases with each other. In one aspect, the device includes a second circuit configured to provide a difference between the first signal and the second signal as a fourth signal. In one aspect, the device includes a third circuit configured to provide the first signal to the second circuit, and resonate at a third frequency between the first frequency and the second frequency. In one aspect, the device includes a fourth circuit configured to provide the second signal to the second circuit, and resonate at the third frequency.

IPC Classes  ?

• H04B 1/00 - TRANSMISSION - Details of transmission systems not characterised by the medium used for transmission
• H04B 1/04 - Circuits

Abstract

A system for detecting angle-of-arrival (AoA) includes a first device and at least one second device. The first device transmits a Bluetooth (BT) packet, and the second device receives the BT packet and determines an AoA of the BT packet. The second device includes a first radio-frequency (RF) antenna to receive a first RF signal and a second RF antenna to receive a second RF signal. The second device also includes a first BT core and a second BT-core and a processing circuit. The first BT core is coupled to the first RF antenna and is used to generate a first signal based on the first RF signal. The second BT core is coupled to the second RF antenna and generates a second signal based on the second RF signal. The processing circuit measures a phase difference between the first signal and the second signal and determines the AoA based on the phase difference.

IPC Classes  ?

• G01S 3/48 - Systems for determining direction or deviation from predetermined direction using antennas spaced apart and measuring phase or time difference between signals therefrom, i.e. path-difference systems the waves arriving at the antennas being continuous or intermittent and the phase difference of signals derived therefrom being measured
• G01S 5/04 - Position of source determined by a plurality of spaced direction-finders
• G01S 5/02 - Position-fixing by co-ordinating two or more direction or position-line determinations; Position-fixing by co-ordinating two or more distance determinations using radio waves
• H04W 4/80 - Services using short range communication, e.g. near-field communication [NFC], radio-frequency identification [RFID] or low energy communication
• H04W 4/33 - Services specially adapted for particular environments, situations or purposes for indoor environments, e.g. buildings
• H04L 67/52 - Network services specially adapted for the location of the user terminal

Abstract

Novel tools and techniques are provided for implementing novel semiconductor package interconnection structure(s) between package substrate and PCB. In various embodiments, a semiconductor device comprises: a substrate; a plurality of posts; a plurality of solder anchor portions; and a plurality of solder balls. Each post is coupled at a proximal end to a conductive point on a layer of the substrate, and has a length extending along its axis between its proximal and distal ends and a width orthogonal to the length. Each solder anchor portion is coupled to the distal end of a corresponding post, and has a width that is larger than the width of a distal end of a pillar portion of the corresponding post. Each solder ball is disposed on and around a corresponding solder anchor portion, the solder balls and corresponding posts forming conductive interconnects between corresponding substrate conductive points and corresponding PCB contact points.

IPC Classes  ?

• H01L 23/498 - Leads on insulating substrates
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups

Abstract

A package, and method for building the package is disclosed. The package includes a substrate having a first surface. The package further includes a die having opposing first and second surfaces, and a lateral surface, with the second surface of the die coupled to the first surface of the substrate. The package further includes a stiffener element having a first surface and a lateral surface, with the first surface of the stiffener element coupled to the first surface of the substrate. The package further includes molding material disposed on the first surface of the substrate and the lateral surface of the die. The coefficient of thermal expansion (CTE) value of the molding material is greater than a CTE value of the die. The first molding surface of the molding material is coplanar with the first surface of the die.

IPC Classes  ?

• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H01L 23/367 - Cooling facilitated by shape of device

Abstract

A resonator may include two or more electrodes and one or more piezoelectric materials, where the two or more electrodes and the one or more piezoelectric materials are distributed in a direction. Further, at least one of the two or more electrodes may have a constant thickness along the direction and may include two or more regions having different densities, where the two or more regions are distributed in a plane normal to the direction and the two or more regions have the constant thickness along the direction.

IPC Classes  ?

• H03H 9/205 - Constructional features of resonators consisting of piezoelectric or electrostrictive material having multiple resonators
• H03H 3/02 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
• H03H 9/13 - Driving means, e.g. electrodes, coils for networks consisting of piezoelectric or electrostrictive materials

Abstract

A module is described. The module includes two dies which are stacked over a top insulating layer of a PCB. When both dies are be connected to the PCB through a copper pillar, the top die has a taller interconnect and the bottom die has a shorter interconnect. To further reduce a height of the module, the bottom die and/or the top die may be placed into a cavity of the PCB and a bulk silicon layer of the top die may be grinded away.

IPC Classes  ?

• H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different main groups of groups , or in a single subclass of , , e.g. forming hybrid circuits
• H05K 1/18 - Printed circuits structurally associated with non-printed electric components
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/498 - Leads on insulating substrates
• H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement

Abstract

Novel tools and techniques are provided for implementing a substrate with an elastomer layer. The substrate might include one or more interconnects and an elastomer layer comprising at least one conductor. In some instances, the at least one conductor of the elastomer layer couples to at least one of the one or more interconnects of the substrate. Additionally, the at least one conductor is configured to couple at least one of the one or more interconnects of the substrate to a circuit board.

IPC Classes  ?

• H01L 23/498 - Leads on insulating substrates
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups

Abstract

A device includes integer multiplier circuits and a multiplexer circuit provides portions of mantissas of feature elements and portions of mantissas of weight elements to respective integer multiplier circuits, wherein the feature elements and the weight elements are floating-point data types, and wherein each integer multiplier circuit multiplies a respective portion of the mantissa of a feature element by a respective portion of the mantissa of a weight element to generate a partial product. A first shift circuit shifts bits of the partial products based on exponents of the feature elements and of the weight elements, and a first integer adder circuit adds the shifted partial products to generate a sum. A composition circuit generates an output element based on the sum generated by the first integer adder circuit, the exponents of the plurality of feature elements, and the exponents of the plurality of weight elements.

IPC Classes  ?

• G06F 7/544 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices for evaluating functions by calculation

Abstract

A device includes a direct memory access (DMA) controller comprising DMA channels, a bridge circuit configured to couple the DMA channels to memory channels coupled to respective memory modules, and a local memory unit. The DMA controller is configured to transfer tensor data between the local memory unit and the memory modules via the DMA channels and the memory channels using concurrent data transactions, the tensor data is stored and addressed as parts of a single tensor in the local memory unit, and the tensor data is interleaved onto the memory modules and is stored and addressed as sub-tensors in respective memory modules.

IPC Classes  ?

• G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal

Abstract

Tools and techniques for a semiconductor package providing side wall interconnections are provided. An apparatus includes two or more die layers that are bonded together, the first 3D stacked die package comprising a top surface, bottom surface, and one or more side walls. A first side wall of the one or more side walls includes two or more side wall pads, wherein each side wall pad of the two or more side wall pads is coupled to an interconnect of a respective die layer of the two or more die layers.

IPC Classes  ?

• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
• H01L 23/498 - Leads on insulating substrates
• H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices

Abstract

A semiconductor package with integrated side wall antennas is provided. An apparatus includes two or more die layers that are bonded together, each of the two or more die layers comprising a top surface, bottom surface, and one or more side walls. A first side wall of the one or more side walls includes a first antenna array, the first antenna array comprising a first plurality of antenna array elements formed in at least one of the two or more die layers, wherein the first plurality of antenna array elements is at least partially exposed at the first side wall.

IPC Classes  ?

• H01Q 1/22 - Supports; Mounting means by structural association with other equipment or articles
• H01Q 9/04 - Resonant antennas
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 23/498 - Leads on insulating substrates
• H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices

Abstract

A circuit for inductive peaking may include a driver, an inverter, a resistor between an output node of the driver and an input node of the inverter and a switch. For example, a first node of the resistor may be connected to the output node of the driver and a second node of the resistor may be connected to the input node of the inverter. The switch may be connected between an output node of the inverter and the first node of the resistor. An input node of the driver may correspond to an input node of the circuit and the output node of the driver may correspond to an output node of the circuit.

IPC Classes  ?

• H03F 1/48 - Modifications of amplifiers to extend the bandwidth of aperiodic amplifiers

Abstract

A rectifier modulates a signal in a rectifier by turning on a low side field effect transistor to produce a load at a coil network in response to a low side field effect transistor in an alternative diagonal being on. The system measures signal quality to determine a necessary modulation depth for ASK communication; then determines a switching time and magnitude of a ballast signal to apply to the low side field effect transistor to achieve that modulation depth.

IPC Classes  ?

• H02M 7/217 - Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
• H02M 1/32 - Means for protecting converters other than by automatic disconnection
• H02J 50/10 - Circuit arrangements or systems for wireless supply or distribution of electric power using inductive coupling
• H04L 27/04 - Modulator circuits; Transmitter circuits

Abstract

A device includes a memory storing a first lookup table of entries each comprising a starting index value and a number of samples corresponding to a respective segment of a function and a second lookup table of entries each comprising a respective sampled mantissa from the function. An interpolation logic circuit retrieves from the first lookup table a starting index value and a number of samples corresponding to a segment of the function corresponding to an input mantissa from an input floating-point element, retrieves from the second lookup table a first sampled mantissa and a second sampled mantissa based on the starting index value and the number of samples retrieved from the first lookup table and the input mantissa, and interpolates an output mantissa.

IPC Classes  ?

• G06F 7/499 - Denomination or exception handling, e.g. rounding or overflow
• G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode

Abstract

Novel tools and techniques are provided for implementing edge seal for bonded stacks of different size semiconductor devices. In various embodiments, a semiconductor device is provided that includes a composite structure and a sealant material. The composite structure includes two or more semiconductor devices that form a stacked configuration with one semiconductor device being disposed on or over each of one or more other semiconductor devices (of different size compared with that of the one semiconductor device) and with interface components of the one semiconductor device being bonded with corresponding interface components to each of the one or more other semiconductor devices in the stacked configuration. The sealant material is disposed along one or more surface portions of the composite structure to cover a region including at least portions of side surfaces of the composite structure that extend to cover at least each interface portion between stacked semiconductor devices.

IPC Classes  ?

• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings

Abstract

A system and method for monitoring signal quality metrics coupled with closed-loop control improves rectifier signal quality and stability. The closed-loop control passes the metric through a high-pass filter and captures error values. This signal is then passed to a controller to adjust rectifier settings. The measured signal, where signal quality is derived could be VRECT, FCLK, network coil measurements, is used for ASK demodulation, or the like. The controller identifies noise levels and noise types in real-time, and sets parameters of the rectifier to preserve system stability. The controller may set baud rates and preamble thresholds in a wireless power transfer system in response to identified noise levels and types.

IPC Classes  ?

• H02M 7/217 - Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
• H02J 50/10 - Circuit arrangements or systems for wireless supply or distribution of electric power using inductive coupling
• H02J 50/70 - Circuit arrangements or systems for wireless supply or distribution of electric power involving the reduction of electric, magnetic or electromagnetic leakage fields

Abstract

Systems and methods are provided for congestion notification in network communications, including multi-protocol label switching (MPLS) network communications. In one or more implementations, an MPLS node that receives a data packet and detects congestion may generate a cloned copy of the data packet, add congestion information, such as a congestion notification label and a congestion notification header, into the data packet, and forward the cloned copy with the congestion notification label and the congestion notification header to a next MPLS node. The next MLPS node may, responsive to receiving the cloned copy with the congestion information, provide one packet with the congestion information to a subsequent node, and another packet with the congestion information to the node from which the cloned copy was received.

IPC Classes  ?

• G06F 15/16 - Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
• G06F 9/54 - Interprogram communication
• H04L 29/06 - Communication control; Communication processing characterised by a protocol
• H04L 45/50 - Routing or path finding of packets in data switching networks using label swapping, e.g. multi-protocol label switch [MPLS]
• H04L 47/122 - Avoiding congestion; Recovering from congestion by diverting traffic away from congested entities
• H04L 45/24 - Multipath

Abstract

A resonator may include a first electrode, a second electrode, and a piezoelectric material between the first electrode and the second electrode, where the piezoelectric material is formed by fabricating the piezoelectric material with a compression axis vector (C-axis vector) oriented along a first direction and applying an electric field across the piezoelectric material to modify a direction of the C-axis vector to be oriented along a second direction. The second direction may be antiparallel to the first direction.

IPC Classes  ?

• H03H 9/13 - Driving means, e.g. electrodes, coils for networks consisting of piezoelectric or electrostrictive materials
• H03H 9/205 - Constructional features of resonators consisting of piezoelectric or electrostrictive material having multiple resonators
• H03H 9/02 - Networks comprising electromechanical or electro-acoustic elements; Electromechanical resonators - Details
• H03H 9/54 - Filters comprising resonators of piezoelectric or electrostrictive material

Abstract

A rectifier includes digital timers to control FET switching rather than direct measurement of current and/or voltage. The digital timers control turn-off time to compensate for a delay produced by comparators in the rectifier. The digital timers are adjusted over multiple cycles to arrive at a turn-off time that produces zero current turn-off. The digital timers may be periodically or continuously readjusted based on a preceding set of cycles. Adaptive turn-off via digital timers is useful for discontinuous conduction mode suppression.

IPC Classes  ?

• H02M 7/5387 - Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
• H02M 1/088 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
• H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion

Abstract

An interposer, and integrated circuit including an interposer, has a lower surface adapted for bump mounting and an upper surface adapted for copper bonding. An interposer layer includes active interposers and passive interposers. Bridges connect interposers in the interposer layer to produce a functionally large interposer from smaller interposer dies. A core may overlap more than one interposer in the interposer layer. Active interposers are disposed around the edge of the core with passive interposers beneath the core to facilitate heat dissipation.

IPC Classes  ?

• H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
• H01L 23/498 - Leads on insulating substrates

Abstract

An RF multiplexing switching circuit for an RF front end (e.g., for a mobile communications device transmitting/receiving in the RF region) includes a set of RF inputs and a set of RF outputs outputting to RF filters, the RF inputs and outputs connected by signal paths. The switching circuit includes series switches for creating conducting signal paths for transmitting/receiving RF signals between the RF inputs and outputs, and a set of common shared shunt switches (e.g., for M RF inputs and N RF outputs, M+X shunt switches, where X

IPC Classes  ?

• H04B 1/00 - TRANSMISSION - Details of transmission systems not characterised by the medium used for transmission
• H04B 1/04 - Circuits
• H04B 1/30 - Circuits for homodyne or synchrodyne receivers

Abstract

A method is provided that includes selecting, by a hardware module, a current parameter set from one or more parameter sets; reading, by the hardware module, a watermark graphic from a location in memory indicated by a parameter in the current parameter set, wherein access to the location in memory is restricted to the hardware module and one or more first trusted applications; blending, by the hardware module, the watermark graphic with a frame of video content; and providing, by the hardware module, the blended frame to a video output.

IPC Classes  ?

• G06T 1/00 - General purpose image data processing
• G06T 3/40 - Scaling of a whole image or part thereof
• G06T 7/11 - Region-based segmentation
• G06T 5/00 - Image enhancement or restoration

Abstract

A device includes multiplication and accumulation (MAC) cells, a feature processor circuit, and a weight processor circuit. The feature processor circuit receives, from a memory input units each comprising input feature elements from different respective channels of an input tensor, generates extended feature units each comprising an input feature element from each of the input units and from a common channel of the input tensor, and provides the extended feature units to respective MAC cells. The weight processor circuit receives, from the memory, weight units each comprising weight elements from different respective channels of a kernel, generates extended weight units each comprising a weight element from each of the weight units and from a common channel of the kernel, and provides the extended weight units to respective MAC cells. Each MAC cell is configured to multiply the input feature elements of the extended feature unit provided by the feature processor circuit by the respective weight elements of the extended weight unit provided by the weight processor circuit in parallel and output a sum of the products.

IPC Classes  ?

• G06F 7/544 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices for evaluating functions by calculation

Abstract

Systems and methods are related to daltonizing images. An image decoder can receive a first image and a second image. The images can be associated with a first metadata and second metadata, respectively. The image decoder and determine a color mapping for the first image and the second image based on the first metadata and the second metadata. The image decoder can process the images in a color vision deficiency (CVD) processor and based on the images and their associated metadata generate daltonized images which are sent to a display.

IPC Classes  ?

• G06V 10/56 - Extraction of image or video features relating to colour
• G06F 3/14 - Digital output to display device

Abstract

A system for automatic in-band MACsec encryption key updates includes a physical layer retimer device attachable to a host system, the host system connected to a peer device via a secure Ethernet link incorporating egress and ingress channels for encrypted data traffic. The host system generates encryption key updates for each secure egress or ingress channel, sending the key updates in-band as Ethernet packets via the secure egress channels. Key updates are identified and extracted from egress data traffic by the retimer device, which identifies the specific encryption key (e.g., corresponding to a specific egress channel or ingress channel) for which each key update is intended. Security blocks of the retimer device update the appropriate encryption key corresponding to each key update. The retimer device generates an acknowledgement packet for each successful key update, sending the acknowledgement packet back to the host device to confirm the key update.

IPC Classes  ?

• H04L 9/08 - Key distribution
• H04L 9/40 - Network security protocols

Abstract

One or more layout techniques may be used to balance a current sense circuit. The current sense circuit may include upstairs resistors for an amplifier which are formed of polysilicon material. The upstairs resistors may be arranged symmetrically about one or more stress gradients for improving an accuracy of the current sense circuit. The stress gradients may include stress gradients about an axis and stress gradients from a die edge.

IPC Classes  ?

• G01R 19/00 - Arrangements for measuring currents or voltages or for indicating presence or sign thereof

Abstract

A structure is described which includes two amplifiers in parallel. A first amplifier is considered an always-on amplifier. The always on amplifier provides continual measurements of a current (Isns) across an integrated polysilicon resistor for one or more analog control loops. A second amplifier is considered a switched amplifier. The switched amplifier provides measurements of the current (Isns) for one or more digital control loops. The switched amplifier is switched by one or more switches for performing offset measurements with high accuracy.

IPC Classes  ?

• G01R 19/00 - Arrangements for measuring currents or voltages or for indicating presence or sign thereof
• H02J 50/10 - Circuit arrangements or systems for wireless supply or distribution of electric power using inductive coupling
• H03F 3/45 - Differential amplifiers

Abstract

An integrated circuit for measuring current while receiving wireless power is described. The integrated circuit measures a current across a resistor by an amplifier. A gain of the amplifier is based on a pair of matched upstairs resistors and a pair of matched downstairs resistors. The pair of matched upstairs resistors may include an offset in resistance. The integrated circuit includes a switch matrix with switches coupled between the integrated resistor and the pair of matched upstairs resistors. The offset for the pair of matched upstairs resistors may be measured by selectively controlling the switches.

IPC Classes  ?

• H03F 3/217 - Class D power amplifiers; Switching amplifiers
• H02J 50/10 - Circuit arrangements or systems for wireless supply or distribution of electric power using inductive coupling
• H02J 50/60 - Circuit arrangements or systems for wireless supply or distribution of electric power responsive to the presence of foreign objects, e.g. detection of living beings

Abstract

A system is disclosed. The system includes a first circuit that includes a first receiver configured to receive a wireless power input, a first conductor, and operably coupled to the first receiver, and a switch network operably coupled to the first conductor configured to rectify the wireless power input and generate a rectified voltage. The first circuit further includes a first field effect transistor operably coupled to the first conductor and configured to receive a portion of the wireless power input from the first conductor and output an output voltage back to the first conductor based upon a gate input. In one or more embodiments, the first circuit further includes a first controller configured to determine if the rectified voltage is greater than a voltage threshold and transmit a transmission of the gate input to the first field effect transistor if the rectified voltage is above the voltage threshold.

IPC Classes  ?

• H02J 50/12 - Circuit arrangements or systems for wireless supply or distribution of electric power using inductive coupling of the resonant type
• H02J 50/80 - Circuit arrangements or systems for wireless supply or distribution of electric power involving the exchange of data, concerning supply or distribution of electric power, between transmitting devices and receiving devices
• H02J 7/02 - Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries for charging batteries from ac mains by converters
• H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
• H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters

Abstract

A multi-link device may be configured to initiate transmission of a first data unit on a first wireless link of a first multi-link device, and request transmission of a trigger from a second multi-link device on a second wireless link. In response to receiving the trigger, the multi-link device may align a last symbol end time of a response transmission on the second wireless link with a last symbol end time of the first data unit being transmitted on the first multi-link device.

IPC Classes  ?

• H04W 56/00 - Synchronisation arrangements
• H04W 76/15 - Setup of multiple wireless link connections
• H04W 74/08 - Non-scheduled access, e.g. random access, ALOHA or CSMA [Carrier Sense Multiple Access]

Abstract

A wireless power system is described. The wireless power system includes a coil for receiving and transmitting wireless power, an integrated circuit, and one or more batteries. The integrated circuit includes a rectifier circuit, a current sense amplifier circuit, a calibration circuit, and a voltage regulator. The rectifier circuit receives alternating current from the coil and generates a rectified voltage when the wireless power system is in receive mode and further transmits alternating current to the coil when the wireless power system is in transmit mode. The current sense amplifier circuit detects a current flowing between the rectifier and the voltage regulator. The calibration circuit generates a voltage which is used by firmware of the integrated circuit to calibrate for aging of resistors within the current sense amplifier circuit.

IPC Classes  ?

• G01R 35/00 - Testing or calibrating of apparatus covered by the other groups of this subclass
• H02J 50/10 - Circuit arrangements or systems for wireless supply or distribution of electric power using inductive coupling
• H03F 3/45 - Differential amplifiers
• G01R 19/25 - Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques

Abstract

A method which comprises storing a readable identifier, which identifies a semiconductor product, and a unique key, being unique for said semiconductor product or for a group of semiconductor products, in a memory of said semiconductor product, generating an initial security data structure, said initial security data structure depending on a root key and on said unique key, wherein both said root key and said unique key are assigned to said semiconductor product, and wherein said initial security data structure is assigned to said readable identifier, and supplying said initial security data structure to said semiconductor product for further processing.

IPC Classes  ?

• G06F 21/73 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by creating or determining hardware identification, e.g. serial numbers
• G06F 21/62 - Protecting access to data via a platform, e.g. using keys or access control rules
• G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities

Abstract

In some aspects, the disclosure is directed to methods and systems for a flexible type-length-value (TLV) parser and identification map that may be used to quickly identify TLV sequences of packet headers for subsequent processing in a pipeline. A flexible TLV bus may provide a secondary path for the TLV header and identification map, allowing for subsequent processing stages to read, process, modify, delete, or otherwise utilize individual TLV sequences within the header.

IPC Classes  ?

• H01M 10/0587 - Construction or manufacture of accumulators having only wound construction elements, i.e. wound positive electrodes, wound negative electrodes and wound separators

Abstract

A semiconductor chip for implementing aggregated flow detection and management includes a number of pipes, where each pipe is coupled to a portion of ports on the semiconductor chip that are to receive data packets. A logic is coupled to the pipes and is used to detect and manage an elephant flow. The elephant flow-detection and management logic includes a flow table and a byte counter.

IPC Classes  ?

• H04L 47/2483 - Traffic characterised by specific attributes, e.g. priority or QoS involving identification of individual flows
• H04L 45/24 - Multipath
• H04L 47/6275 - Queue scheduling characterised by scheduling criteria for service slots or service orders based on priority
• H04L 49/109 - Integrated on microchip, e.g. switch-on-chip

Abstract

In some aspects, the disclosure is directed to methods and systems for signaling and decoding of punctured sub-bands in a trigger-based PPDU. In one aspect, at least one of the communication interface or the processing circuitry of a wireless communication device is configured to generate a trigger frame that includes signaling indicating that at least one other wireless communication device is allowed to reduce a bandwidth of an allocated resource unit (RU) for transmitting data via a communication channel; transmit, via the communication channel, the trigger frame to at least one other wireless communication device; receive, via the communication channel and from the at least one other wireless communication device, an uplink (UL) orthogonal frequency division multiple access (OFDMA) frame including the data; and process the UL OFDMA frame including the data based on the signaling.

IPC Classes  ?

• H04W 72/541 - Allocation or scheduling criteria for wireless resources based on quality criteria using the level of interference
• H04W 72/542 - Allocation or scheduling criteria for wireless resources based on quality criteria using measured or perceived quality

Abstract

Disclosed herein are related to systems and methods for scheduling network operations with synchronized idle slots. In one aspect, a system includes a first data path to provide a first set of packets and a second data path to provide a second set of packets. The system also includes an arbiter to arbitrate the first set of packets and the second set of packets. The arbiter may be configured to receive a request for a task, where the task may be performed during a clock cycle. Based on the request, the arbiter may cause a scheduler to schedule a first idle slot for the first data path, and schedule a second idle slot for the second data path. The arbiter may provide the first idle slot and the second idle slot.

IPC Classes  ?

• H04L 47/625 - Queue scheduling characterised by scheduling criteria for service slots or service orders
• H04L 47/20 - Traffic policing

Abstract

Novel tools and techniques are provided for implementing mixed dielectric materials for improving signal integrity of integrated electronics packages or semiconductor packages. In various embodiments, a substrate for a semiconductor device includes: a first layer made of a first material; a second layer made of a second material; and a third layer disposed between the first and second layers, and that is made of a third material different from the first and second materials. In some cases, the first, second, and third layers each contains a plurality of gas-filled regions (e.g., but not limited to, an aerogel core of the third layer and/or polymer resin matrix embedded with hollow silica spheres or aerogel spheres of the first and second layers, or the like). Coaxial ground shields around signal lines in the substrate can be used to improve signal integrity. High dielectric constant lossy lines between signal lines can reduce crosstalk.

IPC Classes  ?

• H01L 23/14 - Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
• H01L 23/498 - Leads on insulating substrates
• H01L 23/66 - High-frequency adaptations
• H01P 3/00 - Waveguides; Transmission lines of the waveguide type
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
• H01P 11/00 - Apparatus or processes specially adapted for manufacturing waveguides or resonators, lines, or other devices of the waveguide type

Abstract

Virtual machine environments are provided in the switches that form a network, with the virtual machines executing network services previously performed by dedicated appliances. The virtual machines can be executed on a single multi-core processor in combination with normal switch functions or on dedicated services processor boards. Packet processors analyze incoming packets and add a services tag containing services entries to any packets. Each switch reviews the services tag and performs any network services resident on that switch. This allows services to be deployed at the optimal locations in the network. The network services may be deployed by use of drag and drop operations. A topology view is presented, along with network services that may be deployed. Services may be selected and dragged to a single switch or multiple switches. The management tool deploys the network services software, with virtual machines being instantiated on the switches as needed.

IPC Classes  ?

• H04L 45/745 - Address table lookup; Address filtering
• H04L 69/22 - Parsing or analysis of headers
• H04L 45/00 - Routing or path finding of packets in data switching networks
• H04L 43/18 - Protocol analysers
• H04L 49/35 - Switches specially adapted for specific applications
• H04L 41/5041 - Network service management, e.g. ensuring proper service fulfilment according to agreements characterised by the time relationship between creation and deployment of a service
• H04L 45/74 - Address processing for routing
• H04L 49/00 - Packet switching elements
• H04L 49/354 - Switches specially adapted for specific applications for supporting virtual local area networks [VLAN]
• H04L 45/021 - Ensuring consistency of routing table updates, e.g. by using epoch numbers
• H04W 88/08 - Access point devices
• H04W 84/12 - WLAN [Wireless Local Area Networks]

Abstract

In some aspects, the disclosure is directed to methods and systems for early termination of multi-user enhanced distributed channel access parameter application for one or more stations or devices. In various implementations, referred to as un-solicited or solicited termination, the multi-user enhanced distributed channel access timeout period may be terminated early by an access point device, or by a non-access point station or device, respectively.

IPC Classes  ?

• H04W 74/04 - Scheduled access

Abstract

An apparatus includes an interposer comprising one or more area array interconnections, the one or more area array interconnections including a first type of area array interconnection and a second type of area array interconnection. The apparatus further includes a first die coupled to the interposer via the first type of area array interconnection, and a second die coupled to the interposer via the second type of area array interconnection, wherein the first type of area array interconnection is different from the second type of area array interconnection.

IPC Classes  ?

• H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices

Abstract

Novel tools and techniques are provided for implementing cantilevered power planes to provide a return current path for high-speed signals. In various embodiments, a semiconductor package includes a substrate core, a plurality of layers, and an AC coupler(s). The plurality of layers includes power, ground, and signal layers each layer disposed on or above the substrate core, each signal layer being disposed between a power layer and a ground layer, the power layer and the ground layer each providing a return path for high frequency (e.g., 1 kHz or greater) signals carried by each signal layer. Each dielectric layer is disposed between and in contact with a pair of power, ground, or signal layer. The AC coupler(s) is coupled to each of a power layer(s) and a ground layer(s), without any portion of any power layer that is near an edge of the substrate core being anchored to the substrate core.

IPC Classes  ?

• H01L 23/498 - Leads on insulating substrates
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
• H01L 23/66 - High-frequency adaptations

Abstract

An apparatus includes a substrate that includes one or more routing layers, and an optical module coupled to the substrate. The optical module includes a photonic integrated circuit (PIC) and electronic integrated circuit (EIC), wherein the photonic integrated circuit is at least partially embedded within the substrate. The apparatus further includes a fiber optic coupler coupled to at least one of the substrate or PIC, wherein the PIC is configured to transmit or receive an optical signal via the fiber optic coupler.

IPC Classes  ?

• G02B 6/42 - Coupling light guides with opto-electronic elements
• G02B 6/43 - Arrangements comprising a plurality of opto-electronic elements and associated optical interconnections

Abstract

In some aspects, the disclosure is directed to methods and systems for an amplifier having common mode feedback inputs. The inputs are coupled to various points within an amplifier wherein a first set of directly coupled common mode feedback inputs join the amplifier one or more nodes, and a second set of capacitively coupled common mode feedback inputs are joined to the amplifier at one or more different nodes.

IPC Classes  ?

• H03F 3/19 - High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only

Abstract

In some aspects, the disclosure is directed to methods and systems for one or more line-drivers configured to selectively operate between a plurality of modes. When operating as a voltage-mode line-driver increased power efficiency may be realized. When operating as a current-mode line-driver, an increased transmission power may be realized. When operating in a dual/additive mode, still further increased transmission power may be realized.

IPC Classes  ?

• H04B 1/40 - Circuits

Abstract

Novel tools and techniques are provided for implementing detection and estimation of direct and reflected navigation satellite (e.g., global navigation satellite system (“GNSS”), etc.) signal parameters in a multipath environment. In various embodiments, logic of semiconductor package that is disposed on a user device concurrently receives a plurality of signals from a satellite(s), each signal travelling along a different path between each satellite(s) and the user device within a multipath environment. The logic identifies two or more signal peaks that fall within a tracking aperture based on analysis of the received signals, and determines peak parameter estimates for each signal peak based on measurements of signal parameters from at least one signal peak. The logic provides the determined peak parameter estimates for each signal peak to a position engine (“PE”) of the user device to calculate a navigation solution (e.g., position, velocity, and/or time, etc.) for the user device.

IPC Classes  ?

• G01S 19/30 - Acquisition or tracking of signals transmitted by the system code related
• G01S 19/37 - Hardware or software details of the signal processing chain
• G01S 19/22 - Multipath-related issues

Abstract

Novel tools and techniques are provided for implementing a semiconductor package or a chip package, and more particularly, for implementing a semiconductor package or a chip package including a core or a multilayer core having one or more variable width vias or one or more offset vias. In various embodiments, an apparatus includes a substrate. The substrate includes a core. The core may include one or more vias extending through the core. At least one via of the one or more vias includes a cross-section that varies along a length of the at least one via as the via extends through the core. The cross-section of the via may vary based on at least one of varying a width of the at least one via or offsetting a first portion of the at least one via from a second portion of the at least one via.

IPC Classes  ?

• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
• H05K 3/42 - Plated through-holes
• H05K 1/02 - Printed circuits - Details
• H05K 3/46 - Manufacturing multi-layer circuits
• H01L 23/498 - Leads on insulating substrates

Abstract

Novel tools and techniques are provided for implementing a novel integrated programmable gain amplifier (“PGA”) and protection circuit. In various embodiments, a circuit is provided that comprises: a PGA, an analog-to-digital converter (“ADC”), and a protection circuit all disposed on the same semiconductor chip. The PGA is configured to receive as input a wireless signal received from an antenna and to output, at its output, an amplified wireless signal based on the wireless signal being amplified by a programmable gain amount. The protection circuit is configured to, in response to detecting a spike in gain at the output of the PGA that exceeds a threshold amplitude, control a decrease in the programmable gain amount to cause a resultant signal at the output of the PGA to be below the threshold amplitude. A normally-open switch may also be added at differential outputs of the PGA to further clamp PGA output.

IPC Classes  ?

• H04B 1/04 - Circuits
• H04B 1/00 - TRANSMISSION - Details of transmission systems not characterised by the medium used for transmission

Abstract

An amplifier may include first and second terminals to receive first and second input signals and a differential amplifier providing differential amplification of the first and second input signals. The differential amplifier may include a first differential amplifier stage to receive the first input signal and a second differential amplifier stage to receive the second input signal. The amplifier may further include a first bias circuit to bias the first differential amplifier stage, where the first bias circuit is connected to the second input terminal to provide anti-phase bias control of the first differential amplifier stage. The amplifier may further include a second bias circuit to bias the second differential amplifier stage, where the second bias circuit is connected to the first input terminal to provide anti-phase bias control of the second differential amplifier stage.

IPC Classes  ?

• H03F 1/02 - Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
• H03F 3/24 - Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
• H03F 3/45 - Differential amplifiers
• H03F 1/56 - Modifications of input or output impedances, not otherwise provided for
• H04B 1/04 - Circuits

Abstract

A resonator may include a first terminal, a second terminal, a resonator between the first terminal and the second terminal, and a reactive element in series with a switch. The reactive element in series with the switch may be connected in parallel with the resonator. The resonator may provide a first set of resonance frequencies when the switch is operated in a non-conducting state and a second set of resonance frequencies when the switch is operated in a conducting state.

IPC Classes  ?

• H03H 9/54 - Filters comprising resonators of piezoelectric or electrostrictive material
• H03H 9/15 - Constructional features of resonators consisting of piezoelectric or electrostrictive material

Abstract

Transmissions in a data center communications network are monitored at a sending computer, the transmission of data packets being controlled by control messages sent by a receiving computer. The monitor at the sending computer measures the time that a burst of data takes to be transmitted from the sending computer to the receiving computer. Based on feedback received from the receiving computer, the monitor at the sending computer calculates one of more estimated completion times for the transmission. The estimated completion times will approximately match the measured completion time if the network is not the bottleneck for communication. When there is a mismatch between the estimated and measured completion times, this is logged and the information is used to trigger analysis to detect the reason and possible causes for the network under-performing.

IPC Classes  ?

• H04L 43/0882 - Utilisation of link capacity
• H04L 43/50 - Testing arrangements
• H04L 43/10 - Active monitoring, e.g. heartbeat, ping or trace-route
• H04L 12/46 - Interconnection of networks
• H04L 45/74 - Address processing for routing

Abstract

Transmissions in a data center communications network are monitored at a sending computer, the transmission of data packets being controlled by control messages sent by a receiving computer. The monitor at the sending computer measures the time that a burst of data takes to be transmitted from the sending computer to the receiving computer. Based on feedback received from the receiving computer, the monitor at the sending computer calculates one of more estimated completion times for the transmission. The estimated completion times will approximately match the measured completion time if the network is not the bottleneck for communication. When there is a mismatch between the estimated and measured completion times, this is logged and the information is used to trigger analysis to detect the reason and possible causes for the network under-performing.

IPC Classes  ?

• H04L 43/08 - Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
• H04L 43/0876 - Network utilisation, e.g. volume of load or congestion level
• H04L 43/12 - Network monitoring probes
• H04L 43/16 - Threshold monitoring

Abstract

A memory system includes a memory stack including a number of memory dies interconnected via copper bonding, a logic die coupled to the memory stack via a copper bonding. The memory system further includes a buffer die extended to provide the copper bonding between the logic die and the memory stack and a silicon carrier layer bonded to the memory stack and the logic die.

IPC Classes  ?

• H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
• H01L 23/367 - Cooling facilitated by shape of device
• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices

Abstract

Systems, methods, and devices for conducting wireless communication are provided. One method includes identifying a location of a device and obtaining spectrum usage data from a database. The spectrum usage data indicates a licensed entity licensed within an area including the location of the device to communicate across a first sub-band of frequencies within a frequency band, and one or more transmission characteristics of the transmissions of the licensed entity. The method further includes determining beam steering characteristics for wireless transmissions of the device within the frequency band using the spectrum usage data. The beam steering characteristics are determined using the transmission characteristics for the licensed entity and configured to reduce interference with the transmissions of the licensed entity within the frequency band caused by the wireless transmissions of the device. The method further includes conducting wireless transmissions over the frequency band using the beam steering characteristics.

IPC Classes  ?

• H04W 72/0453 - Resources in frequency domain, e.g. a carrier in FDMA
• H04W 16/14 - Spectrum sharing arrangements
• H04W 52/36 - Transmission power control [TPC] using constraints in the total amount of available transmission power with a discrete range or set of values, e.g. step size, ramping or offsets
• H04W 52/42 - TPC being performed in particular situations in systems with time, space, frequency or polarisation diversity
• H04W 72/541 - Allocation or scheduling criteria for wireless resources based on quality criteria using the level of interference
• H04W 52/24 - TPC being performed according to specific parameters using SIR [Signal to Interference Ratio] or other wireless path parameters
• H04W 72/044 - Wireless resource allocation based on the type of the allocated resource

Abstract

A method is provided that includes setting, by a controller, a first bit-rate level for a next video segment, and comparing a fill level of a playback buffer to a first threshold. If the fill level of the playback buffer satisfies the first threshold, the first bit-rate level for the next video segment is replaced by setting a second bit-rate level for the next video. A first request is issued to a server for the next video segment encoded at the first bit-rate level or, if the fill level of the playback buffer satisfies the first threshold, encoded at the second bit-rate level and downloading of the requested next video segment and storing the requested video segment in the playback buffer. A decoder decodes the next video segment from the playback buffer for playback on a display device after the next video segment has been downloaded and stored in the playback buffer.

IPC Classes  ?

• H04N 21/44 - Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to MPEG-4 scene graphs
• H04N 21/845 - Structuring of content, e.g. decomposing content into time segments
• H04N 21/437 - Interfacing the upstream path of the transmission network, e.g. for transmitting client requests to a VOD server
• H04N 21/442 - Monitoring of processes or resources, e.g. detecting the failure of a recording device, monitoring the downstream bandwidth, the number of times a movie has been viewed or the storage space available from the internal hard disk
• H04N 21/439 - Processing of audio elementary streams

Abstract

A method for managing network traffic is shown. The method includes establishing a virtual tunnel between a source endpoint and a destination endpoint, the virtual tunnel including a plurality of data flow paths, each of the plurality of data flow streams connecting the source endpoint and the destination endpoint. The method includes providing, via the destination endpoint, a plurality of credits to the source endpoint, the plurality of credits provided via two or more of the plurality of data flow paths. The method includes updating, at the source endpoint, a data transmission sequence based on the received plurality of credits. The method includes providing a plurality of data packets based on the data transmission sequence to the destination endpoint.

IPC Classes  ?

• H04L 47/12 - Avoiding congestion; Recovering from congestion
• H04L 12/46 - Interconnection of networks

Abstract

An interposer is described. The interposer includes a top layer including an array of passive devices integrated into the top layer. A number of the passive devices may be connected to a pad by a trace disposed above the top layer. The number of the passive devices may be selected to achieve a desired property for the array, such as a desired resistance, inductance, or capacitance. The interposer may thus provide an ability to rapidly tune a die coupled to the pad of the interposer based on the arrangement of the trace.

IPC Classes  ?

• H01L 23/66 - High-frequency adaptations
• H01L 23/498 - Leads on insulating substrates
• H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different main groups of groups , or in a single subclass of , , e.g. forming hybrid circuits

Abstract

An apparatus includes a first substrate comprising one or more first interconnection layers, wherein a first die is coupled to a first side of the first substrate, and a second substrate comprising one or more second interconnection layers. The second die may be coupled to a first side of the second substrate, and a third die is coupled to a second side of the second substrate. The first substrate and the second substrate may be stacked together.

IPC Classes  ?

• H01L 23/528 - Layout of the interconnection structure
• H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
• H01L 23/498 - Leads on insulating substrates
• H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement

Abstract

A wireless power transfer device may include a first circuit configured to be connected in series with a coil, a second circuit, and a switch, where switching a state of the switch may selectively couple the second circuit to the first circuit. The switch may be driven by a pulse width modulation (PWM) signal. The device may further include a PWM controller to receive measurements indicative of wireless power transferred through the coil, generate the PWM signal, and adjust the PWM signal to provide the wireless power transferred through the coil according to a selected metric.

IPC Classes  ?

• H02J 50/10 - Circuit arrangements or systems for wireless supply or distribution of electric power using inductive coupling
• H02J 7/00 - Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries

Abstract

Systems and methods are related to a distributed amplification. An amplification device can include cells including a first cell and a second cell and transmission lines including a first line and a second line. The first cell is coupled to the first line, and the second cell is coupled to the second line. The first line is configured to provide a first delay related to a delay between the first cell and the second cell. The device also includes a summer including a first input coupled to the first line and second input coupled to the second line. The summer is configured to provide an output signal.

IPC Classes  ?

• H03F 3/60 - Amplifiers in which coupling networks have distributed constants, e.g. with waveguide resonators
• H03F 3/21 - Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
• H03F 1/18 - Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of distributed coupling

Abstract

A system including a source follower circuit is disclosed. The source follower circuit configured as a voltage buffer that includes a first common-drain transistor that passes an input signal at the gate to an output loading capacitor at the source, and a second common-drain transistor that is used as a bias current source. The source follower circuit includes a first resistor at the drain of the first transistor generating a first voltage that is fed back through a first path through the gate of the second transistor so as to produce additional current to help the output signal catch up with the input voltage. The source follower circuit further includes an inductive element and bias circuit, which along with the first resistor, increases bandwidth and reduced settling time.

IPC Classes  ?

• H03K 17/60 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being bipolar transistors

Abstract

A semiconductor product being convertible or converted from a customizable configuration into a selectable or selected one of a plurality of different customized configurations, wherein the semiconductor product comprises a customizing unit configured for customizing the semiconductor product into one of the customized configurations selected by a received customizing data structure specifying a selected application of the semiconductor product, and a plurality of functional blocks each configured for providing an assigned functionality and all being deactivated when the semiconductor product is not in one of the customized configurations, wherein the customizing unit is configured for activating only a subgroup of the functional blocks based on the received customizing data structure.

IPC Classes  ?

• H03K 19/0185 - Coupling arrangements; Interface arrangements using field-effect transistors only

Abstract

A switch may operate in a cut-through mode and a store-and-forward mode. While in a default cut-through mode, the switch continuously monitors ports for certain health metrics. If those health metrics fall below a threshold, the switch changes to operate in a store-and-forward mode, either for a predetermined period of time or until the health metrics rise above a threshold, at which point the switch can resume cut-through mode operations. If health metrics fall below an even lower threshold, or remain below threshold for a predefined period of time, the switch can automatically alert a remote system or software process.

IPC Classes  ?

• H04L 43/10 - Active monitoring, e.g. heartbeat, ping or trace-route
• H04L 43/022 - Capturing of monitoring data by sampling
• H04L 43/04 - Processing captured monitoring data, e.g. for logfile generation
• H04L 49/25 - Routing or path finding in a switch fabric

Abstract

An Ethernet bridge architecture enables timing replication. The Ethernet bridge receives data packets from a sensor (such as a video sensor) and immediately tags each data packet with a transmitter timecode. The tagged data packets are then forwarded to the appropriate receiver over the digital data network or link that may exhibit packet delivery time variations and reordering. The receiver identifies data packets including the local timecode and delays processing (display) of the data packet until a timecode local to the receiving node matches the transmitter timecode plus some delay. The receiver also restores the original order of the packets by observing packet sequence number and placing them at appropriate location in memory buffer. By delaying processing, the Ethernet bridge compensates for any variance in network latency. The delay should be greater than a worst-case delay as defined by the network architecture. The Ethernet bridge allows a distributed multi-camera and multi-display system based on high-bandwidth Ethernet infrastructure, while still using non-Ethernet sensors, displays, and application processors.

IPC Classes  ?

• H04L 7/00 - Arrangements for synchronising receiver with transmitter

Abstract

Systems and methods are related to a successive approximation analog to digital converter (SAR ADC). In one aspect, a method includes sampling, by a sample and digital to analog conversion (DAC) circuit, an input voltage to obtain a sampled voltage. The method also includes determining, by a comparator coupled to a set of storage circuits, a state of a plurality of bits corresponding to the sampled voltage. The comparator has a current parameter or voltage parameter adjusted based upon a conversion margin. Adjustment of the current parameter or the voltage parameter affects speed of determining the state of the bits. The method also includes storing the bits in the set of storage circuits. In some aspects, an SAR ADC is configured to perform the method.

IPC Classes  ?

• H03M 1/46 - Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
• H03M 1/06 - Continuously compensating for, or preventing, undesired influence of physical parameters

Abstract

Systems and methods are related to a successive approximation analog to digital converter (SAR ADC). The SAR ADC includes a sample and digital to analog conversion (DAC) circuit configured to sample an input voltage, a comparator circuit coupled to the sample and DAC circuit and having an output, a first set of storage circuits, and a comparator driver. The comparator driver is disposed between the output and the first set of storage circuits (e.g., ratioed latched. The first set of storage circuits are coupled to the comparator circuit and the sample and DAC circuit. The comparator driver can include a first driver and second driver. The first driver is coupled to a first input of a first storage circuit of the first set of storage circuits, and the second driver is coupled to first inputs of a second set of storage circuits within the first set of storage circuits.

IPC Classes  ?

• H03M 1/06 - Continuously compensating for, or preventing, undesired influence of physical parameters

Abstract

A semiconductor product, which comprises a semiconductor chip, an edge integrity detection structure extending along at least part of an edge of the semiconductor chip, and evaluation circuitry formed in and/or on the semiconductor chip, being electrically connected with the edge integrity detection structure, and being configured to evaluate an electric characteristic of the edge integrity detection structure to provide an evaluation signal indicative of a detected edge integrity status of the edge.

IPC Classes  ?

• G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
• H01L 23/58 - Structural electrical arrangements for semiconductor devices not otherwise provided for

Abstract

A PCIe retimer includes read-only vendor registers with low latency mode entry and exit values. In-band low latency switching logic monitors the output of an elastic buffer for read commands of the vendor registers and, when such read commands are received, reads the corresponding address and switches a multiplexer between a link training data path and a low latency data path based on the return value of the read operation. Read commands, and therefore control of data path switching, is handled entirely in-band. Return values of the read operations indicate success or failure of mode switching to the root complex.

IPC Classes  ?

• G06F 13/42 - Bus transfer protocol, e.g. handshake; Synchronisation
• G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode

Abstract

Disclosed herein are related to systems and methods for a successive approximation analog to digital converter (SAR ADC). In one aspect, the SAR ADC includes a calibration circuit configured to receive some or all of the plurality of bits corresponding to the input voltage and accumulates or averages at least some of the bits corresponding to the input voltage. The calibration circuit is configured to provide a first offset signal to control a first offset associated with a first comparator, a second offset signal to control a second offset associated with a second comparator, or reduce an offset difference associated with the first offset and the second offset.

IPC Classes  ?

• H03M 1/10 - Calibration or testing
• H03M 1/12 - Analogue/digital converters
• H03M 1/46 - Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter

Abstract

In some aspects, the disclosure is directed to methods and systems for reducing memory utilization and increasing efficiency during affine merge mode for versatile video coding by utilizing motion vectors stored in a motion data line buffer for a prediction unit of a second coding tree unit neighboring a first coding tree unit to derive control point motion vectors for the first coding tree unit.

IPC Classes  ?

• H04N 11/02 - Colour television systems with bandwidth reduction
• H04N 19/426 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals - characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements using memory downsizing methods
• H04N 19/176 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
• H04N 19/513 - Processing of motion vectors
• H04N 19/105 - Selection of the reference unit for prediction within a chosen coding or prediction mode, e.g. adaptive choice of position and number of pixels used for prediction
• H04N 19/139 - Analysis of motion vectors, e.g. their magnitude, direction, variance or reliability

Abstract

A system for rectifying power is disclosed. The system includes a switch network that includes a plurality of switches configured to receive wireless power input and generate a rectified voltage. The system further includes a first conductor coupled to the first receiver and the switch network configured to transmit a first alternating current to the switch network. The system further includes a second conductor electrically coupled to the first receiver and the switch network, configured to transmit a second alternating current having a second voltage to the first receiver. The system further includes a controller configured to determine a rectified voltage signal and to transmit an input to at least one switch of the plurality of switches based on the rectified voltage signal to change an ON/OFF state of the at least one switch of the plurality of switches, modifying the voltage.

IPC Classes  ?

• H02M 7/219 - Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only in a bridge configuration
• H04B 5/00 - Near-field transmission systems, e.g. inductive loop type
• H02J 50/12 - Circuit arrangements or systems for wireless supply or distribution of electric power using inductive coupling of the resonant type
• H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion

Abstract

A semiconductor chip for implementing load-aware equal-cost multipath routing includes a number of ports and several pipes, each pipe being coupled to a portion of ports on the semiconductor chip, and a central unit consisting of a state machine and multiple databases. The databases contain information regarding a communication network including an overlay network and an underlay network, and the state machine is implemented in hardware and can determine at least one feature of the overlay network and a corresponding group of paths within the underlay network.

IPC Classes  ?

• H04L 45/24 - Multipath
• H04L 45/00 - Routing or path finding of packets in data switching networks
• H04L 45/02 - Topology update or discovery
• H04L 45/42 - Centralised routing
• H04L 47/125 - Avoiding congestion; Recovering from congestion by balancing the load, e.g. traffic engineering

Abstract

Systems and methods provide a fractional signal from a delta sigma modulator to a summer, a combination of an integer value and the fractional signal to a divider, and a divided clock signal from the divider in response to the combination and the input clock signal. The systems and methods also delay the divided clock signal in response to a truncation phase error and gain calibration factor from a calibration unit to provide an output clock signal having equal periods.

IPC Classes  ?

• H03M 3/00 - Conversion of analogue values to or from differential modulation
• H03L 7/099 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop

Abstract

Described herein are a device and a method for performing a network analysis. In one aspect, the device includes a feature extraction circuit, an input processing circuit, and a reconfigurable neural network circuit. In one aspect, the feature extraction circuit receives a raw packet stream, and obtains temporal statistics of a flow, according to a first packet attribute or a first flow attribute of the raw packet stream. In one aspect, the feature extraction circuit generates a feature data including one or more statistical features based on the temporal statistics of the flow. In one aspect, the input processing circuit scales the feature data to generate an adjusted feature data. In one aspect, the reconfigurable neural network circuit performs computations corresponding to a neural network on the adjusted feature data to determine a predicted network characteristic.

IPC Classes  ?

• H04L 43/026 - Capturing of monitoring data using flow identification
• H04L 41/147 - Network analysis or design for predicting network behaviour

Abstract

Novel tools and techniques are provided for implementing synchronization signal (“Sync Mark”) detection using multi-frequency sinusoidal (“MFS”) signal-based filtering. In various embodiments, a computing system may detect a location of a Sync Mark within a data signal, by using MFS signal-based filtering and a sliding window comprising successive search windows each having a bit length corresponding to a bit length of the Sync Mark to identify a portion of the data signal having a magnitude indicative of the Sync Mark. The computing system may refine the location of the Sync Mark within the data signal, by performing a phase measurement on the identified portion of the data signal having the magnitude indicative of the Sync Mark to identify a sub-portion of the identified portion of the data signal, the identified sub-portion having a phase indicative of the Sync Mark, the phase measurement being performed based on the MFS signal-based filtering.

IPC Classes  ?

• H04L 7/04 - Speed or phase control by synchronisation signals
• H04L 7/06 - Speed or phase control by synchronisation signals the synchronisation signals differing from the information signals in amplitude, polarity, or frequency

Abstract

A coupled optic system is disclosed. The coupled optic system includes an optic system. The optic system includes a frame, one or more interface lenses, a lid, and one or more frame alignment surfaces. The coupled optic system further includes an optical connector. The optical connector includes one or more connector lenses, an optical connector holder, and one or more holder alignment surfaces. The optic system is configured to be removably couplable to the optical connector, and the one or more frame alignment surfaces are configured to be removably couplable to the one or more holder alignment surfaces.

IPC Classes  ?

• G02B 6/42 - Coupling light guides with opto-electronic elements
• G02B 6/38 - Mechanical coupling means having fibre to fibre mating means

Abstract

In some aspects, the disclosure is directed to methods and systems for interference mitigation and cancellation in full duplex amplifiers for cable modem or broadband communication systems. In many implementations, an interference canceller in the downstream path may be provided to equalize composite power on the FDX upstream subbands within a predetermined range of amplitude (e.g. X dB) from the desired downstream signal on the same subband, without affecting the downstream subbands.

IPC Classes  ?

• H04L 12/28 - Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
• H04L 5/14 - Two-way operation using the same type of signal, i.e. duplex
• H04L 1/08 - Arrangements for detecting or preventing errors in the information received by repeating transmission, e.g. Verdan system