Embodiments address optimization of an electrical interface between an optical host device and an optical module device at installation time. Certain methods try each entry in a set of Finite Impulse Response (FIR) filter settings at the host transmitter, while asking the module to measure the signal integrity for each. The module will then provide an indication of which entry was the best choice for signal integrity in the current hardware configuration. Note that for the module to host electrical interface, this same technique can be used in reverse, whereby the host asks the module to configure its transmitting FIR filter, and the host records and keeps track of which filter setting is the best, and then configures the module with that filter setting. In both cases, for modules supporting CMIS (Common Management Interface Specification) for module configuration and control, methods are provided.
H04L 25/03 - Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
H04B 10/079 - Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems using an in-service signal using measurements of the data signal
An automated weapon system is comprised a human transported weapon for use by a person, comprising a barrel movable within a stock, utilized for propelling a fired munition towards an area of sighting for the human transported weapon. A targeting subsystem identifies a chosen target in the area of sighting. A computational subsystem, responsive to the targeting subsystem, determines where the chosen target is, and determines where to aim the barrel so that the munitions will strike the chosen target. The barrel is movable within a stock, utilized for propelling a fired munition towards an area of sighting for the human transported weapon. A positioning means adjusts the aim of the barrel responsive to the computational subsystem. A firing subsystem, fires the munition at the chosen target responsive to the positioning means.
In one embodiment, detection logic detects a no-shoot situation prior to the firing of the munition; and, inhibit logic prevents the firing logic from firing the munitions responsive to the detection logic detecting a no shoot situation.
An integrated heatsink for a co-packaged optical-electrical module includes a base plate attached on top of a co-packaged optical-electrical module. The integrated heatsink further includes a plurality of fin structures extended upward from the base plate except a central cavity region with missing sections of fins, each fin extended along an axial direction from a front edge to a back edge of the base plate except some trenches shallow in depth across some fin structures and some other trenches deep in depth down to the base plate either along or across some fin structures. Additionally, the integrated heatsink includes multiple heat pipes including shaped portions embedded in the trenches in the plurality of fin structures. At least one bottom horizontal portion per heat pipe is brazed to the base plate in a corresponding region that is superimposed on hot spots of the co-packaged optical-electrical module under the base plate.
H05K 7/20 - Modifications to facilitate cooling, ventilating, or heating
G02B 6/42 - Coupling light guides with opto-electronic elements
H01L 23/427 - Cooling by change of state, e.g. use of heat pipes
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different main groups of groups , or in a single subclass of , , e.g. forming hybrid circuits
H04Q 11/00 - Selecting arrangements for multiplex systems
G02B 6/43 - Arrangements comprising a plurality of opto-electronic elements and associated optical interconnections
4.
Silicon optical modulator, method for making the same
A silicon optical modulator includes two silicon waveguide branches coupled between a 2×2 splitter at a common input end and a 2×2 splitter at a common output end. The modulator further includes at least one of the two silicon waveguide branches comprising a ridge-shape having a central portion of a height sandwiched in a width direction by a first side portion and a second side portion throughout a length of the waveguide. The central portion in each cross-section plane thereof includes a p-region and a n-region separated by a continuous borderline to form an irregular shaped PN junction. The borderline is configured to have at least one section-line with a sloped angle relative to the width direction and have a total border-length substantially longer than the height. The p-region is in contact with the first side portion and the n-region is in contact with the second side portion.
G02F 1/225 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour by interference in an optical waveguide structure
G02F 1/21 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour by interference
G02B 6/134 - Integrated optical circuits characterised by the manufacturing method by substitution by dopant atoms
5.
ELIMINATING EXECUTION OF INSTRUCTIONS THAT PRODUCE A CONSTANT RESULT
An instruction is received by a processing pipeline of a computer processor. The instruction is a constant-type of instruction and has an associated constant value. A constant register file is assigned to the instruction. The constant value is written to the constant register file without sending the instruction to execution units (e.g., arithmetic logic units) in the processor pipeline.
A device and method of operation for digital compensation of dynamic distortion. The transmitter device includes at least a digital-to-analog converter (DAC) connected to a lookup table (LUT), a first shift register, and a second shift register. The method includes iteratively adjusting the input values via the LUT to induce changes in the DAC output that compensate for dynamic distortion, which depends on precursors, current cursors, and postcursors. More specifically, the method includes producing and capturing average output values for each possible sequence of three symbols using the shift register and LUT configuration. Then, the LUT is updated with estimated values to induce desired output values that are adjusted to eliminate clipping. These steps are performed iteratively until one or more check conditions are satisfied. This method can also be combined with techniques such as equalization, eye modulation, and amplitude scaling to introduce desirable output signal characteristics.
The present invention is directed to communication methods and systems thereof. In a specific embodiment, a noise cancelation system includes a slicer that processes a data stream generates both PAM symbols and error data. An RIN estimator generates RIN data based on the PAM symbols and the error data. A filter removes non-RIN information from the RIN data. The filtered RIN data includes an offset term and a gain term, which are used to remove RIN noise from the data stream. There are other embodiments as well.
An encryption interface provides secure, low-latency communications between processors. A first processor block transforms initial data into encrypted data using a cipher for receipt by a second processor block, which transforms the encrypted data into decrypted data. The first processor block utilized a crypto circuit having a plurality of stages, each of which generate a subset of a cipher digit stream for encrypting the data. The second processor block receives and decrypts the encrypted data using a respective decryption circuit.
G06F 21/72 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in cryptographic circuits
H04L 29/06 - Communication control; Communication processing characterised by a protocol
H04L 9/06 - Arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for blockwise coding, e.g. D.E.S. systems
A light source based on integrated silicon photonics includes a die of a silicon substrate having at least one chip site configured with a surface region, a trench region, and a first stopper region located separately between the surface region and the trench region. The trench region is configured to be a depth lower than the surface region. The light source includes a laser diode chip having a p-side facing the chip site and a n-side being distal to the chip site. The p-side includes a gain region bonded to the trench region, an electrode region bonded to the surface region, and an isolation region engaged with the stopper region to isolate the gain region from the electrode region. The light source also includes a conductor layer in the die configured to connect the gain region to an anode electrode and separately connect the electrode region to a cathode electrode.
H04B 10/00 - Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
H01S 5/02 - Structural details or components not essential to laser action
H01S 5/323 - Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- hetero-structures in AIIIBV compounds, e.g. AlGaAs-laser
H04B 10/07 - Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems
G01R 31/26 - Testing of individual semiconductor devices
G02B 6/12 - Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
H01S 5/12 - Construction or shape of the optical resonator the resonator having a periodic structure, e.g. in distributed feedback [DFB] lasers
10.
Apparatus and method for thermal dissipation of photonic transceiving module
An apparatus for dissipating heat from a photonic transceiver module. The apparatus includes a top-plate member disposed in a length direction of a package for the photonic transceiver module. The apparatus further includes multiple fins formed on the top-plate member along the length direction from a backend position to a frontend position except at least one fin with a shorter length, forming an elongated void from the backend position to one backend of the at least one fin. Additionally, the apparatus includes a cover member disposed over the multiple fins with a horizontal sheet, two vertical side sheets, and a flange bent vertically from a middle portion of backend of the horizontal sheet. Furthermore, the apparatus includes a spring loaded in the elongated void between the flange and the one backend of the at least one fin to minimize an air gap at the backend of the horizontal sheet.
G02B 6/42 - Coupling light guides with opto-electronic elements
H05K 7/20 - Modifications to facilitate cooling, ventilating, or heating
F28F 1/14 - Tubular elements or assemblies thereof with means for increasing heat-transfer area, e.g. with fins, with projections, with recesses the means being only outside the tubular element and extending longitudinally
11.
Compact optical module integrated for communicating cryptocurrency transaction
A compact optical transceiver formed by hybrid multichip integration. The optical transceiver includes a Si-photonics chip attached on a PCB. Additionally, the optical transceiver includes a first TSV interposer and a second TSV interposer separately attached nearby the Si-photonics chip on the PCB. Furthermore, the optical transceiver includes a driver chip flip-bonded partially on the Si-photonics chip through a first sets of bumps and partially on the first TSV interposer through a second sets of bumps. Moreover, the optical transceiver includes a transimpedance amplifier module chip flip-bonded partially on the Si-photonics chip through a third sets of bumps and partially on the second TSV interposer through a fourth set of bumps.
G02B 6/12 - Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
G06Q 20/06 - Private payment circuits, e.g. involving electronic currency used only among participants of a common payment scheme
An integrated compact light engine configured in a on-board in-package optics assembly. The compact light engine includes a single substrate to integrate multiple optical-electrical modules. Each optical-electrical module includes an integrated optical transceiver based on silicon-photonics platform, in which a transmit path configured to output four light signals centered at four CWDM wavelengths and from four laser devices and to modulate the four light signals respectively by four modulators driven by a driver chip and to deliver a multiplexed transmission light. A receive path includes a photodetector to detect four input signals demultiplexed from an incoming light and a trans-impedance amplifier chip to process electrical signals converted from the four input signals detected. A multi-channel light engine is formed by co-integrating or co-mounting a switch device with multiple compact light engines on a common substrate member to provide up to 51.2 Tbit/s total capacity of data communication with median-or-short-reach electrical interconnect.
A system to support data gathering for a machine learning (ML) operation comprises a memory unit configured to maintain data for the ML operation in a plurality of memory blocks each accessible via a memory address. The system further comprises an inference engine comprising a plurality of processing tiles each comprising one or more of an on-chip memory (OCM) configured to load and maintain data for local access by components in the processing tile. The system also comprises a core configured to program components of the processing tiles of the inference engine according to an instruction set architecture (ISA) and a data streaming engine configured to stream data between the memory unit and the OCMs of the processing tiles of the inference engine wherein data streaming engine is configured to perform a data gathering operation via a single data gathering instruction of the ISA at the same time.
The present invention is directed to electrical circuits. and more specially, inductor designs that reduce on-chip electromagnetic coupling in certain applications. In a specific embodiment, the present invention provides an inductor that includes coils that are configured to generate magnetic fields of opposite polarities. The electromagnetic fields generated by the inductor coils substantially cancel out with each other, thereby minimizing parasitic inductance of the inductor and reducing interference with operations of other components in an integrated circuit. There are other embodiments as well.
H04B 1/38 - Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
H03B 5/12 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
The present invention is directed to communication systems and electrical circuits. More specifically, an embodiment of the present invention provides a termination circuit that includes a programmable gain attenuation section, a T-coil section, and a termination resistor. The characteristic resistance of the programmable gain attenuation section matches the resistance of the termination resistor. There are other embodiments as well.
Methods and apparatus for distributing baseband signal processing of fifth generation (5G) new radio uplink signals. In an embodiment, a method includes receiving uplink transmissions having user data, receiving configuration parameters, and performing a first portion of baseband processing that compresses the uplink transmissions using the configuration parameters to generate compressed packets. The method also includes transmitting the compressed packets over a transmission medium to the central office that performs a second portion of the baseband processing to obtain the user data. In an embodiment, an apparatus includes a radio frequency interface that receives uplink transmissions that have user data, and a first baseband processing section that receives configuration parameters, compresses the uplink transmissions using the configuration parameters to generate compressed packets, and transmits the compressed packets over a transmission medium to the central office where a second baseband processing section processes the compressed packets to obtain the user data.
A silicon optical modulator is fabricated to have a multi-slab structure between the contacts and the waveguide, imparting desirable performance attributes. A first slab comprises dopant of a first level. A second slab adjacent to (e.g., on top of) the first slab, comprises a doped region proximate to a contact, and an intrinsic region proximate to the waveguide. The parallel resistance properties and low overlap between the highly doped silicon and optical mode pigtail afforded by the multi-slab configuration, allow the modulator to operate with reduced optical losses and at a high speed. Embodiments may be implemented in a Mach-Zehnder interferometer or in micro-ring resonator modulator configuration.
G02F 1/025 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on semiconductor elements with at least one potential jump barrier, e.g. PN, PIN junction in an optical waveguide structure
G02F 1/225 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour by interference in an optical waveguide structure
G02F 1/015 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on semiconductor elements with at least one potential jump barrier, e.g. PN, PIN junction
G02F 1/21 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour by interference
18.
Method and structure for controlling bandwidth and peaking over gain in a variable gain amplifier (VGA)
A method of controlling bandwidth and peaking over gain in a variable gain amplifier (VGA) device and structure therefor. The device includes at least three differential transistor pairs configured as a cross-coupled differential amplifier with differential input nodes, differential bias nodes, differential output nodes, a current source node, and two cross-coupling nodes. The cross-coupled differential amplifier includes a load resistor coupled to each of the differential output nodes and one of the cross-coupling nodes, and a load inductor coupled to the each of the cross-coupling nodes and a power supply rail. A current source is electrically coupled to the current source node. The cross-coupling configuration with the load resistance and inductance results in a lower bandwidth and lowered peaking at low gain compared to high gain. Further, the tap point into the inductor can be chosen as another variable to “tune” the bandwidth and peaking in a communication system.
The present invention is directed to data communication. In certain embodiments, the present invention provides switching mechanism for choosing between redundant communication links. Data received from a first set of communication links are processed to have alignment markers removed, and first figure of merit value is determined based on the data without alignment markers. Similarly, a second figure of merit value is determined for the data received from the second set of communication links. A switch selects between the first set of communication links and the second set of communication links based on their respective figure of merit values. Alignment markers are inserted into the data transmitted through the selected set of data links. There are other embodiments as well.
H04L 29/08 - Transmission control procedure, e.g. data link level control procedure
G06F 11/20 - Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
H04L 12/427 - Loop networks with decentralised control
H04L 1/22 - Arrangements for detecting or preventing errors in the information received using redundant apparatus to increase reliability
H04L 12/24 - Arrangements for maintenance or administration
An integrated compact light engine configured in a on-board in-package optics assembly. The compact light engine includes a single substrate to integrate multiple optical-electrical modules. Each optical-electrical module includes an integrated optical transceiver based on silicon-photonics platform, in which a transmit path configured to output four light signals centered at four CWDM wavelengths and from four laser devices and to modulate the four light signals respectively by four modulators driven by a driver chipand to deliver a multiplexed transmission light. A receive path includes a photodetector to detect four input signals demultiplexed from an incoming light and a trans-impedance amplifier chip to process electrical signals converted from the four input signals detected. A multi-channel light engine is formed by co-integrating or co-mounting a switch device with multiple compact light engines on a common substrate member to provide up to 51.2 Tbit/s total capacity of data communication with median-or-short-reach electrical interconnect.
An integrated apparatus with optical/electrical interfaces and protocol converter on a single silicon substrate. The apparatus includes an optical module comprising one or more modulators respectively coupled with one or more laser devices for producing a first optical signal to an optical interface and one or more photodetectors for detecting a second optical signal from the optical interface to generate a current signal. Additionally, the apparatus includes a transmit lane module coupled between the optical module and an electrical interface to receive a first electric signal from the electrical interface and provide a framing protocol for driving the one or more modulators. Furthermore, the apparatus includes a receive lane module coupled between the optical module and the electrical interface to process the current signal to send a second electric signal to the electrical interface.
The present invention is directed to electrical circuits. According to an embodiment, the present invention provides a charge pump circuit with a bias section and a switch section. The switch section includes a first switch coupled to an early signal and a second switch coupled to a late signal. The charge pump additionally includes a low-pass filter. The switch section includes a first resistor and a second resistor. The first resistor is directly coupled to the first switch and the low-pass filter. The second resistor is directly coupled to the second switch and the first resistor. There are other embodiments as well.
H02M 3/07 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
H03L 7/089 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
23.
Clock and data recovery devices with fractional-N PLL
The present invention relates to data communication and electrical circuits. More specifically, embodiments of the present invention provide a clock and data recovery (CDR) architecture implementation for high data rate wireline communication links. In an embodiment, a CDR device includes a phase detector, a loop filter, and a fractional-N PLL. The fractional-N PLL generates output clock signal based on output of the loop filter. There are other embodiments as well.
H04L 7/00 - Arrangements for synchronising receiver with transmitter
H03L 7/197 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
H03L 7/099 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
H03L 7/087 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
H03L 7/08 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop
An coherent transceiver includes a single silicon photonics substrate configured to integrate a laser diode chip flip-mounted and coupled with a wavelength tuning section to provide a laser output with tuned wavelengths which is split in X:Y ratio partly into a coherent receiver block as local-oscillator signals and partly into a coherent transmitter block as a light source. The coherent receiver includes a polarization-beam-splitter-rotator to split a coherent input signal to a TE-mode signal and a TM*-mode signal respectively detected by two 90-deg hybrid receivers and a flip-mounted TIA chip assisted by two local-oscillator signals from the tunable laser device. The coherent transmitter includes a driver chip flip-mounted on the silicon photonics substrate to drive a pair of Mach-Zehnder modulators with 90-degree shift in quadrature-phase branches to modulate the laser output to two polarized signals with I/Q modulation and uses a polarization-beam-rotator-combiner to combine them as a coherent output signal.
G02B 6/12 - Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
G02B 6/42 - Coupling light guides with opto-electronic elements
G02B 6/126 - Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind using polarisation effects
G02B 6/122 - Basic optical elements, e.g. light-guiding paths
An coherent transceiver includes a single silicon photonics substrate configured to integrate a laser diode chip flip-mounted and coupled with a wavelength tuning section to provide a laser output with tuned wavelengths which is split in X:Y ratio partly into a coherent receiver block as local-oscillator signals and partly into a coherent transmitter block as a light source. The coherent receiver includes a polarization-beam-splitter-rotator to split a coherent input signal to a TE-mode signal and a TM*-mode signal respectively detected by two 90-deg hybrid receivers and a flip-mounted TIA chip assisted by two local-oscillator signals from the tunable laser device. The coherent transmitter includes a driver chip flip-mounted on the silicon photonics substrate to drive a pair of Mach-Zehnder modulators with 90-degree shift in quadrature-phase branches to modulate the laser output to two polarized signals with I/Q modulation and uses a polarization-beam-rotator-combiner to combine them as a coherent output signal.
H01S 3/13 - Stabilisation of laser output parameters, e.g. frequency or amplitude
G02B 6/12 - Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
G02B 6/42 - Coupling light guides with opto-electronic elements
G02B 6/126 - Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind using polarisation effects
The present invention is directed to communication methods and systems thereof. In a specific embodiment, a noise cancelation system includes a slicer that processes a data stream generates both PAM symbols and error data. An RIN estimator generates RIN data based on the PAM symbols and the error data. A filter removes non-RIN information from the RIN data. The filtered RIN data includes an offset term and a gain term, which are used to remove RIN noise from the data stream. There are other embodiments as well.
A method and structure for compensation techniques in coherent optical receivers. The present invention provides a coherent optical receiver with an improved 8×8 adaptive MIMO (Multiple Input, Multiple Output) equalizer configured within a digital signal processor (DSP) to compensate the effects of transmitter I/Q skew in subcarrier multiplexing (SCM) schemes. The 8×8 MIMO equalizer can be configured such that each of the 8 outputs is electrically coupled to 3 of 8 inputs, wherein each of the input-output couplings is configured as a filter. The method includes compensating for impairments to the digital conversion of an optical input signal via the 8×8 MIMO equalizer following other signal processing steps, such as chromatic dispersion (CD)/polarization-mode dispersion (PMD) compensation, carrier recovery, timing synchronization, and cycle slip correction.
A bias circuit comprises a closed loop gain stage arranged to determine a difference between a first current in a first branch circuit and a second current in a second branch circuit, where the first branch circuit and second branch circuit are coupled to respective terminals of a magnetic resistor (MR). A first set of current mirrors is arranged to provide a source current to the first terminal of the MR and the second set of current mirrors is arranged to provide a sink current to the second terminal of the MR. The first set of current mirrors and a second set of current mirrors are balanced to reduce a difference in setting time between the source current and sink current. The source current and sink current further reduce the difference between the first current and the second current to provide a constant voltage bias to the MR based on a voltage of a voltage source.
G11B 5/54 - Disposition or mounting of heads relative to record carriers with provision for moving the head into, or out of, its operative position or across tracks
G11B 5/39 - Structure or manufacture of flux-sensitive heads using magneto-resistive devices
An coherent transceiver includes a single silicon photonics substrate configured to integrate a laser diode chip flip-mounted and coupled with a wavelength tuning section to provide a laser output with tuned wavelengths which is split in X:Y ratio partly into a coherent receiver block as local-oscillator signals and partly into a coherent transmitter block as a light source. The coherent receiver includes a polarization-beam-splitter-rotator to split a coherent input signal to a TE-mode signal and a TM*-mode signal respectively detected by two 90-deg hybrid receivers and a flip-mounted TIA chip assisted by two local-oscillator signals from the tunable laser device. The coherent transmitter includes a driver chip flip-mounted on the silicon photonics substrate to drive a pair of Mach-Zehnder modulators with 90-degree shift in quadrature-phase branches to modulate the laser output to two polarized signals with I/Q modulation and uses a polarization-beam-rotator-combiner to combine them as a coherent output signal.
G02B 6/12 - Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
G02B 6/126 - Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind using polarisation effects
G02B 6/122 - Basic optical elements, e.g. light-guiding paths
G02B 6/42 - Coupling light guides with opto-electronic elements
The present application discloses a Transverse Electric (TE) polarizer. The TE polarizer includes a semiconductor substrate having an oxide layer. The TE polarizer further includes a waveguide embedded in the oxide layer. Additionally, the TE polarizer includes a plate structure embedded in the oxide layer substantially in parallel to the waveguide with a gap distance. In an embodiment, the plate structure induces an extra transmission loss to a Transverse Magnetic (TM) mode in a light wave traveling through the waveguide.
G02B 6/27 - Optical coupling means with polarisation selective and adjusting means
G02B 6/126 - Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind using polarisation effects
G02B 6/12 - Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
31.
Histogram based optimization for optical modulation
The present invention is directed to communication systems and methods. In a specific embodiment, the present invention provides an optical receiver that receives a data stream from an optical transmitter. The optical receiver determines a histogram contour parameter using the data stream and inserts the histogram contour parameter into a back-channel data segment, which is then transmitted to the optical transmitter. The optical transmitter changes its data transmission setting based on the histogram contour parameter. There are other embodiments as well.
H04B 10/079 - Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems using an in-service signal using measurements of the data signal
H04B 10/516 - Transmitters - Details of coding or modulation
Disclosed is a multi-chip module (MCM) with redundant chip-to-chip communication connection(s) to minimize the need to discard a chip-mounting layer due to defective signal traces. The MCM includes at least first and second chips mounted on the chip-mounting layer. The chip-mounting layer includes signal traces that are electrically connected between first and second links on the first and second chips, respectively, to form communication connections including at least one redundant communication connection. Instead of being directly connected to the chip-to-chip communication connections, first and second interfaces on the first and second chips are connected via first and second multiplexors, respectively, to selected ones of multiple chip-to-chip communication connections. By employing the multiplexors and the redundant chip-to-chip communication connection(s), chip-to-chip communication connection(s) with defective signal trace(s) can be bypassed. Specifically, during MCM assembly, the multiplexors are programmed to avoid using chip-to-chip communication connections with defective signal traces.
H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 21/66 - Testing or measuring during manufacture or treatment
33.
ADC-based SerDes with sub-sampled ADC for eye monitoring
Digital serializer/deserializer circuitry includes a data path and a date eye monitoring path. The data path includes a first analog-to-digital converter (ADC) to sample incoming data at a first rate, first digital filter circuitry to filter output of the first ADC, and a data slicer coupled to output of the first digital filter circuitry to output data above a threshold. The monitoring path includes a second ADC to sample the incoming data at a second rate lower than the first rate and to take samples at varying points along the incoming data waveform, second digital filter circuitry to filter output of the second ADC, and another data slicer coupled to output of the second digital filter circuitry to output data above an adjustable threshold and to sweep through varying threshold values. Error rate circuitry compares outputs of the data slicers to determine a data eye error rate.
An optical dispersion compensator integrated with a silicon photonics system including a first phase-shifter coupled to a second phase-shifter in parallel on the silicon substrate characterized in an athermal condition. The dispersion compensator further includes a third phase-shifter on the silicon substrate to the first phase-shifter and the second phase-shifter through two 2×2 splitters to form an optical loop. A second entry port of a first 2×2 splitter is for coupling with an input fiber and a second exit port of a second 2×2 splitter is for coupling with an output fiber. The optical loop is characterized by a total phase delay tunable via each of the first phase-shifter, the second phase-shifter, and the third phase-shifter such that a normal dispersion (>0) at a certain wavelength in the input fiber is substantially compensated and independent of temperature.
G02B 6/293 - Optical coupling means having data bus means, i.e. plural waveguides interconnected and providing an inherently bidirectional system by mixing and splitting signals with wavelength selective means
G02B 6/122 - Basic optical elements, e.g. light-guiding paths
G02B 6/30 - Optical coupling means for use between fibre and thin-film device
H04B 10/2513 - Arrangements specific to fibre transmission for the reduction or elimination of distortion or dispersion due to chromatic dispersion
G02B 6/12 - Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
35.
Methods and systems for load balancing in network devices
Methods and systems for network devices are provided. One method includes receiving a frame by a network device communicating with a computing device via a peripheral link, the network device receiving the frame via a network connection; using one or more frame header fields to generate a frame context by the network device; determining if a processor of the network device is processing another frame with the same frame context; assigning the frame context to a first processor of the network device, when the first processor is processing the other frame with the same frame context; and when neither processor is processing the same frame context, selecting between the first processor and a second processor of the network device, based on a workload of the first processor and the second processor, the workload determined by a number of contexts that are pending for the first processor and the second processor.
A first communication device receives respective beamforming training data units simultaneously transmitted to the first communication device by multiple second communication devices. The first communication device generates, based on the respective beamforming training data units received from the multiple second communication devices, respective beamforming feedback data units to be transmitted to respective ones of the multiple second communication devices. The first communication device transmits the respective feedback data units to the respective ones of the multiple second communication devices.
H04B 7/06 - Diversity systems; Multi-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station
H04L 5/00 - Arrangements affording multiple use of the transmission path
An instruction execution circuit operable to reduce two or more micro-operations into one by producing multiple permutation and merge results in one execution cycle. The execution circuit includes a permutation and merge switching fabric and a bank of multiplexers. For a fetched instruction, a decoder decodes an opcode to generate a set of control indications used to control the multiplexers to select bytes from the respective inputs that are destined for each of the multiple results. In this manner, multiple permutation results can be output from the execution circuits in one micro-operation.
The present invention includes an integrated system-on-chip device configured on a substrate member. The device has a data input/output interface provided on the substrate member and configured for a predefined data rate and protocol. The device has an input/output block provided on the substrate member and coupled to the data input/output interface. The input/output block comprises a SerDes block, a CDR block, a compensation block, and an equalizer block. The SerDes block is configured to convert a first data stream of N having a first predefined data rate at a first clock rate into a second data stream of M having a second predefined data rate at a second clock rate. The device has a driver module provided on the substrate member and coupled to a signal processing block, and a driver interface provided on the substrate member and coupled to the driver module and a silicon photonics device.
G06F 13/24 - Handling requests for interconnection or transfer for access to input/output bus using interrupt
H04B 10/80 - Optical aspects relating to the use of optical transmission for specific applications, not provided for in groups , e.g. optical power feeding or optical transmission through water
H04B 10/516 - Transmitters - Details of coding or modulation
H04B 10/69 - Electrical arrangements in the receiver
H04B 14/02 - Transmission systems not characterised by the medium used for transmission characterised by the use of pulse modulation
G06F 15/78 - Architectures of general purpose stored program computers comprising a single central processing unit
G06F 13/42 - Bus transfer protocol, e.g. handshake; Synchronisation
G02B 6/12 - Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
G06F 13/364 - Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
An optical module processes first FEC (Forward Error Correction) encoded data produced by a first FEC encoder. The optical module has a second FEC encoder for further coding a subset of the first FEC encoded data to produce second FEC encoded data. The optical module also has an optical modulator for modulating, based on a combination of the second FEC encoded data and a remaining portion of the first FEC encoded data that is not further coded, an optical signal for transmission over an optical channel. The second FEC encoder is an encoder for an FEC code that has a bit-level trellis representation with a number of states in any section of the bit-level trellis representation being less than or equal to 64 states. In this manner, the second FEC encoder has relatively low complexity (e.g. relatively low transistor count) that can reduce power consumption for the optical module.
H03M 13/29 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
A method and structure for probabilistic shaping and compensation techniques in coherent optical receivers. According to an example, the present invention provides a method and structure for an implementation of distribution matcher encoders and decoders for probabilistic shaping applications. The techniques involved avoid the traditional implementations based on arithmetic coding, which requires intensive multiplication functions. Furthermore, these probabilistic shaping techniques can be used in combination with LDPC codes through reverse concatenation techniques.
H04B 10/00 - Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
Apparatus and method for digital signal constellation transformation are provided herein. In certain configurations, an integrated circuit includes an analog front-end that converts an analog signal vector representing an optical signal into a digital signal vector, and a digital signal processing circuit that processes the digital signal vector to recover data from the optical signal. The digital signal processing circuit generates signal data representing a signal constellation of the digital signal vector. The digital signal processing circuit includes an adaptive gain equalizer that compensates the signal data for distortion of the signal constellation arising from biasing errors of optical modulators used to transmit the optical signal.
H04B 10/00 - Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
Disclosed is a multi-port memory array configured to minimize resistance-capacitance (RC) delay caused by wordline coupling. In each row of the array, a first voltage boost circuit is connected to the distal ends of a first wordline and a second wordline and boosts a first voltage on the first wordline during an access period when the first voltage is transitioning from low to high and when, concurrently, a second voltage on the second wordline is either low or transitioning to low. Optionally, a second voltage boost circuit is also connected to the distal ends of the first and second wordlines and boosts the second voltage on the second wordline during a different access period when the second voltage is transitioning from low to high and when, concurrently, the first voltage on the first wordline is either at low or transitioning from high to low. Also disclosed is a corresponding method.
G11C 8/16 - Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
G11C 11/417 - Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
A receiver applies a calibration method to compensate for skew between input channels. The receiver skew is estimated by observing the coefficients of an adaptive equalizer which adjusts the coefficients based on time-varying properties of the multi-channel input signal. The receiver skew is compensated by programming the phase of the sampling clocks for the different channels. Furthermore, during real-time operation of the receiver, channel diagnostics is performed to automatically estimate differential group delay and/or other channel characteristics based on the equalizer coefficients using a frequency averaging or polarization averaging approach. Framer information can furthermore be utilized to estimate differential group delay that is an integer multiple of the symbol rate. Additionally, a DSP reset may be performed when substantial signal degradation is detected based on the channel diagnostics information.
H04B 10/079 - Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems using an in-service signal using measurements of the data signal
A silicon-based edge coupler for coupling a fiber with a waveguide includes a cantilever member being partially suspended with its anchored end coupled to a silicon photonics die in a first part of a silicon substrate and a free end terminated near an edge region separating a second part of the silicon substrate from the first part. The edge coupler further includes a mechanical stopper formed at the edge region with a gap distance ahead of the free end of the cantilever member. Additionally, a V-groove is formed in the second part of the silicon substrate characterized by a top opening and a bottom plane symmetrically connected by two sloped side walls along a fixed Si-crystallography angle. The V-groove is configured to support a fiber with an end facet being pushed against the mechanical stopper and a core center being aligned with the free end of the cantilever member.
G02B 6/43 - Arrangements comprising a plurality of opto-electronic elements and associated optical interconnections
G02B 6/42 - Coupling light guides with opto-electronic elements
G02B 6/122 - Basic optical elements, e.g. light-guiding paths
G02B 6/12 - Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
45.
Impairment compensation techniques for high performance coherent optical transceivers
A method and structure for compensation techniques in coherent optical receivers. The present invention provides a coherent optical receiver with an improved 8×8 adaptive MIMO (Multiple Input, Multiple Output) equalizer configured within a digital signal processor (DSP) to compensate the effects of transmitter I/Q skew in subcarrier multiplexing (SCM) schemes. The 8×8 MIMO equalizer can be configured such that each of the 8 outputs is electrically coupled to 3 of 8 inputs, wherein each of the input-output couplings is configured as a filter. The method includes compensating for impairments to the digital conversion of an optical input signal via the 8×8 MIMO equalizer following other signal processing steps, such as chromatic dispersion (CD)/polarization-mode dispersion (PMD) compensation, carrier recovery, timing synchronization, and cycle slip correction.
The present invention is directed to data communication. More specifically, an embodiment of the present invention provides an error correction system. Input data signals are processed by a feedforward equalization module and a decision feedback back equalization module. Decisions generated by the decision feedback equalization module are processed by an error detection module, which determines error events associated with the decisions. The error detection module implements a reduced state trellis path. There are other embodiments as well.
A semiconductor device comprises a first conductive material, a contact, an a magnetic tunneling junction positioned between the first conductive material and the contact. The semiconductor device further comprises a spacer that is positioned between the first conductive material and the contact and surrounds at least a portion of the magnetic tunneling junction. The spacer comprises spacer material that has at least some etch selectivity compared to a dielectric material that surrounds at least a portion of the first conductive material.
H01L 43/12 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
H01L 43/02 - Devices using galvano-magnetic or similar magnetic effects; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof - Details
H01L 27/22 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate using similar magnetic field effects
An integrated apparatus with optical/electrical interfaces and protocol converter on a single silicon substrate. The apparatus includes an optical module comprising one or more modulators respectively coupled with one or more laser devices for producing a first optical signal to an optical interface and one or more photodetectors for detecting a second optical signal from the optical interface to generate a current signal. Additionally, the apparatus includes a transmit lane module coupled between the optical module and an electrical interface to receive a first electric signal from the electrical interface and provide a framing protocol for driving the one or more modulators. Furthermore, the apparatus includes a receive lane module coupled between the optical module and the electrical interface to process the current signal to send a second electric signal to the electrical interface.
A method for deallocating memory in a first network device is described. A multicast packet is received and stored in memory cells. Egress descriptors corresponding to the multicast packet are generated for transmission of the multicast packet. A final count of the egress descriptors is determined. The egress descriptors are processed for transmission of the multicast packet and a value of a signed reference counter corresponding to the multicast packet is updated in a first direction before the final count has been determined and after a copy of the multicast packet has been received by an egress port of the first network device. The value of the signed reference counter is updated in a second direction opposite the first direction by the final count after determination of the final count. The memory cells are deallocated when cumulative first direction updates are equal to the second direction update.
The present invention is directed to electrical circuits and techniques thereof. In various embodiments, the present invention provides a variable gain amplifier architecture that includes a continuous-time linear equalizer (CTLE) section and a variable gain amplifier (VGA) section. The CTLE section provides both a pair of equalized data signals and a common mode voltage. A DAC generates a control signal based on a control code. The VGA section amplifies the pair of equalized data signals by an amplification factor using a transistor whose resistance value is based on both the common mode voltage and the control signal. There are other embodiments as well.
A package structure of a directly modulated laser in a photonics module includes a thermoelectric cooler including multiple conductor traces formed in a cool surface. The package structure further includes a directly modulated laser (DML) chip having a first electrode being attached with the cool surface and a second electrode at a distance away from the cool surface. Additionally, the package structure includes an interposer having a plurality of through-holes formed between a first surface to a second surface. The first surface is mounted to the cool surface such that each through-hole is aligned with one of the multiple conductor traces and the second surface being leveled with the second electrode. Moreover, the package structure includes a driver disposed on the second surface of the interposer with at least a galvanically coupled output port coupled directly to the second electrode of the DML chip.
During operation of an analog filter having one or more filter stages is configured to operate in a first configuration. Configuring the analog filter to operate in the first filter configuration includes configuring one or both of i) a filter response of the analog filter and ii) a filter bandwidth of the analog filter. A first set of one or more direct current (DC) offset correction codes corresponding to the first filter configuration are retrieved from a memory. The one or more DC offset correction codes in the first set are converted to one or more first analog DC offset correction signals. While operating the analog filter configured in the first configuration, the one or more first analog DC offset correction signals are applied to the one or more filter stages of the analog filter.
A preamplifier comprises an input stage and a capacitive coupling stage. The input stage is arranged to receive a differential signal from a magnetic resistor which indicates a magnetic field sensed on a magnetic disk of a hard disk drive (HDD) when the preamplifier is powered on from an off state. The capacitive coupling stage has an input arranged to receive the differential signal from the input stage, a filter comprising a first resistor, a second resistor, a first capacitor, a second capacitor, and switches arranged in parallel with respective resistors, where the switches are closed when the preamplifier is powered on from the off state to an on state. A switch control is arranged to determine that an offset of the differential signal has settled and open the switches based on the determination.
A circuit and method for mitigating multi-path interference in direct detection optical systems is provided. Samples of an optical signal having a pulse amplitude modulated (PAM) E-field are processed by generating a PAM level for each sample. For each sample, the sample is subtracted from the respective PAM level to generate a corresponding error sample. The error samples are lowpass filtered to produce estimates of multi-path interference (MPI). For each sample, one of the estimates of MPI is combined with the sample to produce an interference-mitigated sample.
H04B 10/516 - Transmitters - Details of coding or modulation
H04B 10/00 - Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
55.
Package structure for photonic transceiving device
A photonic transceiver apparatus in QSFP package. The apparatus includes a case having a base member, two partial side members, and a lid member to provide a spatial volume with an opening at a back end of the base member. Additionally, the apparatus includes a PCB, installed inside the spatial volume over the base member having a pluggable electrical connector at the back end. Further, the apparatus includes multiple optical transmitting devices in mini-transmit-optical-sub-assembly package, each being mounted on a common support structure and having a laser output port in reversed orientation toward the back end. Furthermore, the apparatus includes a silicon photonics chip, including a fiber-to-silicon attachment module, mounted on the PCB and coupled to a modulation driver module and a trans-impedance amplifier module. Moreover, the apparatus includes a pair of optical input/output ports being back connected to the fiber-to-silicon attachment module.
In aspects of acknowledgement options for downlink multi-user transmission, a wireless network system includes an access point that can communicate a downlink multi-user transmission soliciting acknowledgement from one or more station devices. The access point can receive an association request or an operation mode change request frame from one or more of the station devices, and determine an acknowledgement option for each of the station devices that communicate the request to the access point. The access point can then use a multi-user transmission mode or a single user transmission mode for each of the station devices based on the acknowledgement option determined for each of the respective station devices.
Techniques create a semiconductor layout comprising a resistor structure having a defined baseline sheet resistance. The semiconductor layout includes a resistor marker layer over the resistor structure. A sheet resistance matching estimate is performed to ascertain a difference between the baseline sheet resistance and a resultant sheet resistance if the resistor structure were to be manufactured using a manufacturing process. A mask generating algorithm is generated based on the difference effective to achieve a sheet resistance of the resistor structure that is closer to the baseline sheet resistance rather than the resultant sheet resistance. The mask generating algorithm enables one or more masks to be generated to modify the resistor structure relative to the resistor marker layer.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns
H01L 27/105 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
G06F 30/392 - Floor-planning or layout, e.g. partitioning or placement
Disclosed is a parallel prefix adder structure with a carry bit generation circuit that generates primary carry bits for only some bit pairs and a sum circuit with ripple carry adders that use these primary carry bits to generate secondary carry bits and sum bits for a final sum. The carry bit generation circuit has different sections, which process different sequential sets of bit pairs and which have different sparsity configurations. As a result, generation of the primary carry bits is non-uniform. That is, in the different sections the primary carry bits are generated at different carry bit-to-bit pair ratios (e.g., the carry bit-to-bit pair ratios for the different sections can be 1:2, 1:4, and 1:2, respectively). For optimal performance, the specific bit pairs for which these primary carry bits are generated varies depending upon whether the maximum operand size is an odd number of bits or an even number.
G06F 7/506 - Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
The present invention is directed to data communication. In certain embodiments, the present invention provides switching mechanism for choosing between redundant communication links. Data received from a first set of communication links are processed to have alignment markers removed, and first figure of merit value is determined based on the data without alignment markers. Similarly, a second figure of merit value is determined for the data received from the second set of communication links. A switch selects between the first set of communication links and the second set of communication links based on their respective figure of merit values. Alignment markers are inserted into the data transmitted through the selected set of data links. There are other embodiments as well.
H04L 29/08 - Transmission control procedure, e.g. data link level control procedure
G06F 11/20 - Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
H04L 12/427 - Loop networks with decentralised control
H04L 1/22 - Arrangements for detecting or preventing errors in the information received using redundant apparatus to increase reliability
Embodiments described herein provide circuitry employing an inductor having enhanced circuit area usage. The circuitry includes an inductor having a first loop and a second loop adjoining the first loop to form a figure-eight configuration. The circuitry further includes a circuit component disposed at least partially inside an area defined by at least one of the first loop and the second loop. The inductor has an intersection portion between the first loop and the second loop. An input node is located proximate to the intersection portion, the input node having a first extension disposed inside the first loop. An output node is located proximate to the intersection portion. The output node has a second extension disposed inside the second loop. At least a first capacitor is coupled to the input node and the second extension, and at least a second capacitor coupled to the output node and the first extension.
H01F 27/40 - Structural association with built-in electric component, e.g. fuse
H01F 41/04 - Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils or magnets for manufacturing coils
61.
Using dipulse response to detect channel parameters
A receiver device receives a signal via a communication channel, the signal (i) having been transmitted by a transmitter device, and (ii) corresponding to a pseudorandom bit sequence (PRBS). The receiver device correlates the received signal with a known signal to generate a correlation signal. The known signal includes the PRBS. The receiver device identifies one or more characteristics of the correlation signal, and determines one or more parameters of the communication channel using the identified one or more characteristics of the correlation signal. The receiver device i) uses the one or more parameters corresponding to the communication channel to process subsequent signals received via the communication channel, and/or ii) communicates the one or more parameters to the transmitter device to prompt the transmitter device to preprocess subsequent signals to be transmitted via the communication channel by the transmitter device.
Provided is a method in a device under configuration (DUC) for communicating with a remote device over a wireless local area network. The method comprises transmitting a beacon to a remote device, providing a first security key to the remote device using first security measures, authenticating the remote device using second security measures, receiving encrypted secrets from the remote device, and obtaining network access using the secrets. Also, provided is a method of providing network access information over a wireless network. The method comprises identifying a device under configuration (DUC) from information contained in a beacon transmitted by the DUC, retrieving a public KEY from the DUC, authenticating the DUC using first security measures, encrypting secrets, and transmitting encrypted commands to the DUC.
Disclosed are scan flip-flops (SFFs) that reduce the dynamic power consumption of a system-on-chip (SOC) that incorporates them. Each SFF includes a master latch and a slave latch, each having a driver, a feed-forward path and a feedback path. Each SFF further includes at least one shared clock-gated power supply transistor, which is controlled by either a clock signal or an inverted clock signal to selectively and simultaneously connect a voltage rail to both the driver from one latch and the feedback path of the other latch. The different SFF embodiments have different numbers of shared clock-gated power supply transistors and various other different features designed for optimal power and/or performance. For example, the different SFF embodiments have different types of slave latch drivers; different types of transistors; and/or different types of master latch drivers (e.g., a single-stage, multiple clock phase-dependent driver or a multi-stage, single clock phase-dependent driver).
Systems and methods for carrier sensing and symbol timing in a multiple-antenna communication system are provided. A wireless receiver receives two or more signals from two or more antennas, respectively. A set of column vectors comprising time samples obtained from each of the received signals at the two or more antennas are generated. A multiple-antenna eigen-combining (MAEC) vector is computed based on the set of column vectors. The respective received signals are multiplied with a corresponding combining coefficient of the MAEC vector to obtain a respective weighted signal. A combined signal is generated by adding the respective weighted signals and carrier sensing and symbol timing is performed on the two or more received signals based on the combined signal.
H04B 7/06 - Diversity systems; Multi-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station
The present invention relates to telecommunication techniques and integrated circuit (IC) devices. In a specific embodiment, the present invention provides a laser deriver apparatus that includes a main DAC section and a mini DAC section. The main DAC section processes input signal received from a pre-driver array and generates an intermediate output signal. The mini DAC section provides a compensation signal to reduce distortion of the intermediate output signal. The intermediate output signal is coupled to output terminals through a cascode section and/or a T-coil section. There are other embodiments as well.
H01S 3/09 - Processes or apparatus for excitation, e.g. pumping
H01S 3/0933 - Processes or apparatus for excitation, e.g. pumping using optical pumping by incoherent light of a semiconductor, e.g. light emitting diode
H01S 3/091 - Processes or apparatus for excitation, e.g. pumping using optical pumping
H03M 1/68 - Digital/analogue converters with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits
The present disclosure relates to a structure which includes a voltage level shifter circuit which includes a first current mirror leg circuit and a second current mirror leg circuit, the first current mirror leg circuit receives an input signal on a low voltage power supply and level shifts the input signal to a high voltage power supply which is at a greater voltage than the low voltage power supply, and the high voltage power supply is output from the second current mirror leg circuit.
A method of operating a computer network system configured with disaggregated inputs/outputs. This system can be configured in a leaf-spine architecture and include a router coupled to a network source, a plurality of core switches coupled to the router, a plurality of aggregator switches coupled to each of the plurality of core switches, and a plurality of rack modules coupled to each of the plurality of aggregator switches. Each of rack modules can include an I/O appliance with a downstream aggregator module, a plurality of server devices each with PCIe interfaces, and an upstream aggregator module that aggregates each of the PCIe interfaces. A high-speed link can be configured between the downstream and upstream aggregator modules via aggregation of many serial lanes to provide reliable high speed bit stream transport over long distances, which allows for better utilization of resources and scalability of memory capacity independent of the server count.
Multiple data permutation operations in respective different dimensions are used to provide an overall effective data permutation using smaller blocks of data in each permutation than would be used in directly implementing the overall permutation in a single permutation operation. Data that has been permuted in one permutation operation is block interleaved, and the interleaved data is then permuted in a subsequent permutation operation. A matrix transpose is one example of block interleaving that could be applied between permutation operations.
H03M 13/00 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
H03M 13/27 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
H04L 1/00 - Arrangements for detecting or preventing errors in the information received
69.
Efficient ethernet multi-mode coding and modulation for twisted-pair
A method for communication, including, in a Physical Layer (PHY) transceiver, selecting a transmission bitrate from a plurality of transmission bitrates, for transmitting over a media interface bits received from an external device. The received bits are processed by generating, using a framing and encoding scheme that depends on at least the selected transmission bitrate, frames having a common frame length among the framing and encoding schemes. The frames are encoded to produce code words of a predefined Forward Error Correction Code (FEC) code, using a single FEC encoder that accepts a number of bits for encoding equal to the frame length. Sub-units of the code words are mapped into symbols using one of at least two mapping schemes that employ different voltage amplitude levels to define a transmission symbol, the mapping scheme being selected according to the selected transmission bitrate. The symbols are transmitted over the media interface.
H04L 1/00 - Arrangements for detecting or preventing errors in the information received
H03M 13/00 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
H04L 29/08 - Transmission control procedure, e.g. data link level control procedure
A tunable laser device based on silicon photonics includes a substrate configured with a patterned region comprising one or more vertical stoppers, an edge stopper facing a first direction, a first alignment feature structure formed in the patterned region along the first direction, and a bond pad disposed between the vertical stoppers. Additionally, the tunable laser includes an integrated coupler built in the substrate located at the edge stopper and a laser diode chip including a gain region covered by a P-type electrode and a second alignment feature structure formed beyond the P-type electrode. The laser diode chip is flipped to rest against the one or more vertical stoppers with the P-type electrode attached to the bond pad and the gain region coupled to the integrated coupler. Moreover, the tunable laser includes a tuning filter fabricated in the substrate and coupled via a wire waveguide to the integrated coupler.
H01S 5/0687 - Stabilising the frequency of the laser
H01S 5/343 - Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers in AIIIBV compounds, e.g. AlGaAs-laser
H01S 5/40 - Arrangement of two or more semiconductor lasers, not provided for in groups
H01S 5/10 - Construction or shape of the optical resonator
H01S 5/06 - Arrangements for controlling the laser output parameters, e.g. by operating on the active medium
An Ethernet networking system is disclosed. The system includes a first network device having an interface to receive Ethernet data from a first Ethernet source. An Ethernet media converter couples the network device to telephone wires. The Ethernet media converter includes a first Ethernet transceiver PHY integrated circuit (IC) having a first system-side interface for coupling to a first transmission media including multiple pairs of wires and a first line-side interface. The Ethernet media converter further includes a second Ethernet transceiver PHY IC having a second line-side interface connected to the first line-side interface, and a second system-side interface for coupling to the telephone wires.
The present invention is directed to a communication signal tracking system comprising an optical receiver including one or more delay line interferometers (DLIs) configured to demultiplex incoming optical signals and a transimpedance amplifier configured to convert the incoming optical signals to incoming electrical signals. The communication signal tracking system further includes a control module configured to calculate a bit-error-rate (BER) of the incoming electrical signals before forward-error correction decoding, and use the BER as a parameter for optimizing settings of the one or more DLIs in one or more iterations in a control loop and generating a back-channel data.
H04B 10/079 - Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems using an in-service signal using measurements of the data signal
H04B 10/69 - Electrical arrangements in the receiver
H04L 27/18 - Phase-modulated carrier systems, i.e. using phase-shift keying
G02B 6/12 - Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
G02B 6/293 - Optical coupling means having data bus means, i.e. plural waveguides interconnected and providing an inherently bidirectional system by mixing and splitting signals with wavelength selective means
Methods and systems for generating interrupts are provided. One method includes maintaining an in-pointer array by a response direct memory access (DMA) module of an adapter indicating that a message has been posted at a host memory of a host system coupled to the adapter for sending and receiving data using a network; updating an out-pointer array at the response DMA module by a host system processor, after the host system processor reads the message posted at the host memory; receiving event information by a hardware based, interrupt module of the response DMA module, the interrupt module using the event information and information stored at an interrupt array to determine that an interrupt is to be generated for the host processor; and generating the interrupt for the host processor by the interrupt module, without using an adapter processor.
G06F 13/24 - Handling requests for interconnection or transfer for access to input/output bus using interrupt
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
Aspects of the disclosure provide an apparatus that includes a transceiver circuit and a processing circuit. The transceiver circuit is configured to transmit and receive wireless signals. The processing circuit is configured to generate a request frame using an extended control frame format to indicate an enhanced fine timing measurement (EFTM) based range measurement to a second apparatus, cause the transceiver circuit to transmit, when a transmission opportunity (TXOP) is granted to the apparatus, wireless signals carrying the request frame to start the EFTM based range measurement that exchanges null data packets with the second apparatus, and determine a round trip time based on departure and arrival timing information of the null data packets.
A method and structure for signal propagation in a coherent optical receiver device. Asynchronous equalization helps to reduce complexity and power dissipation, and also improves the robustness of timing recovery. However, conventional devices using inverse interpolation filters ignore adaptation algorithms. The present invention provides for forward propagation and backward propagation. In the forward case, the filter input signal is forward propagated through a filter to the adaptation engine, while, in the backward case, the error signal is backward propagated through a filter to the asynchronous domain. Using such forward and backward propagation schemes reduces implementation complexity while providing optical device performance.
H04B 10/079 - Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems using an in-service signal using measurements of the data signal
H04L 1/00 - Arrangements for detecting or preventing errors in the information received
An optical dispersion compensator integrated with a silicon photonics system including a first phase-shifter coupled to a second phase-shifter in parallel on the silicon substrate characterized in an athermal condition. The dispersion compensator further includes a third phase-shifter on the silicon substrate to the first phase-shifter and the second phase-shifter through two 2×2 splitters to form an optical loop. A second entry port of a first 2×2 splitter is for coupling with an input fiber and a second exit port of a second 2×2 splitter is for coupling with an output fiber. The optical loop is characterized by a total phase delay tunable via each of the first phase-shifter, the second phase-shifter, and the third phase-shifter such that a normal dispersion (>0) at a certain wavelength in the input fiber is substantially compensated and independent of temperature.
G02B 6/293 - Optical coupling means having data bus means, i.e. plural waveguides interconnected and providing an inherently bidirectional system by mixing and splitting signals with wavelength selective means
G02B 6/122 - Basic optical elements, e.g. light-guiding paths
G02B 6/30 - Optical coupling means for use between fibre and thin-film device
H04B 10/2513 - Arrangements specific to fibre transmission for the reduction or elimination of distortion or dispersion due to chromatic dispersion
G02B 6/12 - Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
77.
Packaging of a directly modulated laser chip in photonics module
A package structure of a directly modulated laser in a photonics module includes a thermoelectric cooler including multiple conductor traces formed in a cool surface. The package structure further includes a directly modulated laser (DML) chip having a first electrode being attached with the cool surface and a second electrode at a distance away from the cool surface. Additionally, the package structure includes an interposer having a plurality of through-holes formed between a first surface to a second surface. The first surface is mounted to the cool surface such that each through-hole is aligned with one of the multiple conductor traces and the second surface being leveled with the second electrode. Moreover, the package structure includes a driver disposed on the second surface of the interposer with at least a galvanically coupled output port coupled directly to the second electrode of the DML chip.
A method for operation of a first communication device in a wireless local area network (WLAN) communication channel, having a plurality of component channels, between the first communication device and a second communication device is described. A first physical layer (PHY) protocol data unit (PPDU) and a second PPDU, distinct from the first PPDU, are generated. The first PPDU and second PPDU are transmitted simultaneously to the second communication device over the WLAN communication channel, including: transmitting the first PPDU via a first component channel within a first radio frequency (RF) channel segment that occupies a first frequency bandwidth, and transmitting the second PPDU via a second component channel within a second RF channel segment that occupies a second frequency bandwidth that does not overlap the first frequency bandwidth segment, and is separated from the first frequency bandwidth segment by a frequency gap.
H04L 1/16 - Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals
Systems and methods are provided for location determination in wireless communication networks. A client device with a location provider installed is configured to provide location data to a data engine server and to obtain location service from a positioning engine server or the location provider itself. The location provider based on one or more components implements the reference data delivery function and the client location determination function. The data engine server is configured to process the location data received from one or more client devices and maintain a location database. The data engine server based on one or more components implements the reference data retrieval function, station position calculation function, reference data management function, and assistance data delivery function, as it interacts with the client device. The positioning engine server is configured to process the location request data received from one or more client devices and calculate the locations of the client devices. The positioning engine server based on one or more components implements the positioning data retrieval function and device position calculation function, as it interacts with the client device. The location database stores the previously obtained location data.
A method and structure for probabilistic shaping and compensation techniques in coherent optical receivers. According to an example, the present invention provides a method and structure for an implementation of distribution matcher encoders and decoders for probabilistic shaping applications. The techniques involved avoid the traditional implementations based on arithmetic coding, which requires intensive multiplication functions. Furthermore, these probabilistic shaping techniques can be used in combination with LDPC codes through reverse concatenation techniques.
H04B 10/00 - Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
The present invention is directed to data communication. More specifically, embodiments of the present invention provide a transceiver that processes an incoming data stream and generates a recovered clock signal based on the incoming data stream. The transceiver includes a voltage gain amplifier that also performs equalization and provides a driving signal to track and hold circuits that hold the incoming data stream, which is stored by shift and holder buffer circuits. Analog to digital conversion is then performed on the buffer data by a plurality of ADC circuits. Various DSP functions are then performed over the converted data. The converted data are then encoded and transmitted in a PAM format. There are other embodiments as well.
H04B 10/00 - Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
H04L 7/04 - Speed or phase control by synchronisation signals
H03K 5/00 - Manipulation of pulses not covered by one of the other main groups of this subclass
H03K 19/0185 - Coupling arrangements; Interface arrangements using field-effect transistors only
H03L 7/093 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
H03L 7/099 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
H03L 7/197 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
H03L 7/23 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop with pulse counters or frequency dividers
H04L 7/00 - Arrangements for synchronising receiver with transmitter
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
A short-reach data link receiver includes an edge detector configured to generate a pulse on an edge of a data input, a first clock-data recovery path coupled to an output of the edge detector for recovering a clock and data from the output of the edge detector, a second clock-data recovery path coupled to the output of the edge detector for recovering the clock and data from the output of the edge detector, and a controller configured to alternate between the first and second clock-data recovery paths to recover the clock and data using one of the paths while calibrating the other path. The controller may swap the paths whenever calibration of one path is completed. That may include beginning calibration of the next path immediately after swapping of the paths. Alternatively, power consumption may be reduced by delaying calibration of the next path after swapping of the paths.
H04L 7/00 - Arrangements for synchronising receiver with transmitter
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
H03L 7/099 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
H03L 7/085 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
Aspects of the disclosure provide an apparatus that includes a receiving circuit and a processing circuit. The receiving circuit is configured to receive a satellite signal transmitted from a satellite. The satellite signal carries navigation bits that are transmitted with a navigation bit length. The processing circuit is configured to construct aiding navigation bits based on aiding ephemeris and almanac information that are provided by an aiding source other than the satellite signal. Further, the processing circuit is configured to strip the navigation bits from the satellite signal based on the aiding navigation bits to generate a post-stripping signal, and perform an integration on the post-stripping signal.
A timing recovery system generates a sampling clock to synchronize sampling of a receiver to a symbol rate of an incoming signal. The input signal is received over an optical communication channel. The receiver generates a timing matrix representing coefficients of a timing tone detected in the input signal. The timing tone representing frequency and phase of a symbol clock of the input signal and has a non-zero timing tone energy. The receiver computes a rotation control signal based on the timing matrix that represents an amount of accumulated phase shift in the input signal relative to the sampling clock. A numerically controlled oscillator is controlled to adjust at least one of the phase and frequency of the sampling clock based on the rotation control signal.
Methods and systems for a virtual machine environment are provided. One method includes allocating a memory for storing a dirty pages data structure for tracking writes to a virtual machine memory by an adapter coupled to a computing device and shared by a plurality of virtual machines; initiating a tracking operation by the adapter or a virtual function driver to track writes to the virtual memory; providing access to the dirty pages data structure in response to a query command, while the adapter or the virtual function driver tracks writes to the virtual machine memory; and providing a number of dirty pages within the dirty pages data structure and a pointer the dirty pages data structure by the adapter or the virtual function driver.
The present invention is directed to communication systems and electrical circuits. According to an embodiment, an input termination circuit includes a first attenuation resistor and a second attenuation resistor. The resistance values of these two resistors are adjusted in opposite directions to maintain a stable output impedance. There are other embodiments as well.
In one embodiment, a data message is generated at a first system-on-chip (SOC) for transmission to a second SOC. A stream of data words is generated from the data message, the data words alternating between even and odd data words. Each data word in the stream of data words is divided into a first pattern of slices for even data words and a second pattern of slices for odd data words, with the slices distributed across plural output ports at the first SOC. At each output port, two slices from two successive cycles are grouped. The grouped slices are encoded using an encoding scheme to produce an N-bit symbol at M-bits per cycle, alternating between high and low parts of the encoding. Plural metaframes are generated from a stream of symbols and the metaframes for each of the output ports are transmitted to the second SOC.
Systems and methods for decoding a product code is provided. The system comprises a media, a first buffer, a second buffer, and a decoder. The media stores a plurality of codewords of a first code of the product code. The first buffer temporarily stores at least one codeword that has failed to be decoded. The second buffer temporarily stores soft information to be used in decoding. The decoder is configured to decode the plurality of codewords, determine if a first count of the at least one failed codeword exceeds a designed maximum number of codewords recoverable using the decoding method. In response to determining that the first count does not exceed the predefined threshold, the decoder iteratively process each failed codeword of the at least one failed codeword with the soft information, and attempt to decode at least one of each failed codeword that has been iteratively processed.
H03M 13/29 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
G11C 29/52 - Protection of memory contents; Detection of errors in memory contents
H03M 13/45 - Soft decoding, i.e. using symbol reliability information
A packaged transmitter device includes a base member comprising a planar part mounted with a thermoelectric cooler, a transmitter, and a coupling lens assembly, and an assembling part connected to one side of the planar part. The device further includes a circuit board bended to have a first end region and a second end region being raised to a higher level. The first end region disposed on a top surface of the planar part includes multiple electrical connection patches respectively connected to the thermoelectric and the transmitter. The second end region includes an electrical port for external connection. Additionally, the device includes a cover member disposed over the planar part. Furthermore, the device includes a cylindrical member installed to the assembling part for enclosing an isolator aligned to the coupling lens assembly along its axis and connected to a fiber to couple optical signal from the transmitter to the fiber.
An ALU capable of generating a multiply accumulation by compressing like-magnitude partial products. Given N pairs of multiplier and multiplicand, Booth encoding is used to encode the multipliers into M digits, and M partial products are produced for each pair of with each partial product in a smaller precision than a final product. The partial products resulting from the same encoded multiplier digit position, are summed across all the multiplies to produce a summed partial product. In this manner, the partial product summation operations can be advantageously performed in the smaller precision. The M summed partial products are then summed together with an aggregated fixup vector for sign extension. If the N multipliers are equal to a constant, a preliminary fixup vector can be generated based on a predetermined value with adjustment on particular bits, where the predetermined value is determined by the signs of the encoded multiplier digits.
G06F 7/544 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices for evaluating functions by calculation
G06F 7/533 - Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even
The present invention is directed to data communication systems and techniques thereof. More specifically, embodiments of the present invention provide a retimer module that includes plurality of communication lanes for interfacing with a host system and a line system. The retimer module includes a link monitor and cross point sections. The retimer also includes a management interface module. There are other embodiments as well.
A first communication device in a first wireless network determines a transmit power for transmitting a first packet during a spatial reuse opportunity corresponding to a transmission in a second wireless network. Determining the transmit power includes using a spatial reuse parameter, indicative of an acceptable interference level in the second wireless network, included in a second packet transmitted by a second communication device in the second wireless network. The first communication device generates the first packet to include information to indicate to a third communication device, that is an intended receiver of the first packet, to not transmit an acknowledgment of the first packet according to a normal acknowledgment procedure during the spatial reuse opportunity. The first communication device transmits the first packet at the determined transmit power, and receives the acknowledgement from the third communication device, the acknowledgement having not been transmitted according to the normal acknowledgment procedure.
H04W 52/24 - TPC being performed according to specific parameters using SIR [Signal to Interference Ratio] or other wireless path parameters
H04L 5/00 - Arrangements affording multiple use of the transmission path
H04W 52/36 - Transmission power control [TPC] using constraints in the total amount of available transmission power with a discrete range or set of values, e.g. step size, ramping or offsets
Radio-frequency front-end circuitry includes an output terminal, a receive amplifier controllably coupled to the output terminal, at least one transmit amplifier controllably inductively coupled to the output terminal, and at least one impedance element controllably coupled between ground and one of the at least one transmit amplifier to reduce degradation of output of the radio-frequency front-end circuitry when the at least one transmit amplifier is not in use. In differential signaling, there is an impedance element between ground and each pole of the differential signal. A second transmit amplifier may generate second transmit signals and harmonics of the second transmit signals, and the second transmit amplifier may be switchably connected to the output of a first transmit amplifier so that output of the second transmit amplifier is filtered by the one of the first transmit amplifier. The transmit amplifiers may include a WiFi power amplifier and a BLUETOOTH® power amplifier.
This disclosure describes systems and methods for detecting motion based on channel correlation in wireless communication signals. A receiver at a first wireless communication device is capable of wirelessly communicating with a second wireless communication device. The first wireless communication device is configured to receive from the second wireless communication device via two or more subcarriers a first packet and a channel correlation for the first packet across the two or more subcarriers. Control circuitry is configured to estimate a channel energy difference for the receiver based on the channel correlation for the first packet. A motion detection decision is then made based on the estimated channel energy difference.
A method and structure for tap centering in a coherent optical receiver device. The center of gravity (CG) of the filter coefficients can be used to evaluate a proper convergence of a time-domain adaptive equalizer. However, the computation of CG in a dual-polarization optical coherent receiver is difficult when a frequency domain (FD) adaptive equalizer is adopted. In this case, the implementation of several inverse fast-Fourier transform (IFFT) stages is required to back time domain impulse response. Here, examples of the present invention estimate CG directly from the FD equalizer taps and compensate for an error of convergence based off of the estimated CG. This estimation method and associated device architecture is able to achieve an excellent tradeoff between accuracy and complexity.
H04B 10/079 - Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems using an in-service signal using measurements of the data signal
H04L 1/00 - Arrangements for detecting or preventing errors in the information received
A receiver (e.g., for a 10G fiber communications link) includes an interleaved ADC coupled to a multi-channel equalizer that can provide different equalization for different ADC channels within the interleaved ADC. That is, the multi-channel equalizer can compensate for channel-dependent impairments. In one approach, the multi-channel equalizer is a feedforward equalizer (FFE) coupled to a Viterbi decorder, for example, a sliding block Viterbi decoder (SBVD); and the FFE and/or the channel estimator for the Viterbi decoder are adapted using the LMS algorithm.
H04B 1/38 - Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
H04B 10/69 - Electrical arrangements in the receiver
H03M 13/41 - Sequence estimation, i.e using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
H04B 3/23 - Reducing echo effects or singing; Opening or closing transmitting path; Conditioning for transmission in one direction or the other using a replica of transmitted signal in the time domain, e.g. echo cancellers
A master integrated circuit (IC) chip includes transmit circuitry and receiver circuitry. The transmit circuitry includes a timing signal generation circuit to generate a first timing signal, and a driver to transmit first data in response to the first timing signal. A timing signal path routes the first timing signal in a source synchronous manner with the first data. The receiver circuitry includes a receiver to receive second data from a slave IC chip, and sampling circuitry to sample the second data in response to a second timing signal that is derived from the first timing signal.
The present invention is directed to electrical circuits. More specifically, embodiments of the present invention provide a charge pump, which can be utilized as a part of a clock data recovery device. Early and late signals are used as differential switching voltage signals in the charge pump. The first switch and a second switch are used for controlling the direction of the current flowing into the loop filter. Input differential voltages to the switches are being generated with an opamp negative feedback loop. The output voltage of the first switch and the second switch is used in conjunction with a resistor to generate a charge pump current. There are other embodiments as well.
H03L 7/08 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop
H03L 7/07 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
H03L 7/081 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop provided with an additional controlled phase shifter
H03L 7/099 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
H03L 7/187 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number using means for coarse tuning the voltage controlled oscillator of the loop
H03K 5/135 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
H02M 3/07 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
H03L 7/093 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
H04L 7/00 - Arrangements for synchronising receiver with transmitter
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
99.
Light engine based on silicon photonics TSV interposer
A method for forming a silicon photonics interposer having through-silicon vias (TSVs). The method includes forming vias in a front side of a silicon substrate and defining primary structures for forming optical devices in the front side. Additionally, the method includes bonding a first handle wafer to the front side and thinning down the silicon substrate from the back side and forming bumps at the back side to couple with a conductive material in the vias. Furthermore, the method includes bonding a second handle wafer to the back side and debonding the first handle wafer from the front side to form secondary structures based on the primary structures. Moreover, the method includes forming pads at the front side to couple with the bumps at the back side before completing final structures based on the secondary structures and debonding the second handle wafer from the back side.
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
G02B 6/42 - Coupling light guides with opto-electronic elements
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different main groups of groups , or in a single subclass of , , e.g. forming hybrid circuits
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
G02B 6/12 - Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
100.
Data communication systems with forward error correction
Embodiments of the present invention include an apparatus that receives date from multiple lanes, which are then aligned and synchronized for transcoding and encoding.
patents