A memory device includes alternating stacks of insulating layers and electrically conductive layers that are laterally spaced apart from each other along a second horizontal direction, laterally extend along the first horizontal direction through an inter-array region, a first memory array region and a second memory array region that is laterally spaced apart along the first horizontal direction from the memory array region by the inter-array region. Each electrically conductive layer within the alternating stacks has a respective bridge region having a respective strip width along the second horizontal direction within the inter-array region, and the strip width of a topmost electrically conductive layer in a first-tier alternating stack is smaller than the strip width of a topmost electrically conductive layer in a second-tier alternating stack which overlies the first-tier alternating stack.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 43/50 - EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
2.
ERASE METHOD FOR NON-VOLATILE MEMORY WITH MULTIPLE TIERS
A non-volatile memory system comprises a plurality of non-volatile memory cells divided into three or more tiers. The memory cells can be programmed, erased and read. In order to achieve uniform erase speed for the three or more tiers, the erase process comprises applying a larger voltage bias to control gates of non-volatile memory cells in the outer tiers than the voltage bias applied to control gates of non-volatile memory cells in one or more inner tiers.
In a multi-tiered non-volatile memory structure that can perform operations on sub-blocks, performance of the different tiers/sub-blocks is made consistent by using different word line to word line pitches in the different tiers/sub-blocks.
H10B 43/50 - EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
4.
THREE-DIMENSIONAL MEMORY DEVICE CONTAINING MEMORY OPENING MONITORING AREA AND METHODS OF MAKING THE SAME
A method of forming a three-dimensional semiconductor device includes forming an alternating stack of insulating layers and spacer material layers over a substrate, forming memory openings formed in the memory array region and monitor openings formed in a monitor region though the alternating stack, forming memory opening fill structures in the memory openings, forming monitor opening fill structures by depositing a monitor opening fill material in the monitor openings, recessing first portions of the alternating stack in a contact region and second portions of the alternating stack in the monitor region, and determining at least one characteristic of the recessed surfaces of the monitor opening fill structures. At least one characteristic of the memory openings or memory opening fill structures may be determined based on the determining at least one characteristic of the recessed surfaces of the monitor opening fill structures.
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/50 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
H10B 43/50 - EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
5.
THREE-DIMENSIONAL MEMORY DEVICE WITH SOURCE LINE ISOLATION AND METHOD OF MAKING THE SAME
A memory device includes a horizontal source layer which is laterally separated into laterally isolated portions located in adjacent memory blocks by a dielectric backside trench fill structure or a source isolation dielectric structure.
H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
H01L 21/77 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
H01L 21/82 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
A conductive hard mask layer can be patterned with peripheral discrete openings. An anisotropic etch process can be performed to form peripheral discrete via cavities, which are subsequently expanded to form a continuous moat trench. An edge seal structure can be formed in the continuous moat trench. Alternatively, a conductive bridge structure may be formed prior to formation of a patterned conductive hard mask layer, and a moat trench can be formed around a periphery of the semiconductor die while the conductive bridge structure provides electrical connection between an inner portion and an outer portion of the conductive hard mask layer. The entire conductive hard mask layer can be electrically connected to a semiconductor substrate to reduce or prevent arcing during an anisotropic etch process that forms the peripheral discrete via cavities or the moat trench.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
An apparatus includes a control circuit configured to connect to NAND strings that are connected to bit lines, where each bit line is connected to a plurality of NAND strings in a corresponding plurality of regions of a block. The control circuit is configured to apply a read voltage in read operations directed to NAND strings of the plurality of regions of the block and subsequently adjust the read voltage by a first predetermined amount for read operations directed to NAND strings of a first region of the block. The control circuit is further configured to adjust the read voltage by a second predetermined amount for read operations directed to NAND strings of a second region of the block. The first and second predetermined amounts are based on respective locations of the first and second regions in the block.
An apparatus is provided that includes a block of memory cells having a NAND string that includes a first select transistor, and a control circuit coupled to the block of memory cells. The control circuit is configured to perform an erase operation on the block of memory cells by determining a first count of a number of times that the block of memory cells previously has been programmed and erased, determining based on the first count a first drain-to-gate voltage of the first select transistor, wherein the first drain-to-gate voltage is configured to cause the first select transistor to generate a first gate-induced drain leakage current, and applying a first erase pulse to the first select transistor based on the determined first drain-to-gate voltage.
To reduce spikes in the current used by a NAND memory die, different ramp rates for different regions, or zones, of word lines are used for the pass voltage applied to unselected word lines during a program operation. The properties of the word lines, such as their resistance and capacitance (RC) values, vary across the NAND memory array. By determining the RC values of the word lines across the array, the word lines can be broken into multiple zones based on these properties. The zones can then be individually assigned different ramp rates for applying a pass voltage to the unselected word lines, where a parameter for the ramp rates can be stored as a register value on the memory die.
To reduce spikes in the current used by a NAND memory die during a write operation using smart verify, different amounts of delay are introduced into the loops of the programing algorithm. Depending on the number of verify levels following a programming pulse, differing amounts of wait time are used before biasing a selected word line to the verify levels or levels. For example, if only a single verify level is used, a shorter delay is used than if two verify levels are used.
Memory cells are arranged as NAND strings to form a block divided into sub-blocks, and each NAND string includes a dummy memory cell connected to a dummy word line. Memory cells are programmed by applying programming pulses to a selected word line in a selected sub-block with program-verify performed between pulses. Unselected NAND strings are inhibited from programming by boosting channels of the unselected NAND strings in the selected sub-block from a positive pre-charge voltage to a boosted voltage. The pre-charging of the channels of unselected NAND strings is performed while lowering voltages at the end of program-verify by applying overdrive voltages to data word lines in a sub-block closer to the source line than the selected sub-block and lowering to a resting voltage a dummy word line between the sub-blocks prior to lowering to a resting voltage the data word lines in the sub-block closer to the source line.
To reduce spikes in the current used by a NAND memory die, different ramp rates are used for the pass voltage applied to unselected word lines during a program operation depending on whether data is stored in a multi-level cell (MLC) format or in a single level cell (SLC) format. These ramp rates can be determined through device characterization and stored as parameter values on the memory die. Different ramp rate interval values can also be used for the pass voltage applied to unselected word lines during a program operation depending on whether data is stored in an MLC format or in an SLC format.
G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
A bonded assembly includes a first memory die and a logic die. The first memory die includes a first alternating stack of first insulating layers and first electrically conductive layers, first memory opening fill structures, a first stepped dielectric material portion, and first column-shaped conductive via structures including a respective conductive shaft portion vertically extending through a respective subset of the first electrically conductive layers, a respective conductive base portion, and a respective conductive capital portion contacting a horizontal surface of a respective one of the first electrically conductive layers. The logic die includes logic-side bonding pads that are bonded to the first column-shaped conductive via structures.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
14.
DYNAMIC WORD LINE RECONFIGURATION FOR NAND STRUCTURE
Technology is disclosed herein reconfiguring word lines as either data word lines or dummy word lines. In a sub-block mode reconfigurable word lines are used as dummy word lines that provide electrical isolation between data word lines in a block. The block may be divided into an upper tier, a middle tier, and a lower tier, with the reconfigurable word lines within the middle tier. In a full-block mode the reconfigurable group of the word lines are used as data word lines. Because the reconfigurable word lines are used as data word lines in the full-block mode storage capacity is greater in the full-block mode than in the sub-block mode. Moreover, because the sub-blocks are smaller in size but greater in number than the full-blocks, the memory system may be provisioned with fewer blocks and still meet user storage requirements in both the full-block mode and the sub-block mode.
G11C 16/08 - Address circuits; Decoders; Word-line control circuits
G11C 8/14 - Word line organisation; Word line lay-out
G11C 16/14 - Circuits for erasing electrically, e.g. erase voltage switching circuits
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
15.
THREE-DIMENSIONAL MEMORY DEVICE INCLUDING TRENCH BRIDGES AND METHODS OF FORMING THE SAME
A three-dimensional memory device includes layer stacks each of which includes a first-tier alternating stack of first insulating layers and first electrically conductive layers and a second-tier alternating stack of second insulating layers and second electrically conductive layers separated by a backside trench. Memory opening fill structures vertically extend through a respective layer stack, and includes a respective vertical stack of memory elements and a respective vertical semiconductor channel. In one embodiment, a bridge structure spans an entire width of the backside trench such that a top surface of the bridge structure is located below a top surface of the second-tier alternating stack, and a bottom surface of the bridge structure is located above a bottom surface of the first-tier alternating stack. In another embodiment, a perforated bridge structure includes a plurality of vertically-extending openings.
H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
H01L 21/77 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
H01L 21/82 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
Non-volatile memory cells are programmed by pre-charging channels of unselected non-volatile memory cells connected to a selected data word line, boosting the channels of unselected non-volatile memory cells connected to the selected data word line after the pre-charging and applying a program voltage pulse to selected non-volatile memory cells connected to the selected data word line while boosting. The pre-charging includes applying pre-charge voltages to one set of data word lines and dummy word line(s) as well as applying overdrive voltages to another set of data word lines connected to already programmed memory cells. At the end of the pre-charging, the dummy word lines are ramped down to a resting voltage prior to lowering the data word lines to one or more resting voltages.
In a non-volatile memory, to achieve a shallow and tight erased threshold voltage distribution, a process is performed that includes erasing a group of non-volatile memory cells, identifying a first set of the bit lines that are connected to non-volatile memory cells of the group that are erased past a lower limit for erased non-volatile memory cells and identifying a second set of the bit lines that are connected to non-volatile memory cells of the group that are not erased past the lower limit for erased non-volatile memory cells, and applying programming to non-volatile memory cells connected to the first set of bit lines while inhibiting programming for non-volatile memory cells connected to the second set of bit lines.
An apparatus is provided that includes a block including a word line coupled to a plurality of memory cells, and a control circuit coupled to the word line. The control circuit is configured to program the plurality of memory cells by applying program pulses to the word line in a plurality of program loops, determining a first count of a number of the program loops used to complete programming a first subset of the plurality of memory cells to a first programmed state, first comparing the first count to a corresponding first lower limit and a corresponding first upper limit, and determining whether programming the plurality of memory cells has failed based on a result of the first comparing step.
In a non-volatile memory system that performs programming of selected memory cells (in coordination with pre-charging and boosting of channels for unselected memory cells) and program-verify to determine whether the programming was successful, the system transitions from program-verify to the next dose of programming by concurrently lowering a voltage applied to a selected word line and voltages applied to word lines on a first side of the selected word line at the conclusion of program-verify. Subsequent to lowering the voltage applied to the selected word line, the system successively lowers voltages applied to groups of one or more word lines on a second side of the selected word line at the conclusion of program-verify beginning with a group of one or more word lines immediately adjacent the selected word line and progressing to other groups of one or more word lines disposed increasingly remote from the selected word line.
An erase process for a group of non-volatile memory cells comprises applying doses of erasing to the group and performing erase verify between pairs of successive doses of erasing. The time needed to complete the erase process can be reduced by optimizing the order of performing erase verify. For example, erase verify can be performed by separately performing erase verify for multiple portions of the group in order from previously determined slowest erasing portion of the group to previously determined fastest erasing portion of the group, and aborting the performing of erase verify prior to completion of erase verify for all of the portions of the group in response to a number erase errors exceeding a limit.
An apparatus is provided that includes a block of memory cells and a control circuit coupled to the block of memory cells. The control circuit is configured to perform an erase operation on the block of memory cells by determining a first count of a number of times that the block of memory cells previously has been programmed and erased, determining a threshold number based on the first count, and determining whether the erase operation passed or failed based on the threshold number.
A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, where the electrically conductive layers include word line electrically conductive layers and a first select-level electrically conductive layer, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a memory film and a vertical semiconductor channel. A vertical cross-sectional profile of an outer sidewall of the vertical semiconductor channel is straight throughout the word line electrically conductive layers and contains a lateral protrusion at a level of the first select-level electrically conductive layer.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/50 - EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
H10B 41/50 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
23.
THREE-DIMENSIONAL MEMORY DEVICE CONTAINING ETCH STOP METAL PLATES FOR BACKSIDE VIA STRUCTURES AND METHODS FOR FORMING THE SAME
A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers that is located on a front side of at least one semiconductor material layer; memory openings vertically extending through the alternating stack; memory opening fill structures; and a dielectric material portion contacting sidewalls of the insulating layers of the alternating stack. In one embodiment, a connection via structure can vertically extend through the dielectric material portion, and a metal plate can contact the connection via structure. Alternately or additionally, an integrated via and pad structure may be provided, which includes a conductive via portion vertically extending through the dielectric material portion and a conductive pad portion located on an end of the conductive via portion.
A memory apparatus and method of operation are provided. The apparatus includes memory cells connected word lines. The memory cells are disposed in strings and configured to retain a threshold voltage. A control means is configured to apply a program voltage to selected ones of the word lines while applying pass voltages to unselected ones of the word lines and ramp down both the selected ones of the plurality of word lines and the unselected ones of the word lines to a recovery voltage at a start of a verify phase of each of a plurality of program loops and apply a targeted word line bias to each of the word lines during the verify phase. The control means is also configured to adjust the recovery voltage based on the targeted word line bias applied to each of the plurality of word lines during the verify phase.
The memory device includes a memory block with an array of memory cells. The memory device also includes control circuitry that is in communication with the memory cells. The control circuitry is configured to program a group of the memory cells in a programming operation that does not include verify to obtain a natural threshold voltage (nVt) distribution, calculate an nVt width of the nVt distribution, compare the nVt width to a threshold, and identify the memory block as being vulnerable to cross-temperature read errors in response to the nVt width exceeding the threshold.
G11C 16/26 - Sensing or reading circuits; Data output circuits
G11C 7/04 - Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
G11C 29/02 - Detection or location of defective auxiliary circuits, e.g. defective refresh counters
26.
RELIABILITY IMPROVEMENT THROUGH DELAY BETWEEN MULTI-STAGE PROGRAMMING STEPS IN NON-VOLATILE MEMORY STRUCTURES
A method for multi-stage programming of a non-volatile memory structure, wherein the method comprises: (1) initiating a programming operation with respect to a memory block, (2) applying a programming algorithm to the memory block, wherein the programming algorithm comprises at least a first programming stage and a second programming stage, and (3) between the first programming stage and the second programming stage, applying a time delay according to a pre-determined amount of time. Further, the pre-determined amount of time may be defined as the amount of time that, according to a probabilistic function, permits de-trapping of any charges unintentionally trapped within a memory cell of the memory block as a result of the first programming stage.
A storage device comprises: a non-volatile memory including control circuitry and an array of memory cells formed using a set of word lines and a set of bit lines. A controller, coupled to the non-volatile memory, configured to: during a program loop for programming a set of states, select a first bitline biasing mode that dictates a scheme for biasing a first set of bitlines and apply the first bitline biasing mode before verifying the set of states. The controller further configured to during another program loop for programming another set of states, select a second bitline biasing mode that dictates a scheme for biasing a second set of bitlines and apply the second bitline biasing mode before verifying the other set of states.
The memory device includes a plurality of memory blocks that can individually operate in either a multi-bit per memory cell mode or a single-bit per memory cell mode. Certain voltage parameters during programming and reading are shared between these two operating modes, and certain voltage parameters are unique to each operating mode. One unique voltage parameter is a pass voltage VREADK that is applied to word lines adjacent a selected word line being read. Another unique voltage parameter is a VSGD voltage that is applied to a select gate drain transistor during programming. Yet another unique voltage parameter is an inhibit voltage that is applied to a bit line coupled with a memory cell being inhibited from programming while other memory cells are programmed.
G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
29.
THREE-BIT-PER-CELL PROGRAMMING USING A FOUR-BIT-PER-CELL PROGRAMMING ALGORITHM
An apparatus is provided that includes a plurality of memory cells, logic circuits coupled to the memory cells and configured to store 4-bit data in each of the memory cells, and a control circuit coupled to the memory cells and the logic circuits. The control circuit configured to cause the logic circuits to store 3-bit data in each of the memory cells.
A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, a dielectric moat fill structure that includes a nested structure including, from outside to inside, an outer dielectric liner having a first Young's modulus, an outer material layer having a second Young's modulus greater than the first Young's modulus, a dielectric fill material portion, an inner material layer having the second Young's modulus, and an inner dielectric liner having the first Young's modulus, a vertically alternating sequence of insulating plates and dielectric material plates at least partially laterally surrounded by the dielectric moat fill structure, and an interconnection via structure vertically extending the vertically alternating sequence.
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 41/50 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
H10B 43/50 - EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
31.
THREE-DIMENSIONAL MEMORY DEVICE INCLUDING COMPOSITE BACKSIDE METAL FILL STRUCTURES AND METHODS FOR FORMING THE SAME
A three dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate; memory stack structures vertically extending through tire alternating stack: and a backside trench fill structure. The backside trench fill structure includes a backside trench insulating spacer and a backside contact via structure. The backside contact via structure may include a tapered metallic nitride liner and at least one core fill conductive material portion. Alternatively, the backside contact via structure may include a tungsten nitride liner, a metallic nitride liner other than tungsten nitride, and at least one core fill conductive material portion.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
In order to achieve tight and uniform erased threshold voltage distributions in a non-volatile memory system that includes non-volatile memory cells arranged in blocks that have multiple sub-blocks and has an erase process using gate induced drain leakage (GIDL) to generate charge carriers that change threshold voltage of the memory cells, the magnitude of the GIDL is adjusted separately for the sub-blocks.
A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to word lines and disposed in strings and configured to retain a threshold voltage. The memory apparatus also includes a charge pump configured to ramp up to a program voltage in a pump setting process and supply the program voltage to the word lines during a program operation and ramp down from the program voltage in a pump resetting process. A control means is configured to successively apply one of a series of pulses of the program voltage from the charge pump to each selected one of the word lines to program the memory cells during the program operation. The control means is also configured to skip the pump setting process and the pump resetting process of the charge pump in between each of the series of pulses of the program voltage.
Technology is disclosed herein for refreshing threshold switching selectors in programmable resistance memory cells in cross-point memory arrays. The Vt of the threshold switching selector may drift over time. The memory system resets the Vt of the threshold switching selectors with a selector refresh operation and uses a separate data refresh operation to refresh data in programmable resistance memory elements. The data refresh operation itself may also refresh the selector. However, the threshold switching selector refresh operation is faster than the data refresh operation. Moreover, the selector refresh operation consumes much less power and/or current then the data refresh operation. The selector refresh operation may thus be performed at a higher rate than the data refresh operation.
G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
35.
THREE-DIMENSIONAL MEMORY DEVICE CONTAINING DUAL-DEPTH DRAIN-SELECT-LEVEL ISOLATION STRUCTURES AND METHODS FOR FORMING THE SAME
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, and memory opening fill structures located within a respective one of the memory openings. Composite drain-select-level isolation structures divide each drain-select-level electrically conductive layer into a respective plurality of electrically conductive strips. Each drain-select-level isolation structure includes a respective first drain-select-level isolation material portion vertically extending through each drain-select-level electrically conductive layers and a respective set of second drain-select-level isolation material portions vertically extending through each of the drain-select-level electrically conductive layers and at least a topmost dummy electrically conductive layer that underlies the drain-select-level electrically conductive layers.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 43/50 - EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
H10B 41/50 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
36.
TEMPERATURE-DEPENDENT WORD LINE VOLTAGE AND DISCHARGE RATE FOR REFRESH READ OF NON-VOLATILE MEMORY
A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to one of a plurality of word lines. The memory cells are disposed in strings and configured to retain a threshold voltage corresponding to one of a plurality of data states. A control means is coupled to the plurality of word lines and the strings and is configured to apply a read voltage to a selected ones of the plurality of word lines during a read operation and ramp down to a discharge voltage at an end of the read operation and apply a ready voltage to the selected ones of the plurality of word lines during a ready period of time following the read operation. The control means is also configured to adjust at least one of the discharge voltage and the ready voltage based on a temperature of the memory apparatus.
G11C 16/08 - Address circuits; Decoders; Word-line control circuits
G11C 7/04 - Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
G11C 16/26 - Sensing or reading circuits; Data output circuits
G11C 8/14 - Word line organisation; Word line lay-out
37.
LOW POWER MULTI-LEVEL CELL (MLC) PROGRAMMING IN NON-VOLATILE MEMORY STRUCTURES
A method for programming a memory array of a non-volatile memory structure, the memory comprising a population of MLC NAND-type memory cells, wherein the method comprises applying: (1) an inhibit condition to one or more bit lines of the memory array, and (2) a zero voltage condition to one or more bit lines of the memory array such that less than half of the adjacent bit lines of the memory array experience a voltage swing between the inhibit condition and the zero voltage condition.
G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
G06F 3/06 - Digital input from, or digital output to, record carriers
38.
HIGH SPEED MULTI-LEVEL CELL (MLC) PROGRAMMING IN NON-VOLATILE MEMORY STRUCTURES
A method for programming a memory array of a non-volatile memory structure, wherein the memory array comprises a population of MLC NAND-type memory cells, and the method comprises: (1) in a first program pulse, programming selected memory cells according to a first programmable state and a second programmable state, and (2) in a second program pulse, programming the selected memory cells according to a third programmable state.
G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
G11C 16/14 - Circuits for erasing electrically, e.g. erase voltage switching circuits
THREE-DIMENSIONAL MEMORY DEVICE CONTAINING WORD LINE CONTACTS WHICH EXTEND THROUGH DRAIN-SELECT-LEVEL ISOLATION STRUCTURES AND METHODS OF MAKING THE SAME
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, where the electrically conductive layers include word lines and drain select gate electrodes that contain plurality of drain-select-level electrically conductive strips which are located above the word lines, memory stack structures vertically extending through the alternating stack, drain-select-level isolation structures located between a respective neighboring pair of drain-select-level electrically conductive strips, and a first laterally-insulated contact via assembly including a first layer contact via structure and a first tubular insulating spacer. The first laterally-insulated contact via assembly contacts a top surface of a first word line of the word lines, and the first laterally-insulated contact via assembly laterally contacts a first drain-select-level isolation structure of the drain-select-level isolation structures.
H10B 43/50 - EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
H10B 41/50 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
40.
MEMORY CELL GROUP READ WITH COMPENSATION FOR DIFFERENT PROGRAMMING SPEEDS
Technology is disclosed herein for a memory system that compensates for different programming speeds in two sets of memory cells when reading those two sets of memory cells. The memory system programs a group of the memory cells to one or more data states. In one aspect, the memory cells are not verified during programming. The group has a first set of memory cells that program at a first speed and a second set of memory cells that program at a second speed. The memory system reads the first set of the memory cells with a first set of read parameters and reads the second set of the memory cells with a second set of read parameters. The first set of read parameters are different from the second set of read parameters to compensate for the different programming speeds.
A bonded assembly includes a first semiconductor die containing first semiconductor devices and a first bonding pad embedded within a first silicon oxide layer, where the first bonding pad includes a first copper containing portion, a second semiconductor die containing second semiconductor devices and a second bonding pad that is embedded within a second silicon oxide layer and is bonded to the first bonding pad via metal-to-metal bonding, where the second bonding pad includes a second copper containing portion, and at least one metal silicon oxide layer interposed between the first bonding pad and the second silicon oxide layer. In one embodiment, at least one metal silicon oxide layer is a manganese silicon oxide layer.
An apparatus disclosed herein comprises: a plurality of memory cells and a control circuit coupled to the plurality of memory cells.The control circuit is configured to: acquire a first set of read levels on a wordline of a first block of pages of memory cells; acquire a second set of read levels on a first wordline of a second block of pages of a second set of memory cells in response to determining that the fail bit count of the page after a read operation is above the threshold amount; and acquire a third set of read levels on a second wordline of the second block in response to determining that the fail bit count of the page after the second read operation is above the threshold amount.
In a memory array with a cross-point structure, at each cross-point junction a programmable resistive memory element, such as an MRAM memory cell, is connected in series with a threshold switching selector, such as an ovonic threshold switch. The threshold switching selector switches to a conducting state when a voltage above a threshold voltage is applied. When powered down for extended periods, the threshold voltage can drift upward. If the drift is excessive, this can make the memory cell difficult to access and can disturb stored data values when accessed. Techniques are presented to determine whether excessive voltage threshold drift may have occurred, including a read based test and a time based test. Techniques are also presented for initializing a cross-point array, for both first fire and cold start, by using voltage levels shifted from half-select voltage levels used in a standard memory access.
G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
44.
THREE-DIMENSIONAL MEMORY DEVICE CONTAINING A PILLAR CONTACT BETWEEN CHANNEL AND SOURCE AND METHODS OF MAKING THE SAME
A semiconductor structure includes a memory die bonded to a logic die. The memory die includes an alternating stack of insulating layers and electrically conductive layers, a semiconductor material layer located on a distal surface of the alternating stack, a dielectric spacer layer located on a distal surface of the semiconductor material layer, memory opening fill structures vertically extending through the alternating stack, through the semiconductor material layer, and at least partly through the dielectric spacer layer, and a source layer located on a distal surface of the dielectric spacer layer and contacting pillar portions of the vertical semiconductor channels that are embedded within the dielectric spacer layer.
H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 27/11565 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the top-view layout
H01L 27/1157 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the memory core region with cell select transistors, e.g. NAND
H01L 27/11575 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the boundary region between the core and peripheral circuit regions
H01L 27/11556 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 27/11519 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the top-view layout
H01L 27/11524 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the memory core region with cell select transistors, e.g. NAND
H01L 27/11548 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the boundary region between the core and peripheral circuit regions
45.
NON-VOLATILE MEMORY WITH PLANE INDEPENDENT SCREENING
A non-volatile storage apparatus that comprises a plurality of planes of non-volatile memory cells is capable of concurrently programming memory cells in multiple planes. In order to screen for failure of the programming process in a subset of planes, the completion of programming of a fastest plane to a particular data state is used as a trigger to test for program failure of other planes to a different data state. In one embodiment, the test for program failure of other planes to the different data state comprises determining if the memory cells of the other planes that are targeted for programming to the different data state have successfully completed verification of programming for the different data state. The programming process is stopped for those planes that fail the test.
An alternating stack of insulating layers and sacrificial material layers is formed over a substrate, and support pillar structures are formed through the alternating stack. Stepped surfaces are formed by patterning the alternating stack and the support pillar structures. A retro-stepped dielectric material portion is formed over the stepped surfaces. Memory openings and memory opening fill structures are formed through the alternating stack. Electrically conductive layers are formed by replacing at least the sacrificial material layers with at least one electrically conductive material. Contact via structures are formed through the retro-stepped dielectric material portion on the electrically conductive layers. A first support pillar structure is located directly below a first contact via structure.
H01L 27/11553 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
H01L 27/1157 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the memory core region with cell select transistors, e.g. NAND
H01L 27/11524 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the memory core region with cell select transistors, e.g. NAND
H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
47.
NON-VOLATILE MEMORY WITH EFFICIENT WORD LINE HOOK-UP
A three dimensional non-volatile memory structure includes word lines connected to non-volatile memory cells arranged in blocks. A plurality of word line switches are connected to the word lines and one or more sources of voltage. The word line switches are arranged in groups of X word line switches such that each group of X word line switches is positioned in a line under Y blocks of non-volatile memory cells and has a length that is equal to the width of the Y blocks of non-volatile memory cells, where X>Y.
A memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, a memory opening fill structure including a vertical semiconductor channel and a memory film. The memory film includes a tunneling dielectric layer in contact with the vertical semiconductor channel, a first vertical stack of first dielectric oxide material portions located at levels of the insulating layers and including a dielectric oxide material of a first element, and a second vertical stack of second dielectric oxide material portions located at levels of the electrically conductive layers and including a mixed dielectric oxide material that is a dielectric oxide material of the first element and a second element.
H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 27/1157 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the memory core region with cell select transistors, e.g. NAND
H01L 27/11575 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the boundary region between the core and peripheral circuit regions
49.
THREE-DIMENSIONAL MEMORY DEVICE CONTAINING ETCH-STOP STRUCTURES AND SELF-ALIGNED INSULATING SPACERS AND METHOD OF MAKING THE SAME
Contact via openings are formed through a retro-stepped dielectric material portion in a three-dimensional memory device to underlying etch stop structures. The etch stop structures may include a stepped conductive or semiconductor etch stop plate overlying stepped surfaces in the staircase region. The contact via openings are extended through the etch stop structures. Alternatively, electrically conductive layers, including a topmost dummy electrically conductive layer in the staircase region, may be employed as etch stop structures. In this case, the contact via openings can be extended through the electrically conductive layers. Insulating spacers are formed at peripheral regions of the extended contact via openings. Contact via structures surrounded by the insulating spacers are formed in the extended contact via openings to a respective underlying electrically conductive layer.
H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 27/11556 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 27/11575 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the boundary region between the core and peripheral circuit regions
H01L 27/11548 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the boundary region between the core and peripheral circuit regions
H01L 27/1157 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the memory core region with cell select transistors, e.g. NAND
H01L 27/11524 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the memory core region with cell select transistors, e.g. NAND
50.
NON-VOLATILE MEMORY WITH EFFICIENT TESTING DURING ERASE
When erasing multiple sub-blocks of a block, erase verify is performed for memory cells connected to even word lines to generate even results and for memory cells connected to odd word lines to generate odd results. The even results and the odd results are used to determine that the erase verify process successfully completed. For each NAND string of a first sub-block, a last even result for the NAND string is compared to a last odd result for the NAND string. Despite the determination that the first sub-block successfully completed erase verify, the erasing failed for the first sub-block because the number of NAND strings that have the last even result different than the last odd result is greater than a limit. The system determines that one or more additional sub-blocks also failed erasing based on and in response to determining that the first sub-block failed erasing.
A bonded assembly of a primary semiconductor die and a complementary semiconductor die includes first pairs of first primary bonding pads and first complementary bonding pads that are larger in area than the first primary bonding pads, and second pairs of second primary bonding pads and second complementary bonding pads that are smaller in area than the second primary bonding pads.
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 23/528 - Layout of the interconnection structure
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
52.
THREE-DIMENSIONAL MEMORY DEVICE WITH SELF-ALIGNED ETCH STOP RINGS FOR A SOURCE CONTACT LAYER AND METHOD OF MAKING THE SAME
A memory device includes a lower source-level semiconductor layer, a source contact layer, an upper source-level semiconductor layer, and an alternating stack of insulating layers and electrically conductive layers, and a memory opening fill structure vertically extending through the alternating stack and down to an upper portion of the lower source-level semiconductor layer. The memory opening fill structure includes a vertical semiconductor channel, a memory film laterally surrounding the vertical semiconductor channel, and an annular semiconductor cap contacting a bottom surface of the memory film and contacting a top surface segment of the source contact layer. The annular semiconductor cap may be employed as an etch stop structure during a manufacturing process.
H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 27/11556 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 27/11575 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the boundary region between the core and peripheral circuit regions
H01L 27/11548 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the boundary region between the core and peripheral circuit regions
H01L 27/1157 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the memory core region with cell select transistors, e.g. NAND
H01L 27/11524 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the memory core region with cell select transistors, e.g. NAND
53.
NON-VOLATILE MEMORY WITH ZONE BASED PROGRAM SPEED ADJUSTMENT
In order to decrease the width of threshold voltage distributions of programmed memory cells without unreasonably increasing the time needed to complete programming, a non-volatile memory uses a zone based program speed adjustment. The non-volatile memory starts programming a first set of the non-volatile memory cells until a minimum number of memory cells of the first set of non-volatile memory cells reach a first threshold voltage. In response to the minimum number of memory cells reaching the first threshold voltage, the first set of non-volatile memory cells are categorized into zones/groups based on threshold voltage. The speed of programming is then adjusted differently for each zone/group and programming is completed for the first set of non-volatile memory cells.
A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a vertical semiconductor channel, a memory film in contact with the vertical semiconductor channel, and a vertical stack of tubular dielectric spacers laterally surrounding the memory film. The tubular dielectric spacers may include tubular graded silicon oxynitride portions having a composition gradient such that an atomic concentration of nitrogen decreases with a lateral distance from an outer sidewall of the memory film, or may include tubular composite dielectric spacers including a respective tubular silicon oxide spacer and a respective tubular dielectric metal oxide spacer. Each of the electrically conductive layers has a hammerhead-shaped vertical cross-sectional profile.
H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 27/11556 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 27/11524 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the memory core region with cell select transistors, e.g. NAND
H01L 27/1157 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the memory core region with cell select transistors, e.g. NAND
H01L 27/11519 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the top-view layout
H01L 27/11565 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the top-view layout
55.
THREE-DIMENSIONAL MEMORY DEVICE CONTAINING SELF-ALIGNED ISOLATION STRIPS AND METHODS FOR FORMING THE SAME
A semiconductor structure includes an alternating stack of insulating layers and composite layers. Each of the composite layers includes a plurality of electrically conductive word line strips laterally extending along a first horizontal direction and a plurality of dielectric isolation strips laterally extending along the first horizontal direction and interlaced with the plurality of electrically conductive word line strips. Rows of memory openings are arranged along the first horizontal direction. Each row of memory openings vertically extends through each insulating layer within the alternating stack and one electrically conductive strip for each of the composite layers. Rows of memory opening fill structures are located within the rows of memory openings. Each of the memory opening fill structures includes a respective vertical stack of memory elements and a respective vertical semiconductor channel.
H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 27/11575 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the boundary region between the core and peripheral circuit regions
H01L 27/1157 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the memory core region with cell select transistors, e.g. NAND
H01L 27/11565 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the top-view layout
H01L 27/11573 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the peripheral circuit region
56.
FERROELECTRIC DEVICES INCLUDING A SINGLE CRYSTALLINE FERROELECTRIC LAYER AND METHOD OF MAKING THE SAME
A semiconductor structure includes an active region including a source region, a drain region, and a channel region extending between the source region and the drain region, a gate stack, and a gate dielectric layer located between the gate stack and the active region. The gate stack includes an electrically conductive gate electrode and a single crystalline Ill-nitride ferroelectric plate located between the electrically conductive gate electrode and the gate dielectric layer, and an entirety of the single crystalline IIl-nitride ferroelectric plate is single crystalline.
H01L 27/1159 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with the gate electrodes comprising a layer used for its ferroelectric memory properties, e.g. metal-ferroelectric-semiconductor [MFS] or metal-ferroelectric-metal-insulator-semiconductor [MFMIS] characterised by the memory core region
H01L 27/11597 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with the gate electrodes comprising a layer used for its ferroelectric memory properties, e.g. metal-ferroelectric-semiconductor [MFS] or metal-ferroelectric-metal-insulator-semiconductor [MFMIS] characterised by three-dimensional arrangements, e.g. cells on different height levels
H01L 27/11595 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with the gate electrodes comprising a layer used for its ferroelectric memory properties, e.g. metal-ferroelectric-semiconductor [MFS] or metal-ferroelectric-metal-insulator-semiconductor [MFMIS] characterised by the boundary region between core and peripheral circuit regions
H01L 27/11592 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with the gate electrodes comprising a layer used for its ferroelectric memory properties, e.g. metal-ferroelectric-semiconductor [MFS] or metal-ferroelectric-metal-insulator-semiconductor [MFMIS] characterised by the peripheral circuit region
A memory die includes dielectric isolation rails embedded within a substrate semiconductor layer, laterally spaced apart along a first horizontal direction, and each laterally extending along a second horizontal direction that is perpendicular to the first horizontal direction, and alternating stacks of insulating layers and electrically conductive layers located over the substrate semiconductor layer. The alternating stacks are laterally spaced apart along the second horizontal direction by line trenches that laterally extend along the first horizontal direction. Arrays of memory stack structures are provided such that each array of memory stack structures among the arrays of memory stack structures vertically extends through a respective alternating stack. Each of the memory stack structures includes a respective vertical stack of memory elements and a respective vertical semiconductor channel.
A method of depositing a metal includes providing a structure a process chamber, and providing a metal fluoride gas and a growth-suppressant gas into the process chamber to deposit the metal over the structure. The metal may comprise a word line or another conductor of a three-dimensional memory device.
H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
C23C 16/14 - Deposition of only one other metal element
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
C23C 16/02 - Pretreatment of the material to be coated
C23C 16/04 - Coating on selected surface areas, e.g. using masks
H01L 27/11556 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
59.
THREE-DIMENSIONAL MEMORY DEVICE INCLUDING SENSE AMPLIFIERS HAVING A COMMON WIDTH AND SEPARATION
A semiconductor structure includes a memory array including first and second bit lines and a sense amplifier circuit. The sense amplifier circuit includes a first sense amplifier array containing first active sense amplifier transistors that each have an active region having a first width, where the first active sense amplifier transistors are electrically connected to the first bit lines, and a second sense amplifier array including second active sense amplifier transistors that each have the active region having the first width, where the second active sense amplifier transistors are electrically connected to the second bit lines, and dummy active regions which are electrically inactive located between columns of the second active sense amplifier transistors.
H01L 27/11526 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the peripheral circuit region
H01L 27/11573 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the peripheral circuit region
H01L 27/11548 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the boundary region between the core and peripheral circuit regions
H01L 27/11575 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the boundary region between the core and peripheral circuit regions
H01L 27/11556 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
60.
FIELD EFFECT TRANSISTORS HAVING CONCAVE DRAIN EXTENSION REGION AND METHOD OF MAKING THE SAME
A field effect transistor includes a source region embedded in a semiconductor material layer, a drain region embedded in the semiconductor material layer and laterally spaced from the source region by a channel, a gate stack including a gate dielectric and a gate electrode, a shallow trench isolation portion embedded in an upper portion of the semiconductor material layer and contacting the drain region and the gate stack, and a concave drain extension region continuously extending underneath the shallow trench isolation portion from a bottom surface of the gate dielectric to a bottom surface of the drain region.
H01L 27/11526 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the peripheral circuit region
H01L 27/11573 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the peripheral circuit region
H01L 27/11556 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
An integrated memory assembly comprises a control die bonded to a memory die. The memory die includes multiple non-volatile memory structures (e.g., planes, arrays, groups of blocks, etc.), each comprising a stack of alternating conductive and dielectric layers forming staircases at one or more edges of the non-volatile memory structures. The non-volatile memory structures are positioned with gaps between the non-volatile memory structures such that the gaps separate the staircases of adjacent non-volatile memory structures. Metal interlayer segments positioned in the gaps are connected to a top metal layer positioned above non-volatile memory structures and to one or more electrical circuits on the control die via zero, one or more other metal layers/segments.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 27/11573 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the peripheral circuit region
H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices
62.
NON-VOLATILE MEMORY WITH DIFFERENTIAL TEMPERATURE COMPENSATION FOR SUPER PAGE PROGRAMMING
A system has been described that performs differential temperature compensation based on a differential between the temperature at time of programming and temperature at time of reading for a set of data. Differential temperature compensation is useful for bulk programming/reading (e.g., many pages of data) and/or programming/reading super pages of data (multiple pages residing on different memory die).
G11C 7/04 - Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
A system has been described that performs differential temperature compensation based on a differential between the temperature at time of programming and temperature at time of reading for a set of data. Differential temperature compensation is useful for bulk programming/reading (e.g., many pages of data) and/or programming/reading super pages of data (multiple pages residing on different memory die).
G11C 7/04 - Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
A memory system identifies memory cells connected to a common word line that have had their threshold voltage unintentionally drift lower than programmed by determining whether memory cells meet two criteria: (1) the memory cells have threshold voltages within an offset of a read compare voltage of a data state; and (2) adjacent memory cells (connected to word lines that are adjacent to the common word line) are in one or more low data states. For those memory cells meeting the two criteria, the memory system performs some amount of programming on the memory cells to refresh the data stored in those memory cells to be as originally intended.
A three-dimensional memory device containing a plurality of levels of memory elements includes a memory film containing a layer stack that includes a resonant tunneling barrier stack, a semiconductor barrier layer, and a memory material layer located between the resonant tunneling barrier stack and the semiconductor barrier layer, a semiconductor channel, and a control gate electrode.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 43/50 - EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
H01L 29/15 - Structures with periodic or quasi periodic potential variation, e.g. multiple quantum wells, superlattices
66.
NON-VOLATILE MEMORY WITH STAGGERED RAMP DOWN AT THE END OF PRE-CHARGING
In order to inhibit memory cells from programming and mitigate program disturb, the memory pre-charges channels of NAND strings connected to a common set of control lines by applying positive voltages to the control lines and applying voltages to a source line and bit lines connected to the NAND strings. The control lines include word lines and select lines. The word lines include an edge word line. The memory ramps down the positive voltages applied to the control lines, including ramping down control lines on a first side of the edge word line, ramping down the edge word line, and performing a staggered ramp down of three or more control lines on a second side of the edge word line. After the pre-charging, unselected NAND strings have their channel boosted to prevent programming and selected NAND strings experience programming on selected memory cells.
An alternating stack of insulating layers and spacer material layers is formed over a substrate. An insulating cap layer is formed thereupon. A memory opening is formed, which has a greater lateral dimension at a level of an upper insulating cap sublayer than at a level of a lower insulating cap sublayer. A memory film and a semiconductor channel material layer is formed in the memory opening. Ions of at least one dopant species is implanted into a top portion of the semiconductor channel material layer. An isotropic etch process etches an unimplanted portion of the semiconductor channel material layer at a higher etch rate than the implanted top portion of the semiconductor channel material layer to form a vertical semiconductor channel.
H01L 27/11556 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 27/11524 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the memory core region with cell select transistors, e.g. NAND
H01L 27/11575 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the boundary region between the core and peripheral circuit regions
68.
SOFT ERASE PROCESS DURING PROGRAMMING OF NON-VOLATILE MEMORY
Programming a plurality of non-volatile memory cells includes performing a soft erase process during the programming. The soft erase process includes pre-charging channels of the memory cells and performing an erase operation subsequent to the pre-charging while the channels are at one or more elevated voltages at least partially due to the pre-charging.
A CMP system includes a polishing apparatus configured to polish a wafer and roll cleaning apparatus, which includes a rotating roll brush configured to roll against a surface of the wafer during operation, a fluid supply system configured to apply a fluid on the surface of the wafer, and an array of liquid sensors configured to detect a distribution of the fluid on the surface of the wafer in areas that are not covered by the rotating roll brush.
B24B 37/04 - Lapping machines or devices; Accessories designed for working plane surfaces
B24B 57/02 - Devices for feeding, applying, grading or recovering grinding, polishing or lapping agents for feeding of fluid, sprayed, pulverised, or liquefied grinding, polishing or lapping agents
B24B 29/00 - Machines or devices for polishing surfaces on work by means of tools made of soft or flexible material with or without the application of solid or liquid polishing agents
B24B 49/02 - Measuring or gauging equipment for controlling the feed movement of the grinding tool or work; Arrangements of indicating or measuring equipment, e.g. for indicating the start of the grinding operation according to the instantaneous size and required size of the workpiece acted upon, the measuring or gauging being continuous or intermittent
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
70.
THREE-DIMENSIONAL MEMORY DEVICE WITH WORD-LINE ETCH STOP LINERS AND METHOD OF MAKING THEREOF
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures vertically extending through the alternating stack, etch stop plates located in the staircase region, laterally and vertically spaced apart among one another, and overlying an end portion of a respective one of the electrically conductive layers, and contact via structures located in a staircase region, vertically extending through a respective one of the etch stop plates, and contacting a respective one of the electrically conductive layers.
H01L 27/11556 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 27/11524 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the memory core region with cell select transistors, e.g. NAND
H01L 27/11548 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the boundary region between the core and peripheral circuit regions
H01L 27/11519 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the top-view layout
H01L 27/11526 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the peripheral circuit region
71.
HIGH ASPECT RATIO VIA FILL PROCESS EMPLOYING SELECTIVE METAL DEPOSITION AND STRUCTURES FORMED BY THE SAME
A semiconductor structure includes a first dielectric material layer, a first metal interconnect structure embedded within the first dielectric material layer and including a first metallic material portion including a first metal, a second dielectric material layer located over the first dielectric material layer, and a second metal interconnect structure embedded within the second dielectric material layer and including an integrated line-and-via structure that includes a second metallic material portion including a second metal. A metal-semiconductor alloy portion including a first metal-semiconductor alloy of the first metal and a semiconductor material is located underneath the second metallic material portion, and contacts a top surface of the first metal interconnect structure.
H10B 43/50 - EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
H10B 41/50 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
72.
THREE-DIMENSIONAL MEMORY DEVICE WITH ORTHOGONAL MEMORY OPENING AND SUPPORT OPENING ARRAYS AND METHOD OF MAKING THEREOF
An alternating stack of insulating layers and spacer material layers is formed over a substrate. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. Memory openings and support openings are formed through the alternating stack. The memory openings are arranged in a first hexagonal array having a nearest-neighbor direction that is parallel to a first horizontal direction, and the support openings are arranged in a second hexagonal array having a nearest-neighbor direction that is perpendicular to the first horizontal direction. Memory opening fill structures are formed within a respective one of the memory openings, and support pillar structures within a respective one of the support openings.
H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 27/11565 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the top-view layout
H01L 27/1157 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the memory core region with cell select transistors, e.g. NAND
H01L 27/11575 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the boundary region between the core and peripheral circuit regions
73.
NON-VOLATILE MEMORY WITH ADJUSTED BIT LINE VOLTAGE DURING VERIFY
A control circuit connected to non-volatile memory cells applies a programming signal to a plurality of the non-volatile memory cells in order to program the plurality of the non-volatile memory cells to a set of data states. The control circuit performs program verification for the non-volatile memory cells, including applying bit line voltages during program verification based on word line position and data state being verified.
G11C 16/08 - Address circuits; Decoders; Word-line control circuits
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 27/11575 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the boundary region between the core and peripheral circuit regions
74.
THREE-DIMENSIONAL MEMORY DEVICE WITH DISCRETE CHARGE STORAGE ELEMENTS AND METHODS FOR FORMING THE SAME
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, and memory stack structures extending through the alternating stack. Each of the memory stack structures includes a vertical semiconductor channel, a tunneling dielectric layer, a vertical stack of discrete silicon nitride memory elements located at levels of the electrically conductive layers, and a vertical stack of discrete silicon oxide blocking dielectric structures laterally surrounding the vertical stack of discrete silicon nitride memory elements. Each of the silicon oxide blocking dielectric structures includes a silicon oxynitride surface region, and an atomic concentration of nitrogen atoms within the silicon oxynitride surface region decreases with a lateral distance from an interface between the silicon oxynitride surface region and a respective one of the silicon nitride memory elements.
H01L 27/11556 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 27/11524 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the memory core region with cell select transistors, e.g. NAND
H01L 27/1157 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the memory core region with cell select transistors, e.g. NAND
H01L 27/11519 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the top-view layout
H01L 27/11565 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the top-view layout
75.
FIELD EFFECT TRANSISTORS WITH REDUCED GATE FRINGE AREA AND METHOD OF MAKING THE SAME
A semiconductor structure includes at least two field effect transistors. A gate strip including a plurality of gate dielectrics and a gate electrode strip can be formed over a plurality of semiconductor active regions. Deep source/drain regions are formed by implanting dopants into semiconductor active regions without implanting the dopants into inter-electrode regions of a shallow trench isolation structure. The gate strip is divided into gate stacks prior to or after formation of the deep source/drain regions.
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
A three-dimensional memory device includes a first alternating stack of first insulating layers and first electrically conductive layers located over a semiconductor material layer, an inter-tier dielectric layer, and a second alternating stack of second insulating layers and second electrically conductive layers located over the inter-tier dielectric layer. A memory opening vertically extends through the second alternating stack, the inter-tier dielectric layer, and the first alternating stack. A memory opening fill structure is located in the memory opening, and includes a first vertical semiconductor channel, a second vertical semiconductor channel, and an inter-tier doped region located between the first and the second semiconductor channel, and providing a first p-n junction with the first vertical semiconductor channel and providing a second p-n junction with the second vertical semiconductor channel.
H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 27/11568 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the memory core region
H01L 27/11575 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the boundary region between the core and peripheral circuit regions
77.
SEMICONDUCTOR DEVICE CONTAINING BIT LINES SEPARATED BY AIR GAPS AND METHODS FOR FORMING THE SAME
A semiconductor structure includes semiconductor devices located over a substrate, bit lines electrically connected to the semiconductor devices and having a respective reentrant vertical cross-sectional profile within a vertical plane that is perpendicular to a lengthwise direction along which the bit lines laterally extend, and dielectric portions that are interlaced with the bit lines along a horizontal direction that is perpendicular to the lengthwise direction. The dielectric portions may contain air gaps. A bit-line-contact via structure can be formed on top of a bit line. In some embodiments, dielectric cap strips may be located on top surface of the dielectric portions and may cover peripheral regions of the top surfaces of the bit lines without covering middle regions of the top surfaces of the bit lines.
H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 27/11575 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the boundary region between the core and peripheral circuit regions
H01L 27/1157 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the memory core region with cell select transistors, e.g. NAND
H01L 27/11573 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the peripheral circuit region
78.
FIELD EFFECT TRANSISTORS WITH GATE FINS AND METHOD OF MAKING THE SAME
A semiconductor structure includes a semiconductor substrate containing a shallow trench isolation structure that laterally surrounds a transistor active region, at least one line trench vertically extending into the semiconductor substrate, and a source region and a drain region located in the transistor active region. A contoured channel region continuously extends from the source region to the drain region underneath the at least one line trench. A gate dielectric contacts all surfaces of the at least one line trench and extends over an entirety of the contoured channel region. A gate electrode containing at least one fin portion overlies the gate dielectric
H01L 27/108 - Dynamic random access memory structures
H01L 27/105 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
79.
THREE-DIMENSIONAL MEMORY DEVICE WITH REPLACEMENT SELECT GATE ELECTRODES AND METHODS OF MANUFACTURING THE SAME
An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. The sacrificial material layers include a stack of word-line-level sacrificial material layers and at least one drain-select-level sacrificial material layer. Drain-select-level openings are formed through the at least one drain-select-level sacrificial material layer, which is replaced with at least one drain-select-level electrically conductive layer. Memory openings are formed by vertically extending the drain-select-level openings through the word-line-level sacrificial material layers. Memory opening fill structures are formed within the memory openings. The word-line-level sacrificial material layers are replaced with word-line-level electrically conductive layers.
H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 27/11556 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 27/11597 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with the gate electrodes comprising a layer used for its ferroelectric memory properties, e.g. metal-ferroelectric-semiconductor [MFS] or metal-ferroelectric-metal-insulator-semiconductor [MFMIS] characterised by three-dimensional arrangements, e.g. cells on different height levels
H01L 27/11565 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the top-view layout
H01L 27/11519 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the top-view layout
H01L 27/11587 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with the gate electrodes comprising a layer used for its ferroelectric memory properties, e.g. metal-ferroelectric-semiconductor [MFS] or metal-ferroelectric-metal-insulator-semiconductor [MFMIS] characterised by the top-view layout
H01L 27/11575 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the boundary region between the core and peripheral circuit regions
H01L 27/11548 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the boundary region between the core and peripheral circuit regions
80.
NON-VOLATILE MEMORY WITH PROGRAM SKIP FOR EDGE WORD LINE
In a non-volatile memory, a block of NAND strings is divided into sub-blocks by etching the select gate layers between sub-blocks. This results in a subset of NAND strings (e.g., at the border of the sub-blocks) having select gates that are partially etched such that the partially etched select gates are partially shaped as compared to the select gates of NAND strings that have not been etched. Host data is programmed to non-volatile memory cells that are connected to an edge word line and are on NAND strings having a complete shaped select gate. Host data is also programmed to non-volatile memory cells that are connected to non-edge word lines. However, host data is not programmed to non-volatile memory cells that are connected to the edge word line and are on NAND strings having a partial shaped select gate.
H01L 27/11575 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the boundary region between the core and peripheral circuit regions
H01L 27/1157 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the memory core region with cell select transistors, e.g. NAND
H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
Techniques are presented for the application of neural networks to the fabrication of integrated circuits and electronic devices, where example are given for the fabrication of non-volatile memory circuits and the mounting of circuit components on the printed circuit board of a solid state drive (SSD). The techniques include the generation of high precision masks suitable for analyzing electron microscope images of feature of integrated circuits and of handling the training of the neural network when the available training data set is sparse through use of a generative adversary network (GAN).
G05B 19/418 - Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control (DNC), flexible manufacturing systems (FMS), integrated manufacturing systems (IMS), computer integrated manufacturing (CIM)
G05B 13/02 - Adaptive control systems, i.e. systems automatically adjusting themselves to have a performance which is optimum according to some preassigned criterion electric
H01L 21/66 - Testing or measuring during manufacture or treatment
82.
DETECTING BIT LINE OPEN CIRCUITS AND SHORT CIRCUITS IN MEMORY DEVICE WITH MEMORY DIE BONDED TO CONTROL DIE
Apparatuses and techniques are presented for detecting bit line open circuits and short circuits in a memory device in which a memory die is inverted and bonded to a control die. In one approach, the control die comprises a set of bit lines which are connected to a set of bit lines of the memory die, and the set of bit lines of the control die comprise ground transistors, e.g., transistors connected to a ground node. Ground transistors of even-numbered bit lines may be commonly controlled, while ground transistors of odd-numbered bit lines are commonly controlled. The ground transistors may be controlled to detect open circuits and short circuits in the bit lines of the control die and the memory die. A laser scanning technique can also be used to determine a physical location of a defect of a bit line.
G11C 16/26 - Sensing or reading circuits; Data output circuits
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
G11C 29/02 - Detection or location of defective auxiliary circuits, e.g. defective refresh counters
H01L 27/11529 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the peripheral circuit region of memory regions comprising cell select transistors, e.g. NAND
G11C 29/12 - Built-in arrangements for testing, e.g. built-in self testing [BIST]
Apparatuses and techniques are described for programming a multi-tier block in which sub-blocks are arranged in respective tiers. When a program operation involves the source-side sub-block, the NAND strings are pre-charged from the source line. When a program operation involves the drain-side sub-block, the NAND strings are pre-charged from the bit line. When a program operation involves an interior sub-block, the NAND strings can be pre-charged from the bit line if all sub-blocks on the drain side of the interior sub-block are erased, or from the source line if all sub-blocks on the source side of the interior sub-block are erased. A table can be provided which identifies free blocks, free sub-blocks and a corresponding program order. If such a table is not available, the sub-blocks can be read to determine whether they are programmed.
G11C 16/16 - Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
G11C 16/26 - Sensing or reading circuits; Data output circuits
G11C 16/08 - Address circuits; Decoders; Word-line control circuits
H01L 27/11529 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the peripheral circuit region of memory regions comprising cell select transistors, e.g. NAND
84.
THREE-DIMENSIONAL MEMORY DEVICE WITH STAIRCASE ETCH STOP STRUCTURES AND METHODS FOR FORMING THE SAME
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, and memory opening fill structures vertically extending through the alternating stack. An insulating liner overlies stepped surfaces of the alternating stack in a staircase region. A plurality of discrete dielectric plates can be formed over the insulating liner. In one embodiment, the plurality of discrete dielectric plates can function as etch stop structures for formation of contact via structures that contact underlying portions of the electrically conductive layers. In another embodiment, the plurality of discrete dielectric plates may be replaced with a metallic material that forms extensions of the electrically conductive layers, and can be employed as etch stop structures during formation of contact via structures.
H01L 27/11556 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 27/11524 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the memory core region with cell select transistors, e.g. NAND
H01L 27/11519 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the top-view layout
H01L 27/11575 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the boundary region between the core and peripheral circuit regions
85.
MODIFYING PROGRAM AND ERASE PARAMETERS FOR SINGLE-BIT MEMORY CELLS TO IMPROVE SINGLE-BIT/MULTI-BIT HYBRID RATIO
Apparatuses and techniques are described for modifying program and erase parameters in a memory device in which memory cells can be operated in a single bit per cell (SLC) mode or a multiple bits per cell mode. In one approach, the stress on a set of memory cells in an SLC mode is reduced during programming and erasing when the number of program-erase cycles for the block in the SLC mode is below a threshold. For example, during programming, the program-verify voltage and program voltages can be reduced to provide a shallower than normal programming. During erasing, the erase-verify voltage can be increased while the erase voltages can be reduced to provide a shallower than normal erase. When the number of program-erase cycles for the block in the SLC mode is above the threshold, the program and erase parameters revert to a default levels.
G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
Apparatuses and techniques are described for controlling a bit line pre-charge voltage in a program operation based on a number of bits per cell, with a goal to reduce peak current consumption. In one aspect, the ramp up of a bit line voltage to an inhibit level is optimized according to the number of bits per cell. The ramp up can involve increasing the bit line voltage from an initial level to a target voltage at a regulated rate, then increasing the bit line voltage from the target voltage to a final voltage at an unregulated rate. In one approach, the regulated ramp rate is less for single-level cell programming compared to multi-level cell programming. The target voltage can also be optimized based on the number of bis per cell.
H01L 27/11575 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the boundary region between the core and peripheral circuit regions
H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
87.
NON-VOLATILE MEMORY WITH EFFICIENT TESTING DURING ERASE
A non-volatile memory system erasing groups of connected memory cells separately performs erase verify for memory cells connected to even word lines to generate even results and erase verify for memory cells connected to odd word lines to generate odd results. The even results and the odd results are used to determine if the erase verify process indicates that the erasing has successful completed. In addition, for each group of connected memory cells, a last even result for the group is compared to a last odd result for the group. Even if the erase verify indicated that the erasing has successfully completed, the system may determine that the erasing failed (i.e. due to a defect) if the number of groups of connected memory cells that have the last even result different than the last odd result is greater than a limit.
A vertically alternating sequence of continuous insulating layers and continuous sacrificial material layers is formed over a substrate, and memory opening fill structures including vertical stacks of memory elements are formed through the vertically alternating sequence. Backside trenches are formed to divide the vertically alternating sequence into a plurality of alternating stacks of insulating layers and sacrificial material layers. Bridge structures are formed within each of the backside trenches. The sacrificial material layers are replaced with electrically conductive layers while the bridge structure are present within the backside trenches.
H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 27/1157 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the memory core region with cell select transistors, e.g. NAND
H01L 27/11565 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the top-view layout
H01L 27/11575 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the boundary region between the core and peripheral circuit regions
89.
THREE-DIMENSIONAL MEMORY DEVICE INCLUDING ALUMINUM ALLOY WORD LINES AND METHOD OF MAKING THE SAME
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers. The electrically conductive layers include an intermetallic alloy of aluminum and at least one metal other than aluminum. Memory openings vertically extend through the alternating stack. Memory opening fill structures are located in a respective one of the memory openings and include a respective vertical semiconductor channel and a respective vertical stack of memory elements.
H01L 27/11551 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels
H01L 29/80 - Field-effect transistors with field effect produced by a PN or other rectifying junction gate
A memory die includes an alternating stack of insulating layers and electrically conductive layers through which memory opening fill structures vertically extend. The memory die includes at least three memory array regions interlaced with at least two contact regions, or at least three contact regions interlaced with at least two memory array regions in the same memory plane. A logic die including at least two word line driver regions can be bonded to the memory die. The interlacing of the contact regions and the memory array regions can reduce lateral offset of boundaries of the word line driver regions from boundaries of the contact regions.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 43/50 - EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 41/50 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
91.
BONDED ASSEMBLY INCLUDING INTER-DIE VIA STRUCTURES AND METHODS FOR MAKING THE SAME
A bonded assembly includes a first semiconductor die and a second semiconductor die that are bonded to each other by dielectric-to-dielectric bonding. First conductive via structures vertically extend through the second semiconductor die and a respective subset of the first dielectric material layers in the first semiconductor die, and contact a respective first metal interconnect structure in the first semiconductor die. Second conductive via structures vertically extend through a second substrate and a respective subset of the second dielectric material layers in the second semiconductor die, and contacting a respective second metal interconnect structure in the second semiconductor die. Redistribution metal interconnect structures located over a backside surface of the second substrate electrically connect the first conductive via structures and the second conductive via structures, and provide electrical interconnection between the first semiconductor die and the second semiconductor die.
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 23/485 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
92.
THREE-DIMENSIONAL MEMORY DEVICE WITH A COLUMNAR MEMORY OPENING ARRANGEMENT AND METHOD OF MAKING THEREOF
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, a plurality of periodic two-dimensional arrays of memory openings vertically extending through the alternating stack, a plurality of periodic two-dimensional arrays of memory opening fill structures, and bit lines. The bit lines laterally extend along a second horizontal direction. Each periodic two-dimensional array of memory openings includes a plurality of columns of memory openings in which neighboring columns of memory openings are laterally spaced apart along a first horizontal direction with an intercolumnar pitch. Memory openings within each column of memory openings are laterally spaced apart along the second horizontal direction with a nearest-neighbor pitch.
H01L 23/528 - Layout of the interconnection structure
H01L 27/11578 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels
H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 27/11565 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the top-view layout
H01L 23/535 - Arrangements for conducting electric current within the device in operation from one component to another including internal interconnections, e.g. cross-under constructions
93.
THREE DIMENSIONAL MEMORY DEVICE CONTAINING TRUNCATED CHANNELS AND METHOD OF OPERATING THE SAME WITH DIFFERENT ERASE VOLTAGES FOR DIFFERENT BIT LINES
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, first memory opening fill structures extending through the alternating stack and including a respective first vertical semiconductor channel having a tubular section and a semi-tubular section, second memory opening fill structures, first bit lines electrically connected to a respective subset of the first drain regions, second bit lines electrically connected to a respective subset of the second drain regions, and an erase voltage application circuit configured to electrically bias the first bit lines at a first bit line erase voltage and the second bit lines at a second bit line erase voltage during an erase operation. The first bit line erase voltage is greater than the second bit line erase voltage.
H01L 27/11578 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels
G11C 16/14 - Circuits for erasing electrically, e.g. erase voltage switching circuits
H01L 27/1157 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the memory core region with cell select transistors, e.g. NAND
H01L 27/11565 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the top-view layout
H01L 27/11575 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the boundary region between the core and peripheral circuit regions
H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
94.
THREE-DIMENSIONAL MEMORY DEVICE CONTAINING A CAPPED ISOLATION TRENCH FILL STRUCTURE AND METHODS OF MAKING THE SAME
A semiconductor structure includes semiconductor devices located on a top surface of a substrate semiconductor layer, lower-level metal interconnect structures embedded in lower-level dielectric material layers, source-level material layers, an alternating stack of insulating layers and electrically conductive layers overlying the source-level material layer, memory stack structures, a vertically alternating sequence of insulating plates and dielectric material plates laterally surrounded by the alternating stack, an isolation trench fill structure interposed between the alternating stack and the vertically alternating sequence and including a trench fill material portion and a capping dielectric structure overlying the trench fill material portion, and a first through-memory-level interconnection via structure vertically extending through each plate within the vertically alternating sequence and contacting a top surface of one of the lower-level metal interconnect structures.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 27/1157 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the memory core region with cell select transistors, e.g. NAND
H01L 27/11575 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the boundary region between the core and peripheral circuit regions
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
95.
THREE-DIMENSIONAL MEMORY DEVICE INCLUDING AIRGAP CONTAINING INSULATING LAYERS AND METHOD OF MAKING THE SAME
A three-dimensional memory device includes a vertical repetition of multiple instances of a unit layer stack. The unit layer stack includes, in order, an airgap-containing insulating layer, a first interfacial dielectric capping layer, a metal layer, and a second interfacial dielectric capping layer. Memory stack structures extend through the vertical repetition. Each of the memory stack structures includes a vertical semiconductor channel and a vertical stack of memory elements located at levels of the metal layers.
H01L 21/76 - Making of isolation regions between components
H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
96.
NON-VOLATILE MEMORY WITH VARIABLE BITS PER MEMORY CELL
In a three dimensional non-volatile memory structure that etches part of the top of the memory structure (including a portion of the select gates), data is stored on a majority (or all but one) of the word lines as x bits per memory cell while data is stored on a top edge word line that is closest to the etching with variable bits per memory cell. In one example embodiment that implements vertical NAND strings, memory cells connected to the top edge word line and that are on NAND strings adjacent the etching store data as n bits per memory cell and memory cells connected to the top edge word line and that are on NAND strings not adjacent the etching store data as m bits per memory cell, where m>x>n.
A bonded assembly includes a first semiconductor die containing a first substrate, first semiconductor devices, and first bonding pads laterally surrounded by a first pad-level dielectric layer. The first pad-level dielectric layer includes at least one first encapsulated airgap located between neighboring pairs of first bonding pads and encapsulated by a first dielectric fill material of the first pad-level dielectric layer. The bonded assembly includes a second semiconductor die containing a second substrate, second semiconductor devices, and second bonding pads laterally surrounded by a second pad-level dielectric layer. Each of the second bonding pads is bonded to a respective one of the first bonding pads.
A bonded assembly includes a memory die that is bonded to a logic die. The memory die includes a three-dimensional memory array located on a memory-side substrate, memory-side dielectric material layers located on the three-dimensional memory array and embedding memory-side metal interconnect structures and memory-side bonding pads, a backside peripheral circuit located on a backside surface of the memory-side substrate, and backside dielectric material layers located on a backside of the memory-side substrate and embedding backside metal interconnect structures. The logic die includes a logic-side peripheral circuit located on a logic-side substrate, and logic-side dielectric material layers located between the logic-side substrate and the memory die and embedding logic-side metal interconnect structures and logic-side bonding pads that are bonded to a respective one of the memory-side bonding pads.
H01L 27/11526 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the peripheral circuit region
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
99.
HIGH VOLTAGE FIELD EFFECT TRANSISTORS WITH SELF-ALIGNED SILICIDE CONTACTS AND METHODS FOR MAKING THE SAME
A field effect transistor includes a source region and a drain region formed within and/or above openings in a dielectric capping mask layer overlying a semiconductor substrate and a gate electrode. A source-side silicide portion and a drain-side silicide portion are self-aligned to the source region and to the drain region, respectively.
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
100.
THREE-DIMENSIONAL MEMORY DEVICE AND METHOD OF MAKING THEREOF USING DOUBLE PITCH WORD LINE FORMATION
A three-dimensional memory device includes a vertical repetition of multiple instances of a unit layer stack, memory openings vertically extending through the vertical repetition, and memory opening fill structures located within the memory openings. Each of the memory opening fill structures contains a respective vertical stack of memory elements. The unit layer stack includes, from bottom to top or from top to bottom, a cavity-free insulating layer that is free of any cavity therein, a first-type electrically conductive layer, a cavity-containing insulating layer including an encapsulated cavity therein, and a second-type electrically conductive layer.
H01L 21/441 - Deposition of conductive or insulating materials for electrodes
H01L 21/443 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 27/108 - Dynamic random access memory structures
patents
