Sandisk Technologies LLC

United States of America

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IPC Class
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS 1,013
G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention 718
H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels 709
G11C 16/10 - Programming or data input circuits 578
H01L 27/11556 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels 554
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1.

PROGRAMMING TECHNIQUES IN A MEMORY DEVICE TO REDUCE A HYBRID SLC RATIO

      
Application Number 18222735
Status Pending
Filing Date 2023-07-17
First Publication Date 2024-07-18
Owner SanDisk Technologies LLC (USA)
Inventor
  • Xu, Huiwen
  • Dutta, Deepanshu
  • Li, Jia
  • Lei, Bo
  • Oowada, Ken

Abstract

The memory device includes a plurality of hybrid memory blocks that can operate in either a single bit per memory cell mode or a multiple bits per memory cell mode. The memory blocks each include a plurality of memory cells, which are arranged in a plurality of word lines. Control circuitry is configured to program a selected word line to an SLC format. The control circuitry is further configured to determine which zone within the selected hybrid memory block the selected word line is located in and set an SLC programming voltage to a level based on the determination of the zone of the selected word line. The control circuitry is further configured to apply a programming pulse at the SLC programming voltage to the selected word line to program the memory cells of the selected word line.

IPC Classes  ?

  • G11C 16/10 - Programming or data input circuits
  • G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • G11C 16/08 - Address circuits; Decoders; Word-line control circuits

2.

BONDED THREE-DIMENSIONAL MEMORY DEVICE HAVING TEMPORARY ELECTRICAL GROUNDING PATHS IN DUMMY BLOCK AND METHODS OF MAKING THE SAME

      
Application Number 18355765
Status Pending
Filing Date 2023-07-20
First Publication Date 2024-07-18
Owner SANDISK TECHNOLOGIES LLC (USA)
Inventor
  • Moriyama, Takumi
  • Oh, Junji
  • Tsutsumi, Masanori

Abstract

Memory stack structures including electrically floating vertical semiconductor channels can vertically extend through an alternating stack of insulating layers and electrically conductive layers. Metal interconnect structures connected to the electrically floating vertical semiconductor channels can be temporarily electrically grounded by a connection via structure that contacts a semiconducting or conductive carrier substrate, which is subsequently removed. The conductive via structure may be formed through the alternating stack, through a vertical stack of dielectric material plates and the insulating layers, or through a dielectric material portion. The conductive via structure may be connected to at least one bit line. In case the conductive via structure is temporarily connected to a plurality bit lines, the conductive via structure can be subsequently isolated from the bit lines.

IPC Classes  ?

  • H01L 23/528 - Layout of the interconnection structure
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
  • H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
  • H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
  • H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
  • H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region

3.

THREE-DIMENSIONAL MEMORY DEVICE AND METHOD OF MAKING THEREOF INCLUDING NON-CONFORMAL SELECTIVE DEPOSITION OF SPACERS IN MEMORY OPENINGS

      
Application Number 18621735
Status Pending
Filing Date 2024-03-29
First Publication Date 2024-07-18
Owner SANDISK TECHNOLOGIES LLC (USA)
Inventor
  • Sondhi, Kartik
  • Kanakamedala, Senaka

Abstract

A method of forming a memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate, forming a memory opening through the alternating stack, irradiating an upper portion of the memory opening with laser radiation, performing a metal area selective deposition process to selectively grow a vertical stack of tubular metal spacer from physically exposed surfaces of middle and lower sacrificial material layers without growing the tubular metal spacers from upper sacrificial material layers, forming a memory opening fill structure in the memory opening, and replacing the sacrificial material layers with electrically conductive layers.

IPC Classes  ?

  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

4.

THREE-DIMENSIONAL MEMORY DEVICE WITH REDUCED NEIGHBORING WORD LINE INTERFERENCE AND METHODS OF FORMING THE SAME

      
Application Number 18355745
Status Pending
Filing Date 2023-07-20
First Publication Date 2024-07-11
Owner SANDISK TECHNOLOGIES LLC (USA)
Inventor
  • Said, Ramy Nashed Bassely
  • Puthenthermadam, Sarath
  • Yuan, Jiahui
  • Makala, Raghuveer S.
  • Liu, Longju
  • Kanakamedala, Senaka

Abstract

A memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, a memory opening fill structure located in the memory opening and containing a memory film and a vertical semiconductor channel; and a neighboring electrically conductive layer interference reduction feature provided for a first subset of the electrically conductive layers, such that a second subset of the electrically conductive layers lacks the neighboring electrically conductive layer interference reduction feature.

IPC Classes  ?

  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND

5.

THREE-DIMENSIONAL MEMORY DEVICE WITH HYBRID SUPPORT STRUCTURES AND METHODS OF MAKING THE SAME

      
Application Number 18355860
Status Pending
Filing Date 2023-07-20
First Publication Date 2024-07-11
Owner SANDISK TECHNOLOGIES LLC (USA)
Inventor
  • Iwata, Kazuyuki
  • Ikawa, Yusuke
  • Samura, Kei
  • Chen, Zhiwei

Abstract

A three-dimensional memory device includes a first-tier alternating stack of first insulating layers and first electrically conductive layers, a second-tier alternating stack of second insulating layers and second electrically conductive layers overlying the first-tier alternating stack, memory openings vertically extending through the second-tier alternating stack and the first-tier alternating stack, memory opening fill structures located in the memory openings, wherein each of the memory opening fill structures includes a respective vertical stack of memory elements and a respective vertical semiconductor channel including a respective portion of a semiconductor material, and hybrid support structures vertically extending at least through a respective subset of layers within the first-tier alternating stack. Each of the hybrid support structures includes a respective vertical stack of a dielectric support pillar and a composite support pillar having a respective dielectric outer surface and including a respective additional portion of the semiconductor material.

IPC Classes  ?

  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

6.

NON-VOLATILE MEMORY WITH SMART CONTROL OF OVERDRIVE VOLTAGE

      
Application Number 18357274
Status Pending
Filing Date 2023-07-24
First Publication Date 2024-07-11
Owner SanDisk Technologies LLC (USA)
Inventor
  • Song, Yi
  • Yuan, Jiahui
  • Zhu, Xiaochen
  • De La Rama, Lito

Abstract

A non-volatile memory system detects a memory operation failure. In response to the memory operation failure, the system determines whether adjusting an overdrive voltage applied to a word line avoids the memory operation failure. If adjusting the overdrive voltage applied to the word line avoids the memory operation failure, then future memory operations are performed by applying the adjusted overdrive voltage to the word line.

IPC Classes  ?

  • G11C 29/02 - Detection or location of defective auxiliary circuits, e.g. defective refresh counters
  • G11C 29/52 - Protection of memory contents; Detection of errors in memory contents

7.

NON-VOLATILE MEMORY WTH LOOP DEPENDANT RAMP-UP RATE

      
Application Number 18357339
Status Pending
Filing Date 2023-07-24
First Publication Date 2024-07-11
Owner SanDisk Technologies LLC (USA)
Inventor
  • Zainuddin, Abu Naser
  • Yuan, Jiahui
  • Miwa, Toru

Abstract

A non-volatile memory system is configured to program non-volatile memory cells by applying doses of programming to the memory cells and performing a program-verify operation following each dose of programming. Each dose of programming and the corresponding program-verify operation following the dose of programming is referred to as a program loop. The program-verify operation comprises applying a verify reference voltage to a selected word line and applying an overdrive voltage to unselected word lines. To reduce the amount of current used, the memory system includes a loop dependent reduction in the ramp-up rate of the overdrive voltage applied to unselected word lines during program-verify.

IPC Classes  ?

  • G11C 16/10 - Programming or data input circuits
  • G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention

8.

THREE-DIMENSIONAL MEMORY DEVICE AND METHOD OF MAKING THEREOF INCLUDING NON-CONFORMAL SELECTIVE DEPOSITION OF SPACERS IN MEMORY OPENINGS

      
Application Number 18534283
Status Pending
Filing Date 2023-12-08
First Publication Date 2024-07-11
Owner SANDISK TECHNOLOGIES LLC (USA)
Inventor
  • Sondhi, Kartik
  • Tirukkonda, Roshan Jayakhar
  • Zhou, Bing
  • Kanakamedala, Senaka

Abstract

A memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, a memory opening vertically extending through the alternating stack, a memory opening fill structure located in the memory opening and including a vertical stack of memory elements and a vertical semiconductor channel, and a vertical stack of insulating spacers located at levels of the insulating layers between the memory opening fill structure and the insulating layers. The insulating spacers have different thicknesses such that the thicknesses of the insulating spacers increase with an upward vertical distance from a horizontal plane including a top surface of the substrate.

IPC Classes  ?

  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

9.

THREE-DIMENSIONAL MEMORY DEVICE AND METHOD OF MAKING THEREOF USING ETCH STOP STRUCTURES LOCATED BETWEEN TIERS

      
Application Number 18350524
Status Pending
Filing Date 2023-07-11
First Publication Date 2024-07-11
Owner SANDISK TECHNOLOGIES LLC (USA)
Inventor
  • Zhou, Bing
  • Titus, Monica
  • Makala, Raghuveer S.
  • Sharangpani, Rahul
  • Kanakamedala, Senaka

Abstract

A etch stop structure is formed a sacrificial memory opening fill structure formed within a first-tier memory opening vertically extending through a first-tier alternating stack of first insulating layers and first spacer material layers. The etch stop structure may include a conductive etch stop plate that is formed over a sacrificial memory opening fill material portion inside the first-tier memory opening, or may include a semiconductor plug which is selectively grown from sidewalls of an etch stop semiconductor material layer that is formed over the first-tier alternating stack. A second-tier alternating stack of second insulating layers and second spacer material layers is formed over the first-tier alternating stack and the etch stop structure.

IPC Classes  ?

  • H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
  • G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 23/528 - Layout of the interconnection structure
  • H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
  • H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
  • H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

10.

THREE-DIMENSIONAL MEMORY DEVICE AND METHOD OF MAKING THEREOF USING ETCH STOP STRUCTURES LOCATED BETWEEN TIERS

      
Application Number 18350552
Status Pending
Filing Date 2023-07-11
First Publication Date 2024-07-11
Owner SANDISK TECHNOLOGIES LLC (USA)
Inventor
  • Zhou, Bing
  • Titus, Monica
  • Makala, Raghuveer S.
  • Sharangpani, Rahul
  • Kanakamedala, Senaka

Abstract

A etch stop structure is formed a sacrificial memory opening fill structure formed within a first-tier memory opening vertically extending through a first-tier alternating stack of first insulating layers and first spacer material layers. The etch stop structure may include a conductive etch stop plate that is formed over a sacrificial memory opening fill material portion inside the first-tier memory opening, or may include a semiconductor plug which is selectively grown from sidewalls of an etch stop semiconductor material layer that is formed over the first-tier alternating stack. A second-tier alternating stack of second insulating layers and second spacer material layers is formed over the first-tier alternating stack and the etch stop structure.

IPC Classes  ?

  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

11.

THREE-DIMENSIONAL MEMORY DEVICE AND METHOD OF MAKING THEREOF BY NON-CONFORMAL SELECTIVE DEPOSITION OF INSULATING SPACERS IN A MEMORY OPENING

      
Application Number 18355888
Status Pending
Filing Date 2023-07-20
First Publication Date 2024-07-11
Owner SANDISK TECHNOLOGIES LLC (USA)
Inventor
  • Sharangpani, Rahul
  • Makala, Raghuveer S.
  • Rajashekhar, Adarsh
  • Zhou, Fei
  • Zhou, Bing
  • Kanakamedala, Senaka
  • Tirukkonda, Roshan Jayakhar
  • Sondhi, Kartik

Abstract

A method of forming a memory device includes forming an alternating stack of insulating layers including a first insulating material and sacrificial material layers including a first sacrificial material over a substrate, forming a memory opening through the alternating stack, performing a first selective material deposition process that selectively grows a second sacrificial material from physically exposed surfaces of the sacrificial material layers to form a vertical stack of sacrificial material portions; forming a memory opening fill structure in the memory opening, where the memory opening fill structure includes a vertical stack of memory elements and a vertical semiconductor channel, and replacing a combination of the vertical stack of sacrificial material portions and the sacrificial material layers with electrically conductive layers.

IPC Classes  ?

  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 23/528 - Layout of the interconnection structure
  • H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
  • H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
  • H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
  • H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND

12.

NON-VOLATILE MEMORY WITH LOWER CURRENT PROGRAM-VERIFY

      
Application Number 18357489
Status Pending
Filing Date 2023-07-24
First Publication Date 2024-07-11
Owner SanDisk Technologies LLC (USA)
Inventor
  • Zainuddin, Abu Naser
  • Yuan, Jiahui
  • Miwa, Toru

Abstract

A memory system programs memory cells connected to a selected word line by applying doses of programming and performing program-verify between doses. An efficient and low current program-verify operation includes: while scanning the results of a previous program-verify operation, ramp up voltages on the select lines for the next program-verify operation without waiting for the scan to complete and ramp up voltages on unselected word lines for the next program-verify operation following a step signal (so that voltage applied to the unselected word lines rise in steps) without waiting for the scan to complete.

IPC Classes  ?

  • G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
  • G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • G11C 16/08 - Address circuits; Decoders; Word-line control circuits
  • G11C 16/10 - Programming or data input circuits

13.

DYNAMIC CLOCK MASK BASED ON READ DATA FOR POWER SAVING

      
Application Number 18353709
Status Pending
Filing Date 2023-07-17
First Publication Date 2024-07-04
Owner SanDisk Technologies LLC (USA)
Inventor Tang, Tianyu

Abstract

Systems and methods disclosed herein provide for reduced power composition during data read operations from memory devices through gating of clock signals based on a bit pattern of data to be read from the memory device. Example devices and methods disclosed herein comprise receiving a command to read data from a memory structure of the memory device and latching a bit pattern of the data from the memory structure to a data register based on the received command. The disclose systems and methods use the bit pattern to generate a clock mask according to similarities between bit values within the bit pattern. When a read enable signal is detected on a read enable interface of the embodiments disclosed herein, the clock mask is gated based on the clock mask, and bit values are latched to an input/output interface of the memory device in accordance with the gated read enable signal.

IPC Classes  ?

  • G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
  • G11C 7/22 - Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

14.

NONVOLATILE MEMORY WITH ONGOING PROGRAM READ

      
Application Number 18360273
Status Pending
Filing Date 2023-07-27
First Publication Date 2024-07-04
Owner SanDisk Technologies LLC (USA)
Inventor
  • Hsu, Hua-Ling Cynthia
  • Avila, Victor
  • Chin, Henry

Abstract

An apparatus includes control circuits configured to connect to a plurality of non-volatile memory cells. The control circuits are configured to receive a read command directed to at least one logical page of data during a program operation to store the at least one logical page of data in a plurality of non-volatile memory cells. The control circuits are further configured to stop the program operation at an intermediate stage of programming, read the plurality of non-volatile memory cells at the intermediate stage to obtain first partial data of at least one logical page and obtain the at least one logical page of data by combining the first partial data with second partial data of the at least one logical page stored in data latches.

IPC Classes  ?

  • G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers

15.

LOW POWER AND AREA OPTIMIZED TM4 AND TM5 COMPLIANT COMBINATION TMIO TRANSMITTER ARCHITECTURE

      
Application Number 18354211
Status Pending
Filing Date 2023-07-18
First Publication Date 2024-07-04
Owner SanDisk Technologies LLC (USA)
Inventor
  • Patel, Niravkumar Natwarbhai
  • Mathur, Shiv Harit
  • Rathna, Sumanth Reddy

Abstract

The application discloses a system for altering an input/output (I/O) data signal of a NAND programming operation. The system includes a skew-gen circuit comprising: a delay block coupled to an input of a two input logic OR gate, and a MUX logic gate coupled to an output of the logic OR gate. The skew-gen circuit is configured to: alter the pulse width of a input data signal by increasing the width of the data high signal and decreasing the width of the data low signal; and output the altered data signal to the MUX, the MUX configured to select either the altered data signal or the input data signal depending on the mode.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers
  • H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits

16.

AREA-EFFICIENT AND MODERATE CONVERSION TIME ANALOG TO DIGITAL CONVERTER (ADC)

      
Application Number 18354370
Status Pending
Filing Date 2023-07-18
First Publication Date 2024-07-04
Owner SanDisk Technologies LLC (USA)
Inventor
  • Shivasubramaniyarajan, V.M.
  • Addagalla, Aswani Krishna
  • Anantula, Pradeep

Abstract

Systems and methods for converting an input analog signal to a digital representation thereof. A method includes determining an input analog signal voltage range of the input analog signal, and splitting the input analog signal voltage range into n+1 sub-ranges, n being a number of splits in the input analog signal voltage range. The method also includes assigning a respective N-bit coarse digital code i to each sub-range. The method also includes identifying the input analog signal with a corresponding sub-range, the corresponding sub-range having respective digital code i. A delta-sigma operation is performed on the input analog signal using upper and lower reference voltages of the corresponding sub-range that the input analog signal is identified with, to produce the digital representation.

IPC Classes  ?

  • H03M 1/20 - Increasing resolution using an n bit system to obtain n + m bits, e.g. by dithering
  • H03M 1/18 - Automatic control for modifying the range of signals the converter can handle, e.g. gain ranging
  • H03M 7/32 - Conversion to or from delta modulation, i.e. one-bit differential modulation

17.

MULTI-STAGE PROGRAMMING TECHNIQUES WITH THREE STATES PER MEMORY CELL PARITY

      
Application Number 18225248
Status Pending
Filing Date 2023-07-24
First Publication Date 2024-06-27
Owner SanDisk Technologies LLC (USA)
Inventor
  • Prakash, Abhijith
  • Yang, Xiang

Abstract

The memory device includes a memory block with an array of memory cells arranged word lines. The memory device also includes control circuitry that is configured to program final data into a selected word line in a multi-pass programming operation that includes a first pass and a second pass. In the first pass, the control circuitry is configured to program the memory cells of the selected word line to foggy data and program parity data in the memory device. The parity data includes three possible data states. Prior to the second pass, the control circuitry is configured to read the foggy data and the parity data and reconstruct the final data from the foggy data and the parity data. In the second pass, the control circuitry is configured to program the memory cells of the selected word line from the foggy data to the final data.

IPC Classes  ?

  • G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
  • G11C 16/08 - Address circuits; Decoders; Word-line control circuits
  • G11C 16/10 - Programming or data input circuits

18.

THREE-DIMENSIONAL MEMORY DEVICE CONTAINING INTEGRATED CONTACT-AND-SUPPORT ASSEMBLIES AND METHODS OF MAKING THE SAME

      
Application Number 18351828
Status Pending
Filing Date 2023-07-13
First Publication Date 2024-06-27
Owner SANDISK TECHNOLOGIES LLC (USA)
Inventor
  • Miyamoto, Masato
  • Ogawa, Hiroyuki
  • Kubo, Tomohiro

Abstract

A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, memory opening fill structures including a vertical channel and memory elements located in the memory openings, a contact via cavity vertically extending through the alternating stack, and an integrated contact-and-support assembly located in the contact via cavity. The integrated contact-and-support assembly includes a dielectric support pillar and a conductive layer contact via structure electrically contacting a top surface of a first electrically conductive layer of the electrically conductive layers that surrounds the contact via cavity. A dielectric spacer is located in the contact via cavity, covering a sidewall of the first electrically conductive layer in the contact via cavity, and extending above the top surface of the first electrically conductive layer.

IPC Classes  ?

  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • H01L 23/528 - Layout of the interconnection structure
  • H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
  • H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
  • H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND

19.

SELF-ALIGNED LINE-AND-VIA STRUCTURE AND METHOD OF MAKING THE SAME

      
Application Number 18355029
Status Pending
Filing Date 2023-07-19
First Publication Date 2024-06-27
Owner SANDISK TECHNOLOGIES LLC (USA)
Inventor Yamaha, Takashi

Abstract

An integrated line-and-via structure includes a metal line structure including a first metal and having a pair of lengthwise metal line sidewalls that laterally extend along a first horizontal direction, a metallic capping plate including a metallic capping material and overlying the metal line structure and having a pair of lengthwise metal cap sidewalls that are vertically coincident with the pair of lengthwise metal line sidewalls, and a metal via structure including a second metal and having a pair of lengthwise metal via sidewalls that is vertically coincident with the pair of lengthwise metal cap sidewalls and having a lateral extent along the first horizontal direction that is less than a lateral extent of the metal line structure along the first horizontal direction.

IPC Classes  ?

  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

20.

MEMORY DEVICE CONTAINING CONSTRICTED CHANNEL ENDS AND METHODS OF MAKING THE SAME

      
Application Number 18595730
Status Pending
Filing Date 2024-03-05
First Publication Date 2024-06-27
Owner SANDISK TECHNOLOGIES LLC (USA)
Inventor
  • Tanaka, Hiroyuki
  • Tsutsumi, Masanori
  • Sakane, Kento
  • Okina, Teruo

Abstract

A memory die includes an alternating stack of insulating layers and electrically conductive layers, a dielectric spacer layer underlying the alternating stack, memory opening vertically extending through the alternating stack, and through the dielectric spacer layer, a memory opening fill structure located in the memory opening and including a dielectric core, a vertical semiconductor channel having a hollow portion which surrounds the dielectric core and a pillar portion which does not surround the dielectric core, and a memory film, and a source layer located under the dielectric spacer layer and contacting the pillar portion of the vertical semiconductor channel.

IPC Classes  ?

  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
  • H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass

21.

WORD LINE-DEPENDENT WORD LINE AND CHANNEL READ SETUP TIME IN FIRST READ STATE OF NON-VOLATILE MEMORY

      
Application Number 18222708
Status Pending
Filing Date 2023-07-17
First Publication Date 2024-06-27
Owner SanDisk Technologies LLC (USA)
Inventor
  • Moon, Dong-Il
  • Penzo, Erika
  • Chin, Henry

Abstract

A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines and disposed in memory holes each comprising a channel. The memory cells retain a threshold voltage and are operable in one of a first read condition in which a word line voltage of the word lines is discharged and a second read condition in which the word line voltage of the word lines is coupled up to a residual voltage level. A control means is configured to apply a predetermined refresh read voltage to the word lines at predetermined intervals of time during a refresh read operation to maintain the memory cells in the second read condition. The control means also adjusts a read setup time in which the word lines are ramped up and the channel is discharged during a read operation based on occurrences of the refresh read operation.

IPC Classes  ?

  • G11C 11/406 - Management or control of the refreshing or charge-regeneration cycles
  • G11C 11/408 - Address circuits

22.

AREA EFFICIENT LV NMOS TWL CHARGE PUMP

      
Application Number 18353468
Status Pending
Filing Date 2023-07-17
First Publication Date 2024-06-27
Owner SanDisk Technologies LLC (USA)
Inventor
  • Rehani, Ankit
  • G, V.S.N.K. Chaitanya
  • Anantula, Pradeep

Abstract

The application generally discloses systems and methods of generating a voltage waveform having an amplitude three times an input voltage amplitude using a plurality of low voltage (LV) triple well (TWL)N-type field effect devices. The method includes: receiving a first input voltage at a first input of a double switch charge transfer switch (CTS) circuit; applying a 2× kick voltage to a first capacitor coupled to a first portion of the double switch CTS circuit, the first capacitor configured to discharge a kick voltage to a source of a first LV TWL N-type field effect device; and applying a 1× kick voltage to a second capacitor coupled a second portion of the double switch CTS circuit, the second capacitor configured to discharge a kick voltage to a source of a second LV TWL N-type field effect device.

IPC Classes  ?

  • H02M 3/07 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
  • H02M 1/088 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices

23.

THREE-DIMENSIONAL MEMORY DEVICE WITH SELF-ALIGNED MEMORY BLOCK ISOLATION AND METHODS FOR FORMING THE SAME

      
Application Number 18355067
Status Pending
Filing Date 2023-07-19
First Publication Date 2024-06-27
Owner SANDISK TECHNOLOGIES LLC (USA)
Inventor
  • Hosoda, Naohiro
  • Hinoue, Tatsuya

Abstract

A three-dimensional memory device may be formed by forming a vertically alternating sequence of insulating layers and sacrificial material layers over a substrate, forming memory openings, forming sacrificial memory opening fill structures in the memory openings, forming first cavities by removing a first subset of the sacrificial memory opening fill structures, forming laterally-extending cavities by performing an isotropic etch process that laterally recesses the sacrificial material layers, forming electrically conductive layers in the laterally-extending cavities, forming second cavities by removing the second subset of the sacrificial memory opening fill structures, and forming memory opening fill structures in each of the first cavities and the second cavities.

IPC Classes  ?

  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 23/528 - Layout of the interconnection structure
  • H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND

24.

APPARATUS AND METHOD FOR DETECTING NEIGHBOR PLANE ERASE FAILURES

      
Application Number 18355348
Status Pending
Filing Date 2023-07-19
First Publication Date 2024-06-27
Owner SanDisk Technologies LLC (USA)
Inventor
  • Amin, Parth
  • Khandelwal, Anubhav
  • Dutta, Deepanshu

Abstract

An apparatus is provided that includes a control circuit coupled to a plurality of non-volatile memory cells disposed in a plurality of planes. The control circuit is configured to concurrently erase a block of memory cells in each of the plurality of planes, determine that the concurrent erase failed, disconnect a first one of the planes from the plurality of planes to form first remaining planes, and concurrently erase a block of memory cells in each of the first remaining planes.

IPC Classes  ?

  • G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
  • G11C 16/14 - Circuits for erasing electrically, e.g. erase voltage switching circuits

25.

NON-VOLATILE MEMORY WITH ERASE DEPTH DETECTION AND ADAPTIVE ADJUSTMENT TO PROGRAMMING

      
Application Number 18357412
Status Pending
Filing Date 2023-07-24
First Publication Date 2024-06-27
Owner SanDisk Technologies LLC (USA)
Inventor
  • Xu, Huiwen
  • Dutta, Deepanshu
  • Lei, Bo

Abstract

A non-volatile memory system detects an indication of erase depth of a population of memory cells and adjusts the programming process for the memory cells based on the detected erase depth.

IPC Classes  ?

  • G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
  • G11C 16/10 - Programming or data input circuits

26.

NAND PLANE BOUNDARY SHRINK

      
Application Number 18358584
Status Pending
Filing Date 2023-07-25
First Publication Date 2024-06-27
Owner SanDisk Technologies LLC (USA)
Inventor
  • Kwon, Ohwon
  • Mizutani, Yuki
  • Ganguly, Arka
  • Tei, Kou
  • Wu, Yonggang

Abstract

Technology is disclosed herein for a memory device having a narrow gap between planes and a method of shrinking the gap between planes. A first and second adjacent planes each has a word line (WL) hookup region at mid-plane. A dummy array region resides between the two planes. The dummy array region may contain a stack of alternating layers of a first insulating material and a second insulating material. There is a first electrical isolation structure between the dummy array region and a stack in the first plane. There is a second electrical isolation structure between the dummy array region and a stack in a second plane. The electrical isolation structures may be formed in narrow trenches. The combination of the dummy array region and the two electrical isolation structures results in a very short gap between the adjacent planes.

IPC Classes  ?

  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
  • H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region

27.

X-DIRECTION DIVIDED SUB-BLOCK MODE IN NAND

      
Application Number 18358654
Status Pending
Filing Date 2023-07-25
First Publication Date 2024-06-27
Owner SanDisk Technologies LLC (USA)
Inventor
  • Hosoda, Naohiro
  • Ogawa, Hiroyuki

Abstract

A memory system is described having an x-direction (bit line direction) divided sub-block mode. Each block is divided in a y-direction and in the x-direction into a number of groups of contiguous NAND strings that are referred to as XY sub-blocks. The memory system performs a memory operation in parallel in multiple XY sub-blocks in a block while inhibiting the memory operation in the other XY sub-blocks in the block. Each XY sub-block for which the memory operation is performed has its NAND strings connected to a different set of contiguous bit lines. In an aspect the memory operation is a program operation with selected memory cells in each of the multiple XY sub-blocks programmed in parallel while inhibiting programming of all memory cells in all other XY sub-blocks in the block. In one aspect, the memory operation is an erase operation.

IPC Classes  ?

  • G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • G11C 16/10 - Programming or data input circuits
  • G11C 16/16 - Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
  • H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND

28.

TEMPERATURE COMPENSATION FOR PRE-CHARGE SPIKE IN MULTI-PASS PROGRAMMING

      
Application Number 18220707
Status Pending
Filing Date 2023-07-11
First Publication Date 2024-06-20
Owner SanDisk Technologies LLC (USA)
Inventor
  • Guo, Jiacen
  • Yang, Xiang

Abstract

The present disclosure is related to a programming technique for a memory device that includes a plurality of memory cells arranged in a plurality of word lines. An operating temperature of the memory device is determined. A spike pre-charge voltage is selected based on the operating temperature of the memory device. A first word line and a second word line are programmed in a first programming pass of a multi-pass programming operation. After the first programming pass is completed on the first and second word lines, the first word line is further programmed in a second programming pass that includes a plurality of program loops with pre-charge operations. The spike pre-charge voltage is applied to the second word line during each pre-charge operation.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

29.

THREE-DIMENSIONAL NOR ARRAY AND METHOD OF MAKING THE SAME

      
Application Number 18352025
Status Pending
Filing Date 2023-07-13
First Publication Date 2024-06-20
Owner SANDISK TECHNOLOGIES LLC (USA)
Inventor
  • Higashitani, Masaaki
  • Rabkin, Peter
  • Kinoshita, Hiroyuki
  • Shimizu, Satoshi
  • Zhang, Yanli
  • Alsmeier, Johann

Abstract

A semiconductor structure includes a vertical stack of repetition units, where each instance of the repetition unit extends along a first horizontal direction and includes a first electrically conductive strip, a first memory film located over the first electrically conductive strip, discrete semiconductor channels that are laterally spaced apart from each other along the first horizontal direction and located above the first memory film, a second memory film located above the discrete semiconductor channels, a second electrically conductive strip located above the second memory film, and an insulating strip located above the first electrically conductive strip. Source/drain openings are arranged along the first horizontal direction, interlaced with the discrete semiconductor channels, and vertically extending through the vertical stack of repetition units, and source/drain pillar structures are located in respective source/drain openings, and vertically extending through the vertical stack of repetition units.

IPC Classes  ?

  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • G11C 16/10 - Programming or data input circuits
  • G11C 16/14 - Circuits for erasing electrically, e.g. erase voltage switching circuits
  • G11C 16/26 - Sensing or reading circuits; Data output circuits
  • H10B 43/30 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region

30.

IMPLEMENTATION OF DEEP NEURAL NETWORKS FOR TESTING AND QUALITY CONTROL IN THE PRODUCTION OF MEMORY DEVICES

      
Application Number 18586736
Status Pending
Filing Date 2024-02-26
First Publication Date 2024-06-20
Owner SanDisk Technologies LLC (USA)
Inventor
  • Chu, Cheng-Chung
  • George, Janet
  • Linnen, Daniel J.
  • Ghai, Ashish

Abstract

Techniques are presented for the application of neural networks to the fabrication of integrated circuits and electronic devices, where example are given for the fabrication of non-volatile memory circuits and the mounting of circuit components on the printed circuit board of a solid state drive (SSD). The techniques include the generation of high precision masks suitable for analyzing electron microscope images of feature of integrated circuits and of handling the training of the neural network when the available training data set is sparse through use of a generative adversary network (GAN).

IPC Classes  ?

  • G06F 30/398 - Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
  • G06F 119/22 - Yield analysis or yield optimisation
  • G06N 3/04 - Architecture, e.g. interconnection topology
  • G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
  • G06N 3/08 - Learning methods
  • H01L 21/66 - Testing or measuring during manufacture or treatment

31.

CHANNEL PRE-CHARGE PROCESS IN A MEMORY DEVICE

      
Application Number 18221649
Status Pending
Filing Date 2023-07-13
First Publication Date 2024-06-20
Owner SanDisk Technologies LLC (USA)
Inventor
  • Guo, Jiacen
  • Zhang, Peng
  • Yang, Xiang
  • Zhang, Yanli

Abstract

The memory device includes a memory block with memory cells arranged in word lines that are divided into sub-blocks. Control circuitry is configured to program each of the word lines of a selected sub-blocks in a plurality of program loops. During at least one program loop, the control circuitry applies a programming pulse to a selected word line. The control circuitry is also configured to simultaneously apply a verify voltage to the selected word line and a pass voltage to unselected word lines. In a first phase of a multi-phase pre-charge process, the control circuitry reduces the voltages applied to the selected word line and at least one unprogrammed word line to a low voltage. In a second phase that follows the first phase, the control circuitry reduces the voltages applied to all word lines that remained at the pass voltage to the low voltage.

IPC Classes  ?

  • G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
  • G11C 16/08 - Address circuits; Decoders; Word-line control circuits
  • G11C 16/10 - Programming or data input circuits

32.

THREE-DIMENSIONAL NOR ARRAY AND METHOD OF MAKING THE SAME

      
Application Number 18351992
Status Pending
Filing Date 2023-07-13
First Publication Date 2024-06-20
Owner SANDISK TECHNOLOGIES LLC (USA)
Inventor
  • Higashitani, Masaaki
  • Rabkin, Peter
  • Kinoshita, Hiroyuki

Abstract

A semiconductor structure includes a vertical stack of repetition units, where each instance of the repetition unit extends along a first horizontal direction and includes a first electrically conductive strip, a first memory film located over the first electrically conductive strip, discrete semiconductor channels that are laterally spaced apart from each other along the first horizontal direction and located above the first memory film, a second memory film located above the discrete semiconductor channels, a second electrically conductive strip located above the second memory film, and an insulating strip located above the first electrically conductive strip. Source/drain openings are arranged along the first horizontal direction, interlaced with the discrete semiconductor channels, and vertically extending through the vertical stack of repetition units, and source/drain pillar structures are located in respective source/drain openings, and vertically extending through the vertical stack of repetition units.

IPC Classes  ?

  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • G11C 16/10 - Programming or data input circuits
  • G11C 16/14 - Circuits for erasing electrically, e.g. erase voltage switching circuits
  • G11C 16/26 - Sensing or reading circuits; Data output circuits
  • H10B 43/30 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region

33.

THREE-DIMENSIONAL NOR ARRAY AND METHOD OF MAKING THE SAME

      
Application Number 18352012
Status Pending
Filing Date 2023-07-13
First Publication Date 2024-06-20
Owner SANDISK TECHNOLOGIES LLC (USA)
Inventor
  • Shimizu, Satoshi
  • Zhang, Yanli
  • Alsmeier, Johann

Abstract

A semiconductor structure includes a vertical stack of repetition units, where each instance of the repetition unit extends along a first horizontal direction and includes a first electrically conductive strip, a first memory film located over the first electrically conductive strip, discrete semiconductor channels that are laterally spaced apart from each other along the first horizontal direction and located above the first memory film, a second memory film located above the discrete semiconductor channels, a second electrically conductive strip located above the second memory film, and an insulating strip located above the first electrically conductive strip. Source/drain openings are arranged along the first horizontal direction, interlaced with the discrete semiconductor channels, and vertically extending through the vertical stack of repetition units, and source/drain pillar structures are located in respective source/drain openings, and vertically extending through the vertical stack of repetition units.

IPC Classes  ?

  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • G11C 16/10 - Programming or data input circuits
  • G11C 16/14 - Circuits for erasing electrically, e.g. erase voltage switching circuits
  • G11C 16/26 - Sensing or reading circuits; Data output circuits
  • H10B 43/30 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region

34.

APPARATUS AND METHODS FOR SMART VERIFY WITH ADAPTIVE VOLTAGE OFFSET

      
Application Number 18355343
Status Pending
Filing Date 2023-07-19
First Publication Date 2024-06-20
Owner SanDisk Technologies LLC (USA)
Inventor
  • Liu, Longju
  • Puthenthermadam, Sarath
  • Yuan, Jiahui

Abstract

An apparatus is provided that includes a control circuit coupled to a plurality of non-volatile memory cells. The control circuit is configured to perform a program-verify iteration on a first set of the non-volatile memory cells in a plurality of program loops, determine that the first set of the non-volatile memory cells passes verification to a particular programmed state in a first number of program loops, determine a first voltage based on the first number of program loops, add an adaptive voltage offset to the first voltage to obtain a second voltage, and program a second set of the non-volatile memory cells in a plurality of program loops using the second voltage. The adaptive voltage offset varies as a function of temperature.

IPC Classes  ?

  • G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
  • G11C 16/10 - Programming or data input circuits

35.

NON-VOLATILE MEMORY WITH HOLE PRE-CHARGE AND ISOLATED SIGNAL LINES

      
Application Number 18357399
Status Pending
Filing Date 2023-07-24
First Publication Date 2024-06-20
Owner SanDisk Technologies LLC (USA)
Inventor
  • Guo, Jiacen
  • Yang, Xiang
  • Yuan, Jiahui

Abstract

A non-volatile memory system programs memory cells from an erased threshold voltage distribution to programmed threshold voltage distributions by performing hole pre-charging of channels of unselected NAND strings in a selected block of a selected plane including applying a source voltage to a selected signal line of a plurality of signal lines that are isolated from each other. The selected signal line is positioned between the selected block and an unselected block and is connected to a selected source line of a plurality of source lines that are isolated from each other. The selected source line is connected to the selected block. The source voltage is greater in magnitude than any predetermined threshold voltage of the erased threshold voltage distribution. After the pre-charging, the system boosts channels of unselected NAND strings in the selected block and applies a program voltage to selected NAND strings in the selected block.

IPC Classes  ?

  • G11C 16/10 - Programming or data input circuits
  • G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
  • G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention

36.

MULTI-TIER SUB-BLOCK MODE OPERATION

      
Application Number 18220682
Status Pending
Filing Date 2023-07-11
First Publication Date 2024-06-13
Owner SanDisk Technologies LLC (USA)
Inventor
  • Yang, Xiang
  • Cao, Wei
  • Guo, Jiacen

Abstract

A storage device is disclosed herein. The storage device comprises a non-volatile memory, where the non-volatile memory includes a block of 3N wordlines partitioned into a plurality of sub-blocks. The plurality of sub-blocks include an upper sub-block of a first subset of the block of 3N wordlines, a lower sub-block of a second subset of the block of 3N wordlines, and a middle sub-block of a third subset of the block of 3N wordlines. Further, the storage device comprises control circuitry coupled to the block of 3N wordlines and configured to: perform a program operation in a normal order programming sequence on the upper sub-block; perform a program operation in a reverse order programming sequence on the lower sub-block; and perform a program operation in the reverse order programming sequence on the middle sub-block.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

37.

THREE-DIMENSIONAL MEMORY DEVICES WITH LATERAL BLOCK ISOLATION STRUCTURES AND METHODS OF FORMING THE SAME

      
Application Number 18354283
Status Pending
Filing Date 2023-07-18
First Publication Date 2024-06-13
Owner SANDISK TECHNOLOGIES LLC (USA)
Inventor
  • Tobioka, Akihiro
  • Yaegashi, Masahiro
  • Maekura, Takayuki
  • Iwai, Takaaki
  • Ogawa, Hiroyuki

Abstract

A three-dimensional memory device includes alternating stacks of insulating strips and electrically conductive strips, backside trenches located between neighboring pairs of alternating stacks, memory openings vertically extending through the alternating stacks, and memory opening fill structures located within the memory openings. In some embodiments, dielectric etch stop structures may be located within or outside the backside trenches such that each of the dielectric etch stop structures includes a respective pair of dielectric sidewalls that are located within a pair of lengthwise sidewalls of the respective one of the backside trenches. In some other embodiments, a dielectric isolation structure can laterally contact each of the insulating strips within the alternating stacks. Laterally insulated contact via structures can be provided to provide electrical contact to a respective one of the electrically conductive strips.

IPC Classes  ?

  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
  • H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass

38.

MEMORY PROGRAM-VERIFY WITH ADAPTIVE SENSE TIME BASED ON ROW LOCATION

      
Application Number 18360306
Status Pending
Filing Date 2023-07-27
First Publication Date 2024-06-13
Owner SanDisk Technologies LLC (USA)
Inventor
  • Guo, Jiacen
  • Yang, Xiang
  • Song, Yi
  • Yuan, Jiahui

Abstract

Technology is disclosed herein for a memory system that includes control circuits that are configured to connect to a three-dimensional memory structure. The memory structure includes NAND strings arranged in a plurality of rows, a plurality of bit lines connected to the NAND strings and a plurality of word lines, each word line coupled to the plurality of rows of NAND strings. The control circuits are configured to, in a program-verify operation, sense memory cells of a first row of NAND strings coupled to the selected word line for a first sense time and sense memory cells of a second row of NAND strings coupled to the selected word line for a second sense time while applying a program-verify voltage to the selected word line.

IPC Classes  ?

  • G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
  • G11C 16/08 - Address circuits; Decoders; Word-line control circuits
  • G11C 16/26 - Sensing or reading circuits; Data output circuits

39.

MEMORY PROGRAM-VERIFY WITH ADAPTIVE SENSE TIME BASED ON DISTANCE FROM A WORD LINE DRIVER

      
Application Number 18360327
Status Pending
Filing Date 2023-07-27
First Publication Date 2024-06-13
Owner SanDisk Technologies LLC (USA)
Inventor
  • Guo, Jiacen
  • Yang, Xiang

Abstract

Technology is disclosed herein for a memory system that includes one or more control circuits configured to connect to a three-dimensional memory structure that includes word lines, with each word line connected to a word line driver at one end. The one or more control circuits are configured to, in a program verify operation, sense memory cells of a first region of a selected word line for a first sense time and sense memory cells of a second region of the selected word line for a second sense time while applying a program-verify voltage to the selected word line. The first region is closer to the word line driver than the second region.

IPC Classes  ?

  • G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
  • G11C 16/08 - Address circuits; Decoders; Word-line control circuits
  • G11C 16/26 - Sensing or reading circuits; Data output circuits

40.

THREE-DIMENSIONAL MEMORY DEVICES WITH LATERAL BLOCK ISOLATION STRUCTURES AND METHODS OF FORMING THE SAME

      
Application Number 18433918
Status Pending
Filing Date 2024-02-06
First Publication Date 2024-06-13
Owner SANDISK TECHNOLOGIES LLC (USA)
Inventor Tobioka, Akihiro

Abstract

A memory device includes an alternating stack of insulating layers and composite layers that alternate along a vertical direction, where each of the composite layers includes a combination of a dielectric connection plate and a plurality of electrically conductive strips that are laterally spaced apart by backside trench isolation structures, arrays of memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings, and dielectric isolation structures adjoined to an end portion of a respective one of the backside trench fill structures.

IPC Classes  ?

  • G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 23/528 - Layout of the interconnection structure
  • H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
  • H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
  • H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND

41.

THREE-DIMENSIONAL MEMORY DEVICES WITH LATERAL BLOCK ISOLATION STRUCTURES AND METHODS OF FORMING THE SAME

      
Application Number 18493020
Status Pending
Filing Date 2023-10-24
First Publication Date 2024-06-13
Owner SANDISK TECHNOLOGIES LLC (USA)
Inventor
  • Kubo, Tomohiro
  • Tobioka, Akihiro

Abstract

A memory device includes an alternating stack of insulating layers and composite layers that alternate along a vertical direction, arrays of memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings, and including a vertical semiconductor channel and a respective vertical stack of memory elements, and dielectric isolation structures laterally contacting each of the insulating layers and each of the composite layers. Each of the composite layers includes a combination of a dielectric connection plate and a plurality of electrically conductive layers that laterally extend along a first horizontal direction and that are laterally spaced apart along a second horizontal direction by backside trenches that laterally extend along the first horizontal direction.

IPC Classes  ?

  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
  • H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass

42.

THREE-DIMENSIONAL MEMORY DEVICE INCLUDING COMPOSITE BACKSIDE METAL FILL STRUCTURES AND METHODS FOR FORMING THE SAME

      
Application Number 18581037
Status Pending
Filing Date 2024-02-19
First Publication Date 2024-06-13
Owner SANDISK TECHNOLOGIES LLC (USA)
Inventor
  • Kambayashi, Ryo
  • Ohsawa, Kazuto

Abstract

A three dimensional memory device includes: an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings, and a backside trench fill structure that includes a backside trench insulating spacer and a backside contact via structure. The backside contact via structure includes a first metallic nitride liner including a nitride of a first metal, a first metal core fill conductive material portion include a second metal, and a second metallic nitride liner including a nitride of the second metal located between an inner sidewall of the first metallic nitride liner and an outer sidewall of the first metal core fill conductive material portion.

IPC Classes  ?

  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

43.

THREE-DIMENSIONAL MEMORY DEVICE WITH DIELECTRIC FINS IN STAIRCASE REGION AND METHODS OF MAKING THEREOF

      
Application Number 18350595
Status Pending
Filing Date 2023-07-11
First Publication Date 2024-06-13
Owner SANDISK TECHNOLOGIES LLC (USA)
Inventor
  • Ehara, Ryoichi
  • Sugiura, Kenji
  • Okamoto, Katsufumi
  • Tanaka, Yudai
  • Funayama, Kota

Abstract

A memory device is formed by forming an alternating stack of insulating layers and sacrificial material layers over a substrate, forming memory openings through the alternating stack, forming memory opening fill structures in the memory openings, forming an access trench through a portion of the alternating stack forming an access trench fill structure in the access cavity, and iteratively performing multiple instances of a unit processing sequence. Each instance of the unit processing sequence includes a vertical recess etch step that vertically recesses the access trench fill structure and an isotropic etch step that isotropically recesses the sacrificial material layers. A finned access cavity is formed after the multiple instances of the unit processing sequence. A finned dielectric support structure is formed in the finned access cavity, and the sacrificial material layers are replaced with electrically conductive layers.

IPC Classes  ?

  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

44.

THREE-DIMENSIONAL MEMORY DEVICE INCLUDING CAPPED HOLLOW TUBE-SHAPED DRAIN REGIONS AND METHODS OF MAKING THE SAME

      
Application Number 18351235
Status Pending
Filing Date 2023-07-12
First Publication Date 2024-06-13
Owner SANDISK TECHNOLOGIES LLC (USA)
Inventor Yamamoto, Keita

Abstract

A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a memory film, a vertical semiconductor channel, a dielectric core laterally surrounded by the vertical semiconductor channel, and a drain region overlying the dielectric core and the vertical semiconductor channel. The drain region includes an end cap portion and a hollow tubular portion vertically protruding downward from the end cap portion and laterally surrounding a top tip portion of the dielectric core.

IPC Classes  ?

  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 23/528 - Layout of the interconnection structure
  • H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
  • H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
  • H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
  • H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND

45.

THREE-DIMENSIONAL MEMORY DEVICES WITH LATERAL BLOCK ISOLATION STRUCTURES AND METHODS OF FORMING THE SAME

      
Application Number 18354325
Status Pending
Filing Date 2023-07-18
First Publication Date 2024-06-13
Owner SANDISK TECHNOLOGIES LLC (USA)
Inventor
  • Maekura, Takayuki
  • Iwai, Takaaki
  • Ogawa, Hiroyuki

Abstract

A three-dimensional memory device includes alternating stacks of insulating strips and electrically conductive strips, backside trenches located between neighboring pairs of alternating stacks, memory openings vertically extending through the alternating stacks, and memory opening fill structures located within the memory openings. In some embodiments, dielectric etch stop structures may be located within or outside the backside trenches such that each of the dielectric etch stop structures includes a respective pair of dielectric sidewalls that are located within a pair of lengthwise sidewalls of the respective one of the backside trenches. In some other embodiments, a dielectric isolation structure can laterally contact each of the insulating strips within the alternating stacks. Laterally insulated contact via structures can be provided to provide electrical contact to a respective one of the electrically conductive strips.

IPC Classes  ?

  • G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 23/528 - Layout of the interconnection structure
  • H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
  • H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
  • H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND

46.

BITLINE TIMING-BASED MULTI-STATE PROGRAMMING IN NON-VOLATILE MEMORY STRUCTURES

      
Application Number 18220387
Status Pending
Filing Date 2023-07-11
First Publication Date 2024-06-06
Owner SanDisk Technologies LLC (USA)
Inventor
  • Wang, Ming
  • Li, Liang

Abstract

A method for multi-state programming of a non-volatile memory structure, comprising: (1) initiating a programming operation with respect to multiple program states, (2) applying, to all selected word lines of the memory structure, a programming voltage bias (VPGM) level pre-determined to be suitable for programming a highest program state of the multiple program states, wherein the programming voltage bias level is applied according to a given program pulse width, and (3) with respect to each program state other than the highest program state of the multiple program states, applying a zero-volt bitline voltage bias (VBL) to one or more bitlines that are associated with one or more memory elements to be programmed to the program state, wherein the zero-volt bitline voltage bias is applied according to a respective program sub-pulse width that is less than the given program pulse width.

IPC Classes  ?

  • G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
  • G11C 7/12 - Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
  • G11C 8/08 - Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

47.

LOSSLESS, AREA-EFFICIENT ERROR DETECTION SCHEME FOR FLASH MEMORY

      
Application Number 18350350
Status Pending
Filing Date 2023-07-11
First Publication Date 2024-06-06
Owner SANDISK TECHNOLOGIES LLC (USA)
Inventor
  • Mittal, Sajal
  • Darne, Siddhesh

Abstract

A circuit for detecting an error in a byte of data transmitted over a channel includes a controller having a first DBI encoder configured to perform a first DBI encoding on a received byte of data. The circuit also includes a channel configured to receive the encoded byte from the controller. The circuit also includes a non-volatile memory having a second DBI encoder and configured to (1) perform a second DBI encoding on the encoded byte received over the channel, (2) check a DBI flag for the byte after the second DBI encoding, and (3) determine that the byte of data contains an error when the DBI flag after the second DBI encoding is 1. If the byte contains an error then it can be concluded that the channel contains a defect. In case of an error a write operation to memory core can be stopped.

IPC Classes  ?

  • G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens

48.

FAST REFERENCE VOLTAGE TRAINING FOR I/O INTERFACE

      
Application Number 18353294
Status Pending
Filing Date 2023-07-17
First Publication Date 2024-06-06
Owner SanDisk Technologies LLC (USA)
Inventor Tang, Tianyu

Abstract

Systems and methods disclosed herein provide for fast write training that be performed to identify an optimal reference voltage for distinguishing between logic levels of an input signal. An example of the systems and methods disclosed herein include receiving a clock signal at an input-output pad of a receiving device and detecting a voltage level of the clock signal based on a duty cycle and voltage swing of the clock signal. A voltage generator circuit is trained to generate a calibrated reference voltage according to the detected voltage level, and the calibrated reference voltage is supplied to an input receiver of the receiving device from the voltage generator circuit.

IPC Classes  ?

  • G11C 7/14 - Dummy cell management; Sense reference voltage generators
  • G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
  • G11C 7/22 - Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

49.

THREE-DIMENSIONAL MEMORY DEVICE WITH WORD LINE SIDE-CONTACT VIA STRUCTURES AND METHODS FOR FORMING THE SAME

      
Application Number 18353577
Status Pending
Filing Date 2023-07-17
First Publication Date 2024-06-06
Owner SANDISK TECHNOLOGIES LLC (USA)
Inventor Tsutsumi, Masanori

Abstract

A memory device includes at least one alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through each layer within the at least one alternating stack, memory opening fill structures located in the memory openings and containing a respective vertical semiconductor channel and a respective vertical stack of memory elements, and an electrically conductive side-contact via structure vertically extending through each layer within the at least one alternating stack and contacting a sidewall of one of the electrically conductive layers.

IPC Classes  ?

  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 23/528 - Layout of the interconnection structure
  • H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
  • H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
  • H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
  • H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
  • H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region

50.

HYBRID TRIPLE LEVEL CELL PROGRAMMING ALGORITHM FOR ON PITCH SCALING IN BIT COST SCALABLE MEMORY APPARATUSES AND SUB-BLOCK MODE

      
Application Number 18224477
Status Pending
Filing Date 2023-07-20
First Publication Date 2024-06-06
Owner SanDisk Technologies LLC (USA)
Inventor
  • Cao, Wei
  • Yang, Xiang

Abstract

A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to one of a plurality of word lines and disposed in memory holes. The memory cells are configured to retain a threshold voltage corresponding to one of a plurality of data states. A control means is coupled to the plurality of word lines and the memory holes and is configured to identify at least one grouping of the memory cells to be programmed with a multi-pass programming operation. The control means is also configured to program the at least one grouping of the memory cells using the multi-pass programming operation. The control means is additionally configured to program the memory cells other than the at least one grouping of the memory cells in a full sequence programming operation.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

51.

FAST SELF-REFERENCED READ OF PROGRAMMABLE RESISTANCE MEMORY CELLS

      
Application Number 18356814
Status Pending
Filing Date 2023-07-21
First Publication Date 2024-06-06
Owner SanDisk Technologies LLC (USA)
Inventor
  • Houssameddine, Dimitri
  • Tran, Michael Nicolas Albert
  • Parkinson, Ward
  • Grobis, Michael

Abstract

Technology is disclosed herein for reading programmable resistance memory cells. A first (faster) self-referenced read (SRR) of a group of memory cells is performed and if successful the read is complete. However, if the first SRR fails then a second (slower or nominal) SRR is performed. The bit error rate (BER) of the second SRR may be significantly lower than the BER of the first SRR. However, the BER of the first SRR may be low enough such that most of the time the first SRR is successful. Therefore, most of the time the read is completed with just the first SRR, thereby providing for an SRR having on average is faster than if just the second SRR had been used. Moreover, the effective BER of the SRR is extremely low due to the low BER of the second SRR.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

52.

THREE-DIMENSIONAL MEMORY DEVICE WITH SELF-ALIGNED WORD LINE CONTACT VIA STRUCTURES AND METHOD OF MAKING THE SAME

      
Application Number 18221689
Status Pending
Filing Date 2023-07-13
First Publication Date 2024-05-30
Owner SANDISK TECHNOLOGIES LLC (USA)
Inventor
  • Matsuno, Koichi
  • Funayama, Kota

Abstract

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers having stepped surfaces in a contact region, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings, at least one retro-stepped dielectric material portion overlying the alternating stack, finned dielectric pillar structures vertically extending through the alternating stack in the contact region, support pillar structures, and layer contact via structures vertically extending through the at least one retro-stepped dielectric material portion. Each of the layer contact via structures contacts a respective one of the electrically conductive layers and a respective one of the finned dielectric pillar structures.

IPC Classes  ?

  • H01L 23/528 - Layout of the interconnection structure
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND

53.

STAIRLESS THREE-DIMENSIONAL MEMORY DEVICE CONTAINING MEANDERING DIELECTRIC ISOLATION STRUCTURE AND METHODS OF FORMING THE SAME

      
Application Number 18240560
Status Pending
Filing Date 2023-08-31
First Publication Date 2024-05-30
Owner SANDISK TECHNOLOGIES LLC (USA)
Inventor
  • Kubo, Tomohiro
  • Maekura, Takayuki

Abstract

A method includes forming an in-process alternating stack of insulating layers and sacrificial material layers, forming a meandering dielectric isolation structure through the in-process alternating stack, forming memory stack structures through the alternating stack, where each of the memory stack structures includes a respective vertical stack of memory elements and a vertical semiconductor channel, forming sacrificial via fill structures on the respective sacrificial material layers, replacing first portions of the sacrificial material layers with electrically conductive layers, and forming layer contact via structures contacting a respective one of the electrically conductive layers by replacing at least the sacrificial via fill structures with a conductive material portion.

IPC Classes  ?

  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 23/528 - Layout of the interconnection structure
  • H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
  • H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
  • H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
  • H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND

54.

STAIRLESS THREE-DIMENSIONAL MEMORY DEVICE AND METHOD OF MAKING THEREOF BY FORMING REPLACEMENT WORD LINES THROUGH MEMORY OPENINGS

      
Application Number 18352752
Status Pending
Filing Date 2023-07-14
First Publication Date 2024-05-30
Owner SANDISK TECHNOLOGIES LLC (USA)
Inventor
  • Hosoda, Naohiro
  • Isozumi, Kazuki
  • Maekura, Takayuki
  • Ogawa, Hiroyuki
  • Matsuno, Koichi

Abstract

A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, and memory opening fill structures located in the memory openings and including a respective vertical semiconductor channel and a respective vertical stack of memory cells. An integrated line-and-via structure is provided, which is a unitary structure including a metallic plate portion that is a portion of or laterally contacts an electrically conductive layer, and a metallic via portion that vertically extends through dielectric material plates that overlie the metallic plate portion.

IPC Classes  ?

  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

55.

THREE-DIMENSIONAL MEMORY DEVICE INCLUDING A MID-STACK SOURCE LAYER AND METHODS FOR FORMING THE SAME

      
Application Number 18353621
Status Pending
Filing Date 2023-07-17
First Publication Date 2024-05-30
Owner SANDISK TECHNOLOGIES LLC (USA)
Inventor
  • Hosoda, Naohiro
  • Isozumi, Kazuki
  • Tsutsumi, Masanori

Abstract

A memory device includes a first-tier alternating stack of first insulating layers and first electrically conductive layers, a source layer overlying the first-tier alternating stack, a second-tier alternating stack of second insulating layers and second electrically conductive layers overlying the source layer, a memory opening vertically extending through the first-tier alternating stack, the source layer, and the second-tier alternating stack, and a memory opening fill structure located in the memory opening. The memory opening fill structure includes a vertical semiconductor channel that extends through the first-tier alternating stack, the source layer, and the second-tier alternating stack. The vertical semiconductor channel has sidewall in contact with the source layer.

IPC Classes  ?

  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
  • H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
  • H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
  • H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass

56.

STAIRLESS THREE-DIMENSIONAL MEMORY DEVICE AND METHOD OF MAKING THE SAME BY FORMING REPLACEMENT WORD LINES

      
Application Number 18354246
Status Pending
Filing Date 2023-07-18
First Publication Date 2024-05-30
Owner SANDISK TECHNOLOGIES LLC (USA)
Inventor
  • Tobioka, Akihiro
  • Maekura, Takayuki

Abstract

An alternating stack of insulating layers and sacrificial material layers is formed over a substrate, memory openings are formed through the alternating stack, and memory opening fill structures including a respective vertical stack of memory elements are formed in the memory openings. The sacrificial material layers are replaced with electrically conductive layers. Electrical contacts to the electrically conductive layers may be provided by forming integrated layer-and-via structures that simultaneously forms metallic via portions as an integral portion of a continuous electrically conductive structure that includes a respective electrically conductive layer. Alternatively, electrical contacts to the electrically conductive layers may be provided by forming integrated line-and-via structures that includes a metallic plate portion contacting a respective electrically conductive layer and a metallic via portion.

IPC Classes  ?

  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

57.

ADAPTIVE ERASE VOLTAGES FOR NON-VOLATILE MEMORY

      
Application Number 18355339
Status Pending
Filing Date 2023-07-19
First Publication Date 2024-05-30
Owner SanDisk Technologies LLC (USA)
Inventor
  • Song, Yi
  • Yuan, Jiahui
  • Wang, Yanjie

Abstract

An apparatus is provided that includes a block of memory cells, and a control circuit coupled to the block of memory cells. The control circuit is configured to perform an erase operation on the block of memory cells by determining a count of a number of times that the block of memory cells previously has been programmed and erased, determining an erase voltage based on the count, and applying an erase pulse having the erase voltage to the block of memory cells.

IPC Classes  ?

  • G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
  • G11C 16/14 - Circuits for erasing electrically, e.g. erase voltage switching circuits

58.

NON-VOLATILE MEMORY WITH ADAPTIVE DUMMY WORD LINE BIAS

      
Application Number 18357436
Status Pending
Filing Date 2023-07-24
First Publication Date 2024-05-30
Owner SanDisk Technologies LLC (USA)
Inventor
  • Liu, Yihang
  • Zhu, Xiaochen
  • Wang, Peng
  • Liu, Jie
  • De La Rama, Lito
  • Gao, Feng
  • Yang, Xiaoyu

Abstract

A non-volatile storage apparatus includes non-volatile memory cells, word lines connected to the non-volatile memory cells, and a control circuit connected to the word lines and the memory cells. The word lines include data word lines and dummy word lines. Memory cells connected to data word lines are configured to store host data. Memory cells connected to dummy word lines do not store host data. The control circuit is configured to erase, program and read the memory cells. Errors from threshold voltage up-shifting in the memory cells connected to dummy word lines is prevented by adjusting the voltage applied to dummy word lines.

IPC Classes  ?

  • G11C 16/12 - Programming voltage switching circuits
  • G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • G11C 16/08 - Address circuits; Decoders; Word-line control circuits
  • G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention

59.

THREE-DIMENSIONAL MEMORY DEVICE WITH SELF-ALIGNED WORD LINE CONTACT VIA STRUCTURES AND METHOD OF MAKING THE SAME

      
Application Number 18221711
Status Pending
Filing Date 2023-07-13
First Publication Date 2024-05-30
Owner SANDISK TECHNOLOGIES LLC (USA)
Inventor
  • Matsuno, Koichi
  • Funayama, Kota

Abstract

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers having stepped surfaces in a contact region, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings, at least one retro-stepped dielectric material portion overlying the alternating stack, finned dielectric pillar structures vertically extending through the alternating stack in the contact region, support pillar structures, and layer contact via structures vertically extending through the at least one retro-stepped dielectric material portion. Each of the layer contact via structures contacts a respective one of the electrically conductive layers and a respective one of the finned dielectric pillar structures.

IPC Classes  ?

  • H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 23/528 - Layout of the interconnection structure
  • H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

60.

STAIRLESS THREE-DIMENSIONAL MEMORY DEVICE AND METHOD OF MAKING THEREOF BY FORMING REPLACEMENT WORD LINES THROUGH MEMORY OPENINGS

      
Application Number 18349578
Status Pending
Filing Date 2023-07-10
First Publication Date 2024-05-30
Owner SANDISK TECHNOLOGIES LLC (USA)
Inventor
  • Maekura, Takayuki
  • Iwai, Takaaki
  • Izumi, Keisuke

Abstract

A memory device includes an alternating stack of insulating layers and composite layers, where each of the composite layers contains an electrically conductive layer and a dielectric material plate, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings, where each of the memory opening fill structures includes a respective vertical stack of memory elements and a vertical semiconductor channel and a plurality of integrated line-and-via structures. Each of the plurality of integrated line-and-via structures includes a conductive plate portion that contacts the electrically conductive layer of a respective one of the composite layers, and a conductive via portion that is adjoined to a top surface of the conductive plate portion and vertically extends through a respective overlying subset of the insulating layers and a subset of the dielectric material plates of the composite layers.

IPC Classes  ?

  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • H01L 23/528 - Layout of the interconnection structure
  • H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
  • H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
  • H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND

61.

THREE-DIMENSIONAL MEMORY DEVICE CONTAINING ENGINEERED CHARGE STORAGE ELEMENTS AND METHODS FOR FORMING THE SAME

      
Application Number 18351205
Status Pending
Filing Date 2023-07-12
First Publication Date 2024-05-30
Owner SANDISK TECHNOLOGIES LLC (USA)
Inventor
  • Sharangpani, Rahul
  • Makala, Raghuveer S.
  • Rajashekhar, Adarsh
  • Zhou, Fei

Abstract

A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and containing a vertical semiconductor channel and a memory film. The memory film includes a tunneling dielectric layer, a continuous charge storage material layer vertically extending through a plurality of the electrically conductive layers, a vertical stack of discrete charge storage elements located at levels of the electrically conductive layers and contacting a respective surface segment of an outer sidewall of the continuous charge storage material layer, and a vertical stack of discrete blocking dielectric material portions containing silicon atoms and oxygen atoms and located at the levels of the electrically conductive layers and vertically spaced apart from each other.

IPC Classes  ?

  • H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 23/528 - Layout of the interconnection structure
  • H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
  • H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
  • H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND

62.

STAIRLESS THREE-DIMENSIONAL MEMORY DEVICE AND METHOD OF MAKING THEREOF BY FORMING REPLACEMENT WORD LINES THROUGH MEMORY OPENINGS

      
Application Number 18352726
Status Pending
Filing Date 2023-07-14
First Publication Date 2024-05-30
Owner SANDISK TECHNOLOGIES LLC (USA)
Inventor
  • Maekura, Takayuki
  • Iwai, Takaaki
  • Ogawa, Hiroyuki
  • Matsuno, Koichi

Abstract

A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, and memory opening fill structures located in the memory openings and including a respective vertical semiconductor channel and a respective vertical stack of memory cells. An integrated line-and-via structure is provided, which is a unitary structure including a metallic plate portion that is a portion of or laterally contacts an electrically conductive layer, and a metallic via portion that vertically extends through dielectric material plates that overlie the metallic plate portion.

IPC Classes  ?

  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout

63.

THREE-DIMENSIONAL MEMORY DEVICE CONTAINING ETCH STOP STRUCTURES FOR WORD LINE CONTACTS AND METHODS OF EMPLOYING THE SAME

      
Application Number 18353546
Status Pending
Filing Date 2023-07-17
First Publication Date 2024-05-30
Owner SANDISK TECHNOLOGIES LLC (USA)
Inventor
  • Tokita, Hirofumi
  • Sai, Akihisa
  • Miyamoto, Masato

Abstract

A method of making a semiconductor structure includes forming an alternating stack of insulating layers and sacrificial material layers, forming initial vertical stacks of at least one initial insulating plate and at least one initial dielectric material plate, and performing a plurality of pattern transfer process sequences that transfers the pattern of the initial vertical stacks by different numbers of underlying layers to form final vertical stacks of at least one final insulating plate and at least one final dielectric material plate. Sacrificial material layers that underlie the final vertical stacks are replaced with electrically conductive layers. The final dielectric material plates or conductive material plates formed by replacement of the dielectric material plates are employed as etch stop structures during subsequent formation of layer contact via structures.

IPC Classes  ?

  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

64.

STAIRLESS THREE-DIMENSIONAL MEMORY DEVICE AND METHOD OF MAKING THE SAME BY FORMING REPLACEMENT WORD LINES

      
Application Number 18354269
Status Pending
Filing Date 2023-07-18
First Publication Date 2024-05-30
Owner SANDISK TECHNOLOGIES LLC (USA)
Inventor
  • Tobioka, Akihiro
  • Maekura, Takayuki

Abstract

An alternating stack of insulating layers and sacrificial material layers is formed over a substrate, memory openings are formed through the alternating stack, and memory opening fill structures including a respective vertical stack of memory elements are formed in the memory openings. The sacrificial material layers are replaced with electrically conductive layers. Electrical contacts to the electrically conductive layers may be provided by forming integrated layer-and-via structures that simultaneously forms metallic via portions as an integral portion of a continuous electrically conductive structure that includes a respective electrically conductive layer. Alternatively, electrical contacts to the electrically conductive layers may be provided by forming integrated line-and-via structures that includes a metallic plate portion contacting a respective electrically conductive layer and a metallic via portion.

IPC Classes  ?

  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • H01L 23/528 - Layout of the interconnection structure
  • H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
  • H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
  • H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND

65.

EARLY PROGRAM TERMINATION WITH ADAPTIVE TEMPERATURE COMPENSATION

      
Application Number 18355337
Status Pending
Filing Date 2023-07-19
First Publication Date 2024-05-23
Owner SanDisk Technologies LLC (USA)
Inventor
  • Puthenthermadam, Sarath
  • Liu, Yihang
  • Yuan, Jiahui

Abstract

An apparatus is provided that includes a control circuit coupled to a plurality of non-volatile memory cells. The control circuit is configured to perform a program-verify iteration on a first set of the non-volatile memory cells and a second set of the non-volatile memory cells in a plurality of program loops, determine that at least one of the first set of the non-volatile memory cells and the second set of the non-volatile memory cells verification to a programmed state in a first number of program loops, and compare a difference between the first number of program loops and the second number of program loops to an adaptive maximum loop delta limit. The adaptive maximum loop delta limit varies as a function of temperature.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers
  • G11C 29/12 - Built-in arrangements for testing, e.g. built-in self testing [BIST]

66.

THREE-DIMENSIONAL MEMORY DEVICE WITH SEPARATED SOURCE LINES AND METHOD OF MAKING THE SAME

      
Application Number 18425996
Status Pending
Filing Date 2024-01-29
First Publication Date 2024-05-23
Owner SANDISK TECHNOLOGIES LLC (USA)
Inventor
  • Kai, James
  • Alsmeier, Johann
  • De La Rama, Lito
  • Higashitani, Masaaki
  • Matsuno, Koichi
  • Gunji-Yoneoka, Marika
  • Koto, Makoto
  • Otoi, Hisakazu
  • Tsutsumi, Masanori

Abstract

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a plurality of source layers, where the electrically conductive layers include word lines and source-side select gate electrodes which are located between the plurality of source layers and the word lines in a vertical direction, groups of memory openings vertically extending through the alternating stack, and groups of memory opening fill structures located in the groups of memory openings. The plurality of source layers are laterally spaced apart and electrically isolated from each other, and each respective one of the plurality of source layers contacts at least one respective group of the groups of memory opening fill structures.

IPC Classes  ?

  • H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • G11C 7/18 - Bit line organisation; Bit line lay-out
  • G11C 8/14 - Word line organisation; Word line lay-out
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
  • H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
  • H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND

67.

NON-VOLATILE MEMORY WITH SUB-BLOCKS

      
Application Number 18357450
Status Pending
Filing Date 2023-07-24
First Publication Date 2024-05-16
Owner SanDisk Technologies LLC (USA)
Inventor
  • Yang, Xiang
  • Cao, Wei
  • Guo, Jiacen

Abstract

A non-volatile memory includes a plurality of non-volatile memory cells arranged in blocks. Each block includes multiple sub-blocks that can be independently erased and programmed. A control circuit is connected to the non-volatile memory cells. The control circuit is configured to independently erase and program sub-blocks of a same block. The control circuit is configured to only allow one sub-block per block to be open at a time.

IPC Classes  ?

  • G11C 16/08 - Address circuits; Decoders; Word-line control circuits
  • G06F 12/02 - Addressing or allocation; Relocation
  • G11C 16/10 - Programming or data input circuits
  • G11C 16/16 - Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups

68.

VERA DETECTION METHOD TO CATCH ERASE FAIL

      
Application Number 18356786
Status Pending
Filing Date 2023-07-21
First Publication Date 2024-05-16
Owner SanDisk Technologies LLC (USA)
Inventor
  • Amin, Parth
  • Thoppa, Sai Gautham
  • Khandelwal, Anubhav

Abstract

Technology is disclosed herein for quickly determining which erase block is bad if there is a failure in parallel erasing a set of erase blocks. The erase blocks may be tested individually in response to a fail of the parallel multi-block erase. A voltage generator ramps up the erase voltage from a steady state magnitude towards a target magnitude. The magnitude of the erase voltage is measured at a pre-determined time. If there is a defect then the erase voltage may fail to be above a threshold voltage after the ramp-up period. If the erase voltage is below the threshold voltage after the ramp-up period then the erase block may be marked as defective. If the erase voltage is above the threshold voltage after the ramp-up period then the erase block may be marked as good.

IPC Classes  ?

  • G11C 29/46 - Test trigger logic
  • G11C 16/14 - Circuits for erasing electrically, e.g. erase voltage switching circuits
  • G11C 29/12 - Built-in arrangements for testing, e.g. built-in self testing [BIST]

69.

TRANSISTOR CIRCUITS INCLUDING FRINGELESS TRANSISTORS AND METHOD OF MAKING THE SAME

      
Application Number 18500802
Status Pending
Filing Date 2023-11-02
First Publication Date 2024-05-09
Owner SANDISK TECHNOLOGIES LLC (USA)
Inventor
  • Kodate, Hokuto
  • Yoshizawa, Kazutaka

Abstract

A lateral extent of a gate electrode of a field effect transistor along a gate electrode direction that is perpendicular to a channel direction can be the same as a width of an underlying active region. A gate electrode of an additional field effect transistor may extend over a trench isolation structure that laterally surrounds the additional field effect transistor. Different types of electrodes may be formed by patterning a lower gate material layer and by patterning an upper gate material layer with different patterns such that patterned portions of the lower gate material layer are confined within areas of active regions, while patterned portions of the upper gate material layer extends outside of the areas of the active regions.

IPC Classes  ?

  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 21/8234 - MIS technology
  • H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
  • H01L 29/786 - Thin-film transistors

70.

THREE-DIMENSIONAL MEMORY DEVICE CONTAINING MULTI-LEVEL SUPPORT BRIDGE STRUCTURES AND METHODS FOR FORMING THE SAME

      
Application Number 18450791
Status Pending
Filing Date 2023-08-16
First Publication Date 2024-05-09
Owner SANDISK TECHNOLOGIES LLC (USA)
Inventor
  • Rashidi, Seyyed Ehsan Esfahani
  • Zhang, Yanli
  • Matsuno, Koichi
  • Kai, James

Abstract

A semiconductor structure includes alternating stacks of insulating layers and electrically conductive layers which are located over a substrate and are laterally spaced apart from each other by first backside trenches and second backside trenches that are interlaced along a horizontal direction, first backside trench fill structures located in the first backside trenches, and second backside trench fill structures located in the second backside trenches. Each of the first backside trench fill structures includes a respective set of first backside support bridge structures located at a first vertical spacing from the substrate, and each of the second backside trench fill structures includes a respective set of second backside support bridge structures located at a second vertical spacing from the substrate that is different from the first vertical spacing.

IPC Classes  ?

  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

71.

THREE-DIMENSIONAL MEMORY DEVICE CONTAINING DOPED SOURCE-CHANNEL INTERFACE STRUCTURE AND METHOD OF MAKING THE SAME

      
Application Number 18351181
Status Pending
Filing Date 2023-07-12
First Publication Date 2024-05-02
Owner SANDISK TECHNOLOGIES LLC (USA)
Inventor
  • Ohaga, Motoo
  • Nakamura, Tadashi
  • Yuda, Takashi
  • Fujimura, Nobuyuki
  • Ogawa, Hiroyuki

Abstract

A memory device includes source-level material layers including a source contact layer, an alternating stack of insulating layers and electrically conductive layers located over the source-level material layers, a memory opening vertically extending through the alternating stack and the source contact layer, and a memory opening fill structure located in the memory opening and including a vertical semiconductor channel including an intrinsic or first conductivity type semiconductor material, a memory film surrounding the vertical semiconductor channel, and a conical source pedestal in contact with the source contact layer and in contact with a bottom surface of the vertical semiconductor channel, such that at least portion of the conical source pedestal includes a second conductivity type semiconductor material.

IPC Classes  ?

  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 23/528 - Layout of the interconnection structure
  • H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
  • H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
  • H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
  • H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND

72.

WAFER HOTSPOT-FIXING LAYOUT HINTS BY MACHINE LEARNING

      
Application Number 18355331
Status Pending
Filing Date 2023-07-19
First Publication Date 2024-05-02
Owner SanDisk Technologies LLC (USA)
Inventor
  • Huang, Chen-Che
  • Matsumoto, Lauren
  • Wang, Chunming

Abstract

A system that includes a machine learning model that is configured to receive an input layout file that includes a portion of an integrated circuit layout that has a previously identified wafer hotspot, match the previously identified wafer hotspot to one of a plurality of categories of wafer hotspot types, and output a proposed layout modification associated with the matching category of wafer hotspot types.

IPC Classes  ?

73.

NON-VOLATILE MEMORY WITH DUMMY WORD LINE ASSISTED PRE-CHARGE

      
Application Number 18357467
Status Pending
Filing Date 2023-07-24
First Publication Date 2024-05-02
Owner SanDisk Technologies LLC (USA)
Inventor
  • Zhang, Peng
  • Zhang, Yanli
  • Zhao, Dengtao
  • Guo, Jiacen

Abstract

Memory cells of a second sub-block are programmed by pre-charging channels of unselected memory cells connected to the selected word line, boosting the pre-charged channels of unselected memory cells and applying a program voltage to selected non-volatile memory cells connected to the selected word line. The pre-charging includes applying one or more overdrive voltages to word lines connected to memory cells of a first sub-block to provide a conductive path from memory cells of the second sub-block through the first sub-block to a source line and maintaining the word lines connected to memory cells of the first sub-block at one or more overdrive voltages while ramping down signals at the end of the pre-charging. Dummy word lines, positioned between sub-blocks, are maintained at a resting voltage during the boosting in order to cut-off channels of memory cells in the second sub-block from channels of memory cells in the first sub-block.

IPC Classes  ?

  • G11C 16/08 - Address circuits; Decoders; Word-line control circuits
  • G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • G11C 16/10 - Programming or data input circuits
  • G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention

74.

READ SCHEMES WITH ADJUSTMENT FOR NEIGHBORING WORD LINE SANITIZATION

      
Application Number 18360252
Status Pending
Filing Date 2023-07-27
First Publication Date 2024-05-02
Owner SanDisk Technologies LLC (USA)
Inventor
  • Raquibuzzaman, Md
  • Islam, Sujjatul
  • Kumar, Ravi J.

Abstract

An apparatus includes a control circuit configured connect to non-volatile memory cells. The control circuit is configured to receive a read command directed to data stored in non-volatile memory cells of a first word line and determine that a second word line adjacent to the first word line is sanitized. The control circuit is further configured to select an adjusted read voltage for a read operation directed to the non-volatile memory cells of the first word line based on the determination.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

75.

TRANSISTOR CIRCUITS INCLUDING FRINGELESS TRANSISTORS AND METHOD OF MAKING THE SAME

      
Application Number 18500721
Status Pending
Filing Date 2023-11-02
First Publication Date 2024-05-02
Owner SANDISK TECHNOLOGIES LLC (USA)
Inventor
  • Shishido, Kiyokazu
  • Yoshizawa, Kazutaka
  • Iwata, Dai
  • Kodate, Hokuto

Abstract

A lateral extent of a gate electrode of a field effect transistor along a gate electrode direction that is perpendicular to a channel direction can be the same as a width of an underlying active region. A gate electrode of an additional field effect transistor may extend over a trench isolation structure that laterally surrounds the additional field effect transistor. Different types of electrodes may be formed by patterning a lower gate material layer and by patterning an upper gate material layer with different patterns such that patterned portions of the lower gate material layer are confined within areas of active regions, while patterned portions of the upper gate material layer extends outside of the areas of the active regions.

IPC Classes  ?

  • H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
  • H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region

76.

ROTATABLE TEM GRID HOLDER FOR IMPROVED FIB THINNING PROCESS

      
Application Number 18222280
Status Pending
Filing Date 2023-07-14
First Publication Date 2024-04-18
Owner SanDisk Technologies LLC (USA)
Inventor
  • Zhu, Xiaochen
  • Lay, Norman
  • De La Rama, Lito
  • Yeh, Jimmy

Abstract

A rotatable transmission electron microscope (TEM) grid holder includes first and second legs orthogonally positioned with respect to each other. Each clamp holder leg is configured to be received within a hole in a main stage supporting the rotatable TEM grid holder. When the first leg of the clamp holder is affixed within the main stage, the sample has a first orientation with respect to the FIB, and when second leg of the clamp holder is affixed within the main stage, the sample has a second orientation with respect to the FIB, rotated 90° relative to the first orientation. The sample may be rotated back and forth between the first and second orientations multiple times as needed to produce a sample which may be clearly imaged by the TEM system, substantially free of curtaining effects.

IPC Classes  ?

  • H01J 37/20 - Means for supporting or positioning the object or the material; Means for adjusting diaphragms or lenses associated with the support

77.

NON-VOLATILE MEMORY WITH OVERDRIVE VOLTAGE ZONING TO COMPENSATE FOR REDUCED MARGINS

      
Application Number 18351179
Status Pending
Filing Date 2023-07-12
First Publication Date 2024-04-18
Owner SanDisk Technologies LLC (USA)
Inventor
  • Wang, Peng
  • Wan, Zhenni
  • Li, Jia
  • Liu, Yihang
  • Lei, Bo

Abstract

During a read operation for memory cells connected a selected word line, a memory system adjusts the overdrive voltage applied to word lines adjacent the selected word line in order to compensate for margin degradation between the erased data state and the lowest programmed data state.

IPC Classes  ?

  • G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
  • G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • G11C 16/10 - Programming or data input circuits
  • G11C 16/26 - Sensing or reading circuits; Data output circuits

78.

PROGRAM PULSE DURATION INCREASE FOR NAND PROGRAM FAILURE

      
Application Number 18356760
Status Pending
Filing Date 2023-07-21
First Publication Date 2024-04-18
Owner SanDisk Technologies LLC (USA)
Inventor
  • Zainuddin, Abu Naser
  • Amin, Parth
  • Zhu, Xiaochen
  • Yuan, Jiahui
  • Khandelwal, Anubhav
  • Shanthakumar, Vishwanath Basavaegowda

Abstract

Technology is disclosed herein in which a duration of a program pulse used to program non-volatile memory cells such as NAND may be increased responsive to a programming failure using a shorter duration program pulse. The duration of at least one program pulse may be increased for at least one group of memory cells in response to a failure to program a group using a default program pulse duration. The group that experiences the increased duration program pulse may be the same group for which the program operation failed using the shorter program pulse or may be a different group than the group for which the program operation failed using the shorter program pulse.

IPC Classes  ?

  • G11C 16/10 - Programming or data input circuits
  • G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • G11C 16/16 - Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
  • G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention

79.

SEMICONDUCTOR WAFER CONFIGURED FOR SINGLE TOUCH-DOWN TESTING

      
Application Number 18221797
Status Pending
Filing Date 2023-07-13
First Publication Date 2024-04-18
Owner SanDisk Technologies LLC (USA)
Inventor
  • Miwa, Toru
  • Murai, Takashi
  • Ogawa, Hiroyuki

Abstract

A semiconductor wafer includes pairs of semiconductor dies having test pads which are electrically coupled to each other to enable testing of pairs of semiconductor dies together at the same time. In this way, even wafers having large numbers of semiconductor dies can be tested with a semiconductor test assembly in a single touch-down test process.

IPC Classes  ?

  • H01L 21/66 - Testing or measuring during manufacture or treatment

80.

SEMICONDUCTOR WAFER CONFIGURED FOR SINGLE TOUCH-DOWN TESTING

      
Application Number 18221803
Status Pending
Filing Date 2023-07-13
First Publication Date 2024-04-18
Owner SanDisk Technologies LLC (USA)
Inventor
  • Miwa, Toru
  • Murai, Takashi
  • Ogawa, Hiroyuki
  • Kuliyampattil, Nisha Padattil

Abstract

A semiconductor wafer includes pairs of semiconductor dies having test pads which are electrically coupled to each other to enable testing of pairs of semiconductor dies together at the same time. In this way, even wafers having large numbers of semiconductor dies can be tested with a semiconductor test assembly in a single touch-down test process.

IPC Classes  ?

  • H01L 21/66 - Testing or measuring during manufacture or treatment
  • G01R 1/073 - Multiple probes
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices

81.

SEMICONDUCTOR WAFER CONFIGURED FOR SINGLE TOUCH-DOWN TESTING

      
Application Number 18221824
Status Pending
Filing Date 2023-07-13
First Publication Date 2024-04-18
Owner SanDisk Technologies LLC (USA)
Inventor
  • Miwa, Toru
  • Murai, Takashi
  • Ogawa, Hiroyuki
  • Kuliyampattil, Nisha Padattil

Abstract

A semiconductor wafer includes pairs of semiconductor dies having test pads which are electrically coupled to each other to enable testing of pairs of semiconductor dies together at the same time. In this way, even wafers having large numbers of semiconductor dies can be tested with a semiconductor test assembly in a single touch-down test process.

IPC Classes  ?

  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
  • G01R 1/073 - Multiple probes
  • H01L 21/66 - Testing or measuring during manufacture or treatment
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

82.

THREE-DIMENSIONAL MEMORY DEVICE CONTAINING SELF-ALIGNED FERROELECTRIC MEMORY ELEMENTS AND METHOD OF MAKING THE SAME

      
Application Number 18233628
Status Pending
Filing Date 2023-08-14
First Publication Date 2024-04-18
Owner SANDISK TECHNOLOGIES LLC (USA)
Inventor
  • Sondhi, Kartik
  • Makala, Raghuveer S.
  • Rajashekhar, Adarsh
  • Sharangpani, Rahul
  • Zhou, Fei

Abstract

A semiconductor memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a vertical semiconductor channel and a vertical stack of discrete ferroelectric material portions located at levels of the electrically conductive layers. The discrete ferroelectric material portions protrude inward into the memory opening relative to vertical sidewalls of the insulating layers.

IPC Classes  ?

  • H10B 51/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 51/10 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the top-view layout
  • H10B 51/40 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the peripheral circuit region

83.

THREE-DIMENSIONAL MEMORY DEVICE INCLUDING LATERALLY SEPARATED SOURCE LINES AND METHOD OF MAKING THE SAME

      
Application Number 18350573
Status Pending
Filing Date 2023-07-11
First Publication Date 2024-04-18
Owner SANDISK TECHNOLOGIES LLC (USA)
Inventor
  • Higashitani, Masaaki
  • Kai, James
  • Alsmeier, Johann

Abstract

A memory device includes a first memory block containing first word lines and a first source layer segment, and a second memory block containing second word lines and a second source layer segment which is electrically isolated from the first source layer segment. The first word lines in the first memory block are electrically connected to the respective second word lines in the second memory block.

IPC Classes  ?

  • G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
  • G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 23/528 - Layout of the interconnection structure
  • H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
  • H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
  • H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
  • H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
  • H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region

84.

MULTI-TIER MEMORY DEVICE WITH DIFFERENT WIDTH CENTRAL STAIRCASE REGIONS IN DIFFERENT VERTICAL TIERS AND METHODS FOR FORMING THE SAME

      
Application Number 18347858
Status Pending
Filing Date 2023-07-06
First Publication Date 2024-04-11
Owner SANDISK TECHNOLOGIES LLC (USA)
Inventor
  • Tokita, Hirofumi
  • Sai, Akihisa

Abstract

A memory device includes alternating stacks of insulating layers and electrically conductive layers that are laterally spaced apart from each other along a second horizontal direction, laterally extend along the first horizontal direction through an inter-array region, a first memory array region and a second memory array region that is laterally spaced apart along the first horizontal direction from the memory array region by the inter-array region. Each electrically conductive layer within the alternating stacks has a respective bridge region having a respective strip width along the second horizontal direction within the inter-array region, and the strip width of a topmost electrically conductive layer in a first-tier alternating stack is smaller than the strip width of a topmost electrically conductive layer in a second-tier alternating stack which overlies the first-tier alternating stack.

IPC Classes  ?

  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

85.

THREE-DIMENSIONAL MEMORY DEVICE CONTAINING DISCRETE CHARGE STORAGE ELEMENTS AND METHODS FOR FORMING THE SAME

      
Application Number 18348702
Status Pending
Filing Date 2023-07-07
First Publication Date 2024-04-11
Owner SANDISK TECHNOLOGIES LLC (USA)
Inventor
  • Rajashekhar, Adarsh
  • Makala, Raghuveer S.
  • Zhou, Fei
  • Sharangpani, Rahul
  • Sondhi, Kartik

Abstract

A memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack and having a lateral undulation in a vertical cross-sectional profile such that the memory opening laterally protrudes outward at levels of the electrically conductive layers, and a memory opening fill structure located in the memory opening and including a vertical stack of blocking dielectric material portions located at the levels of the electrically conductive layers, a vertical stack of discrete memory elements located at the levels of the electrically conductive layers and including a respective contoured charge storage material portion, a tunneling dielectric layer overlying the contoured inner sidewalls of the tubular charge storage material portion, and a vertical semiconductor channel.

IPC Classes  ?

  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
  • H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND

86.

METHOD OF MAKING A THREE-DIMENSIONAL MEMORY DEVICE USING DUAL WATER VAPOR FLOW OXIDATION AND APPARATUS FOR PERFORMING THE SAME

      
Application Number 18348727
Status Pending
Filing Date 2023-07-07
First Publication Date 2024-04-11
Owner SANDISK TECHNOLOGIES LLC (USA)
Inventor
  • Hashimoto, Hiraku
  • Takii, Eisuke
  • Koyama, Shin

Abstract

A method includes forming a first portion of a layer over a substrate by flowing a reactant gas past the substrate in a first direction, and forming a second portion of the layer on the first portion of the layer by flowing the reactant gas past the substrate in a second direction different from the first direction.

IPC Classes  ?

  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H01L 21/673 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components using specially adapted carriers
  • H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
  • H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND

87.

GATE-INDUCED DRAIN LEAKAGE PRE-CHARGE IN SUB-BLOCK MODE FOR THREE OR MORE TIER NON-VOLATILE MEMORY STRUCTURE

      
Application Number 17956409
Status Pending
Filing Date 2022-09-29
First Publication Date 2024-04-04
Owner SanDisk Technologies LLC (USA)
Inventor
  • Zhang, Peng
  • Zhang, Yanli

Abstract

An apparatus includes memory cells connected to word lines and disposed in strings each defining a channel and coupled to bit lines and a source line. The memory cells are configured to retain a threshold voltage corresponding to data states. A control means is configured to apply programming pulses followed by verification pulses of program verify voltages associated with the data states to the word lines during a program operation. The control means ramps a selected word line voltage applied to the word lines from one of the program verify voltages to approximately zero while ramping voltages applied to the bit lines and the source line to a high supply voltage during a pre-charge operation. The control means ramps an assist voltage applied to a pre-charge assist portion of the memory apparatus to generate gate-induced drain leakage current in the strings and pre-charge the channel during the pre-charge operation.

IPC Classes  ?

  • G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
  • G11C 16/08 - Address circuits; Decoders; Word-line control circuits
  • G11C 16/24 - Bit-line control circuits
  • G11C 16/28 - Sensing or reading circuits; Data output circuits using differential sensing or reference cells, e.g. dummy cells

88.

Non-volatile memory with reduced word line switch area

      
Application Number 17957424
Grant Number 12032837
Status In Force
Filing Date 2022-09-30
First Publication Date 2024-04-04
Grant Date 2024-07-09
Owner SanDisk Technologies LLC (USA)
Inventor
  • Mizutani, Yuki
  • Yoshizawa, Kazutaka
  • Shishido, Kiyokazu
  • Fujikura, Eiichi

Abstract

A three dimensional non-volatile memory structure includes word lines connected to non-volatile memory cells arranged in blocks. A plurality of word line switches are connected to the word lines and one or more sources of voltage. The word line switches are arranged in groups of X word line switches such that each group of X word line switches is positioned in a line under Y blocks of non-volatile memory cells and has a length that is equal to the width of the Y blocks of non-volatile memory cells. To allow closer placement of word line switches that supply different blocks and support the possible large voltage differences between their transistors, word line switches supplying different blocks are formed over a single active region and separated by an intermediate control gate set to be off.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

89.

NON-VOLATILE MEMORY WITH DIFFERENT WORD LINE TO WORD LINE PITCHES

      
Application Number 17955878
Status Pending
Filing Date 2022-09-29
First Publication Date 2024-04-04
Owner SanDisk Technologies LLC (USA)
Inventor
  • Yang, Xiang
  • Cao, Wei
  • Guo, Jiacen

Abstract

In a multi-tiered non-volatile memory structure that can perform operations on sub-blocks, performance of the different tiers/sub-blocks is made consistent by using different word line to word line pitches in the different tiers/sub-blocks.

IPC Classes  ?

  • G11C 16/08 - Address circuits; Decoders; Word-line control circuits
  • G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • G11C 16/10 - Programming or data input circuits
  • G11C 16/24 - Bit-line control circuits

90.

HIGH PERFORMANCE VERIFY TECHNIQUES IN A MEMORY DEVICE

      
Application Number 17957606
Status Pending
Filing Date 2022-09-30
First Publication Date 2024-04-04
Owner SanDisk Technologies LLC (USA)
Inventor
  • Yang, Xiang
  • Cao, Wei
  • Dutta, Deepanshu

Abstract

The memory device includes at least one memory block with a plurality of memory cells arranged in a plurality of word lines. The memory device includes control circuitry that is configured to program the memory cells of the at least one memory block in a plurality of program loops. The control circuitry is further configured to receive a command to write user data to the memory device. On at least a portion of a selected word line of the plurality of word lines, the control circuitry is configured to perform a smart verify operation to acquire a smart verify programming voltage. After the smart verify programming voltage is acquired, in a plurality of program loops, the control circuitry is configured to program the memory cells of the selected word line to include the user data and data that corresponds to the smart verify programming voltage.

IPC Classes  ?

  • G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
  • G11C 16/08 - Address circuits; Decoders; Word-line control circuits
  • G11C 16/10 - Programming or data input circuits

91.

THREE-DIMENSIONAL MEMORY DEVICE WITH SOURCE LINE ISOLATION AND METHOD OF MAKING THE SAME

      
Application Number 17934685
Status Pending
Filing Date 2022-09-23
First Publication Date 2024-03-28
Owner SANDISK TECHNOLOGIES LLC (USA)
Inventor
  • Said, Ramy Nashed Bassely
  • Yuan, Jiahui
  • De La Rama, Lito

Abstract

A memory device includes a horizontal source layer which is laterally separated into laterally isolated portions located in adjacent memory blocks by a dielectric backside trench fill structure or a source isolation dielectric structure.

IPC Classes  ?

  • H01L 23/535 - Arrangements for conducting electric current within the device in operation from one component to another including internal interconnections, e.g. cross-under constructions
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
  • H01L 27/11529 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the peripheral circuit region of memory regions comprising cell select transistors, e.g. NAND
  • H01L 27/11556 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H01L 27/11573 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the peripheral circuit region
  • H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

92.

NON-VOLATILE MEMORY WITH SUB-PLANES HAVING INDIVIDUALLY BIASABLE SOURCE LINES

      
Application Number 17952857
Status Pending
Filing Date 2022-09-26
First Publication Date 2024-03-28
Owner SanDisk Technologies LLC (USA)
Inventor
  • Said, Ramy Nashed Bassely
  • Yuan, Jiahui
  • De La Rama, Lito

Abstract

To reduce data disturbs and lower current requirements of a 3D NAND memory die, a multi-block plane of non-volatile memory cells has its source line separated into multiple source line regions by introduction of isolation trenches. The plane structure for the NAND memory is maintained, but is broken into multi-block sub-planes, each with an independently biasable source line.

IPC Classes  ?

  • G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • G06F 3/06 - Digital input from, or digital output to, record carriers
  • G11C 16/08 - Address circuits; Decoders; Word-line control circuits
  • G11C 16/14 - Circuits for erasing electrically, e.g. erase voltage switching circuits
  • G11C 16/26 - Sensing or reading circuits; Data output circuits

93.

BIT LINE MODULATION TO COMPENSATE FOR CELL SOURCE VARIATION

      
Application Number 17954489
Status Pending
Filing Date 2022-09-28
First Publication Date 2024-03-28
Owner SanDisk Technologies LLC (USA)
Inventor
  • Amarnath, Anirudh
  • Suresh, Aravind
  • Prakash, Abhijith

Abstract

Systems and methods for bit line modulation to compensate for cell source variation are disclosed. For example, a method for reading data from non-volatile storage comprising determining a first bit line level based on a first programmed data state that is being sensed and determining a second bit line level based on a second programmed data state that is being sensed. As another example, a storage device comprising a first bit line driver configured to generate a first bit line level for a first set of bit lines corresponding to a first set of memory strings based on a first cell source level associated with the first set of memory strings a second bit line driver configured to generate a second bit line level for a second set of bit lines corresponding to a second set of memory strings based on a second cell source level associated with the second set of memory strings.

IPC Classes  ?

  • G11C 16/26 - Sensing or reading circuits; Data output circuits
  • G11C 16/10 - Programming or data input circuits
  • G11C 16/24 - Bit-line control circuits

94.

PREVENTING ERASE DISTURB IN NAND

      
Application Number 17954937
Status Pending
Filing Date 2022-09-28
First Publication Date 2024-03-28
Owner SanDisk Technologies LLC (USA)
Inventor
  • Zhang, Yanli
  • Kai, James K.
  • Alsmeier, Johann

Abstract

Technology is disclosed herein for preventing erase disturb in NAND. Erase voltages are applied to a source line and bit lines associated with selected memory cells, while applying an erase enable voltage to word lines connected to the selected cells. Preventing erase disturb may include raising the channel potential of unselected memory cells to a source line voltage that has a sufficiently low magnitude to not erase the unselected cells given a voltage on word lines connected to the unselected cells. The unselected cells share bit lines with the selected cells and may also share word lines. Preventing erase disturb may also include applying voltages to the select transistors that prevent the erase voltage from passing from the shared bit lines to the channels of the unselected cells. The voltages decrease from the bit lines to the unselected memory cells and may prevent GIDL generation. Current consumption is kept low.

IPC Classes  ?

  • G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
  • G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • G11C 16/08 - Address circuits; Decoders; Word-line control circuits
  • G11C 16/14 - Circuits for erasing electrically, e.g. erase voltage switching circuits
  • G11C 16/24 - Bit-line control circuits

95.

NON-VOLATILE MEMORY WITH PROGRAMMABLE RESISTANCE NON-DATA WORD LINE

      
Application Number 17955018
Status Pending
Filing Date 2022-09-28
First Publication Date 2024-03-28
Owner SanDisk Technologies LLC (USA)
Inventor
  • Razzak, Towhidur
  • Kumar, Ravi
  • Zainuddin, Abu Naser
  • Yuan, Jiahui

Abstract

In order to lower the peak and average current through the channel (thereby lowering peak and average power consumption) during program-verify, which exhibits a word line dependency, the inventors propose to program dummy memory cells connected to a dummy word line before programming data memory cells connected to a data word line. The additional resistance in the NAND string introduced by the preprogrammed dummy memory cells will cause the peak current, and power consumption, to be lower. To address the word line dependency, the dummy memory cells connected to the dummy word line can be programmed to different threshold voltages based on which data word line is to be programmed. Thus, prior to programming data non-volatile memory cells connected to a particular data word line, the dummy memory cells are programmed to a threshold voltage that is chosen based on the position of the particular data word line.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

96.

THREE-DIMENSIONAL MEMORY DEVICE WITH SOURCE LINE ISOLATION AND METHOD OF MAKING THE SAME

      
Application Number 17934676
Status Pending
Filing Date 2022-09-23
First Publication Date 2024-03-28
Owner SANDISK TECHNOLOGIES LLC (USA)
Inventor
  • Said, Ramy Nashed Bassely
  • Yuan, Jiahui
  • De La Rama, Lito

Abstract

A memory device includes a horizontal source layer which is laterally separated into laterally isolated portions located in adjacent memory blocks by a dielectric backside trench fill structure or a source isolation dielectric structure.

IPC Classes  ?

  • H01L 23/535 - Arrangements for conducting electric current within the device in operation from one component to another including internal interconnections, e.g. cross-under constructions
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
  • H01L 27/11529 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the peripheral circuit region of memory regions comprising cell select transistors, e.g. NAND
  • H01L 27/11556 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H01L 27/11573 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the peripheral circuit region
  • H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

97.

THREE-DIMENSIONAL MEMORY DEVICE CONTAINING MEMORY OPENING MONITORING AREA AND METHODS OF MAKING THE SAME

      
Application Number 17936012
Status Pending
Filing Date 2022-09-28
First Publication Date 2024-03-28
Owner SANDISK TECHNOLOGIES LLC (USA)
Inventor
  • Ogawa, Hiroyuki
  • Miyamoto, Masato
  • Shigemura, Keisuke

Abstract

A method of forming a three-dimensional semiconductor device includes forming an alternating stack of insulating layers and spacer material layers over a substrate, forming memory openings formed in the memory array region and monitor openings formed in a monitor region though the alternating stack, forming memory opening fill structures in the memory openings, forming monitor opening fill structures by depositing a monitor opening fill material in the monitor openings, recessing first portions of the alternating stack in a contact region and second portions of the alternating stack in the monitor region, and determining at least one characteristic of the recessed surfaces of the monitor opening fill structures. At least one characteristic of the memory openings or memory opening fill structures may be determined based on the determining at least one characteristic of the recessed surfaces of the monitor opening fill structures.

IPC Classes  ?

  • H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 23/528 - Layout of the interconnection structure
  • H01L 27/11519 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the top-view layout
  • H01L 27/11524 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the memory core region with cell select transistors, e.g. NAND
  • H01L 27/11556 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H01L 27/11565 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the top-view layout
  • H01L 27/1157 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the memory core region with cell select transistors, e.g. NAND

98.

ERASE METHOD FOR NON-VOLATILE MEMORY WITH MULTIPLE TIERS

      
Application Number 17952846
Status Pending
Filing Date 2022-09-26
First Publication Date 2024-03-28
Owner SanDisk Technologies LLC (USA)
Inventor
  • Yang, Xiang
  • Higashitani, Masaaki
  • Prakash, Abhijith
  • Zhao, Dengtao

Abstract

A non-volatile memory system comprises a plurality of non-volatile memory cells divided into three or more tiers. The memory cells can be programmed, erased and read. In order to achieve uniform erase speed for the three or more tiers, the erase process comprises applying a larger voltage bias to control gates of non-volatile memory cells in the outer tiers than the voltage bias applied to control gates of non-volatile memory cells in one or more inner tiers.

IPC Classes  ?

  • G11C 16/14 - Circuits for erasing electrically, e.g. erase voltage switching circuits
  • G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention

99.

SEMICONDUCTOR DEVICE HAVING EDGE SEAL AND METHOD OF MAKING THEREOF WITHOUT METAL HARD MASK ARCING

      
Application Number 17932887
Status Pending
Filing Date 2022-09-16
First Publication Date 2024-03-21
Owner SANDISK TECHNOLOGIES LLC (USA)
Inventor Watanabe, Kazuto

Abstract

A conductive hard mask layer can be patterned with peripheral discrete openings. An anisotropic etch process can be performed to form peripheral discrete via cavities, which are subsequently expanded to form a continuous moat trench. An edge seal structure can be formed in the continuous moat trench. Alternatively, a conductive bridge structure may be formed prior to formation of a patterned conductive hard mask layer, and a moat trench can be formed around a periphery of the semiconductor die while the conductive bridge structure provides electrical connection between an inner portion and an outer portion of the conductive hard mask layer. The entire conductive hard mask layer can be electrically connected to a semiconductor substrate to reduce or prevent arcing during an anisotropic etch process that forms the peripheral discrete via cavities or the moat trench.

IPC Classes  ?

  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 21/311 - Etching the insulating layers

100.

SEMICONDUCTOR DEVICE HAVING EDGE SEAL AND METHOD OF MAKING THEREOF WITHOUT METAL HARD MASK ARCING

      
Application Number 17932907
Status Pending
Filing Date 2022-09-16
First Publication Date 2024-03-21
Owner SANDISK TECHNOLOGIES LLC (USA)
Inventor
  • Sano, Michiaki
  • Hinoue, Tatsuya

Abstract

A conductive hard mask layer can be patterned with peripheral discrete openings. An anisotropic etch process can be performed to form peripheral discrete via cavities, which are subsequently expanded to form a continuous moat trench. An edge seal structure can be formed in the continuous moat trench. Alternatively, a conductive bridge structure may be formed prior to formation of a patterned conductive hard mask layer, and a moat trench can be formed around a periphery of the semiconductor die while the conductive bridge structure provides electrical connection between an inner portion and an outer portion of the conductive hard mask layer. The entire conductive hard mask layer can be electrically connected to a semiconductor substrate to reduce or prevent arcing during an anisotropic etch process that forms the peripheral discrete via cavities or the moat trench.

IPC Classes  ?

  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 21/311 - Etching the insulating layers
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