A first optical module includes an optical transceiver and a chip. The optical transceiver, subsequent to completion of link training of an in-band transmission link between the first optical module and a host device, waits for a second optical module to come up including transmitting a first awake signal from the first optical module to the second optical module, and receives a second awake signal from the second optical module when the second optical module is up. The chip i) based on a first out-of-band signal transmitted via an out-of-band link, performs the link training of the in-band transmission link independently of an in-band reception link between the first optical module and the host device, and ii) based on the second awake signal and a second out-of-band signal transmitted via the out-of-band link, performs link training of the in-band reception link independent of the in-band transmission link.
H04B 10/079 - Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems using an in-service signal using measurements of the data signal
H04B 10/077 - Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems using an in-service signal using a supervisory or additional signal
H04B 10/80 - Optical aspects relating to the use of optical transmission for specific applications, not provided for in groups , e.g. optical power feeding or optical transmission through water
2.
GATE ALL-AROUND (GAA) FIELD EFFECT TRANSISTORS (FETS) FORMED ON BOTH SIDES OF A SUBSTRATE
An electronic device (11) includes a substrate (55), first and second semiconductor devices (22, 33), and a power supply structure (88b). The first semiconductor device (22) includes a first plurality of gate all-around (GAA) field effect transistors (FETs) (44) formed over a first side (25) of substrate (55). The second semiconductor device (33) includes a second plurality of GAA FETs (44) formed over a second side (35) of substrate (55), opposite first side (25). The power supply structure (88b) is (a) disposed at the first side (25), and (b) configured to supply power to one or more of: (i) the first plurality of GAA FETs (44) through first electrical couplings (77) disposed at the first side (25), and (ii) the second plurality of GAA FETs (44) through second electrical couplings (77) including inter-side vias (ISVs) (66) traversing the substrate (55) from the second side (35) to the first side (35).
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
The present disclosure describes apparatuses and methods for implementing an adaptive low-density parity check (LDPC) decoder performing iterations on bit-flipping or symbol-flipping operations. In various aspects, an adaptive LDPC decoder (130) processes (704) a first portion of data using first parameters, e.g. flipping thresholds, effective to change a status of the LDPC decoder, e.g. syndrome weight. The LDPC decoder selects (706) second parameters, e.g. adaptively changes flipping thresholds, of the LDPC decoder based on the status of the LDPC decoder. The LDPC decoder then processes (708) a second portion of the data with the LDPC decoder using the second parameters and provides (712) decoded data of the channel based on at least the processing the first portion of the data using the first parameters and the processing of the second portion of the data using the second parameters. By adaptively altering the decoding parameters based the status of the decoder, the adaptive LDPC decoder may decode channel data in fewer decoding iterations or with a higher success rate, thereby improving LDPC decoding performance.
H03M 13/37 - Decoding methods or techniques, not specific to the particular type of coding provided for in groups
H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
4.
INTEGRATED CIRCUIT DEVICE EXPOSED DIE PACKAGE STRUCTURE WITH ADHESIVE
An integrated circuit (IC) device package includes a structure having a base and walls extending from the base, at least one IC die mounted to the base within the walls, each die having a top surface parallel to the base and having a thickness extending along an axis, perpendicular to the top surface, at most equal to a height of the walls, a thermally conductive heat spreader extending parallel to the base above the die and the walls, and an interface layer including an adhesive layer portion disposed between the walls and the heat spreader to adhere the heat spreader to the walls, and a thermal interface material (TIM) layer portion coplanar with, and laterally displaced from, the adhesive layer portion, the TIM layer portion being disposed in thermally conductive relationship between the heat spreader and each respective die, to dissipate heat from each respective die to the heat spreader.
An optical signal transceiver includes a circuit board substrate, a silicon photonics-based interposer mounted on the circuit board substrate, the silicon photonics-based interposer including at least one of a waveguide configured to transmit optical communication signals and a photo detector configured to detect optical communication signals, and a planar lightwave circuit disposed on the circuit board substrate. The planar lightwave circuit is configured to perform at least a portion of propagation of light signals in an optical communication network, and the planar lightwave circuit is aligned with a side surface of the silicon photonics-based interposer to transmit optical communication signals between the silicon photonics-based interposer and the planar lightwave circuit. The optical signal transceiver includes at least one spacer component disposed between the planar lightwave circuit and the circuit board substrate, and epoxy material in contact with the spacer component.
A network interface device operates in a normal transmit operating mode in which the network interface device continually receives transmission symbols from a link partner via the communication link. The network interface device determines that receive circuitry of the network interface device is to transition to a low power mode in response to receiving a sleep signal from the link partner. The network interface device then operates according to a quiet/refresh cycle of the low power mode to conserve power. The quiet/refresh cycle corresponds to a time schedule that includes a refresh time window in which receive circuitry of the network interface device is to be powered to receive a refresh signal from the link partner. Immediately after transmission of the sleep signal, the network interface device transitions to a quiet time window of the time schedule in which the network interface device ignores transmissions from the link partner.
In a communication network operating according to a communication protocol that defines a link establishment procedure having i) a negotiating procedure and ii) a training procedure, a first communication device performs the link establishment procedure with a second communication device. During the negotiating procedure, the first communication device negotiates one or more new parameter values for the link establishment procedure that are different than one or more mandated parameter values specified by the communication protocol. During the link establishment procedure, the first communication device uses the one or more new parameter values instead of using the one or more mandated parameter values specified by the communication protocol.
An optical module includes a plurality of lasers, each of at least some of the lasers configured to be selectively turned on and turned off depending on a type of modulation to be used. Each laser corresponds to a respective wavelength. The optical module also includes an optical modulation system having a plurality of optical modulators. A reconfigurable optical network of the optical module is configured to selectively direct light from the plurality of lasers to the optical modulation system differently depending on the type of modulation to be used.
An optical modulator includes a semiconductor substrate and an optical waveguide portion disposed on the semiconductor substrate. A signal contact that extends alongside the optical waveguide portion is disposed on the semiconductor substrate. A first ground line is disposed on the semiconductor substrate spaced away from the signal contact by a first spacing. A second ground line is disposed on the semiconductor substrate spaced away from the signal contact by a second spacing opposite the first ground line. The first spacing is different from the second spacing.
G02F 1/015 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on semiconductor elements with at least one potential jump barrier, e.g. PN, PIN junction
G02F 1/025 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on semiconductor elements with at least one potential jump barrier, e.g. PN, PIN junction in an optical waveguide structure
G02F 1/225 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour by interference in an optical waveguide structure
10.
METHOD OF FABRICATING SI PHOTONICS CHIP WITH INTEGRATED HIGH SPEED GE PHOTO DETECTOR WORKING FOR ENTIRE C- AND L-BAND
A receiver for receiving optical signals transmitted over a communications network includes a silicon photonics substrate including multiple regions with respectively different doping, an epitaxial germanium layer extending at least partially over at least two or more of regions with different doping, and at least one of a tensile stressor component and a compressive stressor component in contact with the epitaxial germanium layer. The tensile stressor component and the compressive stressor component are respectively configured to mechanically strain the epitaxial germanium layer to modify an optical signal absorption attribute of the epitaxial germanium layer. The receiver includes a receive circuit including at least one electrode component in electrical contact with the epitaxial germanium layer. The receive circuit is configured to generate an electrical output in response to an optical signal received from a network interface of the communications network by the epitaxial germanium layer.
H01L 31/10 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by at least one potential-jump barrier or surface barrier, e.g. phototransistors
H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
H01L 31/0256 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by their semiconductor bodies characterised by the material
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H04B 10/69 - Electrical arrangements in the receiver
A photonic integrated circuit (PIC) includes photonic components fabricated on the PIC. One of the photonic components includes an optical coupler configured to optically couple to an optical component. The optical coupler includes waveguide elements arranged in a 2- dimensional array that is configured to provide a first mode having a first shape chosen to match a second shape of a second mode of the optical component.
G02B 6/12 - Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
G02B 6/122 - Basic optical elements, e.g. light-guiding paths
A sensor bridge (36), for use in an Ethernet network in a vehicle (24), includes a sensor interface (52), a mapper (56) and a communication processor (60). The sensor interface is configured to receive sensor data from a sensor (28) installed in the vehicle. The mapper is configured to form mapped sensor data by applying to the sensor data a direct mapping that maps specified parts of the sensor data to corresponding bit positions in one or more Ethernet packets. The communication processor is configured to generate the one or more Ethernet packets including the mapped sensor data, and to transmit the one or more Ethernet packets over the Ethernet network.
An apparatus for controlling an imaging sensor (28) in a vehicle (24) includes an Ethernet transceiver (72), a sensor interface (80) and a local processor (76). The Ethernet transceiver is configured to communicate over an in-vehicle Ethernet network with a remote processor. The sensor interface is configured to communicate with the imaging sensor. The local processor that is local to the apparatus and remotely located from the remote processor is configured to receive from the imaging sensor, via the sensor interface, image data and auxiliary data related to the image data, to send at least the image data to the remote processor via the Ethernet transceiver, to generate locally, based on the auxiliary data, and independently from the remote processor, control commands to control an operational aspect of the imaging sensor, and to send the control commands to the imaging sensor via the sensor interface.
H04N 7/18 - Closed-circuit television [CCTV] systems, i.e. systems in which the video signal is not broadcast
B60R 16/023 - Electric or fluid circuits specially adapted for vehicles and not otherwise provided for; Arrangement of elements of electric or fluid circuits specially adapted for vehicles and not otherwise provided for electric for transmission of signals between vehicle parts or subsystems
An input signal is sampled at a current sampling phase by a sampler device of a receiver device. The sampled input signal is equalized by an adaptive equalizer of the receiver device. One or more parameters of the adaptive equalizer are adapted, based on the equalized input signal, under one or more adaptation constraints. Phase gradient information indicative of an offset of the current sampling phase from an optimal sampling phase is determined, and the one or more adaptation constraints of the adaptive equalizer are updated based on the phase gradient information to move the current sampling phase towards the optimal sampling phase
The present disclosure describes apparatuses and methods for machine learning-enabled (ML-enabled) management of storage media access. In some aspects, an ML-enabled storage controller obtains features of available blocks of storage media of a storage media system. The controller can receive, from a host system, a request to write data and determine features of the data to be written to the storage media. The controller provides the respective features of the available blocks and the data to a neural network and receives, from the neural network, a selected block of the available blocks for writing of the data. The selected block may include an ML-optimized selection from the available blocks based on the features of both the available blocks and the data. The controller then writes the data of the request to the ML-selected block of storage media of the storage media system, which may improve storage media performance.
A semiconductor device package includes a semiconductor die having two largest dimensions that define a major plane, a packaging material enclosing the semiconductor die, a plurality of contacts on a first exterior surface of the semiconductor device package that is parallel to the major plane, the first exterior surface defining a bottom of the semiconductor device package, and a pedestal of semiconductor material above the semiconductor die in a thermally-conductive, electrically non-conductive relationship with the semiconductor die. The semiconductor material of the pedestal may be doped to provide electromagnetic shielding of the semiconductor die.
A communication system (20) includes a first physical -layer (PHY) transceiver (36) and a second PHY transceiver (36). The first PHY transceiver includes (i) a first transmitter and (ii) a first receiver including a first equalizer (64). The second PHY transceiver includes (i) a second transmitter and (ii) a second receiver including a second equalizer (64). The first PHY transceiver and the second PHY transceiver are configured to communicate with one another over a full-duplex link (40), including training the first equalizer on a second training signal transmitted from the second PHY transceiver, and concurrently training the second equalizer on a first training signal transmitted from the first PHY transceiver.
H04B 3/23 - Reducing echo effects or singing; Opening or closing transmitting path; Conditioning for transmission in one direction or the other using a replica of transmitted signal in the time domain, e.g. echo cancellers
An electronic device (66), including a substrate (33) and a stack of dies stacked on the substrate. The stack of dies includes: (a) one or more functional dies (12, 13, 14, 15), the functional dies (12, 13, 14, 15) including functional electronic circuits and being configured to exchange electrical signals at least with the substrate (33), and (b) one or more dummy dies (88, 99), the dummy dies (88, 99) being disposed among dies forming the stack and being configured to: (i) dissipate heat generated by the one or more functional dies (12, 13, 14, 15) and (ii) pass electrical signals exchanged between the substrate (33) and the one or more functional dies (12, 13, 14, 15) or between two or more of the functional dies (12, 13, 14, 15).
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 23/36 - Selection of materials, or shaping, to facilitate cooling or heating, e.g. heat sinks
H01L 23/14 - Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
19.
DOUBLE SEAL RING AND ELECTRICAL CONNECTION OF MULTIPLE CHIPLETS
An electronic device (11) includes: (i) a first chiplet (22) including a first seal ring (44), which is disposed in metal layers embedded between a first surface (20a) of the first chiplet (22), and a first substrate (18a) of the first chiplet (22), (ii) a second chiplet (33) including a second seal ring (55), which is disposed in metal layers embedded between a second surface (20b) of the second chiplet (33), and a second substrate (18b) of the second chiplet (33), and (iii) a third seal ring (66), which surrounds the first and second chiplets (22, 33) and is disposed in a dielectric substrate (67, 68, 69a, 69b) extrinsic to the metal layers and overlaying the first and second surfaces (20a, 20b) of the first and second chiplets (22, 33).
H01L 23/58 - Structural electrical arrangements for semiconductor devices not otherwise provided for
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 23/14 - Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
20.
METHOD AND APPARATUS FOR CANCELLING FRONT-END DISTORTION
Transceiver circuitry in an integrated circuit device includes a receive path including an analog front end for receiving analog signals from an analog transmission path and conditioning the analog signals, and an analog-to-digital converter configured to convert the conditioned analog signals into received digital signals for delivery to functional circuitry, and a transmit path including a digital front end configured to accept digital signals from the functional circuitry and to condition the accepted digital signals, and a digital-to-analog converter configured to convert the conditioned digital signals into analog signals for transmission onto the analog transmission path. At least one of the analog front end and the digital front end introduces distortion and outputs a distorted conditioned signal. The transceiver circuitry further includes distortion correction circuitry at the one of the analog front end and the digital front end, to determine and apply a distortion cancellation function to the distorted signal.
H04B 1/12 - Neutralising, balancing, or compensation arrangements
H04B 1/38 - Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
H03F 1/32 - Modifications of amplifiers to reduce non-linear distortion
H04B 1/525 - Hybrid arrangements, i.e. arrangements for transition from single-path two-direction transmission to single-direction transmission on each of two paths or vice versa with means for reducing leakage of transmitter signal into the receiver
21.
SPECTRAL CONTENT DETECTION FOR EQUALIZING INTERLEAVED DATA PATHS
A high-speed data receiver includes interleaver circuitry configured to divide a received data stream into a plurality of interleaved paths for processing, spectral content detection circuitry configured to derive spectral content information from data on each of the plurality of interleaved paths, sorting circuitry configured to bin the derived spectral content information according to energy levels, stream attribute determination circuitry configured to determine, based on sorted spectral content, one or more of path offsets of the interleaved paths, gain mismatch among interleaved paths, signal bandwidth mismatch and pulse width mismatch, and equalization circuitry configured to correct the one or more of the determined offsets, the determined gain mismatch and the determined signal width mismatch. Equalization circuitry may be configured to equalize a gain-normalized signal by separately adjusting respective bandwidth actuators of each respective interleaved path and respective pulse width actuators of each respective interleaved path.
A network device (20) includes one or more circuit components (28, 56, 64, 68, 76, 84). The circuit components include a semiconductor substrate (24), a first device terminal (32) and a second device terminal (40), a drift region (44), and a mobility modulator (52). Both device terminals are coupled to the substrate, the second device terminal being spatially separated from the first device terminal. The drift region is disposed on the substrate between the first device terminal and the second device terminal, the drift region being configured to allow a flow of charge-carriers between the first device terminal and the second device terminal. The mobility modulator is coupled to the drift region and is configured to apply a field across the drift region responsive to one or more modulation signals, so as to modulate a mobility of charge-carriers as a function of longitudinal position along the drift region.
An apparatus for monitoring strain in an optical chip in silicon photonics platform. The apparatus includes a silicon photonics substrate shared with the optical chip. Additionally, the apparatus includes an optical input configured in the silicon photonics substrate to supply an input signal of a single wavelength. The apparatus further includes a first waveguide arm and a second waveguide arm embedded in the silicon photonics substrate to form an on-chip interferometer. The second waveguide arm forms a delay line being disposed at a region in or adjacent to the optical chip. The on-chip interferometer is configured to generate an interference pattern serving as an indicator of strain distributed at the region in or adjacent to the optical chip. The interference pattern is caused by a temperature-independent phase shift at the single wavelength of the interferometer between the first waveguide arm and the second waveguide arm.
G01D 5/353 - Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using optical means, i.e. using infrared, visible or ultraviolet light with attenuation or whole or partial obturation of beams of light the beams of light being detected by photocells influencing the transmission properties of an optical fibre
G01L 1/24 - Measuring force or stress, in general by measuring variations of optical properties of material when it is stressed, e.g. by photoelastic stress analysis
G02B 6/10 - Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
24.
METHOD AND DEVICE FOR TIMING RECOVERY DECOUPLED FEE ADAPTATION IN SERDES RECEIVERS
A device and method for a receiver configured to perform timing recovery decoupled feed-forward equalizer (FFE) adaptation. The receiver device can include an analog front-end (AFE) device, which is coupled to a time-interleaved (TI) interface. The TI interface is coupled in a timing recovery feedback loop to FFE equalizers, a digital signal processor (DSP), a delay timing loop (DTL) device, and a clock device, which feeds back to the TI interface. The DSP has an additional pathway to the FFE equalizers, which has an additional pathway to the DTL device. The DTL loop is equipped with an interleave specific enable/disable vector Q[1:N] that can turn on/off the contribution of the specific time interleave errors to the timing recovery loop, which allows the FFE adaptation process to be decoupled from the timing recovery loop.
H04L 25/03 - Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
25.
NETWORK OPTIMIZATION FOR MITIGATION OF CROSSTALK BETWEEN NETWORK LINKS
A network controller receives link metrics for network links on cables between network devices in a communication network. The link metrics include metrics indicative of crosstalk experienced by network links among the network links on cables. The network controller determines, based at least in part on the link metrics, respective link settings for respective network links among the network links. The link settings are determined to mitigate crosstalk experienced by the respective network links as a result of transmission of signals in at least some of the network links at baud rates that correspond to bandwidths that exceed maximum bandwidth ratings of respective cables of the corresponding ones of the network links. The network controller causes configuration of the respective network links based on the link settings to optimize performance across the plurality of network links in the communication network.
A transceiver transmits data via a first cable among a plurality of cables in a wired communication network, and selectively operates in one of (i) an active mode for transmitting data to a link partner via the first cable and (ii) a low power mode during which the transceiver quiets transmissions to conserve power. A crosstalk detector determines that transmission of data in the first cable is causing crosstalk in one or more second cables. A controller, in response to the crosstalk detector determining that transmission of the data in the first cable is causing crosstalk in one or more second cables, controls the transceiver to operate in the low power mode during a plurality of first time periods to reduce crosstalk in the one or more second cables during the plurality of first time periods.
An optical modulator includes, a semiconductor substrate, an optical waveguide portion disposed on the semiconductor substrate, a first P-N junction disposed on the semiconductor substrate, and a second P-N disposed on the semiconductor substrate. The optical waveguide portion provides an optical path for light that is to be modulated. The first P-N junction is disposed on the semiconductor substrate along the optical path and defines a border between an N-doped portion disposed on the semiconductor substrate and a P-doped portion disposed on the semiconductor substrate. The second P-N junction is disposed on a portion of the semiconductor substrate alongside the optical path and spaced apart from the first P-N junction.
G02F 1/025 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on semiconductor elements with at least one potential jump barrier, e.g. PN, PIN junction in an optical waveguide structure
28.
METHODS FOR CO-PACKAGING OPTICAL MODULES ON SWITCH PACKAGE SUBSTRATE
An assembled electro-optical switch module includes a package substrate. Four optical socket members are disposed respectively to the package substrate. Each optical socket member includes four sockets closely packed in a row. Each socket has a recessed flat region with topside land grid array (LGA) interposer connected to bottom side solder bumps and a side notch opening aligned to an edge of the package substrate at the corresponding edge region. Sixteen optical modules in four sets are co-packaged in the package substrate. Each set has four optical modules respectively seated in the four sockets of each optical socket member with top side LGA interposer. Four clamp latch members are applied to clamp each of the four sets of optical modules in respective optical socket members. A data processor device with 51.2Tbps data interface is disposed to the package substrate and electrically coupled to each of the sixteen optical modules.
G02B 6/42 - Coupling light guides with opto-electronic elements
G02B 6/12 - Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
G02B 6/35 - Optical coupling means having switching means
G02B 6/38 - Mechanical coupling means having fibre to fibre mating means
29.
INTEGRATED CIRCUIT PACKAGE COMPRISING A SUBSTRATE STACK AND METHOD OF ASSEMBLY USING A TEMPORARY RIGID CARRIER
A method for assembling at least one stacked substrate package, each stacked substrate package includes binding a laminated base substrate (104), configured to route interconnections between circuitry on a first surface of the laminated base substrate and circuitry on a second surface of the laminated base substrate, to a surface of a rigid carrier (102) to prevent warping of the laminated base substrate (104). Each base substrate is coupled to at least one dielectric build-up substrate (106), which is configured to route integrated interconnections between a top surface and a bottom surface of the dielectric build-up substrate, to the laminated base substrate (104). At least one integrated circuit die (108) is coupled to the at least one dielectric build-up substrate (106), and then the carrier (102) is released from the laminated base substrate (104) to form an assembled stacked substrate package. Also, multiple stacked substrate packages may be assembled in parallel on one carrier.
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 23/36 - Selection of materials, or shaping, to facilitate cooling or heating, e.g. heat sinks
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
30.
HIGH-POWER TUNABLE LASER ON SILICON PHOTONICS PLATFORM
A high-power tunable laser for outputting wavelength tuned laser light includes a gain medium configured to receive light, amplify a light intensity of light in the gain medium and emit light having an amplified light intensity. The gain medium is configured as a reflective semiconductor optical amplifier having a length extending between a backend and a frontend configured as an output port for outputting light having amplified light intensity relative to light that is received at the backend. A wavelength tuner optically coupled to the backend of the gain medium is configured to receive and tune a wavelength of light from the gain medium. The wavelength tuner has a high-reflectivity reflector configured to reflect the light with a tuned wavelength back to the gain medium. The length of the gain medium is dimensioned to amplify light power of light received from the wavelength tuner to output wavelength tune laser light.
H01S 5/026 - Monolithically integrated components, e.g. waveguides, monitoring photo-detectors or drivers
H01S 5/323 - Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- hetero-structures in AIIIBV compounds, e.g. AlGaAs-laser
H01S 5/343 - Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers in AIIIBV compounds, e.g. AlGaAs-laser
H01S 3/10 - Controlling the intensity, frequency, phase, polarisation or direction of the emitted radiation, e.g. switching, gating, modulating or demodulating
31.
METHOD AND APPARATUS FOR TRAINING A FULL-DUPLEX COMMUNICATION LINK
During a training procedure for communicating via a full-duplex communication link, a first communication device receives training information from a second communication device. The training information corresponds to first signal processing parameters developed at the second communication device for use by the second communication device to process signals received by the second communication device via the full-duplex communication link. After receiving the training information from the second communication device, the first communication device develops second signal processing parameters to be used by the first communication device to process signals received by the first communication device via the full-duplex communication link. The second signal processing parameters are developed using the training information received from the second communication device.
A physical layer transceiver for connecting a host device to a wireline channel medium includes a host interface for coupling to the host device, a line interface for coupling to the channel medium, a transmit path operatively coupled to the host interface and the line interface, a receive path operatively coupled to the line interface and the host interface, and adaptive filter circuitry operatively coupled to at least one of the transmit path and the receive path for filtering signals on the at least one of the transmit path and the receive path, the adaptive filter circuitry including a non-linear equalizer. The non-linear equalizer may be a neural network equalizer based on a multi-layer perceptron or a radial- basis function, or may be a linear equalizer with a non- linear activation function. The non-linear equalizer also may have a front-end filter to reduce input complexity.
H04B 3/23 - Reducing echo effects or singing; Opening or closing transmitting path; Conditioning for transmission in one direction or the other using a replica of transmitted signal in the time domain, e.g. echo cancellers
G06N 3/04 - Architecture, e.g. interconnection topology
H04L 25/03 - Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
33.
METHOD AND DEVICE FOR HIGH BANDWIDTH RECEIVER FOR HIGH BAUD-RATE COMMUNICATIONS
An analog front-end (AFE) device and method for a high baud-rate receiver. The device can include an input matching network coupled to a first buffer device, which is coupled to a sampler array. The input matching network can include a first T-coil configured to receive a first input and a second T-coil configured to receive a second input. The first buffer device can include one or more buffers each having a bias circuit coupled to a first class-AB source follower and a second class-AB source follower. The sampling array can include a plurality of sampler devices configured to receive a multi-phase clocking signal. Additional optimization techniques can be used, such as having a multi-tiered sampler array and having the first buffer device configured with separate buffers for odd and even sampling phases. Benefits of this AFE configuration can include increased bandwidth, sampling rate, and power efficiency.
H03F 1/56 - Modifications of input or output impedances, not otherwise provided for
H03F 3/20 - Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
34.
ANALOG RECEIVER EQUALIZER ARCHITECTURES FOR HIGH-SPEED WIRELINE AND OPTICAL APPLICATIONS
The present invention is directed to communication method and techniques. In a specific embodiment, the present invention provides a receiver that interleaves data signal n-ways for n slices. Each of the n slices includes feedforward equalizer and decision feedback equalizers that are coupled to other slices. Each of the n slices also includes an analog-to-digital converter section that includes data and error slicers. There are other embodiments as well.
A transmitter transmits a first signal via a first cable at a first baud rate. A receiver receives a second signal via the first cable concurrently with transmitting the first signal via the first cable. The second signal is transmitted by another device at a second baud rate that is lower than both i) the first baud rate and ii) a third baud rate at which a third signal is being transmitted in a second cable that causes crosstalk in the second signal being received via the first cable. Reception of the second signal at the second baud rate that is lower than the third baud rate facilitates mitigation of the crosstalk in the second signal caused by transmission of the third signal in the second cable at the third baud rate.
A receiver (500) for use in a data channel on an integrated circuit device includes a non-linear equalizer (501) having as inputs digitized samples (521) of signals on the data channel, decision circuitry (501) configured to determine from outputs of the non-linear equalizer a respective value of each of the signals, and adaptation circuitry (573) configured to adapt parameters of the non-linear equalizer based on respective ones of the value. The non-linear equalizer may be a neural network equalizer (541), such as a multi-layer perceptron neural network equalizer, or a reduced complexity multi- layer perceptron neural network equalizer. A method for detecting data on a data channel on an integrated circuit device includes performing non-linear equalization of digitized samples of input signals on the data channel, determining from output signals of the non-linear equalization a respective value of each of the output signals, and adapting parameters of the non-linear equalization based on respective ones of the value.
A physical layer transceiver, for connecting a host device to a wireline channel medium that is divided into a total number of link segments, includes a host interface for coupling to a host device, a line interface for coupling to the wireline channel medium, and feed-forward equalization (FFE) circuitry operatively coupled to the line interface to add back, into a signal, components that were scattered in time. Respective individual filter segments are selectably configurable, by adjustment of respective delay lines, to correspond to respective individual link segments. The FFE circuitry also includes control circuitry configured to detect a signal energy peak in at least one particular link segment and, upon detection of the signal energy peak in the particular link segment, configure a respective one of the respective individual filter segments, by adjustment of a respective delay line, to correspond to the respective particular link segment.
A first communication device generates an Operation, Administration, and Maintenance (OAM) frame that includes i) OAM message content and ii) an OAM frame header outside of the OAM message content, wherein generating the OAM frame comprises generating the OAM frame header to include information that signals one of i) a low power sleep (LPS) request, and ii) a wake-up request (WUR). The first communication device transmits the OAM frame to a second communication device via a communication medium to signal to the second communication device the one of i) the LPS request, and ii) the WUR.
A first communication device performs a handshaking procedure with a second communication device, the handshaking procedure associated with transitioning from an active mode to a low power mode. The first communication device transmits data and/or idle symbols to the second communication device i) after completion of the handshake procedure, and ii) at least until the earlier of a) a time period expiring, and b) determining that the second communication device quieted a transmitter of the second communication device. The first communication device transitions to the low power mode in connection with the handshaking procedure.
A second device receives a first synchronization signal transmitted by a first device for training synchronization between the second device and the first device. The second device then transmits one or more initial synchronization response signals to the first device. The one or more initial synchronization response signals are from among a fixed number of synchronization response signals that the second device is configured to transmit to the first device. After transmission of the one or more initial synchronization response signals, the second device receives a second synchronization signal from the first device. After receiving the second synchronization signal, the second device continues transmission of synchronization response signals to the first device until the fixed number of synchronization response signals are transmitted from the second device to the first device.
A network element (40), for use in an automotive network in a vehicle, includes one or more ports (48), packet processing circuitry (52) and a validation data collector (56). The one or more ports are configured for communicating over the automotive network in the vehicle. The packet processing circuitry is configured to receive packets from the automotive network via the one or more ports, the packets including time-protocol packets, to process the received packets, and to forward the processed packets to the automotive network via the one or more ports. The validation data collector is configured to derive, from at least some of the time-protocol packets that are processed by the packet-processing circuitry, validation data indicative of compliance of the network element with a vehicle-safety requirement, and to make the validation data accessible from outside the network element.
Methods and systems provide for fault diagnosis in a vehicular communication network. The methods and systems utilize a trained neural network model (200) which is downloaded to a local computer (110) associated with the vehicular communication network of a given vehicle and which applies inputs from the given vehicle (100) to output maintenance recommendations for the given vehicle.
G07C 5/08 - Registering or indicating performance data other than driving, working, idle, or waiting time, with or without registering driving, working, idle, or waiting time
43.
METHOD AND APPARATUS FOR BACK END GATHER/SCATTER MEMORY COALESCING
A system for processing gather and scatter instructions can implement a front-end subsystem, a back-end subsystem, or both. The front-end subsystem includes a prediction unit configured to determine a predicted quantity of coalesced memory access operations required by an instruction. A decode unit converts the instruction into a plurality of access operations based on the predicted quantity, and transmits the plurality of access operations and an indication of the predicted quantity to an issue queue. The back-end subsystem includes a load-store unit that receives a plurality of access operations corresponding to an instruction, determines a subset of the plurality of access operations that can be coalesced, and forms a coalesced memory access operation from the subset. A queue stores multiple memory addresses for a given load-store entry to provide for execution of coalesced memory accesses.
A system for processing gather and scatter instructions can implement a front-end subsystem, a back-end subsystem, or both. The front-end subsystem includes a prediction unit configured to determine a predicted quantity of coalesced memory access operations required by an instruction. A decode unit converts the instruction into a plurality of access operations based on the predicted quantity, and transmits the plurality of access operations and an indication of the predicted quantity to an issue queue. The back-end subsystem includes a load-store unit that receives a plurality of access operations corresponding to an instruction, determines a subset of the plurality of access operations that can be coalesced, and forms a coalesced memory access operation from the subset. A queue stores multiple memory addresses for a given load-store entry to provide for execution of coalesced memory accesses.
Embodiments address optimization of an electrical interface between an optical host device and an optical module device at installation time. Certain methods try each entry in a set of Finite Impulse Response (FIR) filter settings at the host transmitter, while asking the module to measure the signal integrity for each. The module will then provide an indication of which entry was the best choice for signal integrity in the current hardware configuration. Note that for the module to host electrical interface, this same technique can be used in reverse, whereby the host asks the module to configure its transmitting FIR filter, and the host records and keeps track of which filter setting is the best, and then configures the module with that filter setting. In both cases, for modules supporting CMIS (Common Management Interface Specification) for module configuration and control, methods are provided.
A multi-chip integrated circuit (IC) apparatus includes a substrate, one or more first IC chips mounted on the substrate, and a second IC chip mounted on the substrate. One or more first heat sinks are respectively thermally coupled to the one or more first IC chips. A second heat sink is thermally coupled to the second IC chip. An under side of the second heat sink is located further from the substrate than each of respective one or more top sides of the one or more first heat sinks.
A physical layer transceiver, for connecting a host device to a wireline channel medium having a cable length, includes a host interface for coupling to a host device, a line interface for coupling to the channel medium, and filter circuitry operatively coupled to the line interface. The filter circuitry includes a plurality of filter segments, fewer in number than a total number of link segments in the cable length. Individual filter segments in the plurality of filter segments are configurable to correspond to individual link segments and are separately controllable from other filter segments. Control circuitry detects a change of transmission conditions in a particular link segment, and upon detection of the change of transmission conditions, changes a configuration of one of the plurality of filter segments to cause an alteration in filtering of signals in the particular link segment at which the change of transmission conditions is detected.
H04B 3/23 - Reducing echo effects or singing; Opening or closing transmitting path; Conditioning for transmission in one direction or the other using a replica of transmitted signal in the time domain, e.g. echo cancellers
H04B 3/32 - Reducing cross-talk, e.g. by compensating
48.
METHODS AND SYSTEMS FOR SECURE NETWORK COMMUNICATION
Methods and systems for executing a communication protocol are provided. One method includes receiving, by a security module of a first computing device, an API call to authenticate a certificate received from a second computing device to establish a communication session between the computing devices; selecting, by the security module, an authentication module to authenticate the certificate; generating, by an encryption module of the security module, a shared secret key for the communication session based on a private key of the first computing device and a public key of the second computing device; encrypting, by the encryption module, the shared secret key using an algorithm negotiated between the first computing device and the second computing device; generating, by the security module, an encrypted message for the second computing device; and transmitting, by the first computing device, the encrypted shared secret key and message to the second computing device.
H04L 9/32 - Arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system
H04L 29/06 - Communication control; Communication processing characterised by a protocol
49.
ON-BOARD INTEGRATED ENCLOSURE FOR ELECTROMAGNETIC COMPATIBILITY SHIELDING
A printed circuit board (PCB) and a method of manufacturing the same is described. The PCB includes a substrate defining a major plane and an integrated electromagnetic interference and compatibility (EMC/EMI) shielding enclosure configured to enclose the substrate. The shielding enclosure includes a metallic top layer deposited on top of the major plane of the substrate so as to envelope an uppermost layer of the substrate, a metallic bottom layer deposited on bottom of the major plane of the substrate so as to envelope a bottommost layer of the substrate, and a metallic side layer formed along a length of one or more edges of the substrate to electrically connect the metallic top layer and the metallic bottom layer.
An automotive Ethernet physical-layer (PHY) transceiver (32) includes an analog Front End (FE - 46) and a digital processor (44). The FE is configured to receive an analog Ethernet signal over a physical Ethernet link (36) while the Ethernet PHY transceiver is operating in a vehicle (24), and to convert the received analog Ethernet signal into a digital signal. The digital processor is configured to hold one or more noise profiles (84) that characterize respective predefined noise types of noise signals that are expected to corrupt the received analog Ethernet signal, to classify an actual noise signal present in the digital signal into one of the noise types, using the noise profiles, and in response to deciding that the actual noise signal matches a given noise type among the predefined noise types, to apply a noise mitigation operation selected responsively to the given noise type.
H04B 3/32 - Reducing cross-talk, e.g. by compensating
H04L 27/144 - Demodulator circuits; Receiver circuits with demodulation using spectral properties of the received signal, e.g. by using frequency selective- or frequency sensitive elements
H04L 27/156 - Demodulator circuits; Receiver circuits with demodulation using temporal properties of the received signal, e.g. detecting pulse width
51.
PCB RF NOISE GROUNDING FOR SHIELDED HIGH-SPEED INTERFACE CABLE
A printed circuit board (PCB) includes a substrate defining a major plane. A first side of the major plane is configured for mounting of functional circuit elements. A cable connector is mounted on a second side of the major plane of the substrate, opposite the first side, for coupling to a shielded radiofrequency (RF) communications cable. At least one component grounding layer is parallel to the major plane and configured for coupling to the functional elements. At least one cable grounding layer is parallel to the major plane and is separated from the at least one component grounding layer. Each cable grounding layer in the at least one cable grounding layer is coextensive with the substrate and is configured for coupling, through the connector, to shielding of the shielded RF communications cable, without coupling to any other component. Nodes of an RF communications system may be mounted on such PCBs.
A physical layer transceiver for a wireline channel medium includes a host interface to a host device, a line interface to the medium, encoding/decoding circuitry for interfacing between the host device and the medium, and adaptive filter circuitry coupled to the encoding/decoding circuitry. The adaptive filter circuitry includes a plurality of filter taps, each corresponding to a segment of the medium, and capable of being powered ON and OFF separately from each other filter tap. Adaptive control circuitry can power ON a first subset, fewer than all the filter taps, corresponding to segments distributed along the medium, monitor powered-ON filter taps for occurrence of interference events, and upon detection of an interference event at a particular segment to which a particular powered-ON filter tap corresponds, power ON one or more additional filter taps corresponding to one or more segments in a vicinity of the particular segment.
H04B 3/23 - Reducing echo effects or singing; Opening or closing transmitting path; Conditioning for transmission in one direction or the other using a replica of transmitted signal in the time domain, e.g. echo cancellers
H04B 3/32 - Reducing cross-talk, e.g. by compensating
53.
INTERFERENCE MITIGATION IN HIGH SPEED ETHERNET COMMUNICATION NETWORKS
Data symbols in an input signal are detected with a slicer of a DFE of a transceiver device. An output of a feedback filter of the DFE is generated, during a particular clock cycle, based on a first set of one or more data symbols detected during first one or more previous clock cycles and a second set of one or more data symbols detected during second one or more previous clock cycles. The second set is separated from the first set by a third set of one or more data symbols detected during third one or more clock cycles that occur after the first one or more clock cycles and before the second one or more clock cycles, where the output is generated without use of the third set of symbols. The output is subtracted from the input signal to generate an equalized input to the slicer.
An automotive data processing system (20) includes a storage subsystem (44) and a processor (48). The storage subsystem is disposed in a vehicle and is configured to store at least data (45) produced by one or more data sources (24, 28, 30, 32, 34) of the vehicle. The processor is installed in a vehicle and is configured to apply, to the data stored in the storage subsystem or that is en route to be stored in the storage subsystem, at least one model that identifies one or more specified features-of-interest in the data, so as to generate metadata (46) that tags occurrences of the specified features-of-interest in the stored data, and to export at least part of the metadata to an external system that is external to the vehicle.
A system and corresponding method alter memory accesses using machine learning. The system comprises a system controller coupled to a processing system that is coupled to a memory system. The system further comprises a learning system coupled to the system controller. The learning system identifies, via a machine learning process, variations on a manner for altering memory access of the memory system to meet at least one goal. The system controller applies the variations identified to the processing system. The machine learning process employs at least one monitored parameter to converge on a given variation of the variations identified and applied. The at least one monitored parameter is affected by the memory access. The given variation enables the at least one goal to be met, improving the processing system, such as by increasing throughput, reducing latency, reducing power consumption, reducing temperature, etc.
G06F 12/0862 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
56.
SYSTEM AND METHOD FOR IMPROVING A PROCESSING SYSTEM
A system and corresponding method improve a processing system. The system comprises a first learning system coupled to a system controller. The first learning system identifies variations for altering processing of a processing system to meet at least one goal. The system controller applies the variations identified to the processing system. The system further comprises a second learning system coupled to the system controller. The second learning system determines respective effects of the variations identified and applied. The first learning system converges on a given variation of the variations based on the respective effects determined. The given variation enables the at least one goal to be met, improving the processing system, such as by increasing throughput, reducing latency, reducing power consumption, reducing temperature, etc.
G06F 12/0862 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
An automotive gateway (44) includes one or more interfaces (56) and one or more processors (52). The one or more interfaces are configured to communicate with electronic subsystems (24, 28, 30, 32, 34) of a vehicle. The one or more processors and configured to host one or more guest applications (48) and to control communication traffic between the one or more guest applications and the electronic subsystems of the vehicle in accordance with a security policy (60).
In a method for establishing a communication link (106) between a first network interface device (102) and a second network interface device (104) comprises, the second network interface device receives a training signal (184) transmitted by the first network interface device. The training signal is for timing synchronization between the second network interface device and the first network interface device. The second network interface device determines, based on at least one physical characteristic of the training signal, a physical layer (PHY) parameter of the first network interface device (194). A controller (198) of the second network interface device configures one or more components of the second network interface device to operate in a mode that corresponds to the determined PHY operating parameter of the first network interface device.
A printed circuit board (PCB) for coupling to an automotive Ethernet connection includes first and second board conduction traces, a first off-board conductor coupled to the first trace at a first contact point spaced from an edge of the PCB, and extending over the PCB from the first contact point to the edge for connection a first off-board conduction path, a second off-board conductor coupled, adjacent to the first off-board conduction path, to the second trace at a second contact point spaced from the edge of the PCB, and extending over the PCB from the second contact point to the edge for connection the second off-board conduction path. The off-board paths are a power path and a signal path. A loop in one of board conduction traces inductively couples that one the board conduction traces to a respective one of off-board conduction paths.
An automotive data storage system (20) disposed in a vehicle includes a packet network and at least one centralized storage device (44). The packet network includes multiple electronic subsystems (24, 28, 30, 32, 34) that are configured to generate data during operation of the vehicle, the electronic subsystems being deployed at different locations in the vehicle and being indirectly coupled to one another via network links (36) and one or more network switches (40). The centralized storage device is installed in the vehicle and coupled to the packet network, and is configured to receive from the electronic subsystems write commands for storing the data, over the packet network, in accordance with a network storage protocol, and to store the data in the centralized storage device.
In a vehicular communication network, a communication device generates a physical layer (PHY) preamble of a PHY protocol data unit (PPDU) for transmission in the vehicular communication network. The communication device generates a plurality of PHY data segments of the PPDU, and one or more PHY midambles, each PHY midamble to be transmitted between a respective pair of adjacent PHY data segments, and each PHY midamble including one or more training signal fields. Generating the one or more PHY midambles includes, when the PPDU is to be transmitted according to an extended range (ER) mode, generating each training signal field to include i) a first portion based on a very high throughput long training field (VHT-LTF) defined by the IEEE 802.11ac Standard and ii) a second portion based on the VHT-LTF defined by the IEEE 802.11ac Standard; and transmitting, by the communication device, the PPDU in the vehicular communication network.
An Ethernet physical layer (PHY) transceiver (20, 24) includes a transmitter (32, 40) and a receiver (36, 44). The transmitter is configured to precode a first data stream by summing two or more mutually-delayed replicas of the first data stream, and to transmit the precoded first data stream over a full-duplex wired channel (28) to a peer Ethernet PHY transceiver. The receiver is configured to receive a second data stream from the peer Ethernet PHY transceiver over the full-duplex wired channel, and to decode the received second data stream while the transmitter concurrently is transmitting the precoded first data stream.
An automotive network switch (32) includes multiple ports (48), a switch core (52) and one or more processors (54, 56). The ports are configured to receive packets from electronic subsystems (28) of a vehicle (24) over a computer network (20) deployed in the vehicle, and to transmit the packets to other electronic subsystems (28) of the vehicle over the computer network. The switch core is configured to receive the packets from one or more of the ports, to forward the packets to at least one of the ports, and to transmit the packets over network links of the computer network. The processors are configured to obtain at least some of the packets processed by the switch, to analyze the obtained packets to identify an anomaly in one or more of the electronic subsystems of the vehicle, and to send a notification of the anomaly over the computer network to a central processor (60) that is external to the switch.
A communication device determines that simultaneous transmission and reception via multiple frequency segments in a WLAN is not permitted. The communication device transmits a first packet in a first frequency segment beginning at a first time, and transmits a second packet in a second frequency segment beginning at a second time that is different than the first time. Transmission of the second packet overlaps in time with transmission of the first packet. In response to having determined that simultaneous transmission and reception via multiple frequency segments is not permitted, the communication device includes in the first packet padding so that an end of transmission of the first packet occurs at a same time as an end of transmission of the second packet.
A wireless communication device generates physical layer (PHY) protocol service data units (PSDUs), and, in response to determining that the PHY data unit is to be transmitted according to a HARQ process, generates HARQ coding units of a common length, each of the HARQ coding units including a respective set of one or more PSDUs, and individually encodes the HARQ coding units. The wireless communication device also generates a HARQ signal field to the included in a PHY preamble of the PHY data unit. The HARQ signal field includes i) a common information subfield to indicate one or more parameters that commonly apply to each of at least some of the one or more HARQ coding units and ii) a respective HARQ coding unit information subfield for each of the HARQ coding units to indicate one or more parameters that apply to only the corresponding HARQ coding unit.
A first communication device determines whether a second communication device is in a power save mode with respect to a first communication link among a plurality of communication links that correspond to respective frequency segments, and determines whether the second communication device is in a power save mode with respect to a second communication link among the plurality of communication links. The second communication device is permitted to be in the power save mode with respect to the second communication link when the second communication device is not in the power save mode with respect to the first communication link, and vice versa. The first communication device communicates with the second communication device in accordance with the power save modes of the second communication device with respect to the first and second communication links.
At least a portion of a physical layer (PHY) preamble of a PHY protocol data unit (PPDU) for transmission in a vehicular communication network is generated to span a first bandwidth a) based on a first orthogonal frequency division multiplexing (OFDM) numerology that is defined for a second bandwidth greater than the first bandwidth and b) down-clocked to generate the at least the portion to span the first bandwidth. The at least the portion includes a legacy portion decodable by a legacy device operating in the network. A data portion is generated based on a second OFDM numerology defined to span the second bandwidth. The PPDU is generated to include the at least the legacy portion of the PHY preamble in a first sub- band, a duplicate of the at least the portion of the preamble in a second sub-band, and the data portion that spans the second bandwidth.
A communication device determines whether simultaneous transmissions in a first frequency segment and a second frequency segment are to be synchronized in time. In response determining that simultaneous transmissions in the first frequency segment and the second frequency segment are to be synchronized in time, the communication device transmits a first packet in the first frequency segment beginning at a first time, and transmits a second packet in the second frequency segment beginning at the first time. In response to determining that simultaneous transmissions in the first frequency segment and the second frequency segment are to be unsynchronized in time, the communication device transmits a third packet in the first frequency segment beginning at a second time, and transmits a fourth packet in the second frequency segment beginning at a third time that is different than the second time.
A first aggregated MAC protocol data unit (A-MPDU) is generated for transmission over a first frequency segment of a communication channel, and a second A-MPDU is generated for transmission over a second frequency segment of the communication channel. A PHY protocol data unit (PPDU) is generated to include the plurality of A-MPDUs and a second PPDU is generated to include the second A-MPDU. A first transmit processor generates a first RF signal for transmission of the first PPDU over the first frequency segment and a second transmit processor generates a second RF signal for transmission of the second PPDU over the second frequency segment. The first RF signal is transmitted in the first frequency segment simultaneously with the second RF signal being transmitted in the second frequency segment.
An Ethernet communication device (32, 38) includes a data interface (40) and circuitry (52, 56, 60, 72, 80, 84). The data interface is configured for communicating with a neighbor device. The circuitry is configured to exchange Ethernet data frames (88) with the neighbor device over the data interface, wherein successive data frames are separated in time by an Inter-Packet Gap (IPG - 92) having at least a predefined minimal duration, and to further exchange with the neighbor device, over the data interface, during the IPG between Ethernet frames exchanged on the data interface, a wake-up/sleep command (96, 100) that instructs switching between an active mode and a sleep mode.
A communication device operates according to a communication protocol defines a first set of frequency resource units (RUs) and a second set of frequency RUs. The first set of frequency RUs includes at least a first subset of frequency RUs having a first bandwidth and a second set of RUs having a second bandwidth greater than the first bandwidth, and the second set of frequency RUs omits at least some of the frequency RUs in the first subset of frequency RUs. The communication device determines that a communication channel to be used for an uplink (UL) multi-user (MU) transmission spans a frequency bandwidth greater than 160 MHz, and allocates one or more frequency RUs for the UL MU transmission, including: in response to determining that the communication channel spans the frequency bandwidth greater than 160 MHz, selecting one or more frequency RUs from a second set of frequency RUs.
A first access point (AP), which is associated with one or more first client stations, generates an announcement frame that announces a coordinated multi-user (MU) transmission involving multiple APs including the first AP and one or more second APs. Each of the second APs is associated with a respective one or more second client stations. The announcement frame is generated to indicate respective one or more frequency resource units (RUs) allocated to the one or more second APs for the coordinated MU transmission. The first AP transmits the announcement frame to the one or more second APs to initiate the coordinated MU transmission, and participates in the coordinated MU transmission while the one or more second APs also participate in the coordinated MU transmission.
The present disclosure describes aspects of constant-density writing for magnetic storage media. In some aspects, a constant-density writer delays transitions between bits within write data to enable constant-density writing. The write data has an initial bit period based on a constant clock signal, which is generated based on the rotation of a media disk. The constant-density writer modifies the write data to generate phase-delayed write data, which has a bit period that is greater than or equal to the initial bit period. To realize this bit period, the constant-density writer changes write phases of bit transitions within the write data. The constant-density writer can also insert stretch bits, filter single-bit transitions, and mitigate glitches within the phase-delayed write data.
G11B 5/596 - Disposition or mounting of heads relative to record carriers with provision for moving the head for the purpose of maintaining alignment of the head relative to the record carrier during transducing operation, e.g. to compensate for surface irregularities of the latter or for track following for track following on disks
A storage device, such as a solid-state drive, is configured to receive messages, such as non-volatile memory networking messages issued by a host processor or computer, that utilize NVM Express over Fabric (NVMe-oF) or NVMe/Transmission Control Protocol communication formatting for transmitting the command over a network fabric. The storage device is configured to terminate the NVMe-oF or NVMe/TCP formatted communication at the storage drive level. The storage device may further be configured to issued reply messages that include NVMe-oF or NVMe/TCP formatting for the communication formatting used to deliver the reply messages over a network fabric.
A first solid state drive (SSD) includes a first built-in network interface device configured to communicate via a network fabric, and a second SSD includes a second built-in network interface device configured to communicate via the network fabric. A connection is opened between the first SSD and the second SSD over the network fabric. Based on a non-volatile memory over fabric (NVMe-oF) communication protocol, an NVMe command to transfer data between the first SSD and the second SSD over the connection is encapsulated in a capsule. The capsule is sent from the first SSD to the second SSD over the connection via the network fabric. The second SSD executes the NVMe command in the capsule to transfer the data between the first SSD and the second SSD over the connection.
A unitary solid state drive (SSD) assembly includes a non-volatile memory (NVM), and a processor communicatively coupled to the NVM. The processor is configured to implement a communication protocol configured for accessing solid state memories over a communication network. The unitary SSD assembly also includes a network interface device communicatively coupled to the processor, and network connector coupled to the network interface device. The network interface device is configured to communicate via a network fabric according to a network communication protocol. The NVM, the processor, and the network interface device are arranged in a unitary assembly.
A first master receives a first virtual address in a virtual memory, the first virtual address m the virtual memory corresponding, according to a mapping function, to a first physical address of a first physical memory bank which is to be accessed by the first master. The first master accesses the first physical address to perform a first memory' operation in the first memory' bank. A second master receives a second virtual address in a virtual memory, the second virtual address m the virtual memory corresponding, according to the mapping function, to a second physical address of a second physical memory bank which is to be accessed by the second master. Concurrently with access by the first master to the first physical address, the second master accesses the second physical address to perform a second memory operation in the second physical memory bank.
The present disclosure describes aspects of cache management of logical-physical translation metadata. In some aspects, a cache (260) for logical-physical translation entries of a storage media system (114) is divided into a plurality of segments (264). An indexer (364) is configured to efficiently balance a distribution of the logical-physical translation entries (252) between the segments (252). A search engine (362) associated with the cache is configured to search respective cache segments (264) and a cache manager (160) may leverage masked search functionality of the search engine (362) to reduce the overhead of cache flush operations.
The present disclosure describes aspects of codeword interleaving for magnetic storage media. In some aspects, segments of a codeword are spread or interleaved across multiple sectors of magnetic storage media. Data for one or more codewords may be received by a read channel and, for each codeword, a respective indicator is selected or received. The indicator may indicate which partitions of the multiple sectors that segments of one of the codewords are to be written. The data is then encoded to provide the codewords and segments of the codewords are placed in an interleaver based on the respective indicator corresponding to the codeword. The codeword segments are written from the interleaver to partitions of the multiple sectors of the magnetic storage media. By so doing, codewords may be spread across multiple sectors, such that a loss of a few sectors does not prevent readback and decoding of the codewords.
Fractional bit storage is disclosed herein which allows for storage of additional bits distributed over multiple SSD cells and maximizes data stored for SSD cells with non -binary amounts of allowable threshold voltages while minimizing required bits dedicated to error correction code (ECC). For an SSD cell with twenty-four levels of threshold voltage, set partitioning is used to create three equal subsets of levels each corresponding to eight levels of threshold voltage and each partitioned subset able to encode three bits. Each partitioned subset is designed with eight allowable threshold voltage ranges, each of which is separated from any other allowable threshold voltage range by at least two of the twenty-four levels of maximum threshold voltage. By choosing both set partitioning and assigning bit values determined via code modulation, bits stored within a partitioned subset are protected without the need for additional ECC.
A solid-state drive (SSD) comprises densely packed memory cells that experience inter-cell interference (ICI) of voltage across memory cells. An ICI block decoder is trained to remove ICI from the voltage stored at memory cells when the SSD is calibrated and retrained periodically as the memory cells degrade. The ICI block decoder learns to predict true bit values (i.e. true voltage values without ICI) at each cell based on measured bit values for nearby cells. In response to read operations for the SSD, the trained ICI block decoder robustly reads memory and recovers the true bit values.
G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
G11C 16/26 - Sensing or reading circuits; Data output circuits
G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
82.
TECHNIQUES ON INPUT TRANSFORMER TO PUSH THE OP1DB HIGHER IN POWER AMPLIFIER DESIGN
A power amplifier includes a first transistor and a first inductor disposed between the first transistor and a voltage source. A first node between the first transistor and the first inductor is an output node. The power amplifier further includes a second inductor disposed between the first transistor and ground. The power amplifier further includes a third inductor coupled to a gate of the first transistor and configured as a first AC input. The power amplifier further includes a first phase conditioner inductively coupled to the second inductor and the third inductor and configured to set phases of AC signals across the first inductor and the second inductor in phase. The second inductor is configured to release energy into the first inductor to raise a voltage of the AC signal and raise a power output at the output node.
H02H 7/20 - Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from norm for electronic equipment
83.
TECHNIQUES TO IMPROVE THE STRESS ISSUE IN CASCODE POWER AMPLIFIER DESIGN
An amplifier includes a first transistor, and a first inductor disposed between the first transistor and a voltage source. A first output node is between the first transistor and the first inductor. The amplifier further includes a second inductor disposed between the first transistor and ground. The amplifier further includes a second transistor, and a third inductor disposed between the second transistor and a ground. A second output node is between the second transistor and the third inductor. The amplifier further includes a fourth inductor disposed between the second transistor and the voltage source. The amplifier further includes a first capacitor disposed between the first output node and the second output node, and a second capacitor disposed between a first mid-node, which is between the first transistor and the first inductor, and a second mid-node, which is between the second transistor and fourth inductor.
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