Marvell Asia PTE, Ltd.

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H04L 1/00 - Arrangements for detecting or preventing errors in the information received 343
H03M 13/00 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes 264
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1.

CABLE ASSEMBLY WITH PROTECTION SWITCHING

      
Application Number 18442848
Status Pending
Filing Date 2024-02-15
First Publication Date 2024-06-06
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Lee, Whay Sing
  • Farhoodfar, Arash

Abstract

The present invention is directed to data communication systems and techniques thereof. In a specific embodiment, the present invention provides a network connector that includes an interface for connecting to a host. The interface includes a circuit for utilizing two data paths for the host. The circuit is configured to transform the host address to different addresses based on the data path being used. There are other embodiments as well.

IPC Classes  ?

  • H04L 61/10 - Mapping addresses of different types
  • H04L 1/00 - Arrangements for detecting or preventing errors in the information received
  • H04L 101/622 - Layer-2 addresses, e.g. medium access control [MAC] addresses

2.

SIMULTANEOUS TRANSMISSION IN MULTIPLE FREQUENCY SEGMENTS

      
Application Number 18440961
Status Pending
Filing Date 2024-02-13
First Publication Date 2024-06-06
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Cao, Rui
  • Zhang, Hongyuan
  • Chu, Liwen
  • Zhang, Yan
  • Lou, Hui-Ling

Abstract

A communication device generates a first packet and a second packet. The first packet includes a first physical layer (PHY) preamble having: a first legacy signal field (L-SIG) having first duration information that indicates a first duration of the first packet; and first non-legacy signal field information having first modulation information that indicates a first modulation used in the first packet. The second packet includes a second PHY preamble having: a second L-SIG having second duration information that indicates a second duration of the second packet, wherein the second duration is different than the first duration; and second non-legacy signal field information having second modulation information that indicates a second modulation used in the second packet, wherein the second modulation is different than the first modulation. The communication device simultaneously transmits the first packet in a first frequency segment and the second packet in a second frequency segment.

IPC Classes  ?

3.

System and Method for Queuing Work within a Virtualized Scheduler Based on In-Unit Accounting of In-Unit Entries

      
Application Number 18434110
Status Pending
Filing Date 2024-02-06
First Publication Date 2024-05-30
Owner Marvell Asia Pte, Ltd. (Singapore)
Inventor
  • Zebchuk, Jason D.
  • Snyder, Ii, Wilson P.

Abstract

A system and corresponding method queue work within a virtualized scheduler based on in-unit accounting (IUA) of in-unit entries (IUEs). The system comprises an IUA resource and arbiter. The IUA resource stores, in association with an IUA identifier, an IUA count and threshold. The IUA count represents a global count of work-queue entries (WQEs) that are associated with the IUA identifier and occupy respective IUEs of an IUE resource. The IUA threshold limits the global count. The arbiter retrieves the IUA count and threshold from the IUA resource based on the IUA identifier and controls, as a function of the IUA count and threshold, whether a given WQE from a given scheduling group, assigned to the IUA identifier, is moved into the IUE resource to be queued for scheduling. The IUA count and threshold prevent group(s) assigned to the IUA identifier from using more than an allocated amount of IUEs.

IPC Classes  ?

  • G06F 9/48 - Program initiating; Program switching, e.g. by interrupt
  • G06F 9/50 - Allocation of resources, e.g. of the central processing unit [CPU]

4.

Method and Apparatus for Controlling Clock Cycle Time

      
Application Number 18434225
Status Pending
Filing Date 2024-02-06
First Publication Date 2024-05-30
Owner Marvell Asia Pte., Ltd. (Singapore)
Inventor
  • Rosen, Eitan
  • Norman, Oded

Abstract

A circuit and corresponding method control cycle time of an output clock used to clock at least one other circuit. The circuit comprises an agile ring oscillator (ARO) and ARO controller. The ARO includes at least one instance of a first ring oscillator (RO) and second RO that generate high and low phases, respectively, of cycles of the output clock. The ARO controller controls durations of the high and low phases, independently, via first and second control words output to the ARO, respectively. In a present cycle of the output clock, the ARO controller effects a change to the high or low phase, or a combination thereof, in a next cycle of the output clock by updating the first or second control word, or a combination thereof, based on an indication of expected usage of the at least one other circuit in the next cycle. The change improves a performance-to-power ratio of the at least one other circuit.

IPC Classes  ?

  • H03L 7/16 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
  • H03K 3/03 - Astable circuits
  • H03K 5/13 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
  • H03L 5/00 - Automatic control of voltage, current, or power
  • H03L 7/099 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop

5.

Method and apparatus for establishing timing to perform link training in ethernet communication based on link quality and/or channel conditions

      
Application Number 18309966
Grant Number 11996906
Status In Force
Filing Date 2023-05-01
First Publication Date 2024-05-28
Grant Date 2024-05-28
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Razavi Majomard, Seid Alireza
  • Tahir, Ehab

Abstract

Systems and methods are described for dynamically updating a duration of link training time for a first stage of link training implemented to set up a first characteristic of a link connection between a physical layer transceiver (PHY) and a link partner. A first stage of link training preconfigured to last for a first duration of time is initiated and a metric of link quality that measures a link connection quality is initiated. Based on the determined metric of link quality, updating the first duration of time for the first stage of link training.

IPC Classes  ?

  • H04B 3/46 - Monitoring; Testing
  • H04B 3/20 - Reducing echo effects or singing; Opening or closing transmitting path; Conditioning for transmission in one direction or the other

6.

Method and apparatus for performing machine learning operations in parallel on machine learning hardware

      
Application Number 17511111
Grant Number 11995448
Status In Force
Filing Date 2021-10-26
First Publication Date 2024-05-28
Grant Date 2024-05-28
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Sodani, Avinash
  • Hanebutte, Ulf
  • Chou, Chien-Chun
  • Hakkarainen, Harri

Abstract

A method includes receiving a first set of data. The method also includes receiving an instruction to determine a largest value within the first set of data. The first set of data is divided into a first plurality of data portions based on a hardware architecture of a first plurality of processing elements. The first plurality of data portions is mapped to the first plurality of processing elements. Each data portion of the first plurality of data portions is mapped exclusively to a processing element of the first plurality of processing elements. Each data portion of the first plurality of data portions is processed by its respective processing element to identify a largest value from each data portion of the first plurality of data portions, wherein the processing forms a first output data comprising the largest value from the each data portion of the first plurality of data portions.

IPC Classes  ?

  • G06F 8/41 - Compilation
  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline, look ahead
  • G06F 15/78 - Architectures of general purpose stored program computers comprising a single central processing unit
  • G06F 17/16 - Matrix or vector computation
  • G06N 20/00 - Machine learning
  • G06N 20/10 - Machine learning using kernel methods, e.g. support vector machines [SVM]
  • G06F 15/80 - Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
  • G06N 5/04 - Inference or reasoning models
  • G06N 20/20 - Ensemble learning

7.

METHODS AND SYSTEMS FOR DATA TRANSMISSION

      
Application Number 18421304
Status Pending
Filing Date 2024-01-24
First Publication Date 2024-05-23
Owner MARVELL ASIA PTE LTD (Singapore)
Inventor
  • Smith, Benjamin
  • Riani, Jamal
  • Farhoodfar, Arash
  • Bhoja, Sudeep

Abstract

An optical transmitter includes a first encoder, a first interleaver, a second encoder, a mapper, a second interleaver, and a frame generator. The first encoder is configured to encode data using a staircase code to generate first codewords. The first interleaver is configured to interleave the first codewords using convolutional interleaving to spread a transmission order of the first codewords. The second encoder is configured to encode the interleaved first codewords using a second code to generate second codewords. The mapper is configured to map the second codewords to transmit symbols. The second interleaver is configured to interleave the transmit symbols to distribute the transmit symbols between pilot symbols. The frame generator is configured to generate a transmit frame including the interleaved transmit symbols and the pilot symbols.

IPC Classes  ?

  • H04L 1/00 - Arrangements for detecting or preventing errors in the information received
  • H03M 13/19 - Single error correction without using particular properties of the cyclic codes, e.g. Hamming codes, extended or generalised Hamming codes
  • H03M 13/25 - Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
  • H03M 13/29 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes

8.

METHOD AND APPARATUS FOR COMMUNICATING INFORMATION VIA PILOT SIGNALS

      
Application Number US2023080130
Publication Number 2024/108029
Status In Force
Filing Date 2023-11-16
Publication Date 2024-05-23
Owner MARVELL ASIA PTE LTD (Singapore)
Inventor Smith, Benjamin P.

Abstract

A first communication device receives control data that are to be communicated to a transceiver of a second communication device, the control data for use by the transceiver to adjust one or more operating parameters of the transceiver. The first communication device encodes the control data on multiple pilot symbols so that each pilot symbol of the multiple pilot symbols encodes less than all of the multiple bits of control data. The first communication device receives information bits that are to be communicated to the second communication device via data symbols, and generates a plurality of data symbols using the information bits. The first communication device transmits the plurality of data symbols and the multiple pilot symbols to the second communication device via a communication medium. When transmitted, the multiple pilot symbols and encoded portions of the multiple bits of control data are interspersed among the plurality of data symbols.

IPC Classes  ?

  • H04L 1/00 - Arrangements for detecting or preventing errors in the information received

9.

METHOD AND APPARATUS FOR CANCELLING FRONT-END DISTORTION

      
Application Number 18403900
Status Pending
Filing Date 2024-01-04
First Publication Date 2024-05-16
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Nguyen, Ray Luan
  • Reyes, Benjamin Tomas
  • Hatcher, Geoffrey
  • Jantzi, Stephen

Abstract

Transceiver circuitry in an integrated circuit device includes a receive path including an analog front end for receiving analog signals from an analog transmission path and conditioning the analog signals, and an analog-to-digital converter configured to convert the conditioned analog signals into received digital signals for delivery to functional circuitry, and a transmit path including a digital front end configured to accept digital signals from the functional circuitry and to condition the accepted digital signals, and a digital-to-analog converter configured to convert the conditioned digital signals into analog signals for transmission onto the analog transmission path. At least one of the analog front end and the digital front end introduces distortion and outputs a distorted conditioned signal. The transceiver circuitry further includes distortion correction circuitry at the one of the analog front end and the digital front end, to determine and apply a distortion cancellation function to the distorted signal.

IPC Classes  ?

10.

METHOD AND APPARATUS FOR COMMUNICATING INFORMATION VIA PILOT SIGNALS

      
Application Number 18511794
Status Pending
Filing Date 2023-11-16
First Publication Date 2024-05-16
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Smith, Benjamin P.
  • Riani, Jamal

Abstract

A first communication device receives control data that are to be communicated to a transceiver of a second communication device, the control data for use by the transceiver to adjust one or more operating parameters of the transceiver. The first communication device encodes the control data on multiple pilot symbols so that each pilot symbol of the multiple pilot symbols encodes less than all of the multiple bits of control data. The first communication device receives information bits that are to be communicated to the second communication device via data symbols, and generates a plurality of data symbols using the information bits. The first communication device transmits the plurality of data symbols and the multiple pilot symbols to the second communication device via a communication medium. When transmitted, the multiple pilot symbols and encoded portions of the multiple bits of control data are interspersed among the plurality of data symbols.

IPC Classes  ?

  • H04L 5/00 - Arrangements affording multiple use of the transmission path

11.

Reinforcement learning-enabled low-density parity check decoder

      
Application Number 18050387
Grant Number 11984910
Status In Force
Filing Date 2022-10-27
First Publication Date 2024-05-14
Grant Date 2024-05-14
Owner Marvell Asia Pte, Ltd. (Singapore)
Inventor
  • Fan, Di
  • Varnica, Nedeljko
  • Lu, Xuanxuan

Abstract

The present disclosure describes apparatuses and methods for implementing a reinforcement learning-enabled low-density parity check (LDPC) decoder. In aspects, an RL-enabled LDPC decoder processes, as part of a first decoding iteration, data of a channel to generate LDPC state information and provides the LDPC state information to a machine learning (ML) algorithm of an RL agent. The RL-enabled LDPC decoder is then configured with LDPC decoding parameters obtained from the ML algorithm and processes, as part of a second decoding operation, the data using the decoding parameters to generate subsequent LDPC state information. The RL-enabled LDPC decoder provides decoded data of the channel based on the subsequent LDPC state information. By using the LDPC decoding parameters provided by the ML algorithm of the RL agent, the RL-enabled LDPC decoder may decode channel data in fewer decoding iterations or with a higher success rate, thereby improving LDPC decoding performance.

IPC Classes  ?

  • H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
  • G06N 3/04 - Architecture, e.g. interconnection topology

12.

Integrated Optical Transceiver

      
Application Number 18380085
Status Pending
Filing Date 2023-10-13
First Publication Date 2024-05-09
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Liang, Ding
  • Patterson, Mark
  • Coccioli, Roberto
  • Nagarajan, Radhakrishnan L.

Abstract

An optical transceiver includes a silicon photonics substrate, transmitter circuitry, and receiver circuitry that are heterogeneously integrated. The transmitter circuitry includes a plurality of laser devices formed on the silicon photonics substrate, each of the plurality of laser devices configured to generate a respective laser light, a plurality of modulators formed on the silicon photonics substrate, each of the plurality of modulators configured to modulate the laser lights based on driver signals and output, from the silicon photonics substrate, the modulated laser lights, and a driver formed on the silicon photonics substrate and configured to generate the driver signals. The receiver circuitry includes a photodetector configured to receive a plurality of optical signals and convert the plurality of optical signals to respective electrical signals and a transimpedance amplifier device configured to receive the electrical signals and output the electrical signals from the silicon photonics substrate as electrical outputs.

IPC Classes  ?

  • B60G 21/05 - Interconnection systems for two or more resiliently-suspended wheels, e.g. for stabilising a vehicle body with respect to acceleration, deceleration or centrifugal forces permanently interconnected mechanically between wheels on the same axle but on different sides of the vehicle, i.e. the left and right wheel suspensions being interconnected
  • B60G 15/02 - Resilient suspensions characterised by arrangement, location, or type of combined spring and vibration- damper, e.g. telescopic type having mechanical spring

13.

Control of Ethernet Link-Partner GPIO using OAM

      
Application Number 18513566
Status Pending
Filing Date 2023-11-19
First Publication Date 2024-05-09
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Mann, Jessica Lauren
  • Mash, Christopher
  • Lau, Timothy See-Hung
  • Fung, Hon Wai
  • Zhu, Liang
  • Wu, Dance

Abstract

An Ethernet Physical layer (PHY) device includes a PHY interface and PHY circuitry. The PHY interface is configured to connect to a physical link. The PHY circuitry is configured to generate layer-1 frames that carry data for transmission to a peer Ethernet PHY device, to insert among the layer-1 frames one or more management frames that are separate from the layer-1 frames and that are configured to control a General-Purpose Input-Output (GPIO) port associated with the peer Ethernet PHY device, to transmit the layer-1 frames and the inserted management frames, via the PHY interface, to the peer Ethernet PHY device over the physical link, for controlling one or more operations of the GPIO port associated with the peer Ethernet PHY device, and to receive, via the PHY interface, one or more verifications acknowledging that the one or more management frames were received successfully at the peer Ethernet PHY device.

IPC Classes  ?

  • H04L 49/351 - Switches specially adapted for specific applications for local area network [LAN], e.g. Ethernet switches
  • H04L 12/40 - Bus networks
  • H04L 12/413 - Bus networks with decentralised control with random access, e.g. carrier-sense multiple-access with collision detection (CSMA-CD)
  • H04L 69/323 - Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions in the physical layer [OSI layer 1]

14.

DISTRIBUTED ARBITRATION FOR SHARED DATA PATH

      
Application Number 18160127
Status Pending
Filing Date 2023-01-26
First Publication Date 2024-05-09
Owner Marvell Asia Pte Ltd (Singapore)
Inventor Drabenstott, Thomas Lorne

Abstract

Passage of data packets on a data pipeline is arbitrated in a distributed manner along the pipeline. Multiple data arbiters each operate to merge data from a respective data source to the data pipeline at a distinct point in the pipeline. At each stage, a multiplexer selectively passes, to the data pipeline, an upstream data packet or a local data packet from the respective data source. A register stores an indication of data packets passed by the multiplexer based on the respective data source originating the data packet. A controller controls the multiplexer to select the upstream data packet or the local data packet based on the indication of data packets passed by the multiplexer.

IPC Classes  ?

  • G06F 13/42 - Bus transfer protocol, e.g. handshake; Synchronisation
  • G06F 9/52 - Program synchronisation; Mutual exclusion, e.g. by means of semaphores

15.

Method and apparatus for compiler and low-level instruction validation of machine learning operations on hardware

      
Application Number 17684940
Grant Number 11977475
Status In Force
Filing Date 2022-03-02
First Publication Date 2024-05-07
Grant Date 2024-05-07
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Chou, Chien-Chun
  • Durakovic, Senad
  • Hanebutte, Ulf
  • Hakkarainen, Harri
  • Chou, Yao
  • Karthikeyan, Veena

Abstract

A system to support validation and debugging of compiled low-level instructions for a machine learning (ML) network model on an ML-specific hardware. A compiler identifies well-defined boundaries in the ML network model based on primitives used to generate low-level instructions for the hardware. The ML network model is partitioned into units/layers/sub-graphs based on the plurality of well-defined boundaries. The compiler then generates an internal representation for each of the units wherein the internal representation is mapped to components in the hardware. Each of the units is compiled into a first set to be executed on the ML-specific hardware and a second set to be executed on a second computing device. The output results from executing the two sets of low-level instructions are compared to validate the first set of low-level instructions. If the outputs do not match fully, the first set of low-level instructions is debugged and recompiled.

IPC Classes  ?

16.

System and method for mining digital currency in a blockchain network

      
Application Number 17817873
Grant Number 11979487
Status In Force
Filing Date 2022-08-05
First Publication Date 2024-05-07
Grant Date 2024-05-07
Owner Marvell Asia Pte, Ltd. (Singapore)
Inventor Carlson, David A.

Abstract

A circuit and corresponding method enable mining for digital currency in a blockchain network. The circuit comprises a controller and at least one partial hash engine that (i) implements a hash function, partially, to compute a partial hash digest of a final hash digest for a block header of a block candidate and (ii) generates a notification based on determining that the partial hash digest satisfies a criterion. The controller includes a complete hash engine that implements the hash function, completely. In response to the notification generated, the controller activates the complete hash engine to compute, in its entirety, the final hash digest for the block header, effectuating a decision for submission of the block candidate with the block header to the blockchain network for mining the digital currency. Power savings and reduction in area are achieved relative to multiple hash engines that compute the entire final hash digest.

IPC Classes  ?

  • H04L 29/06 - Communication control; Communication processing characterised by a protocol
  • G06Q 20/06 - Private payment circuits, e.g. involving electronic currency used only among participants of a common payment scheme
  • G06Q 20/38 - Payment architectures, schemes or protocols - Details thereof
  • G06Q 20/40 - Authorisation, e.g. identification of payer or payee, verification of customer or shop credentials; Review and approval of payers, e.g. check of credit lines or negative lists
  • H04L 9/06 - Arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for blockwise coding, e.g. D.E.S. systems
  • H04L 9/00 - Arrangements for secret or secure communications; Network security protocols

17.

Quieting a wireless local area network

      
Application Number 18114790
Grant Number 11979870
Status In Force
Filing Date 2023-02-27
First Publication Date 2024-05-07
Grant Date 2024-05-07
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Chu, Liwen
  • Chao, Yi-Ling
  • Zhang, Hongyuan
  • Lou, Hui-Ling

Abstract

A first communication device generates and transmits a frame that is configured to cause one or more second communication devices in a wireless local area network (WLAN) to refrain from transmitting during a set of repeating time segments, and the frame is generated to include an indication of a time period of the time segments in the set of repeating time segments, the time period being less than a duration of a beacon interval of the WLAN such that multiple ones of the time segments occur within one beacon interval. Alternatively, the frame is configured to cause one or more second communication devices in the WLAN to refrain from transmitting during a time segment that begins in conjunction with an end of transmission of i) the frame or ii) a packet that includes the frame, and the frame is generated to include an indication of a time duration of the time segment.

IPC Classes  ?

18.

METHODS AND APPARATUS FOR GENERATION OF PHYSICAL LAYER PROTOCOL DATA UNITS FOR VEHICULAR ENVIRONMENTS

      
Application Number 18407159
Status Pending
Filing Date 2024-01-08
First Publication Date 2024-05-02
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Cao, Rui
  • Zhang, Hongyuan
  • Lou, Hui-Ling
  • Zheng, Xiayu

Abstract

A communication device selects a frequency bandwidth via which a physical layer (PHY) protocol data unit (PPDU) will be transmitted in a vehicular communication network, and generates, the PPDU i) according to a downclocking ratio of 1/2, and ii) based on an orthogonal frequency division multiplexing (OFDM) numerology defined by an IEEE 802.11ac Standard. In response to the selected frequency bandwidth being 10 MHz, the PPDU is generated according to the downclocking ratio of 1/2 and based on the OFDM numerology defined by the IEEE 802.11ac Standard for 20 MHz PPDUs. In response to the selected frequency bandwidth being 20 MHz, the PPDU is generated according to the downclocking ratio of 1/2 and based on the OFDM numerology defined by the IEEE 802.11ac Standard for 40 MHz PPDUs.

IPC Classes  ?

  • H04L 27/26 - Systems using multi-frequency codes
  • H04L 5/00 - Arrangements affording multiple use of the transmission path

19.

METHOD AND APPARATUS FOR DETERMINING TIME OF FLIGHT

      
Application Number US2023077443
Publication Number 2024/086811
Status In Force
Filing Date 2023-10-20
Publication Date 2024-04-25
Owner MARVELL ASIA PTE LTD (Singapore)
Inventor
  • Dai, Shaoan
  • Sun, Wensheng
  • Gu, Zhenzhong

Abstract

A first communication device receives an analog receive signal via a communication medium. An ADC of the first communication device converts the analog receive signal to a digital receive signal. Logic circuitry of the first communication device detects a plurality of timing signals from a second communication device based on analyzing the digital receive signal. The logic circuitry adjusts a sampling phase of the ADC in connection with at least some of the timing signals so that the ADC is using different sampling phases when different ones of the timing signals are detected. The logic circuitry determines timing information based on the detection of the plurality of timing signals when the ADC is using different sampling phases when different ones of the timing signals are detected. The first communication device determines a time of flight between the first communication device and the second communication device based on the timing information.

IPC Classes  ?

  • G01S 7/00 - RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES - Details of systems according to groups , ,
  • G01S 13/34 - Systems for measuring distance only using transmission of continuous waves, whether amplitude-, frequency-, or phase-modulated, or unmodulated using transmission of continuous, frequency-modulated waves while heterodyning the received signal, or a signal derived therefrom, with a locally-generated signal related to the contemporaneously transmitted signal
  • H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop

20.

METHOD AND APPARATUS FOR DETERMINING TIME OF FLIGHT

      
Application Number 18382215
Status Pending
Filing Date 2023-10-19
First Publication Date 2024-04-25
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Dai, Shaoan
  • Sun, Wensheng
  • Wu, Xing
  • Gu, Zhenzhong

Abstract

A first communication device receives an analog receive signal via a communication medium. An ADC of the first communication device converts the analog receive signal to a digital receive signal. Logic circuitry of the first communication device detects a plurality of timing signals from a second communication device based on analyzing the digital receive signal. The logic circuitry adjusts a sampling phase of the ADC in connection with at least some of the timing signals so that the ADC is using different sampling phases when different ones of the timing signals are detected. The logic circuitry determines timing information based on the detection of the plurality of timing signals when the ADC is using different sampling phases when different ones of the timing signals are detected. The first communication device determines a time of flight between the first communication device and the second communication device based on the timing information.

IPC Classes  ?

  • H04L 43/106 - Active monitoring, e.g. heartbeat, ping or trace-route using time related information in packets, e.g. by adding timestamps
  • H04L 41/12 - Discovery or management of network topologies

21.

CIRCUIT FOR MULTI-PATH INTERFERENCE MITIGATION IN AN OPTICAL COMMUNICATION SYSTEM

      
Application Number 18393017
Status Pending
Filing Date 2023-12-21
First Publication Date 2024-04-25
Owner MARVELL ASIA PTE LTD (Singapore)
Inventor
  • Smith, Benjamin P.
  • Riani, Jamal
  • Bhoja, Sudeep
  • Farhoodfar, Arash
  • Bhatt, Vipul

Abstract

An optical receiver includes an error generator, a multipath interference estimator, and a combiner. The error generator is configured to receive an input comprising a received optical signal, to estimate a modulation level of samples of the received optical signal, and to generate an error signal based on the estimated modulation level of the samples, the error signal representing a difference between an actual level of the received optical signal and the estimated modulation level. The multipath interference estimator is configured to generate estimates of multipath interference (MPI) associated with the samples of the received optical signal based on the error signal. The combiner is configured to generate an MPI-mitigated signal based on a combination of the samples and the estimates of MPI.

IPC Classes  ?

  • H04B 10/58 - Compensation for non-linear transmitter output
  • H04B 10/00 - Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
  • H04B 10/2507 - Arrangements specific to fibre transmission for the reduction or elimination of distortion or dispersion
  • H04B 10/516 - Transmitters - Details of coding or modulation
  • H04B 10/54 - Intensity modulation
  • H04B 10/69 - Electrical arrangements in the receiver

22.

Methods and apparatus for receiving a user message in a communication network

      
Application Number 17326092
Grant Number 11968065
Status In Force
Filing Date 2021-05-20
First Publication Date 2024-04-23
Grant Date 2024-04-23
Owner Marvell Asia Pte, Ltd. (Singapore)
Inventor Cheon, Hyun Soo

Abstract

Methods and apparatus for receiving a user message in a communication network are disclosed. In an exemplary embodiment, a method includes receiving data samples in an uplink transmission from user equipment, performing preamble detection on the data samples, generating a trigger signal that indicates when a preamble is detected, and decoding a user message in response to the trigger signal, wherein the user message follows the detected preamble.

IPC Classes  ?

  • H04L 27/233 - Demodulator circuits; Receiver circuits using non-coherent demodulation
  • H04B 1/10 - Means associated with receiver for limiting or suppressing noise or interference

23.

Write signal interference cancellation across data/servo clock boundary

      
Application Number 18344472
Grant Number 11967341
Status In Force
Filing Date 2023-06-29
First Publication Date 2024-04-23
Grant Date 2024-04-23
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Katchmart, Supaket
  • Oberg, Mats

Abstract

A method for cancelling, from servo signals read in a read channel while a write channel is active, interference caused by write signals in the write channel, includes generating a predicted channel response signal from the write signals in a data clock domain, resampling the generated predicted channel response signal using a clock in the data clock domain having a rate corresponding to a servo clock from a servo clock domain, transferring the resampled predicted channel response signal from the data clock domain to the servo clock domain and aligning phase of the transferred resampled predicted channel response signal with phase of the servo clock, determining a domain-boundary-crossing delay incurred in the transferring, based on the domain-boundary-crossing delay, synchronizing the phase-aligned transferred resampled predicted channel response signal with the servo signals, and subtracting the synchronized phase-aligned transferred resampled predicted channel response signal from the servo signals.

IPC Classes  ?

  • G11B 5/00 - Recording by magnetisation or demagnetisation of a record carrier; Reproducing by magnetic means; Record carriers therefor
  • G11B 5/012 - Recording on, or reproducing or erasing from, magnetic disks
  • G11B 20/10 - Digital recording or reproducing

24.

REPORTING BANDWIDTH CAPABILITY OF A BANDWIDTH-LIMITED COMMUNICATION DEVICE

      
Application Number 18543786
Status Pending
Filing Date 2023-12-18
First Publication Date 2024-04-18
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Chu, Liwen
  • Wang, Lei
  • Zhang, Hongyuan
  • Sun, Yakun
  • Jiang, Jinjing
  • Lou, Hui-Ling

Abstract

A first communication device generates a first physical layer (PHY) data unit that includes information indicating a capability to use a channel bandwidth greater than a maximum channel bandwidth of the first communication device, and transmits the first PHY data unit to a second communication device during an association process with the second communication device. The first communication device generates a second PHY data unit that includes information indicating a capability to use at most the maximum channel bandwidth of the first communication device, and transmits the second PHY data unit to the second communication device when the first communication device is associated with the second communication device.

IPC Classes  ?

  • H04W 72/21 - Control channels or signalling for resource management in the uplink direction of a wireless link, i.e. towards the network
  • H04W 8/22 - Processing or transfer of terminal data, e.g. status or physical capabilities

25.

SLEEP AND WAKEUP SIGNALING FOR ETHERNET

      
Application Number 18393369
Status Pending
Filing Date 2023-12-21
First Publication Date 2024-04-18
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Leung, Ming-Tak
  • Abedinzadeh, Bizhan
  • Fung, Hon Wai
  • Zhu, Liang
  • Chu, Der-Ren

Abstract

A first communication device generates an Operation, Administration, and Maintenance (OAM) frame that includes i) OAM message content and ii) an OAM frame header outside of the OAM message content, wherein generating the OAM frame comprises generating the OAM frame header to include information that signals one of i) a low power sleep (LPS) request, and ii) a wake-up request (WUR). The first communication device transmits the OAM frame to a second communication device via a communication medium to signal to the second communication device the one of i) the LPS request, and ii) the WUR.

IPC Classes  ?

  • H04L 12/12 - Arrangements for remote connection or disconnection of substations or of equipment thereof
  • G06F 1/3296 - Power saving characterised by the action undertaken by lowering the supply or operating voltage

26.

System and method for large memory transaction (LMT) stores

      
Application Number 17937128
Grant Number 11960727
Status In Force
Filing Date 2022-09-30
First Publication Date 2024-04-16
Grant Date 2024-04-16
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Shreedhar, Aadeetya
  • Zebchuk, Jason D.
  • Snyder, Ii, Wilson P.
  • Ma, Albert
  • Featherston, Joseph

Abstract

A system and corresponding method perform large memory transaction (LMT) stores. The system comprises a processor associated with a data-processing width and a processor accelerator. The processor accelerator performs a LMT store of a data set to a coprocessor in response to an instruction from the processor targeting the coprocessor. The data set corresponds to the instruction. The LMT store includes storing data from the data set, atomically, to the coprocessor based on a LMT line (LMTLINE). The LMTLINE is wider than the data-processing width. The processor accelerator sends, to the processor, a response to the instruction. The response is based on completion of the LMT store of the data set in its entirety. The processor accelerator enables the processor to perform useful work in parallel with the LMT store, thereby improving processing performance of the processor.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers
  • G06F 12/1045 - Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache

27.

Structures and methods for deriving stable physical unclonable functions from semiconductor devices

      
Application Number 17305825
Grant Number 11962709
Status In Force
Filing Date 2021-07-15
First Publication Date 2024-04-16
Grant Date 2024-04-16
Owner Marvell Asia Pte, Ltd. (Singapore)
Inventor
  • Hunt-Schroeder, Eric D.
  • Anand, Darren
  • Pontius, Dale

Abstract

A semiconductor device includes circuitry configured to derive a physical unclonable function. The circuitry includes a plurality of bitcells, each bitcell being readable as one of a ‘0’ value and a ‘1’ value, and sense amplifier circuitry configurable to read values from the plurality of bitcells. The sense amplifier circuitry includes margin circuitry configurable (i) to selectably bias reading of the plurality of bitcells toward one of ‘0’ values and ‘1’ values, (ii) to identify addresses of bitcells having a stable ‘1’ value when the margin circuitry is configured to bias reading of the plurality of bitcells toward ‘0’ values, and (iii) to identify addresses of bitcells having a stable ‘0’ value when the margin circuitry is configured to bias reading of the plurality of bitcells toward ‘1’ values. Each bitcell in the plurality of bitcells may include a differential transistor pair.

IPC Classes  ?

  • H04L 9/32 - Arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system
  • G06F 21/44 - Program or device authentication

28.

PACKET FORMATS FOR VEHICULAR NETWORKS

      
Application Number 18543765
Status Pending
Filing Date 2023-12-18
First Publication Date 2024-04-11
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Zhang, Hongyuan
  • Chu, Liwen

Abstract

A first communication device is configured to process packets that conform to a first physical layer (PHY) protocol for wireless vehicular communications and packets that conform to a second PHY protocol for wireless vehicular communications. The first communication device determines that one or more second communication devices neighboring the first communication device are not capable of processing packets that conform to the second PHY protocol. The first communication device transmits a first packet to a third communication device that is configured to process packets that conform to the first PHY protocol and packets that conform to the second PHY protocol. The first packet indicates that the one or more second communication devices neighboring the first communication device are not capable of processing packets that conform to the second PHY protocol to inform the third communication device of the one or more second communication devices.

IPC Classes  ?

  • H04L 69/323 - Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions in the physical layer [OSI layer 1]
  • H04L 1/00 - Arrangements for detecting or preventing errors in the information received
  • H04L 5/00 - Arrangements affording multiple use of the transmission path
  • H04W 28/02 - Traffic management, e.g. flow control or congestion control
  • H04W 72/044 - Wireless resource allocation based on the type of the allocated resource

29.

MEMORY ALLOCATION AND REALLOCATION FOR PROGRAM INSTRUCTIONS AND DATA USING INTERMEDIATE PROCESSOR

      
Application Number 18544745
Status Pending
Filing Date 2023-12-19
First Publication Date 2024-04-11
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Farhoodfar, Arash
  • Lee, Whay Sing

Abstract

Memory blocks are allocated for a microcontroller having one memory subsystem storing instruction information, and a separate memory subsystem storing data information. At design time, an address map is created implementing configurations of different ways of allocating instruction information and data information between memory blocks. At runtime, a configuration signal is received, and a particular memory block configuration for storing instruction information and data information is determined. An incoming instruction signal received from a dedicated microcontroller port, is communicated according to the configuration signal and the address map to a connection point (e.g., pin, fuse, register). Via that connection point, the instruction signal is routed to a memory block designated exclusively for instructions. Similarly, based upon the configuration signal and the address map, an incoming data signal (received from another dedicated microcontroller port), is routed via a connection point to a different memory block designated to store exclusively data information.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

30.

DECODING FEC CODEWORDS USING LDPC CODES DEFINED BY A PARITY CHECK MATRIX WHICH IS DEFINED BY RPC AND QC CONSTRAINTS

      
Application Number 18377647
Status Pending
Filing Date 2023-10-06
First Publication Date 2024-04-11
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Morero, Damian Alfonso
  • Castrillon, Mario Alejandro
  • Schnidrig, Matias German
  • Hueda, Mario Rafael

Abstract

A decoder for a receiver in a communication system includes an interface configured to receive encoded input data via a communication channel. The encoded input data includes forward error correction (FEC) codewords. A processor is configured to decode the FEC codewords using low density parity check (LDPC) codes defined by a parity check matrix. The parity check matrix is defined by both regular column partition (RCP) constraints and quasi-cyclic (QC) constraints. An output circuit is configured to output a decoded codeword based on the FEC codewords decoded by the processor.

IPC Classes  ?

  • H03M 13/00 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
  • H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits

31.

System and Method for Neural Network-Based Autonomous Driving

      
Application Number 18541463
Status Pending
Filing Date 2023-12-15
First Publication Date 2024-04-11
Owner Marvell Asia Pte, Ltd. (Singapore)
Inventor Ladd, William Knox

Abstract

A system and corresponding method for autonomous driving of a vehicle are provided. The system comprises at least one neural network (NN) that generates at least one output for controlling the autonomous driving. The system further comprises a main data path that routes bulk sensor data to the at least one NN and a low-latency data path with reduced latency relative to the main data path. The low-latency data path routes limited sensor data to the at least one NN which, in turn, employs the limited sensor data to improve performance of the at least one NN's processing of the bulk sensor data for generating the at least one output. Improving performance of the at least one NN's processing of the bulk sensor data enables the system to, for example, identify a safety hazard sooner, enabling the autonomous driving to divert the vehicle and avoid contact with the safety hazard.

IPC Classes  ?

32.

Apparatus and Techniques for Contextual Search of a Storage System

      
Application Number 18541867
Status Pending
Filing Date 2023-12-15
First Publication Date 2024-04-04
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Kudryavtsev, Konstantin
  • Oberg, Mats
  • Varnica, Nedeljko

Abstract

The present disclosure describes apparatuses and methods for contextual search of a storage system. In some aspects, a metadata manager of a storage system receives a query to search the data stored on the storage media of the apparatus. The metadata manager identifies an entry in a relational database of the metadata manager that includes a label that is relevant to the query and determines, based on the entry in the relational database, a reference address of a target node in a navigational database of the metadata manager that corresponds to the label. As results for the query to search, the metadata manager returns an object of the target node at the reference address in the navigational database and corresponding objects of relative nodes connected to the target node via respective links. By so doing, the metadata database may enable contextual or implicit search of data in the storage system.

IPC Classes  ?

  • G06F 16/2457 - Query processing with adaptation to user needs
  • G06F 16/22 - Indexing; Data structures therefor; Storage structures
  • G06F 16/28 - Databases characterised by their database models, e.g. relational or object models
  • G06N 20/00 - Machine learning

33.

Physical layer transceiver with increased noise and interference tolerance and reduced loss

      
Application Number 17677863
Grant Number 11943083
Status In Force
Filing Date 2022-02-22
First Publication Date 2024-03-26
Grant Date 2024-03-26
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Dai, Shaoan
  • Sun, Wensheng
  • Wu, Xing

Abstract

Methods, PHYs, and computer-readable media are provided for reliably receiving data at a physical layer transceiver of an automobile in the presence of noise or interference. A non-equalized signal is received at a physical layer transceiver via a communication channel in a high noise or interference automotive environment. The non-equalized signal is prepared for extraction of data by performing one or more of the following: improving a signal-to-noise ratio of the non-equalized signal by using two or more parallel matching filters to correlate the non-equalized signal with two or more signal templates to detect the presence of logic low signal patterns and logic high signal patterns in the non-equalized signal; reducing jitter in the non-equalized signal by tracking a phase of the non-equalized signal using a digital timing loop; compensating for noise or interference distortion in the non-equalized signal by selecting a decision sample defined by a plurality of peaks, the selecting performed based on tracking peaks in the non-equalized signal; searching the non-equalized signal for a preamble before initiating a process of receiving payload data, to reduce false data reception caused by noise or interference; and extracting data from the prepared non-equalized signal.

IPC Classes  ?

  • H04L 25/497 - Transmitting circuits; Receiving circuits using three or more amplitude levels by correlative coding, e.g. partial response coding or echo modulation coding
  • H04L 25/49 - Transmitting circuits; Receiving circuits using three or more amplitude levels

34.

Generic cryptography wrapper

      
Application Number 17323263
Grant Number 11943367
Status In Force
Filing Date 2021-05-18
First Publication Date 2024-03-26
Grant Date 2024-03-26
Owner Marvell Asia Pte, Ltd. (Singapore)
Inventor
  • Saravanan, Dhanalakshmi
  • Nemalipuri, Raga Sruthi
  • Ainapur, Priya
  • Raveendra, K.
  • Hinge, Bapu

Abstract

An apparatus for performing cryptographic primitives includes a processor that is configured to receive an instruction to perform a cryptographic primitive, where the instruction includes one or more operands, at least one of the operands indicates one or more data structures that include values for the cryptographic primitive, and where the values include a first value indicating a mode of encryption that indicates an order of performing an encryption operation and an authentication operation and a second value indicating a cipher type; and perform the cryptographic primitive and store an output of the cryptographic primitive in an output data structure.

IPC Classes  ?

  • H04L 29/06 - Communication control; Communication processing characterised by a protocol
  • H04L 9/06 - Arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for blockwise coding, e.g. D.E.S. systems
  • H04L 9/08 - Key distribution
  • H04L 9/32 - Arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system

35.

EXPLICIT BEAMFORMING IN A HIGH EFFICIENCY WIRELESS LOCAL AREA NETWORK

      
Application Number 18520523
Status Pending
Filing Date 2023-11-27
First Publication Date 2024-03-21
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Cao, Rui
  • Zhang, Hongyuan

Abstract

A first communication device receives a sounding packet from a second communication device and develops beamforming information based on the sounding packet. The first communication device transmits beamforming feedback to the second communication device, the beamforming feedback including beamforming information for use by the second communication device to beamsteer a data packet to the first communication device, the data packet having a data portion that includes a second number of OFDM tones greater than a first number of OFDM tones in the sounding packet. After transmitting the beamforming feedback, the first communication device receives the data packet from the second communication device, the data packet including one or more data OFDM symbols, each of the one or more data OFDM symbols having the second number of OFDM tones.

IPC Classes  ?

  • H04B 7/0417 - Feedback systems
  • H04B 7/0456 - Selection of precoding matrices or codebooks, e.g. using matrices for antenna weighting
  • H04B 7/06 - Diversity systems; Multi-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station
  • H04L 5/00 - Arrangements affording multiple use of the transmission path
  • H04W 16/28 - Cell structures using beam steering

36.

Multi-Termination Scheme Interface

      
Application Number 18524662
Status Pending
Filing Date 2023-11-30
First Publication Date 2024-03-21
Owner Marvell Asia Pte, Ltd. (Singapore)
Inventor Wang, Lu

Abstract

In an embodiment, a method includes programming a control signal that specifies a target resistance and a target voltage in a circuit. The method further includes sending the control signal to at least one transistor configured to control a current flow in the circuit. The method further includes providing, as an output, a signal with the target voltage and target resistance.

IPC Classes  ?

  • H03K 19/00 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
  • H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits

37.

MANAGING POWER IN AN ELECTRONIC DEVICE

      
Application Number 17745092
Status Pending
Filing Date 2022-05-16
First Publication Date 2024-03-21
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Matthews, William Brad
  • Kwan, Bruce H.

Abstract

A network device accesses, from a queue corresponding to a port of the device, a packet for processing. The device identifies a present operating region (ORE) of one or more OREs specified for the device, an ORE being associated with at least one of (i) one or more device attributes, or (ii) one or more environmental factors associated with an environment in which the device is operational. The device determines a number of power credits available for processing one or more packets. In response to determining that the number of power credits available is non-negative, the device completes processing of the packet. The device computes, based at least on the present ORE, a power credit reduction for the packet, which corresponds to an amount of power for processing the packet, and reduces the number of power credits available by the power credit reduction for the packet.

IPC Classes  ?

  • G06F 1/3296 - Power saving characterised by the action undertaken by lowering the supply or operating voltage
  • H04L 49/90 - Buffering arrangements

38.

WIRELINE TRANSCEIVER WITH INTERNAL AND EXTERNAL CLOCK GENERATION

      
Application Number 18514479
Status Pending
Filing Date 2023-11-20
First Publication Date 2024-03-21
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Cai, Li
  • Chong, Sau Siong
  • Loi, Chang-Feng
  • Tse, Lawrence

Abstract

An integrated circuit device having functional circuitry driven by a clock signal includes onboard clock generation circuitry. The clock generation circuitry includes an input configured to accept a frequency reference signal, at least one variable loading capacitor coupled to the input for converting the crystal resonator signal into a calibrated clock signal, and calibration circuitry configured to calibrate the at least one variable loading capacitor based on a reference voltage. The input configured to accept a frequency reference signal may be configured to accept a crystal resonator signal.

IPC Classes  ?

  • G06F 1/08 - Clock generators with changeable or programmable clock frequency
  • G06F 1/10 - Distribution of clock signals
  • G06F 1/12 - Synchronisation of different clock signals

39.

Digital timing recovery for constant density servo read operations

      
Application Number 18157585
Grant Number 11935561
Status In Force
Filing Date 2023-01-20
First Publication Date 2024-03-19
Grant Date 2024-03-19
Owner Marvell Asia Pte Ltd (Singapore)
Inventor Katchmart, Supaket

Abstract

A method of reading servo wedge data from a rotating constant-density magnetic storage medium having a plurality of tracks, where each track is written at a track pattern frequency, the respective track pattern frequencies varying from a lowest frequency at an innermost one of the tracks to a highest frequency at an outermost one of the tracks, includes, for each respective track, determining, based on the pattern frequency of the respective track, a desired sampling position, sampling actual samples of servo wedge data based on a sampling clock used for all tracks, having a sampling frequency at least equal to the track pattern frequency of the outermost track, determining a phase relationship of the desired sampling position to the sampling clock, and, depending on the phase relationship between the sampling position and the sampling clock, interpolating a sample, or omitting interpolation of a sample and squelching the interpolation clock.

IPC Classes  ?

  • G11B 5/09 - Digital recording
  • G11B 20/10 - Digital recording or reproducing
  • G11B 20/14 - Digital recording or reproducing using self-clocking codes

40.

Dual-surface RRO write in a storage device servo system

      
Application Number 18066394
Grant Number 11935571
Status In Force
Filing Date 2022-12-15
First Publication Date 2024-03-19
Grant Date 2024-03-19
Owner Marvell Asia Pte Ltd (Singapore)
Inventor Katchmart, Supaket

Abstract

A method for writing repeatable run-out (RRO) data, to surfaces of a rotating magnetic storage medium in a storage device having two read channels, includes detecting, with a first head, using a first read channel, a servo sync mark (SSM) on a first track on a first surface, establishing a recurring servo-gating signal at a successive fixed interval from the SSM, detecting, with the first head, servo signals from the first track on occurrence of the recurring servo-gating signal, processing the servo signals from the first track, to generate first positioning signals for positioning the first head relative to the first track, following a similar procedure with a second read channel having a second head to generate second positioning signals for the second read head, and writing first and second RRO data to servo wedges of the first and second tracks according to the respective positioning signals.

IPC Classes  ?

  • G11B 5/596 - Disposition or mounting of heads relative to record carriers with provision for moving the head for the purpose of maintaining alignment of the head relative to the record carrier during transducing operation, e.g. to compensate for surface irregularities of the latter or for track following for track following on disks

41.

Reduction of four-wave mixing crosstalk in optical links

      
Application Number 18462470
Status Pending
Filing Date 2023-09-07
First Publication Date 2024-03-14
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Mak, Gary
  • Patra, Lenin Kumar
  • Riani, Jamal

Abstract

A transmitter includes at least three tunable laser sources, an optical multiplexer, and a processor. The at least three tunable laser sources are configured to receive respective data streams, and to output respective Tx light beams at different respective carrier frequencies, modulated with the respective data streams. The optical multiplexer is configured to combine the multiple Tx light beams to produce a combined beam formed of the modulated Tx light beams at the different carrier frequencies, and to transmit the combined beam over an optical fiber. The processor is configured to receive a notification indicative of an interference occurring due to Four-Wave Mixing (FWM) in the optical fiber, and to modify at least one of the carrier frequencies responsively to the notification in order to mitigate the interference due to FWM.

IPC Classes  ?

  • H04B 10/50 - Transmitters
  • G02B 6/293 - Optical coupling means having data bus means, i.e. plural waveguides interconnected and providing an inherently bidirectional system by mixing and splitting signals with wavelength selective means
  • H04B 10/2563 - Four-wave mixing [FWM]
  • H04J 14/02 - Wavelength-division multiplex systems

42.

INTEGRATED COHERENT OPTICAL TRANSCEIVER

      
Application Number 18502449
Status Pending
Filing Date 2023-11-06
First Publication Date 2024-03-14
Owner Marvell Asia Pte Ltd (Singapore)
Inventor Nagarajan, Radhakrishnan L.

Abstract

An integrated circuit includes a silicon photonics substrate having a silicon-based material, silicon photonics components formed in the silicon photonics substrate to receive and transmit optical signals, and electrical connections; a transimpedance amplifier chip arranged on the silicon photonics substrate, having a silicon-germanium material that is different than the silicon-based material, connected via the electrical connections to at least one of the silicon photonics components configured to receive an optical signal, and configured to process a received optical signal and output a processed signal to a digital signal processor; and a driver chip arranged on the silicon photonics substrate, having CMOS material that is different than the silicon-germanium material and the silicon-based material, connected via the electrical connections to drive at least one of the silicon photonics components configured to generate an optical signal for transmission.

IPC Classes  ?

  • H04B 10/40 - Transceivers
  • G02B 6/12 - Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
  • G02B 6/126 - Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind using polarisation effects
  • G02B 6/42 - Coupling light guides with opto-electronic elements
  • H01S 3/13 - Stabilisation of laser output parameters, e.g. frequency or amplitude
  • H01S 5/00 - Semiconductor lasers
  • H01S 5/0234 - Up-side down mountings, e.g. Flip-chip, epi-side down mountings or junction down mountings
  • H01S 5/02375 - Positioning of the laser chips

43.

EFFICIENT SIGNALING SCHEME FOR HIGH-SPEED ULTRA SHORT REACH INTERFACES

      
Application Number 18512744
Status Pending
Filing Date 2023-11-17
First Publication Date 2024-03-14
Owner MARVELL ASIA PTE LTD (Singapore)
Inventor
  • Farjadrad, Ramin
  • Langner, Paul

Abstract

A multi-chip package includes first and second groups of integrated circuit (IC) chips and a transfer IC chip disposed in the multi-chip package. The transfer IC chip is communicatively interposed between the first and second groups of IC chips and is configured to transfer signals from at least a first IC chip of the first group of IC chips to at least a second IC chip of the second group of IC chips or an output interface. The output interface is configured to output first data from the multi-chip package. A first set of ultra-short reach (USR) signaling links connects the first group of IC chips to the transfer IC chip. A second set of USR signaling links connects the second group of IC chips to the transfer IC chip. Each of the USR signaling links comprises a trace length of less than one inch.

IPC Classes  ?

  • G06F 13/36 - Handling requests for interconnection or transfer for access to common bus or bus system
  • H04L 7/00 - Arrangements for synchronising receiver with transmitter
  • H04L 25/20 - Repeater circuits; Relay circuits

44.

GATE STACK FOR METAL GATE TRANSISTOR

      
Application Number 18514146
Status Pending
Filing Date 2023-11-20
First Publication Date 2024-03-14
Owner Marvell Asia Pte, Ltd. (Singapore)
Inventor Chang, Runzi

Abstract

Forming a metal gate transistor includes forming a semiconductor channel in a substrate, and depositing a source electrode and a drain electrode on the semiconductor channel. The source and drain electrodes are spaced apart. Dielectric spacers are provided above the source and drain electrodes to define a gate void spanning the source and drain electrodes. A dielectric layer is deposited on a bottom wall and sidewalls of the gate void. A work-function metal layer is deposited on the dielectric layer. The work-function metal layer is etched away from the sidewalls leaving the work-function metal layer on the bottom wall to control work function between the semiconductor channel and a conductive metal gate material to be deposited. The gate void above the work-function metal layer on the bottom wall, and between the dielectric layers on the sidewalls, is filled with the conductive metal gate material.

IPC Classes  ?

  • H01L 29/40 - Electrodes
  • H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
  • H01L 29/49 - Metal-insulator semiconductor electrodes
  • H01L 29/66 - Types of semiconductor device

45.

Semiconductor device with mechanism to prevent reverse engineering

      
Application Number 17845606
Grant Number 11928248
Status In Force
Filing Date 2022-06-21
First Publication Date 2024-03-12
Grant Date 2024-03-12
Owner Marvell Asia Pte Ltd (Singapore)
Inventor Hunt-Schroeder, Eric

Abstract

A semiconductor device is configured to implement a security protocol. The semiconductor device includes an entropy source that includes a plurality of bitcells. The entropy source is configured to output a sequence of physical unclonable function bit values based on intrinsic properties of the plurality of bitcells to generate a unique device secret for the security protocol, and selectively damage at least a portion of the plurality of bitcells to prevent reverse engineering the sequence of physical unclonable function bit values.

IPC Classes  ?

  • G06F 21/71 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
  • G06F 21/14 - Protecting executable software against software analysis or reverse engineering, e.g. by obfuscation

46.

Circuit and method for resource arbitration

      
Application Number 17932084
Grant Number 11929940
Status In Force
Filing Date 2022-09-14
First Publication Date 2024-03-12
Grant Date 2024-03-12
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Featherston, Joseph
  • Shreedhar, Aadeetya

Abstract

A circuit and corresponding method perform resource arbitration. The circuit comprises a pending arbiter (PA) that outputs a PA selection for accessing a resource. The PA is selection based on PA input. The PA input represents respective pending-state of requesters of the resource. The circuit further comprises a valid arbiter (VA) that outputs a VA selection for accessing the resource. The VA selection is based on VA input. The VA input represents respective valid-state of the requesters. The circuit performs a validity check on the PA selection output. The circuit outputs a final selection for accessing the resource by selecting, based on the validity check performed, the PA selection output or VA selection output. The circuit addresses arbitration fairness issues that may result when multiple requesters are arbitrating to be selected for access to a shared resource and such requesters require a credit (token) to be eligible for arbitration.

IPC Classes  ?

  • G06F 13/36 - Handling requests for interconnection or transfer for access to common bus or bus system
  • H04L 47/783 - Distributed allocation of resources, e.g. bandwidth brokers
  • H04L 47/80 - Actions related to the user profile or the type of traffic

47.

Digital droop detector

      
Application Number 18048018
Grant Number 11927612
Status In Force
Filing Date 2022-10-19
First Publication Date 2024-03-12
Grant Date 2024-03-12
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Knoll, Ernest
  • Yassur, Omer

Abstract

A circuit detects a voltage droop exhibited by a power supply. A first signal delay line outputs a first delayed signal, and is comprised of delay elements having a first threshold voltage. A second delay line outputs a second delayed signal, and is comprised of delay elements having a second threshold voltage that is higher than the first threshold voltage. A phase detector compares the first and second delayed signals and outputs a comparison signal indicating which of the first and second signal delay lines exhibits a shorter delay. A reset circuit resets the first and second signal delay lines in response to the comparison signal, and a clock controller outputs a command to adjust a clock frequency or engage in other mitigation measures based on the comparison signal.

IPC Classes  ?

  • G01R 25/00 - Arrangements for measuring phase angle between a voltage and a current or between voltages or currents
  • H03K 5/14 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of delay lines
  • H03L 7/00 - Automatic control of frequency or phase; Synchronisation

48.

System and method for schedule-based I/O multiplexing for integrated circuit (IC) scan test

      
Application Number 17500453
Grant Number 11927630
Status In Force
Filing Date 2021-10-13
First Publication Date 2024-03-12
Grant Date 2024-03-12
Owner Marvell Asia Pte Ltd (Singapore)
Inventor Biswas, Sounil

Abstract

An approach is proposed to support schedule-based I/O multiplexing for scan testing of an IC. A plurality of I/Os are assigned to a plurality of blocks in the IC for scan testing based on a set of slots under a set of schedules. Each of the set of slots includes a fixed number of scan input pins/pads and scan output pins/pads of the IC. Each slot is then assigned to a specific block on the IC for the scan test until all of the slots available are utilized. The group of assigned blocks is referred to as a schedule, and all of these blocks belonging to this schedule are scan tested in parallel at the same time. The remaining blocks on the IC are also assigned to the slots until all blocks on the IC are assigned to a schedule to be scan tested.

IPC Classes  ?

  • G01R 31/3177 - Testing of logic operation, e.g. by logic analysers
  • G01R 31/317 - Testing of digital circuits
  • G01R 31/3185 - Reconfiguring for testing, e.g. LSSD, partitioning
  • G01R 31/319 - Tester hardware, i.e. output processing circuits
  • G06F 30/34 - Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
  • G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
  • G11C 11/4093 - Input/output [I/O] data interface arrangements, e.g. data buffers
  • G11C 11/4096 - Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches

49.

OUT-OF-BAND BASED INDEPENDENT LINK TRAINING OF IN-BAND LINKS BETWEEN HOST DEVICES AND OPTICAL MODULES

      
Application Number US2023031613
Publication Number 2024/049950
Status In Force
Filing Date 2023-08-31
Publication Date 2024-03-07
Owner
  • MARVELL ASIA PTE LTD (Singapore)
  • MARVELL SEMICONDUCTOR INC. (USA)
Inventor
  • Lee, Whay Sing
  • Rope, Todd

Abstract

A first optical module includes an optical transceiver and a chip. The optical transceiver, subsequent to completion of link training of an in-band transmission link between the first optical module and a host device, waits for a second optical module to come up including transmitting a first awake signal from the first optical module to the second optical module, and receives a second awake signal from the second optical module when the second optical module is up. The chip i) based on a first out-of-band signal transmitted via an out-of-band link, performs the link training of the in-band transmission link independently of an in-band reception link between the first optical module and the host device, and ii) based on the second awake signal and a second out-of-band signal transmitted via the out-of-band link, performs link training of the in-band reception link independent of the in-band transmission link.

IPC Classes  ?

  • H04B 10/079 - Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems using an in-service signal using measurements of the data signal
  • H04B 10/077 - Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems using an in-service signal using a supervisory or additional signal
  • H04B 10/80 - Optical aspects relating to the use of optical transmission for specific applications, not provided for in groups , e.g. optical power feeding or optical transmission through water

50.

OUT-OF-BAND BASED INDEPENDENT LINK TRAINING OF IN-BAND LINKS BETWEEN HOST DEVICES AND OPTICAL MODULES

      
Application Number 18239819
Status Pending
Filing Date 2023-08-30
First Publication Date 2024-03-07
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Lee, Whay Sing
  • Rope, Todd

Abstract

A first optical module includes an optical transceiver and a chip. The optical transceiver, subsequent to completion of link training of an in-band transmission link between the first optical module and a host device, waits for a second optical module to come up including transmitting a first awake signal from the first optical module to the second optical module, and receives a second awake signal from the second optical module when the second optical module is up. The chip i) based on a first out-of-band signal transmitted via an out-of-band link, performs the link training of the in-band transmission link independently of an in-band reception link between the first optical module and the host device, and ii) based on the second awake signal and a second out-of-band signal transmitted via the out-of-band link, performs link training of the in-band reception link independent of the in-band transmission link.

IPC Classes  ?

51.

GATE ALL-AROUND (GAA) FIELD EFFECT TRANSISTORS (FETS) FORMED ON BOTH SIDES OF A SUBSTRATE

      
Application Number IB2023058399
Publication Number 2024/047479
Status In Force
Filing Date 2023-08-24
Publication Date 2024-03-07
Owner MARVELL ASIA PTE LTD (Singapore)
Inventor Chang, Runzi

Abstract

An electronic device (11) includes a substrate (55), first and second semiconductor devices (22, 33), and a power supply structure (88b). The first semiconductor device (22) includes a first plurality of gate all-around (GAA) field effect transistors (FETs) (44) formed over a first side (25) of substrate (55). The second semiconductor device (33) includes a second plurality of GAA FETs (44) formed over a second side (35) of substrate (55), opposite first side (25). The power supply structure (88b) is (a) disposed at the first side (25), and (b) configured to supply power to one or more of: (i) the first plurality of GAA FETs (44) through first electrical couplings (77) disposed at the first side (25), and (ii) the second plurality of GAA FETs (44) through second electrical couplings (77) including inter-side vias (ISVs) (66) traversing the substrate (55) from the second side (35) to the first side (35).

IPC Classes  ?

  • H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
  • H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
  • H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
  • H01L 21/8234 - MIS technology
  • H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
  • H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body

52.

System and methods for firmware security mechanism

      
Application Number 16947424
Grant Number 11921904
Status In Force
Filing Date 2020-07-31
First Publication Date 2024-03-05
Grant Date 2024-03-05
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Sundararaman, Ramacharan
  • Miyar, Nithyananda
  • Kovac, Martin

Abstract

A new approach is proposed to support a hardware-based lock mechanism having a hardware-based lock unit associated with a resource, wherein the lock is utilized by an arbitrator to arbitrate between multiple agents requesting access to the resource. When a first agent requests access to resource in unlocked state, the arbitrator creates a lock ID and set a locked state indicating that the resource is locked. The lock ID is provided to the first agent, which now has exclusive control over the resource. The arbitrator ensures that any agent with the same ID may access the resource. When a second agent requests access to the resource with a lock ID to the arbitrator, it is granted access to the resource if the lock ID provided matches the one stored on the lock unit. If there is a mismatch between the lock IDs, access to the resource is denied.

IPC Classes  ?

  • G06F 21/71 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
  • G06F 8/65 - Updates

53.

Multi-port transceiver

      
Application Number 17744478
Grant Number 11923978
Status In Force
Filing Date 2022-05-13
First Publication Date 2024-03-05
Grant Date 2024-03-05
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Ghazali, Sabu
  • Patra, Lenin
  • Chen, Jeng-Jong Douglas
  • Youm, Dong-Seok
  • Tsai, Tunghao
  • Susanto, Kong Chuan

Abstract

A multi-port transceiver comprises a plurality of first ports, a first communication interface, and a second communication interface. Multi-rate interleaver circuitry interleaves i) a plurality of first data streams, each received via a respective first port at a first data rate, and ii) a second data stream received via the first communication interface at a second data rate, to generate a third data stream to be transmitted via the second communication interface at a third data rate. Multi-rate deinterleaver circuitry deinterleaves a fourth data stream that was received via the second communication interface at the third data rate into i) a plurality of fifth data streams, each fifth data stream to be transmitted via a respective first port at the first data rate, and ii) a sixth data stream to be transmitted via the first communication interface at the second data rate.

IPC Classes  ?

  • H04L 1/00 - Arrangements for detecting or preventing errors in the information received
  • H04B 1/40 - Circuits
  • H04L 49/00 - Packet switching elements

54.

Method and apparatus for control of congestion in storage area network

      
Application Number 17661174
Grant Number 11924105
Status In Force
Filing Date 2022-04-28
First Publication Date 2024-03-05
Grant Date 2024-03-05
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Sundar, Gourangadoss
  • Easi, Arun
  • Basrur, Girish

Abstract

In a storage area network operating in accordance with a transport-level protocol to interconnect host and target devices, where the transport-level protocol issues congestion notifications when any of the host or target devices becomes congested, a method for reducing congestion includes, on receipt of a request to (a) write data to one of the target devices or (b) read data from one of the target devices for return to one of the host devices, (A) determining whether congestion already exists at (a) the target device to which the write request is directed, or (b) the host device to which data from the read request is to be returned, and (B) when a congestion state already exists, comparing current depth of a queue of write or read requests to a maximum permissible queue depth. When the current depth of the queue exceeds a maximum permissible queue depth, the request is rejected.

IPC Classes  ?

  • H04L 47/12 - Avoiding congestion; Recovering from congestion

55.

Adaptive Low-Density Parity Check Decoder

      
Application Number 18452316
Status Pending
Filing Date 2023-08-18
First Publication Date 2024-02-29
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Lu, Xuanxuan
  • Varnica, Nedeljko

Abstract

The present disclosure describes apparatuses and methods for implementing an adaptive low-density parity check (LDPC) decoder. In various aspects, an adaptive LDPC decoder processes a first portion of data using first parameters effective to change a status of the LDPC decoder. The LDPC decoder selects second parameters of the LDPC decoder based on the status of the LDPC decoder. The LDPC decoder then processes a second portion of the data with the LDPC decoder using the second parameters and provides decoded data of the channel based on at least the processing the first portion of the data using the first parameters and the processing of the second portion of the data using the second parameters. By adaptively altering the decoding parameters based the status of the decoder, the adaptive LDPC decoder may decode channel data in fewer decoding iterations or with a higher success rate, thereby improving LDPC decoding performance.

IPC Classes  ?

  • H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
  • H03M 13/00 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes

56.

Gate All-Around (GAA) Field Effect Transistors (FETS) Formed on Both Sides of a Substrate

      
Application Number 18454835
Status Pending
Filing Date 2023-08-24
First Publication Date 2024-02-29
Owner Marvell Asia Pte Ltd (Singapore)
Inventor Chang, Runzi

Abstract

An electronic device includes a substrate, first and second semiconductor devices, and a power supply structure. The first semiconductor device includes a first plurality of gate all-around (GAA) field effect transistors (FETs) formed over a first side of the substrate. The second semiconductor device includes a second plurality of GAA FETs formed over a second side of the substrate, opposite the first side. The power supply structure is (a) disposed at the first side, and (b) configured to supply power to one or more of: (i) the first plurality of GAA FETs through first electrical couplings disposed at the first side, and (ii) the second plurality of GAA FETs through second electrical couplings including one or more inter-side vias (ISVs) traversing the substrate from the second side to the first side.

IPC Classes  ?

  • H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
  • H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 23/535 - Arrangements for conducting electric current within the device in operation from one component to another including internal interconnections, e.g. cross-under constructions
  • H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate

57.

SLEEP SIGNALING HANDSHAKE FOR ETHERNET

      
Application Number 18502963
Status Pending
Filing Date 2023-11-06
First Publication Date 2024-02-29
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Fung, Hon Wai
  • Wu, Dance

Abstract

A first communication device performs a handshaking procedure with a second communication device, the handshaking procedure associated with transitioning from an active mode to a low power mode. The first communication device transmits data and/or idle symbols to the second communication device i) after completion of the handshake procedure, and ii) at least until the earlier of a) a time period expiring, and b) determining that the second communication device quieted a transmitter of the second communication device. The first communication device transitions to the low power mode in connection with the handshaking procedure.

IPC Classes  ?

58.

ADAPTIVE LOW-DENSITY PARITY CHECK DECODER

      
Application Number IB2023058299
Publication Number 2024/042443
Status In Force
Filing Date 2023-08-18
Publication Date 2024-02-29
Owner MARVELL ASIA PTE LTD (Singapore)
Inventor
  • Lu, Xuanxuan
  • Varnica, Nedeljko

Abstract

The present disclosure describes apparatuses and methods for implementing an adaptive low-density parity check (LDPC) decoder performing iterations on bit-flipping or symbol-flipping operations. In various aspects, an adaptive LDPC decoder (130) processes (704) a first portion of data using first parameters, e.g. flipping thresholds, effective to change a status of the LDPC decoder, e.g. syndrome weight. The LDPC decoder selects (706) second parameters, e.g. adaptively changes flipping thresholds, of the LDPC decoder based on the status of the LDPC decoder. The LDPC decoder then processes (708) a second portion of the data with the LDPC decoder using the second parameters and provides (712) decoded data of the channel based on at least the processing the first portion of the data using the first parameters and the processing of the second portion of the data using the second parameters. By adaptively altering the decoding parameters based the status of the decoder, the adaptive LDPC decoder may decode channel data in fewer decoding iterations or with a higher success rate, thereby improving LDPC decoding performance.

IPC Classes  ?

  • H03M 13/37 - Decoding methods or techniques, not specific to the particular type of coding provided for in groups
  • H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits

59.

Disk writing mode with timing control of main pole relaxation

      
Application Number 18156852
Grant Number 11915729
Status In Force
Filing Date 2023-01-19
First Publication Date 2024-02-27
Grant Date 2024-02-27
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Wu, Kai
  • Fang, Hao
  • Licona, Jorge Estuardo

Abstract

When writing data to a magnetic data storage medium, it is detected whether duration, before occurrence of a data transition, of data to be written exceeds a predetermined threshold. When the duration, before the transition, of the data to be written exceeds the predetermined threshold, the data is written by applying an initial pulse and then maintaining, until a shut-off pulse, a steady-state write current having an amplitude less than the initial pulse. A shut-off adjustment is determined based on a predetermined delay. The shut-off pulse is initiated at a time based on one bit period prior to the transition, adjusted by the shut-off adjustment. When the duration, before the transition, of the data to be written is at most equal to the predetermined threshold, the data is written by applying the initial pulse without applying a steady-state write current before the transition.

IPC Classes  ?

  • G11B 20/10 - Digital recording or reproducing
  • G11B 11/105 - Recording on, or reproducing from, the same record carrier wherein for these two operations the methods or means are covered by different main groups of groups or by different subgroups of group ; Record carriers therefor using recording by magnetisation or demagnetisation using a beam of light or a magnetic field for recording and a beam of light for reproducing, e.g. light-induced thermomagnetic recording or Kerr effect reproducing
  • G11B 5/09 - Digital recording

60.

Coherent receiver with polarization diversity clock detection

      
Application Number 18366695
Status Pending
Filing Date 2023-08-08
First Publication Date 2024-02-22
Owner Marvell Asia Pte Ltd (Singapore)
Inventor Chen, Chen

Abstract

A receiver includes an optical front-end and digital circuitry. The optical front-end is configured to receive an optical signal including first and second optical signal components having first and second polarizations and modulated with symbols at a symbol rate. The digital circuitry is configured to derive first and second digital signals representing the first and second optical signal components having the first and second polarizations. The digital circuitry includes a clock detector configured to calculate correlation terms, the correlation terms being calculated in a frequency-domain with a frequency offset commensurate with the symbol rate. The clock detector is configured to recover a clock signal of the symbols by (i) summing selected pairs of the correlation terms, and (ii) calculating or estimating a sum-of-squares of the summed pairs.

IPC Classes  ?

  • H04B 10/61 - Coherent receivers
  • H04L 7/00 - Arrangements for synchronising receiver with transmitter

61.

Methods and Apparatus for Providing Soft and Blind Combining for PUSCH Acknowledgement (ACK) Processing

      
Application Number 18386562
Status Pending
Filing Date 2023-11-02
First Publication Date 2024-02-22
Owner Marvell Asia Pte, Ltd. (Singapore)
Inventor
  • Guzelgoz, Sabih
  • Kim, Hong Jik
  • Bhatt, Tejas Maheshbhai
  • Heidari, Fariba

Abstract

Methods and apparatus for providing soft and blind combining for PUSCH acknowledgement (ACK) processing. In an exemplary embodiment, a method includes soft-combining acknowledgement (ACK) bits received from a UE that are contained in a received sub-frame of symbols. The ACK bits are soft-combined using a plurality of scrambling sequences to generate a plurality of hypothetical soft-combined ACK bit streams. The method also includes receiving a parameter that identifies a selected scrambling sequence to be used. The method also includes decoding a selected hypothetical soft-combined ACK bit stream to generate a decoded ACK value, wherein the selected hypothetical soft-combined ACK bit stream is selected from the plurality of hypothetical soft-combined ACK bit streams based on the parameter.

IPC Classes  ?

  • H04L 5/00 - Arrangements affording multiple use of the transmission path
  • H04L 25/06 - Dc level restoring means; Bias distortion correction
  • H04L 1/00 - Arrangements for detecting or preventing errors in the information received
  • H04L 1/1607 - Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals - Details of the supervisory signal
  • H04W 72/121 - Wireless traffic scheduling for groups of terminals or users
  • H04W 72/1268 - Mapping of traffic onto schedule, e.g. scheduled allocation or multiplexing of flows of uplink data flows

62.

POWER MONITOR FOR SILICON-PHOTONICS-BASED LASER

      
Application Number 18495848
Status Pending
Filing Date 2023-10-27
First Publication Date 2024-02-22
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • He, Xiaoguang
  • Nagarajan, Radhakrishnan L.

Abstract

A laser device based on silicon photonics with in-cavity power monitor includes a gain chip, a reflector, and a photodiode. The gain chip is mounted on a silicon photonics substrate and is configured to emit light from an active region bounded between a frontend facet and a backend facet. The reflector is configured to reflect the light in a cavity formed between the reflector and the frontend facet through which a laser light is output. The photodiode is coupled to one or more waveguides in the cavity by a splitter disposed directly in an optical path between the reflector and a component positioned in the cavity. The photodiode is configured to measure power of light propagating through the cavity between the reflector and the component.

IPC Classes  ?

  • H01S 5/026 - Monolithically integrated components, e.g. waveguides, monitoring photo-detectors or drivers
  • H01S 5/02 - Structural details or components not essential to laser action
  • H01S 5/343 - Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers in AIIIBV compounds, e.g. AlGaAs-laser

63.

SOFT FEC WITH PARITY CHECK

      
Application Number 18384267
Status Pending
Filing Date 2023-10-26
First Publication Date 2024-02-22
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Riani, Jamal
  • Smith, Benjamin
  • Shvydun, Volodymyr
  • Bhoja, Sudeep
  • Farhoodfar, Arash

Abstract

A method for data transmission includes receiving a data stream from a host device, the data stream as received from the host device including encoded data, separating the encoded data in the data stream into first data blocks and second data blocks, and generating a first forward error correction (FEC) block. The first FEC block includes a first parity section and a first data section, the first parity section includes a first parity bit corresponding to the first data blocks and a second parity bit corresponding to the second data blocks, and the first data section includes the first data blocks and the second data blocks. The method further includes transmitting the first FEC block.

IPC Classes  ?

  • H04L 1/00 - Arrangements for detecting or preventing errors in the information received
  • H03M 13/15 - Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
  • H03M 13/29 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
  • H04B 14/02 - Transmission systems not characterised by the medium used for transmission characterised by the use of pulse modulation

64.

HIERARCHICAL STATISICALLY MULTIPLEXED COUNTERS AND A METHOD THEREOF

      
Application Number 18500091
Status Pending
Filing Date 2023-11-01
First Publication Date 2024-02-22
Owner Marvell Asia Pte, Ltd. (Singapore)
Inventor
  • Wang, Weihuang
  • Schmidt, Gerald
  • Atluri, Srinath
  • Ma, Weinan
  • Lnu, Shrikant Sundaram

Abstract

Embodiments of the present invention relate to an architecture that uses hierarchical statistically multiplexed counters to extend counter life by orders of magnitude. Each level includes statistically multiplexed counters. The statistically multiplexed counters includes P base counters and S subcounters, wherein the S subcounters are dynamically concatenated with the P base counters. When a row overflow in a level occurs, counters in a next level above are used to extend counter life. The hierarchical statistically multiplexed counters can be used with an overflow FIFO to further extend counter life.

IPC Classes  ?

  • H03K 21/02 - Input circuits
  • H03K 23/64 - Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
  • H04L 47/62 - Queue scheduling characterised by scheduling criteria
  • H04L 49/90 - Buffering arrangements

65.

M MARVELL BRIGHTLANE

      
Application Number 018988503
Status Pending
Filing Date 2024-02-21
Owner Marvell Asia Pte Ltd (Singapore)
NICE Classes  ? 09 - Scientific and electric apparatus and instruments

Goods & Services

Computer hardware; computer chips; semiconductors; semiconductor chips and chip sets; microprocessors; central processing units; integrated circuits; integrated circuit chips; software and firmware for controlling and using integrated circuits; integrated circuits in the nature of application specific standard products (ASSPs), application specific integrated circuits (ASICs), and system-on-chips (SoCs), and related downloadable software for use in automotive applications, namely, downloadable software for providing high-performance computing and secure Ethernet connectivity in a vehicle; data communication circuits; computer network bridges; Ethernet switches; Ethernet adapters; Ethernet transceivers; Ethernet controllers; Ethernet repeaters; data processors for packet processing, encryption, Ethernet connectivity, digital signal processing, telematic control, advanced driver assistance, in-vehicle cameras and sensors, and artificial intelligence for use in automotive applications; processors, namely, artificial intelligence data processors, server data processors, general purpose computer data processors, high-performance computing data processors, digital signal data processors, data processors, programmable data processors, audio or video data processors; computer hardware and downloadable software and firmware for setting up, configuring, managing, operating, and securing local and wide-area computer networks and network products; In-Vehicle Networking (INV) systems comprised of computer hardware and recorded software for facilitating electronic data communication transmission used to connect electronic control units in automobiles; computer hardware and downloadable software and firmware for use in enabling autonomous driving vehicles, connected vehicles, and components of autonomous driving vehicles and connected vehicles; lidar apparatus; computer hardware and software for lidar apparatus.

66.

Traffic characteristics for target wake time (TWT) negotiation

      
Application Number 18072048
Grant Number 11910240
Status In Force
Filing Date 2022-11-30
First Publication Date 2024-02-20
Grant Date 2024-02-20
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Chu, Liwen
  • Zhang, Hongyuan
  • Lou, Hui-Ling

Abstract

A first communication device generates a beacon frame that includes i) parameters of a broadcast target wake time (TWT) schedule and ii) information regarding a quantity of client stations that have currently joined the broadcast TWT schedule. The first communication device transmits the beacon frame to inform one or more second communication devices of i) the parameters of the broadcast TWT schedule and ii) the quantity of client stations that have currently joined the broadcast TWT schedule.

IPC Classes  ?

  • H04L 69/324 - Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions in the data link layer [OSI layer 2], e.g. HDLC
  • H04W 28/18 - Negotiating wireless communication parameters
  • H04W 52/02 - Power saving arrangements
  • H04W 84/12 - WLAN [Wireless Local Area Networks]

67.

Common-mode filtering for converting differential signaling to single-ended signaling

      
Application Number 17654316
Grant Number 11903123
Status In Force
Filing Date 2022-03-10
First Publication Date 2024-02-13
Grant Date 2024-02-13
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Huang, Shaowu
  • Wu, Dance

Abstract

An interface in a communications system includes a physical layer transceiver (PHY) for coupling to a wireline channel medium, and for coupling to a functional device via a single-ended cable. The PHY is an integrated circuit (IC) device having first and second differential input/output (I/O) conductors for coupling to the functional device, an impedance element configured to terminate a first one of the differential I/O conductors to a system ground, a second one of the differential I/O conductors being coupled to the single-ended cable, and a common-mode filter coupled to both of the differential I/O conductors. The PHY may further include a printed circuit board (PCB), with the IC device being mounted on the PCB, the first and second differential I/O conductors being signal traces on the PCB. The single-ended cable may be a coaxial cable.

IPC Classes  ?

68.

Circuit and Method for Timestamp Jitter Reduction

      
Application Number 17815635
Status Pending
Filing Date 2022-07-28
First Publication Date 2024-02-08
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Babitsky, Eliya
  • Noiman, Moran
  • Katz, Adi
  • Yehezkel, Yaakov
  • Halili, Ofer
  • Robinson, Tal

Abstract

A circuit and corresponding method generate a filtered timestamp. The circuit comprises recursive filter logic. The circuit generates the filtered timestamp from a received timestamp by filtering the received timestamp via the recursive filter logic. The recursive filter logic reduces jitter in the filtered timestamp relative to jitter of the received timestamp. The jitter represents a deviation of the received timestamp from a target (ideal) timestamp. The circuit outputs the filtered timestamp generated. The filtered timestamp is a more accurate representation of the target timestamp, relative to the received timestamp, due to the jitter reduced.

IPC Classes  ?

  • H04L 43/106 - Active monitoring, e.g. heartbeat, ping or trace-route using time related information in packets, e.g. by adding timestamps
  • H04L 43/087 - Jitter

69.

SILICON PHOTONICS INTEGRATION CIRCUIT

      
Application Number 17882888
Status Pending
Filing Date 2022-08-08
First Publication Date 2024-02-08
Owner MARVELL ASIA PTE LTD. (Singapore)
Inventor
  • Tu, Xiaoguang
  • Kato, Masaki
  • Li, Yu

Abstract

A silicon photonics integration circuit includes a silicon substrate member; a RX sub-circuit formed in the silicon substrate member including multiple RX-input ports each having a mode size converter configured to receive an incoming light signal into one of multiple waveguides and multiple RX photo detectors coupled respectively to the multiple waveguides; and a TX sub-circuit formed in the silicon substrate member including one or more TX-input ports each having a mode size converter coupled to a first TX photo detector into one input waveguide, one or more 1×2 directional couplers each coupled between the input waveguide and two mod-input waveguides, multiple modulators coupled between respective multiple mod-input waveguides and multiple mod-output waveguides each being coupled to a second TX photo detector into one of multiple output waveguides, and multiple TX-output ports each having a mode size converter coupled to respective one of the multiple output waveguides.

IPC Classes  ?

  • G02B 6/12 - Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
  • H04B 10/50 - Transmitters

70.

Mixed-Dimension Order Routing

      
Application Number 18154314
Status Pending
Filing Date 2023-01-13
First Publication Date 2024-02-08
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Viego, Anthony
  • Featherston, Joseph
  • Shreedhar, Aadeetya

Abstract

A circuit and corresponding method employ mixed-dimension order routing. The circuit comprises an interconnect, associated with a two-dimensional (2D) coordinate system, and a switch coupled to the interconnect. The switch determines a route path for a flit based on a mixed-dimension order routing method. The flit originates at an origin. The mixed-dimension order routing method employs, based on the origin of the flit, vertical-to-horizontal dimension routing or horizontal-to-vertical dimension routing. The switch routes the flit via the interconnect of the circuit based on the route path determined. The vertical-to-horizontal dimension routing and horizontal-to-vertical dimension routing are relative to the 2D coordinate system. The mixed-dimension order routing method prevents deadlock and congestion that otherwise degrade performance of the circuit.

IPC Classes  ?

  • H04L 49/109 - Integrated on microchip, e.g. switch-on-chip
  • H04L 47/122 - Avoiding congestion; Recovering from congestion by diverting traffic away from congested entities
  • H04L 45/58 - Association of routers
  • H04L 49/25 - Routing or path finding in a switch fabric

71.

Optimized path selection for multi-path groups

      
Application Number 18090288
Grant Number 11895015
Status In Force
Filing Date 2022-10-28
First Publication Date 2024-02-06
Grant Date 2024-02-06
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Budhia, Rupa
  • Matthews, William Brad
  • Agarwal, Puneet

Abstract

A packet to be forwarded over a computer network to a destination is received. A group of multiple network paths is available to forward to the packet to the destination. One or more path selection factors are determined to be used to identify a specific network load balancing algorithm to select a specific network path from the group of multiple network paths. The one or more path selection factors include at least one path selection factor determined based at least in part on a dynamic state of the computer network or a network node in the computer network. In response to selecting, by the specific network load balancing algorithm, the specific network path from among the group of multiple network paths, the packet is forwarded over the specific network path.

IPC Classes  ?

72.

Disk writing mode providing main pole relaxation

      
Application Number 18053470
Grant Number 11894025
Status In Force
Filing Date 2022-11-08
First Publication Date 2024-02-06
Grant Date 2024-02-06
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Wu, Kai
  • Oberg, Mats
  • Fang, Hao

Abstract

A method for writing data to a magnetic data storage medium includes detecting whether the duration, before occurrence of a data transition, of data to be written exceeds a predetermined threshold, and, when the duration, before the occurrence of the data transition, of the data to be written exceeds the predetermined threshold, writing the data by applying an initial pulse and then maintaining a steady-state write current for a defined interval, and when the duration, before the occurrence of the data transition, of the data to be written is at most equal to the predetermined threshold, writing the data by applying the initial pulse without applying a steady-state write current before the data transition. The predetermined threshold may be determined by size of a magnetic bubble formed when writing a single bit to the magnetic data storage medium. A subsequent pulse may be applied following the defined interval.

IPC Classes  ?

  • G11B 11/105 - Recording on, or reproducing from, the same record carrier wherein for these two operations the methods or means are covered by different main groups of groups or by different subgroups of group ; Record carriers therefor using recording by magnetisation or demagnetisation using a beam of light or a magnetic field for recording and a beam of light for reproducing, e.g. light-induced thermomagnetic recording or Kerr effect reproducing
  • G11B 7/00 - Recording or reproducing by optical means, e.g. recording using a thermal beam of optical radiation, reproducing using an optical beam at lower power; Record carriers therefor
  • G11B 5/012 - Recording on, or reproducing or erasing from, magnetic disks
  • G11B 5/49 - Fixed mountings

73.

PROTOCOL INDEPENDENT PROGRAMMABLE SWITCH (PIPS) FOR SOFTWARE DEFINED DATA CENTER NETWORKS

      
Application Number 18378463
Status Pending
Filing Date 2023-10-10
First Publication Date 2024-02-01
Owner Marvell Asia PTE, LTD (Singapore)
Inventor
  • Hutchison, Guy Townsend
  • Gandhi, Sachin Ramesh
  • Daniel, Tsahi
  • Schmidt, Gerald
  • Fishman, Albert
  • White, Martin Leslie
  • Shah, Zubin

Abstract

A software-defined network (SDN) system, device and method comprise one or more input ports, a programmable parser, a plurality of programmable lookup and decision engines (LDEs), programmable lookup memories, programmable counters, a programmable rewrite block and one or more output ports. The programmability of the parser, LDEs, lookup memories, counters and rewrite block enable a user to customize each microchip within the system to particular packet environments, data analysis needs, packet processing functions, and other functions as desired. Further, the same microchip is able to be reprogrammed for other purposes and/or optimizations dynamically.

IPC Classes  ?

  • H04L 49/109 - Integrated on microchip, e.g. switch-on-chip
  • G06F 3/06 - Digital input from, or digital output to, record carriers
  • H04L 45/64 - Routing or path finding of packets in data switching networks using an overlay routing layer
  • H04L 45/745 - Address table lookup; Address filtering
  • H04L 49/1546 - Non-blocking multistage, e.g. Clos using pipelined operation
  • H04L 69/22 - Parsing or analysis of headers
  • H04L 49/00 - Packet switching elements
  • G06F 16/00 - Information retrieval; Database structures therefor; File system structures therefor
  • H04L 45/74 - Address processing for routing
  • G06F 40/205 - Parsing
  • H04L 67/63 - Routing a service request depending on the request content or context

74.

Circuit and Method for Timestamp Filtering with Input/Output Format Conversion

      
Application Number 17815646
Status Pending
Filing Date 2022-07-28
First Publication Date 2024-02-01
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Babitsky, Eliya
  • Noiman, Moran
  • Katz, Adi
  • Yehezkel, Yaakov
  • Halili, Ofer
  • Robinson, Tal

Abstract

A circuit and corresponding method perform timestamp filtering. The circuit comprises input format-conversion logic that converts a received timestamp from an original format to an intermediate format. The circuit further comprises recursive filter logic coupled to the input format-conversion logic. The recursive filter logic generates a filtered timestamp in the intermediate format by filtering the received timestamp in the intermediate format. The circuit further comprises output format-conversion logic coupled to the recursive filter logic. The output format-conversion logic converts the filtered timestamp from the intermediate timestamp format to the original timestamp format and outputs the filtered timestamp in the original timestamp format. Converting the received timestamp into a different format avoids use of complex logic to handle rollover of input values, thereby reducing area and power consumption of the circuit.

IPC Classes  ?

75.

Circuit and Method for Timestamp Filtering with RLS Filter

      
Application Number 17815652
Status Pending
Filing Date 2022-07-28
First Publication Date 2024-02-01
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Babitsky, Eliya
  • Noiman, Moran
  • Katz, Adi
  • Yehezkel, Yaakov
  • Halili, Ofer
  • Robinson, Tal

Abstract

A circuit and corresponding method perform timestamp filtering. The circuit comprises recursive filter logic that implements a recursive least-squares (RLS) filter. The circuit (i) generates a filtered timestamp from a received timestamp by filtering the received timestamp via the recursive filter logic. The recursive filter logic applies the RLS filter to a portion of the received timestamp. A number of bits of the portion is less relative to a total number of bits of the received timestamp. The circuit outputs the filtered timestamp generated. Applying the RLS filter to the portion enables the circuit to be more efficient (e.g., smaller adders, fewer flipflops, etc.), thereby reducing area and power consumption of the circuit.

IPC Classes  ?

  • H04L 43/106 - Active monitoring, e.g. heartbeat, ping or trace-route using time related information in packets, e.g. by adding timestamps
  • H04L 43/087 - Jitter

76.

Aggregation of frames for transmission in a wireless communication network

      
Application Number 17353144
Grant Number 11889488
Status In Force
Filing Date 2021-06-21
First Publication Date 2024-01-30
Grant Date 2024-01-30
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Chu, Liwen
  • Zheng, Xiayu
  • Zhang, Hongyuan
  • Lou, Hui-Ling

Abstract

A first communication device determines that a trigger frame and another frame are to be transmitted to at least a second communication device. The first communication device determines whether the second communication device announced support of aggregation of buffer status report (BSRP) trigger frames with additional frames. In response to the first communication device determining that the second communication device announced support of aggregation of BSRP trigger frames with additional frames, the first communication device generates an aggregate media access control protocol data unit (A-MPDU) to include the BSRP trigger frame and the other frame, and transmits the A-MPDU within a packet. In response to the first communication device determining that the second communication device did not announce support of aggregation of BSRP trigger frames with additional frames, the first communication device transmits a packet having only the BSRP trigger frame.

IPC Classes  ?

  • H04L 5/00 - Arrangements affording multiple use of the transmission path
  • H04W 72/0453 - Resources in frequency domain, e.g. a carrier in FDMA
  • H04W 84/12 - WLAN [Wireless Local Area Networks]

77.

METHOD, SYSTEM AND DEVICE OF SERIALIZING AND DE-SERIALIZING THE DELIVERY OF SCAN TEST DATA THROUGH CHIP I/O TO REDUCE THE SCAN TEST DURATION OF AN INTEGRATED CIRCUIT

      
Application Number 17869495
Status Pending
Filing Date 2022-07-20
First Publication Date 2024-01-25
Owner MARVELL ASIA PTE LTD. (Singapore)
Inventor
  • Biswas, Sounil
  • Wangoo, Amit
  • Zhong, Zhanwei

Abstract

An integrated circuit verification system including automatic test equipment (ATE) and a device under test (DUT) having an internal test data de-serializer and test response data serializer. Specifically, the de-serializer of the DUT is able to de-serialize a test pattern or scan test data generated and received from an ATE at a general-purpose I/O pin (or functional pin) of the DUT for testing a circuit under test (CUT) of the DUT and then serialize the response to the test data with the serializer for output back to the ATE via the same or a different general-purpose I/O pin (or functional pin) of the DUT.

IPC Classes  ?

78.

A METHOD OF USING BIT VECTORS TO ALLOW EXPANSION AND COLLAPSE OF HEADER LAYERS WITHIN PACKETS FOR ENABLING FLEXIBLE MODIFICATIONS AND AN APPARATUS THEREOF

      
Application Number 18370821
Status Pending
Filing Date 2023-09-20
First Publication Date 2024-01-18
Owner Marvell Asia Pte., Ltd. (Singapore)
Inventor
  • Singh, Chirinjeev
  • Daniel, Tsahi
  • Schmidt, Gerald

Abstract

Embodiments of the apparatus for modifying packet headers relate to a use of bit vectors to allow expansion and collapse of protocol headers within packets for enabling flexible modification. A rewrite engine expands each protocol header into a generic format and applies various commands to modify the generalized protocol header. The rewrite engine maintains a bit vector for the generalized protocol header with each bit in the bit vector representing a byte of the generalized protocol header. A bit marked as 0 in the bit vector corresponds to an invalid byte, while a bit marked as 1 in the bit vector corresponds to a valid byte. The rewrite engine uses the bit vector to remove all the invalid bytes after all commands have been operated on the generalized protocol header to thereby form a new protocol header.

IPC Classes  ?

  • H04L 69/22 - Parsing or analysis of headers
  • H04L 69/04 - Protocols for data compression, e.g. ROHC
  • H04L 49/00 - Packet switching elements
  • H04L 69/08 - Protocols for interworking; Protocol conversion

79.

Optical transceiver with multimode interferometers

      
Application Number 18353084
Status Pending
Filing Date 2023-07-16
First Publication Date 2024-01-18
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Wang, Yun
  • Cai, Hong
  • Lin, Nathan
  • Lin, Jie

Abstract

An optical transceiver includes optical circuitry disposed on a substrate and comprising a transmitter and a receiver. The circuitry includes least one multi-mode interferometer (MMI), including a multi-mode waveguide comprising an input face and an output face, the input and output faces being bisected by a longitudinal axis, the multi-mode waveguide having a predefined width transverse to the longitudinal axis. Ports are coupled to respective waveguides and are configured to launch one or more input beams through the input face and receive one or more output beams from the output face. The ports include, on at least one of the faces, two or more ports at respective locations that are offset transversely from the longitudinal axis by at least λ0/300 from respective base transverse displacements that are equal to integer fractions of the width.

IPC Classes  ?

  • H04B 10/40 - Transceivers
  • H04B 10/11 - Arrangements specific to free-space transmission, i.e. transmission through air or vacuum
  • G02B 6/293 - Optical coupling means having data bus means, i.e. plural waveguides interconnected and providing an inherently bidirectional system by mixing and splitting signals with wavelength selective means

80.

Method and apparatus for determining bit-error rate in a data channel

      
Application Number 17815415
Grant Number 11876532
Status In Force
Filing Date 2022-07-27
First Publication Date 2024-01-16
Grant Date 2024-01-16
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Chen, Yuanjie
  • Visani, Davide
  • Wu, Min

Abstract

A method for determining a bit-error rate in data received on high-speed data channel that uses a forward-error-correcting decoder includes receiving at receiver circuitry on the high-speed data channel a received predetermined data pattern, comparing, bit-wise, the received predetermined data pattern to a locally generated copy of the predetermined data pattern to derive output bits representing whether there was an error in a corresponding bit of the received predetermined data pattern, to determine error bits in the received predetermined data pattern, grouping output bits from the comparing into symbols and codewords, and for each codeword for which a count of symbols containing errors exceeds a number of symbols correctable by the forward-error-correcting decoder, counting a total number of bit errors contained in the symbols containing errors, for use in adjusting the receiver circuitry in response to the total number of bit errors.

IPC Classes  ?

  • H03M 13/01 - Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
  • H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
  • H03M 13/15 - Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes

81.

Bandwidth indication, negotiation and TXOP protection with multiple channel segments

      
Application Number 17857945
Grant Number 11877274
Status In Force
Filing Date 2022-07-05
First Publication Date 2024-01-16
Grant Date 2024-01-16
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Chu, Liwen
  • Zhang, Hongyuan
  • Lou, Hui-Ling

Abstract

A communication device generates a first packet to include a first indication of one or more first frequency subchannels in a first frequency segment that will be utilized to transmit the first packet. The communication device also generates a second packet to include a second indication of one or more second frequency subchannels in a second frequency segment that will be utilized to transmit the second packet. The communication device simultaneously transmits the first packet via the first frequency segment and the second packet via the second frequency segment.

IPC Classes  ?

  • H04W 72/0453 - Resources in frequency domain, e.g. a carrier in FDMA
  • H04L 5/00 - Arrangements affording multiple use of the transmission path
  • H04W 72/23 - Control channels or signalling for resource management in the downlink direction of a wireless link, i.e. towards a terminal
  • H04W 74/08 - Non-scheduled access, e.g. random access, ALOHA or CSMA [Carrier Sense Multiple Access]
  • H04W 84/12 - WLAN [Wireless Local Area Networks]
  • H04L 1/1607 - Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals - Details of the supervisory signal
  • H04L 69/22 - Parsing or analysis of headers
  • H04L 101/622 - Layer-2 addresses, e.g. medium access control [MAC] addresses

82.

INTEGRATED CIRCUIT DEVICE EXPOSED DIE PACKAGE STRUCTURE WITH ADHESIVE

      
Application Number US2023027010
Publication Number 2024/010859
Status In Force
Filing Date 2023-07-06
Publication Date 2024-01-11
Owner MARVELL ASIA PTE LTD (Singapore)
Inventor Chee, Choong Kooi

Abstract

An integrated circuit (IC) device package includes a structure having a base and walls extending from the base, at least one IC die mounted to the base within the walls, each die having a top surface parallel to the base and having a thickness extending along an axis, perpendicular to the top surface, at most equal to a height of the walls, a thermally conductive heat spreader extending parallel to the base above the die and the walls, and an interface layer including an adhesive layer portion disposed between the walls and the heat spreader to adhere the heat spreader to the walls, and a thermal interface material (TIM) layer portion coplanar with, and laterally displaced from, the adhesive layer portion, the TIM layer portion being disposed in thermally conductive relationship between the heat spreader and each respective die, to dissipate heat from each respective die to the heat spreader.

IPC Classes  ?

  • H01L 23/367 - Cooling facilitated by shape of device
  • H01L 23/373 - Cooling facilitated by selection of materials for the device
  • H01L 23/42 - Fillings or auxiliary members in containers selected or arranged to facilitate heating or cooling

83.

BLOCK ACKNOWLEDGMENT OPERATION

      
Application Number 18237785
Status Pending
Filing Date 2023-08-24
First Publication Date 2024-01-11
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Chu, Liwen
  • Ho, Ken Kinwah
  • Zhang, Hongyuan
  • Lou, Hui-Ling

Abstract

A first communication device transmits first bitmap length capability information for the first communication device regarding block acknowledgment procedures, and receives second bitmap length capability information for a second communication device regarding block acknowledgment procedures. The first communication device performs a block acknowledgment procedure, including setting a block acknowledgment transmission window size for the block acknowledgment procedure based on the second bitmap length capability information for the second communication device, and a determination of whether a block acknowledgement frame used in the block acknowledgment procedure is a compressed block acknowledgement (C-BA) frame or a multi-station (multi-STA) block acknowledgement frame.

IPC Classes  ?

  • H04L 1/1607 - Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals - Details of the supervisory signal
  • H04L 1/1829 - Arrangements specially adapted for the receiver end
  • H04L 1/1867 - Arrangements specially adapted for the transmitter end
  • H04B 7/26 - Radio transmission systems, i.e. using radiation field for communication between two or more posts at least one of which is mobile
  • H04L 5/00 - Arrangements affording multiple use of the transmission path

84.

INTEGRATED CIRCUIT DEVICE EXPOSED DIE PACKAGE STRUCTURE WITH ADHESIVE

      
Application Number 18348041
Status Pending
Filing Date 2023-07-06
First Publication Date 2024-01-11
Owner Marvell Asia Pte Ltd (Singapore)
Inventor Chee, Choong Kooi

Abstract

An integrated circuit (IC) device package includes a structure having a base and walls extending from the base, at least one IC die mounted to the base within the walls, each die having a top surface parallel to the base and having a thickness extending along an axis, perpendicular to the top surface, at most equal to a height of the walls, a thermally conductive heat spreader extending parallel to the base above the die and the walls, and an interface layer including an adhesive layer portion disposed between the walls and the heat spreader to adhere the heat spreader to the walls, and a thermal interface material (TIM) layer portion coplanar with, and laterally displaced from, the adhesive layer portion, the TIM layer portion being disposed in thermally conductive relationship between the heat spreader and each respective die, to dissipate heat from each respective die to the heat spreader.

IPC Classes  ?

  • H01L 23/373 - Cooling facilitated by selection of materials for the device
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
  • H01L 23/367 - Cooling facilitated by shape of device

85.

System and methods for latency reduction for fuse reload post reset

      
Application Number 17086371
Grant Number 11868475
Status In Force
Filing Date 2020-10-31
First Publication Date 2024-01-09
Grant Date 2024-01-09
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Sundararaman, Ramacharan
  • Miyar, Nithyananda
  • Kovac, Martin
  • Sodani, Avinash
  • Shivaraj, Raghuveer

Abstract

A new approach is proposed that contemplates systems and methods to support post reset fuse reload for latency reduction. First, values of fuses are read once and stored into one or more load registers on an electronic device, wherein the load registers are protected. Once the values of the fuse are loaded into the load registers, a valid indicator of the load registers is set indicating that the values have been successfully loaded into the load registers. When other components of the electronic device need to access these values, the other components will check the load registers first. If it is determined that the valid indicator of the load registers is set, the stored values are read from the load registers instead of from the fuses. If the valid indicator of the load registers is not set, the values are loaded again from the fuses into the load registers.

IPC Classes  ?

  • G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
  • G06F 9/4401 - Bootstrapping

86.

Frequency division multiple access (FDMA) support for wakeup radio (WUR) operation

      
Application Number 17991494
Grant Number 11871348
Status In Force
Filing Date 2022-11-21
First Publication Date 2024-01-09
Grant Date 2024-01-09
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Chu, Liwen
  • Cao, Rui
  • Zhang, Hongyuan
  • Lou, Hui-Ling

Abstract

A wireless network interface of a first client station negotiates with an access point a first component channel of an operating channel via which the first client station is to receive wakeup frames from the access point. A wakeup radio of the first client station receives a wakeup packet from the access point. The wakeup packet spans the operating channel, which comprises at least four component channels, and one or more of the component channels within the operating channel are punctured so that the access point does not transmit the wakeup packet in the one or more component channels that are punctured. The wakeup packet includes a first wakeup frame for the first client station in the first component channel and one or more respective second wakeup frames for one or more second client stations in one or more respective second component channels.

IPC Classes  ?

87.

Network device using cache techniques to process control signals

      
Application Number 17698196
Grant Number 11868282
Status In Force
Filing Date 2022-03-18
First Publication Date 2024-01-09
Grant Date 2024-01-09
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Sonksen, Bradley
  • Nitza, Paul

Abstract

A network controller for coupling a host device to a data network, in accordance with network command blocks initiated in a request queue in the host device, includes a channel interface configured to couple to the data network, where the channel interface includes memory configured to store the network command blocks and processing circuitry configured to execute the network command blocks to move data between the host device and the data network, and a host interface configured to couple the network controller to the host device, and to move the network command blocks from the request queue in the host device to the memory using cache operations, including fetching one of the network command blocks from the request queue upon receipt from the host device of a message advising that a request queue location has changed.

IPC Classes  ?

  • G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
  • G06F 12/0831 - Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means

88.

Systems and methods for introducing time diversity in Wifi transmissions

      
Application Number 17536381
Grant Number 11870579
Status In Force
Filing Date 2021-11-29
First Publication Date 2024-01-09
Grant Date 2024-01-09
Owner Marvell Asia Pte, Ltd. (Singapore)
Inventor
  • Sun, Yakun
  • Zhang, Hongyuan
  • Chu, Liwen
  • Lou, Hui-Ling

Abstract

Systems and methods are provided for introducing time diversity in a transmitter. The systems and methods may include receiving, at the transmitter, a request from a receiver to retransmit data. The systems and methods may further include receiving an input of data corresponding to the data requested for retransmission at a first transmitter block. The systems and methods may further include operating on the signals using the first transmitter block in at least one of a first mode and a second mode, such that an output of signals from the first transmitter block is dependent on a time-varying function and corresponds to the data requested by the receiver for retransmission.

IPC Classes  ?

  • H04L 1/00 - Arrangements for detecting or preventing errors in the information received
  • H04L 1/1867 - Arrangements specially adapted for the transmitter end
  • H04L 1/1825 - Adaptation of specific ARQ protocol parameters according to transmission conditions
  • H04L 1/08 - Arrangements for detecting or preventing errors in the information received by repeating transmission, e.g. Verdan system
  • H04B 7/06 - Diversity systems; Multi-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station

89.

PHYSICAL LAYER FRAME FORMAT FOR WLAN

      
Application Number 18244792
Status Pending
Filing Date 2023-09-11
First Publication Date 2023-12-28
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Zhang, Hongyuan
  • Lou, Hui-Ling
  • Nabar, Rohit U.
  • Srinivasa, Sudhir
  • Yu, Mao
  • Banerjea, Raja

Abstract

A preamble of physical layer (PHY) data unit includes a first legacy portion and a first non-legacy portion that follows the first legacy portion. The first non-legacy portion includes i) a first orthogonal frequency division multiplexing (OFDM) symbol that immediately follows the first legacy portion and that is modulated using binary phase shift keying (BPSK), and ii) a second OFDM symbol that immediately follows the first OFDM symbol and that is modulated using BPSK modulation rotated by 90 degrees (Q-BPSK). The modulation of the first and second OFDM symbols indicates to a receiver device that conforms to a first communication protocol that the data unit conforms to the first communication protocol. The first OFDM symbol being modulated using BPSK modulation causes a receiver device that conforms to a second communication protocol to determine that the PHY data unit conforms to a third communication protocol.

IPC Classes  ?

  • H04L 1/00 - Arrangements for detecting or preventing errors in the information received
  • H04L 27/26 - Systems using multi-frequency codes
  • H04L 69/18 - Multiprotocol handlers, e.g. single devices capable of handling multiple protocols
  • H04W 28/06 - Optimising, e.g. header compression, information sizing

90.

COMMUNICATION DEVICE WITH INTERLEAVED ENCODING FOR FEC ENCODED DATA STREAMS

      
Application Number 18244880
Status Pending
Filing Date 2023-09-11
First Publication Date 2023-12-28
Owner Marvell Asia Pte Ltd. (Singapore)
Inventor
  • Smith, Benjamin P.
  • Shvydun, Volodymyr
  • Riani, Jamal
  • Lyubomirsky, Ilya

Abstract

A communication device includes a convolutional interleaver and an encoder. The convolutional interleaver is configured to receive blocks of data defining symbol blocks that are encoded using a block code to correct an error in a block of data and to interleave the symbol blocks into a stream of interleaved symbol blocks. The encoder is configured to encode a set of symbol blocks among the interleaved symbol blocks with an error-correcting code to correct single bit errors in the set of symbol blocks. The error-correcting code is configured to generate an error-correcting block and to add the error-correcting block to the set of interleaved symbol blocks.

IPC Classes  ?

  • H03M 13/27 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
  • H03M 13/15 - Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes

91.

Lossless integer compression scheme

      
Application Number 17197268
Grant Number 11854235
Status In Force
Filing Date 2021-03-10
First Publication Date 2023-12-26
Grant Date 2023-12-26
Owner Marvell Asia Pte, Ltd. (Singapore)
Inventor Lu, Tao

Abstract

Decompressing a compressed image to obtain a decompressed image includes receiving, in a compressed stream, compressed pixel values of the compressed image; decompressing, from the compressed stream, a first compressed pixel value of the compressed pixel values using a lossy floating-point decompression scheme to obtain a floating-point pixel value; rounding the floating-point pixel value to a nearest integer to obtain a pixel value of the decompressed image; and displaying or storing the decompressed image.

IPC Classes  ?

  • G06K 9/36 - Image preprocessing, i.e. processing the image information without deciding about the identity of the image
  • G06T 9/00 - Image coding
  • H03M 7/30 - Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
  • G06T 3/40 - Scaling of a whole image or part thereof

92.

Adaptive orthogonal frequency division multiplexing (OFDM) numerology in a wireless communication network

      
Application Number 14701208
Grant Number 11855818
Status In Force
Filing Date 2015-04-30
First Publication Date 2023-12-26
Grant Date 2023-12-26
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Sun, Yakun
  • Zhang, Hongyuan
  • Xu, Mingguang
  • Lou, Hui-Ling

Abstract

In a method for adapting an orthogonal frequency division multiplexing (OFDM) numerology configuration for use in a communication network one or more OFDM numerology configurations are adaptively selected at a first communication device to be used in communication with one or more second communication devices. Adaptively one or more OFDM numerology configurations includes selecting at least one combination of two or more of (i) a guard interval duration, (ii) a tone spacing, (iii) a starting location of the selected guard interval duration, and (iv) a starting location of the selected tone spacing. A physical layer (PHY) data unit to be transmitted to a second communication device is generated at the first communication device. The PHY data unit is generated using one of the one or more adaptively selected OFDM numerology configurations to generate OFDM symbols of at least a portion of the PHY data unit.

IPC Classes  ?

  • H04L 27/26 - Systems using multi-frequency codes
  • H04L 5/00 - Arrangements affording multiple use of the transmission path
  • H04W 84/12 - WLAN [Wireless Local Area Networks]

93.

Automotive asymmetric ethernet using frequency-division duplex

      
Application Number 18460546
Status Pending
Filing Date 2023-09-03
First Publication Date 2023-12-21
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Wu, Xing
  • Dai, Shaoan
  • Wu, Dance
  • Chu, William

Abstract

An Ethernet Physical Layer (PHY) device includes a link interface and a transceiver. The link interface is configured to connect to a full-duplex wired Ethernet link. The transceiver is configured to receive first Ethernet signals carrying first data at a first data rate over the Ethernet link in a first direction, the first Ethernet signals occupying a first frequency band, and to transmit second Ethernet signals carrying second data at a second data rate different from the first data rate, over the Ethernet link in a second direction that is opposite the first direction, the second Ethernet signals occupying a second frequency band that is different from the first frequency band.

IPC Classes  ?

  • H04L 5/14 - Two-way operation using the same type of signal, i.e. duplex
  • H04B 3/23 - Reducing echo effects or singing; Opening or closing transmitting path; Conditioning for transmission in one direction or the other using a replica of transmitted signal in the time domain, e.g. echo cancellers
  • H04L 7/04 - Speed or phase control by synchronisation signals

94.

ESSENTIAL TECHNOLOGY, DONE RIGHT

      
Serial Number 98321720
Status Pending
Filing Date 2023-12-19
Owner Marvell Asia Pte, Ltd. (Singapore)
NICE Classes  ? 25 - Clothing; footwear; headgear

Goods & Services

Clothing, namely, shirts, tank tops, shorts, pants, clothing jerseys, clothing jackets, vests, hooded pullovers, cycling shorts, cycling bib shorts, cycling gloves, triathlon suits, arm warmers, and leg warmers; headwear; neckwear; shoe accessories, namely, fitted decorative covers for shoes

95.

Shift-register-based clock phase interpolator

      
Application Number 17455784
Grant Number 11849015
Status In Force
Filing Date 2021-11-19
First Publication Date 2023-12-19
Grant Date 2023-12-19
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Zhao, Hui
  • Guo, Zhendong

Abstract

An integrated circuit device includes functional circuitry, and serializer/deserializer circuitry for serial communication with the functional circuitry. The serializer/deserializer circuitry includes phase interpolator circuitry for interpolating phases of a clock signal of the integrated circuit device. The phase interpolator circuitry includes a phase shift register having storage locations configured to represent the phases of the clock signal, and phase rotation control circuitry configured to decode a phase code signal to determine a shifting direction for phase selections in storage locations of the phase shift register. The phase rotation control circuitry may be configured to determine the shifting direction based on only the most significant bit and the second most significant bit of the phase code signal. The phase interpolator circuitry may further include weight decoder circuitry configured to derive, from the phase code signal, interpolation weights to control combination of selected phases of the clock signal.

IPC Classes  ?

  • H04L 7/00 - Arrangements for synchronising receiver with transmitter

96.

Method And Device For High Bandwidth Receiver For High Baud-Rate Communications

      
Application Number 18236675
Status Pending
Filing Date 2023-08-22
First Publication Date 2023-12-14
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Dallaire, Stephane
  • Nguyen, Ray Luan
  • Hatcher, Geaffrey

Abstract

An analog front-end (AFE) device and method for a high baud-rate receiver. The device can include an input matching network coupled to a first buffer device, which is coupled to a sampler array. The input matching network can include a first T-coil configured to receive a first input and a second T-coil configured to receive a second input. The first buffer device can include one or more buffers each having a bias circuit coupled to a first class-AB source follower and a second class-AB source follower. The sampling array can include a plurality of sampler devices configured to receive a multi-phase clocking signal. Additional optimization techniques can be used, such as having a multi-tiered sampler array and having the first buffer device configured with separate buffers for odd and even sampling phases. Benefits of this AFE configuration can include increased bandwidth, sampling rate, and power efficiency.

IPC Classes  ?

  • H03H 7/38 - Impedance-matching networks
  • H04B 1/16 - Circuits
  • H03F 3/19 - High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only

97.

LOW LOSS AND STABLE PLANAR LIGHTWAVE CIRCUIT ATTACHEMENT WITH SILICON INTERPOSER

      
Application Number US2023024685
Publication Number 2023/239774
Status In Force
Filing Date 2023-06-07
Publication Date 2023-12-14
Owner MARVELL ASIA PTE., LTD. (Singapore)
Inventor
  • Wang, Hsiu-Che
  • Tumne, Pushkraj
  • Shirley, Dwayne R.
  • Coccioli, Roberto
  • Fu, Peikeng

Abstract

An optical signal transceiver includes a circuit board substrate, a silicon photonics-based interposer mounted on the circuit board substrate, the silicon photonics-based interposer including at least one of a waveguide configured to transmit optical communication signals and a photo detector configured to detect optical communication signals, and a planar lightwave circuit disposed on the circuit board substrate. The planar lightwave circuit is configured to perform at least a portion of propagation of light signals in an optical communication network, and the planar lightwave circuit is aligned with a side surface of the silicon photonics-based interposer to transmit optical communication signals between the silicon photonics-based interposer and the planar lightwave circuit. The optical signal transceiver includes at least one spacer component disposed between the planar lightwave circuit and the circuit board substrate, and epoxy material in contact with the spacer component.

IPC Classes  ?

  • G02B 6/42 - Coupling light guides with opto-electronic elements
  • G02B 6/255 - Splicing of light guides, e.g. by fusion or bonding

98.

CO-PACKAGING OPTICAL MODULES WITH SURFACE AND EDGE COUPLING

      
Application Number 18227180
Status Pending
Filing Date 2023-07-27
First Publication Date 2023-12-14
Owner Marvell Asia Pie Ltd (Singapore)
Inventor
  • Nagarajan, Radhakrishnan L.
  • Patterson, Mark

Abstract

An assembled electro-optical switch module includes a package substrate. Four optical socket members are disposed respectively to the package substrate. Each optical socket member includes four sockets closely packed in a row. Each socket has a recessed flat region with topside land grid array (LGA) interposer connected to bottom side solder bumps and a side notch opening aligned to an edge of the package substrate at the corresponding edge region. Sixteen optical modules in four sets are co-packaged in the package substrate. Each set has four optical modules respectively seated in the four sockets of each optical socket member with top side LGA interposer. Four clamp latch members are applied to clamp each of the four sets of optical modules in respective optical socket members. A data processor device with 51.2 Tbps data interface is disposed to the package substrate and electrically coupled to each of the sixteen optical module.

IPC Classes  ?

  • G02B 6/43 - Arrangements comprising a plurality of opto-electronic elements and associated optical interconnections
  • G02B 6/42 - Coupling light guides with opto-electronic elements

99.

United states test controller for system-on-chip validation

      
Application Number 17655706
Grant Number 11841396
Status In Force
Filing Date 2022-03-21
First Publication Date 2023-12-12
Grant Date 2023-12-12
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Vaidya, Sameer
  • Katchmart, Supaket
  • Khanzode, Vivek
  • Joshi, Pallavi
  • Sutioso, Henri
  • Siemsen-Schumann, Naim
  • Sheng, Hongying

Abstract

A storage device controller includes drive controller circuitry configured to control writing and fetching of data from a storage medium, read data channel circuitry for interfacing between the drive controller circuitry and the storage medium, test controller circuitry configured to test the read data channel circuitry by issuing test commands simulating the writing and fetching of data from the storage medium, and selector circuitry configured to switchably couple the read data channel circuitry to the drive controller circuitry in an operating mode and to the test controller circuitry in a testing mode. The storage device controller may include a pattern generator configured to output the test commands. Processor circuitry may be configured to store test results in memory, to compute performance metrics from the stored test results, and communicate the performance metrics to a host device.

IPC Classes  ?

100.

Managing out-of-order retirement of instructions based on received instructions indicating start or stop to out-of-order retirement

      
Application Number 17515712
Grant Number 11842198
Status In Force
Filing Date 2021-11-01
First Publication Date 2023-12-12
Grant Date 2023-12-12
Owner Marvell Asia Pte, Ltd. (Singapore)
Inventor Mukherjee, Shubhendu Sekhar

Abstract

Retiring instructions out-of-order includes: receiving processor instructions comprising two or more and fewer than all processor instructions generated based on a program, where the processor instructions include a first instruction and a second instruction such that the first instruction precedes the second instruction in a program order of the program; receiving a start instruction that immediately precedes the processor instructions and indicates that the processor instructions are to be retired out-of-order; receiving a stop instruction immediately that succeeds the processor instructions and indicates a stop to out-of-order instruction retirement; and, in response to completing execution of the second instruction before completing execution of the first instruction, retiring the second instruction before retiring the first instruction.

IPC Classes  ?

  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline, look ahead
  • G06F 9/32 - Address formation of the next instruction, e.g. by incrementing the instruction counter
  • G06F 8/41 - Compilation
  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
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