Marvell Asia PTE, Ltd.

Singapore

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H04L 1/00 - Arrangements for detecting or preventing errors in the information received 339
H03M 13/00 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes 264
H04L 29/06 - Communication control; Communication processing characterised by a protocol 251
H04L 5/00 - Arrangements affording multiple use of the transmission path 247
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1.

EXPLICIT BEAMFORMING IN A HIGH EFFICIENCY WIRELESS LOCAL AREA NETWORK

      
Application Number 18520523
Status Pending
Filing Date 2023-11-27
First Publication Date 2024-03-21
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Cao, Rui
  • Zhang, Hongyuan

Abstract

A first communication device receives a sounding packet from a second communication device and develops beamforming information based on the sounding packet. The first communication device transmits beamforming feedback to the second communication device, the beamforming feedback including beamforming information for use by the second communication device to beamsteer a data packet to the first communication device, the data packet having a data portion that includes a second number of OFDM tones greater than a first number of OFDM tones in the sounding packet. After transmitting the beamforming feedback, the first communication device receives the data packet from the second communication device, the data packet including one or more data OFDM symbols, each of the one or more data OFDM symbols having the second number of OFDM tones.

IPC Classes  ?

  • H04B 7/0417 - Feedback systems
  • H04B 7/0456 - Selection of precoding matrices or codebooks, e.g. using matrices for antenna weighting
  • H04B 7/06 - Diversity systems; Multi-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station
  • H04L 5/00 - Arrangements affording multiple use of the transmission path
  • H04W 16/28 - Cell structures using beam steering

2.

Multi-Termination Scheme Interface

      
Application Number 18524662
Status Pending
Filing Date 2023-11-30
First Publication Date 2024-03-21
Owner Marvell Asia Pte, Ltd. (Singapore)
Inventor Wang, Lu

Abstract

In an embodiment, a method includes programming a control signal that specifies a target resistance and a target voltage in a circuit. The method further includes sending the control signal to at least one transistor configured to control a current flow in the circuit. The method further includes providing, as an output, a signal with the target voltage and target resistance.

IPC Classes  ?

  • H03K 19/00 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
  • H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits

3.

MANAGING POWER IN AN ELECTRONIC DEVICE

      
Application Number 17745092
Status Pending
Filing Date 2022-05-16
First Publication Date 2024-03-21
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Matthews, William Brad
  • Kwan, Bruce H.

Abstract

A network device accesses, from a queue corresponding to a port of the device, a packet for processing. The device identifies a present operating region (ORE) of one or more OREs specified for the device, an ORE being associated with at least one of (i) one or more device attributes, or (ii) one or more environmental factors associated with an environment in which the device is operational. The device determines a number of power credits available for processing one or more packets. In response to determining that the number of power credits available is non-negative, the device completes processing of the packet. The device computes, based at least on the present ORE, a power credit reduction for the packet, which corresponds to an amount of power for processing the packet, and reduces the number of power credits available by the power credit reduction for the packet.

IPC Classes  ?

  • G06F 1/3296 - Power saving characterised by the action undertaken by lowering the supply or operating voltage
  • H04L 49/90 - Buffering arrangements

4.

WIRELINE TRANSCEIVER WITH INTERNAL AND EXTERNAL CLOCK GENERATION

      
Application Number 18514479
Status Pending
Filing Date 2023-11-20
First Publication Date 2024-03-21
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Cai, Li
  • Chong, Sau Siong
  • Loi, Chang-Feng
  • Tse, Lawrence

Abstract

An integrated circuit device having functional circuitry driven by a clock signal includes onboard clock generation circuitry. The clock generation circuitry includes an input configured to accept a frequency reference signal, at least one variable loading capacitor coupled to the input for converting the crystal resonator signal into a calibrated clock signal, and calibration circuitry configured to calibrate the at least one variable loading capacitor based on a reference voltage. The input configured to accept a frequency reference signal may be configured to accept a crystal resonator signal.

IPC Classes  ?

  • G06F 1/08 - Clock generators with changeable or programmable clock frequency
  • G06F 1/10 - Distribution of clock signals
  • G06F 1/12 - Synchronisation of different clock signals

5.

Digital timing recovery for constant density servo read operations

      
Application Number 18157585
Grant Number 11935561
Status In Force
Filing Date 2023-01-20
First Publication Date 2024-03-19
Grant Date 2024-03-19
Owner Marvell Asia Pte Ltd (Singapore)
Inventor Katchmart, Supaket

Abstract

A method of reading servo wedge data from a rotating constant-density magnetic storage medium having a plurality of tracks, where each track is written at a track pattern frequency, the respective track pattern frequencies varying from a lowest frequency at an innermost one of the tracks to a highest frequency at an outermost one of the tracks, includes, for each respective track, determining, based on the pattern frequency of the respective track, a desired sampling position, sampling actual samples of servo wedge data based on a sampling clock used for all tracks, having a sampling frequency at least equal to the track pattern frequency of the outermost track, determining a phase relationship of the desired sampling position to the sampling clock, and, depending on the phase relationship between the sampling position and the sampling clock, interpolating a sample, or omitting interpolation of a sample and squelching the interpolation clock.

IPC Classes  ?

  • G11B 5/09 - Digital recording
  • G11B 20/10 - Digital recording or reproducing
  • G11B 20/14 - Digital recording or reproducing using self-clocking codes

6.

Dual-surface RRO write in a storage device servo system

      
Application Number 18066394
Grant Number 11935571
Status In Force
Filing Date 2022-12-15
First Publication Date 2024-03-19
Grant Date 2024-03-19
Owner Marvell Asia Pte Ltd (Singapore)
Inventor Katchmart, Supaket

Abstract

A method for writing repeatable run-out (RRO) data, to surfaces of a rotating magnetic storage medium in a storage device having two read channels, includes detecting, with a first head, using a first read channel, a servo sync mark (SSM) on a first track on a first surface, establishing a recurring servo-gating signal at a successive fixed interval from the SSM, detecting, with the first head, servo signals from the first track on occurrence of the recurring servo-gating signal, processing the servo signals from the first track, to generate first positioning signals for positioning the first head relative to the first track, following a similar procedure with a second read channel having a second head to generate second positioning signals for the second read head, and writing first and second RRO data to servo wedges of the first and second tracks according to the respective positioning signals.

IPC Classes  ?

  • G11B 5/596 - Disposition or mounting of heads relative to record carriers with provision for moving the head for the purpose of maintaining alignment of the head relative to the record carrier during transducing operation, e.g. to compensate for surface irregularities of the latter or for track following for track following on disks

7.

Reduction of four-wave mixing crosstalk in optical links

      
Application Number 18462470
Status Pending
Filing Date 2023-09-07
First Publication Date 2024-03-14
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Mak, Gary
  • Patra, Lenin Kumar
  • Riani, Jamal

Abstract

A transmitter includes at least three tunable laser sources, an optical multiplexer, and a processor. The at least three tunable laser sources are configured to receive respective data streams, and to output respective Tx light beams at different respective carrier frequencies, modulated with the respective data streams. The optical multiplexer is configured to combine the multiple Tx light beams to produce a combined beam formed of the modulated Tx light beams at the different carrier frequencies, and to transmit the combined beam over an optical fiber. The processor is configured to receive a notification indicative of an interference occurring due to Four-Wave Mixing (FWM) in the optical fiber, and to modify at least one of the carrier frequencies responsively to the notification in order to mitigate the interference due to FWM.

IPC Classes  ?

  • H04B 10/50 - Transmitters
  • G02B 6/293 - Optical coupling means having data bus means, i.e. plural waveguides interconnected and providing an inherently bidirectional system by mixing and splitting signals with wavelength selective means
  • H04B 10/2563 - Four-wave mixing [FWM]
  • H04J 14/02 - Wavelength-division multiplex systems

8.

INTEGRATED COHERENT OPTICAL TRANSCEIVER

      
Application Number 18502449
Status Pending
Filing Date 2023-11-06
First Publication Date 2024-03-14
Owner Marvell Asia Pte Ltd (Singapore)
Inventor Nagarajan, Radhakrishnan L.

Abstract

An integrated circuit includes a silicon photonics substrate having a silicon-based material, silicon photonics components formed in the silicon photonics substrate to receive and transmit optical signals, and electrical connections; a transimpedance amplifier chip arranged on the silicon photonics substrate, having a silicon-germanium material that is different than the silicon-based material, connected via the electrical connections to at least one of the silicon photonics components configured to receive an optical signal, and configured to process a received optical signal and output a processed signal to a digital signal processor; and a driver chip arranged on the silicon photonics substrate, having CMOS material that is different than the silicon-germanium material and the silicon-based material, connected via the electrical connections to drive at least one of the silicon photonics components configured to generate an optical signal for transmission.

IPC Classes  ?

  • H04B 10/40 - Transceivers
  • G02B 6/12 - Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
  • G02B 6/126 - Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind using polarisation effects
  • G02B 6/42 - Coupling light guides with opto-electronic elements
  • H01S 3/13 - Stabilisation of laser output parameters, e.g. frequency or amplitude
  • H01S 5/00 - Semiconductor lasers
  • H01S 5/0234 - Up-side down mountings, e.g. Flip-chip, epi-side down mountings or junction down mountings
  • H01S 5/02375 - Positioning of the laser chips

9.

EFFICIENT SIGNALING SCHEME FOR HIGH-SPEED ULTRA SHORT REACH INTERFACES

      
Application Number 18512744
Status Pending
Filing Date 2023-11-17
First Publication Date 2024-03-14
Owner MARVELL ASIA PTE LTD (Singapore)
Inventor
  • Farjadrad, Ramin
  • Langner, Paul

Abstract

A multi-chip package includes first and second groups of integrated circuit (IC) chips and a transfer IC chip disposed in the multi-chip package. The transfer IC chip is communicatively interposed between the first and second groups of IC chips and is configured to transfer signals from at least a first IC chip of the first group of IC chips to at least a second IC chip of the second group of IC chips or an output interface. The output interface is configured to output first data from the multi-chip package. A first set of ultra-short reach (USR) signaling links connects the first group of IC chips to the transfer IC chip. A second set of USR signaling links connects the second group of IC chips to the transfer IC chip. Each of the USR signaling links comprises a trace length of less than one inch.

IPC Classes  ?

  • G06F 13/36 - Handling requests for interconnection or transfer for access to common bus or bus system
  • H04L 7/00 - Arrangements for synchronising receiver with transmitter
  • H04L 25/20 - Repeater circuits; Relay circuits

10.

GATE STACK FOR METAL GATE TRANSISTOR

      
Application Number 18514146
Status Pending
Filing Date 2023-11-20
First Publication Date 2024-03-14
Owner Marvell Asia Pte, Ltd. (Singapore)
Inventor Chang, Runzi

Abstract

Forming a metal gate transistor includes forming a semiconductor channel in a substrate, and depositing a source electrode and a drain electrode on the semiconductor channel. The source and drain electrodes are spaced apart. Dielectric spacers are provided above the source and drain electrodes to define a gate void spanning the source and drain electrodes. A dielectric layer is deposited on a bottom wall and sidewalls of the gate void. A work-function metal layer is deposited on the dielectric layer. The work-function metal layer is etched away from the sidewalls leaving the work-function metal layer on the bottom wall to control work function between the semiconductor channel and a conductive metal gate material to be deposited. The gate void above the work-function metal layer on the bottom wall, and between the dielectric layers on the sidewalls, is filled with the conductive metal gate material.

IPC Classes  ?

  • H01L 29/40 - Electrodes
  • H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
  • H01L 29/49 - Metal-insulator semiconductor electrodes
  • H01L 29/66 - Types of semiconductor device

11.

Semiconductor device with mechanism to prevent reverse engineering

      
Application Number 17845606
Grant Number 11928248
Status In Force
Filing Date 2022-06-21
First Publication Date 2024-03-12
Grant Date 2024-03-12
Owner Marvell Asia Pte Ltd (Singapore)
Inventor Hunt-Schroeder, Eric

Abstract

A semiconductor device is configured to implement a security protocol. The semiconductor device includes an entropy source that includes a plurality of bitcells. The entropy source is configured to output a sequence of physical unclonable function bit values based on intrinsic properties of the plurality of bitcells to generate a unique device secret for the security protocol, and selectively damage at least a portion of the plurality of bitcells to prevent reverse engineering the sequence of physical unclonable function bit values.

IPC Classes  ?

  • G06F 21/71 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
  • G06F 21/14 - Protecting executable software against software analysis or reverse engineering, e.g. by obfuscation

12.

Circuit and method for resource arbitration

      
Application Number 17932084
Grant Number 11929940
Status In Force
Filing Date 2022-09-14
First Publication Date 2024-03-12
Grant Date 2024-03-12
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Featherston, Joseph
  • Shreedhar, Aadeetya

Abstract

A circuit and corresponding method perform resource arbitration. The circuit comprises a pending arbiter (PA) that outputs a PA selection for accessing a resource. The PA is selection based on PA input. The PA input represents respective pending-state of requesters of the resource. The circuit further comprises a valid arbiter (VA) that outputs a VA selection for accessing the resource. The VA selection is based on VA input. The VA input represents respective valid-state of the requesters. The circuit performs a validity check on the PA selection output. The circuit outputs a final selection for accessing the resource by selecting, based on the validity check performed, the PA selection output or VA selection output. The circuit addresses arbitration fairness issues that may result when multiple requesters are arbitrating to be selected for access to a shared resource and such requesters require a credit (token) to be eligible for arbitration.

IPC Classes  ?

  • G06F 13/36 - Handling requests for interconnection or transfer for access to common bus or bus system
  • H04L 47/783 - Distributed allocation of resources, e.g. bandwidth brokers
  • H04L 47/80 - Actions related to the user profile or the type of traffic

13.

Digital droop detector

      
Application Number 18048018
Grant Number 11927612
Status In Force
Filing Date 2022-10-19
First Publication Date 2024-03-12
Grant Date 2024-03-12
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Knoll, Ernest
  • Yassur, Omer

Abstract

A circuit detects a voltage droop exhibited by a power supply. A first signal delay line outputs a first delayed signal, and is comprised of delay elements having a first threshold voltage. A second delay line outputs a second delayed signal, and is comprised of delay elements having a second threshold voltage that is higher than the first threshold voltage. A phase detector compares the first and second delayed signals and outputs a comparison signal indicating which of the first and second signal delay lines exhibits a shorter delay. A reset circuit resets the first and second signal delay lines in response to the comparison signal, and a clock controller outputs a command to adjust a clock frequency or engage in other mitigation measures based on the comparison signal.

IPC Classes  ?

  • G01R 25/00 - Arrangements for measuring phase angle between a voltage and a current or between voltages or currents
  • H03K 5/14 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of delay lines
  • H03L 7/00 - Automatic control of frequency or phase; Synchronisation

14.

System and method for schedule-based I/O multiplexing for integrated circuit (IC) scan test

      
Application Number 17500453
Grant Number 11927630
Status In Force
Filing Date 2021-10-13
First Publication Date 2024-03-12
Grant Date 2024-03-12
Owner Marvell Asia Pte Ltd (Singapore)
Inventor Biswas, Sounil

Abstract

An approach is proposed to support schedule-based I/O multiplexing for scan testing of an IC. A plurality of I/Os are assigned to a plurality of blocks in the IC for scan testing based on a set of slots under a set of schedules. Each of the set of slots includes a fixed number of scan input pins/pads and scan output pins/pads of the IC. Each slot is then assigned to a specific block on the IC for the scan test until all of the slots available are utilized. The group of assigned blocks is referred to as a schedule, and all of these blocks belonging to this schedule are scan tested in parallel at the same time. The remaining blocks on the IC are also assigned to the slots until all blocks on the IC are assigned to a schedule to be scan tested.

IPC Classes  ?

  • G01R 31/3177 - Testing of logic operation, e.g. by logic analysers
  • G01R 31/317 - Testing of digital circuits
  • G01R 31/3185 - Reconfiguring for testing, e.g. LSSD, partitioning
  • G01R 31/319 - Tester hardware, i.e. output processing circuits
  • G06F 30/34 - Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
  • G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
  • G11C 11/4093 - Input/output [I/O] data interface arrangements, e.g. data buffers
  • G11C 11/4096 - Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches

15.

OUT-OF-BAND BASED INDEPENDENT LINK TRAINING OF IN-BAND LINKS BETWEEN HOST DEVICES AND OPTICAL MODULES

      
Application Number US2023031613
Publication Number 2024/049950
Status In Force
Filing Date 2023-08-31
Publication Date 2024-03-07
Owner
  • MARVELL ASIA PTE LTD (Singapore)
  • MARVELL SEMICONDUCTOR INC. (USA)
Inventor
  • Lee, Whay Sing
  • Rope, Todd

Abstract

A first optical module includes an optical transceiver and a chip. The optical transceiver, subsequent to completion of link training of an in-band transmission link between the first optical module and a host device, waits for a second optical module to come up including transmitting a first awake signal from the first optical module to the second optical module, and receives a second awake signal from the second optical module when the second optical module is up. The chip i) based on a first out-of-band signal transmitted via an out-of-band link, performs the link training of the in-band transmission link independently of an in-band reception link between the first optical module and the host device, and ii) based on the second awake signal and a second out-of-band signal transmitted via the out-of-band link, performs link training of the in-band reception link independent of the in-band transmission link.

IPC Classes  ?

  • H04B 10/079 - Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems using an in-service signal using measurements of the data signal
  • H04B 10/077 - Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems using an in-service signal using a supervisory or additional signal
  • H04B 10/80 - Optical aspects relating to the use of optical transmission for specific applications, not provided for in groups , e.g. optical power feeding or optical transmission through water

16.

OUT-OF-BAND BASED INDEPENDENT LINK TRAINING OF IN-BAND LINKS BETWEEN HOST DEVICES AND OPTICAL MODULES

      
Application Number 18239819
Status Pending
Filing Date 2023-08-30
First Publication Date 2024-03-07
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Lee, Whay Sing
  • Rope, Todd

Abstract

A first optical module includes an optical transceiver and a chip. The optical transceiver, subsequent to completion of link training of an in-band transmission link between the first optical module and a host device, waits for a second optical module to come up including transmitting a first awake signal from the first optical module to the second optical module, and receives a second awake signal from the second optical module when the second optical module is up. The chip i) based on a first out-of-band signal transmitted via an out-of-band link, performs the link training of the in-band transmission link independently of an in-band reception link between the first optical module and the host device, and ii) based on the second awake signal and a second out-of-band signal transmitted via the out-of-band link, performs link training of the in-band reception link independent of the in-band transmission link.

IPC Classes  ?

17.

GATE ALL-AROUND (GAA) FIELD EFFECT TRANSISTORS (FETS) FORMED ON BOTH SIDES OF A SUBSTRATE

      
Application Number IB2023058399
Publication Number 2024/047479
Status In Force
Filing Date 2023-08-24
Publication Date 2024-03-07
Owner MARVELL ASIA PTE LTD (Singapore)
Inventor Chang, Runzi

Abstract

An electronic device (11) includes a substrate (55), first and second semiconductor devices (22, 33), and a power supply structure (88b). The first semiconductor device (22) includes a first plurality of gate all-around (GAA) field effect transistors (FETs) (44) formed over a first side (25) of substrate (55). The second semiconductor device (33) includes a second plurality of GAA FETs (44) formed over a second side (35) of substrate (55), opposite first side (25). The power supply structure (88b) is (a) disposed at the first side (25), and (b) configured to supply power to one or more of: (i) the first plurality of GAA FETs (44) through first electrical couplings (77) disposed at the first side (25), and (ii) the second plurality of GAA FETs (44) through second electrical couplings (77) including inter-side vias (ISVs) (66) traversing the substrate (55) from the second side (35) to the first side (35).

IPC Classes  ?

  • H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
  • H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
  • H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
  • H01L 21/8234 - MIS technology
  • H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
  • H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body

18.

System and methods for firmware security mechanism

      
Application Number 16947424
Grant Number 11921904
Status In Force
Filing Date 2020-07-31
First Publication Date 2024-03-05
Grant Date 2024-03-05
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Sundararaman, Ramacharan
  • Miyar, Nithyananda
  • Kovac, Martin

Abstract

A new approach is proposed to support a hardware-based lock mechanism having a hardware-based lock unit associated with a resource, wherein the lock is utilized by an arbitrator to arbitrate between multiple agents requesting access to the resource. When a first agent requests access to resource in unlocked state, the arbitrator creates a lock ID and set a locked state indicating that the resource is locked. The lock ID is provided to the first agent, which now has exclusive control over the resource. The arbitrator ensures that any agent with the same ID may access the resource. When a second agent requests access to the resource with a lock ID to the arbitrator, it is granted access to the resource if the lock ID provided matches the one stored on the lock unit. If there is a mismatch between the lock IDs, access to the resource is denied.

IPC Classes  ?

  • G06F 21/71 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
  • G06F 8/65 - Updates

19.

Multi-port transceiver

      
Application Number 17744478
Grant Number 11923978
Status In Force
Filing Date 2022-05-13
First Publication Date 2024-03-05
Grant Date 2024-03-05
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Ghazali, Sabu
  • Patra, Lenin
  • Chen, Jeng-Jong Douglas
  • Youm, Dong-Seok
  • Tsai, Tunghao
  • Susanto, Kong Chuan

Abstract

A multi-port transceiver comprises a plurality of first ports, a first communication interface, and a second communication interface. Multi-rate interleaver circuitry interleaves i) a plurality of first data streams, each received via a respective first port at a first data rate, and ii) a second data stream received via the first communication interface at a second data rate, to generate a third data stream to be transmitted via the second communication interface at a third data rate. Multi-rate deinterleaver circuitry deinterleaves a fourth data stream that was received via the second communication interface at the third data rate into i) a plurality of fifth data streams, each fifth data stream to be transmitted via a respective first port at the first data rate, and ii) a sixth data stream to be transmitted via the first communication interface at the second data rate.

IPC Classes  ?

  • H04L 1/00 - Arrangements for detecting or preventing errors in the information received
  • H04B 1/40 - Circuits
  • H04L 49/00 - Packet switching elements

20.

Method and apparatus for control of congestion in storage area network

      
Application Number 17661174
Grant Number 11924105
Status In Force
Filing Date 2022-04-28
First Publication Date 2024-03-05
Grant Date 2024-03-05
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Sundar, Gourangadoss
  • Easi, Arun
  • Basrur, Girish

Abstract

In a storage area network operating in accordance with a transport-level protocol to interconnect host and target devices, where the transport-level protocol issues congestion notifications when any of the host or target devices becomes congested, a method for reducing congestion includes, on receipt of a request to (a) write data to one of the target devices or (b) read data from one of the target devices for return to one of the host devices, (A) determining whether congestion already exists at (a) the target device to which the write request is directed, or (b) the host device to which data from the read request is to be returned, and (B) when a congestion state already exists, comparing current depth of a queue of write or read requests to a maximum permissible queue depth. When the current depth of the queue exceeds a maximum permissible queue depth, the request is rejected.

IPC Classes  ?

  • H04L 47/12 - Avoiding congestion; Recovering from congestion

21.

Adaptive Low-Density Parity Check Decoder

      
Application Number 18452316
Status Pending
Filing Date 2023-08-18
First Publication Date 2024-02-29
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Lu, Xuanxuan
  • Varnica, Nedeljko

Abstract

The present disclosure describes apparatuses and methods for implementing an adaptive low-density parity check (LDPC) decoder. In various aspects, an adaptive LDPC decoder processes a first portion of data using first parameters effective to change a status of the LDPC decoder. The LDPC decoder selects second parameters of the LDPC decoder based on the status of the LDPC decoder. The LDPC decoder then processes a second portion of the data with the LDPC decoder using the second parameters and provides decoded data of the channel based on at least the processing the first portion of the data using the first parameters and the processing of the second portion of the data using the second parameters. By adaptively altering the decoding parameters based the status of the decoder, the adaptive LDPC decoder may decode channel data in fewer decoding iterations or with a higher success rate, thereby improving LDPC decoding performance.

IPC Classes  ?

  • H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
  • H03M 13/00 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes

22.

Gate All-Around (GAA) Field Effect Transistors (FETS) Formed on Both Sides of a Substrate

      
Application Number 18454835
Status Pending
Filing Date 2023-08-24
First Publication Date 2024-02-29
Owner Marvell Asia Pte Ltd (Singapore)
Inventor Chang, Runzi

Abstract

An electronic device includes a substrate, first and second semiconductor devices, and a power supply structure. The first semiconductor device includes a first plurality of gate all-around (GAA) field effect transistors (FETs) formed over a first side of the substrate. The second semiconductor device includes a second plurality of GAA FETs formed over a second side of the substrate, opposite the first side. The power supply structure is (a) disposed at the first side, and (b) configured to supply power to one or more of: (i) the first plurality of GAA FETs through first electrical couplings disposed at the first side, and (ii) the second plurality of GAA FETs through second electrical couplings including one or more inter-side vias (ISVs) traversing the substrate from the second side to the first side.

IPC Classes  ?

  • H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
  • H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 23/535 - Arrangements for conducting electric current within the device in operation from one component to another including internal interconnections, e.g. cross-under constructions
  • H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate

23.

SLEEP SIGNALING HANDSHAKE FOR ETHERNET

      
Application Number 18502963
Status Pending
Filing Date 2023-11-06
First Publication Date 2024-02-29
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Fung, Hon Wai
  • Wu, Dance

Abstract

A first communication device performs a handshaking procedure with a second communication device, the handshaking procedure associated with transitioning from an active mode to a low power mode. The first communication device transmits data and/or idle symbols to the second communication device i) after completion of the handshake procedure, and ii) at least until the earlier of a) a time period expiring, and b) determining that the second communication device quieted a transmitter of the second communication device. The first communication device transitions to the low power mode in connection with the handshaking procedure.

IPC Classes  ?

24.

ADAPTIVE LOW-DENSITY PARITY CHECK DECODER

      
Application Number IB2023058299
Publication Number 2024/042443
Status In Force
Filing Date 2023-08-18
Publication Date 2024-02-29
Owner MARVELL ASIA PTE LTD (Singapore)
Inventor
  • Lu, Xuanxuan
  • Varnica, Nedeljko

Abstract

The present disclosure describes apparatuses and methods for implementing an adaptive low-density parity check (LDPC) decoder performing iterations on bit-flipping or symbol-flipping operations. In various aspects, an adaptive LDPC decoder (130) processes (704) a first portion of data using first parameters, e.g. flipping thresholds, effective to change a status of the LDPC decoder, e.g. syndrome weight. The LDPC decoder selects (706) second parameters, e.g. adaptively changes flipping thresholds, of the LDPC decoder based on the status of the LDPC decoder. The LDPC decoder then processes (708) a second portion of the data with the LDPC decoder using the second parameters and provides (712) decoded data of the channel based on at least the processing the first portion of the data using the first parameters and the processing of the second portion of the data using the second parameters. By adaptively altering the decoding parameters based the status of the decoder, the adaptive LDPC decoder may decode channel data in fewer decoding iterations or with a higher success rate, thereby improving LDPC decoding performance.

IPC Classes  ?

  • H03M 13/37 - Decoding methods or techniques, not specific to the particular type of coding provided for in groups
  • H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits

25.

Disk writing mode with timing control of main pole relaxation

      
Application Number 18156852
Grant Number 11915729
Status In Force
Filing Date 2023-01-19
First Publication Date 2024-02-27
Grant Date 2024-02-27
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Wu, Kai
  • Fang, Hao
  • Licona, Jorge Estuardo

Abstract

When writing data to a magnetic data storage medium, it is detected whether duration, before occurrence of a data transition, of data to be written exceeds a predetermined threshold. When the duration, before the transition, of the data to be written exceeds the predetermined threshold, the data is written by applying an initial pulse and then maintaining, until a shut-off pulse, a steady-state write current having an amplitude less than the initial pulse. A shut-off adjustment is determined based on a predetermined delay. The shut-off pulse is initiated at a time based on one bit period prior to the transition, adjusted by the shut-off adjustment. When the duration, before the transition, of the data to be written is at most equal to the predetermined threshold, the data is written by applying the initial pulse without applying a steady-state write current before the transition.

IPC Classes  ?

  • G11B 20/10 - Digital recording or reproducing
  • G11B 11/105 - Recording on, or reproducing from, the same record carrier wherein for these two operations the methods or means are covered by different main groups of groups or by different subgroups of group ; Record carriers therefor using recording by magnetisation or demagnetisation using a beam of light or a magnetic field for recording and a beam of light for reproducing, e.g. light-induced thermomagnetic recording or Kerr effect reproducing
  • G11B 5/09 - Digital recording

26.

Coherent receiver with polarization diversity clock detection

      
Application Number 18366695
Status Pending
Filing Date 2023-08-08
First Publication Date 2024-02-22
Owner Marvell Asia Pte Ltd (Singapore)
Inventor Chen, Chen

Abstract

A receiver includes an optical front-end and digital circuitry. The optical front-end is configured to receive an optical signal including first and second optical signal components having first and second polarizations and modulated with symbols at a symbol rate. The digital circuitry is configured to derive first and second digital signals representing the first and second optical signal components having the first and second polarizations. The digital circuitry includes a clock detector configured to calculate correlation terms, the correlation terms being calculated in a frequency-domain with a frequency offset commensurate with the symbol rate. The clock detector is configured to recover a clock signal of the symbols by (i) summing selected pairs of the correlation terms, and (ii) calculating or estimating a sum-of-squares of the summed pairs.

IPC Classes  ?

  • H04B 10/61 - Coherent receivers
  • H04L 7/00 - Arrangements for synchronising receiver with transmitter

27.

Methods and Apparatus for Providing Soft and Blind Combining for PUSCH Acknowledgement (ACK) Processing

      
Application Number 18386562
Status Pending
Filing Date 2023-11-02
First Publication Date 2024-02-22
Owner Marvell Asia Pte, Ltd. (Singapore)
Inventor
  • Guzelgoz, Sabih
  • Kim, Hong Jik
  • Bhatt, Tejas Maheshbhai
  • Heidari, Fariba

Abstract

Methods and apparatus for providing soft and blind combining for PUSCH acknowledgement (ACK) processing. In an exemplary embodiment, a method includes soft-combining acknowledgement (ACK) bits received from a UE that are contained in a received sub-frame of symbols. The ACK bits are soft-combined using a plurality of scrambling sequences to generate a plurality of hypothetical soft-combined ACK bit streams. The method also includes receiving a parameter that identifies a selected scrambling sequence to be used. The method also includes decoding a selected hypothetical soft-combined ACK bit stream to generate a decoded ACK value, wherein the selected hypothetical soft-combined ACK bit stream is selected from the plurality of hypothetical soft-combined ACK bit streams based on the parameter.

IPC Classes  ?

  • H04L 5/00 - Arrangements affording multiple use of the transmission path
  • H04L 25/06 - Dc level restoring means; Bias distortion correction
  • H04L 1/00 - Arrangements for detecting or preventing errors in the information received
  • H04L 1/1607 - Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals - Details of the supervisory signal
  • H04W 72/121 - Wireless traffic scheduling for groups of terminals or users
  • H04W 72/1268 - Mapping of traffic onto schedule, e.g. scheduled allocation or multiplexing of flows of uplink data flows

28.

POWER MONITOR FOR SILICON-PHOTONICS-BASED LASER

      
Application Number 18495848
Status Pending
Filing Date 2023-10-27
First Publication Date 2024-02-22
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • He, Xiaoguang
  • Nagarajan, Radhakrishnan L.

Abstract

A laser device based on silicon photonics with in-cavity power monitor includes a gain chip, a reflector, and a photodiode. The gain chip is mounted on a silicon photonics substrate and is configured to emit light from an active region bounded between a frontend facet and a backend facet. The reflector is configured to reflect the light in a cavity formed between the reflector and the frontend facet through which a laser light is output. The photodiode is coupled to one or more waveguides in the cavity by a splitter disposed directly in an optical path between the reflector and a component positioned in the cavity. The photodiode is configured to measure power of light propagating through the cavity between the reflector and the component.

IPC Classes  ?

  • H01S 5/026 - Monolithically integrated components, e.g. waveguides, monitoring photo-detectors or drivers
  • H01S 5/02 - Structural details or components not essential to laser action
  • H01S 5/343 - Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers in AIIIBV compounds, e.g. AlGaAs-laser

29.

SOFT FEC WITH PARITY CHECK

      
Application Number 18384267
Status Pending
Filing Date 2023-10-26
First Publication Date 2024-02-22
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Riani, Jamal
  • Smith, Benjamin
  • Shvydun, Volodymyr
  • Bhoja, Sudeep
  • Farhoodfar, Arash

Abstract

A method for data transmission includes receiving a data stream from a host device, the data stream as received from the host device including encoded data, separating the encoded data in the data stream into first data blocks and second data blocks, and generating a first forward error correction (FEC) block. The first FEC block includes a first parity section and a first data section, the first parity section includes a first parity bit corresponding to the first data blocks and a second parity bit corresponding to the second data blocks, and the first data section includes the first data blocks and the second data blocks. The method further includes transmitting the first FEC block.

IPC Classes  ?

  • H04L 1/00 - Arrangements for detecting or preventing errors in the information received
  • H03M 13/15 - Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
  • H03M 13/29 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
  • H04B 14/02 - Transmission systems not characterised by the medium used for transmission characterised by the use of pulse modulation

30.

HIERARCHICAL STATISICALLY MULTIPLEXED COUNTERS AND A METHOD THEREOF

      
Application Number 18500091
Status Pending
Filing Date 2023-11-01
First Publication Date 2024-02-22
Owner Marvell Asia Pte, Ltd. (Singapore)
Inventor
  • Wang, Weihuang
  • Schmidt, Gerald
  • Atluri, Srinath
  • Ma, Weinan
  • Lnu, Shrikant Sundaram

Abstract

Embodiments of the present invention relate to an architecture that uses hierarchical statistically multiplexed counters to extend counter life by orders of magnitude. Each level includes statistically multiplexed counters. The statistically multiplexed counters includes P base counters and S subcounters, wherein the S subcounters are dynamically concatenated with the P base counters. When a row overflow in a level occurs, counters in a next level above are used to extend counter life. The hierarchical statistically multiplexed counters can be used with an overflow FIFO to further extend counter life.

IPC Classes  ?

  • H03K 21/02 - Input circuits
  • H03K 23/64 - Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
  • H04L 47/62 - Queue scheduling characterised by scheduling criteria
  • H04L 49/90 - Buffering arrangements

31.

M MARVELL BRIGHTLANE

      
Application Number 018988503
Status Pending
Filing Date 2024-02-21
Owner Marvell Asia Pte Ltd (Singapore)
NICE Classes  ? 09 - Scientific and electric apparatus and instruments

Goods & Services

Computer hardware; computer chips; semiconductors; semiconductor chips and chip sets; microprocessors; central processing units; integrated circuits; integrated circuit chips; software and firmware for controlling and using integrated circuits; integrated circuits in the nature of application specific standard products (ASSPs), application specific integrated circuits (ASICs), and system-on-chips (SoCs), and related downloadable software for use in automotive applications, namely, downloadable software for providing high-performance computing and secure Ethernet connectivity in a vehicle; data communication circuits; computer network bridges; Ethernet switches; Ethernet adapters; Ethernet transceivers; Ethernet controllers; Ethernet repeaters; data processors for packet processing, encryption, Ethernet connectivity, digital signal processing, telematic control, advanced driver assistance, in-vehicle cameras and sensors, and artificial intelligence for use in automotive applications; processors, namely, artificial intelligence data processors, server data processors, general purpose computer data processors, high-performance computing data processors, digital signal data processors, data processors, programmable data processors, audio or video data processors; computer hardware and downloadable software and firmware for setting up, configuring, managing, operating, and securing local and wide-area computer networks and network products; In-Vehicle Networking (INV) systems comprised of computer hardware and recorded software for facilitating electronic data communication transmission used to connect electronic control units in automobiles; computer hardware and downloadable software and firmware for use in enabling autonomous driving vehicles, connected vehicles, and components of autonomous driving vehicles and connected vehicles; lidar apparatus; computer hardware and software for lidar apparatus.

32.

Traffic characteristics for target wake time (TWT) negotiation

      
Application Number 18072048
Grant Number 11910240
Status In Force
Filing Date 2022-11-30
First Publication Date 2024-02-20
Grant Date 2024-02-20
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Chu, Liwen
  • Zhang, Hongyuan
  • Lou, Hui-Ling

Abstract

A first communication device generates a beacon frame that includes i) parameters of a broadcast target wake time (TWT) schedule and ii) information regarding a quantity of client stations that have currently joined the broadcast TWT schedule. The first communication device transmits the beacon frame to inform one or more second communication devices of i) the parameters of the broadcast TWT schedule and ii) the quantity of client stations that have currently joined the broadcast TWT schedule.

IPC Classes  ?

  • H04L 69/324 - Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions in the data link layer [OSI layer 2], e.g. HDLC
  • H04W 28/18 - Negotiating wireless communication parameters
  • H04W 52/02 - Power saving arrangements
  • H04W 84/12 - WLAN [Wireless Local Area Networks]

33.

Common-mode filtering for converting differential signaling to single-ended signaling

      
Application Number 17654316
Grant Number 11903123
Status In Force
Filing Date 2022-03-10
First Publication Date 2024-02-13
Grant Date 2024-02-13
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Huang, Shaowu
  • Wu, Dance

Abstract

An interface in a communications system includes a physical layer transceiver (PHY) for coupling to a wireline channel medium, and for coupling to a functional device via a single-ended cable. The PHY is an integrated circuit (IC) device having first and second differential input/output (I/O) conductors for coupling to the functional device, an impedance element configured to terminate a first one of the differential I/O conductors to a system ground, a second one of the differential I/O conductors being coupled to the single-ended cable, and a common-mode filter coupled to both of the differential I/O conductors. The PHY may further include a printed circuit board (PCB), with the IC device being mounted on the PCB, the first and second differential I/O conductors being signal traces on the PCB. The single-ended cable may be a coaxial cable.

IPC Classes  ?

34.

Circuit and Method for Timestamp Jitter Reduction

      
Application Number 17815635
Status Pending
Filing Date 2022-07-28
First Publication Date 2024-02-08
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Babitsky, Eliya
  • Noiman, Moran
  • Katz, Adi
  • Yehezkel, Yaakov
  • Halili, Ofer
  • Robinson, Tal

Abstract

A circuit and corresponding method generate a filtered timestamp. The circuit comprises recursive filter logic. The circuit generates the filtered timestamp from a received timestamp by filtering the received timestamp via the recursive filter logic. The recursive filter logic reduces jitter in the filtered timestamp relative to jitter of the received timestamp. The jitter represents a deviation of the received timestamp from a target (ideal) timestamp. The circuit outputs the filtered timestamp generated. The filtered timestamp is a more accurate representation of the target timestamp, relative to the received timestamp, due to the jitter reduced.

IPC Classes  ?

  • H04L 43/106 - Active monitoring, e.g. heartbeat, ping or trace-route using time related information in packets, e.g. by adding timestamps
  • H04L 43/087 - Jitter

35.

SILICON PHOTONICS INTEGRATION CIRCUIT

      
Application Number 17882888
Status Pending
Filing Date 2022-08-08
First Publication Date 2024-02-08
Owner MARVELL ASIA PTE LTD. (Singapore)
Inventor
  • Tu, Xiaoguang
  • Kato, Masaki
  • Li, Yu

Abstract

A silicon photonics integration circuit includes a silicon substrate member; a RX sub-circuit formed in the silicon substrate member including multiple RX-input ports each having a mode size converter configured to receive an incoming light signal into one of multiple waveguides and multiple RX photo detectors coupled respectively to the multiple waveguides; and a TX sub-circuit formed in the silicon substrate member including one or more TX-input ports each having a mode size converter coupled to a first TX photo detector into one input waveguide, one or more 1×2 directional couplers each coupled between the input waveguide and two mod-input waveguides, multiple modulators coupled between respective multiple mod-input waveguides and multiple mod-output waveguides each being coupled to a second TX photo detector into one of multiple output waveguides, and multiple TX-output ports each having a mode size converter coupled to respective one of the multiple output waveguides.

IPC Classes  ?

  • G02B 6/12 - Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
  • H04B 10/50 - Transmitters

36.

Mixed-Dimension Order Routing

      
Application Number 18154314
Status Pending
Filing Date 2023-01-13
First Publication Date 2024-02-08
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Viego, Anthony
  • Featherston, Joseph
  • Shreedhar, Aadeetya

Abstract

A circuit and corresponding method employ mixed-dimension order routing. The circuit comprises an interconnect, associated with a two-dimensional (2D) coordinate system, and a switch coupled to the interconnect. The switch determines a route path for a flit based on a mixed-dimension order routing method. The flit originates at an origin. The mixed-dimension order routing method employs, based on the origin of the flit, vertical-to-horizontal dimension routing or horizontal-to-vertical dimension routing. The switch routes the flit via the interconnect of the circuit based on the route path determined. The vertical-to-horizontal dimension routing and horizontal-to-vertical dimension routing are relative to the 2D coordinate system. The mixed-dimension order routing method prevents deadlock and congestion that otherwise degrade performance of the circuit.

IPC Classes  ?

  • H04L 49/109 - Integrated on microchip, e.g. switch-on-chip
  • H04L 47/122 - Avoiding congestion; Recovering from congestion by diverting traffic away from congested entities
  • H04L 45/58 - Association of routers
  • H04L 49/25 - Routing or path finding in a switch fabric

37.

Optimized path selection for multi-path groups

      
Application Number 18090288
Grant Number 11895015
Status In Force
Filing Date 2022-10-28
First Publication Date 2024-02-06
Grant Date 2024-02-06
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Budhia, Rupa
  • Matthews, William Brad
  • Agarwal, Puneet

Abstract

A packet to be forwarded over a computer network to a destination is received. A group of multiple network paths is available to forward to the packet to the destination. One or more path selection factors are determined to be used to identify a specific network load balancing algorithm to select a specific network path from the group of multiple network paths. The one or more path selection factors include at least one path selection factor determined based at least in part on a dynamic state of the computer network or a network node in the computer network. In response to selecting, by the specific network load balancing algorithm, the specific network path from among the group of multiple network paths, the packet is forwarded over the specific network path.

IPC Classes  ?

38.

Disk writing mode providing main pole relaxation

      
Application Number 18053470
Grant Number 11894025
Status In Force
Filing Date 2022-11-08
First Publication Date 2024-02-06
Grant Date 2024-02-06
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Wu, Kai
  • Oberg, Mats
  • Fang, Hao

Abstract

A method for writing data to a magnetic data storage medium includes detecting whether the duration, before occurrence of a data transition, of data to be written exceeds a predetermined threshold, and, when the duration, before the occurrence of the data transition, of the data to be written exceeds the predetermined threshold, writing the data by applying an initial pulse and then maintaining a steady-state write current for a defined interval, and when the duration, before the occurrence of the data transition, of the data to be written is at most equal to the predetermined threshold, writing the data by applying the initial pulse without applying a steady-state write current before the data transition. The predetermined threshold may be determined by size of a magnetic bubble formed when writing a single bit to the magnetic data storage medium. A subsequent pulse may be applied following the defined interval.

IPC Classes  ?

  • G11B 11/105 - Recording on, or reproducing from, the same record carrier wherein for these two operations the methods or means are covered by different main groups of groups or by different subgroups of group ; Record carriers therefor using recording by magnetisation or demagnetisation using a beam of light or a magnetic field for recording and a beam of light for reproducing, e.g. light-induced thermomagnetic recording or Kerr effect reproducing
  • G11B 7/00 - Recording or reproducing by optical means, e.g. recording using a thermal beam of optical radiation, reproducing using an optical beam at lower power; Record carriers therefor
  • G11B 5/012 - Recording on, or reproducing or erasing from, magnetic disks
  • G11B 5/49 - Fixed mountings

39.

Circuit and Method for Timestamp Filtering with Input/Output Format Conversion

      
Application Number 17815646
Status Pending
Filing Date 2022-07-28
First Publication Date 2024-02-01
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Babitsky, Eliya
  • Noiman, Moran
  • Katz, Adi
  • Yehezkel, Yaakov
  • Halili, Ofer
  • Robinson, Tal

Abstract

A circuit and corresponding method perform timestamp filtering. The circuit comprises input format-conversion logic that converts a received timestamp from an original format to an intermediate format. The circuit further comprises recursive filter logic coupled to the input format-conversion logic. The recursive filter logic generates a filtered timestamp in the intermediate format by filtering the received timestamp in the intermediate format. The circuit further comprises output format-conversion logic coupled to the recursive filter logic. The output format-conversion logic converts the filtered timestamp from the intermediate timestamp format to the original timestamp format and outputs the filtered timestamp in the original timestamp format. Converting the received timestamp into a different format avoids use of complex logic to handle rollover of input values, thereby reducing area and power consumption of the circuit.

IPC Classes  ?

40.

Circuit and Method for Timestamp Filtering with RLS Filter

      
Application Number 17815652
Status Pending
Filing Date 2022-07-28
First Publication Date 2024-02-01
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Babitsky, Eliya
  • Noiman, Moran
  • Katz, Adi
  • Yehezkel, Yaakov
  • Halili, Ofer
  • Robinson, Tal

Abstract

A circuit and corresponding method perform timestamp filtering. The circuit comprises recursive filter logic that implements a recursive least-squares (RLS) filter. The circuit (i) generates a filtered timestamp from a received timestamp by filtering the received timestamp via the recursive filter logic. The recursive filter logic applies the RLS filter to a portion of the received timestamp. A number of bits of the portion is less relative to a total number of bits of the received timestamp. The circuit outputs the filtered timestamp generated. Applying the RLS filter to the portion enables the circuit to be more efficient (e.g., smaller adders, fewer flipflops, etc.), thereby reducing area and power consumption of the circuit.

IPC Classes  ?

  • H04L 43/106 - Active monitoring, e.g. heartbeat, ping or trace-route using time related information in packets, e.g. by adding timestamps
  • H04L 43/087 - Jitter

41.

PROTOCOL INDEPENDENT PROGRAMMABLE SWITCH (PIPS) FOR SOFTWARE DEFINED DATA CENTER NETWORKS

      
Application Number 18378463
Status Pending
Filing Date 2023-10-10
First Publication Date 2024-02-01
Owner Marvell Asia PTE, LTD (Singapore)
Inventor
  • Hutchison, Guy Townsend
  • Gandhi, Sachin Ramesh
  • Daniel, Tsahi
  • Schmidt, Gerald
  • Fishman, Albert
  • White, Martin Leslie
  • Shah, Zubin

Abstract

A software-defined network (SDN) system, device and method comprise one or more input ports, a programmable parser, a plurality of programmable lookup and decision engines (LDEs), programmable lookup memories, programmable counters, a programmable rewrite block and one or more output ports. The programmability of the parser, LDEs, lookup memories, counters and rewrite block enable a user to customize each microchip within the system to particular packet environments, data analysis needs, packet processing functions, and other functions as desired. Further, the same microchip is able to be reprogrammed for other purposes and/or optimizations dynamically.

IPC Classes  ?

  • H04L 49/109 - Integrated on microchip, e.g. switch-on-chip
  • G06F 3/06 - Digital input from, or digital output to, record carriers
  • H04L 45/64 - Routing or path finding of packets in data switching networks using an overlay routing layer
  • H04L 45/745 - Address table lookup; Address filtering
  • H04L 49/1546 - Non-blocking multistage, e.g. Clos using pipelined operation
  • H04L 69/22 - Parsing or analysis of headers
  • H04L 49/00 - Packet switching elements
  • G06F 16/00 - Information retrieval; Database structures therefor; File system structures therefor
  • H04L 45/74 - Address processing for routing
  • G06F 40/205 - Parsing
  • H04L 67/63 - Routing a service request depending on the request content or context

42.

Aggregation of frames for transmission in a wireless communication network

      
Application Number 17353144
Grant Number 11889488
Status In Force
Filing Date 2021-06-21
First Publication Date 2024-01-30
Grant Date 2024-01-30
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Chu, Liwen
  • Zheng, Xiayu
  • Zhang, Hongyuan
  • Lou, Hui-Ling

Abstract

A first communication device determines that a trigger frame and another frame are to be transmitted to at least a second communication device. The first communication device determines whether the second communication device announced support of aggregation of buffer status report (BSRP) trigger frames with additional frames. In response to the first communication device determining that the second communication device announced support of aggregation of BSRP trigger frames with additional frames, the first communication device generates an aggregate media access control protocol data unit (A-MPDU) to include the BSRP trigger frame and the other frame, and transmits the A-MPDU within a packet. In response to the first communication device determining that the second communication device did not announce support of aggregation of BSRP trigger frames with additional frames, the first communication device transmits a packet having only the BSRP trigger frame.

IPC Classes  ?

  • H04L 5/00 - Arrangements affording multiple use of the transmission path
  • H04W 72/0453 - Resources in frequency domain, e.g. a carrier in FDMA
  • H04W 84/12 - WLAN [Wireless Local Area Networks]

43.

METHOD, SYSTEM AND DEVICE OF SERIALIZING AND DE-SERIALIZING THE DELIVERY OF SCAN TEST DATA THROUGH CHIP I/O TO REDUCE THE SCAN TEST DURATION OF AN INTEGRATED CIRCUIT

      
Application Number 17869495
Status Pending
Filing Date 2022-07-20
First Publication Date 2024-01-25
Owner MARVELL ASIA PTE LTD. (Singapore)
Inventor
  • Biswas, Sounil
  • Wangoo, Amit
  • Zhong, Zhanwei

Abstract

An integrated circuit verification system including automatic test equipment (ATE) and a device under test (DUT) having an internal test data de-serializer and test response data serializer. Specifically, the de-serializer of the DUT is able to de-serialize a test pattern or scan test data generated and received from an ATE at a general-purpose I/O pin (or functional pin) of the DUT for testing a circuit under test (CUT) of the DUT and then serialize the response to the test data with the serializer for output back to the ATE via the same or a different general-purpose I/O pin (or functional pin) of the DUT.

IPC Classes  ?

44.

A METHOD OF USING BIT VECTORS TO ALLOW EXPANSION AND COLLAPSE OF HEADER LAYERS WITHIN PACKETS FOR ENABLING FLEXIBLE MODIFICATIONS AND AN APPARATUS THEREOF

      
Application Number 18370821
Status Pending
Filing Date 2023-09-20
First Publication Date 2024-01-18
Owner Marvell Asia Pte., Ltd. (Singapore)
Inventor
  • Singh, Chirinjeev
  • Daniel, Tsahi
  • Schmidt, Gerald

Abstract

Embodiments of the apparatus for modifying packet headers relate to a use of bit vectors to allow expansion and collapse of protocol headers within packets for enabling flexible modification. A rewrite engine expands each protocol header into a generic format and applies various commands to modify the generalized protocol header. The rewrite engine maintains a bit vector for the generalized protocol header with each bit in the bit vector representing a byte of the generalized protocol header. A bit marked as 0 in the bit vector corresponds to an invalid byte, while a bit marked as 1 in the bit vector corresponds to a valid byte. The rewrite engine uses the bit vector to remove all the invalid bytes after all commands have been operated on the generalized protocol header to thereby form a new protocol header.

IPC Classes  ?

  • H04L 69/22 - Parsing or analysis of headers
  • H04L 69/04 - Protocols for data compression, e.g. ROHC
  • H04L 49/00 - Packet switching elements
  • H04L 69/08 - Protocols for interworking; Protocol conversion

45.

Optical transceiver with multimode interferometers

      
Application Number 18353084
Status Pending
Filing Date 2023-07-16
First Publication Date 2024-01-18
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Wang, Yun
  • Cai, Hong
  • Lin, Nathan
  • Lin, Jie

Abstract

An optical transceiver includes optical circuitry disposed on a substrate and comprising a transmitter and a receiver. The circuitry includes least one multi-mode interferometer (MMI), including a multi-mode waveguide comprising an input face and an output face, the input and output faces being bisected by a longitudinal axis, the multi-mode waveguide having a predefined width transverse to the longitudinal axis. Ports are coupled to respective waveguides and are configured to launch one or more input beams through the input face and receive one or more output beams from the output face. The ports include, on at least one of the faces, two or more ports at respective locations that are offset transversely from the longitudinal axis by at least λ0/300 from respective base transverse displacements that are equal to integer fractions of the width.

IPC Classes  ?

  • H04B 10/40 - Transceivers
  • H04B 10/11 - Arrangements specific to free-space transmission, i.e. transmission through air or vacuum
  • G02B 6/293 - Optical coupling means having data bus means, i.e. plural waveguides interconnected and providing an inherently bidirectional system by mixing and splitting signals with wavelength selective means

46.

Method and apparatus for determining bit-error rate in a data channel

      
Application Number 17815415
Grant Number 11876532
Status In Force
Filing Date 2022-07-27
First Publication Date 2024-01-16
Grant Date 2024-01-16
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Chen, Yuanjie
  • Visani, Davide
  • Wu, Min

Abstract

A method for determining a bit-error rate in data received on high-speed data channel that uses a forward-error-correcting decoder includes receiving at receiver circuitry on the high-speed data channel a received predetermined data pattern, comparing, bit-wise, the received predetermined data pattern to a locally generated copy of the predetermined data pattern to derive output bits representing whether there was an error in a corresponding bit of the received predetermined data pattern, to determine error bits in the received predetermined data pattern, grouping output bits from the comparing into symbols and codewords, and for each codeword for which a count of symbols containing errors exceeds a number of symbols correctable by the forward-error-correcting decoder, counting a total number of bit errors contained in the symbols containing errors, for use in adjusting the receiver circuitry in response to the total number of bit errors.

IPC Classes  ?

  • H03M 13/01 - Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
  • H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
  • H03M 13/15 - Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes

47.

Bandwidth indication, negotiation and TXOP protection with multiple channel segments

      
Application Number 17857945
Grant Number 11877274
Status In Force
Filing Date 2022-07-05
First Publication Date 2024-01-16
Grant Date 2024-01-16
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Chu, Liwen
  • Zhang, Hongyuan
  • Lou, Hui-Ling

Abstract

A communication device generates a first packet to include a first indication of one or more first frequency subchannels in a first frequency segment that will be utilized to transmit the first packet. The communication device also generates a second packet to include a second indication of one or more second frequency subchannels in a second frequency segment that will be utilized to transmit the second packet. The communication device simultaneously transmits the first packet via the first frequency segment and the second packet via the second frequency segment.

IPC Classes  ?

  • H04W 72/0453 - Resources in frequency domain, e.g. a carrier in FDMA
  • H04L 5/00 - Arrangements affording multiple use of the transmission path
  • H04W 72/23 - Control channels or signalling for resource management in the downlink direction of a wireless link, i.e. towards a terminal
  • H04W 74/08 - Non-scheduled access, e.g. random access, ALOHA or CSMA [Carrier Sense Multiple Access]
  • H04W 84/12 - WLAN [Wireless Local Area Networks]
  • H04L 1/1607 - Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals - Details of the supervisory signal
  • H04L 69/22 - Parsing or analysis of headers
  • H04L 101/622 - Layer-2 addresses, e.g. medium access control [MAC] addresses

48.

INTEGRATED CIRCUIT DEVICE EXPOSED DIE PACKAGE STRUCTURE WITH ADHESIVE

      
Application Number US2023027010
Publication Number 2024/010859
Status In Force
Filing Date 2023-07-06
Publication Date 2024-01-11
Owner MARVELL ASIA PTE LTD (Singapore)
Inventor Chee, Choong Kooi

Abstract

An integrated circuit (IC) device package includes a structure having a base and walls extending from the base, at least one IC die mounted to the base within the walls, each die having a top surface parallel to the base and having a thickness extending along an axis, perpendicular to the top surface, at most equal to a height of the walls, a thermally conductive heat spreader extending parallel to the base above the die and the walls, and an interface layer including an adhesive layer portion disposed between the walls and the heat spreader to adhere the heat spreader to the walls, and a thermal interface material (TIM) layer portion coplanar with, and laterally displaced from, the adhesive layer portion, the TIM layer portion being disposed in thermally conductive relationship between the heat spreader and each respective die, to dissipate heat from each respective die to the heat spreader.

IPC Classes  ?

  • H01L 23/367 - Cooling facilitated by shape of device
  • H01L 23/373 - Cooling facilitated by selection of materials for the device
  • H01L 23/42 - Fillings or auxiliary members in containers selected or arranged to facilitate heating or cooling

49.

BLOCK ACKNOWLEDGMENT OPERATION

      
Application Number 18237785
Status Pending
Filing Date 2023-08-24
First Publication Date 2024-01-11
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Chu, Liwen
  • Ho, Ken Kinwah
  • Zhang, Hongyuan
  • Lou, Hui-Ling

Abstract

A first communication device transmits first bitmap length capability information for the first communication device regarding block acknowledgment procedures, and receives second bitmap length capability information for a second communication device regarding block acknowledgment procedures. The first communication device performs a block acknowledgment procedure, including setting a block acknowledgment transmission window size for the block acknowledgment procedure based on the second bitmap length capability information for the second communication device, and a determination of whether a block acknowledgement frame used in the block acknowledgment procedure is a compressed block acknowledgement (C-BA) frame or a multi-station (multi-STA) block acknowledgement frame.

IPC Classes  ?

  • H04L 1/1607 - Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals - Details of the supervisory signal
  • H04L 1/1829 - Arrangements specially adapted for the receiver end
  • H04L 1/1867 - Arrangements specially adapted for the transmitter end
  • H04B 7/26 - Radio transmission systems, i.e. using radiation field for communication between two or more posts at least one of which is mobile
  • H04L 5/00 - Arrangements affording multiple use of the transmission path

50.

INTEGRATED CIRCUIT DEVICE EXPOSED DIE PACKAGE STRUCTURE WITH ADHESIVE

      
Application Number 18348041
Status Pending
Filing Date 2023-07-06
First Publication Date 2024-01-11
Owner Marvell Asia Pte Ltd (Singapore)
Inventor Chee, Choong Kooi

Abstract

An integrated circuit (IC) device package includes a structure having a base and walls extending from the base, at least one IC die mounted to the base within the walls, each die having a top surface parallel to the base and having a thickness extending along an axis, perpendicular to the top surface, at most equal to a height of the walls, a thermally conductive heat spreader extending parallel to the base above the die and the walls, and an interface layer including an adhesive layer portion disposed between the walls and the heat spreader to adhere the heat spreader to the walls, and a thermal interface material (TIM) layer portion coplanar with, and laterally displaced from, the adhesive layer portion, the TIM layer portion being disposed in thermally conductive relationship between the heat spreader and each respective die, to dissipate heat from each respective die to the heat spreader.

IPC Classes  ?

  • H01L 23/373 - Cooling facilitated by selection of materials for the device
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
  • H01L 23/367 - Cooling facilitated by shape of device

51.

System and methods for latency reduction for fuse reload post reset

      
Application Number 17086371
Grant Number 11868475
Status In Force
Filing Date 2020-10-31
First Publication Date 2024-01-09
Grant Date 2024-01-09
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Sundararaman, Ramacharan
  • Miyar, Nithyananda
  • Kovac, Martin
  • Sodani, Avinash
  • Shivaraj, Raghuveer

Abstract

A new approach is proposed that contemplates systems and methods to support post reset fuse reload for latency reduction. First, values of fuses are read once and stored into one or more load registers on an electronic device, wherein the load registers are protected. Once the values of the fuse are loaded into the load registers, a valid indicator of the load registers is set indicating that the values have been successfully loaded into the load registers. When other components of the electronic device need to access these values, the other components will check the load registers first. If it is determined that the valid indicator of the load registers is set, the stored values are read from the load registers instead of from the fuses. If the valid indicator of the load registers is not set, the values are loaded again from the fuses into the load registers.

IPC Classes  ?

  • G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
  • G06F 9/4401 - Bootstrapping

52.

Frequency division multiple access (FDMA) support for wakeup radio (WUR) operation

      
Application Number 17991494
Grant Number 11871348
Status In Force
Filing Date 2022-11-21
First Publication Date 2024-01-09
Grant Date 2024-01-09
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Chu, Liwen
  • Cao, Rui
  • Zhang, Hongyuan
  • Lou, Hui-Ling

Abstract

A wireless network interface of a first client station negotiates with an access point a first component channel of an operating channel via which the first client station is to receive wakeup frames from the access point. A wakeup radio of the first client station receives a wakeup packet from the access point. The wakeup packet spans the operating channel, which comprises at least four component channels, and one or more of the component channels within the operating channel are punctured so that the access point does not transmit the wakeup packet in the one or more component channels that are punctured. The wakeup packet includes a first wakeup frame for the first client station in the first component channel and one or more respective second wakeup frames for one or more second client stations in one or more respective second component channels.

IPC Classes  ?

53.

Network device using cache techniques to process control signals

      
Application Number 17698196
Grant Number 11868282
Status In Force
Filing Date 2022-03-18
First Publication Date 2024-01-09
Grant Date 2024-01-09
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Sonksen, Bradley
  • Nitza, Paul

Abstract

A network controller for coupling a host device to a data network, in accordance with network command blocks initiated in a request queue in the host device, includes a channel interface configured to couple to the data network, where the channel interface includes memory configured to store the network command blocks and processing circuitry configured to execute the network command blocks to move data between the host device and the data network, and a host interface configured to couple the network controller to the host device, and to move the network command blocks from the request queue in the host device to the memory using cache operations, including fetching one of the network command blocks from the request queue upon receipt from the host device of a message advising that a request queue location has changed.

IPC Classes  ?

  • G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
  • G06F 12/0831 - Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means

54.

Systems and methods for introducing time diversity in Wifi transmissions

      
Application Number 17536381
Grant Number 11870579
Status In Force
Filing Date 2021-11-29
First Publication Date 2024-01-09
Grant Date 2024-01-09
Owner Marvell Asia Pte, Ltd. (Singapore)
Inventor
  • Sun, Yakun
  • Zhang, Hongyuan
  • Chu, Liwen
  • Lou, Hui-Ling

Abstract

Systems and methods are provided for introducing time diversity in a transmitter. The systems and methods may include receiving, at the transmitter, a request from a receiver to retransmit data. The systems and methods may further include receiving an input of data corresponding to the data requested for retransmission at a first transmitter block. The systems and methods may further include operating on the signals using the first transmitter block in at least one of a first mode and a second mode, such that an output of signals from the first transmitter block is dependent on a time-varying function and corresponds to the data requested by the receiver for retransmission.

IPC Classes  ?

  • H04L 1/00 - Arrangements for detecting or preventing errors in the information received
  • H04L 1/1867 - Arrangements specially adapted for the transmitter end
  • H04L 1/1825 - Adaptation of specific ARQ protocol parameters according to transmission conditions
  • H04L 1/08 - Arrangements for detecting or preventing errors in the information received by repeating transmission, e.g. Verdan system
  • H04B 7/06 - Diversity systems; Multi-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station

55.

PHYSICAL LAYER FRAME FORMAT FOR WLAN

      
Application Number 18244792
Status Pending
Filing Date 2023-09-11
First Publication Date 2023-12-28
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Zhang, Hongyuan
  • Lou, Hui-Ling
  • Nabar, Rohit U.
  • Srinivasa, Sudhir
  • Yu, Mao
  • Banerjea, Raja

Abstract

A preamble of physical layer (PHY) data unit includes a first legacy portion and a first non-legacy portion that follows the first legacy portion. The first non-legacy portion includes i) a first orthogonal frequency division multiplexing (OFDM) symbol that immediately follows the first legacy portion and that is modulated using binary phase shift keying (BPSK), and ii) a second OFDM symbol that immediately follows the first OFDM symbol and that is modulated using BPSK modulation rotated by 90 degrees (Q-BPSK). The modulation of the first and second OFDM symbols indicates to a receiver device that conforms to a first communication protocol that the data unit conforms to the first communication protocol. The first OFDM symbol being modulated using BPSK modulation causes a receiver device that conforms to a second communication protocol to determine that the PHY data unit conforms to a third communication protocol.

IPC Classes  ?

  • H04L 1/00 - Arrangements for detecting or preventing errors in the information received
  • H04L 27/26 - Systems using multi-frequency codes
  • H04L 69/18 - Multiprotocol handlers, e.g. single devices capable of handling multiple protocols
  • H04W 28/06 - Optimising, e.g. header compression, information sizing

56.

COMMUNICATION DEVICE WITH INTERLEAVED ENCODING FOR FEC ENCODED DATA STREAMS

      
Application Number 18244880
Status Pending
Filing Date 2023-09-11
First Publication Date 2023-12-28
Owner Marvell Asia Pte Ltd. (Singapore)
Inventor
  • Smith, Benjamin P.
  • Shvydun, Volodymyr
  • Riani, Jamal
  • Lyubomirsky, Ilya

Abstract

A communication device includes a convolutional interleaver and an encoder. The convolutional interleaver is configured to receive blocks of data defining symbol blocks that are encoded using a block code to correct an error in a block of data and to interleave the symbol blocks into a stream of interleaved symbol blocks. The encoder is configured to encode a set of symbol blocks among the interleaved symbol blocks with an error-correcting code to correct single bit errors in the set of symbol blocks. The error-correcting code is configured to generate an error-correcting block and to add the error-correcting block to the set of interleaved symbol blocks.

IPC Classes  ?

  • H03M 13/27 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
  • H03M 13/15 - Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes

57.

Lossless integer compression scheme

      
Application Number 17197268
Grant Number 11854235
Status In Force
Filing Date 2021-03-10
First Publication Date 2023-12-26
Grant Date 2023-12-26
Owner Marvell Asia Pte, Ltd. (Singapore)
Inventor Lu, Tao

Abstract

Decompressing a compressed image to obtain a decompressed image includes receiving, in a compressed stream, compressed pixel values of the compressed image; decompressing, from the compressed stream, a first compressed pixel value of the compressed pixel values using a lossy floating-point decompression scheme to obtain a floating-point pixel value; rounding the floating-point pixel value to a nearest integer to obtain a pixel value of the decompressed image; and displaying or storing the decompressed image.

IPC Classes  ?

  • G06K 9/36 - Image preprocessing, i.e. processing the image information without deciding about the identity of the image
  • G06T 9/00 - Image coding
  • H03M 7/30 - Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
  • G06T 3/40 - Scaling of a whole image or part thereof

58.

Adaptive orthogonal frequency division multiplexing (OFDM) numerology in a wireless communication network

      
Application Number 14701208
Grant Number 11855818
Status In Force
Filing Date 2015-04-30
First Publication Date 2023-12-26
Grant Date 2023-12-26
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Sun, Yakun
  • Zhang, Hongyuan
  • Xu, Mingguang
  • Lou, Hui-Ling

Abstract

In a method for adapting an orthogonal frequency division multiplexing (OFDM) numerology configuration for use in a communication network one or more OFDM numerology configurations are adaptively selected at a first communication device to be used in communication with one or more second communication devices. Adaptively one or more OFDM numerology configurations includes selecting at least one combination of two or more of (i) a guard interval duration, (ii) a tone spacing, (iii) a starting location of the selected guard interval duration, and (iv) a starting location of the selected tone spacing. A physical layer (PHY) data unit to be transmitted to a second communication device is generated at the first communication device. The PHY data unit is generated using one of the one or more adaptively selected OFDM numerology configurations to generate OFDM symbols of at least a portion of the PHY data unit.

IPC Classes  ?

  • H04L 27/26 - Systems using multi-frequency codes
  • H04L 5/00 - Arrangements affording multiple use of the transmission path
  • H04W 84/12 - WLAN [Wireless Local Area Networks]

59.

Automotive asymmetric ethernet using frequency-division duplex

      
Application Number 18460546
Status Pending
Filing Date 2023-09-03
First Publication Date 2023-12-21
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Wu, Xing
  • Dai, Shaoan
  • Wu, Dance
  • Chu, William

Abstract

An Ethernet Physical Layer (PHY) device includes a link interface and a transceiver. The link interface is configured to connect to a full-duplex wired Ethernet link. The transceiver is configured to receive first Ethernet signals carrying first data at a first data rate over the Ethernet link in a first direction, the first Ethernet signals occupying a first frequency band, and to transmit second Ethernet signals carrying second data at a second data rate different from the first data rate, over the Ethernet link in a second direction that is opposite the first direction, the second Ethernet signals occupying a second frequency band that is different from the first frequency band.

IPC Classes  ?

  • H04L 5/14 - Two-way operation using the same type of signal, i.e. duplex
  • H04B 3/23 - Reducing echo effects or singing; Opening or closing transmitting path; Conditioning for transmission in one direction or the other using a replica of transmitted signal in the time domain, e.g. echo cancellers
  • H04L 7/04 - Speed or phase control by synchronisation signals

60.

ESSENTIAL TECHNOLOGY, DONE RIGHT

      
Serial Number 98321720
Status Pending
Filing Date 2023-12-19
Owner Marvell Asia Pte, Ltd. (Singapore)
NICE Classes  ? 25 - Clothing; footwear; headgear

Goods & Services

Clothing, namely, shirts, tank tops, shorts, pants, clothing jerseys, clothing jackets, vests, hooded pullovers, cycling shorts, cycling bib shorts, cycling gloves, triathlon suits, arm warmers, and leg warmers; headwear; neckwear; shoe accessories, namely, fitted decorative covers for shoes

61.

Shift-register-based clock phase interpolator

      
Application Number 17455784
Grant Number 11849015
Status In Force
Filing Date 2021-11-19
First Publication Date 2023-12-19
Grant Date 2023-12-19
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Zhao, Hui
  • Guo, Zhendong

Abstract

An integrated circuit device includes functional circuitry, and serializer/deserializer circuitry for serial communication with the functional circuitry. The serializer/deserializer circuitry includes phase interpolator circuitry for interpolating phases of a clock signal of the integrated circuit device. The phase interpolator circuitry includes a phase shift register having storage locations configured to represent the phases of the clock signal, and phase rotation control circuitry configured to decode a phase code signal to determine a shifting direction for phase selections in storage locations of the phase shift register. The phase rotation control circuitry may be configured to determine the shifting direction based on only the most significant bit and the second most significant bit of the phase code signal. The phase interpolator circuitry may further include weight decoder circuitry configured to derive, from the phase code signal, interpolation weights to control combination of selected phases of the clock signal.

IPC Classes  ?

  • H04L 7/00 - Arrangements for synchronising receiver with transmitter

62.

Method And Device For High Bandwidth Receiver For High Baud-Rate Communications

      
Application Number 18236675
Status Pending
Filing Date 2023-08-22
First Publication Date 2023-12-14
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Dallaire, Stephane
  • Nguyen, Ray Luan
  • Hatcher, Geaffrey

Abstract

An analog front-end (AFE) device and method for a high baud-rate receiver. The device can include an input matching network coupled to a first buffer device, which is coupled to a sampler array. The input matching network can include a first T-coil configured to receive a first input and a second T-coil configured to receive a second input. The first buffer device can include one or more buffers each having a bias circuit coupled to a first class-AB source follower and a second class-AB source follower. The sampling array can include a plurality of sampler devices configured to receive a multi-phase clocking signal. Additional optimization techniques can be used, such as having a multi-tiered sampler array and having the first buffer device configured with separate buffers for odd and even sampling phases. Benefits of this AFE configuration can include increased bandwidth, sampling rate, and power efficiency.

IPC Classes  ?

  • H03H 7/38 - Impedance-matching networks
  • H04B 1/16 - Circuits
  • H03F 3/19 - High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only

63.

LOW LOSS AND STABLE PLANAR LIGHTWAVE CIRCUIT ATTACHEMENT WITH SILICON INTERPOSER

      
Application Number US2023024685
Publication Number 2023/239774
Status In Force
Filing Date 2023-06-07
Publication Date 2023-12-14
Owner MARVELL ASIA PTE., LTD. (Singapore)
Inventor
  • Wang, Hsiu-Che
  • Tumne, Pushkraj
  • Shirley, Dwayne R.
  • Coccioli, Roberto
  • Fu, Peikeng

Abstract

An optical signal transceiver includes a circuit board substrate, a silicon photonics-based interposer mounted on the circuit board substrate, the silicon photonics-based interposer including at least one of a waveguide configured to transmit optical communication signals and a photo detector configured to detect optical communication signals, and a planar lightwave circuit disposed on the circuit board substrate. The planar lightwave circuit is configured to perform at least a portion of propagation of light signals in an optical communication network, and the planar lightwave circuit is aligned with a side surface of the silicon photonics-based interposer to transmit optical communication signals between the silicon photonics-based interposer and the planar lightwave circuit. The optical signal transceiver includes at least one spacer component disposed between the planar lightwave circuit and the circuit board substrate, and epoxy material in contact with the spacer component.

IPC Classes  ?

  • G02B 6/42 - Coupling light guides with opto-electronic elements
  • G02B 6/255 - Splicing of light guides, e.g. by fusion or bonding

64.

CO-PACKAGING OPTICAL MODULES WITH SURFACE AND EDGE COUPLING

      
Application Number 18227180
Status Pending
Filing Date 2023-07-27
First Publication Date 2023-12-14
Owner Marvell Asia Pie Ltd (Singapore)
Inventor
  • Nagarajan, Radhakrishnan L.
  • Patterson, Mark

Abstract

An assembled electro-optical switch module includes a package substrate. Four optical socket members are disposed respectively to the package substrate. Each optical socket member includes four sockets closely packed in a row. Each socket has a recessed flat region with topside land grid array (LGA) interposer connected to bottom side solder bumps and a side notch opening aligned to an edge of the package substrate at the corresponding edge region. Sixteen optical modules in four sets are co-packaged in the package substrate. Each set has four optical modules respectively seated in the four sockets of each optical socket member with top side LGA interposer. Four clamp latch members are applied to clamp each of the four sets of optical modules in respective optical socket members. A data processor device with 51.2 Tbps data interface is disposed to the package substrate and electrically coupled to each of the sixteen optical module.

IPC Classes  ?

  • G02B 6/43 - Arrangements comprising a plurality of opto-electronic elements and associated optical interconnections
  • G02B 6/42 - Coupling light guides with opto-electronic elements

65.

United states test controller for system-on-chip validation

      
Application Number 17655706
Grant Number 11841396
Status In Force
Filing Date 2022-03-21
First Publication Date 2023-12-12
Grant Date 2023-12-12
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Vaidya, Sameer
  • Katchmart, Supaket
  • Khanzode, Vivek
  • Joshi, Pallavi
  • Sutioso, Henri
  • Siemsen-Schumann, Naim
  • Sheng, Hongying

Abstract

A storage device controller includes drive controller circuitry configured to control writing and fetching of data from a storage medium, read data channel circuitry for interfacing between the drive controller circuitry and the storage medium, test controller circuitry configured to test the read data channel circuitry by issuing test commands simulating the writing and fetching of data from the storage medium, and selector circuitry configured to switchably couple the read data channel circuitry to the drive controller circuitry in an operating mode and to the test controller circuitry in a testing mode. The storage device controller may include a pattern generator configured to output the test commands. Processor circuitry may be configured to store test results in memory, to compute performance metrics from the stored test results, and communicate the performance metrics to a host device.

IPC Classes  ?

66.

Managing out-of-order retirement of instructions based on received instructions indicating start or stop to out-of-order retirement

      
Application Number 17515712
Grant Number 11842198
Status In Force
Filing Date 2021-11-01
First Publication Date 2023-12-12
Grant Date 2023-12-12
Owner Marvell Asia Pte, Ltd. (Singapore)
Inventor Mukherjee, Shubhendu Sekhar

Abstract

Retiring instructions out-of-order includes: receiving processor instructions comprising two or more and fewer than all processor instructions generated based on a program, where the processor instructions include a first instruction and a second instruction such that the first instruction precedes the second instruction in a program order of the program; receiving a start instruction that immediately precedes the processor instructions and indicates that the processor instructions are to be retired out-of-order; receiving a stop instruction immediately that succeeds the processor instructions and indicates a stop to out-of-order instruction retirement; and, in response to completing execution of the second instruction before completing execution of the first instruction, retiring the second instruction before retiring the first instruction.

IPC Classes  ?

  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline, look ahead
  • G06F 9/32 - Address formation of the next instruction, e.g. by incrementing the instruction counter
  • G06F 8/41 - Compilation
  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode

67.

Managing Power in an Integrated Circuit for High-Speed Activation

      
Application Number 18454151
Status Pending
Filing Date 2023-08-23
First Publication Date 2023-12-07
Owner Marvell Asia Pte, Ltd. (Singapore)
Inventor
  • Mukherjee, Shubhendu Sekhar
  • Chu, William

Abstract

Controlling a vehicle comprises: providing, from an activation port, an activation signal for activating control of at least one of one or more electronically controllable devices during a high-speed activation time interval; and managing power consumed by an integrated circuit that includes two or more processor cores during the high-speed activation time interval. The managing includes: receiving the activation signal from the activation port, in response to the activation signal, executing at least a portion of stored code by a first subset of fewer than all of the processor cores at a first power level, and after the high-speed activation time interval, executing at least a portion of the stored code by a second subset of one or more of the processor cores at a second power level lower than the first power level.

IPC Classes  ?

  • B60R 16/03 - Electric or fluid circuits specially adapted for vehicles and not otherwise provided for; Arrangement of elements of electric or fluid circuits specially adapted for vehicles and not otherwise provided for electric for supply of electrical power to vehicle subsystems
  • G06F 1/324 - Power saving characterised by the action undertaken by lowering clock frequency
  • G06F 9/4401 - Bootstrapping
  • G06F 1/3293 - Power saving characterised by the action undertaken by switching to a less power-consuming processor, e.g. sub-CPU

68.

System and methods for hardware-based PCIe link up based on post silicon characterization

      
Application Number 18098388
Grant Number 11836501
Status In Force
Filing Date 2023-01-18
First Publication Date 2023-12-05
Grant Date 2023-12-05
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Sundararaman, Ramacharan
  • Miyar, Nithyananda

Abstract

A new approach is proposed to support hardware-based PCIe link up based on post silicon characterization of an electronic device. A non-volatile storage medium of a bootup unit on the electronic device maintains an initialization sequence for the physical layer of a PCIe link, and a non-volatile storage medium allows flexible programming. During operation, the bootup unit reads from the non-volatile storage medium instructions to program/override one or more PCIe physical layer settings and controller registers for the PCIe link based on the post silicon characterization of the electronic device. The bootup unit is limited to access and override only to the one or more physical layer settings and controller registers of the PCIe link. The entire process of reading the initialization sequence and programming the one or more PCIe physical layer settings and the controller registers happens within time limit constraints of the PCIe specification for latency reduction.

IPC Classes  ?

  • G06F 9/4401 - Bootstrapping
  • G06F 9/445 - Program loading or initiating
  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
  • G06F 13/40 - Bus structure
  • G06F 13/42 - Bus transfer protocol, e.g. handshake; Synchronisation

69.

Method of manufacturing and packaging silicon photonics integrated circuit dies in wafer form

      
Application Number 16920069
Grant Number 11837509
Status In Force
Filing Date 2020-07-02
First Publication Date 2023-12-05
Grant Date 2023-12-05
Owner MARVELL ASIA PTE LTD (Singapore)
Inventor
  • Chou, Hsu-Feng
  • Nellis, Keith
  • Nguyen, Loi

Abstract

A method of packaging the silicon photonics wafer for fabricating custom optical-electrical modules includes fabricating a wafer with multiple dies of silicon photonics circuits based on custom design and conducting electrical and optical tests of the silicon photonics circuits in wafer level. The method further includes preparing the wafer for next point of use. Additionally, the method includes performing post-wafer processing on the wafer received at the next point of use. The method further includes conducting post-process electrical tests of the silicon photonics circuits in wafer level. Furthermore, the method includes preparing the wafer with known-good-dies or a known-good-wafer identified for custom use. Moreover, the method includes performing custom process on the know good dies.

IPC Classes  ?

  • H01L 31/02 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof - Details
  • H01L 21/66 - Testing or measuring during manufacture or treatment
  • G02B 6/13 - Integrated optical circuits characterised by the manufacturing method
  • G01M 11/00 - Testing of optical apparatus; Testing structures by optical methods not otherwise provided for
  • H01L 31/0232 - Optical elements or arrangements associated with the device
  • H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof

70.

Managing address collision in a network device

      
Application Number 17841703
Grant Number 11838265
Status In Force
Filing Date 2022-06-16
First Publication Date 2023-12-05
Grant Date 2023-12-05
Owner MARVELL ASIA PTE LTD (Singapore)
Inventor
  • Parmar, Harivaden
  • Ovchinnikov, Gleb
  • Mann, Jessica Lauren

Abstract

A network device includes a memory, a memory access circuit, and a processor. The memory is configured to store a hash table for accessing a database of network addresses, the hash table including multiple buckets, each bucket dimensioned to store entries for up to a maximal permitted number of the network addresses. The memory access circuit is configured to receive a network address, to calculate a hash value over at least the network address by applying a hashing scheme selected from among a plurality of hashing schemes, to choose a bucket of the hash table based on the hash value, and to access information in the database pertaining to the network address by accessing the selected bucket. The processor is configured to select the hashing scheme to ensure that none of the buckets will be mapped to more than the maximal permitted number of the network addresses.

IPC Classes  ?

  • G06F 12/1018 - Address translation using page tables, e.g. page table structures involving hashing techniques, e.g. inverted page tables
  • G06F 12/0864 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing
  • H04L 61/5046 - Resolving address allocation conflicts; Testing of addresses
  • H04L 9/06 - Arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for blockwise coding, e.g. D.E.S. systems
  • H04L 9/40 - Network security protocols
  • H04L 61/5007 - Internet protocol [IP] addresses

71.

IMPROVED ENERGY EFFICIENT ETHERNET (EEE) OPERATION

      
Application Number US2023023281
Publication Number 2023/230096
Status In Force
Filing Date 2023-05-23
Publication Date 2023-11-30
Owner
  • MARVELL ASIA PTE LTD (Singapore)
  • MARVELL SEMICONDUCTOR, INC. (USA)
Inventor
  • Mcclellan, Brett Anthony
  • Wu, Xing
  • Zimmerman, George

Abstract

A network interface device operates in a normal transmit operating mode in which the network interface device continually receives transmission symbols from a link partner via the communication link. The network interface device determines that receive circuitry of the network interface device is to transition to a low power mode in response to receiving a sleep signal from the link partner. The network interface device then operates according to a quiet/refresh cycle of the low power mode to conserve power. The quiet/refresh cycle corresponds to a time schedule that includes a refresh time window in which receive circuitry of the network interface device is to be powered to receive a refresh signal from the link partner. Immediately after transmission of the sleep signal, the network interface device transitions to a quiet time window of the time schedule in which the network interface device ignores transmissions from the link partner.

IPC Classes  ?

  • H04L 12/12 - Arrangements for remote connection or disconnection of substations or of equipment thereof

72.

ASSOCIATIVELY INDEXED CIRCULAR BUFFER

      
Application Number 18232531
Status Pending
Filing Date 2023-08-10
First Publication Date 2023-11-30
Owner Marvell Asia Pte Ltd (Singapore)
Inventor Said, Lawrence

Abstract

Some embodiments of the present disclosure provide an associatively indexed circular buffer (ACB). The ACB may be viewed as a dynamically allocatable memory structure that offers in-order data access (say, first-in-first-out, or “FIFO”) or random order data access at a fixed, relatively low latency. The ACB includes a data store of non-contiguous storage. To manage the pushing of data to, and popping data from, the data store, the ACB includes a contiguous pointer generator, a content addressable memory (CAM) and a free pool.

IPC Classes  ?

  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
  • G06F 5/10 - Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
  • G06F 12/02 - Addressing or allocation; Relocation

73.

System and method for hardware-based register protection mechanism

      
Application Number 17162521
Grant Number 11829492
Status In Force
Filing Date 2021-01-29
First Publication Date 2023-11-28
Grant Date 2023-11-28
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Sundararaman, Ramacharan
  • Shrivastava, Saurabh
  • Sodani, Avinash
  • Miyar, Nithyananda

Abstract

A new approach is proposed to support hardware-based protection for registers of an electronic device. Sources requesting access to the registers are categorized into a set of internal sources that can be trusted and a set of external sources that are untrusted. The registers are classified into a set of internal registers allowed to be accessed by the internal resources only, a set of read-only external registers that can be read by the external resources in addition to accessed by the internal resources, and a set of read/write external registers that can be read and written by both the internal and the external resources. Each access request by a source to the registers includes the source type, wherein access request is granted or denied based on the matching between the source bits in the access request and the register classification bits of the one or more registers to be accessed.

IPC Classes  ?

  • H04L 29/06 - Communication control; Communication processing characterised by a protocol
  • G06F 21/62 - Protecting access to data via a platform, e.g. using keys or access control rules

74.

Distributed link descriptor memory

      
Application Number 17946902
Grant Number 11831567
Status In Force
Filing Date 2022-09-16
First Publication Date 2023-11-28
Grant Date 2023-11-28
Owner Marvell Asia Pte, Ltd. (Singapore)
Inventor
  • Matthews, William Brad
  • Agarwal, Puneet
  • Jain, Ajit Kumar

Abstract

Link data is stored in a distributed link descriptor memory (“DLDM”) including memory instances storing protocol data unit (“PDU”) link descriptors (“PLDs”) or cell link descriptors (“CLDs”). Responsive to receiving a request for buffering a current transfer data unit (“TDU”) in a current PDU, a current PLD is accessed in a first memory instance in the DLDM. It is determined whether any data field designated to store address information in connection with a TDU is currently unoccupied within the current PLD. If no data field designated to store address information in connection with a TDU is currently unoccupied within the current PLD, a current CLD is accessed in a second memory instance in the plurality of memory instances of the same DLDM. Current address information in connection with the current TDU is stored in an address data field within the current CLD.

IPC Classes  ?

  • H04L 49/901 - Buffering arrangements using storage descriptor, e.g. read or write pointers
  • H04L 49/00 - Packet switching elements
  • H04L 49/9047 - Buffering arrangements including multiple buffers, e.g. buffer pools

75.

WIFI backoff timer

      
Application Number 18101890
Grant Number 11832315
Status In Force
Filing Date 2023-01-26
First Publication Date 2023-11-28
Grant Date 2023-11-28
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Chu, Liwen
  • Zhang, Hongyuan
  • Lou, Hui-Ling

Abstract

A communication device performs a first backoff operation to determine when the communication device can begin a first simultaneous transmission via multiple channel segments. The first backoff operation includes counting down a first backoff timer in connection with a first channel segment. In response to the first backoff timer expiring, the communication device performs the first simultaneous transmission via the multiple channel segments. After performing the first simultaneous transmission via the multiple channel segments, the communication device performs a second backoff operation to determine when the communication device can begin a second simultaneous transmission via the multiple channel segments. The second backoff operation includes counting down a second backoff timer in connection with a second channel segment. In response to the second backoff timer expiring, the communication device performs the second simultaneous transmission via the multiple channel segments.

IPC Classes  ?

  • H04W 74/08 - Non-scheduled access, e.g. random access, ALOHA or CSMA [Carrier Sense Multiple Access]
  • H04W 76/18 - Management of setup rejection or failure
  • H04W 76/15 - Setup of multiple wireless link connections

76.

Spatial stream configuration encoding for wifi

      
Application Number 17959057
Grant Number 11831370
Status In Force
Filing Date 2022-10-03
First Publication Date 2023-11-28
Grant Date 2023-11-28
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Zhang, Yan
  • Cao, Rui
  • Yu, Bo
  • Zhang, Hongyuan
  • Chu, Liwen

Abstract

A first client station receives a multi-user physical layer (PHY) data unit from an access point. The multi-user PHY data unit includes i) a PHY preamble, and ii) a multi-user multiple input, multiple output (MU-MIMO) transmission. The PHY preamble includes a subfield that indicates respective numbers of spatial streams allocated to respective client stations among a plurality of client station that includes the first client station. The subfield has been encoded according to an encoding that supports allocating up to sixteen spatial streams to up to eight intended receivers, and the subfield consists of six or fewer bits. The first client station decodes the subfield to determine a number of spatial streams allocated to the first client station and processes the determined number of spatial streams in the MU-MIMO transmission.

IPC Classes  ?

  • H04B 7/0452 - Multi-user MIMO systems
  • H04L 5/00 - Arrangements affording multiple use of the transmission path
  • H04W 84/12 - WLAN [Wireless Local Area Networks]
  • H04L 27/26 - Systems using multi-frequency codes

77.

Methods and Apparatus for Successive Interference Cancellation (SIC)

      
Application Number 18229140
Status Pending
Filing Date 2023-08-01
First Publication Date 2023-11-23
Owner Marvell Asia Pte, Ltd. (Singapore)
Inventor
  • Kim, Hong Jik
  • Yao, Timothy Shee
  • Kurapati, Nagabhushana Rao

Abstract

Methods and apparatus for successive interference cancellation (SIC). In an embodiment, a method includes receiving symbols from a plurality of user equipment (UE), identify a target UE and non-target UEs, decoding code blocks from the symbols received from the non-target UEs to generate decoded bits for each code block. The method also includes performing a CRC check on each code block to generate a tag (0) when the CRC check passes and a tag (1) when the CRC check fails, and re-encoding the decoded bits to generate re-encoded code blocks having the associated tags attached. The method also includes reconstructing symbols from the re-encoded code blocks where symbols reconstructed from re-encoded code blocks having tag (0) are reconstructed with data and symbols reconstructed from re-encoded code blocks having tag (1) are reconstructed as zero value symbols, and utilizing the reconstructed symbols to cancel interference on symbols from the target UE.

IPC Classes  ?

  • H04J 11/00 - Orthogonal multiplex systems
  • H04B 7/0413 - MIMO systems
  • H04L 25/03 - Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
  • H04L 1/00 - Arrangements for detecting or preventing errors in the information received

78.

Prime and probe attack mitigation

      
Application Number 17956330
Grant Number 11822652
Status In Force
Filing Date 2022-09-29
First Publication Date 2023-11-21
Grant Date 2023-11-21
Owner Marvell Asia Pte, Ltd. (Singapore)
Inventor Mukherjee, Shubhendu Sekhar

Abstract

Described herein are systems and methods for prime and probe attack mitigation. For example, some methods include, responsive to a cache miss caused by a process, checking whether a priority level of the process satisfies a first priority requirement of a first cache block of a cache with multiple ways including cache blocks associated with respective priority requirements; responsive to the priority level satisfying the first priority requirement, loading the first cache block; and, responsive to the priority level satisfying the first priority requirement, updating the first priority requirement to be equal to the priority level of the process.

IPC Classes  ?

79.

Physical layer preamble for wireless local area networks

      
Application Number 17848373
Grant Number 11824652
Status In Force
Filing Date 2022-06-23
First Publication Date 2023-11-21
Grant Date 2023-11-21
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Ram, B Hari
  • Ahirwar, Vijay
  • Rottela, Sri Varsha
  • Zhang, Hongyuan
  • Srinivasa, Sudhir
  • Khude, Nilesh

Abstract

A communication device generates a legacy portion of a physical layer (PHY) preamble of a PHY data unit. The legacy portion includes a plurality of legacy training fields and a legacy signal field that indicates a duration of the PHY data unit. The communication device generates a non-legacy portion of the PHY preamble to include a multi-bit signal field header to indicate at least one of i) a particular wireless communication protocol from among the multiple wireless communication protocols, and ii) a particular version of the particular wireless communication protocol. The communication device generates the non-legacy portion of the PHY preamble to also include a non-legacy signal field having a field format that conforms to the at least one of the i) particular wireless communication protocol and ii) the particular version of the particular wireless communication protocol.

IPC Classes  ?

  • H04L 1/00 - Arrangements for detecting or preventing errors in the information received
  • H04L 5/00 - Arrangements affording multiple use of the transmission path

80.

Data unit aggregation in a wireless network with multiple channel segments

      
Application Number 16889798
Grant Number 11818799
Status In Force
Filing Date 2020-06-01
First Publication Date 2023-11-14
Grant Date 2023-11-14
Owner MARVELL ASIA PTE LTD (Singapore)
Inventor
  • Chu, Liwen
  • Zhang, Hongyuan
  • Lou, Hui-Ling
  • Tan, Po Wei
  • Cao, Rui
  • Ho, Ken Kinwah

Abstract

A first communication device selects respective sets of medium access control (MAC) layer data units for transmission via respective channel segments of a communication channel, where the first channel segment and the second channel segment are non-overlapping frequency segments of the communication channel. The first communication device generates respective aggregate MAC layer data units to include the respective sets of MAC layer data units, generates respective physical (PHY) layer data units to include the respective aggregate MAC layer data units, and transmits the respective PHY layer data units in the respective channel segments to one or more second communication devices, where transmissions of the respective aggregate MAC layer data units in the respective channel segment overlap in time.

IPC Classes  ?

  • H04W 80/02 - Data link layer protocols
  • H04W 74/08 - Non-scheduled access, e.g. random access, ALOHA or CSMA [Carrier Sense Multiple Access]
  • H04L 5/00 - Arrangements affording multiple use of the transmission path
  • H04L 1/1607 - Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals - Details of the supervisory signal
  • H04W 84/12 - WLAN [Wireless Local Area Networks]

81.

CHIRPED OPTICAL MODULATOR

      
Application Number 18143743
Status Pending
Filing Date 2023-05-05
First Publication Date 2023-11-09
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Kato, Masaki
  • Mak, Gary
  • Karimelahi, Samira

Abstract

An optical modulator includes a photonic substrate a first modulator arm disposed on the photonic substrate. The first modulator arm is configured to modulate a first optical signal portion of an input optical signal at a first signal level. The optical modulator further includes a second modulator arm disposed on the photonic substrate. The second modulator arm is configured to modulate a second optical signal portion of the input optical signal at a second signal level that is different from the first signal level. The optical modulator further includes an optical combiner configured combine the first optical signal portion at the first signal level and the second optical signal portion at the second signal level to impart a target chirp onto the recombined optical signal. The target chirp is based on a signal level difference between the first signal level and the second signal level.

IPC Classes  ?

  • G02B 6/12 - Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
  • G02B 6/122 - Basic optical elements, e.g. light-guiding paths
  • G02B 6/293 - Optical coupling means having data bus means, i.e. plural waveguides interconnected and providing an inherently bidirectional system by mixing and splitting signals with wavelength selective means

82.

IMPROVING INTEROPERABILITY OF COMMUNICATION DEVICES

      
Application Number US2023020753
Publication Number 2023/215332
Status In Force
Filing Date 2023-05-02
Publication Date 2023-11-09
Owner MARVELL ASIA PTE LTD (Singapore)
Inventor Lee, Whay Sing

Abstract

In a communication network operating according to a communication protocol that defines a link establishment procedure having i) a negotiating procedure and ii) a training procedure, a first communication device performs the link establishment procedure with a second communication device. During the negotiating procedure, the first communication device negotiates one or more new parameter values for the link establishment procedure that are different than one or more mandated parameter values specified by the communication protocol. During the link establishment procedure, the first communication device uses the one or more new parameter values instead of using the one or more mandated parameter values specified by the communication protocol.

IPC Classes  ?

  • H04L 12/413 - Bus networks with decentralised control with random access, e.g. carrier-sense multiple-access with collision detection (CSMA-CD)
  • H04L 5/14 - Two-way operation using the same type of signal, i.e. duplex
  • H04L 49/00 - Packet switching elements

83.

Differential diode-based variable impedance modules

      
Application Number 17943578
Grant Number 11811374
Status In Force
Filing Date 2022-09-13
First Publication Date 2023-11-07
Grant Date 2023-11-07
Owner MARVELL ASIA PTE LTD (Singapore)
Inventor
  • Hoffman, James
  • Pera, Florin

Abstract

The present invention is directed to electrical circuits. More specifically, an embodiment of the present invention provides a variable impedance module with a first capacitor coupled to a first input terminal and the second capacitor coupled to a second input terminal. A diode bridge is connected between the input capacitors. The anodes of the top diodes are connected to a supply through a resistor, and the cathodes of the lower diodes are connected to a high-impedance current source. A third capacitor is connected between these two nodes.

IPC Classes  ?

84.

PHYSICAL LAYER (PHY) DATA UNIT FORMAT FOR HYBRID AUTOMATIC REPEAT REQUEST (HARQ)

      
Application Number 18206030
Status Pending
Filing Date 2023-06-05
First Publication Date 2023-11-02
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Zhang, Yan
  • Chu, Liwen
  • Cao, Rui
  • Zhang, Hongyuan

Abstract

A wireless communication device generates physical layer (PHY) protocol service data units (PSDUs), and, in response to determining that the PHY data unit is to be transmitted according to a HARQ process, generates HARQ coding units of a common length, each of the HARQ coding units including a respective set of one or more PSDUs, and individually encodes the HARQ coding units. The wireless communication device also generates a HARQ signal field to the included in a PHY preamble of the PHY data unit. The HARQ signal field includes i) a common information subfield to indicate one or more parameters that commonly apply to each of at least some of the one or more HARQ coding units and ii) a respective HARQ coding unit information subfield for each of the HARQ coding units to indicate one or more parameters that apply to only the corresponding HARQ coding unit.

IPC Classes  ?

  • H04W 80/02 - Data link layer protocols
  • H04L 1/1867 - Arrangements specially adapted for the transmitter end
  • H04L 1/1812 - Hybrid protocols; Hybrid automatic repeat request [HARQ]
  • H04L 1/00 - Arrangements for detecting or preventing errors in the information received

85.

INTEROPERABILITY OF COMMUNICATION DEVICES

      
Application Number 18142574
Status Pending
Filing Date 2023-05-02
First Publication Date 2023-11-02
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Lee, Whay Sing
  • Patra, Lenin Kumar

Abstract

In a communication network operating according to a communication protocol that defines a link establishment procedure having i) a negotiating procedure and ii) a training procedure, a first communication device performs the link establishment procedure with a second communication device. During the negotiating procedure, the first communication device negotiates one or more new parameter values for the link establishment procedure that are different than one or more mandated parameter values specified by the communication protocol. During the link establishment procedure, the first communication device uses the one or more new parameter values instead of using the one or more mandated parameter values specified by the communication protocol.

IPC Classes  ?

86.

ENERGY EFFICIENT ETHERNET (EEE) OPERATION

      
Application Number 18201135
Status Pending
Filing Date 2023-05-23
First Publication Date 2023-11-02
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Jonsson, Ragnar Hlynur
  • Edem, Brian
  • Mcclellan, Brett Anthony
  • Razavi Majomard, Seid Alireza
  • Wu, Xing
  • Zimmerman, George

Abstract

A network interface device operates in a normal transmit operating mode in which the network interface device continually receives transmission symbols from a link partner via the communication link. The network interface device determines that receive circuitry of the network interface device is to transition to a low power mode in response to receiving a sleep signal from the link partner. The network interface device then operates according to a quiet/refresh cycle of the low power mode to conserve power. The quiet/refresh cycle corresponds to a time schedule that includes a refresh time window in which receive circuitry of the network interface device is to be powered to receive a refresh signal from the link partner Immediately after transmission of the sleep signal, the network interface device transitions to a quiet time window of the time schedule in which the network interface device ignores transmissions from the link partner.

IPC Classes  ?

  • H04L 12/12 - Arrangements for remote connection or disconnection of substations or of equipment thereof
  • H04L 7/00 - Arrangements for synchronising receiver with transmitter

87.

WIRELESS LOCAL AREA NETWORK MANAGEMENT

      
Application Number 18218007
Status Pending
Filing Date 2023-07-03
First Publication Date 2023-10-26
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Chu, Liwen
  • Zhang, Hongyuan
  • Lou, Hui-Ling

Abstract

An access point manages a first wireless local area network (WLAN) in a 6 GHz radio frequency (RF) band and ii) a second WLAN operating in another RF band. The access point generates a physical layer (PHY) data unit to include a management frame having i) first information indicating first network parameters of the first WLAN, and ii) second information indicating second network parameters of the second WLAN. The AP transmits the PHY data unit in the other RF band to provide, to any client stations that are operating in the other RF band and that are also capable of operating in the 6 GHz band: the first information indicating the first network parameters of the first WLAN operating in the 6 GHz RF band to assist the any client stations that are operating in the other RF band with joining the first WLAN operating in the 6 GHz RF band.

IPC Classes  ?

  • H04W 74/08 - Non-scheduled access, e.g. random access, ALOHA or CSMA [Carrier Sense Multiple Access]
  • H04W 72/0453 - Resources in frequency domain, e.g. a carrier in FDMA
  • H04W 72/0446 - Resources in time domain, e.g. slots or frames
  • H04W 8/24 - Transfer of terminal data
  • H04W 56/00 - Synchronisation arrangements
  • H04W 40/24 - Connectivity information management, e.g. connectivity discovery or connectivity update
  • H04W 80/02 - Data link layer protocols
  • H04L 1/00 - Arrangements for detecting or preventing errors in the information received
  • H04L 69/18 - Multiprotocol handlers, e.g. single devices capable of handling multiple protocols
  • H04L 5/00 - Arrangements affording multiple use of the transmission path
  • H04L 27/26 - Systems using multi-frequency codes

88.

RECONFIGURABLE OPTICAL TRANSCEIVER FOR USE WITH MULTIPLE MODULATION TECHNIQUES

      
Application Number US2023019140
Publication Number 2023/205264
Status In Force
Filing Date 2023-04-19
Publication Date 2023-10-26
Owner MARVELL ASIA PTE LTD (Singapore)
Inventor
  • Kato, Masaki
  • Mak, Gary

Abstract

An optical module includes a plurality of lasers, each of at least some of the lasers configured to be selectively turned on and turned off depending on a type of modulation to be used. Each laser corresponds to a respective wavelength. The optical module also includes an optical modulation system having a plurality of optical modulators. A reconfigurable optical network of the optical module is configured to selectively direct light from the plurality of lasers to the optical modulation system differently depending on the type of modulation to be used.

IPC Classes  ?

89.

RECONFIGURABLE OPTICAL TRANSCEIVER FOR USE WITH MULTIPLE MODULATION TECHNIQUES

      
Application Number 18136759
Status Pending
Filing Date 2023-04-19
First Publication Date 2023-10-19
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Nagarajan, Radhakrishnan
  • Kato, Masaki
  • Mak, Gary

Abstract

An optical module includes a plurality of lasers, each of at least some of the lasers configured to be selectively turned on and turned off depending on a type of modulation to be used. Each laser corresponds to a respective wavelength. The optical module also includes an optical modulation system having a plurality of optical modulators. A reconfigurable optical network of the optical module is configured to selectively direct light from the plurality of lasers to the optical modulation system differently depending on the type of modulation to be used.

IPC Classes  ?

90.

EQUALIZATION IN HIGH-SPEED DATA CHANNEL HAVING SPARSE IMPULSE RESPONSE

      
Application Number 18333248
Status Pending
Filing Date 2023-06-12
First Publication Date 2023-10-19
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Razavi Majomard, Seid Alireza
  • Shen, David
  • Jonsson, Ragnar Hlynur

Abstract

A physical layer transceiver, for connecting a host device to a wireline channel medium that is divided into a total number of link segments, includes a host interface for coupling to a host device, a line interface for coupling to the wireline channel medium, and feed-forward equalization (FFE) circuitry operatively coupled to the line interface to add back, into a signal, components that were scattered in time. Respective individual filter segments are selectably configurable, by adjustment of respective delay lines, to correspond to respective individual link segments. The FFE circuitry also includes control circuitry configured to detect a signal energy peak in at least one particular link segment and, upon detection of the signal energy peak in the particular link segment, configure a respective one of the respective individual filter segments, by adjustment of a respective delay line, to correspond to the respective particular link segment.

IPC Classes  ?

  • H04L 25/03 - Shaping networks in transmitter or receiver, e.g. adaptive shaping networks

91.

Power management and current/ramp detection mechanism

      
Application Number 17827508
Grant Number 11789513
Status In Force
Filing Date 2022-05-27
First Publication Date 2023-10-17
Grant Date 2023-10-17
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Bhattarai, Atul
  • Sripada, Srinivas
  • Sodani, Avinash
  • Dudek, Michael
  • Walworth, Darren
  • Fernando, Roshan
  • Irvine, James
  • Gopal, Mani

Abstract

A system includes a multicore chip configured to perform machine learning (ML) operations. The system also includes a power monitoring module configured to measure power consumption of the multicore chip on a main power rail of the multicore chip. The power monitoring module is further configured to assert a signal in response to the measured power consumption exceeding a first threshold. The power monitoring module is further configured to transmit the asserted signal to a power throttling module to initiate a power throttling for the multicore chip.

IPC Classes  ?

  • G06F 1/3206 - Monitoring of events, devices or parameters that trigger a change in power modality
  • G06F 11/30 - Monitoring

92.

Media access control for frequency division full duplex in WLAN

      
Application Number 17705858
Grant Number 11791957
Status In Force
Filing Date 2022-03-28
First Publication Date 2023-10-17
Grant Date 2023-10-17
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Jiang, Jinjing
  • Chu, Liwen
  • Zhang, Hongyuan
  • Lou, Hui-Ling

Abstract

A first communication device in a wireless local area network (WLAN) determines one or more frequency division, full duplex (FDFD) parameters for an FDFD operation that includes FDFD communications via a first frequency segment and a second frequency segment. The first frequency segment and the second frequency segment are separated by a gap in frequency. The one or more FDFD parameters include a parameter indicating a duration of the FDFD operation. The first communication device generates a communication frame that includes one or more indications of the one or more FDFD parameters. The one or more indications in the communication frame include an indication of the duration of the FDFD operation. The first communication device transmits the communication frame to prompt a plurality of second communication devices to participate in the FDFD operation.

IPC Classes  ?

  • H04L 5/00 - Arrangements affording multiple use of the transmission path
  • H04L 5/14 - Two-way operation using the same type of signal, i.e. duplex
  • H04W 84/12 - WLAN [Wireless Local Area Networks]
  • H04W 80/02 - Data link layer protocols
  • H04W 72/0453 - Resources in frequency domain, e.g. a carrier in FDMA
  • H04L 47/10 - Flow control; Congestion control
  • H04W 28/10 - Flow control
  • H04J 1/04 - Frequency-transposition arrangements
  • H04W 28/02 - Traffic management, e.g. flow control or congestion control
  • H04W 8/04 - Registration at HLR or HSS [Home Subscriber Server]

93.

Soft FEC With Parity Check

      
Application Number 18210823
Status Pending
Filing Date 2023-06-16
First Publication Date 2023-10-12
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Riani, Jamal
  • Smith, Benjamin
  • Shvydun, Volodymyr
  • Swaminathan, Srinivas
  • Farhoodfar, Arash

Abstract

A data transmission device includes a de-interleaver configured to receive, from a host device at a first data rate, a data stream including encoded data, de-interleave the data stream into a plurality of forward error correction (FEC) data streams, and output the plurality of FEC data streams at a second data rate less than the first data rate. Each of a plurality of interleavers is configured to interleave a respective one of the plurality of FEC data streams into an intermediate data stream including first data blocks and second data blocks. An encoder module configured to generate, for each of the intermediate data streams, FEC blocks including a first parity section and a first data section, the first parity section including a first parity bit corresponding to the first data blocks and a second parity bit corresponding to the second data blocks, and the first data section including the first data blocks and the second data blocks, and output the FEC blocks at the second data rate.

IPC Classes  ?

  • H04L 1/00 - Arrangements for detecting or preventing errors in the information received

94.

Explicit multiuser beamforming training in a wireless local area network

      
Application Number 17883308
Grant Number 11784692
Status In Force
Filing Date 2022-08-08
First Publication Date 2023-10-10
Grant Date 2023-10-10
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Chu, Liwen
  • Sun, Yakun
  • Cao, Rui
  • Zhang, Hongyuan
  • Lou, Hui-Ling

Abstract

A first communication device transmits a null data packet (NDP) to a second communication device as part of a multi-user beamforming training transmission sequence and receives a first packet from the second communication device responsive to transmitting the NDP. The first packet includes an aggregate media access control protocol data unit (A-MPDU) having a plurality of fragments of beamforming training information that was generated by the second communication device based on the NDP. The first communication device determines that one or more of the fragments were not correctly received by the first communication device and generates a bitmap to indicate a set of at least one fragment that is to be retransmitted by the second communication device. The first communication device transmits a second packet having the bitmap to the second communication device to prompt the second communication device to retransmit the set of at least one fragment.

IPC Classes  ?

  • H04B 7/06 - Diversity systems; Multi-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station
  • H04L 5/00 - Arrangements affording multiple use of the transmission path
  • H04L 25/02 - Baseband systems - Details
  • H04L 1/1607 - Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals - Details of the supervisory signal
  • H04W 84/12 - WLAN [Wireless Local Area Networks]
  • H04B 7/0452 - Multi-user MIMO systems
  • H04L 27/26 - Systems using multi-frequency codes

95.

ASYMMETRICAL SEMICONDUCTOR-BASED OPTICAL MODULATOR

      
Application Number 18128996
Status Pending
Filing Date 2023-03-30
First Publication Date 2023-10-05
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Pishvaibazargani, Hamed
  • Lin, Jie
  • Kato, Masaki

Abstract

An optical modulator includes a semiconductor substrate and an optical waveguide portion disposed on the semiconductor substrate. A signal contact that extends alongside the optical waveguide portion is disposed on the semiconductor substrate. A first ground line is disposed on the semiconductor substrate spaced away from the signal contact by a first spacing. A second ground line is disposed on the semiconductor substrate spaced away from the signal contact by a second spacing opposite the first ground line. The first spacing is different from the second spacing.

IPC Classes  ?

  • G02F 1/21 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour by interference
  • G02F 1/015 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on semiconductor elements with at least one potential jump barrier, e.g. PN, PIN junction
  • G02F 1/225 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour by interference in an optical waveguide structure

96.

ASYMMETRICAL SEMICONDUCTOR-BASED OPTICAL MODULATOR

      
Application Number US2023016991
Publication Number 2023/192536
Status In Force
Filing Date 2023-03-30
Publication Date 2023-10-05
Owner MARVELL ASIA PTE LTD (Singapore)
Inventor
  • Pishvaibazargani, Hamed
  • Lin, Jie

Abstract

An optical modulator includes a semiconductor substrate and an optical waveguide portion disposed on the semiconductor substrate. A signal contact that extends alongside the optical waveguide portion is disposed on the semiconductor substrate. A first ground line is disposed on the semiconductor substrate spaced away from the signal contact by a first spacing. A second ground line is disposed on the semiconductor substrate spaced away from the signal contact by a second spacing opposite the first ground line. The first spacing is different from the second spacing.

IPC Classes  ?

  • G02F 1/015 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on semiconductor elements with at least one potential jump barrier, e.g. PN, PIN junction
  • G02F 1/025 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on semiconductor elements with at least one potential jump barrier, e.g. PN, PIN junction in an optical waveguide structure
  • G02F 1/225 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour by interference in an optical waveguide structure

97.

Methods and systems for enabling communications from a station to an access point using a backoff counter and carrier sensing

      
Application Number 15710707
Grant Number 11778663
Status In Force
Filing Date 2017-09-20
First Publication Date 2023-10-03
Grant Date 2023-10-03
Owner Marvell Asia Pte, Ltd. (Singapore)
Inventor
  • Jiang, Jinjing
  • Chu, Liwen
  • Wang, Lei
  • Zhang, Hongyuan
  • Lou, Hui-Ling

Abstract

A method for communicating with an access point by a station. The station receives a first signal including an indication of a plurality of channels. The first signal is received from an access point. The station modifies a counter value in in response to receiving the first signal. The station further compares the counter value to a threshold value and selects a channel of the plurality of channels in response to determining the counter value corresponds to the threshold value. The station determines whether the selected channel is busy or idle. The station modifies the counter value in in response to determining that the selected channel is busy. The station transmits a second signal using the selected channel in response to determining that the selected channel is idle.

IPC Classes  ?

  • H04W 56/00 - Synchronisation arrangements
  • H04W 74/08 - Non-scheduled access, e.g. random access, ALOHA or CSMA [Carrier Sense Multiple Access]
  • H04L 1/1829 - Arrangements specially adapted for the receiver end
  • H04W 72/23 - Control channels or signalling for resource management in the downlink direction of a wireless link, i.e. towards a terminal
  • H04W 72/1268 - Mapping of traffic onto schedule, e.g. scheduled allocation or multiplexing of flows of uplink data flows
  • H04W 74/00 - Wireless channel access, e.g. scheduled or random access
  • H04L 49/90 - Buffering arrangements
  • H04W 76/20 - Manipulation of established connections

98.

Transmitting network management information in a wireless local area network

      
Application Number 17698856
Grant Number 11778690
Status In Force
Filing Date 2022-03-18
First Publication Date 2023-10-03
Grant Date 2023-10-03
Owner Marvell Asia Pte Ltd (Singapore)
Inventor
  • Chu, Liwen
  • Zhang, Hongyuan
  • Lou, Hui-Ling

Abstract

An access point (AP) allocates a broadcast resource unit (RU), and ii) one or more other RUs for a multi-user physical layer protocol data unit (MU PPDU). The AP generates the MU PPDU to include i) a physical layer (PHY) preamble, and ii) a management medium access control layer (MAC) frame in the broadcast RU. When the AP device is allowing unassociated stations to associate with the AP device, the AP device sets a station identifier in the PHY preamble corresponding to the broadcast RU to a first value that indicates the AP device is allowing unassociated stations to associate with the AP device. When the AP device is not allowing unassociated stations to associate with the AP device, the AP device sets the station identifier to a second value that indicates the AP device is not allowing unassociated stations to associate with the AP device.

IPC Classes  ?

  • H04W 80/02 - Data link layer protocols
  • H04W 76/11 - Allocation or use of connection identifiers
  • H04W 72/30 - Resource management for broadcast services
  • H04W 84/12 - WLAN [Wireless Local Area Networks]

99.

Real-time, in-situ reliability monitoring in an integrated circuit

      
Application Number 16917943
Grant Number 11774490
Status In Force
Filing Date 2020-07-01
First Publication Date 2023-10-03
Grant Date 2023-10-03
Owner MARVELL ASIA PTE LTD (Singapore)
Inventor Chang, Runzi

Abstract

An Integrated Circuit (IC) includes an electronic circuit and reliability monitoring circuitry. The electronic circuit includes multiple electronic components. The reliability monitoring circuitry is configured to assess, during operation of the IC in a host system, one or more parameters indicative of a reliability of one or more components-of-interest, selected from among the electronic components, and to provide an output indicative of the reliability.

IPC Classes  ?

  • G01R 31/26 - Testing of individual semiconductor devices
  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
  • G01R 31/52 - Testing for short-circuits, leakage current or ground faults
  • H01L 29/772 - Field-effect transistors

100.

METHOD OF FABRICATING SI PHOTONICS CHIP WITH INTEGRATED HIGH SPEED GE PHOTO DETECTOR WORKING FOR ENTIRE C- AND L-BAND

      
Application Number 18126119
Status Pending
Filing Date 2023-03-24
First Publication Date 2023-09-28
Owner MARVELL ASIA PTE LTD (Singapore)
Inventor
  • Ding, Liang
  • Kato, Masaki
  • Nagarajan, Radhakrishnan

Abstract

A receiver for receiving optical signals transmitted over a communications network includes a silicon photonics substrate including multiple regions with respectively different doping, an epitaxial germanium layer extending at least partially over at least two or more of regions with different doping, and at least one of a tensile stressor component and a compressive stressor component in contact with the epitaxial germanium layer. The tensile stressor component and the compressive stressor component are respectively configured to mechanically strain the epitaxial germanium layer to modify an optical signal absorption attribute of the epitaxial germanium layer. The receiver includes a receive circuit including at least one electrode component in electrical contact with the epitaxial germanium layer. The receive circuit is configured to generate an electrical output in response to an optical signal received from a network interface of the communications network by the epitaxial germanium layer.

IPC Classes  ?

  • H01L 31/109 - Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier being of the PN heterojunction type
  • H01L 31/028 - Inorganic materials including, apart from doping material or other impurities, only elements of Group IV of the Periodic System
  • H01L 31/0216 - Coatings
  • H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
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