A receiver for receiving optical signals transmitted over a communications network includes a silicon photonics substrate including multiple regions with respectively different doping, an epitaxial germanium layer extending at least partially over at least two or more of regions with different doping, and at least one of a tensile stressor component and a compressive stressor component in contact with the epitaxial germanium layer. The tensile stressor component and the compressive stressor component are respectively configured to mechanically strain the epitaxial germanium layer to modify an optical signal absorption attribute of the epitaxial germanium layer. The receiver includes a receive circuit including at least one electrode component in electrical contact with the epitaxial germanium layer. The receive circuit is configured to generate an electrical output in response to an optical signal received from a network interface of the communications network by the epitaxial germanium layer.
H01L 31/109 - Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier being of the PN heterojunction type
H01L 31/028 - Inorganic materials including, apart from doping material or other impurities, only elements of Group IV of the Periodic System
A receiver for receiving optical signals transmitted over a communications network includes a silicon photonics substrate including multiple regions with respectively different doping, an epitaxial germanium layer extending at least partially over at least two or more of regions with different doping, and at least one of a tensile stressor component and a compressive stressor component in contact with the epitaxial germanium layer. The tensile stressor component and the compressive stressor component are respectively configured to mechanically strain the epitaxial germanium layer to modify an optical signal absorption attribute of the epitaxial germanium layer. The receiver includes a receive circuit including at least one electrode component in electrical contact with the epitaxial germanium layer. The receive circuit is configured to generate an electrical output in response to an optical signal received from a network interface of the communications network by the epitaxial germanium layer.
H01L 31/10 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by at least one potential-jump barrier or surface barrier, e.g. phototransistors
H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
H01L 31/0256 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by their semiconductor bodies characterised by the material
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H04B 10/69 - Electrical arrangements in the receiver
3.
System and method for bitcoin mining with reduced power
A circuit and corresponding method enable bitcoin mining in a blockchain network. The circuit comprises a nonce generator that generates a nonce value, on a cycle-by-cycle basis, and changes only one binary digit of the nonce value per cycle. The circuit further comprises a hash engine that inserts, on the cycle-by-cycle basis, the nonce value into a block header of a block candidate and generates a digest by applying a hash function to the block header. The block header includes a representation of a target value. The circuit further comprises a validator that compares, on the cycle-by-cycle basis, the digest to the target value. In an event the digest satisfies the target value, the validator submits the block candidate to the blockchain network, causing newly minted bitcoin to be mined from the blockchain network. Changing only one binary digit of the nonce value, per cycle, reduces power consumption of the circuit.
H04L 29/06 - Communication control; Communication processing characterised by a protocol
H04L 9/32 - Arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system
G06Q 20/06 - Private payment circuits, e.g. involving electronic currency used only among participants of a common payment scheme
G06F 21/76 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]
H04L 9/00 - Arrangements for secret or secure communications; Network security protocols
4.
Method and apparatus for timing-annotated scan-chain testing using parallel testbench
A method of testing an integrated circuit device, that operates at a clock frequency and that has at least one scan chain that includes a plurality of registers separated by combinatorial logic, includes establishing a respective scan chain test pattern for testing the scan chain where the scan chain test pattern includes a respective bit for each register in the plurality of registers of the scan chain, determining in advance a respective timing delay for each pair of adjacent registers in the scan chain, and, within a single clock period of the clock frequency, applying, in parallel, each bit of the respective scan chain pattern to a respective register in the plurality of registers in the scan chain, each bit of the respective scan chain pattern being applied to its respective register at a respective temporal offset, within the single clock period, based on the respective timing delay.
A method for forming a silicon photonics interposer having through-silicon vias (TSVs). The method includes forming vias in a front side of a silicon substrate and defining primary structures for forming optical devices in the front side. Additionally, the method includes bonding a first handle wafer to the front side and thinning down the silicon substrate from the back side and forming bumps at the back side to couple with a conductive material in the vias. Furthermore, the method includes bonding a second handle wafer to the back side and debonding the first handle wafer from the front side to form secondary structures based on the primary structures. Moreover, the method includes forming pads at the front side to couple with the bumps at the back side before completing final structures based on the secondary structures and debonding the second handle wafer from the back side.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
G02B 6/42 - Coupling light guides with opto-electronic elements
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different main groups of groups , or in a single subclass of , , e.g. forming hybrid circuits
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
6.
Printed circuit boards with meshed conductive structures
Electronic apparatus includes a dielectric substrate and alternating layers of conducting and dielectric materials disposed over the dielectric substrate, including at least first and second patterned layers of the conducting material separated by an intervening layer of the dielectric material. A conductive trace is disposed within the first patterned layer of the conducting material. A conductive mesh extends within the second patterned layer of the conducting material over a region that overlaps transversely with at least a part of the conductive trace in the first patterned layer.
In a multi-node system, each node includes tiles. Each tile includes a cache controller, a local cache, and a snoop filter cache (SFC). The cache controller responsive to a memory access request by the tile checks the local cache to determine whether the data associated with the request has been cached by the local cache of the tile. The cached data from the local cache is returned responsive to a cache-hit. The SFC is checked to determine whether any other tile of a remote node has cached the data associated with the memory access request. If it is determined that the data has been cached by another tile of a remote node and if there is a cache-miss by the local cache, then the memory access request is transmitted to the global coherency unit (GCU) and the snoop filter to fetch the cached data. Otherwise an interconnected memory is accessed.
The present invention is directed to electrical circuits. According to an embodiment, the present invention provides a charge pump circuit with a bias section and a switch section. The switch section includes a first switch coupled to an early signal and a second switch coupled to a late signal. The charge pump additionally includes a low-pass filter. The switch section includes a first resistor and a second resistor. The first resistor is directly coupled to the first switch and the low-pass filter. The second resistor is directly coupled to the second switch and the first resistor. There are other embodiments as well.
H02M 3/07 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
H03L 7/089 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
A first communication device determines, based on information included in a first packet received from a second communication device, i) an overall frequency bandwidth of an operating channel of a WLAN and ii) one or more punctured sub-channels for the operating channel. The first communication device transmits, via a plurality sub-channels included in the operating channel of the WLAN, the plurality of sub-channels not including any of the one or more punctured sub-channels, a second packet that includes an RTS frame to initiate a TXOP of the first communication device. The first communication device receives, via a subset of the plurality of sub-channels, a third packet that includes a CTS frame, determines that the subset of sub-channels is reserved for the transmit opportunity TXOP initiated by the first communication device, and transmit a fourth packet to the second communication device during the TXOP via the subset of sub-channels.
A photonic integrated circuit (PIC) includes photonic components fabricated on the PIC. One of the photonic components includes an optical coupler configured to optically couple to an optical component. The optical coupler includes waveguide elements arranged in a 2- dimensional array that is configured to provide a first mode having a first shape chosen to match a second shape of a second mode of the optical component.
G02B 6/12 - Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
G02B 6/122 - Basic optical elements, e.g. light-guiding paths
A photonic integrated circuit (PIC) includes photonic components fabricated on the PIC. One of the photonic components includes an optical coupler configured to optically couple to an optical component. The optical coupler includes waveguide elements arranged in a 2-Dimensional array that is configured to provide a first mode having a first shape chosen to match a second shape of a second mode of the optical component.
A cryptographic system includes a block transfer engine and a crypto map unit. The block transfer engine is configured to receive a plurality of encrypted counter values and a plurality of packet attributes. The block transfer engine is further configured to determine a subset of encrypted counter values from the plurality of counter values that is to be used to encrypt a subset of incoming packets from a plurality of incoming packets. Encrypted counter values other than the subset of encrypted counter values are stored for later encryption use. The crypto map unit is configured to receive the plurality of incoming packets and the subset of encrypted counter values from the block transfer engine. The crypto map unit is further configured to encrypt the subset of incoming packets from the received plurality of incoming packets with the subset of encrypted counter values.
H04L 9/06 - Arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for blockwise coding, e.g. D.E.S. systems
H04L 9/32 - Arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system
A variable gain amplifier system includes a variable gain amplifier circuit configured to receive an input signal, apply a gain to the input signal, and generate an output signal in accordance with the gain applied to the input signal. The variable gain amplifier circuit is further configured to receive a gain control signal and a bandwidth control signal. A control module is configured to generate the gain control signal to adjust the gain of the variable gain amplifier circuit and generate, separately from the gain control signal, the bandwidth control signal to adjust a bandwidth of the variable gain amplifier circuit by selectively varying an amount of inductance contributed by an inductor circuit of the variable gain amplifier circuit.
Embodiments of the present invention relate to a Lookup and Decision Engine (LDE) for generating lookup keys for input tokens and modifying the input tokens based on contents of lookup results. The input tokens are parsed from network packet headers by a Parser, and the tokens are then modified by the LDE. The modified tokens guide how corresponding network packets will be modified or forwarded by other components in a software-defined networking (SDN) system. The design of the LDE is highly flexible and protocol independent. Conditions and rules for generating lookup keys and for modifying tokens are fully programmable such that the LDE can perform a wide variety of reconfigurable network features and protocols in the SDN system.
Systems and methods of using a packet order work scheduler (POWS) to assign packets to a set of scheduler queues for supplying packets to parallel processing units. A processing unit and the associated scheduler queue are dedicated to a specific flow until a queue-reallocation event, which may correspond to the associated scheduler queue being idle for at least a certain interval as indicated by its age counter, or the queue being the least recently used, when a new flow arrives. In this case, the scheduler queue and the associated processing unit may be reallocated to the new flow and disassociated with the previous flow. As a result, dynamic packet workload balancing can be advantageously achieved across the multiple processing paths.
A hardware client and corresponding method employ an object-oriented memory device. The hardware client generates an object-oriented message associated with an object of an object class. The object class includes at least one data member and at least one method. The hardware client transmits the object-oriented message generated to the object-oriented memory device via a hardware communications interface. The hardware communications interface couples the hardware client to the object-oriented memory device. The object is instantiated or to-be instantiated in at least one physical memory of the object-oriented memory device according to the object class. The at least one method enables the object-oriented memory device to access the at least one data member for the hardware client.
G06F 9/38 - Concurrent instruction execution, e.g. pipeline, look ahead
G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
G06F 5/06 - Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising
G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
17.
SERIAL MANAGEMENT INTERFACE WITH IMPROVED RELIABILITY
A first serial management interface device includes one or more input/output pins and a controller coupled to the one or more input/output pins. The controller receives a first frame from a second serial management interface device via a first input/output pin and generates a first error code based on the first frame received from the second serial management interface device. The controller receives a second frame from the second serial management interface device via a second input/output pin subsequent to receiving the first frame. The second frame includes a second error code. The controller compares the first error code to the second error code to determine whether first error code and the second error code match.
A sensor bridge (36), for use in an Ethernet network in a vehicle (24), includes a sensor interface (52), a mapper (56) and a communication processor (60). The sensor interface is configured to receive sensor data from a sensor (28) installed in the vehicle. The mapper is configured to form mapped sensor data by applying to the sensor data a direct mapping that maps specified parts of the sensor data to corresponding bit positions in one or more Ethernet packets. The communication processor is configured to generate the one or more Ethernet packets including the mapped sensor data, and to transmit the one or more Ethernet packets over the Ethernet network.
H03K 19/00 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
H03K 19/0185 - Coupling arrangements; Interface arrangements using field-effect transistors only
G06F 1/06 - Clock generators producing several clock signals
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
A processor receives data corresponding to a sensor, and generates a frame having a header and a payload. A data type value is selected from a set of multiple data type values corresponding to different respective types of data, the set of multiple data type values including at least i) a first data type value corresponding to video data from a camera, and ii) a second data type value corresponding to non-video data. The header is generated to include one or more fields set to the selected data type value to indicate a type of data included in the payload, and the payload is generated to include the data received from the sensor. The processor provides the frame to an Ethernet network interface. The Ethernet network interface encapsulates the frame in an Ethernet packet, and transmits the Ethernet packet via an Ethernet link.
A first client station receives a management frame from a physical access point (AP), which implements a plurality of virtual APs. The management frame includes an indication of a plurality of respective basic services set (BSS) identifiers of a plurality of BSSs that correspond to the plurality of virtual APs. The first client station transmits a first signal as part of an uplink multi-user transmission to the physical AP. The first signal includes i) a first physical layer (PHY) preamble with a field set to a single BSS color identifier that corresponds to all of the virtual APs, and ii) a PHY payload with data intended for the first virtual AP. The first signal is transmitted while one or more second client stations transmit one or more second signals with data intended for one or more second virtual APs as part of the UL multi-user transmission.
H04W 4/06 - Selective distribution of broadcast services, e.g. multimedia broadcast multicast service [MBMS]; Services to user groups; One-way selective calling services
H04W 72/21 - Control channels or signalling for resource management in the uplink direction of a wireless link, i.e. towards the network
An access point generates respective first data units for transmission in respective frequency segments, each first data unit including a respective beacon frame having an indication that the access point is operating in multiple frequency segments, and each beacon frame including a respective MAC address utilized by the access point for operation in the respective frequency segment. The access point transmits the respective first data units having the respective beacon frames in respective primary channels of the respective frequency segments to permit client stations to discover the access point in any of the respective primary channels. In response to receiving from a first client station a probe request frame in one of the frequency segments, the access point transmits a probe response frame in the one frequency segment, the probe response frame including, for each frequency segment, respective operation information indicating respective operation parameters for the respective frequency segment.
A sensor bridge, for use in an Ethernet network in a vehicle, includes a sensor interface, a mapper and a communication processor. The sensor interface is configured to receive sensor data from a sensor installed in the vehicle. The mapper is configured to form mapped sensor data by applying to the sensor data a direct mapping that maps specified parts of the sensor data to corresponding bit positions in one or more Ethernet packets. The communication processor is configured to generate the one or more Ethernet packets including the mapped sensor data, and to transmit the one or more Ethernet packets over the Ethernet network.
Methods and apparatus for preamble detection in a communication network are disclosed. In an exemplary embodiment, a method includes retrieving parameters from a parameter database, filling a buffer of preamble data received in an uplink transmission from user equipment, and frequency shifting the buffer of preamble data based on one or more first parameters to generate frequency shifted data. The method also includes oversampling the frequency shifted data to generates oversampled data, downsampling the over sampled data based on one or more second parameters to generate preamble samples, and updating the parameter database with updated values for the one or more first and second parameters. The method also includes repeating all the operations until a selected amount of preamble samples is obtained.
An apparatus for controlling an imaging sensor (28) in a vehicle (24) includes an Ethernet transceiver (72), a sensor interface (80) and a local processor (76). The Ethernet transceiver is configured to communicate over an in-vehicle Ethernet network with a remote processor. The sensor interface is configured to communicate with the imaging sensor. The local processor that is local to the apparatus and remotely located from the remote processor is configured to receive from the imaging sensor, via the sensor interface, image data and auxiliary data related to the image data, to send at least the image data to the remote processor via the Ethernet transceiver, to generate locally, based on the auxiliary data, and independently from the remote processor, control commands to control an operational aspect of the imaging sensor, and to send the control commands to the imaging sensor via the sensor interface.
H04N 7/18 - Closed-circuit television [CCTV] systems, i.e. systems in which the video signal is not broadcast
B60R 16/023 - Electric or fluid circuits specially adapted for vehicles and not otherwise provided for; Arrangement of elements of electric or fluid circuits specially adapted for vehicles and not otherwise provided for electric for transmission of signals between vehicle parts or subsystems
09 - Scientific and electric apparatus and instruments
Goods & Services
Computer hardware; computer chips; semiconductors; semiconductor chips and chip sets; microprocessors; central processing units; integrated circuits; integrated circuit chips; downloadable computer software and firmware for controlling and using integrated circuits; integrated circuits in the nature of application specific standard products (ASSPs), application specific integrated circuits (ASICs), and system-on-chips (SoCs), and related downloadable software for use in automotive applications, namely, downloadable software for providing high-performance computing and secure Ethernet connectivity in a vehicle; data communication circuits; computer network bridges; Ethernet switches; Ethernet adapters; Ethernet transceivers; Ethernet controllers; Ethernet repeaters; data processors for packet processing, encryption, Ethernet connectivity, digital signal processing, telematic control, advanced driver assistance, in-vehicle cameras and sensors, and artificial intelligence for use in automotive applications; processors, namely, artificial intelligence data processors, server data processors, general purpose computer data processors, high-performance computing data processors, digital signal data processors, data processors, programmable data processors, audio or video data processors; computer hardware and downloadable software and firmware for setting up, configuring, managing, operating, and securing local and wide-area computer networks and network products; In-Vehicle Networking (INV) systems comprised of computer hardware and recorded software for facilitating electronic data communication transmission used to connect electronic control units in automobiles; computer hardware and downloadable software and firmware for use in enabling autonomous driving vehicles, connected vehicles, and components of autonomous driving vehicles and connected vehicles; lidar apparatus; computer hardware and downloadable computer software for operating lidar apparatus
An optical module includes first circuitry configured to receive data transmitted from a host over an electrical communication link at a first data rate, the data transmitted from the host being either one of PCIe data and CXL data and change a data rate for transmission of data from the optical module, the data transmitted from the optical module being transmitted at a second data rate different from the first data rate. Second circuitry is configured to convert the data transmitted from the host at the first data rate from an electrical format to an optical format for transmission from the optical module at the second data rate and convert data received from an optical receiver at the second data rate from the optical format to the electrical format for transmission from the optical module to the host at the first data rate via the first circuitry.
H04B 10/80 - Optical aspects relating to the use of optical transmission for specific applications, not provided for in groups , e.g. optical power feeding or optical transmission through water
H04L 1/00 - Arrangements for detecting or preventing errors in the information received
H04L 69/10 - Streamlined, light-weight or high-speed protocols, e.g. express transfer protocol [XTP] or byte stream
A system-on-chip integrated circuit device includes a plurality of functional circuit modules, at least a first circuit module of the plurality of functional circuit modules operating under a first protocol, the first protocol being an interface protocol for communicating outside the system-on-chip integrated circuit device, an interconnect fabric coupled to the functional circuit modules in the plurality of functional circuit modules, and a built-in self-test circuit module coupled to the interconnect fabric. The built-in self-test circuit is configured to test one or more selected functional circuit modules in the plurality of functional circuit modules, including at least the first circuit module under the first protocol for communicating outside the system-on-chip integrated circuit device, by routing test data through the one or more selected functional circuit modules.
Methods and apparatus for dynamic acknowledgement list selection in detection of uplink control channel formats. In an exemplary embodiment, an apparatus includes a dynamic acknowledgement (ACK) list allocation circuit that generates a dynamic ACK list that includes one or two most likely ACK candidates, and a top-Q candidate CQI bits detector that dynamically allocates a detection branch to each of the one or two most likely ACK candidates to detect top-Q candidate CQI bits. The apparatus also includes a merger circuit that mergers the top-Q candidate CQI bits detected for the one or two most likely ACK candidates to generate a merged list, a top-Q CQI symbol generator that generates top-Q CQI symbols for the top-Q candidate CQI bits detected for the one or two most likely ACK candidates, and a joint detector that detects transmitted CQI bits and ACK bits.
An electronic device includes a substrate, and a stack of dies stacked on the substrate. The stack includes (i) multiple dies stacked on one another, the multiple dies include electronic components and interconnections, and (ii) one or more heat pipes (HPs), which are traversing at least a subset of the dies at a right angle relative to the substrate, at least one of the HPs being configured to dissipate heat generated by operation of the electronic components away from at least the subset of the dies.
H01L 23/427 - Cooling by change of state, e.g. use of heat pipes
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
An apparatus for controlling an imaging sensor in a vehicle includes an Ethernet transceiver, a sensor interface and a local processor. The Ethernet transceiver is configured to communicate over an in-vehicle Ethernet network with a remote processor. The sensor interface is configured to communicate with the imaging sensor. The local processor that is local to the apparatus and remotely located from the remote processor is configured to receive from the imaging sensor, via the sensor interface, image data and auxiliary data related to the image data, to send at least the image data to the remote processor via the Ethernet transceiver, to generate locally, based on the auxiliary data, and independently from the remote processor, control commands to control an operational aspect of the imaging sensor, and to send the control commands to the imaging sensor via the sensor interface.
Methods and apparatus for providing a resource element identification system to process received uplink transmissions. In an embodiment, a method is provided that includes receiving soft-demapped symbols that comprises resource elements. The method also includes descrambling the resource elements of the symbols one-by-one using descrambling bits generated by at least one linear feedback shift register (LFSR). After each symbol is descrambled, a state of the at least one LFSR is stored as a stored state. The method also comprises restoring the stored state to the at least one LFSR before a next symbol is descrambled so that generation of the descrambling bits continues from symbol to symbol. The method also comprises forwarding the descrambled symbols to a downstream combining function.
Methods and apparatus are disclosed for searching and tracking intercell interference in communication networks. In an exemplary embodiment, a method is provided that includes operations of receiving a noise covariance matrix and generating a beam sub-space from the noise covariance matrix. The beam sub-space includes one or more sub-space beams. The method also includes determining a set of selected sub-space beams having energy levels that exceed a threshold, calculating an Eigenvector decomposition for the set of selected sub-space beams to identify an Eigenspace of interference energy, and tracking the Eigenspace over time.
Methods and apparatus for channel detection in an uplink shared control channel. In an exemplary embodiment, a method includes generating soft-combined bit streams for an acknowledgement (ACK) indicator, rank indicator (RI), and channel quality indicator (CQI) received in an uplink shared channel. The method also includes decoding the ACK, RI, and CQI soft-combined bit streams to generate Top-M decoded bit streams for each indicator, and generating Top-Q symbols for each indicator from the Top-M decoded bit streams for each indicator. The method also includes calculating metrics from the Top-Q symbols and uplink control information (UCI) symbols extracted from the uplink shared channel, combining the metrics to form a search space, and searching the search space to determine transmitted ACK, RI, and CQI bits.
A tunable laser for generating and outputting wavelength-tuned light using only a single gain chip includes a reflective semiconductor optical amplifier (RSOA) having a front-end configured as an output port for outputting the wavelength-tuned light with an amplified light intensity relative to light received at a back-end of the RSOA. A wavelength tuner is optically coupled to the back-end of the RSOA and includes a plurality of ring resonators having respective Q-factors above 2000 and below 4000.
Hybrid automatic repeat request (HARQ) parameters for transmission of respective HARQ data units are determined. Determining HARQ parameters includes determining initial HARQ parameters, including an initial number of orthogonal frequency division multiplexing (OFDM) symbols that will be occupied by the HARQ data unit and an initial pre-coding padding factor corresponding to a boundary within a last OFDM symbol. Based at least in part on the initial pre-coding padding factor, it is determined whether the HARQ data unit will be misaligned with both a beginning of a first OFDM symbol occupied by the HARQ data unit and an end of a last OFDM symbol occupied by the HARQ data unit. When it is determined that the HARQ data unit will be misaligned, the initial pre-coding padding factor is adjusted to account for a reduced data tone OFDM symbol segment to be occupied by the HARQ data unit.
A tuning structure to mitigate a capacitive discontinuity in an integrated circuit (IC) package includes an electrical conductor having a first end, a second end, and a conductor body between the first end and the second end. The first end is electrically coupled to a signal via, and the second end electrically coupled to an IC package core via cap. The electrical conductor is disposed substantially coplanar with the core via cap, and the conductor body is disposed along an outer perimeter of the core via cap. The second end is coupled to the via cap at a contact location. The contact location is determined based on a measurement of a performance metric associated with the transmission path through the IC package core, the core via cap, the electrical conductor, and the signal via.
A system includes a power profile engine, a power measurement engine, and a power throttling signal generator. The power profile engine receives a desired power profile, e.g., a first profile current average associated with a first time duration and a second profile current average associated with a second time duration. The power measurement engine measures current being drawn and generates a first running average for the measured currents for the first time duration and generates a second running average for the measured currents for the second time duration. The power throttling signal generator generates a first power throttling signal to throttle power in response to the first running average for the measured currents being greater than the first profile current average and generates a second power throttling signal to throttle power in response to the second running average for the measured currents being greater than the second profile current average.
Systems and methods of multi-chip processing with low latency and congestion. In a multi-chip processing system, each chip includes a plurality of clusters arranged in a mesh design. A respective interconnect controller is disposed at the end of each column. The column is linked to a corresponding remote column in the other chip. A share cache controller in the column is paired with a corresponding cache controller in the remote column, the pair of cache controllers are configured to control data caching for a same set of main memory locations. Communications between cross-chip cache controllers are performed within linked columns of clusters via the column-specific inter-chip interconnect controllers.
A network switch includes a plurality of Ethernet ports having their respective Physical (PHY) Layers interconnected via a common interface local to the network switch. The common interface passes local information among respective PHY layers of the Ethernet ports. One or more receivers receive for a first Ethernet port, over the common interface, information indicative of alien cross talk affecting at least one second Ethernet port of the network switch. A transmission attribute controller adjusts, based on the received information indicative of alien cross talk affecting the at least one second Ethernet port of the network switch, a first data rate and/or a first transmit power level to a second data rate and/or a second transmit power level for transmitting data to a remote network device. A first transmitter transmits data via the first Ethernet port according to the second data rate and/or the second transmit power level.
A communication device generates a first packet and a second packet. The first packet includes a first physical layer (PHY) preamble having: a first legacy signal field (L-SIG) having first duration information that indicates a first duration of the first packet; and first non-legacy signal field information having first modulation information that indicates a first modulation used in the first packet. The second packet includes a second PHY preamble having: a second L-SIG having second duration information that indicates a second duration of the second packet, wherein the second duration is different than the first duration; and second non-legacy signal field information having second modulation information that indicates a second modulation used in the second packet, wherein the second modulation is different than the first modulation. The communication device simultaneously transmits the first packet in a first frequency segment and the second packet in a second frequency segment.
A system and corresponding method queue work within a virtualized scheduler based on in-unit accounting (IUA) of in-unit entries (IUEs). The system comprises an IUA resource and arbiter. The IUA resource stores, in association with an IUA identifier, an IUA count and threshold. The IUA count represents a global count of work-queue entries (WQEs) that are associated with the IUA identifier and occupy respective IUEs of an IUE resource. The IUA threshold limits the global count. The arbiter retrieves the IUA count and threshold from the IUA resource based on the IUA identifier and controls, as a function of the IUA count and threshold, whether a given WQE from a given scheduling group, assigned to the IUA identifier, is moved into the IUE resource to be queued for scheduling. The IUA count and threshold prevent group(s) assigned to the IUA identifier from using more than an allocated amount of IUEs.
An apparatus for controlling a sensor over a network includes a transceiver and a processor. The transceiver is configured to communicate over a network. The processor is configured to receive or generate control data for controlling a sensor connected to the network, to generate a packet including (i) the control data and (ii) a trigger timestamp indicative of a future time at which the control data is to be provided to the sensor, and to transmit the packet using the transceiver over the network.
An apparatus for controlling a sensor over a network includes a transceiver and a processor. The transceiver is configured to communicate over the network. The processor is configured to receive or generate control data for controlling a sensor, the sensor being connected to the network by a peer device. The processor is further configured to wake-up a link with the peer device in accordance with a schedule, and, during a time period in the schedule in which the link with the peer device is awake, to send to the peer device a packet comprising the control data.
Systems and corresponding methods employ an object-oriented (OO) memory (OOM) to effect inter-hardware-client (IHC) communication among a plurality of hardware clients included in same. A system comprises a centralized OOM and the plurality of hardware clients communicate, directly, to the centralized OOM device via OO message transactions. The centralized OOM device effects IHC communication among the plurality of hardware clients based on the OO message transactions. Another system comprises a plurality of OO memories (OOMs) capable of inter-object-oriented-memory-device communication. A hardware client communicates, directly, to a respective OOM device via OO message transactions. The inter-object-oriented-memory-device communication effects IHC communication among the plurality of hardware clients based on the OO message transactions.
G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
G06F 5/06 - Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising
G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
G06F 9/448 - Execution paradigms, e.g. implementations of programming paradigms
An optical communication system includes a co-packaged optical module and a heatsink mounted to the co-packaged optical module. The co-packaged optical module includes a processor disposed on a substrate and a plurality of light engines disposed at different locations around the processor on the substrate. The processor and the light engines generating different amounts of heat during operation. The heatsink includes a plurality of heat pipes non-uniformly distributed throughout the heatsink to remove the different amounts of heat generated at a location of the processor and respective locations of the different ones of the light engines.
H05K 7/20 - Modifications to facilitate cooling, ventilating, or heating
G02B 6/42 - Coupling light guides with opto-electronic elements
H01L 23/427 - Cooling by change of state, e.g. use of heat pipes
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different main groups of groups , or in a single subclass of , , e.g. forming hybrid circuits
H04Q 11/00 - Selecting arrangements for multiplex systems
G02B 6/43 - Arrangements comprising a plurality of opto-electronic elements and associated optical interconnections
47.
Method and apparatus for authorizing unlocking of a device
A programmable integrated circuit device includes a programmable core, a boot device configured to boot up the programmable core, and a one-time programmable memory module controlling life cycle states of the programmable integrated circuit device, including (i) an operational state during which programming resources of the programmable device are locked, and (ii) an inspection state in which the programming resources of the programmable device are accessible. The one-time programmable memory module is configured to allow unidirectional advance from the operational state to the inspection state, when authorized by a lock control circuit responsive to control signals from the boot device to authorize the unidirectional advance from the operational state to the inspection state. Authorization of the unidirectional advance may be limited to a time interval during a boot cycle of the programmable device. The unidirectional advance may be based on receipt of an authenticated request from a requester.
H04L 29/06 - Communication control; Communication processing characterised by a protocol
G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
Embodiments of the present invention relate to a centralized network analytic device, the centralized network analytic device efficiently uses on-chip memory to flexibly perform counting, traffic rate monitoring and flow sampling. The device includes a pool of memory that is shared by all cores and packet processing stages of each core. The counting, the monitoring and the sampling are all defined through software allowing for greater flexibility and efficient analytics in the device. In some embodiments, the device is a network switch.
Embodiments relate to a die package featuring a sputtered metal shield to reduce Electro-Magnetic Interference (EMI). According to a particular embodiment, a die featuring a top surface exposed by surrounding Molded Underfill (MUF) material, is subjected to metal sputtering. The resulting sputtered metal shield is in direct physical and thermal contact with the die, and is in electrical contact with a substrate supporting the die (e.g., to provide shield grounding). Specific embodiments may be particularly suited to reducing the EMI of a package containing an electro-optic die, to between 3-15 dB. The conformal nature and small thickness of the sputtered metal shield desirably conserves space and reduces package footprint. Direct physical contact between the shield and the die surface exposed by the MUF, enhances thermal communication (e.g., reducing junction temperature). According to certain embodiments, the sputtered metal shield comprises a stainless steel liner, copper, and a stainless steel coating.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
50.
SYSTEM AND METHODS FOR TAG-BASED SYNCHRONIZATION OF TASKS FOR MACHINE LEARNING OPERATIONS
A new approach for supporting tag-based synchronization among different tasks of a machine learning (ML) operation. When a first task tagged with a set tag indicating that one or more subsequent tasks need to be synchronized with it is received at an instruction streaming engine, the engine saves the set tag in a tag table and transmits instructions of the first task to a set of processing tiles for execution. When a second task having an instruction sync tag indicating that it needs to be synchronized with one or more prior tasks is received at the engine, the engine matches the instruction sync tag with the set tags in the tag table to identify prior tasks that the second task depends on. The engine holds instructions of the second task until these matching prior tasks have been completed and then releases the instructions to the processing tiles for execution.
G06F 9/38 - Concurrent instruction execution, e.g. pipeline, look ahead
G06F 9/52 - Program synchronisation; Mutual exclusion, e.g. by means of semaphores
G06F 9/48 - Program initiating; Program switching, e.g. by interrupt
G06F 15/80 - Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
51.
Silicon optical modulator, method for making the same
A silicon optical modulator includes a silicon-on-insulator substrate and a first waveguide and a second waveguide arranged parallel to each other in the silicon-on-insulator substrate. The first waveguide includes a first PN junction. The second waveguide includes a second PN junction. At least one of the first PN junction and the second PN junction is disposed at an interface between a P type doped region and a N type doped region. The interface has an irregular shape that is not perpendicular to a plane in which the silicon-on-insulator substrate lies.
G02F 1/225 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour by interference in an optical waveguide structure
G02F 1/21 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour by interference
G02B 6/134 - Integrated optical circuits characterised by the manufacturing method by substitution by dopant atoms
52.
Reducing leakage power in low-power mode of an integrated circuit device
An integrated circuit device includes a plurality of cells or modules. Each respective one of the cells or modules consumes leakage power, and the amount of leakage power consumed by a respective one of the cells or modules varies depending on states of its inputs. Scan-chain circuitry is configured to propagate through the integrated circuit device, on entry of the integrated circuit device to a low-power mode, a scan-chain pattern created in advance, to apply, to each respective cell or module in the low-power mode, a set of inputs that results in a respective low-power state with reduced leakage power. Creating the scan chain pattern includes identifying respective ones of the cells or modules as having the highest leakage power consumption, and a respective combination of inputs to place each of those the cells or modules in a respective low-power state.
G06F 1/00 - ELECTRIC DIGITAL DATA PROCESSING - Details not covered by groups and
G06F 1/3296 - Power saving characterised by the action undertaken by lowering the supply or operating voltage
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
09 - Scientific and electric apparatus and instruments
Goods & Services
Semiconductors, integrated circuits, computer networking switches, and computer networking interface cards; all of the foregoing incorporating telemetry that delivers visibility and analytics for data traffic at the network and switch level; semiconductors; integrated circuits; computer networking switches; computer networking interface cards; downloadable application programming interface (API) software; downloadable software development kits (SDK); downloadable telemetry and data analytics software; downloadable computer software for providing real-time visibility and network analytics to troubleshoot and resolve network issues.
54.
STIFFENER RING FOR PACKAGES WITH MICRO-CABLE/OPTICAL CONNECTORS
A semiconductor package includes a package substrate, a semiconductor chip disposed on the package substrate, and a stiffener disposed on the package substrate. The stiffener includes an inner portion configured to surround the semiconductor chip, the inner portion defining a space on the package substrate external to the inner portion and located between the inner portion and outer edges of the package substrate, and a plurality of leg portions extending outwardly from the inner portion toward one or more of the outer edges of the package substrate and corners of the package substrate.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
55.
Midamble Format for Packets in a Vehicular Communication Network
In a vehicular communication network, a communication device generates a physical layer (PHY) preamble of a PHY protocol data unit (PPDU) for transmission in the vehicular communication network. The communication device generates a plurality of PHY data segments of the PPDU, and one or more PHY midambles, each PHY midamble to be transmitted between a respective pair of adjacent PHY data segments, and each PHY midamble including one or more training signal fields. Generating the one or more PHY midambles includes, when the PPDU is to be transmitted according to an extended range (ER) mode, generating each training signal field to include i) a first portion based on a very high throughput long training field (VHT-LTF) defined by the IEEE 802.11ac Standard and ii) a second portion based on the VHT-LTF defined by the IEEE 802.11ac Standard; and transmitting, by the communication device, the PPDU in the vehicular communication network.
A method and structure for probabilistic shaping and compensation techniques in coherent optical receivers. According to an example, the present invention provides a method and structure for an implementation of distribution matcher encoders and decoders for probabilistic shaping applications. The techniques involved avoid the traditional implementations based on arithmetic coding, which requires intensive multiplication functions. Furthermore, these probabilistic shaping techniques can be used in combination with LDPC codes through reverse concatenation techniques.
H04B 10/00 - Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
A multi-lane integrated circuit transceiver device includes first and second integrated circuit dies having respective first and second pluralities of transmit block/receive block pairs. Each respective transmit block and each respective receive block in the first plurality of block pairs on the first die and the second plurality of block pairs on the second die includes respective digital clock generation circuitry. The device further includes digital clock distribution circuitry to distribute a digital clock signal output by one respective receive block, in one of the first and second pluralities of block pairs, to the transmit blocks in both of the pluralities of block pairs, for use as a baseline clock by the respective digital clock generation circuitry in each of the transmit blocks in both of the pluralities of block pairs. Where each plurality includes N block pairs, the two dies together form a single 2N-lane device.
G06F 13/42 - Bus transfer protocol, e.g. handshake; Synchronisation
H04B 1/38 - Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
An Ethernet Physical Layer (PHY) device includes a link interface and a transceiver. The link interface connects to a full-duplex wired Ethernet link. The transceiver receives first Ethernet signals carrying first data at a first data rate over toe Ethernet link at a first baud rate, transmits second Ethernet signals carrying second data at a second data rate higher than the first data rate, over the Ethernet link, at a second baud rate that is higher than the first baud rate, resamples a reference signal related to the second Ethernet signals to match the first baud rate, generates from the resampled reference signal, at the first baud rate, an echo cancelation signal indicative of an echo signal originating from the second Ethernet signals and interfering with reception of the first Ethernet signals, and suppresses the echo signal from the first Ethernet signals using the echo cancelation signal.
H04L 5/14 - Two-way operation using the same type of signal, i.e. duplex
H04B 3/23 - Reducing echo effects or singing; Opening or closing transmitting path; Conditioning for transmission in one direction or the other using a replica of transmitted signal in the time domain, e.g. echo cancellers
H04L 7/04 - Speed or phase control by synchronisation signals
59.
PACKET PROCESSING SYSTEM, METHOD AND DEVICE UTILIZING A PORT CLIENT CHAIN
A packet processing system having each of a plurality of hierarchical clients and a packet memory arbiter serially communicatively coupled together via a plurality of primary interfaces thereby forming a unidirectional client chain. This chain is then able to be utilized by all of the hierarchical clients to write the packet data to or read the packet data from the packet memory.
A memory request, including an address, is accessed. The memory request also specifies a type of an operation (e.g., a read or write) associated with an instance (e.g., a block) of data. A group of caches is selected using a bit or bits in the address. A first hash of the address is performed to select a cache in the group. A second hash of the address is performed to select a set of cache lines in the cache. Unless the operation results in a cache miss, the memory request is processed at the selected cache. When there is a cache miss, a third hash of the address is performed to select a memory controller, and a fourth hash of the address is performed to select a bank group and a bank in memory.
A packet processing system having each of a plurality of hierarchical clients and a packet memory arbiter serially communicatively coupled together via a plurality of primary interfaces thereby forming a unidirectional client chain. This chain is then able to be utilized by all of the hierarchical clients to write the packet data to or read the packet data from the packet memory.
A packet processing system having each of a plurality of hierarchical clients and a packet memory arbiter serially communicatively coupled together via a plurality of primary interfaces thereby forming a unidirectional client chain. This chain is then able to be utilized by all of the hierarchical clients to write the packet data to or read the packet data from the packet memory.
A packet processing system having each of a plurality of hierarchical clients and a packet memory arbiter serially communicatively coupled together via a plurality of primary interfaces thereby forming a unidirectional client chain. This chain is then able to be utilized by all of the hierarchical clients to write the packet data to or read the packet data from the packet memory.
Systems and methods for selecting an optimal error recovery procedure for correcting a read error in a solid-state drive are provided. A machine learning model is trained to forecast which error recovery procedure of a plurality of error recovery procedures is most likely to achieve a predetermined goal given a state of a solid-state drive. The predetermined goal is based on at least one of a read latency and a failure rate of the solid-state drive. A current state of the solid-state drive is determined. An error recovery procedure is selected from among the plurality of error recovery procedures by inputting the current state of the solid-state drive into the trained machine learning model, thereby triggering the trained machine learning model to output the selected error recovery procedure. The selected error recovery procedure is executed to recover data from the solid-state drive.
A bandwidth-limited client station is configured to operate with a maximum bandwidth that is less than a full bandwidth of a communication channel of a wireless local area network. The bandwidth-limited client station negotiates a target wake time (TWT) period with an access point, including negotiating a particular non-primary component channel among one or more non-primary component channels in which the bandwidth-limited client station is expected to operate during the TWT period. The bandwidth-limited client station receives a first legacy packet from the access point in the particular non-primary component channel, the first legacy packet including a beacon frame. The bandwidth-limited client station also receives a trigger frame from the access point in a second legacy packet in the particular non-primary component channel during the TWT period. The trigger frame is configured to prompt the bandwidth-limited client station to transmit an uplink transmission in the particular non-primary component channel.
A system for performing a failure assessment of an IC may comprise a hardware subsystem and a control subsystem to control operations performed by the hardware subsystem. The hardware system may change a duration of cycles of a clocking signal on the IC, and stop the clocking signal at a selected clock cycle. The operations may comprise changing the duration of selected clock cycles across a block of clock cycles, and performing a binary search across the block of clock cycles, such that the selected clock cycles are temporally placed at selected different locations within the block of clock cycles. At each iteration of the binary search, the system determines when a failure occurs. When the binary search indicates a single clock cycle causing a failure, the system stops clocking transitions at the single clock cycle, and the system extracts data from one or more circuit components of the IC.
In a system with multiple host computers and one or more single-port non-volatile memory devices, a non-volatile memory switch receives memory transaction messages from different root complexes corresponding to the multiple host computers. Each of at least some of the memory transaction messages includes a host identifier that identifies a root complex from which the memory transaction was received. The non-volatile memory switch generates modified memory transaction messages at least by changing host identifiers within memory transaction messages to a common value indicative of a single root complex to present to the one or more single-port non-volatile memory devices the different root complexes as the single root complex. The non-volatile memory switch maintains associations of memory transaction messages with corresponding ones of the different root complexes, and sends the modified memory transaction messages to the one or more single-port non-volatile memory devices.
A communication device performs a backoff procedure for a duration of time to determine whether a first sub-channel of a communication channel and a second sub-channel of the communication channel are available for transmission by the communication device. The first sub-channel is designated as a primary channel and the second sub-channel is designated as a secondary channel. Performing the backoff procedure includes using a single backoff counter, and starting and stopping the backoff counter based on sensing the first sub-channel and sensing the second sub-channel.
An input signal is sampled at a current sampling phase by a sampler device of a receiver device. The sampled input signal is equalized by an adaptive equalizer of the receiver device. One or more parameters of the adaptive equalizer are adapted, based on the equalized input signal, under one or more adaptation constraints. Phase gradient information indicative of an offset of the current sampling phase from an optimal sampling phase is determined, and the one or more adaptation constraints of the adaptive equalizer are updated based on the phase gradient information to move the current sampling phase towards the optimal sampling phase.
H04L 7/00 - Arrangements for synchronising receiver with transmitter
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
70.
PADDING AND BACKOFF OPERATIONS WHEN TRANSMITTING VIA MULTIPLE FREQUENCY SEGMENTS IN A WLAN
A communication device determines that simultaneous transmission/reception via multiple frequency segments in a WLAN is not permitted, and transmits a first packet in a first frequency segment and a second packet in a second frequency segment. The communication device determines that an end of the first packet does not align with an end of the second packet and that the first packet and/or the second packet prompts transmission of a respective response packet a defined time period after transmission of the corresponding one of the first packet and the second packet. In response to having determined that simultaneous transmission/reception is not permitted and that the first packet and/or the second packet prompts transmission of the respective response packet, the communication device pads the first packet and/or the second packet so that an end of transmission of the first packet is aligned with an end of transmission of the second packet.
An input signal is sampled at a current sampling phase by a sampler device of a receiver device. The sampled input signal is equalized by an adaptive equalizer of the receiver device. One or more parameters of the adaptive equalizer are adapted, based on the equalized input signal, under one or more adaptation constraints. Phase gradient information indicative of an offset of the current sampling phase from an optimal sampling phase is determined, and the one or more adaptation constraints of the adaptive equalizer are updated based on the phase gradient information to move the current sampling phase towards the optimal sampling phase
Described herein are systems and methods for cache replacement mechanisms for speculative execution. For example, some systems include, a buffer comprising entries that are each configured to store a cache line of data and a tag that includes an indication of a status of the cache line stored in the entry, in an integrated circuit that is configured to: responsive to a cache miss caused by a load instruction that is speculatively executed by a processor pipeline, load a cache line of data corresponding to the cache miss into a first entry of the buffer and update the tag of the first entry to indicate the status is speculative; responsive to the load instruction being retired by the processor pipeline, update the tag to indicate the status is validated; and, responsive to the load instruction being flushed from the processor pipeline, update the tag to indicate the status is cancelled.
G06F 12/08 - Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
G06F 12/0862 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
G06F 12/121 - Replacement control using replacement algorithms
73.
Method and apparatus for contemporary test time reduction for JTAG
A method of loading a data string into a Joint Test Action Group (JTAG) shift register is provided. The method includes determining whether the last bit of the data string is equal to one or zero. In response to determining that the last bit is equal to one, the method includes simultaneously setting each flip-flop of the shift register to one, identifying first data string loading bits by removing, from the data string, the last bit and any other bits in a continuous sequence of bits, including the last bit, that are each equal to one, and sequentially loading the identified first data string loading bits into the shift register. A testing apparatus for performing the method and an enhanced JTAG interface are also provided. The method, testing apparatus, and enchanced JTAG interface may reduce the number of clock cycles required to load the shift register.
A first communication device generates a first packet and transmits the first packet via a first wireless local area network (WLAN) communication channel having a first radio frequency (RF) bandwidth. The first communication device generates a second packet and, after transmitting the first packet, transmits the second packet via the first WLAN communication channel. The first communication device receives a transmission from one or more second communication devices that overlaps in time with transmission of the second packet. The transmission from the one or more second communication devices is received via a second WLAN communication channel having a second RF bandwidth.
H04L 1/1607 - Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals - Details of the supervisory signal
H04W 72/0453 - Resources in frequency domain, e.g. a carrier in FDMA
H04W 72/1263 - Mapping of traffic onto schedule, e.g. scheduled allocation or multiplexing of flows
An access point (AP) generates a multi-user request to send (MU-RTS) frame for protecting a channel bandwidth during a communication exchange, and transmits the MU-RTS frame in multiple duplicate first packets in respective communication subchannels that span the channel bandwidth. Each first packet has a first packet format that conforms to a legacy protocol. The AP receives multiple clear-to-send (CTS) frames from multiple client stations via respective communication subchannels that span the channel bandwidth. The AP generates a trigger frame configured to prompt the multiple client stations to transmit respective data to the AP. After transmitting the multiple first packets, the AP transmits the trigger frame in one or more second packets that span the channel bandwidth and that conform to a second packet format defined by a non-legacy protocol. The AP receives, from the multiple client stations, data frames that are responsive to the trigger frame.
A first communication device is configured to process packets that conform to a first physical layer (PHY) protocol for wireless vehicular communications and packets that conform to a second PHY protocol for wireless vehicular communications. The first communication device determines that one or more second communication devices neighboring the first communication device are not capable of processing packets that conform to the second PHY protocol. The first communication device transmits a first packet to a third communication device that is configured to process packets that conform to the first PHY protocol and packets that conform to the second PHY protocol. The first packet indicates that the one or more second communication devices neighboring the first communication device are not capable of processing packets that conform to the second PHY protocol to inform the third communication device of the one or more second communication devices.
A first communication device generates a trigger frame for use in a multi-user ranging measurement exchange session with a plurality of second communication devices. The trigger frame includes trigger type information for indicating a type of frame exchange to which the trigger frame corresponds, and the first communication device generates the trigger frame to include trigger type information that indicates the trigger frame is for prompting an uplink (UL) multi-user (MU) null data packet (NDP) transmission as part of the MU ranging measurement exchange session. The first communication device transmits the trigger frame as part of the ranging measurement exchange session with the plurality of second communication devices, and receives an UL MU NDP transmission from the plurality of second communication devices as part of the ranging measurement exchange session, the UL MU NDP transmission being responsive to the trigger frame.
A communication device selects a frequency bandwidth via which a physical layer (PHY) protocol data unit (PPDU) will be transmitted in a vehicular communication network, and generates, the PPDU i) according to a downclocking ratio of 1/2, and ii) based on an orthogonal frequency division multiplexing (OFDM) numerology defined by an IEEE 802.11ac Standard. In response to the selected frequency bandwidth being 10 MHz, the PPDU is generated according to the downclocking ratio of 1/2 and based on the OFDM numerology defined by the IEEE 802.11ac Standard for 20 MHz PPDUs. In response to the selected frequency bandwidth being 20 MHz, the PPDU is generated according to the downclocking ratio of 1/2 and based on the OFDM numerology defined by the IEEE 802.11ac Standard for 40 MHz PPDUs.
A system and corresponding method unwind instructions in an out-of-order (OoO) processor. The system comprises a mapper. In response to a restart event causing at least one instruction to be unwound, the mapper restores a present integer mapper state and present floating-point (FP) mapper state, used for mapping instructions, to a former integer mapper state and former FP mapper state, respectively. The mapper stores integer snapshots and FP snapshots of the present integer and FP mapper state, respectively, to expedite restoration to the former integer and FP mapper state, respectively. Access to the FP snapshots is blocked, intermittently, as a function of at least one FP present indicator used by the mapper to record presence of FP registers used as destinations in the instructions. Blocking the access, intermittently, improves power efficiency of the OoO processor.
Systems and methods are described for dynamically updating a duration of link training time for a first stage of link training implemented to set up a first characteristic of a link connection between a physical layer transceiver (PHY) and a link partner. A first stage of link training preconfigured to last for a first duration of time is initiated and a metric of link quality that measures a link connection quality is initiated. Based on the determined metric of link quality, updating the first duration of time for the first stage of link training.
A physical layer (PHY) processor of a network interface device operates in a low power state in which a transceiver of the PHY processor device periodically does not transmit on a communication link during a plurality of quiet time slots. In response to determining a low signal-to-noise ratio (SNR) condition associated with the communication link, the PHY processor transitions to a link recovery state in which the transceiver continuously transmits idle symbols. In response to determining that the low SNR condition has ended, the PHY processor transitions from the link recovery state to the low power state.
Methods and apparatus for preamble detection in a communication network are disclosed. In an exemplary embodiment, a method includes retrieving parameters from a parameter database, filling a buffer of preamble data received in an uplink transmission from user equipment, and frequency shifting the buffer of preamble data based on one or more first parameters to generate frequency shifted data. The method also includes oversampling the frequency shifted data to generates oversampled data, downsampling the over sampled data based on one or more second parameters to generate preamble samples, and updating the parameter database with updated values for the one or more first and second parameters. The method also includes repeating all the operations until a selected amount of preamble samples is obtained.
A first access point (AP), which is associated with one or more first client stations, generates an announcement frame that announces a coordinated multi-user (MU) transmission involving multiple APs including the first AP and one or more second APs. Each of the second APs is associated with a respective one or more second client stations. The announcement frame is generated to indicate one or more respective sets of communication parameters to be used by the one or more second APs for communicating with the respective one or more second client stations during the coordinated MU transmission. The first AP transmits the announcement frame to the one or more second APs to initiate the coordinated MU transmission, and participates in the coordinated MU transmission while the one or more second APs also participate in the coordinated MU transmission.
H04B 7/024 - Co-operative use of antennas at several sites, e.g. in co-ordinated multipoint or co-operative multiple-input multiple-output [MIMO] systems
A switch device is configured to communicate with a plurality of hosts and a solid state drive (SSD). The plurality of hosts includes a first host and a second host. The switch device receives a first memory access command from the SSD, the first memory access command including an indication of the first host to indicate the first memory access command is intended for the first host. The switch device uses the indication of the first host in the first memory access command to route the first memory access command to the first host. The switch device removes the indication of the first host from the first memory access command prior to sending the first memory access command to the first host via a peripheral computer interface express (PCIe) interface of the switch device.
An Integrated Circuit (IC) includes electronic circuitry, an electronic fuse (eFuse) and a protection circuit. The eFuse is configured to be selectably programmed to a logical state. The electronic circuitry is configured to read the eFuse and to operate in accordance with the logical state read from the eFuse. The eFuse has a first range of operational voltages, and the electronic circuitry has a second range of operational voltages that is broader than the first range of operational voltages. The protection circuit is configured to prevent the electronic circuitry from misreading the logical state of the eFuse due to a voltage supply to the IC falling within the second operational voltage range but outside the first operational voltage range.
H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
A first access point (AP) generates and transmits a first physical layer (PHY) data unit for initiating a joint channel sounding procedure between a group of APs, including the first AP and one or more second APs, and one or more client stations. The first PHY data unit is generated to indicate that the first PHY data unit is of joint channel sounding type. The first AP generates and transmits a second PHY data unit for initiating synchronous data transmissions by the group of APs. The second PHY data unit is generated to indicate that the second PHY data unit is of a joint data transmission type. The synchronous data transmissions initiated by the second PHY data unit are steered using beamforming parameters determined based on the joint sounding procedure. A synchronous data transmission by a second AP is adjusted based on the relative timing offset.
A system includes a test access port (TAP) configured to provide internal joint test action group (IJTAG) access to one or more test data registry (TDR). The system further includes a plurality of hierarchical electronic components, wherein each hierarchical electronic component includes a de-asserted segment inserted bit (D-SIB) register, an asserted segment inserted bit (A-SIB) register, and a TDR associated with the D-SIB register. Each D-SIB register is configured to prevent access to its associated TDR when a reset signal is asserted and each A-SIB register is configured to provide access to its subsequent A-SIB register or D-SIB register coupled thereto when the reset signal is asserted.
A system includes a power profile engine, a power measurement engine, and a power throttling signal generator. The power profile engine receives a desired power profile, e.g., a first profile current average associated with a first time duration and a second profile current average associated with a second time duration. The power measurement engine measures current being drawn and generates a first running average for the measured currents for the first time duration and generates a second running average for the measured currents for the second time duration. The power throttling signal generator generates a first power throttling signal to throttle power in response to the first running average for the measured currents being greater than the first profile current average and generates a second power throttling signal to throttle power in response to the second running average for the measured currents being greater than the second profile current average.
A physical layer transceiver for a node in a wireline communication system includes receiver circuitry for receiving communications from a link partner on a first link path, transmitter circuitry for transmitting communications to the link partner on a second link path, and an energy-efficient Ethernet (EEE) controller for reducing power consumption on the first or second link path, when activity on that link path is reduced. In a low-power mode, there are periodic refresh intervals of a first duration, during which signals are received or transmitted, and, between the refresh intervals, quiet intervals of a second, longer, duration, during which transmission and reception of signals are avoided. The EEE controller detects a change in an environmental condition affecting that link path, and upon detection of that change, adjusts a parameter of the low-power mode on at least one of the first and second link paths.
Methods and apparatus for decoding received uplink transmissions using log-likelihood ratio optimization. In an embodiment, a method includes soft-demapping resource elements based on soft-demapping parameters as part of a process to generate log-likelihood ratios (LLR) values, decoding the LLRs to generate decoded data, and identifying a target performance value. The method also includes determining a performance metric from the decoded data, and performing a machine learning algorithm that dynamically adjusts the soft-demapping parameters to move the performance metric toward the target performance value.
An automotive gateway includes one or more interfaces and one or more processors. The one or more interfaces are configured to communicate with electronic subsystems of a vehicle. The one or more processors and configured to host one or more guest applications, to associate both (i) the hosted guest applications and (ii) a first subset of the electronic subsystems of the vehicle with a non-secured domain, to associate a second subset of the electronic subsystems of the vehicle with a secured domain, and to control communication traffic between the secured domain and the non-secured domain of the vehicle in accordance with a security policy.
B60R 16/023 - Electric or fluid circuits specially adapted for vehicles and not otherwise provided for; Arrangement of elements of electric or fluid circuits specially adapted for vehicles and not otherwise provided for electric for transmission of signals between vehicle parts or subsystems
B60R 25/30 - Detection related to theft or to other events relevant to anti-theft systems
G06F 9/455 - Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
H04L 12/66 - Arrangements for connecting between networks having differing types of switching systems, e.g. gateways
H04L 67/12 - Protocols specially adapted for proprietary or special-purpose networking environments, e.g. medical networks, sensor networks, networks in vehicles or remote metering networks
92.
Systems and methods for providing a compatible backplane operation mechanism for 2.5-gigabit high-speed Ethernet
Embodiments described herein provide a method for providing a compatible backplane operation mechanism for 2.5-gigabit Ethernet. A first input of data including a first sequence-ordered set in compliance with a first interface protocol is received from a medium access control (MAC) layer. The first input of data is encoded into four outputs of encoded data including a second sequence-ordered set in compliance with a second interface protocol. The first sequence-ordered set in a first form of a sequence code followed by three bytes of data is mapped to the second sequence-ordered set in a second form of consecutive units of the sequence code followed by an encoded data byte. The four parallel outputs of encoded data are serialized into a serial output. The serial output to a linking partner is transmitted on a physical layer of an Ethernet link at a speed specified in the second interface protocol.
A CPU having a plurality of cores is configured by determining a number of cores required for operation of the CPU. Each respective core is tested, and a performance parameter of the respective core is determined based on the test. The respective core is then classified for suitability to perform a set of functions based on the performance parameter of the respective core. If at least the number of cores required for operation of the CPU are classified for suitability to perform the set of functions, a subset of suitable cores is defined, the subset including cores that are classified for the set of functions and at least the number of cores required for operation of the CPU. The required number of cores from among the subset of cores are then enabled.
An Ethernet physical-layer (PHY) device includes an analog front-end and one or more processors. The analog front-end is configured to interface with an Ethernet link that is coupled to a peer Ethernet PHY device. The one or more processors are configured to receive a firmware image from the peer Ethernet PHY device over the Ethernet link, and to boot the Ethernet PHY device and establish Ethernet communication with the peer Ethernet PHY device in accordance with the received firmware image.
The present disclosure describes apparatuses and methods for machine learning-enabled (ML-enabled) management of storage media access. In some aspects, an ML-enabled storage controller obtains features of available blocks of storage media of a storage media system. The controller can receive, from a host system, a request to write data and determine features of the data to be written to the storage media. The controller provides the respective features of the available blocks and the data to a neural network and receives, from the neural network, a selected block of the available blocks for writing of the data. The selected block may include an ML-optimized selection from the available blocks based on the features of both the available blocks and the data. The controller then writes the data of the request to the ML-selected block of storage media of the storage media system, which may improve storage media performance.
Methods and apparatus for adaptive power profiling in a baseband processing system. In an exemplary embodiment, an apparatus includes one or more processing engines. Each processing engine performs at least one data processing function. The apparatus also includes an adaptive power profile (APP) and a job manager that receives job requests for data processing. The job manager allocates the data processing associated with the job requests to the processing engines based on the adaptive power profile. The adaptive power profile identifies a first group of the processing engines to perform the data processing associated with the job requests, and identifies remaining processing engines to be set to a low power mode.
A circuit and corresponding method control cycle time of an output clock used to clock at least one other circuit. The circuit comprises an agile ring oscillator (ARO) and ARO controller. The ARO includes at least one instance of a first ring oscillator (RO) and second RO that generate high and low phases, respectively, of cycles of the output clock. The ARO controller controls durations of the high and low phases, independently, via first and second control words output to the ARO, respectively. In a present cycle of the output clock, the ARO controller effects a change to the high or low phase, or a combination thereof, in a next cycle of the output clock by updating the first or second control word, or a combination thereof, based on an indication of expected usage of the at least one other circuit in the next cycle. The change improves a performance-to-power ratio of the at least one other circuit.
H03L 7/16 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
H03L 5/00 - Automatic control of voltage, current, or power
H03L 7/099 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
H03K 5/13 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
The present disclosure describes apparatuses and methods for machine learning-enabled (ML-enabled) management of storage media access. In some aspects, an ML-enabled storage controller obtains features of available blocks of storage media of a storage media system. The controller can receive, from a host system, a request to write data and determine features of the data to be written to the storage media. The controller provides the respective features of the available blocks and the data to a neural network and receives, from the neural network, a selected block of the available blocks for writing of the data. The selected block may include an ML-optimized selection from the available blocks based on the features of both the available blocks and the data. The controller then writes the data of the request to the ML-selected block of storage media of the storage media system, which may improve storage media performance.
09 - Scientific and electric apparatus and instruments
Goods & Services
Semiconductors, integrated circuits, computer networking switches, and computer networking interface cards; all of the foregoing incorporating telemetry that delivers visibility and analytics for data traffic at the network and switch level; semiconductors; integrated circuits; computer networking switches; computer networking interface cards; downloadable application programming interface (API) software; downloadable software development kits (SDK); downloadable telemetry and data analytics software; downloadable computer software for providing real-time visibility and network analytics to troubleshoot and resolve network issues
100.
Reduced power consumption by SSD using host memory buffer
A solid state drive (SSD) device includes: non-volatile memory, and volatile memory associated with an SSD device controller. In response to determining that the SSD device is to transition to a power saving mode, information is transferred from the volatile memory to a host memory of a host computer via a communication interface, and the at least some of the volatile memory is transitioned to an OFF state. In response to determining that the SSD device is to transition from the power saving mode to a normal operating mode, the at least some of the volatile memory of the SSD device is transitioned to an ON state in which the at least some of the volatile memory is capable of retaining data, and the information from the host memory is transferred to the volatile memory of the SSD device via the communication interface.
G06F 3/06 - Digital input from, or digital output to, record carriers
G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
G06F 12/0804 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
